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/*
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* Copyright (C) 2011-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <arch.h>
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#include <debug.h>
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#include <drivers/miu.h>
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#include <platform.h>
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#include <platform/memmap.h>
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#include <platform/miu.h>
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#include <platform/soc/chipid.h>
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#include <platform/soc/miu.h>
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#include <platform/soc/pmgr.h>
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#include <platform/clocks.h>
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#include <platform/soc/hwclocks.h>
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static void miu_configure_bridge(const u_int32_t *bridge_settings);
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#define STATIC_BRIDGE_SHIFT (28)
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#define STATIC_BRIDGE_MASK ((1 << STATIC_BRIDGE_SHIFT) - 1)
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#define SB_WIDGETS (0 << STATIC_BRIDGE_SHIFT)
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#define SOCBUSMUX_WIDGETS (1 << STATIC_BRIDGE_SHIFT)
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#define IOBUSMUX_WIDGETS (2 << STATIC_BRIDGE_SHIFT)
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#define SWITCH_FAB_WIDGETS (3 << STATIC_BRIDGE_SHIFT)
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#define CP_WIDGETS (4 << STATIC_BRIDGE_SHIFT)
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#define LIO_WIDGETS (5 << STATIC_BRIDGE_SHIFT)
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#define ANS_WIDGETS (6 << STATIC_BRIDGE_SHIFT)
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static const u_int64_t bridge_registers[] = {
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SB_BASE_ADDR,
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SOC_BUSMUX_BASE_ADDR,
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IOBUSMUX_BASE_ADDR,
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SWTCH_FAB_BASE_ADDR,
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CP_COM_BASE_ADDR,
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LIO_AFC_AIU_BASE_ADDR,
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ANS_AFC_AIU_BASE_ADDR
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};
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#if (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
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static const u_int32_t bridge_settings_static[] = {
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SB_WIDGETS | ASIO_CLK_CTRL, 0x03000102,
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SB_WIDGETS | DYN_CLK_GATING, (0x30 << 16) | (0x1 << 4) | (0x1 << 3) | (0x1 << 0),
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SB_WIDGETS | SIO_ASYNC_FIFO_SB_RD_RATE_LIMIT, 0x0,
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SB_WIDGETS | SIO_ASYNC_FIFO_SB_WR_RATE_LIMIT, 0x0,
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SB_WIDGETS | SIO_ASYNC_FIFO_SB_WGATHER, (0x1 << 8),
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SB_WIDGETS | SIO_DAPASYNC_FIFO_SB_RD_RATE_LIMIT, 0x0,
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SB_WIDGETS | SIO_DAPASYNC_FIFO_SB_WR_RATE_LIMIT, 0x0,
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SB_WIDGETS | SIO_DAPASYNC_FIFO_SB_WGATHER, (0x1 << 8),
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SB_WIDGETS | AIU_SB_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x1 << 12) | 0x4,
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0,0,
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SOCBUSMUX_WIDGETS | DWRRCFG_DISPMUX_BULK, (0x51 << 8) | (0x41 << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL0_CAMERAMUX, (0x40 << 8) | (0xff << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL1_CAMERAMUX, (0x20 << 8) | (0x80 << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL1_MEDIAMUX, (0x60 << 8) | (0x20 << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL2_MEDIAMUX, (0x40 << 8) | (0x10 << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL0_IOMUX, 0x40,
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SOCBUSMUX_WIDGETS | TLIMIT_LVL1_IOMUX, 0x40,
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SOCBUSMUX_WIDGETS | TLIMIT_LVL2_IOMUX, 0x30,
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SOCBUSMUX_WIDGETS | TLIMIT_LVL3_IOMUX, 0x20,
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SOCBUSMUX_WIDGETS | SOCBUSMUX_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x1 << 12) | (0x1 << 11) | (0x1 << 10) | (0x4 << 0),
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0,0,
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IOBUSMUX_WIDGETS | IOBUSMUX_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x1 << 12) | (0x1 << 10) | (0x4 << 0),
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0,0,
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SWITCH_FAB_WIDGETS | SWITCH_FAB_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x1 << 12) | (0x1 << 11) | (0x1 << 10) | (0x4 << 0),
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0,0,
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CP_WIDGETS | CP_DYN_CLK_GATING_CTRL, (0x1 << 4) | (0x1 << 3) | (0x1 << 2) | (0x1 << 1) | (0x1 << 0),
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0,0,
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LIO_WIDGETS | LIO_MEMCACHE_DATASETID_OVERRIDE, (0xC00F000F),
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0,0,
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0,0,
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};
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#endif // (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
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// Alert: The ordering effects the device tree entries under pmgr node's reg dictionary.
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// If you touch this table, and DISPLAY0 index gets changed, please update miu_update_device_tree.
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#if WITH_DEVICETREE && !SUPPORT_FPGA
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static const u_int32_t bridge_settings_dynamic[] = {
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MEDIABUSMUX_REGS_DWRRCFG_JPEG_BULK, (0x28 << 8) | (0x20 << 0),
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MEDIABUSMUX_REGS_DWRRCFG_MSR_BULK, (0x35 << 8) | (0x2a << 0),
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MEDIABUSMUX_REGS_DWRRCFG_VXE_LLT, (0x14 << 8) | (0x10 << 0),
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MEDIABUSMUX_REGS_DWRRCFG_VXE_BULK, (0x67 << 8) | (0x52 << 0),
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MEDIABUSMUX_REGS_DWRRCFG_VXD_LLT, (0x14 << 8) | (0x10 << 0),
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MEDIABUSMUX_REGS_DWRRCFG_VXD_BULK, (0x35 << 8) | (0x2a << 0),
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MEDIABUSMUX_REGS_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x1 << 13) | (0x1 << 12) | (0x1 << 11) | (0x1 << 10) | (0x4 << 0),
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0,0,
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MSR_REGS_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x4 << 0),
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MSR_REGS_AW_TLIMIT, (0x28 << 8) | (0x28 << 0),
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MSR_REGS_MEMCACHE_DATASETID_OVERRIDE, (0xC00F000F),
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0,0,
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AJPEG_REGS_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x4 << 0),
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AJPEG_REGS_MEMCACHE_DATASETID_OVERRIDE, (0xC00F000F),
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0,0,
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VXE_REGS_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x4 << 0),
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VXE_REGS_AR_TLIMIT, (0x10 << 8) | (0x10 << 0),
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VXE_REGS_MEMCACHE_DATASETID_OVERRIDE, (0xC00F000F),
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VXE_REGS_MEMCACHE_HINT_OVERRIDE, (0x1 << 31) | (0x1 << 30) | (0x1 << 16) | (0x4 << 0),
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VENC_INT_IDLE_CTRL, (0x1 << 20) | (0x1 << 16) | (0x1 << 12),
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VENC_INT_AxCACHE_REMAPPING_REG(0, 0), (0x01234567),
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VENC_INT_AxCACHE_REMAPPING_REG(0, 1), (0x89abcd0f),
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VENC_INT_AxCACHE_REMAPPING_REG(1, 0), (0x01234567),
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VENC_INT_AxCACHE_REMAPPING_REG(1, 1), (0x89abcd0f),
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0,0,
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VXD_REGS_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x4 << 0),
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VXD_REGS_MEMCACHE_HINT_OVERRIDE, (0x1 << 31) | (0x1 << 30) | (0x1 << 16) | (0x4 << 0),
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VXD_REGS_MEMCACHE_DATASETID_OVERRIDE, (0xC00F000F),
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VDEC_INT_IDLE_CTRL, (0x1 << 12),
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VDEC_INT_AxCACHE_REMAPPING_REG(0, 0), (0x01234567),
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VDEC_INT_AxCACHE_REMAPPING_REG(0, 1), (0x89abcdef),
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VDEC_INT_AxCACHE_REMAPPING_REG(1, 0), (0x01234567),
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VDEC_INT_AxCACHE_REMAPPING_REG(1, 1), (0x89abcd0f),
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0,0,
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CAMERABUSMUX_REGS_ISPKF_RT, (0x10 << 8) | (0xc << 0),
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CAMERABUSMUX_REGS_CPG_CNTL, (0x1 << 31) | (0x4 << 0),
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0,0,
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ISP_DMA_REGS_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x4 << 0),
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ISP_DMA_REGS_BW_THRESHOLD, (0x24 << 16) | (0x10 << 0),
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ISP_DMA_REGS_AW_LIMIT, (0x30 << 8) | (0x30 << 0),
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ISP_DMA_REGS_AR_LIMIT, (0x40 << 8) | (0x40 << 0),
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ISP_DMA_REGS_MEMCACHE_DATASETID_OVERRIDE, (0xC00F000F),
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ISP_KF_REGS_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x4 << 0),
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ISP_KF_REGS_MEMCACHE_DATASETID_OVERRIDE, (0xC00F000F),
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0,0,
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DISPBUSMUX_REGS_DWRRCFG_DP1_BULK, (0x1e << 8) | (0x18 << 0),
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DISPBUSMUX_REGS_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x1 << 11) | (0x1 << 10) | (0x4 << 0),
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0,0,
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// For A0, DISP0 DYN_ENA is disabled in miu_update_device_tree.
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DISPLAYPIPE0_REGS_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x4 << 0),
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DISPLAYPIPE0_REGS_MEMCACHE_DATASETID_OVERRIDE, (0xC00F000F),
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0,0,
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DISPLAYPIPE1_REGS_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x4 << 0),
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DISPLAYPIPE1_REGS_MEMCACHE_DATASETID_OVERRIDE, (0xC00F000F),
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0,0,
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ANS_REGS_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x4 << 0),
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ANS_REGS_MEMCACHE_DATASETID_OVERRIDE, (0xC00F000F),
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ANS_KF_TLIMIT_RD, (0x00000909),
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ANS_KF_TLIMIT_WR, (0x00000909),
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ANS_ANC0_TLIMIT_RD, (0x00000505),
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ANS_ANC0_TLIMIT_WR, (0x00000505),
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ANS_ANC1_TLIMIT_RD, (0x00000505),
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ANS_ANC1_TLIMIT_WR, (0x00000505),
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0,0,
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GFX_REGS_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x4 << 0),
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0,0,
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GFX_IMG4_AFUSER_REGS_MCCFG_0, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x4 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_1, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x4 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_2, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x4 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_3, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x1 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_4, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x1 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_5, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x4 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_6, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x4 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_7, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x4 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_8, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x4 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_9, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x4 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_10, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x4 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_11, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x4 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_12, (0x0 << 23) | (0xD << 19) | (0x4 << 16) | (0x0 << 15) | (0xD << 11) | (0x1 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_13, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x1 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_14, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x4 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_15, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x4 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_16, (0x0 << 23) | (0xE << 19) | (0x4 << 16) | (0x0 << 15) | (0xE << 11) | (0x2 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_17, (0x0 << 23) | (0xE << 19) | (0x4 << 16) | (0x0 << 15) | (0xE << 11) | (0x2 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_18, (0x0 << 23) | (0xE << 19) | (0x4 << 16) | (0x0 << 15) | (0xE << 11) | (0x2 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_19, (0x0 << 23) | (0xE << 19) | (0x4 << 16) | (0x0 << 15) | (0xE << 11) | (0x2 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_20, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x4 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_21, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x4 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_22, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x4 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_23, (0x0 << 23) | (0xD << 19) | (0x4 << 16) | (0x0 << 15) | (0xD << 11) | (0x1 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_24, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x4 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_25, (0x0 << 23) | (0xF << 19) | (0x1 << 16) | (0x0 << 15) | (0xF << 11) | (0x1 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_26, (0x0 << 23) | (0xF << 19) | (0x1 << 16) | (0x0 << 15) | (0xF << 11) | (0x1 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_27, (0x0 << 23) | (0xF << 19) | (0x4 << 16) | (0x0 << 15) | (0xF << 11) | (0x4 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_28, (0x0 << 23) | (0xD << 19) | (0x4 << 16) | (0x0 << 15) | (0xD << 11) | (0x1 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_29, (0x0 << 23) | (0xF << 19) | (0x1 << 16) | (0x0 << 15) | (0xF << 11) | (0x1 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_30, (0x0 << 23) | (0xF << 19) | (0x1 << 16) | (0x0 << 15) | (0xF << 11) | (0x1 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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GFX_IMG4_AFUSER_REGS_MCCFG_31, (0x0 << 23) | (0xF << 19) | (0x1 << 16) | (0x0 << 15) | (0xF << 11) | (0x1 << 8) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0),
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0,0,
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AUSB_REGS_RD_RATE_LIMIT, (0x0),
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AUSB_REGS_WRALIMIT, (0x0),
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AUSB_REGS_WGATHER, (0x1 << 8),
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0,0,
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0,0,
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};
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#endif
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extern void ausb_setup_widgets();
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int miu_initialize_internal_ram(void)
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{
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#if APPLICATION_SECUREROM
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// Ensure that rPMGR_SCRATCH0-3 get cleared
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rPMGR_SCRATCH0 = 0;
|
||||
rPMGR_SCRATCH1 = 0;
|
||||
rPMGR_SCRATCH2 = 0;
|
||||
rPMGR_SCRATCH3 = 0;
|
||||
#endif /* APPLICATION_SECUREROM */
|
||||
|
||||
// Save the Security Epoch in the top byte of PMGR_SCRATCH0
|
||||
rPMGR_SCRATCH0 &= ~0xFF000000;
|
||||
rPMGR_SCRATCH0 |= (platform_get_security_epoch()) << 24;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int miu_init(void)
|
||||
{
|
||||
#if APPLICATION_IBOOT && !PRODUCT_IBEC
|
||||
// Verify that the Security Epoch in PMGR_SCRATCH0 matches
|
||||
if ((rPMGR_SCRATCH0 >> 24) != platform_get_security_epoch()) {
|
||||
panic("miu_init: Epoch Mismatch\n");
|
||||
}
|
||||
#endif
|
||||
#if (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
|
||||
miu_configure_bridge(bridge_settings_static);
|
||||
#endif
|
||||
ausb_setup_widgets();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void miu_suspend(void)
|
||||
{
|
||||
/* nothing required for suspend */
|
||||
}
|
||||
|
||||
int miu_initialize_dram(bool resume)
|
||||
{
|
||||
#if APPLICATION_IBOOT && WITH_HW_AMC
|
||||
mcu_initialize_dram(resume);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
void miu_select_remap(enum remap_select sel)
|
||||
{
|
||||
switch (sel) {
|
||||
case REMAP_SRAM:
|
||||
rTZSROMCTRL_ROMADDRREMAP = (rTZSROMCTRL_ROMADDRREMAP & ~3) | (1 << 0);
|
||||
break;
|
||||
|
||||
case REMAP_SDRAM:
|
||||
rTZSROMCTRL_ROMADDRREMAP = (rTZSROMCTRL_ROMADDRREMAP & ~3) | (2 << 0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void miu_bypass_prep(void)
|
||||
{
|
||||
}
|
||||
|
||||
static void miu_configure_bridge(const u_int32_t *bridge_settings)
|
||||
{
|
||||
volatile u_int32_t *reg;
|
||||
u_int32_t cnt = 0, bridge, offset, data;
|
||||
|
||||
while ((bridge_settings[cnt] != 0) || (bridge_settings[cnt + 1] != 0)) {
|
||||
while ((bridge_settings[cnt] != 0) || (bridge_settings[cnt + 1] != 0)) {
|
||||
bridge = bridge_settings[cnt] >> STATIC_BRIDGE_SHIFT;
|
||||
offset = bridge_settings[cnt] & STATIC_BRIDGE_MASK;
|
||||
data = bridge_settings[cnt + 1];
|
||||
reg = (volatile u_int32_t *)(bridge_registers[bridge] + offset);
|
||||
*reg = data;
|
||||
cnt += 2;
|
||||
}
|
||||
cnt += 2;
|
||||
}
|
||||
}
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
void miu_update_device_tree(DTNode *pmgr_node)
|
||||
{
|
||||
// XXX TODO: handle this better once we understand tunable story for FPGA
|
||||
#if !SUPPORT_FPGA
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
// Fill in the bridge-settings property
|
||||
propName = "bridge-settings";
|
||||
if (FindProperty(pmgr_node, &propName, &propData, &propSize)) {
|
||||
if (propSize < sizeof(bridge_settings_dynamic)) {
|
||||
panic("miu_update_device_tree: bridge-settings property is too small (0x%x/0x%zx)", propSize, sizeof(bridge_settings_dynamic));
|
||||
}
|
||||
memcpy(propData, bridge_settings_dynamic, sizeof(bridge_settings_dynamic));
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (C) 2011 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_MIU=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/miu.o
|
||||
Reference in new issue
Block a user