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/*
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* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <drivers/amc/amc.h>
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#include <drivers/amc/amc_phy.h>
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#include <drivers/amc/amc_regs.h>
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#include <drivers/amp/amp_v2.h>
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#include <drivers/amp/amp_v2_calibration.h>
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#include <drivers/dram.h>
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#include <drivers/miu.h>
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#include <sys.h>
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#include <platform/soc/hwclocks.h>
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#include <platform/soc/reconfig.h>
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int mcu_initialize_dram (bool resume)
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{
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return amc_init(resume);
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}
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void mcu_bypass_prep (int step)
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{
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amc_phy_bypass_prep(step);
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}
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uint64_t mcu_get_memory_size (void)
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{
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return amc_get_memory_size();
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}
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void amc_configure_address_decoding_and_mapping (void)
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{
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rAMC_ADDRCFG = amc_params.addrcfg;
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rAMC_CHNLDEC = amc_params.chnldec;
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rAMC_ADDRMAP_MODE = 2; // RIBI2
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rAMC_AIU_ADDRBANKHASH2 = amc_params.bankhash2;
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rAMC_AIU_ADDRBANKHASH1 = amc_params.bankhash1;
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rAMC_AIU_ADDRBANKHASH0 = amc_params.bankhash0;
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}
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void amc_enable_slow_boot (bool enable)
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{
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if (enable) {
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// switch to slow clock
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clocks_set_performance(kPerformanceMemoryLow);
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spin(1);
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} else {
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#if !SUPPORT_FPGA
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// switch back to full-speed
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clocks_set_performance(kPerformanceMemoryFull);
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spin(1);
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#endif
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}
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}
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// Some AMC features to be changed before calibration starts, and restored after calibration is complete
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void amc_calibration_start(bool start)
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{
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if (start)
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// Disable OdtsRdIntrvl
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rAMC_ODTS &= 0xFFFFFC00;
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else
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// Re-enable OdtsRdIntrvl
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rAMC_ODTS |= amc_params.odts;
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}
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void amc_enable_rddqcal(bool enable)
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{
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if (enable)
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rAMC_READ_LEVELING |= 1;
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else
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rAMC_READ_LEVELING &= ~1;
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}
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void amc_wrdqcal_start(bool start)
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{
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if (start) {
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// Enable WriteMergeEn and WqInOrderEn
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rAMC_PSQWQCTL0 = (1 << 8) | (1 << 0);
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// Set SelfRefTmrVal to max
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rAMC_PWRMNGTPARAM |= (0xFFFF << 16);
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// Designer suggests 0xBB, so that writes do not age out
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rAMC_PSQWQCTL1 = 0xBB;
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} else {
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rAMC_PSQWQCTL0 = 0x00010100;
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rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_guided;
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// WqAgeOutVal has to be set to 3/4 of SelfRefTmrVal
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rAMC_PSQWQCTL1 = (3 * ((amc_params.pwrmngtparam_guided & 0xFFFF0000) >> 16)) >> 2;
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// Enabling AutoSR only after wrdqcal is done
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rAMC_PWRMNGTEN |= 0x00011011;
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}
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}
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void amc_finalize (bool resume)
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{
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rAMC_AREFPARAM |= 0x00001800;
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rAMC_QBREN = 0x00110001;
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if (!resume) {
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#if SUPPORT_FPGA
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rAMC_ODTS = amc_params.odts;
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#else
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rAMC_ODTS = 0x00010000 | amc_params.odts;
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#endif
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amc_enable_autorefresh();
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}
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rAMC_ZQC = 0x010c03ff;
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#if !SUPPORT_FPGA
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rAMC_AIUPRT_RD_CWF = 0x00323200;
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#endif
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rAMC_QBRPARAM = 0x00510000;
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rAMC_QBREN = 0x00111001;
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rAMC_PSQWQCTL0 = 0x00010100;
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#if SUPPORT_FPGA
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rAMC_PWRMNGTEN = 0x00110010;
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#else
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rAMC_PWRMNGTEN = 0x00111011;
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rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_guided;
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#endif
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}
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void amc_dram_workarounds (bool resume)
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{
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const struct amc_memory_device_info *dev_info;
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dev_info = amc_get_memory_device_info();
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switch (dev_info->vendor_id) {
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case JEDEC_MANUF_ID_HYNIX:
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// No work-arounds for Hynix ... yet!
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break;
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case JEDEC_MANUF_ID_ELPIDA:
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/* Filter only for Elpida 25nm to apply test MRS */
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if ((dev_info->rev_id == 0x2) && (dev_info->rev_id2 <= 0x2)) { // MR6 = 2(25nm) and MR7 = 2(Rev2)
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if (!resume) {
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// Elpida has no TestMRS entry/exit cmd
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// <rdar://problem/15465954> Fiji: Need Duty Cycle Adjust work-around to improve Fiji+Elpida 25nm DDR eye margin
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xbb);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x27);
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}
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}
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break;
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default:
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break;
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}
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return;
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}
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// Shift dq offset as needed.
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// In the future, it's possible the shift value changes based on SOC or DRAM vendor.
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// Thus, we need to have this function per SOC.
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void amc_dram_shift_dq_offset (int8_t *dq_offset, uint8_t num_bytes) {
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int8_t shift_val;
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uint8_t i;
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const struct amc_memory_device_info *dev_info;
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dev_info = amc_get_memory_device_info();
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// No shifts defined by SEG yet for M7
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switch (dev_info->vendor_id) {
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case JEDEC_MANUF_ID_HYNIX:
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case JEDEC_MANUF_ID_SAMSUNG:
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case JEDEC_MANUF_ID_ELPIDA:
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default:
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shift_val = 0;
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break;
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}
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if (shift_val)
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for (i = 0; i < num_bytes; i++)
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dq_offset[i] += shift_val;
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}
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#if WITH_HW_RECONFIG
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#define CALIB_TYPE_CAWRLVL 0
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#define CALIB_TYPE_DQWRLVL 1
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// <rdar://problem/16356260> M7 MEM Reconfig sequence: remove phyupdates
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#if 0
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static void amp_phy_update_reconfig(uint32_t update)
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{
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// Release CKE and disable phyupdt to allow normal operation
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if (!update)
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_TESTMODE(AMP_CA,0), 0, 0);
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// issue phyupdt to block AMC traffic
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_CAPHYUPDTCRTL(0), update, 0);
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// wait for the phyupdt change to take effect. there is only 1 bit in the status reg: bit 0.
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reconfig_append_command(RECONFIG_TYPE_MEM, ((addr_t) &rAMP_CAPHYUPDTSTATUS(0)) | RECONFIG_RAM_CMD_READ, (update & 1), 1);
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// CKE must be low when updating dlysel to avoid glitches
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if (update)
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_TESTMODE(AMP_CA,0), TESTMODE_FORCECKELOW, 0);
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}
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#endif
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static void amp_wrlvl_program_reconfig(uint32_t calib_type, uint32_t byte)
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{
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addr_t codeaddr, dlyaddr;
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uint32_t code, dly;
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if (calib_type == CALIB_TYPE_CAWRLVL) {
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codeaddr = (addr_t) &rAMP_CAWRLVLSDLLCODE(0);
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code = rAMP_CAWRLVLSDLLCODE(0);
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dlyaddr = (addr_t) &rAMP_CAWRLVLCLKDLYSEL(0);
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dly = rAMP_CAWRLVLCLKDLYSEL(0);
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} else {
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codeaddr = (addr_t) &rAMP_DQWRLVLSDLLCODE(0, byte);
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dlyaddr = (addr_t) &rAMP_DQWRLVLDLYCHAINCTRL(0, byte);
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code = rAMP_DQWRLVLSDLLCODE(0, byte);
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dly = rAMP_DQWRLVLDLYCHAINCTRL(0, byte);
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}
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reconfig_append_command(RECONFIG_TYPE_MEM, codeaddr, code, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, dlyaddr, dly, 0);
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}
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void amc_configure_mem_reconfig_ram(void)
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{
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uint32_t f, i;
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#if !SUPPORT_FPGA
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uint32_t byte, bit;
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#endif
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/* Step 1: AMC Initial Configuration */
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLSTS(AMP_DQ,0), 0x00017307, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLSTS(AMP_CA,0), 0x00017307, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_LAT, (amc_params.rdlat << 16) | (amc_params.wrlat << 8), 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_PHYRDWRTIM, (amc_params.phywrlat << 16) | (amc_params.phyrdlat << 8) | (amc_params.rdlat - 2), 0);
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for(f = 0; f < AMC_FREQUENCY_SLOTS; f++) {
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_CAS_FREQ(f), amc_params.freq[f].cas, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_PCH_FREQ(f), amc_params.freq[f].pch, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_ACT_FREQ(f), amc_params.freq[f].act, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_AUTO_FREQ(f), amc_params.freq[f].autoref | ((f == 0) ? amc_params.tREFi : 0), 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_SELF_FREQ(f), amc_params.freq[f].selfref, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_MODE_FREQ(f), amc_params.freq[f].modereg, 0);
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}
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_AUTOREF_PARAMS, amc_params.autoref_params, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_PDN, amc_params.pdn, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_DERATE, amc_params.derate, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_RD, amc_params.read, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_BUSTAT, amc_params.bustat, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_BUSTAT_FREQ23, amc_params.bustat2, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_TREFBWBASECYC_FREQ(0), amc_params.freq[0].trefbwbasecyc, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_TREFBWBASECYC_FREQ(1), amc_params.freq[1].trefbwbasecyc, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_TREFBWBASECYC_FREQ(2), amc_params.freq[2].trefbwbasecyc, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_MIFCASSCH_FREQ(0), amc_params.freq[0].mifcassch, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_CH0RNKCFG0, 1, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_PWRMNGTEN, amc_params.pwrmngten_default, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_SCHEN, amc_params.schen_default, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_MCPHY_UPDTPARAM1, amc_params.mcphyupdate1, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_MCPHY_UPDTPARAM, amc_params.mcphyupdate, 0);
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// AMCEN
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{
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uint32_t amc_en = 0x00000001;
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if (amc_params.flags & FLAG_AMC_PARAM_LEGACY)
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{
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amc_en |= 0x80000000;
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}
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if (amc_params.flags & FLAG_AMC_PARAM_ENABLE_AIU)
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{
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amc_en |= 0x10000;
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}
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_AMCEN, amc_en, 0);
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}
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_AIU_ADDRBANKHASH2, amc_params.bankhash2, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_AIU_ADDRBANKHASH1, amc_params.bankhash1, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_AIU_ADDRBANKHASH0, amc_params.bankhash0, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_ADDRMAP_MODE, 2, 0);
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/* Step 2: AMP Initial Configurations */
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_AMPEN(AMP_CA,0), 1, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_AMPEN(AMP_DQ,0), 1, 0);
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#if !SUPPORT_FPGA
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DQDQSDS(0), amc_phy_params.drive_strength, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_NONDQDS(0), amc_phy_params.drive_strength, 0);
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#endif
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// DIFFMODE_FREQ[n], n=0..3
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for(f = 0; f < AMP_FREQUENCY_SLOTS; f++)
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DIFFMODE_FREQ(0,f), 0x00000121, 0);
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#if !SUPPORT_FPGA
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// RDnDQm_DESKEW_CTRL, n=0..3, m=0..7
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for(byte = 0; byte < AMP_MAX_RD; byte++)
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for(bit = 0; bit < AMP_MAX_DQ; bit++)
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_RDDQDESKEW_CTRL(0, byte, bit), 0x00000006, 0);
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// DLLLOCKTIM
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLLOCKTIM(AMP_CA,0), 0x000d0013, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLLOCKTIM(AMP_DQ,0), 0x000d0013, 0);
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#endif
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for(f = 0; f < AMP_FREQUENCY_SLOTS; f++) {
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_CAOUTDLLSCL_FREQ(0,f), amc_phy_params.freq[f].caoutdllscl, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DQSINDLLSCL_FREQ(0,f), amc_phy_params.freq[f].dqsindllscl, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_RDCAPCFG_FREQ(AMP_DQ,0,f), amc_phy_params.freq[f].rdcapcfg, 0);
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}
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#if !SUPPORT_FPGA
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// DLLUPDTCTRL
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLUPDTCTRL(AMP_CA,0), 0x00017507, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLUPDTCTRL(AMP_DQ,0), 0x00017507, 0);
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// IMPAUTOCAL
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_IMPAUTOCAL(AMP_DQ,0), amc_phy_params.imp_auto_cal, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_IMPAUTOCAL(AMP_CA,0), amc_phy_params.imp_auto_cal, 0);
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#endif
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// DLLUPDTINTVL
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#if !SUPPORT_FPGA
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uint32_t dllupdtintvl = 0x10200000;
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#else
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uint32_t dllupdtintvl = 0;
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#endif
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLUPDTINTVL(AMP_CA,0), dllupdtintvl, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLUPDTINTVL(AMP_DQ,0), dllupdtintvl, 0);
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// DLLEN sequence
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#if !SUPPORT_FPGA
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLEN(AMP_CA,0), 0x00000100, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLEN(AMP_DQ,0), 0x00000100, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLEN(AMP_CA,0), 0x00000101, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLEN(AMP_DQ,0), 0x00000101, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLEN(AMP_CA,0), 0x00000100, 0);
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reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLEN(AMP_DQ,0), 0x00000100, 0);
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#endif
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||||
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||||
// MDLLFREQBINDISABLE
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||||
#if !SUPPORT_FPGA
|
||||
uint32_t mdllfreqbindisable = 0x00000008;
|
||||
#else
|
||||
uint32_t mdllfreqbindisable = 0x0000000f;
|
||||
#endif
|
||||
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_MDLLFREQBINDISABLE(AMP_CA,0), mdllfreqbindisable, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_MDLLFREQBINDISABLE(AMP_DQ,0), mdllfreqbindisable, 0);
|
||||
|
||||
// DLLUPDTCMD
|
||||
#if !SUPPORT_FPGA
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLUPDTCMD(AMP_CA,0), 0x00000001, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLUPDTCMD(AMP_DQ,0), 0x00000001, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, ((addr_t) &rAMP_DLLUPDTCMD(AMP_CA,0)) | RECONFIG_RAM_CMD_READ, 0, 1);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, ((addr_t) &rAMP_DLLUPDTCMD(AMP_DQ,0)) | RECONFIG_RAM_CMD_READ, 0, 1);
|
||||
#endif
|
||||
|
||||
// AMPINIT
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_AMPINIT(AMP_CA,0), 0x00000001, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_AMPINIT(AMP_DQ,0), 0x00000001, 0);
|
||||
// IMPCALCMD sequence
|
||||
#if !SUPPORT_FPGA
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_IMPCALCMD(AMP_CA,0), 0x00000101, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_IMPCALCMD(AMP_DQ,0), 0x00000101, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, ((addr_t) &rAMP_IMPCALCMD(AMP_CA,0)) | RECONFIG_RAM_CMD_READ, 0, 1);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, ((addr_t) &rAMP_IMPCALCMD(AMP_DQ,0)) | RECONFIG_RAM_CMD_READ, 0, 1);
|
||||
#endif
|
||||
|
||||
/* Step 3: Self-Refresh Exit */
|
||||
|
||||
#if !SUPPORT_FPGA
|
||||
/* CA calibration offsets */
|
||||
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_CASDLLCTRL(0), (1 << 24) | (rAMP_CASDLLCTRL(0)), 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, ((addr_t) &rAMP_CASDLLCTRL(0)) | RECONFIG_RAM_CMD_READ, 0, (1 << 24));
|
||||
|
||||
for (bit = 0; bit < CA_NUM_BITS; bit++)
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_CADESKEW_CTRL(0,bit), rAMP_CADESKEW_CTRL(0,bit), 0);
|
||||
|
||||
// ck: skip if 0, since that is reset value
|
||||
uint32_t caclk = rAMP_CKDESKEW_CTRL(0);
|
||||
if (caclk) {
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_TESTMODE(AMP_CA,0), TESTMODE_FORCECKELOW, 0);
|
||||
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DRAMSIGDLY(AMP_CA, 0, 0), rAMP_DRAMSIGDLY(AMP_CA, 0, 0), 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_CSDESKEW_CTRL(0), caclk, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_CKDESKEW_CTRL(0), caclk, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_CKEDESKEW_CTRL(0), caclk, 0);
|
||||
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_TESTMODE(AMP_CA,0), 0, 0);
|
||||
}
|
||||
|
||||
/* WrLvl calibration offsets */
|
||||
|
||||
amp_wrlvl_program_reconfig(CALIB_TYPE_CAWRLVL, 0);
|
||||
for (byte = 0; byte < DQ_NUM_BYTES; byte++)
|
||||
amp_wrlvl_program_reconfig(CALIB_TYPE_DQWRLVL, byte);
|
||||
#endif
|
||||
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_AREFPARAM, amc_params.freq[0].arefparam, 0);
|
||||
for (f = 1; f < AMC_FREQUENCY_SLOTS; f++)
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_AREFPARAM_FREQ(f), amc_params.freq[f].arefparam, 0);
|
||||
|
||||
#if !SUPPORT_FPGA
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_ODTS, amc_params.odts | 0x00010000, 0);
|
||||
#else
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_ODTS, amc_params.odts, 0);
|
||||
#endif
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_LONGSR, 0x01000000 | amc_params.longsrcnt | amc_params.srextrarefcnt, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_AREFEN_FREQ(3), 0, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_AREFEN_FREQ(2), 0, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_AREFEN_FREQ(1), amc_params.aref_freq1, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_AREFEN_FREQ(0), 0x01011001 | amc_params.aref_freq0, 0);
|
||||
// INITCMDCH0
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_CH0INITCMD, 0x1000, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, ((addr_t) &rAMC_CH0INITCMD) | RECONFIG_RAM_CMD_READ, 0, 0x1000);
|
||||
|
||||
/* Step 4: DRAM Reset, skipped for resume boot */
|
||||
|
||||
/* Step 5: Topology-specific configuration */
|
||||
|
||||
// ZQC
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_ZQC, 0x00090000, 0);
|
||||
// MR10: ZQCL
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_CH0MRCMD, 0xab000a01, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, ((addr_t) &rAMC_CH01MRSTATUS) | RECONFIG_RAM_CMD_READ, 0, 1);
|
||||
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_ZQC, 0x00080000, 0);
|
||||
// ADDRCFG
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_ADDRCFG, amc_params.addrcfg, 0);
|
||||
// CHNLDEC
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_AIU_CHNLDEC, amc_params.chnldec, 0);
|
||||
|
||||
/* Step 6: Switch from boot-clock speed to normal operation speed */
|
||||
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_SCHEN, amc_params.schen_default | 0x1, 0);
|
||||
|
||||
/* Step 7: CA and Rddq calibration, skipped for resume boot */
|
||||
|
||||
/* Step 8: Enable other features */
|
||||
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_AREFPARAM, amc_params.freq[0].arefparam | 0x00001800, 0);
|
||||
// ZQC
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_ZQC, 0x010c03ff, 0);
|
||||
// QBREN
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_QBREN, 0x00110001, 0);
|
||||
// PSQWQCTRL0
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_PSQWQCTL0, 0x00010100, 0);
|
||||
|
||||
/* Step 9: Enable the Fast Critical Word Forwarding feature */
|
||||
|
||||
// RD_CWF
|
||||
#if !SUPPORT_FPGA
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_AIUPRT_RD_CWF, 0x00323200, 0);
|
||||
#else
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_AIUPRT_RD_CWF, 0, 0);
|
||||
#endif
|
||||
// QBRPARAM
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_QBRPARAM, 0x00510000, 0);
|
||||
// QBREN
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_QBREN, 0x00111001, 0);
|
||||
|
||||
/* Step 10: Rddq and Wrdq offsets, restore dllupdtintvl POR value */
|
||||
|
||||
#if !SUPPORT_FPGA
|
||||
/* Rddq calibration offsets */
|
||||
|
||||
for (byte = 0; byte < DQ_NUM_BYTES; byte++) {
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DQSDLLCTRL_RD(0, byte), (1 << 24) | rAMP_DQSDLLCTRL_RD(0, byte), 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, ((addr_t) &rAMP_DQSDLLCTRL_RD(0, byte)) | RECONFIG_RAM_CMD_READ, 0, (1 << 24));
|
||||
|
||||
for (bit = 0; bit < DQ_NUM_BITS_PER_BYTE; bit++)
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_RDDQDESKEW_CTRL(0, byte, bit), rAMP_RDDQDESKEW_CTRL(0, byte, bit), 0);
|
||||
}
|
||||
|
||||
/* Wrdq calibration offsets */
|
||||
|
||||
for (byte = 0; byte < DQ_NUM_BYTES; byte++) {
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DQSDLLCTRL_WR(0, byte), (1 << 24) | rAMP_DQSDLLCTRL_WR(0, byte), 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, ((addr_t) &rAMP_DQSDLLCTRL_WR(0, byte)) | RECONFIG_RAM_CMD_READ, 0, (1 << 24));
|
||||
|
||||
// rAMP_DQWRLVLDLYCHAINCTRL.WrLvlClk90Dly already restored as part of wrlvl offset restorations
|
||||
|
||||
for (bit = 0; bit < DQ_NUM_BITS_PER_BYTE; bit++)
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_WRDQDESKEW_CTRL(0, byte, bit), rAMP_WRDQDESKEW_CTRL(0, byte, bit), 0);
|
||||
|
||||
// DM controlled by DQS register
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_WRDQSDESKEW_CTRL(0, byte), rAMP_WRDQSDESKEW_CTRL(0, byte), 0);
|
||||
|
||||
// DQS controlled by DM register
|
||||
uint32_t dqs_deskew = rAMP_WRDMDESKEW_CTRL(0, byte);
|
||||
// skip if 0, since that is reset value
|
||||
if (dqs_deskew)
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_WRDMDESKEW_CTRL(0, byte), dqs_deskew, 0);
|
||||
}
|
||||
|
||||
// DLLUPDTCMD
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLUPDTCMD(AMP_CA,0), 0x00000001, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLUPDTCMD(AMP_DQ,0), 0x00000001, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, ((addr_t) &rAMP_DLLUPDTCMD(AMP_CA,0)) | RECONFIG_RAM_CMD_READ, 0, 1);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, ((addr_t) &rAMP_DLLUPDTCMD(AMP_DQ,0)) | RECONFIG_RAM_CMD_READ, 0, 1);
|
||||
#endif
|
||||
|
||||
// DLLUPDTINTVL
|
||||
#if !SUPPORT_FPGA
|
||||
dllupdtintvl = 0x1020005a;
|
||||
#else
|
||||
dllupdtintvl = 0;
|
||||
#endif
|
||||
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLUPDTINTVL(AMP_CA,0), dllupdtintvl, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_DLLUPDTINTVL(AMP_DQ,0), dllupdtintvl, 0);
|
||||
|
||||
/* Step 11: Enable Power & ClockGating features */
|
||||
|
||||
// AMPCLK
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_AMPCLK(AMP_CA,0), 0x00010000, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMP_AMPCLK(AMP_DQ,0), 0x00010000, 0);
|
||||
#if SUPPORT_FPGA
|
||||
// PWRMNGTEN
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_PWRMNGTEN, 0x00110010, 0);
|
||||
#else
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_PWRMNGTEN, 0x00111011, 0);
|
||||
#endif
|
||||
#if !SUPPORT_FPGA
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_PWRMNGTPARAM, amc_params.pwrmngtparam_guided, 0);
|
||||
// PSQWQCTL1
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_PSQWQCTL1, 0x00000120, 0);
|
||||
#endif
|
||||
|
||||
/* Step 12: Do a ODTS Read */
|
||||
|
||||
// MR4
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) &rAMC_CH0MRCMD, 0x00000411, 0);
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, ((addr_t) &rAMC_CH01MRSTATUS) | RECONFIG_RAM_CMD_READ, 0, 1);
|
||||
|
||||
/* AMC Tunables */
|
||||
for (i = 0; i < sizeof(amc_tunables) / sizeof(amc_tunables[0]); i++) {
|
||||
if (amc_tunables[i].reg == 0)
|
||||
break;
|
||||
reconfig_append_command(RECONFIG_TYPE_MEM, (addr_t) amc_tunables[i].reg, amc_tunables[i].value, 0);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // WITH_HW_RECONFIG
|
||||
@@ -0,0 +1,16 @@
|
||||
# Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_AMC=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/amc.o
|
||||
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* Copyright (c) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <arch/arm/assembler.h>
|
||||
|
||||
#if APPLICATION_IBOOT && (PRODUCT_IBSS || PRODUCT_LLB)
|
||||
|
||||
.text
|
||||
.arm
|
||||
.align 12
|
||||
.globl _boot_handoff_trampoline, _boot_handoff_trampoline_end
|
||||
_boot_handoff_trampoline:
|
||||
// Reset VBAR to 0
|
||||
mov r1, #0 // iBSS and LLB doesn't pass forward anything to next stage.
|
||||
mcr p15, 0, r1, c12, c0, 0
|
||||
isb
|
||||
bx r0
|
||||
_boot_handoff_trampoline_end:
|
||||
|
||||
.text
|
||||
.arm
|
||||
.align 12
|
||||
.globl _platform_start
|
||||
_platform_start:
|
||||
// Use VBAR to relocate exception vectors to binary linked address
|
||||
mcr p15, 0, r0, c12, c0, 0
|
||||
isb
|
||||
bx lr
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,130 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <platform.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <platform/soc/pmgr.h>
|
||||
|
||||
bool chipid_get_current_production_mode(void)
|
||||
{
|
||||
return ((rCFG_FUSE0 >> 0) & 1) != 0;
|
||||
}
|
||||
|
||||
bool chipid_get_raw_production_mode(void)
|
||||
{
|
||||
return ((rCFG_FUSE0_RAW >> 0) & 1) != 0;
|
||||
}
|
||||
|
||||
void chipid_clear_production_mode(void)
|
||||
{
|
||||
rCFG_FUSE0 &= ~1;
|
||||
}
|
||||
|
||||
bool chipid_get_secure_mode(void)
|
||||
{
|
||||
// we never demote secure mode on platforms that don't have an SEP
|
||||
return ((rCFG_FUSE0_RAW >> 1) & 1) != 0;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_security_domain(void)
|
||||
{
|
||||
return (rCFG_FUSE0 >> 2) & 3;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_board_id(void)
|
||||
{
|
||||
return (rCFG_FUSE0 >> 4) & 3;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_minimum_epoch(void)
|
||||
{
|
||||
return (rCFG_FUSE0 >> 9) & 0x7F;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_chip_id(void)
|
||||
{
|
||||
return 0x7002;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_chip_revision(void)
|
||||
{
|
||||
return (((rCFG_FUSE0 >> 25) & 0x7) << 4) | (((rCFG_FUSE0 >> 22) & 0x7) << 0);
|
||||
}
|
||||
|
||||
uint32_t chipid_get_osc_frequency(void)
|
||||
{
|
||||
return OSC_FREQ;
|
||||
}
|
||||
|
||||
uint64_t chipid_get_ecid_id(void)
|
||||
{
|
||||
return ((uint64_t)rECIDHI << 32) | rECIDLO;
|
||||
}
|
||||
|
||||
uint64_t chipid_get_die_id(void)
|
||||
{
|
||||
return ((uint64_t)rECIDHI << 32) | rECIDLO;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_soc_voltage(uint32_t index)
|
||||
{
|
||||
uint32_t soc_voltage = 0;
|
||||
|
||||
return soc_voltage;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_cpu_voltage(uint32_t index)
|
||||
{
|
||||
uint32_t cpu_voltage = 0;
|
||||
|
||||
return cpu_voltage;
|
||||
}
|
||||
|
||||
|
||||
uint32_t chipid_get_ram_voltage(uint32_t index)
|
||||
{
|
||||
uint32_t sram_voltage = 0;
|
||||
|
||||
return sram_voltage;
|
||||
}
|
||||
|
||||
bool chipid_get_fuse_lock(void)
|
||||
{
|
||||
return (rCFG_FUSE1 & (1 << 31)) != 0;
|
||||
}
|
||||
|
||||
void chipid_set_fuse_lock(bool locked)
|
||||
{
|
||||
if (locked) rCFG_FUSE1 |= (1 << 31);
|
||||
}
|
||||
|
||||
uint32_t chipid_get_fuse_revision(void)
|
||||
{
|
||||
return (rCFG_FUSE0 >> 18) & 0xf;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_total_rails_leakage()
|
||||
{
|
||||
uint32_t total_leakage;
|
||||
uint32_t leakage_data0;
|
||||
uint8_t leakage_data1;
|
||||
|
||||
leakage_data0 = rCFG_FUSE5;
|
||||
leakage_data1 = (rCFG_FUSE4 >> 31) & 1;
|
||||
|
||||
total_leakage = ((leakage_data0 >> 28) & 0xf) + 1; // soc_sram: cfg_fuse4[31:28]
|
||||
total_leakage += ((leakage_data0 >> 24) & 0xf) + 1; // cpu_sram: cfg_fuse4[27:24]
|
||||
total_leakage += ((leakage_data0 >> 16) & 0xff) + 1; // gpu: cfg_fuse4[23:16]
|
||||
total_leakage += ((leakage_data0 >> 8) & 0xff) + 1; // soc: cfg_fuse4[15:8]
|
||||
total_leakage += ((((leakage_data0 >> 0) & 0xff) << 1) | leakage_data1) + 1; // cpu: cfg_fuse4[7:0], cfg_fuse4[31]
|
||||
|
||||
return total_leakage;
|
||||
}
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_PLATFORM_CHIPID=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/chipid.o
|
||||
@@ -0,0 +1,145 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#if WITH_TARGET_AMC_PARAMS
|
||||
#include <target/amcconfig.h>
|
||||
#else
|
||||
static const struct amc_param amc_params = {
|
||||
.flags = FLAG_AMC_PARAM_BUSTAT23 | FLAG_AMC_PARAM_ENABLE_AIU | FLAG_AMC_PARAM_LEGACY | FLAG_AMC_PARAM_ZQCL,
|
||||
|
||||
.freqsel = 3,
|
||||
.tREFi = 0x5d,
|
||||
.longsrcnt = 0x2008,
|
||||
.srextrarefcnt = (0x2 << 16),
|
||||
.rdlat = 4,
|
||||
.wrlat = 2,
|
||||
.phyrdlat = 8,
|
||||
.phywrlat = 1,
|
||||
.pdn = 0x22000303,
|
||||
.read = 0x00000102,
|
||||
.bustat = 0x00222209,
|
||||
.bustat2 = 0x00222209,
|
||||
.derate = 0x1c620d46,
|
||||
.mcphyupdate = 0x05030000,
|
||||
.mcphyupdate1 = 0x00000004,
|
||||
.autoref_params = 0x1a1a1a1a,
|
||||
.chnldec = 0x00050001,
|
||||
.qbrparam = 0x00510000,
|
||||
.odts = 0x190,
|
||||
.aref_freq0 = 0x00000110,
|
||||
.pwrmngtparam_small = 0x00011000,
|
||||
.pwrmngtparam_guided = 0x01803000,
|
||||
.schen_default = 0x00000110,
|
||||
.pwrmngten_default = 0x00100100,
|
||||
.addrcfg = 0x00020201,
|
||||
.bankhash0 = 0x00006db6,
|
||||
.bankhash1 = 0x00005b6d,
|
||||
.bankhash2 = 0x000036db,
|
||||
.bootclkdivsr = 1,
|
||||
.mr1 = 0xc4,
|
||||
.mr3 = 0x2,
|
||||
.mr2 = 0x6,
|
||||
.mr63 = 0xfc,
|
||||
.readleveling = 0x00000300,
|
||||
|
||||
.freq = {
|
||||
{ // 533MHz
|
||||
.cas = 0x00000206,
|
||||
.pch = 0x0002040c,
|
||||
.act = 0x0c040706,
|
||||
.autoref = 0x11240000,
|
||||
.selfref = 0x00026040,
|
||||
.modereg = 0x20190762,
|
||||
.arefparam = 0x0c022131,
|
||||
.mifcassch = 0x00000110,
|
||||
.trefbwbasecyc = 0x0000002d,
|
||||
},
|
||||
{ // 266MHz
|
||||
.cas = 0x00000004,
|
||||
.pch = 0x00000007,
|
||||
.act = 0x06020404,
|
||||
.autoref = 0x09120000,
|
||||
.selfref = 0x00014000,
|
||||
.modereg = 0x000d0000,
|
||||
.arefparam = 0x00000101,
|
||||
.mifcassch = 0x00000000,
|
||||
.trefbwbasecyc = 0x00000017,
|
||||
},
|
||||
{ // 133MHz
|
||||
.cas = 0x00000002,
|
||||
.pch = 0x00000004,
|
||||
.act = 0x04010302,
|
||||
.autoref = 0x050a0000,
|
||||
.selfref = 0x0000a000,
|
||||
.modereg = 0x00070000,
|
||||
.arefparam = 0x00000101,
|
||||
.mifcassch = 0x00000000,
|
||||
.trefbwbasecyc = 0x0000000c,
|
||||
},
|
||||
{ // 24MHz
|
||||
.cas = 0x00000002,
|
||||
.pch = 0x00000002,
|
||||
.act = 0x04010202,
|
||||
.autoref = 0x02030000,
|
||||
.selfref = 0x00003000,
|
||||
.modereg = 0x00020000,
|
||||
.arefparam = 0x00000101,
|
||||
.mifcassch = 0x00000010,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static const struct amc_tunable amc_tunables[] = {
|
||||
{ &rAMC_AIUPRT_CFG, 0x00070000},
|
||||
{ &rAMC_AIUPRT_RD_GEN, 0x80000018},
|
||||
{ &rAMC_AIU_CHNLCRD, 0x00180018},
|
||||
{ &rAMC_AIU_CHNLTM, 0x40003101},
|
||||
{ &rAMC_AIU_RDBRSTLEN, 0x01010101},
|
||||
{ &rAMC_AIU_RDMAXCRD, 0x3012097f},
|
||||
{ &rAMC_AIU_RDREFL, 0x280f087f},
|
||||
{ &rAMC_AIU_WRBRSTLEN, 0x01010101},
|
||||
{ &rAMC_AIU_WRMAXCRD, 0x3012097f},
|
||||
{ &rAMC_AIU_WRREFL, 0x280f087f},
|
||||
{ &rAMC_AIU_CPUSPCREQ, 0x00000013},
|
||||
{ &rAMC_AIU_GFXSPCREQ, 0x00000019},
|
||||
{ &rAMC_AIU_NRTSPCREQ, 0x00000019},
|
||||
{ &rAMC_AIU_RTSPCREQ, 0x00000013},
|
||||
{ &rAMC_AIU_WPQSCH, 0x08000800},
|
||||
{ &rAMC_AIU_THOTLEN, 0x00000030},
|
||||
{ &rAMC_AIU_THOTLCPUPARAM, 0x00000084},
|
||||
{ &rAMC_AIU_THOTLRTPARAM, 0x00000084},
|
||||
{ &rAMC_AIU_THOTLNRTPARAM, 0x00000080},
|
||||
{ &rAMC_AIU_THOTLGFXPARAM, 0x00000080},
|
||||
{ &rAMC_AIU_PUSHEN, 0x00001100},
|
||||
{ &rAMC_AIU_THOTLCPUPARAM2, 0x00c00040},
|
||||
{ &rAMC_AIU_THOTLRTPARAM2, 0x00c00040},
|
||||
{ &rAMC_AIU_THOTLNRTPARAM2, 0x00000040},
|
||||
{ &rAMC_AIU_THOTLGFXPARAM2, 0x00000040},
|
||||
{ &rAMC_AIU_LLTSCHCTL, 0x00000001},
|
||||
{ &rAMC_OPIDLETMR, 0x00200000},
|
||||
{ &rAMC_OPTMRADJPARAM, 0x20400064},
|
||||
{ &rAMC_MIFACTSCH, 0x00000001},
|
||||
{ &rAMC_PSQRQCTL0, 0x01010000},
|
||||
{ &rAMC_PSQRQCTL1, 0x0000132a},
|
||||
{ &rAMC_PSQRQTIMER0, 0x00000018},
|
||||
{ &rAMC_PSQRQTIMER1, 0x00000006},
|
||||
{ &rAMC_PSQRQTIMER2, 0x00000020},
|
||||
{ &rAMC_PSQRQBRST, 0x040c040c},
|
||||
{ &rAMC_PSQRQSCHCRD, 0x002028f5},
|
||||
{ &rAMC_PSQWQCTL1, 0x00000180},
|
||||
{ &rAMC_PSQWQBRST, 0x02020208},
|
||||
{ &rAMC_PSQWQSCHCRD, 0x000405f5},
|
||||
{ &rAMC_MCUQOS, 0x00010f04},
|
||||
{ &rAMC_MCUQOSLLT, 0x00010108},
|
||||
|
||||
{0, 0},
|
||||
};
|
||||
#endif
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The amc_param struct is defined in drivers/apple/amp/amp.h, and this
|
||||
* file should only by included from that amp.c.
|
||||
*/
|
||||
|
||||
#if WITH_TARGET_AMP_PARAMS
|
||||
#include <target/ampconfig.h>
|
||||
#else
|
||||
static struct amp_params amc_phy_params = {
|
||||
.freq = {
|
||||
{
|
||||
.caoutdllscl = 0x00000008,
|
||||
.dqsindllscl = 0x00000008,
|
||||
.rdcapcfg = 0x2102050b,
|
||||
},
|
||||
{
|
||||
.caoutdllscl = 0x00000010,
|
||||
.dqsindllscl = 0x00000010,
|
||||
.rdcapcfg = 0x31020507,
|
||||
},
|
||||
{
|
||||
.caoutdllscl = 0x00000020,
|
||||
.dqsindllscl = 0x00000020,
|
||||
.rdcapcfg = 0x51020505,
|
||||
},
|
||||
{
|
||||
.caoutdllscl = 0x0000003f,
|
||||
.dqsindllscl = 0x0000003f,
|
||||
.rdcapcfg = 0x61020504,
|
||||
},
|
||||
},
|
||||
.drive_strength = 0x12121212,
|
||||
.cacalib_hw_loops = 8,
|
||||
.cacalib_sw_loops = 8,
|
||||
.wrlvl_togglephyupdt = true,
|
||||
.imp_auto_cal = 0x001103ac,
|
||||
};
|
||||
#endif
|
||||
@@ -0,0 +1,163 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Dmin.h is provided by the diags team, defining the 'DMin' key's format
|
||||
* The contents below are copy-pasted verbatim from header files supplied by Diags.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _DMin_h_
|
||||
#define _DMin_h_
|
||||
|
||||
/* vim: set ts=4 sw=4 softtabstop=4 noexpandtab */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef MULTICHARACTER_LITERAL
|
||||
# define MULTICHARACTER_LITERAL(a,b,c,d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
|
||||
#endif
|
||||
|
||||
enum {
|
||||
kEnclosureNone = 0,
|
||||
kEnclosureAlumLight6063 = 1,
|
||||
kEnclosureAlumDark6063 = 2,
|
||||
kEnclosureAlumLight7003 = 3,
|
||||
kEnclosureAlumDark7003 = 4,
|
||||
kEnclosureSUSMirror = 5,
|
||||
kEnclosureSUSBrushed = 6,
|
||||
kEnclosureSUSBlackPVD = 7,
|
||||
kEnclosureMaverickYellow = 8,
|
||||
kEnclosureMaverickRose = 9,
|
||||
kEnclosureZirconiaWhite = 10,
|
||||
kEnclosureGlass = 11,
|
||||
};
|
||||
typedef uint32_t EnclosureType_t; // goes with above enum
|
||||
|
||||
enum {
|
||||
kFCMTypeNone = 0,
|
||||
kFCMTypeOnyx = 1,
|
||||
kFCMTypeGlass = 2,
|
||||
};
|
||||
typedef uint32_t FCMType_t; // goes with above
|
||||
|
||||
enum {
|
||||
kBCMWindowTypeNone = 0,
|
||||
kBCMWindowTypeOnyx = 1,
|
||||
kBCMWindowTypeGlass = 2,
|
||||
};
|
||||
typedef uint32_t BCMWindowType_t;
|
||||
|
||||
enum {
|
||||
kBCMLensTypeNone = 0,
|
||||
kBCMLensTypeNormal = 1,
|
||||
kBCMLensTypeFresnel = 2,
|
||||
};
|
||||
typedef uint32_t BCMLensType_t;
|
||||
|
||||
enum {
|
||||
kBCMLEDTypeNone = 0,
|
||||
kBCMLEDTypeNormal = 1,
|
||||
kBCMLEDTypeNew = 2,
|
||||
};
|
||||
typedef uint32_t BCMPTLEDType_t;
|
||||
|
||||
enum {
|
||||
kBCMPlatinumTypeNone = 0,
|
||||
kBCMPlatinumTypeProtoN_34 = 1,
|
||||
kBCMPlatinumTypeProtoC = 2,
|
||||
};
|
||||
typedef uint32_t BCMPTSensorType_t;
|
||||
|
||||
/* Version 2 information - added Lisa Bits */
|
||||
|
||||
enum {
|
||||
kLisaOpAmpNone = 0,
|
||||
kLisaOpAmpMAX4321 = 1,
|
||||
kLisaOpAmpLMV693 = 2,
|
||||
kLisaOpAmpLMV881 = 3,
|
||||
};
|
||||
typedef uint32_t LisaOpAmpType_t;
|
||||
|
||||
enum {
|
||||
kLisaSensorICNone = 0,
|
||||
kLisaSensorICA0 = 1,
|
||||
kLisaSensorICB0 = 2,
|
||||
};
|
||||
typedef uint32_t LisaSensorICType_t;
|
||||
|
||||
enum {
|
||||
kLisaWheelNone = 0,
|
||||
kLisaWheelLF31 = 1,
|
||||
kLisaWheelLF31LowDiffusion = 2,
|
||||
kLisaWheelLF31HighStripeVar = 3,
|
||||
kLisaWheelLF31pSLaser = 4,
|
||||
kLisaWheelLF45 = 5,
|
||||
kLisaWheelSantek = 6,
|
||||
kLisaWheelNisseiBlack = 7,
|
||||
kLisaWheelNissei = 8,
|
||||
kLisaWheelHeptagonGrind = 9,
|
||||
kLisaWheelHeptagonFormed = 10
|
||||
};
|
||||
typedef uint32_t LisaWheelType_t;
|
||||
|
||||
enum {
|
||||
kLisaKnurlNone = 0,
|
||||
kLisaKnurlProtoN = 1,
|
||||
};
|
||||
typedef uint32_t LisaKnurlType_t;
|
||||
|
||||
/* Pack the structure, do not allow compiler padding */
|
||||
typedef struct __attribute__((packed)) {
|
||||
EnclosureType_t topEnclosure; // See enum at the top
|
||||
EnclosureType_t botEnclosure; // Same values here
|
||||
FCMType_t fcmType; // Onyx or Glass
|
||||
uint32_t fcmARCoated; // 0x00000000 = no AR coating, 0x00000001 = AR coating
|
||||
uint32_t fcmInkColor; // 0x00RRGGBB (little endian, 32-bit word, just like DClr)
|
||||
BCMWindowType_t bcmWindow; // Onyx or Glass
|
||||
BCMLensType_t bcmLens; // Normal or Fresnel
|
||||
BCMPTSensorType_t bcmPTSensorType; // 3 or 4
|
||||
BCMPTLEDType_t bcmPTLEDType; // Normal or "New"
|
||||
} DMin_v1_t;
|
||||
|
||||
typedef struct __attribute__((packed)) {
|
||||
EnclosureType_t topEnclosure; // See enum at the top
|
||||
EnclosureType_t botEnclosure; // Same values here
|
||||
FCMType_t fcmType; // Onyx or Glass
|
||||
uint32_t fcmARCoated; // 0x00000000 = no AR coating, 0x00000001 = AR coating
|
||||
uint32_t fcmInkColor; // 0x00RRGGBB (little endian, 32-bit word, just like DClr)
|
||||
BCMWindowType_t bcmWindow; // Onyx or Glass
|
||||
BCMLensType_t bcmLens; // Normal or Fresnel
|
||||
BCMPTSensorType_t bcmPTSensorType; // 3 or 4
|
||||
BCMPTLEDType_t bcmPTLEDType; // Normal or "New"
|
||||
|
||||
// v2 bits
|
||||
LisaOpAmpType_t lisaOAType;
|
||||
LisaSensorICType_t lisaSensorIC;
|
||||
LisaWheelType_t lisaEncoderWheel;
|
||||
LisaKnurlType_t lisaKnurl;
|
||||
} DMin_v2_t;
|
||||
|
||||
#define DMIN_VERSION_1 0x00000001
|
||||
#define DMIN_VERSION_2 0x00000002
|
||||
|
||||
typedef struct {
|
||||
uint32_t version; // Set to DMIN_VERSION_2
|
||||
union {
|
||||
DMin_v1_t v1; // if version == DMIN_VERSION_1, use this struct
|
||||
DMin_v2_t v2; // if version == DMIN_VERSION_2, use this struct
|
||||
}; // Anonymous union to bridge between v1 and any later version
|
||||
}DMin_t;
|
||||
|
||||
#define SYSCFG_DEVICE_MATERIAL_INFO_SIZE (sizeof(DMin_t)) /* v1 = 40 bytes, v2 = 56 bytes */
|
||||
#define SYSCFG_DEVICE_MATERIAL_INFO MULTICHARACTER_LITERAL('D','M','i','n')
|
||||
|
||||
#endif /* _DMin_h_ */
|
||||
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __DOCKFIFO_CONFIG_H
|
||||
#define __DOCKFIFO_CONFIG_H
|
||||
|
||||
#include <drivers/dockfifo/dockfifo.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <platform/soc/hwisr.h>
|
||||
|
||||
// Fifo enumeration
|
||||
#define DOCKFIFO_UART_WRITE (DOCKFIFO_0)
|
||||
#define DOCKFIFO_UART_READ (DOCKFIFO_1)
|
||||
#define DOCKFIFO_BULK_WRITE (DOCKFIFO_2)
|
||||
#define DOCKFIFO_BULK_READ (DOCKFIFO_3)
|
||||
|
||||
static const struct dockfifo_config dockfifo_configs[] = {
|
||||
/* read/write clock interrupt fifo name */
|
||||
{ DOCKFIFO_W, CLK_DOCKFIFO, DBGFIFO_0_NOT_EMPTY, "uart write" },
|
||||
{ DOCKFIFO_R, CLK_DOCKFIFO, DBGFIFO_1_NOT_EMPTY, "uart read" },
|
||||
{ DOCKFIFO_W, CLK_DOCKFIFO, DBGFIFO_2_NOT_EMPTY, "bulk write" },
|
||||
{ DOCKFIFO_R, CLK_DOCKFIFO, DBGFIFO_3_NOT_EMPTY, "bulk read" },
|
||||
};
|
||||
|
||||
#endif /* __DOCKFIFO_CONFIG_H */
|
||||
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_GPIODEF_H
|
||||
#define __PLATFORM_GPIODEF_H
|
||||
|
||||
/* S7002 specific gpio -> pin mappings */
|
||||
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#if WITH_TARGET_CONFIG
|
||||
# include <target/gpiodef.h>
|
||||
#endif
|
||||
|
||||
/* define platform-specific gpios in a generic fashion here. */
|
||||
#define GPIO_BOARD_ID0 GPIOC(GPIO_AP, 12, 1)
|
||||
#define GPIO_BOARD_ID1 GPIOC(GPIO_AP, 12, 2)
|
||||
#define GPIO_BOARD_ID2 GPIOC(GPIO_AP, 12, 3)
|
||||
#define GPIO_BOARD_ID3 GPIOC(GPIO_AP, 4, 6)
|
||||
#define GPIO_BERMUDA_TO_AP_CTS GPIOC(GPIO_AP, 8, 1)
|
||||
|
||||
#define GPIO_BOOT_CONFIG0 GPIOC(GPIO_AP, 4, 2)
|
||||
#define GPIO_BOOT_CONFIG1 GPIOC(GPIO_AP, 4, 3)
|
||||
#define GPIO_BOOT_CONFIG2 GPIOC(GPIO_AP, 4, 4)
|
||||
#define GPIO_BOOT_CONFIG3 GPIOC(GPIO_AP, 4, 5)
|
||||
|
||||
#define GPIO_BOARD_REV0 GPIOC(GPIO_AP, 4, 7)
|
||||
#define GPIO_BOARD_REV1 GPIOC(GPIO_AP, 5, 0)
|
||||
#define GPIO_BOARD_REV2 GPIOC(GPIO_AP, 5, 1)
|
||||
#define GPIO_BOARD_REV3 GPIOC(GPIO_AP, 5, 2)
|
||||
|
||||
#define GPIO_REQUEST_DFU1 GPIOC(GPIO_SPU, 0, 0)
|
||||
#define GPIO_REQUEST_DFU2 GPIOC(GPIO_SPU, 0, 1)
|
||||
#define GPIO_FORCE_DFU GPIOC(GPIO_SPU, 2, 6)
|
||||
#define GPIO_DFU_STATUS GPIOC(GPIO_SPU, 2, 5)
|
||||
#define GPIO_DOCK_CONNECT GPIOC(GPIO_SPU, 0, 2)
|
||||
#define GPIO_DOCK_ATTENTION GPIOC(GPIO_SPU, 3, 2)
|
||||
|
||||
#define SPI_NOR0 (0)
|
||||
|
||||
#define GPIO_SPI0_CS GPIOC(GPIO_AP, 12, 4)
|
||||
|
||||
#define GPIO_IIC0_SCL GPIOC(GPIO_AP, 11, 7)
|
||||
#define GPIO_IIC0_SDA GPIOC(GPIO_AP, 11, 6)
|
||||
#define GPIO_IIC1_SCL GPIOC(GPIO_AP, 6, 1)
|
||||
#define GPIO_IIC1_SDA GPIOC(GPIO_AP, 6, 0)
|
||||
|
||||
#endif /* ! __PLATFORM_GPIODEF_H */
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_IMAGE_DEVICES_H
|
||||
#define __PLATFORM_IMAGE_DEVICES_H
|
||||
|
||||
static const struct image_device platform_image_devices[] = {
|
||||
#if defined(WITH_HW_ASP)
|
||||
{ "asp_fw", 0x00000 },
|
||||
|
||||
#if defined(WITH_LLB_NVRAM)
|
||||
{ "anc_firmware", 0x00000 } // iBoot->Dali may also use ANC firmware instead of ASP
|
||||
#endif
|
||||
#if WITH_LLB_BLKDEV
|
||||
, { "anc_llb", 0x00000 } // iBoot->Dali needs to read Dali out of block0
|
||||
#endif
|
||||
#elif defined(WITH_ANC_FIRMWARE)
|
||||
{ "anc_firmware", 0x00000 }
|
||||
#if WITH_LLB_BLKDEV
|
||||
, { "anc_llb", 0x00000 }
|
||||
#endif
|
||||
#else
|
||||
{ "nor0", 0x00000 }
|
||||
#endif
|
||||
};
|
||||
|
||||
#if WITH_SYSCFG
|
||||
static const struct image_device platform_syscfg_devices[] = {
|
||||
#if defined(WITH_NAND_BOOT)
|
||||
{ "nand_syscfg", 0x00000 }
|
||||
#else
|
||||
{ "nor0", 0x00000 }
|
||||
#endif
|
||||
};
|
||||
#endif /* WITH_SYSCFG */
|
||||
|
||||
#endif /* ! __PLATFORM_IMAGE_DEVICES_H */
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_MEMCONFIG_H
|
||||
#define __PLATFORM_MEMCONFIG_H
|
||||
|
||||
/* Stub */
|
||||
|
||||
static const gpio_t memory_interface_gpios[] = {
|
||||
/* Not needed */
|
||||
};
|
||||
#endif /* ! __PLATFORM_MEMCONFIG_H */
|
||||
@@ -0,0 +1,204 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_MEMMAP_H
|
||||
#define __PLATFORM_MEMMAP_H
|
||||
|
||||
#include <platform/memmap_defaults.h>
|
||||
|
||||
/* S7002 specific memory map */
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
// 0x80000000 + dram_size --> -------------------------------
|
||||
// | Sleep Token Buffer (1KiB) |
|
||||
// |-----------------------------|
|
||||
// | Panic (512KiB) |
|
||||
// |-----------------------------|
|
||||
// | Display (16MiB) |
|
||||
// | (Framebuffer + scratch) |
|
||||
// | |
|
||||
// | |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | iBoot (32MiB) |
|
||||
// | (Text + Data + Stacks ) |
|
||||
// | (Page Tables + Heap) |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | Unused |
|
||||
// | |
|
||||
// | |
|
||||
// | |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | |
|
||||
// | (Ramdisk) |
|
||||
// | (Kernel + DeviceTree) |
|
||||
// | Secure memory |
|
||||
// |-----------------------------|
|
||||
// | |
|
||||
// | |
|
||||
// | Load region / |
|
||||
// | Insecure Memory |
|
||||
// | |
|
||||
// | |
|
||||
// | |
|
||||
// 0x80000000 --> -------------------------------
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define SDRAM_BASE (0x80000000ULL)
|
||||
#define SDRAM_BANK_LEN (SDRAM_LEN)
|
||||
#define SDRAM_BANK_COUNT (1)
|
||||
#define SDRAM_END (SDRAM_BASE + SDRAM_LEN)
|
||||
#define SDRAM_BASE_UNCACHED (SDRAM_END)
|
||||
|
||||
#define VROM_BASE (0x40000000ULL)
|
||||
#define VROM_BANK_LEN (0x00100000ULL)
|
||||
#define VROM_LEN (0x00040000ULL)
|
||||
|
||||
#define SRAM_BASE (0x46000000ULL)
|
||||
#define SRAM_LEN (0x00048000ULL)
|
||||
#define SRAM_BANK_LEN (SRAM_LEN)
|
||||
#define SRAM_BANK_COUNT (1)
|
||||
#define SRAM_END (SRAM_BASE + SRAM_LEN)
|
||||
|
||||
#define IO_BASE (0x40000000ULL)
|
||||
#define IO_SIZE (0x20000000ULL)
|
||||
|
||||
/* custom ROM is stored at first physical page DRAM, and booted by enabling remap */
|
||||
#define SECUREROM_LOAD_ADDRESS (SDRAM_BASE)
|
||||
|
||||
/* sleep token is stored at first physical page in kernel memory */
|
||||
#define SLEEP_TOKEN_BUFFER_BASE (SDRAM_BASE)
|
||||
#define SLEEP_TOKEN_BUFFER_SIZE (1024)
|
||||
|
||||
/* reserved area for ASP */
|
||||
#define ASP_SIZE (0x00500000ULL)
|
||||
#define ASP_BASE (SDRAM_END - ASP_SIZE)
|
||||
|
||||
#define CONSISTENT_DEBUG_SIZE (0x00004000ULL)
|
||||
#define CONSISTENT_DEBUG_BASE (ASP_BASE - CONSISTENT_DEBUG_SIZE)
|
||||
|
||||
/* reserved area for panic info */
|
||||
#define PANIC_SIZE (0x00080000ULL)
|
||||
#define PANIC_BASE (CONSISTENT_DEBUG_BASE - PANIC_SIZE)
|
||||
|
||||
/* reserved area for display
|
||||
* DISPLAY_SIZE comes from platform's rules.mk
|
||||
*/
|
||||
#define DISPLAY_BASE (PANIC_BASE - DISPLAY_SIZE)
|
||||
|
||||
/* where to stick heap and insecure memory */
|
||||
#if APPLICATION_SECUREROM
|
||||
|
||||
#define INSECURE_MEMORY_SIZE (SRAM_END - HEAP_END)
|
||||
#define INSECURE_MEMORY_BASE (HEAP_END)
|
||||
|
||||
#define DATA_SIZE (0x00007000ULL)
|
||||
|
||||
#define BOOK_KEEPING_BASE (DATA_BASE + DATA_SIZE)
|
||||
#define BOOT_TRAMPOLINE_BASE (BOOK_KEEPING_BASE)
|
||||
#define BOOT_TRAMPOLINE_SIZE (0x00001000ULL)
|
||||
#define MMU_TT_BASE (BOOK_KEEPING_BASE + BOOT_TRAMPOLINE_SIZE)
|
||||
#define MMU_TT_SIZE (0x00004000ULL)
|
||||
#define STACK_BASE (BOOK_KEEPING_BASE + BOOT_TRAMPOLINE_SIZE + MMU_TT_SIZE)
|
||||
#define STACK_SIZE (0x00004000ULL)
|
||||
#define BOOK_KEEPING_SIZE (BOOT_TRAMPOLINE_SIZE + STACK_SIZE + MMU_TT_SIZE)
|
||||
|
||||
#define HEAP_BASE (BOOK_KEEPING_BASE + BOOK_KEEPING_SIZE)
|
||||
#define HEAP_SIZE (0x00008000ULL)
|
||||
#define HEAP_END (HEAP_BASE + HEAP_SIZE)
|
||||
|
||||
#endif /* APPLICATION_SECUREROM */
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
|
||||
#if WITH_DFU_MODE
|
||||
/* LLB, iBSS DFU */
|
||||
|
||||
/* reserved area for iBoot (aligned to 1MB boundary) */
|
||||
#define IBOOT_SIZE (0x02000000ULL + 0x100000ULL - (PANIC_SIZE + DISPLAY_SIZE))
|
||||
#define IBOOT_BASE (DISPLAY_BASE - IBOOT_SIZE)
|
||||
|
||||
#define INSECURE_MEMORY_SIZE (IBOOT_SIZE)
|
||||
#define INSECURE_MEMORY_BASE (IBOOT_BASE)
|
||||
|
||||
#define STACK_SIZE (0x00004000ULL)
|
||||
#define MMU_TT_SIZE (0x00004000ULL)
|
||||
#define BOOK_KEEPING_SIZE (STACK_SIZE + MMU_TT_SIZE)
|
||||
#define BOOK_KEEPING_BASE (SRAM_BASE)
|
||||
#define MMU_TT_BASE (BOOK_KEEPING_BASE)
|
||||
#define STACK_BASE (BOOK_KEEPING_BASE + MMU_TT_SIZE)
|
||||
|
||||
#define HEAP_SIZE (TEXT_BASE - HEAP_BASE)
|
||||
#define HEAP_BASE (BOOK_KEEPING_BASE + BOOK_KEEPING_SIZE)
|
||||
#define HEAP_END (HEAP_BASE + HEAP_SIZE)
|
||||
|
||||
#else /* !WITH_DFU_MODE */
|
||||
|
||||
#if WITH_RECOVERY_MODE_IBSS
|
||||
|
||||
/* reserved area for iBoot (aligned to 1MB boundary) */
|
||||
#define IBOOT_SIZE (0x02000000ULL + 0x100000ULL - (PANIC_SIZE + DISPLAY_SIZE))
|
||||
#define IBOOT_BASE (DISPLAY_BASE - IBOOT_SIZE)
|
||||
|
||||
#define INSECURE_MEMORY_SIZE (IBOOT_SIZE)
|
||||
#define INSECURE_MEMORY_BASE (IBOOT_BASE)
|
||||
|
||||
#define STACK_SIZE (0x00004000ULL)
|
||||
#define MMU_TT_SIZE (0x00004000ULL)
|
||||
#define BOOK_KEEPING_SIZE (STACK_SIZE + MMU_TT_SIZE)
|
||||
#define BOOK_KEEPING_BASE (TEXT_BASE + TEXT_FOOTPRINT)
|
||||
#define MMU_TT_BASE (BOOK_KEEPING_BASE)
|
||||
#define STACK_BASE (BOOK_KEEPING_BASE + MMU_TT_SIZE)
|
||||
|
||||
#define HEAP_SIZE (SRAM_END - HEAP_BASE)
|
||||
#define HEAP_BASE (BOOK_KEEPING_BASE + BOOK_KEEPING_SIZE)
|
||||
#define HEAP_END (HEAP_BASE + HEAP_SIZE)
|
||||
|
||||
#else
|
||||
|
||||
/* iBoot, iBEC */
|
||||
|
||||
#define IBOOT_BASE (TEXT_BASE)
|
||||
#define IBOOT_SIZE (HEAP_END - IBOOT_BASE)
|
||||
|
||||
#define BOOK_KEEPING_BASE (IBOOT_BASE + TEXT_FOOTPRINT)
|
||||
#define MMU_TT_BASE (BOOK_KEEPING_BASE)
|
||||
#define MMU_TT_SIZE (0x00004000ULL)
|
||||
#define STACK_BASE (BOOK_KEEPING_BASE + MMU_TT_SIZE)
|
||||
#define STACK_SIZE (0x00004000ULL)
|
||||
#define BOOK_KEEPING_SIZE (STACK_SIZE + MMU_TT_SIZE)
|
||||
|
||||
#define HEAP_BASE (BOOK_KEEPING_BASE + BOOK_KEEPING_SIZE)
|
||||
#define HEAP_SIZE (DISPLAY_BASE - HEAP_BASE - PAGE_SIZE)
|
||||
#define HEAP_END (HEAP_BASE + HEAP_SIZE)
|
||||
#define HEAP_GUARD (HEAP_END)
|
||||
#if (HEAP_GUARD != (DISPLAY_BASE - PAGE_SIZE))
|
||||
#error "Memory map configuration error"
|
||||
#endif
|
||||
|
||||
#define INSECURE_MEMORY_BASE (SDRAM_BASE)
|
||||
#define INSECURE_MEMORY_SIZE (DEFAULT_LOAD_SIZE)
|
||||
|
||||
#define SECURE_MEMORY_BASE (INSECURE_MEMORY_BASE + INSECURE_MEMORY_SIZE)
|
||||
#define SECURE_MEMORY_SIZE (DEFAULT_FREE_ADDRESS - SECURE_MEMORY_BASE)
|
||||
|
||||
/* unused area */
|
||||
#define UNUSED_MEMORY_BASE (SECURE_MEMORY_BASE + SECURE_MEMORY_SIZE)
|
||||
#define UNUSED_MEMORY_SIZE (IBOOT_BASE - UNUSED_MEMORY_BASE)
|
||||
|
||||
#endif /* WITH_RECOVERY_MODE_IBSS */
|
||||
|
||||
#endif /* !WITH_DFU_MODE */
|
||||
|
||||
#endif /* APPLICATION_IBOOT */
|
||||
|
||||
#endif /* ! __PLATFORM_MEMMAP_H */
|
||||
@@ -0,0 +1,301 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_PINCONFIG_H
|
||||
#define __PLATFORM_PINCONFIG_H
|
||||
|
||||
/* Default S7002 SoC Pin Configuration */
|
||||
#define NAND_DRIVE_STR (DRIVE_X2 | SLOW_SLEW)
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_0_GROUP_COUNT * GPIOPADPINS] = {
|
||||
/* Port 0 */
|
||||
CFG_DISABLED, // I2S0_MCK ->
|
||||
CFG_DISABLED, // I2S1_MCK ->
|
||||
CFG_DISABLED, // SD_CLKOUT ->
|
||||
CFG_DISABLED, // SD_CMD_IO ->
|
||||
CFG_DISABLED, // SD_DATA_IO[0] ->
|
||||
CFG_DISABLED, // SD_DATA_IO[1] ->
|
||||
CFG_DISABLED, // SD_DATA_IO[2] ->
|
||||
CFG_DISABLED, // SD_DATA_IO[3] ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED, // SDIO_IRQ ->
|
||||
CFG_DISABLED, // WL_HOST_WAKE ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED, // GPIO0 ->
|
||||
CFG_DISABLED, // GPIO1 ->
|
||||
CFG_DISABLED, // GPIO2 -> BOOT_CONFIG[0]
|
||||
CFG_DISABLED, // GPIO3 -> BOOT_CONFIG[1]
|
||||
CFG_DISABLED, // GPIO4 -> BOOT_CONFIG[2]
|
||||
CFG_DISABLED, // GPIO5 -> BOOT_CONFIG[3]
|
||||
CFG_DISABLED, // GPIO6 -> BOARD_ID[3]
|
||||
CFG_DISABLED, // GPIO7 ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED, // GPIO8 ->
|
||||
CFG_DISABLED, // GPIO9 ->
|
||||
CFG_DISABLED, // GPIO10 ->
|
||||
CFG_DISABLED, // GPIO11 ->
|
||||
CFG_DISABLED, // GPIO12 ->
|
||||
CFG_DISABLED, // GPIO13 ->
|
||||
CFG_DISABLED, // GPIO14 ->
|
||||
CFG_DISABLED, // GPIO15 ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED, // I2C1_SDA ->
|
||||
CFG_DISABLED, // I2C1_SCL ->
|
||||
CFG_DISABLED, // I2S0_LRCK ->
|
||||
CFG_DISABLED, // I2S0_BCLK ->
|
||||
CFG_DISABLED, // I2S0_DOUT ->
|
||||
CFG_DISABLED, // I2S0_DIN ->
|
||||
CFG_DISABLED, // I2S1_LRCK ->
|
||||
CFG_DISABLED, // I2S1_BCLK ->
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED, // I2S1_DOUT ->
|
||||
CFG_DISABLED, // I2S1_DIN ->
|
||||
CFG_DISABLED, // UART1_TXD ->
|
||||
CFG_DISABLED, // UART1_RXD ->
|
||||
CFG_DISABLED, // UART1_RTSN ->
|
||||
CFG_DISABLED, // UART1_CTSN ->
|
||||
CFG_DISABLED, // UART2_TXD ->
|
||||
CFG_DISABLED, // UART2_RXD ->
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // UART2_RTSN ->
|
||||
CFG_DISABLED, // UART2_CTSN ->
|
||||
CFG_DISABLED, // UART4_TXD ->
|
||||
CFG_DISABLED, // UART4_RXD ->
|
||||
CFG_DISABLED, // UART3_RTXD ->
|
||||
CFG_DISABLED, // CLK32K_OUT ->
|
||||
CFG_DISABLED, // TEST_CLKOUT ->
|
||||
CFG_DISABLED, // GPIO16 ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // GPIO17 ->
|
||||
CFG_DISABLED, // GPIO18 ->
|
||||
CFG_DISABLED, // TMR32_PWM1 ->
|
||||
CFG_DISABLED, // TMR32_PWM2 ->
|
||||
CFG_DISABLED, // TMR32_PWM3 ->
|
||||
CFG_DISABLED, // DISP_TE ->
|
||||
CFG_DISABLED, // GPIO19 ->
|
||||
CFG_DISABLED | NAND_DRIVE_STR, // NAND_CEN[0] ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED | NAND_DRIVE_STR, // NAND_CEN[1] ->
|
||||
CFG_DISABLED | PULL_DOWN | NAND_DRIVE_STR, // NAND_IO[7] ->
|
||||
CFG_DISABLED | PULL_DOWN | NAND_DRIVE_STR, // NAND_IO[6] ->
|
||||
CFG_DISABLED | PULL_DOWN | NAND_DRIVE_STR, // NAND_IO[5] ->
|
||||
CFG_DISABLED | PULL_DOWN | NAND_DRIVE_STR, // NAND_IO[4] ->
|
||||
CFG_DISABLED | PULL_DOWN | NAND_DRIVE_STR, // NAND_DQS ->
|
||||
CFG_DISABLED | PULL_UP | NAND_DRIVE_STR, // NAND_REN ->
|
||||
CFG_DISABLED | PULL_DOWN | NAND_DRIVE_STR, // NAND_IO[3] ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED | PULL_DOWN | NAND_DRIVE_STR, // NAND_IO[2] ->
|
||||
CFG_DISABLED | PULL_DOWN | NAND_DRIVE_STR, // NAND_IO[1] ->
|
||||
CFG_DISABLED | PULL_DOWN | NAND_DRIVE_STR, // NAND_IO[0] ->
|
||||
CFG_DISABLED | PULL_UP | NAND_DRIVE_STR, // NAND_WEN ->
|
||||
CFG_DISABLED | PULL_DOWN | NAND_DRIVE_STR, // NAND_CLE ->
|
||||
CFG_DISABLED | PULL_DOWN | NAND_DRIVE_STR, // NAND_ALE ->
|
||||
CFG_DISABLED, // I2C0_SDA ->
|
||||
CFG_DISABLED, // I2C0_SCL ->
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // DISPLAY_SYNC ->
|
||||
CFG_DISABLED, // SPI0_SCLK -> SPI0_SCLK/BOARD_ID[0]
|
||||
CFG_DISABLED, // SPI0_MOSI -> SPI0_MOSI/BOARD_ID[1]
|
||||
CFG_DISABLED, // SPI0_MISO -> SPI0_MISO/BOARD_ID[2]
|
||||
CFG_DISABLED, // SPI0_SSIN ->
|
||||
CFG_DISABLED, // UART0_TXD ->
|
||||
CFG_DISABLED, // UART0_RXD ->
|
||||
CFG_DISABLED, // SPI1_SCLK ->
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // SPI1_MOSI ->
|
||||
CFG_DISABLED, // SPI1_MISO ->
|
||||
CFG_DISABLED, // SPI1_SSIN ->
|
||||
CFG_DISABLED, // GPIO20 ->
|
||||
CFG_DISABLED, // GPIO21 ->
|
||||
CFG_DISABLED, // GPIO22 ->
|
||||
CFG_DISABLED, // GPIO23 ->
|
||||
CFG_DISABLED, // GPIO24 ->
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // GPIO25 ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED, // ENET_MDC ->
|
||||
CFG_DISABLED, // ENET_MDIO ->
|
||||
CFG_DISABLED, // RMII_RXER ->
|
||||
CFG_DISABLED, // RMII_TXEN ->
|
||||
CFG_DISABLED, // RMII_CLK ->
|
||||
CFG_DISABLED, // RMII_TXD[0] ->
|
||||
CFG_DISABLED, // RMII_TXD[1] ->
|
||||
CFG_DISABLED, // RMII_RXD[0] ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // RMII_RXD[1] ->
|
||||
CFG_DISABLED, // RMII_RXD[0] ->
|
||||
CFG_DISABLED, // RMII_CRSDV ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
};
|
||||
|
||||
static const uint32_t gpio_1_default_cfg[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
|
||||
/* Port 0 */
|
||||
CFG_IN, // REQUEST_DFU1 ->
|
||||
CFG_IN, // REQUEST_DFU2 ->
|
||||
CFG_IN | PULL_DOWN, // DOCK_CONNECT ->
|
||||
CFG_DISABLED, // CLK32K_IN ->
|
||||
CFG_DISABLED, // SPU_UART0_TXD ->
|
||||
CFG_DISABLED, // SPU_UART0_RXD ->
|
||||
CFG_DISABLED, // SPU_UART0_RTSN ->
|
||||
CFG_DISABLED, // SPU_UART0_CTSN ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED, // SPU_UART1_TXD ->
|
||||
CFG_DISABLED, // SPU_UART1_RXD ->
|
||||
CFG_DISABLED, // SPU_UART1_RTSN ->
|
||||
CFG_DISABLED, // SPU_UART1_CTSN ->
|
||||
CFG_DISABLED, // SPU_GPIO[0] ->
|
||||
CFG_DISABLED, // SPU_GPIO[1] ->
|
||||
CFG_DISABLED, // SPU_GPIO[2] ->
|
||||
CFG_DISABLED, // SPU_GPIO[3] ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // SPU_GPIO[4] ->
|
||||
CFG_DISABLED, // SPU_GPIO[5] ->
|
||||
CFG_DISABLED, // SPU_GPIO[6] ->
|
||||
CFG_DISABLED, // SPU_GPIO[7] ->
|
||||
CFG_DISABLED, // SPU_GPIO[8] ->
|
||||
CFG_DISABLED | PULL_DOWN, // DFU_STATUS ->
|
||||
CFG_IN | PULL_DOWN, // FORCE_DFU ->
|
||||
CFG_DISABLED, // POWER_GOOD ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // SOC_VDD_HI_LO ->
|
||||
CFG_DISABLED, // SOC_VDD_ALL_ON ->
|
||||
CFG_DISABLED | PULL_DOWN, // DOCK_ATTENTION ->
|
||||
CFG_DISABLED, // PMU_HOST_WAKE ->
|
||||
CFG_DISABLED, // SPU_SPI_SCLK ->
|
||||
CFG_DISABLED, // SPU_SPI_MOSI ->
|
||||
CFG_DISABLED, // SPU_SPI_MISO ->
|
||||
CFG_DISABLED, // SPU_SPI_CS_TRIG[0] ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED, // SPU_SPI_CS_TRIG[1] ->
|
||||
CFG_DISABLED, // SPU_SPI_CS_TRIG[2] ->
|
||||
CFG_DISABLED, // SPU_SPI_CS_TRIG[3] ->
|
||||
CFG_DISABLED, // SPU_SPI_CS_TRIG[4] ->
|
||||
CFG_DISABLED, // SPU_SPI_CS_TRIG[5] ->
|
||||
CFG_DISABLED, // SPU_SPI_CS_TRIG[6] ->
|
||||
CFG_DISABLED, // SPU_SPI_CS_TRIG[7] ->
|
||||
CFG_DISABLED, // SPU_SPI_CS_TRIG[8] ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED, // SPU_SPI_CS_TRIG[9] ->
|
||||
CFG_DISABLED, // SPU_SPI_CS_TRIG[10] ->
|
||||
CFG_DISABLED, // SPU_SPI_CS_TRIG[11] ->
|
||||
CFG_DISABLED, // SPU_SPI_CS_TRIG[12] ->
|
||||
CFG_DISABLED, // SPU_SPI_CS_TRIG[13] ->
|
||||
CFG_DISABLED, // SPU_SPI_CS_TRIG[14] ->
|
||||
CFG_DISABLED, // SPU_SPI_CS_TRIG[15] ->
|
||||
CFG_DISABLED, // SPU_GPIO[9] ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED, // SPU_I2C_SDA ->
|
||||
CFG_DISABLED, // SPU_I2C_SCL ->
|
||||
CFG_DISABLED, // WDOG ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // RESETN -> RESET_L
|
||||
CFG_DISABLED, // JTAG_TRSTN ->
|
||||
CFG_DISABLED, // JTAG_SEL ->
|
||||
CFG_DISABLED, // JTAG_TCK ->
|
||||
CFG_DISABLED, // JTAG_TMS ->
|
||||
CFG_DISABLED, // JTAG_TRTCK ->
|
||||
CFG_DISABLED, // JTAG_TDO ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // JTAG_TDI ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
};
|
||||
|
||||
#endif /* ! __PLATFORM_PINCONFIG_H */
|
||||
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PL080DMAC_CONFIG_H
|
||||
#define __PL080DMAC_CONFIG_H
|
||||
|
||||
#include <drivers/primecell/pl080dmac.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <platform/soc/hwdmachannels.h>
|
||||
#include <platform/soc/hwisr.h>
|
||||
|
||||
/* LIO Integration spec contains details on PL080DMAC configuration */
|
||||
|
||||
static const struct pl080dmac_config pl080dmac_configs[PL080DMAC_COUNT] = {
|
||||
{
|
||||
CLK_DMARX,
|
||||
INT_DMA_RX_TC,
|
||||
INT_DMA_RX_ERR,
|
||||
{
|
||||
/* channel type config reg control reg fifo_address */
|
||||
{ 0x0, PL080DMAC_PERPH_SRC, 0x00001014, 0x0A489000, 0x47380080 },
|
||||
},
|
||||
},
|
||||
{
|
||||
CLK_DMATX,
|
||||
INT_DMA_TX_TC,
|
||||
INT_DMA_TX_ERR,
|
||||
{
|
||||
/* channel type config reg control reg fifo_address */
|
||||
{ 0x0, PL080DMAC_PERPH_DEST, 0x00000a80, 0x05489000, 0x47380040 },
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
#endif /* __PL080DMAC_CONFIG_H */
|
||||
|
||||
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_CHIPID_H
|
||||
#define __PLATFORM_SOC_CHIPID_H
|
||||
|
||||
#include <platform/chipid.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rCFG_FUSE0 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x00))
|
||||
#define rCFG_FUSE1 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x04))
|
||||
#define rCFG_FUSE2 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x08))
|
||||
#define rCFG_FUSE3 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x0C))
|
||||
#define rCFG_FUSE4 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x10))
|
||||
#define rCFG_FUSE5 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x14))
|
||||
|
||||
#define rECIDLO (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x80))
|
||||
#define rECIDHI (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x84))
|
||||
|
||||
#define rCFG_FUSE0_RAW (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x100))
|
||||
|
||||
uint32_t chipid_get_total_rails_leakage();
|
||||
uint32_t chipid_get_soc_voltage(uint32_t index);
|
||||
uint32_t chipid_get_fuse_revision(void);
|
||||
|
||||
#endif /* __PLATFORM_SOC_CHIPID_H */
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_H
|
||||
#define __APPLE_DISPLAY_H
|
||||
|
||||
// Platform-specific displaypipe tunables
|
||||
|
||||
static struct adfe_v2_tuneable adfe_tuneables[] =
|
||||
{
|
||||
{
|
||||
.name = "default",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x20) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x130),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x1f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x7d0) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x130),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x128),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x118),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x114),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x24) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcenab = ADPCENAB_IDEAL_ARB_ENAB,
|
||||
},
|
||||
};
|
||||
|
||||
#endif /* ! __APPLE_DISPLAY_H */
|
||||
@@ -0,0 +1,107 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_TIMINGS_H
|
||||
#define __APPLE_DISPLAY_TIMINGS_H
|
||||
|
||||
//Supported timings by this platform
|
||||
static struct display_timing timing_list[] =
|
||||
{
|
||||
#if DEBUG_BUILD || SUB_TARGET_N27 || SUB_TARGET_N28 || SUB_TARGET_N27A || SUB_TARGET_N28A || SUB_TARGET_S7002SIM
|
||||
{
|
||||
.display_name = "C1",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 6412500,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 232,
|
||||
.h_pulse_width = 2,
|
||||
.h_back_porch = 44,
|
||||
.h_front_porch = 42,
|
||||
.v_active = 288,
|
||||
.v_pulse_width = 1,
|
||||
.v_back_porch = 23,
|
||||
.v_front_porch = 22,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_SUMMIT,
|
||||
.display_config = NULL,
|
||||
},
|
||||
|
||||
{
|
||||
.display_name = "POR_DISP_S",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 22200000,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 272,
|
||||
.h_pulse_width = 8,
|
||||
.h_back_porch = 8,
|
||||
.h_front_porch = 16,
|
||||
.v_active = 340,
|
||||
.v_pulse_width = 1,
|
||||
.v_back_porch = 1,
|
||||
.v_front_porch = 43,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_SUMMIT,
|
||||
.display_config = NULL,
|
||||
},
|
||||
|
||||
{
|
||||
.display_name = "POR_DISP_B",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 22200000,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 312,
|
||||
.h_pulse_width = 8,
|
||||
.h_back_porch = 8,
|
||||
.h_front_porch = 16,
|
||||
.v_active = 390,
|
||||
.v_pulse_width = 1,
|
||||
.v_back_porch = 1,
|
||||
.v_front_porch = 38,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_SUMMIT,
|
||||
.display_config = NULL,
|
||||
},
|
||||
|
||||
{
|
||||
.display_name = "POR_DISP_B_VID",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 12000000,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 312,
|
||||
.h_pulse_width = 4,
|
||||
.h_back_porch = 102,
|
||||
.h_front_porch = 42,
|
||||
.v_active = 390,
|
||||
.v_pulse_width = 1,
|
||||
.v_back_porch = 23,
|
||||
.v_front_porch = 22,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_SUMMIT,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
#endif /* ! __APPLE_DISPLAY_TIMINGS_H */
|
||||
@@ -0,0 +1,87 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWCLOCKS_H
|
||||
#define __PLATFORM_SOC_HWCLOCKS_H
|
||||
|
||||
#include <platform/clocks.h>
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define OSC_FREQ (5000000UL)
|
||||
#else
|
||||
#define OSC_FREQ (24000000UL)
|
||||
#endif
|
||||
|
||||
// Start from an offset of 128. So that we are safely outside the PS indexes.
|
||||
#define CLK_FCLK (HWCLOCK_BASE+128)
|
||||
#define CLK_ACLK (HWCLOCK_BASE+129)
|
||||
#define CLK_HCLK (HWCLOCK_BASE+130)
|
||||
#define CLK_PCLK (HWCLOCK_BASE+131)
|
||||
#define CLK_VCLK0 (HWCLOCK_BASE+132)
|
||||
#define CLK_VCLK1 (HWCLOCK_BASE+133)
|
||||
#define CLK_MCLK (HWCLOCK_BASE+134)
|
||||
#define CLK_NCLK (HWCLOCK_BASE+135)
|
||||
#define CLK_USBPHYCLK (HWCLOCK_BASE+136)
|
||||
#define CLK_NCOREF (HWCLOCK_BASE+137)
|
||||
#define CLK_ANS_LINK (HWCLOCK_BASE+138)
|
||||
|
||||
/*
|
||||
* S7002 clock gate devices.
|
||||
* Refers to the ps register offsets.
|
||||
*/
|
||||
enum {
|
||||
CLK_CPU0,
|
||||
CLK_AIC,
|
||||
CLK_SPU,
|
||||
CLK_SPU_AKF,
|
||||
CLK_SPU_UART0,
|
||||
CLK_SPU_UART1,
|
||||
CLK_SPU_SMB,
|
||||
CLK_SPU_SGPIO,
|
||||
CLK_DOCKFIFO,
|
||||
CLK_MCU,
|
||||
CLK_AMP,
|
||||
CLK_PIOSYS,
|
||||
CLK_DISP0,
|
||||
CLK_MIPI_DSI,
|
||||
CLK_MIPI = CLK_MIPI_DSI,
|
||||
CLK_MSR,
|
||||
CLK_MEDIA,
|
||||
CLK_ANS,
|
||||
CLK_GFX,
|
||||
CLK_SDIO,
|
||||
CLK_LIO,
|
||||
CLK_GPIO,
|
||||
CLK_MCA0,
|
||||
CLK_MCA1,
|
||||
CLK_SPI0,
|
||||
CLK_SPI1,
|
||||
CLK_DMATX,
|
||||
CLK_DMARX,
|
||||
CLK_UART0,
|
||||
CLK_UART1,
|
||||
CLK_UART2,
|
||||
CLK_UART3,
|
||||
CLK_UART4,
|
||||
CLK_AES0,
|
||||
CLK_I2C0,
|
||||
CLK_I2C1,
|
||||
CLK_PWM0,
|
||||
CLK_AUE,
|
||||
CLK_USB = CLK_AUE,
|
||||
CLK_USB_M7,
|
||||
CLK_USBCTLREG = CLK_USB_M7,
|
||||
CLK_USB_OTG = CLK_USB_M7,
|
||||
CLK_ETH,
|
||||
CLK_VDEC,
|
||||
PMGR_LAST_DEVICE,
|
||||
};
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWCLOCKS_H */
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWDMACHANNELS_H
|
||||
#define __PLATFORM_SOC_HWDMACHANNELS_H
|
||||
|
||||
#define DMA_AES_RD (0)
|
||||
#define DMA_AES_WR ((1 << DMA_SELECTOR_SHIFT) | (0))
|
||||
|
||||
#define DMA_SELECTOR_SHIFT (4)
|
||||
#define DMA_SELECTOR_MASK (0xf)
|
||||
#define DMA_CHANNEL_MASK (0xf)
|
||||
|
||||
#define PL080DMAC_SUPPORTED_CHANNEL_COUNT (1)
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWDMACHANNELS_H */
|
||||
@@ -0,0 +1,159 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWISR_H
|
||||
#define __PLATFORM_SOC_HWISR_H
|
||||
|
||||
#define INT_SW0 0 // Software 0 Interrupt
|
||||
#define INT_SW1 1 // Software 1 Interrupt
|
||||
#define INT_SW2 2 // Software 2 Interrupt
|
||||
#define INT_SW3 3 // Software 3 Interrupt
|
||||
|
||||
// Reserved 4
|
||||
|
||||
#define INT_WDT 5 // Watchdog Timer Interrupt
|
||||
|
||||
// Reserved 6
|
||||
|
||||
#define INT_ANS_KF_INBOX_EMPTY 7 // ANS KF Inbox Empty Interrupt
|
||||
#define INT_ANS_KF_INBOX_NOTEMPTY 8 // ANS KF Inbox Not Empty Interrupt
|
||||
#define INT_ANS_KF_OUTBOX_EMPTY 9 // ANS KF Outbox Empty Interrupt
|
||||
#define INT_ANS_KF_OUTBOX_NOTEMPTY 10 // ANS KF Outbox Not Empty Interrupt
|
||||
#define INT_ANS_CHNL0 11 // ANS Channel 0 Interrupt
|
||||
|
||||
// Reserved 12
|
||||
|
||||
#define INT_ENET 13
|
||||
|
||||
#define INT_USB_OTG 14 // USB OTG Interrupt
|
||||
#define INT_USB_20_BATT_CHRG_DET 15 // USB 2.0 Battery Charge Detect Interrupt
|
||||
#define INT_USBOTG_RESUME 16 // USB OTG Resume Interrupt
|
||||
|
||||
// Reserved 17
|
||||
|
||||
#define INT_GPIO_CLASS0 18 // GPIO Class 0 Interrupt
|
||||
#define INT_GPIO_CLASS1 19 // GPIO Class 1 Interrupt
|
||||
#define INT_GPIO_CLASS2 20 // GPIO Class 2 Interrupt
|
||||
#define INT_GPIO_CLASS3 21 // GPIO Class 3 Interrupt
|
||||
#define INT_GPIO_CLASS4 22 // GPIO Class 4 Interrupt
|
||||
#define INT_GPIO_CLASS5 23 // GPIO Class 5 Interrupt
|
||||
#define INT_GPIO_CLASS6 24 // GPIO Class 6 Interrupt
|
||||
|
||||
// Reserved 25
|
||||
|
||||
#define INT_MEM_CONTROLLER 26 // Memory Controller Interrupt
|
||||
|
||||
// Reserved 27
|
||||
|
||||
#define INT_CPU0_PMU_IRQ 28 // CPU 0 PMU IRQ Interrupt
|
||||
#define INT_CPU0_CTI_IRQ 29 // CPU 0 CTI Interrupt
|
||||
#define INT_CPU0_COMM_TX 30 // CPU 0 COMM TX Interrupt
|
||||
#define INT_CPU0_COMM_RX 31 // CPU 0 COMM RX Interrupt
|
||||
#define INT_CPU0_AXI_ERR_IRQ 32 // CPU 0 AXI Error IRQ Interrupt
|
||||
#define INT_CPU0_CX_ETB_FUKK 33 // CPU 0 CXETB Full Interrupt
|
||||
|
||||
#define INT_DISP0 35 // Display Interrupt
|
||||
|
||||
// Reserved 46
|
||||
|
||||
#define INT_DISP_DART 37 // Display DART Interrupt
|
||||
#define INT_DISP_SMMU 38 // Display SMMU Interrupt
|
||||
#define INT_DISP_BACK_END_VBI 39 // Display Back End VBI Interrupt
|
||||
#define INT_DISP_BACK_END_VFTG_IDLE 40 // Display Back End VFTG Idle Interrupt
|
||||
#define INT_DISP_BACK_END_VBL_CNTR 41 // Display Back End VBL Counter Interrupt
|
||||
#define INT_MIPIDSI 42 // MIPI DSI Interrupt
|
||||
|
||||
// Reserved 43
|
||||
|
||||
#define INT_GFX 44 // GFX Interrupt
|
||||
|
||||
// Reserved 45-46
|
||||
|
||||
#define INT_MSR 47 // MSR Interrupt
|
||||
#define INT_MSR_SMMU 48 // MSR SMMU Interrupt
|
||||
#define INT_MSR_DART 49 // MSR DART Interrupt
|
||||
#define INT_MSR_SMMU_PERF 50 // MSR SMMU Performance Interrupt
|
||||
#define INT_MSR_DART_PERF 51 // MSR DART Performance Interrupt
|
||||
|
||||
// Reserved 52
|
||||
|
||||
#define INT_PIO 53 // PIO IRQ
|
||||
|
||||
// Reserved 54
|
||||
|
||||
#define INT_DMA_RX_TC 55 // DMA Rx Transfer Complete Interrupt
|
||||
#define INT_DMA_RX_ERR 56 // DMA Rx Error Interrupt
|
||||
#define INT_DMA_TX_TC 57 // DMA Tx Transfer Complete Interrupt
|
||||
#define INT_DMA_TX_ERR 58 // DMA Tx Error Interrupt
|
||||
|
||||
// Reserved 59
|
||||
|
||||
#define INT_SPI0 60 // SPI 0 Interrupt
|
||||
#define INT_SPI1 61 // SPI 1 Interrupt
|
||||
|
||||
// Reserved 62
|
||||
|
||||
#define INT_UART0 63 // UART 0 Interrupt
|
||||
#define INT_UART1 64 // UART 1 Interrupt
|
||||
#define INT_UART2 65 // UART 2 Interrupt
|
||||
#define INT_UART3 66 // UART 3 Interrupt
|
||||
#define INT_UART4 67 // UART 4 Interrupt
|
||||
|
||||
// Reserved 68
|
||||
|
||||
#define INT_PWM0 69 // PWM0 Interrupt
|
||||
|
||||
// Reserved 70
|
||||
|
||||
#define INT_MCA0 71 // Multi-Channel Audio 0 Interrupt
|
||||
#define INT_MCA1 72 // Multi-Channel Audio 1 Interrupt
|
||||
|
||||
// Reserved 73
|
||||
|
||||
#define INT_IIC0 74 // I2C 0 Interrupt
|
||||
#define INT_IIC1 75 // I2C 1 Interrupt
|
||||
|
||||
// Reserved 76
|
||||
|
||||
#define INT_AES 77 // AES Interrupt
|
||||
|
||||
// Reserved 78
|
||||
|
||||
#define INT_VDEC 79 // Video Decoder
|
||||
|
||||
// Reserved 80
|
||||
|
||||
#define INT_SDIO_KF_INBOX_EMPTY 81 // ANS KF Inbox Empty Interrupt
|
||||
#define INT_SDIO_KF_INBOX_NOTEMPTY 82 // ANS KF Inbox Not Empty Interrupt
|
||||
#define INT_SDIO_KF_OUTBOX_EMPTY 83 // ANS KF Outbox Empty Interrupt
|
||||
#define INT_SDIO_KF_OUTBOX_NOTEMPTY 84 // ANS KF Outbox Not Empty Interrupt
|
||||
#define INT_SDIO_SDHC_WAKEUP 85 // SDIO SDHC Wakeup
|
||||
#define INT_SDIO_SDHC_INT 86 // SDIO SDHC Tnterrupt
|
||||
#define INT_SDIO_CARD_INT 87 // SDIO SDHC Interrupt
|
||||
#define INT_SDIO_IRQ 88 // SDIO IRQ
|
||||
#define INT_SDIO_WL_HOST_WAKE_INT 89 // SDIO Host Wake Interrupt
|
||||
|
||||
// Reserved 90
|
||||
|
||||
// 91 - 117 SPU interrupts
|
||||
|
||||
#define DBGFIFO_0_NOT_EMPTY 118 // DebugFifo 0 Not Empty Interrupt
|
||||
#define DBGFIFO_1_NOT_EMPTY 119 // DebugFifo 1 Not Empty Interrupt
|
||||
#define DBGFIFO_2_NOT_EMPTY 120 // DebugFifo 2 Not Empty Interrupt
|
||||
#define DBGFIFO_3_NOT_EMPTY 121 // DebugFifo 3 Not Empty Interrupt
|
||||
#define DBGFIFO_4_NOT_EMPTY 122 // DebugFifo 4 Not Empty Interrupt
|
||||
#define DBGFIFO_5_NOT_EMPTY 123 // DebugFifo 5 Not Empty Interrupt
|
||||
#define DBGFIFO_6_NOT_EMPTY 124 // DebugFifo 6 Not Empty Interrupt
|
||||
#define DBGFIFO_7_NOT_EMPTY 125 // DebugFifo 7 Not Empty Interrupt
|
||||
|
||||
// Reserved 126 - 127
|
||||
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWISR_H */
|
||||
@@ -0,0 +1,188 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWREGBASE_H
|
||||
#define __PLATFORM_SOC_HWREGBASE_H
|
||||
|
||||
#include <platform/memmap.h>
|
||||
|
||||
/* S7002 Reg Base Defs */
|
||||
|
||||
// Memory Subsystem
|
||||
#define SECUREROM_BASE_ADDR (IO_BASE + 0x00000000) // SecureROM access through PIO
|
||||
#define PIO_BASE_ADDR (IO_BASE + 0x00100000) // PIO Config
|
||||
#define CPU_FABRIC_BASE_ADDR (IO_BASE + 0x00101000) // PL301 Config
|
||||
#define NRT_FABRIC_BASE_ADDR (IO_BASE + 0x00102000) // PL301 Config
|
||||
#define CPU_BASE_ADDR (IO_BASE + 0x00103000) // AP Config
|
||||
#define AMC_BASE_ADDR (IO_BASE + 0x00200000) // AMC Config
|
||||
#define AMPS_DQ_BASE_ADDR (IO_BASE + 0x00300000) // AMP DQ DRAM Phy
|
||||
#define AMPS_CA_BASE_ADDR (IO_BASE + 0x00310000) // AMP CA DRAM Phy
|
||||
|
||||
// MSR Subsystem
|
||||
#define MSR_BASE_ADDR (IO_BASE + 0x01000000) // MSR Config
|
||||
#define MSR_SMMU_BASE_ADDR (IO_BASE + 0x01004000) // MSR SMMU
|
||||
#define MSR_DART_BASE_ADDR (IO_BASE + 0x01008000) // MSR DART
|
||||
#define VDEC_BASE_ADDR (IO_BASE + 0x02000000) // VXD394 Video Decoder
|
||||
#define SGX544_SC_BASE_ADDR (IO_BASE + 0x02800000) // SGX544-SC Space
|
||||
|
||||
// Display Subsystem
|
||||
#define DISP_ADP_BASE_ADDR (IO_BASE + 0x03200000) // Display pipe configuration
|
||||
#define DISP0_BASE_ADDR DISP_ADP_BASE_ADDR
|
||||
#define DISP_ADP_SMMU_BASE_ADDR (IO_BASE + 0x03300000) // Display pipe SMMU configuration
|
||||
#define DISP_ADE_BASE_ADDR (IO_BASE + 0x03400000) // DBE Timing controller
|
||||
#define DISP0_ADBE_BASE_ADDR DISP_ADE_BASE_ADDR
|
||||
#define DISP_AAP_BASE_ADDR (IO_BASE + 0x03440000) // DBE Ambient-Adaptive Pixel
|
||||
#define DISP_DITHER_BASE_ADDR (IO_BASE + 0x034C0000) // DBE Dither
|
||||
#define DISP_MIPI_DSI_BASE_ADDR (IO_BASE + 0x03600000) // MIPI DSI Core configuration
|
||||
|
||||
// ANS Subsystem
|
||||
#define ANS_PL301_BASE_ADDR (IO_BASE + 0x04010000) // ANS PL301 Configuration
|
||||
#define ANS_PL301_TLIMIT0_BASE_ADDR (IO_BASE + 0x04020000) // ANS Cortex-A7 Transaction Limit
|
||||
#define ANS_PL301_TLIMIT1_BASE_ADDR (IO_BASE + 0x04030000) // ANS NAND controoler Transaction Limit
|
||||
#define ANS_AKF_BASE_ADDR (IO_BASE + 0x04040000) // ANS Cortex-A7 and wrapper
|
||||
// ANS KF Debug registers
|
||||
#define ANS_CFG_BASE_ADDR (IO_BASE + 0x04080000) // ANS Config
|
||||
#define ANS_PPN_N_PL_BASE_ADDR (IO_BASE + 0x04081000)
|
||||
#define ANS_ANC_BASE_ADDR (IO_BASE + 0x04800000) // NAND Controller
|
||||
|
||||
// SDIO Subsystem
|
||||
#define SDIO_PL301_BASE_ADDR (IO_BASE + 0x05010000) // SDIO PL301 Configuration
|
||||
#define SDIO_PL301_TLIMIT0_BASE_ADDR (IO_BASE + 0x05020000) // SDIO Cortex-A7 Transaction Limit
|
||||
#define SDIO_PL301_TLIMIT1_BASE_ADDR (IO_BASE + 0x05030000) // SDIO controller Transaction Limit
|
||||
#define SDIO_AKF_BASE_ADDR (IO_BASE + 0x05040000) // SDIO Cortex-A7 and wrapper
|
||||
// SDIO KF Debug registers
|
||||
#define SDIO_CFG_BASE_ADDR (IO_BASE + 0x05080000) // SDIO Config
|
||||
|
||||
// SPU Subsystem
|
||||
#define SPU_SRAM_A_BASE_ADDR (IO_BASE + 0x06000000) // SPU Local SRAM-A
|
||||
#define SPU_SRAM_B_BASE_ADDR (IO_BASE + 0x06040000) // SPU Local SRAM-B
|
||||
#define SPU_SRAM_SIZE (0x48000) // SPU SRAM size is 288 KB
|
||||
#define SPU_CPU_PL301_BASE_ADDR (IO_BASE + 0x06410000) // SPU CPU PL301 Configuration
|
||||
#define SPU_SRAM_PL301_BASE_ADDR (IO_BASE + 0x06411000) // SPU SRAM PL301 Configuration
|
||||
#define SPU_MEM_PL301_BASE_ADDR (IO_BASE + 0x06412000) // SPU MEM PL301 Configuration
|
||||
#define SPU_AKF_BASE_ADDR (IO_BASE + 0x06500000) // SPU Cortex-A7 and wrapper
|
||||
// SPU KF Debug registers
|
||||
#define SPU_SPI_BASE_ADDR (IO_BASE + 0x06600000) // SPU SPI Device
|
||||
#define SPU_SEQUENCER_BASE_ADDR (IO_BASE + 0x06700000) // SPU Sequencer configuration
|
||||
#define SPU_SMB_BASE_ADDR (IO_BASE + 0x06800000) // SPU I2C
|
||||
#define SPU_GPIO_BASE_ADDR (IO_BASE + 0x06810000) // SPU GPIO
|
||||
#define SPU_UART_BASE_ADDR (IO_BASE + 0x06820000) // SPU UART
|
||||
#define SPU_SOC_RECONFIG_BASE_ADDR (IO_BASE + 0x06900000) // SPU SOC ReConfig
|
||||
#define SPU_AIC_WRAP_BASE_ADDR (IO_BASE + 0x06A00000) // AIC
|
||||
#define SPU_AIC_BASE_ADDR (IO_BASE + 0x06B00000) // AIC
|
||||
#define SPU_PMGR_BASE_ADDR (IO_BASE + 0x06C00000) // PMGR
|
||||
#define SPU_DBG_FIFO_0_BASE_ADDR (IO_BASE + 0x06E00000) // Debug FIFO [0] registers
|
||||
#define SPU_DBG_FIFO_1_BASE_ADDR (IO_BASE + 0x06E03000) // Debug FIFO [1] registers
|
||||
#define SPU_DBG_FIFO_2_BASE_ADDR (IO_BASE + 0x06E06000) // Debug FIFO [2] registers
|
||||
#define SPU_DBG_FIFO_3_BASE_ADDR (IO_BASE + 0x06E09000) // Debug FIFO [3] registers
|
||||
#define SPU_DBG_FIFO_4_BASE_ADDR (IO_BASE + 0x06E0C000) // Debug FIFO [4] registers
|
||||
#define SPU_DBG_FIFO_5_BASE_ADDR (IO_BASE + 0x06E0F000) // Debug FIFO [5] registers
|
||||
#define SPU_DBG_FIFO_6_BASE_ADDR (IO_BASE + 0x06E12000) // Debug FIFO [6] registers
|
||||
#define SPU_DBG_FIFO_7_BASE_ADDR (IO_BASE + 0x06E15000) // Debug FIFO [7] registers
|
||||
#define SPU_DBG_WRAP_BASE_ADDR (IO_BASE + 0x06EB0000) // Debug sub-system config space
|
||||
|
||||
// LIO Subsystem
|
||||
#define LIO_MISC_BASE_ADDR (IO_BASE + 0x07000000) // Miscellaneous registers
|
||||
#define LIO_AUD_MUX_BASE_ADDR (IO_BASE + 0x07004000) // Audio I2S Switch registers
|
||||
#define LIO_PWM_BASE_ADDR (IO_BASE + 0x07010000) // PWM Device registers
|
||||
#define LIO_SMB_0_BASE_ADDR (IO_BASE + 0x07020000) // I2C Device registers
|
||||
#define LIO_GPIO_BASE_ADDR (IO_BASE + 0x07100000) // GPIO
|
||||
#define LIO_SPI_BASE_ADDR (IO_BASE + 0x07200000) // SPI Device registers
|
||||
#define LIO_UART_BASE_ADDR (IO_BASE + 0x07230000) // UART Device registers
|
||||
#define LIO_MCA_BASE_ADDR (IO_BASE + 0x07240000) // MCA Device registers
|
||||
#define LIO_DMAC_BASE_ADDR (IO_BASE + 0x07300000) // PL080 DMAC registers
|
||||
#define LIO_AES_BASE_ADDR (IO_BASE + 0x07380000) // AES
|
||||
|
||||
// AUE Subsystem
|
||||
#define AUE_USBCONT_BASE_ADDR (IO_BASE + 0x08000000) // USB Control
|
||||
#define AUE_USBOTG_BASE_ADDR (IO_BASE + 0x08100000) // USBOTG
|
||||
#define AUE_AUSB_WIDGETS_BASE_ADDR (IO_BASE + 0x08200000) // AUSB Widgets
|
||||
#define AUE_AUSB_AFIFO_WDGTS_BASE_ADDR (IO_BASE + 0x08300000) // AUSB Async Fifo Widgets
|
||||
#define AUE_PL301_BASE_ADDR (IO_BASE + 0x08800000) // AUE PL301 Configuration
|
||||
|
||||
/* iBoot Specific Defs */
|
||||
|
||||
#define AKF_VERSION (1)
|
||||
|
||||
#define UART0_BASE_ADDR (LIO_UART_BASE_ADDR)
|
||||
#define UART1_BASE_ADDR (LIO_UART_BASE_ADDR + 0x04000)
|
||||
#define UART2_BASE_ADDR (LIO_UART_BASE_ADDR + 0x08000)
|
||||
#define UART3_BASE_ADDR (LIO_UART_BASE_ADDR + 0x0C000)
|
||||
#define UART4_BASE_ADDR (LIO_UART_BASE_ADDR + 0x10000)
|
||||
#define UARTS_COUNT (5)
|
||||
#define UART_VERSION (1)
|
||||
|
||||
#define SPI0_BASE_ADDR (LIO_SPI_BASE_ADDR)
|
||||
#define SPI1_BASE_ADDR (LIO_SPI_BASE_ADDR + 0x04000)
|
||||
#define SPI_VERSION (1)
|
||||
#define SPIS_COUNT (2)
|
||||
|
||||
#define IIC_BASE_ADDR (LIO_SMB_0_BASE_ADDR)
|
||||
#define IIC_SPACING (0x00004000)
|
||||
#define IICS_COUNT (2)
|
||||
|
||||
#define DSIM_BASE_ADDR (DISP_MIPI_DSI_BASE_ADDR)
|
||||
#define DSIM_LANE_COUNT (1)
|
||||
#define DSIM_VERSION (3)
|
||||
|
||||
#define ADBE_DISPLAYPIPE_BASE_ADDR (DISP0_BASE_ADDR)
|
||||
#define DISP_VERSION (5)
|
||||
#define ADP_VERSION (1)
|
||||
|
||||
#define AMP_BASE_ADDR (AMPS_DQ_BASE_ADDR)
|
||||
#define AMP_SPACING (0)
|
||||
#define AMP_CA_SPACING (0x00010000)
|
||||
|
||||
#if !CONFIG_SIM
|
||||
#define AMP_REG_OFFSET (4)
|
||||
#else
|
||||
// FIXME M7 fastsim has an Alcatraz-y AMP until <rdar://problem/15464244> M7: update AMC/AMP for M7
|
||||
#define AMP_REG_OFFSET (0)
|
||||
#endif
|
||||
|
||||
#define PMGR_BASE_ADDR (SPU_PMGR_BASE_ADDR)
|
||||
#define CHIPID_BASE_ADDR (PMGR_BASE_ADDR + 0x2A000)
|
||||
#define PMGR_WDG_VERSION (1)
|
||||
|
||||
#define GPIOC_COUNT (2)
|
||||
#define GPIO_VERSION (4)
|
||||
#define GPIO_BASE_ADDR (LIO_GPIO_BASE_ADDR)
|
||||
#define GPIO_0_GROUP_COUNT (18)
|
||||
#define GPIO_GROUP_COUNT (GPIO_0_GROUP_COUNT)
|
||||
#define GPIO_1_BASE_ADDR (SPU_GPIO_BASE_ADDR)
|
||||
#define GPIO_1_GROUP_COUNT (10)
|
||||
#define GPIO_AP (GPIOC_0)
|
||||
#define GPIO_SPU (GPIOC_1)
|
||||
|
||||
#define AIC_BASE_ADDR (SPU_AIC_BASE_ADDR)
|
||||
#define AIC_VERSION (1)
|
||||
#define AIC_INT_COUNT (192)
|
||||
|
||||
#define PL080DMAC_BASE_ADDR (LIO_DMAC_BASE_ADDR)
|
||||
#define PL080DMAC_SPACING (0x4000)
|
||||
#define PL080DMAC_COUNT (2)
|
||||
#define PL080DMAC_CHANNEL_COUNT (8)
|
||||
|
||||
#define USBOTG_BASE_ADDR (AUE_USBOTG_BASE_ADDR)
|
||||
#define AUSB_CTL_REG_BASE_ADDR (AUE_USBCONT_BASE_ADDR)
|
||||
#define AUSB_CTL_USB20PHY_REG_OFFSET (0x30)
|
||||
#define AUSB_USB20PHY_ONLY_VERSION (1)
|
||||
#define AUSB_PL301_WIDGET_BASE_ADDR (AUE_PL301_BASE_ADDR)
|
||||
|
||||
#define AES_S7002_BASE_ADDR (LIO_AES_BASE_ADDR)
|
||||
#define AES_S7002_VERSION (1)
|
||||
|
||||
#define DBGFIFO_0_BASE_ADDR (SPU_DBG_FIFO_0_BASE_ADDR)
|
||||
#define DBGFIFO_SPACING (0x3000)
|
||||
#define DBGFIFO_COUNT (8)
|
||||
|
||||
#define RECONFIG_RAM_SIZE_IN_WORDS (1024)
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWREGBASE_H */
|
||||
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_MIU_H
|
||||
#define __PLATFORM_SOC_MIU_H
|
||||
|
||||
#include <lib/devicetree.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
// CPU Fabric Widget Registers (base address @ CPU_FABRIC_BASE_ADDR)
|
||||
#define CPU_Fabric_pl301Wrap0_AMCRDRATELIMIT (0x0000) // AMC Read Rate Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_AMCWRALIMIT (0x0004) // AMC Write Rate Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_AMCRTRLIMIT (0x0008) // AMC Read Transactions Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_AMCWTRLIMIT (0x000c) // AMC Write Transactions Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_SPURDRATELIMIT (0x0040) // SPU Read Rate Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_SPUWRALIMIT (0x0044) // SPU Write Rate Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_SPURTRLIMIT (0x0048) // SPU Read Transactions Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_SPUWTRLIMIT (0x004c) // SPU Write Transactions Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_SPUWGATHER (0x0050) // SPU Write Gather Register
|
||||
#define CPU_Fabric_pl301Wrap0_LIOWGATHER (0x0090) // LIO Write Gather Register
|
||||
#define CPU_Fabric_pl301Wrap0_AUERDRATELIMIT (0x00c0) // AUE Read Rate Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_AUEWRALIMIT (0x00c4) // AUE Write Rate Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_AUERTRLIMIT (0x00c8) // AUE Read Transactions Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_AUEWTRLIMIT (0x00cc) // AUE Write Transactions Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_AUEWGATHER (0x00d0) // AUE Write Gather Register
|
||||
#define CPU_Fabric_pl301Wrap0_ANSRDRATELIMIT (0x0100) // ANS Read Rate Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_ANSWRALIMIT (0x0104) // ANS Write Rate Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_ANSRTRLIMIT (0x0108) // ANS Read Transactions Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_ANSWTRLIMIT (0x010c) // ANS Write Transactions Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_ANSWGATHER (0x0110) // ANS Write Gather Register
|
||||
#define CPU_Fabric_pl301Wrap0_AXI0_ARCHANARBMI0 (0x0408) // Configured AR channel arbitration value for MI 0
|
||||
|
||||
// NRT Fabric Widget Registers (base address @ NRT_FABRIC_BASE_ADDR)
|
||||
#define NRT_Fabric_pl301Wrap1_AMCRDRATELIMIT (0x0000) // AMC Read Rate Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_AMCWRALIMIT (0x0004) // AMC Write Rate Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_AMCRTRLIMIT (0x0008) // AMC Read Transactions Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_AMCWTRLIMIT (0x000c) // AMC Write Transactions Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_MSRRDRATELIMIT (0x0040) // MSR Read Rate Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_MSRWRALIMIT (0x0044) // MSR Write Rate Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_MSRRTRLIMIT (0x0048) // MSR Read Transactions Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_MSRWTRLIMIT (0x004c) // MSR Write Transactions Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_SDIORDRATELIMIT (0x0080) // SDIO Read Rate Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_SDIOWRALIMIT (0x0084) // SDIO Write Rate Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_SDIORTRLIMIT (0x0088) // SDIO Read Transactions Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_SDIOWTRLIMIT (0x008c) // SDIO Write Transactions Limit Register
|
||||
|
||||
#define rFABRIC_REMAP_REG *(volatile uint32_t *)(PMGR_BASE_ADDR + 0x31000)
|
||||
#define rPIO_REMAP_CTL *(volatile uint32_t *)(PIO_BASE_ADDR + 0x00)
|
||||
|
||||
enum remap_select {
|
||||
REMAP_SRAM = 1,
|
||||
REMAP_SDRAM
|
||||
};
|
||||
|
||||
extern void miu_select_remap(enum remap_select sel);
|
||||
extern void miu_bypass_prep(void);
|
||||
extern void miu_update_device_tree(DTNode *pmgr_node);
|
||||
extern void miu_configure_bridge_soc_reconfig_ram(void);
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_MIU_H */
|
||||
@@ -0,0 +1,300 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_PMGR_H
|
||||
#define __PLATFORM_SOC_PMGR_H
|
||||
|
||||
#include <lib/devicetree.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
enum {
|
||||
PMGR_CLK_OSC = 0,
|
||||
PMGR_CLK_PLL0,
|
||||
PMGR_CLK_GPIO,
|
||||
PMGR_CLK_SOURCE_FIRST = PMGR_CLK_GPIO,
|
||||
PMGR_CLK_MCU,
|
||||
PMGR_CLK_MCU_FIXED,
|
||||
PMGR_CLK_GFX,
|
||||
PMGR_CLK_MIPI_DSI,
|
||||
PMGR_CLK_VID,
|
||||
PMGR_CLK_MEDIA,
|
||||
PMGR_CLK_DISP,
|
||||
PMGR_CLK_SDIO,
|
||||
PMGR_CLK_ANS,
|
||||
PMGR_CLK_PIO,
|
||||
PMGR_CLK_LIO,
|
||||
PMGR_CLK_AUE,
|
||||
PMGR_CLK_USB,
|
||||
PMGR_CLK_SPI0_N,
|
||||
PMGR_CLK_SPI1_N,
|
||||
PMGR_CLK_NCO_REF0,
|
||||
PMGR_CLK_NCO_REF1,
|
||||
PMGR_CLK_NCO_ALG0,
|
||||
PMGR_CLK_NCO_ALG1,
|
||||
PMGR_CLK_MCA0_M,
|
||||
PMGR_CLK_MCA1_M,
|
||||
PMGR_CLK_SOURCE_LAST = PMGR_CLK_MCA1_M,
|
||||
PMGR_CLK_S0,
|
||||
PMGR_CLK_S1,
|
||||
PMGR_CLK_COUNT,
|
||||
PMGR_CLK_NOT_SUPPORTED
|
||||
};
|
||||
|
||||
#define PMGR_CLK_CFG_INDEX(_clk) ((_clk) - PMGR_CLK_GPIO)
|
||||
|
||||
// PLL Config Regs
|
||||
#define rPMGR_PLL0_CTL (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x0000))
|
||||
#define PMGR_PLL_ENABLE (1 << 31)
|
||||
#define PMGR_PLL_LOAD (1 << 29)
|
||||
#define PMGR_PLL_PENDING (1 << 25)
|
||||
#define PMGR_PLL_M_SHIFT (12)
|
||||
#define PMGR_PLL_M_MASK (0x1FF)
|
||||
#define PMGR_PLL_P_SHIFT (4)
|
||||
#define PMGR_PLL_P_MASK (0x1F)
|
||||
#define PMGR_PLL_S_SHIFT (0)
|
||||
#define PMGR_PLL_S_MASK (0xF)
|
||||
#define PMGR_PLL_M(_m) (((_m) & PMGR_PLL_M_MASK) << PMGR_PLL_M_SHIFT)
|
||||
#define PMGR_PLL_P(_p) (((_p) & PMGR_PLL_P_MASK) << PMGR_PLL_P_SHIFT)
|
||||
#define PMGR_PLL_S(_s) (((_s) & PMGR_PLL_S_MASK) << PMGR_PLL_S_SHIFT)
|
||||
#define PMGR_PLL_FREQ(_m, _p, _s) ((((_m) * OSC_FREQ) / (_p))/((_s) + 1))
|
||||
|
||||
#define rPMGR_PLL0_EXT_BYPASS_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x0004))
|
||||
#define PMGR_PLL_BYP_ENABLED (1 << 31)
|
||||
#define PMGR_PLL_PLL_ENABLED (1 << 30)
|
||||
#define PMGR_PLL_EXT_BYPASS (1 << 0)
|
||||
|
||||
#define rPMGR_PLL0_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x0008))
|
||||
#define rPMGR_PLL0_ANA_PARAMS0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x000c))
|
||||
#define rPMGR_PLL0_ANA_PARAMS1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x0010))
|
||||
//#define rPMGR_PLL0_FD_CTL (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x0014))
|
||||
//#define rPMGR_PLL0_FRAC (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x0018))
|
||||
//#define rPMGR_PLL0_DEBUG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x001c))
|
||||
//#define rPMGR_PLL0_DEBUG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x0020))
|
||||
#define rPMGR_PLL0_PLL_DELAY_CTL0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x0024))
|
||||
#define rPMGR_PLL0_PLL_DELAY_CTL1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x0028))
|
||||
|
||||
// General Clocks Config Regs
|
||||
#define rPMGR_GPIO_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10000))
|
||||
#define rPMGR_MCU_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10004))
|
||||
#define rPMGR_MCU_FIXED_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10008))
|
||||
#define rPMGR_GFX_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x1000c))
|
||||
#define rPMGR_MIPI_DSI_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10010))
|
||||
#define rPMGR_VID_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10014))
|
||||
#define PMGR_MEDIA_CLK_CFG (0x10018)
|
||||
#define rPMGR_MEDIA_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_MEDIA_CLK_CFG))
|
||||
#define rPMGR_DISP_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x1001c))
|
||||
#define rPMGR_SDIO_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10020))
|
||||
#define rPMGR_ANS_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10024))
|
||||
#define rPMGR_PIO_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10028))
|
||||
#define rPMGR_LIO_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x1002c))
|
||||
#define rPMGR_AUE_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10030))
|
||||
#define rPMGR_USB_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10034))
|
||||
#define rPMGR_SPI0_N_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10038))
|
||||
#define rPMGR_SPI1_N_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x1003c))
|
||||
#define rPMGR_NCO_REF0_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10040))
|
||||
#define rPMGR_NCO_REF1_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10044))
|
||||
#define rPMGR_NCO_ALG0_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10048))
|
||||
#define rPMGR_NCO_ALG1_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x1004c))
|
||||
#define rPMGR_MCA0_M_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10050))
|
||||
#define rPMGR_MCA1_M_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10054))
|
||||
|
||||
#define PMGR_FIRST_CLK_CFG (&rPMGR_GPIO_CLK_CFG)
|
||||
#define PMGR_LAST_CLK_CFG (&rPMGR_MCA1_M_CLK_CFG)
|
||||
#define PMGR_CLK_CFG_COUNT (((((void *)(PMGR_LAST_CLK_CFG)) - ((void *)(PMGR_FIRST_CLK_CFG))) / 4) + 1)
|
||||
#define PMGR_CLK_NUM(_r) (((void *)&(rPMGR_ ## _r ## _CLK_CFG) - ((void *)(PMGR_FIRST_CLK_CFG))) / 4)
|
||||
|
||||
// Spare Clocks Config Regs
|
||||
#define rPMGR_S0_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10200))
|
||||
#define rPMGR_S1_CLK_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10204))
|
||||
|
||||
#define PMGR_FIRST_SPARE_CLK_CFG (&rPMGR_S0_CLK_CFG)
|
||||
#define PMGR_LAST_SPARE_CLK_CFG (&rPMGR_S1_CLK_CFG)
|
||||
#define PMGR_SPARE_CLK_CFG_COUNT (((((void *)(PMGR_LAST_SPARE_CLK_CFG)) - ((void *)(PMGR_FIRST_SPARE_CLK_CFG))) / 4) + 1)
|
||||
#define PMGR_SPARE_CLK_NUM(_r) (((void *)&(rPMGR_ ## _r ## _CLK_CFG) - ((void *)(PMGR_FIRST_SPARE_CLK_CFG))) / 4)
|
||||
|
||||
// CLK_CFG Bits
|
||||
#define PMGR_CLK_CFG_ENABLE (1 << 31)
|
||||
#define PMGR_CLK_CFG_PENDING (1 << 30)
|
||||
#define PMGR_CLK_CFG_PENDING_SHIFT (30)
|
||||
#define PMGR_CLK_CFG_SRC_SEL_MASK (0x3F)
|
||||
#define PMGR_CLK_CFG_CFG_SEL_SHIFT (16)
|
||||
#define PMGR_CLK_CFG_SRC_SEL_SHIFT (24)
|
||||
#define PMGR_CLK_CFG_SRC_SEL(_n) ((_n) << PMGR_CLK_CFG_SRC_SEL_SHIFT)
|
||||
#define PMGR_CLK_CFG_DIVISOR_MASK (0x3F)
|
||||
#define PMGR_CLK_CFG_DIVISOR(_n) ((_n) << 0)
|
||||
|
||||
// NCO Config block
|
||||
#define rPMGR_NCO_CLK_CFG(_n) (*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * 0x1000 + 0x11000 + 0x0))
|
||||
|
||||
// Misc Clock Tree Power Saving Regs
|
||||
#define rPMGR_CLK_DIVIDER_ACG_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10300))
|
||||
#define rPMGR_CLK_POWER_CONFIG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x10304))
|
||||
|
||||
//PERF_STATE
|
||||
#define rPMGR_SOC_PERF_STATE_CTL (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x1a000))
|
||||
|
||||
// Power State Regs
|
||||
#define rPMGR_CPU_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20000))
|
||||
#define rPMGR_AIC_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20008))
|
||||
#define rPMGR_SPU_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20010))
|
||||
#define rPMGR_SPU_AKF_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20018))
|
||||
#define rPMGR_SPU_UART0_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20020))
|
||||
#define rPMGR_SPU_UART1_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20028))
|
||||
#define rPMGR_SPU_SMB_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20030))
|
||||
#define rPMGR_SPU_SGPIO_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20038))
|
||||
#define rPMGR_DOCKFIFO_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20040))
|
||||
#define rPMGR_MCU_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20048))
|
||||
#define rPMGR_AMP_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20050))
|
||||
#define rPMGR_PIOSYS_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20058))
|
||||
#define rPMGR_DISP_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20060))
|
||||
#define rPMGR_MIPI_DSI_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20068))
|
||||
#define PMGR_MSR_PS (0x20070)
|
||||
#define rPMGR_MSR_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_MSR_PS))
|
||||
#define rPMGR_MEDIA_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20078))
|
||||
#define rPMGR_ANS_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20080))
|
||||
#define rPMGR_GFX_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20088))
|
||||
#define rPMGR_SDIO_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20090))
|
||||
#define rPMGR_LIO_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20098))
|
||||
#define rPMGR_GPIO_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x200a0))
|
||||
#define rPMGR_MCA0_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x200a8))
|
||||
#define rPMGR_MCA1_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x200b0))
|
||||
#define rPMGR_SPI0_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x200b8))
|
||||
#define rPMGR_SPI1_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x200c0))
|
||||
#define rPMGR_DMATX_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x200c8))
|
||||
#define rPMGR_DMARX_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x200d0))
|
||||
#define rPMGR_UART0_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x200d8))
|
||||
#define rPMGR_UART1_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x200e0))
|
||||
#define rPMGR_UART2_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x200e8))
|
||||
#define rPMGR_UART3_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x200f0))
|
||||
#define rPMGR_UART4_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x200f8))
|
||||
#define rPMGR_AES_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20100))
|
||||
#define rPMGR_I2C0_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20108))
|
||||
#define rPMGR_I2C1_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20110))
|
||||
#define rPMGR_PWM0_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20118))
|
||||
#define rPMGR_AUE_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20120))
|
||||
#define rPMGR_USB_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20128))
|
||||
#define rPMGR_ETH_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20130))
|
||||
#define rPMGR_VDEC_PS (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20138))
|
||||
|
||||
#define rSPU_PMGR_DEBUG_PS (*(volatile uint32_t *) (SPU_SEQUENCER_BASE_ADDR + 0x03004))
|
||||
|
||||
#define PMGR_PS_RESET (1 << 31)
|
||||
#define PMGR_PS_ACTUAL_PS_SHIFT (4)
|
||||
#define PMGR_PS_ACTUAL_PS_MASK (0xF)
|
||||
#define PMGR_PS_MANUAL_PS_MASK (0xF)
|
||||
#define PMGR_PS_RUN_MAX (0xF)
|
||||
#define PMGR_PS_CLOCK_OFF (0x4)
|
||||
#define PMGR_PS_POWER_OFF (0x0)
|
||||
|
||||
#define PMGR_FIRST_PS (&rPMGR_CPU_PS)
|
||||
#define PMGR_LAST_PS (&rPMGR_VDEC_PS)
|
||||
#define PMGR_PS_COUNT (((((void *)(PMGR_LAST_PS)) - ((void *)(PMGR_FIRST_PS))) / 8) + 1)
|
||||
#define PMGR_PS_NUM(_r) (((void *)&(rPMGR_ ## _r ## _PS) - ((void *)(PMGR_FIRST_PS))) / 8)
|
||||
|
||||
// Power Gate Tunable Regs
|
||||
#define rPMGR_PWR_CPU_CFG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22000))
|
||||
#define rPMGR_PWR_CPU_CFG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22004))
|
||||
#define rPMGR_PWR_CPU_CFG2 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22008))
|
||||
#define rPMGR_PWR_CPU_DBG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x2200c))
|
||||
#define rPMGR_PWR_AMCPIO_CFG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22010))
|
||||
#define rPMGR_PWR_AMCPIO_CFG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22014))
|
||||
#define rPMGR_PWR_AMCPIO_CFG2 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22018))
|
||||
#define rPMGR_PWR_AMCPIO_DBG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x2201c))
|
||||
#define rPMGR_PWR_DISP_CFG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22020))
|
||||
#define rPMGR_PWR_DISP_CFG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22024))
|
||||
#define rPMGR_PWR_DISP_CFG2 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22028))
|
||||
#define rPMGR_PWR_DISP_DBG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x2202c))
|
||||
#define rPMGR_PWR_DISP_BE_CFG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22030))
|
||||
#define rPMGR_PWR_DISP_BE_CFG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22034))
|
||||
#define rPMGR_PWR_DISP_BE_CFG2 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22038))
|
||||
#define rPMGR_PWR_DISP_BE_DBG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x2203c))
|
||||
#define rPMGR_PWR_MSR_CFG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22040))
|
||||
#define rPMGR_PWR_MSR_CFG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22044))
|
||||
#define rPMGR_PWR_MSR_CFG2 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22048))
|
||||
#define rPMGR_PWR_MSR_DBG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x2204c))
|
||||
#define rPMGR_PWR_ANS_CFG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22050))
|
||||
#define rPMGR_PWR_ANS_CFG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22054))
|
||||
#define rPMGR_PWR_ANS_CFG2 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22058))
|
||||
#define rPMGR_PWR_ANS_DBG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x2205c))
|
||||
#define rPMGR_PWR_GFX_CFG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22060))
|
||||
#define rPMGR_PWR_GFX_CFG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22064))
|
||||
#define rPMGR_PWR_GFX_CFG2 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22068))
|
||||
#define rPMGR_PWR_GFX_DBG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x2206c))
|
||||
#define rPMGR_PWR_SDIO_CFG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22070))
|
||||
#define rPMGR_PWR_SDIO_CFG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22074))
|
||||
#define rPMGR_PWR_SDIO_CFG2 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22078))
|
||||
#define rPMGR_PWR_SDIO_DBG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x2207c))
|
||||
#define rPMGR_PWR_LIO_CFG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22080))
|
||||
#define rPMGR_PWR_LIO_CFG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22084))
|
||||
#define rPMGR_PWR_LIO_CFG2 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22088))
|
||||
#define rPMGR_PWR_LIO_DBG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x2208c))
|
||||
#define rPMGR_PWR_AUE_CFG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22090))
|
||||
#define rPMGR_PWR_AUE_CFG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22094))
|
||||
#define rPMGR_PWR_AUE_CFG2 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22098))
|
||||
#define rPMGR_PWR_AUE_DBG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x2209c))
|
||||
#define rPMGR_PWR_VDEC_CFG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x220a0))
|
||||
#define rPMGR_PWR_VDEC_CFG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x220a4))
|
||||
#define rPMGR_PWR_VDEC_CFG2 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x220a8))
|
||||
#define rPMGR_PWR_VDEC_DBG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x220ac))
|
||||
#define rPMGR_MCU_ASYNC_RESET (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x22300))
|
||||
|
||||
// EMA Tunable Regs
|
||||
#define rPMGR_EMA_SOC0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x26000))
|
||||
#define rPMGR_EMA_SOC1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x26004))
|
||||
|
||||
// Timer Regs
|
||||
#define rPMGR_CHIP_WDOG_TMR (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x27000))
|
||||
#define rPMGR_CHIP_WDOG_RST_CNT (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x27004))
|
||||
#define rPMGR_CHIP_WDOG_INTR_CNT (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x27008))
|
||||
#define rPMGR_CHIP_WDOG_CTL (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x2700c))
|
||||
#define rPMGR_SYS_WDOG_TMR (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x27010))
|
||||
#define rPMGR_SYS_WDOG_RST_CNT (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x27014))
|
||||
#define rPMGR_SYS_WDOG_CTL (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x2701c))
|
||||
#define rPMGR_EVENT_TMR (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x27100))
|
||||
#define rPMGR_EVENT_TMR_PERIOD (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x27104))
|
||||
#define rPMGR_EVENT_TMR_CTL (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x27108))
|
||||
#define rPMGR_INTERVAL_TMR (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x27200))
|
||||
#define rPMGR_INTERVAL_TMR_CTL (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x27204))
|
||||
|
||||
#define rPMGR_SCRATCH(_n) (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x29000 + ((_n)*4)))
|
||||
#define rPMGR_SCRATCH0 rPMGR_SCRATCH(0) /* Flags */
|
||||
#define rPMGR_SCRATCH1 rPMGR_SCRATCH(1)
|
||||
#define rPMGR_SCRATCH2 rPMGR_SCRATCH(2)
|
||||
#define rPMGR_SCRATCH3 rPMGR_SCRATCH(3)
|
||||
#define rPMGR_SCRATCH4 rPMGR_SCRATCH(4)
|
||||
#define rPMGR_SCRATCH5 rPMGR_SCRATCH(5)
|
||||
#define rPMGR_SCRATCH6 rPMGR_SCRATCH(6)
|
||||
#define rPMGR_SCRATCH7 rPMGR_SCRATCH(7) /* Consistent debug root pointer */
|
||||
#define rPMGR_SCRATCH8 rPMGR_SCRATCH(8)
|
||||
#define rPMGR_SCRATCH9 rPMGR_SCRATCH(9)
|
||||
#define rPMGR_SCRATCH10 rPMGR_SCRATCH(10)
|
||||
#define rPMGR_SCRATCH11 rPMGR_SCRATCH(11)
|
||||
#define rPMGR_SCRATCH12 rPMGR_SCRATCH(12)
|
||||
#define rPMGR_SCRATCH13 rPMGR_SCRATCH(13) /* Memory info */
|
||||
#define rPMGR_SCRATCH14 rPMGR_SCRATCH(14) /* Boot Nonce 0 */
|
||||
#define rPMGR_SCRATCH15 rPMGR_SCRATCH(15) /* Boot Nonce 1 */
|
||||
#define rPMGR_SCRATCH16 rPMGR_SCRATCH(16) /* Boot Manifest Hash 0 */
|
||||
#define rPMGR_SCRATCH17 rPMGR_SCRATCH(17) /* Boot Manifest Hash 1 */
|
||||
#define rPMGR_SCRATCH18 rPMGR_SCRATCH(18) /* Boot Manifest Hash 2 */
|
||||
#define rPMGR_SCRATCH19 rPMGR_SCRATCH(19) /* Boot Manifest Hash 3 */
|
||||
#define rPMGR_SCRATCH20 rPMGR_SCRATCH(20) /* Boot Manifest Hash 4 */
|
||||
#define rPMGR_SCRATCH21 rPMGR_SCRATCH(21)
|
||||
#define rPMGR_SCRATCH22 rPMGR_SCRATCH(22)
|
||||
#define rPMGR_SCRATCH23 rPMGR_SCRATCH(23)
|
||||
|
||||
#define rPMGR_SECURITY (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x31020))
|
||||
|
||||
#define rPMGR_MISC_GFX_CTL (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x31040))
|
||||
|
||||
#define rPMGR_MISC_ACG (*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x32000))
|
||||
|
||||
extern void pmgr_update_device_tree(DTNode *pmgr_node);
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_PMGR_H */
|
||||
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_RECONFIG_H
|
||||
#define __PLATFORM_RECONFIG_H
|
||||
|
||||
#include <sys/types.h>
|
||||
|
||||
#define rRECONFIG_CONFIGURATION *(volatile uint32_t *)(SPU_SOC_RECONFIG_BASE_ADDR + 0x0000)
|
||||
#define rRECONFIG_CONFIG_MEM *(volatile uint32_t *)(SPU_SOC_RECONFIG_BASE_ADDR + 0x0004)
|
||||
#define rRECONFIG_TIMEOUT_MEM *(volatile uint32_t *)(SPU_SOC_RECONFIG_BASE_ADDR + 0x0008)
|
||||
#define rRECONFIG_INTERRUPT_MEM *(volatile uint32_t *)(SPU_SOC_RECONFIG_BASE_ADDR + 0x000C)
|
||||
#define rRECONFIG_CONFIG_SOC *(volatile uint32_t *)(SPU_SOC_RECONFIG_BASE_ADDR + 0x0010)
|
||||
#define rRECONFIG_TIMEOUT_SOC *(volatile uint32_t *)(SPU_SOC_RECONFIG_BASE_ADDR + 0x0014)
|
||||
#define rRECONFIG_INTERRUPT_SOC *(volatile uint32_t *)(SPU_SOC_RECONFIG_BASE_ADDR + 0x0018)
|
||||
#define rRECONFIG_CONFIG_AKF *(volatile uint32_t *)(SPU_SOC_RECONFIG_BASE_ADDR + 0x001C)
|
||||
#define rRECONFIG_TIMEOUT_AKF *(volatile uint32_t *)(SPU_SOC_RECONFIG_BASE_ADDR + 0x0020)
|
||||
#define rRECONFIG_INTERRUPT_AKF *(volatile uint32_t *)(SPU_SOC_RECONFIG_BASE_ADDR + 0x0024)
|
||||
|
||||
|
||||
#define rRECONFIG_RAM_CMD(i) *(volatile uint32_t *)(SPU_SOC_RECONFIG_BASE_ADDR + 0x1000 + (i * 4))
|
||||
#define rRECONFIG_RAM_DATA(i) *(volatile uint32_t *)(SPU_SOC_RECONFIG_BASE_ADDR + 0x2000 + (i * 4))
|
||||
#define rRECONFIG_RAM_MASK(i) *(volatile uint32_t *)(SPU_SOC_RECONFIG_BASE_ADDR + 0x3000 + (i * 4))
|
||||
|
||||
#define RECONFIG_RAM_CMD_READ (1 << 0)
|
||||
|
||||
// Removing this debug region now that reconfig engine/code seems to be working fine
|
||||
// Do not use this space since SPU may have reclaimed it
|
||||
#if 0
|
||||
// last page of SPU SRAM allocated to RECONFIG for reconfig debug purposes
|
||||
#define RECONFIG_DEBUG_SPACE (SPU_SRAM_A_BASE_ADDR + SPU_SRAM_SIZE - PAGE_SIZE)
|
||||
#endif
|
||||
|
||||
typedef enum {RECONFIG_TYPE_MEM, RECONFIG_TYPE_SOC, RECONFIG_TYPE_AKF} reconfig_type_t;
|
||||
|
||||
|
||||
/**
|
||||
* Adds a reconfig command of the given type to the reconfig buffer
|
||||
*
|
||||
* Note that the reconfig driver expects you to program in all the RECONFIG_TYPE_MEM commands,
|
||||
* followed by SOC commands, followed by AKF commands. The driver will panic if you attempt to program
|
||||
* the block in a different sequence.
|
||||
*
|
||||
**/
|
||||
void reconfig_append_command(reconfig_type_t type, uint32_t cmd, uint32_t data, uint32_t mask);
|
||||
|
||||
/**
|
||||
* Program the RECONFIG_CONFIG_{SOC/MEM/AKF} registers with the start / counts, and enables the reconfig block.
|
||||
*
|
||||
* Call this after you've fully reprogrammed the reconfig memory using reconfig_append_command()
|
||||
**/
|
||||
void reconfig_commit();
|
||||
|
||||
|
||||
/**
|
||||
* Prints the contents of the reconfig buffer via printf. For debugging purposes only
|
||||
**/
|
||||
void reconfig_dbg_dump_contents(void);
|
||||
|
||||
#endif /* __PLATFORM_RECONFIG_H */
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_SPU_H
|
||||
#define __PLATFORM_SOC_SPU_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rSPU_AKF_AXI_BASE (*(volatile uint32_t *) (SPU_AKF_BASE_ADDR + 0x8))
|
||||
#define rSPU_AKF_AXI_BASE_EXT (*(volatile uint32_t *) (SPU_AKF_BASE_ADDR + 0xC))
|
||||
#define rSPU_AKF_AXI_START (*(volatile uint32_t *) (SPU_AKF_BASE_ADDR + 0x10))
|
||||
#define rSPU_AKF_AXI_END (*(volatile uint32_t *) (SPU_AKF_BASE_ADDR + 0x18))
|
||||
#define rSPU_AKF_AXI_EN (*(volatile uint32_t *) (SPU_AKF_BASE_ADDR + 0x20))
|
||||
#define rSPU_AKF_AXI_IDLE_CTRL (*(volatile uint32_t *) (SPU_AKF_BASE_ADDR + 0x24))
|
||||
#define rSPU_AKF_AXI_CPU_CTRL (*(volatile uint32_t *) (SPU_AKF_BASE_ADDR + 0x28))
|
||||
|
||||
#define SP_AKF_AXI_CPU_CTRL_RUN (1 << 4)
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_SPU_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_TRAMPOLINE_H
|
||||
#define __PLATFORM_TRAMPOLINE_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
/* ROM related registers in PMGR space */
|
||||
|
||||
#define SECURITY_REG (PMGR_BASE_ADDR + 0x31020)
|
||||
#define ROM_READ_DISABLE (1 << 4)
|
||||
|
||||
#endif /* ! __PLATFORM_TRAMPOLINE_H */
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_USBCONFIG_H
|
||||
#define __PLATFORM_USBCONFIG_H
|
||||
|
||||
#ifdef WITH_TARGET_USB_CONFIG
|
||||
#include <target/usbconfig.h>
|
||||
#endif /* WITH_TARGET_USB_CONFIG */
|
||||
|
||||
#define USBPHY_OTGTUNE0 (0x374413F3)
|
||||
|
||||
#define USBOTG_AHB_DMA_BURST (DWCUSB_GAHBCFG_HBST_INCR16)
|
||||
|
||||
#endif /* ! __PLATFORM_USBCONFIG_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,216 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <arch.h>
|
||||
#include <debug.h>
|
||||
#include <drivers/miu.h>
|
||||
#include <platform.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <platform/miu.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <platform/soc/miu.h>
|
||||
#include <platform/soc/pmgr.h>
|
||||
#include <platform/soc/reconfig.h>
|
||||
#include <platform/clocks.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <platform/timer.h>
|
||||
|
||||
#if (APPLICATION_IBOOT)
|
||||
|
||||
static void miu_configure_bridge(const u_int32_t *bridge_settings);
|
||||
|
||||
#define STATIC_BRIDGE_SHIFT (28)
|
||||
#define STATIC_BRIDGE_OFFSET_MASK ((1 << STATIC_BRIDGE_SHIFT) - 1)
|
||||
|
||||
#define PMGR_REGISTERS (0 << STATIC_BRIDGE_SHIFT)
|
||||
#define CPU_FABRIC_WIDGETS (1 << STATIC_BRIDGE_SHIFT)
|
||||
#define NRT_FABRIC_WIDGETS (2 << STATIC_BRIDGE_SHIFT)
|
||||
|
||||
static const u_int32_t bridge_registers[] = {
|
||||
PMGR_BASE_ADDR,
|
||||
CPU_FABRIC_BASE_ADDR,
|
||||
NRT_FABRIC_BASE_ADDR,
|
||||
};
|
||||
|
||||
// This array is composed of 3-item tuples consisting of:
|
||||
// Bridge id | register offset (with optional | RECONFIG_RAM_CMD_READ)
|
||||
// Register data value or comparison value if RECONFIG_RAM_CMD_READ is specified
|
||||
// Mask value if RECONFIG_RAM_CMD_READ is specified (used only by reconfig engine)
|
||||
static const u_int32_t bridge_settings_static[] = {
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_AMCRDRATELIMIT, 0, 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_AMCWRALIMIT, 0, 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_AMCRTRLIMIT, (0x3f << 8) | (0x3f << 0), 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_AMCWTRLIMIT, (0x3f << 8) | (0x3f << 0), 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_SPURDRATELIMIT, 0, 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_SPUWRALIMIT, 0, 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_SPURTRLIMIT, (0x3f << 8) | (0x3f << 0), 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_SPUWTRLIMIT, (0x3f << 8) | (0x3f << 0), 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_SPUWGATHER, (0x01 << 8), 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_LIOWGATHER, (0x01 << 8), 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_AUERDRATELIMIT, 0, 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_AUEWRALIMIT, 0, 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_AUERTRLIMIT, (0x3f << 8) | (0x3f << 0), 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_AUEWTRLIMIT, (0x3f << 8) | (0x3f << 0), 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_AUEWGATHER, (0x01 << 8), 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_ANSRDRATELIMIT, 0, 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_ANSWRALIMIT, 0, 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_ANSRTRLIMIT, (0x08 << 8) | (0x08 << 0), 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_ANSWTRLIMIT, (0x05 << 8) | (0x05 << 0), 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_ANSWGATHER, (0x01 << 8), 0,
|
||||
CPU_FABRIC_WIDGETS | CPU_Fabric_pl301Wrap0_AXI0_ARCHANARBMI0, 0, 0,
|
||||
|
||||
// Turn on the clock that controls the NRT Fabric widgets. The MSR clock
|
||||
// is behind the Media clock so we turn it on to keep the Media clock
|
||||
// from gating.
|
||||
PMGR_REGISTERS | PMGR_MSR_PS, (0x1 << 8) | (0x1 << 9) | (0xf << 0), 0,
|
||||
PMGR_REGISTERS | PMGR_MEDIA_CLK_CFG, 0x80100000, 0,
|
||||
PMGR_REGISTERS | PMGR_MEDIA_CLK_CFG | RECONFIG_RAM_CMD_READ,0, 0x40000000,
|
||||
|
||||
NRT_FABRIC_WIDGETS | NRT_Fabric_pl301Wrap1_AMCRDRATELIMIT, 0, 0,
|
||||
NRT_FABRIC_WIDGETS | NRT_Fabric_pl301Wrap1_AMCWRALIMIT, 0, 0,
|
||||
NRT_FABRIC_WIDGETS | NRT_Fabric_pl301Wrap1_AMCRTRLIMIT, (0x3f << 8) | (0x3f << 0), 0,
|
||||
NRT_FABRIC_WIDGETS | NRT_Fabric_pl301Wrap1_AMCWTRLIMIT, (0x3f << 8) | (0x3f << 0), 0,
|
||||
NRT_FABRIC_WIDGETS | NRT_Fabric_pl301Wrap1_MSRRDRATELIMIT, 0, 0,
|
||||
NRT_FABRIC_WIDGETS | NRT_Fabric_pl301Wrap1_MSRWRALIMIT, 0, 0,
|
||||
NRT_FABRIC_WIDGETS | NRT_Fabric_pl301Wrap1_MSRRTRLIMIT, (0x3f << 8) | (0x3f << 0), 0,
|
||||
NRT_FABRIC_WIDGETS | NRT_Fabric_pl301Wrap1_MSRWTRLIMIT, (0x3f << 8) | (0x3f << 0), 0,
|
||||
NRT_FABRIC_WIDGETS | NRT_Fabric_pl301Wrap1_SDIORDRATELIMIT, 0, 0,
|
||||
NRT_FABRIC_WIDGETS | NRT_Fabric_pl301Wrap1_SDIOWRALIMIT, 0, 0,
|
||||
NRT_FABRIC_WIDGETS | NRT_Fabric_pl301Wrap1_SDIORTRLIMIT, (0x3f << 8) | (0x3f << 0), 0,
|
||||
NRT_FABRIC_WIDGETS | NRT_Fabric_pl301Wrap1_SDIOWTRLIMIT, (0x04 << 8) | (0x04 << 0), 0,
|
||||
// Need a read to make sure writes are pushed out to the fabric
|
||||
// before the following steps are executed.
|
||||
NRT_FABRIC_WIDGETS | NRT_Fabric_pl301Wrap1_SDIOWTRLIMIT | RECONFIG_RAM_CMD_READ, (0x04 << 8) | (0x04 << 0), (0xf << 8) | (0xf << 0),
|
||||
|
||||
// Reprogram the clock configuration to its expected value.
|
||||
// NOTE: We can't write PMGR_MSR_PS back to its original value here.
|
||||
// Attempting to do so will result in a hang.
|
||||
PMGR_REGISTERS | PMGR_MEDIA_CLK_CFG, 0x83100000, 0,
|
||||
PMGR_REGISTERS | PMGR_MEDIA_CLK_CFG | RECONFIG_RAM_CMD_READ,0, 0x40000000,
|
||||
};
|
||||
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
int miu_initialize_internal_ram(void)
|
||||
{
|
||||
#if APPLICATION_SECUREROM
|
||||
// Ensure that rPMGR_SCRATCH0-3 get cleared
|
||||
rPMGR_SCRATCH0 = 0;
|
||||
rPMGR_SCRATCH1 = 0;
|
||||
rPMGR_SCRATCH2 = 0;
|
||||
rPMGR_SCRATCH3 = 0;
|
||||
#endif /* APPLICATION_SECUREROM */
|
||||
|
||||
// Save the Security Epoch in the top byte of PMGR_SCRATCH0
|
||||
rPMGR_SCRATCH0 &= ~0xFF000000;
|
||||
rPMGR_SCRATCH0 |= (platform_get_security_epoch()) << 24;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int miu_init(void)
|
||||
{
|
||||
#if APPLICATION_IBOOT && !PRODUCT_IBEC
|
||||
// Verify that the Security Epoch in PMGR_SCRATCH0 matches
|
||||
if ((rPMGR_SCRATCH0 >> 24) != platform_get_security_epoch()) {
|
||||
panic("miu_init: Epoch Mismatch\n");
|
||||
}
|
||||
#endif
|
||||
#if (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
|
||||
miu_configure_bridge(bridge_settings_static);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void miu_suspend(void)
|
||||
{
|
||||
/* nothing required for suspend */
|
||||
}
|
||||
|
||||
int miu_initialize_dram(bool resume)
|
||||
{
|
||||
#if APPLICATION_IBOOT && WITH_HW_AMC
|
||||
mcu_initialize_dram(resume);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
void miu_select_remap(enum remap_select sel)
|
||||
{
|
||||
switch (sel) {
|
||||
case REMAP_SRAM:
|
||||
rPIO_REMAP_CTL = (rPIO_REMAP_CTL & ~1) | (1 << 0); // Resources mapped to address 0x0 are now remapped SPU_SRAM
|
||||
break;
|
||||
|
||||
case REMAP_SDRAM:
|
||||
rFABRIC_REMAP_REG = (rFABRIC_REMAP_REG & ~1) | (1 << 0); // 0x0000_0000 to 0x0010_0000 is mapped to DRAM
|
||||
break;
|
||||
|
||||
// reset back to default behavior
|
||||
default:
|
||||
rPIO_REMAP_CTL = 0;
|
||||
rFABRIC_REMAP_REG = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void miu_bypass_prep(void)
|
||||
{
|
||||
}
|
||||
|
||||
#if (APPLICATION_IBOOT && (PRODUCT_IBSS || PRODUCT_LLB))
|
||||
static void miu_configure_bridge(const u_int32_t *bridge_settings)
|
||||
{
|
||||
volatile u_int32_t *reg;
|
||||
u_int32_t bridge, offset, data, mask;
|
||||
u_int32_t i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(bridge_settings_static); i += 3) {
|
||||
bridge = bridge_settings[i] >> STATIC_BRIDGE_SHIFT;
|
||||
offset = bridge_settings[i] & STATIC_BRIDGE_OFFSET_MASK & ~RECONFIG_RAM_CMD_READ;
|
||||
data = bridge_settings[i + 1];
|
||||
reg = (volatile u_int32_t *)(bridge_registers[bridge] + offset);
|
||||
if (bridge_settings[i] & RECONFIG_RAM_CMD_READ) {
|
||||
mask = bridge_settings_static[i + 2];
|
||||
SPIN_W_TMO_UNTIL((*reg & mask) == data);
|
||||
} else {
|
||||
*reg = data;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif // (APPLICATION_IBOOT && (PRODUCT_IBSS || PRODUCT_LLB))
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void miu_configure_bridge_soc_reconfig_ram(void)
|
||||
{
|
||||
addr_t reg;
|
||||
u_int32_t bridge, offset, data, mask;
|
||||
u_int32_t i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(bridge_settings_static); i += 3) {
|
||||
bridge = bridge_settings_static[i] >> STATIC_BRIDGE_SHIFT;
|
||||
offset = bridge_settings_static[i] & STATIC_BRIDGE_OFFSET_MASK;
|
||||
data = bridge_settings_static[i + 1];
|
||||
mask = bridge_settings_static[i + 2];
|
||||
reg = (addr_t)(bridge_registers[bridge] + offset);
|
||||
reconfig_append_command(RECONFIG_TYPE_SOC, reg, data, mask);
|
||||
}
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
void miu_update_device_tree(DTNode *pmgr_node)
|
||||
{
|
||||
// Nothing to do here
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_MIU=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/miu.o
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,18 @@
|
||||
# Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_CLOCKS=1 \
|
||||
WITH_HW_PLATFORM_POWER=1 \
|
||||
WITH_HW_TIMER=1 \
|
||||
WITH_FIQ_TIMER=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/pmgr.o
|
||||
@@ -0,0 +1,103 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <platform/soc/reconfig.h>
|
||||
#include <sys.h>
|
||||
|
||||
#define ENCODE_RECONFIG_CONFIG(start, count) ((((count) & 0x3ff) << 16) | ((start & 0x3ff) << 0))
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint32_t mem_reconfig_count;
|
||||
uint32_t soc_reconfig_count;
|
||||
uint32_t akf_reconfig_count;
|
||||
} reconfig_stat_t;
|
||||
|
||||
static reconfig_stat_t reconfig_stat;
|
||||
|
||||
void reconfig_append_command(reconfig_type_t type, uint32_t cmd, uint32_t data, uint32_t mask)
|
||||
{
|
||||
uint32_t reconfig_offset = 0;
|
||||
uint32_t *reconfig_count_ptr = NULL;
|
||||
|
||||
// First, a basic check that reconfig is being programmed in the right order (mem -> soc -> akf)
|
||||
switch (type)
|
||||
{
|
||||
case RECONFIG_TYPE_MEM:
|
||||
ASSERT(reconfig_stat.soc_reconfig_count == 0);
|
||||
ASSERT(reconfig_stat.akf_reconfig_count == 0);
|
||||
reconfig_offset = reconfig_stat.mem_reconfig_count;
|
||||
reconfig_count_ptr = &reconfig_stat.mem_reconfig_count;
|
||||
break;
|
||||
case RECONFIG_TYPE_SOC:
|
||||
ASSERT(reconfig_stat.mem_reconfig_count != 0);
|
||||
ASSERT(reconfig_stat.akf_reconfig_count == 0);
|
||||
reconfig_offset = reconfig_stat.mem_reconfig_count + reconfig_stat.soc_reconfig_count;
|
||||
reconfig_count_ptr = &reconfig_stat.soc_reconfig_count;
|
||||
break;
|
||||
case RECONFIG_TYPE_AKF:
|
||||
ASSERT(reconfig_stat.mem_reconfig_count != 0);
|
||||
ASSERT(reconfig_stat.soc_reconfig_count != 0);
|
||||
reconfig_offset = reconfig_stat.mem_reconfig_count + reconfig_stat.soc_reconfig_count + reconfig_stat.akf_reconfig_count;
|
||||
reconfig_count_ptr = &reconfig_stat.akf_reconfig_count;
|
||||
break;
|
||||
default:
|
||||
panic("Unknown reconfig type: %d", type);
|
||||
}
|
||||
|
||||
if(reconfig_offset >= RECONFIG_RAM_SIZE_IN_WORDS - 1)
|
||||
{
|
||||
panic("Out of reconfig space!");
|
||||
}
|
||||
|
||||
rRECONFIG_RAM_CMD(reconfig_offset) = cmd;
|
||||
rRECONFIG_RAM_DATA(reconfig_offset) = data;
|
||||
rRECONFIG_RAM_MASK(reconfig_offset) = mask;
|
||||
|
||||
(*reconfig_count_ptr)++;
|
||||
}
|
||||
|
||||
void reconfig_commit()
|
||||
{
|
||||
// Encode start/range
|
||||
rRECONFIG_CONFIG_MEM = ENCODE_RECONFIG_CONFIG(0, reconfig_stat.mem_reconfig_count);
|
||||
rRECONFIG_CONFIG_SOC = ENCODE_RECONFIG_CONFIG(reconfig_stat.mem_reconfig_count, reconfig_stat.soc_reconfig_count);
|
||||
rRECONFIG_CONFIG_AKF = ENCODE_RECONFIG_CONFIG(reconfig_stat.mem_reconfig_count + reconfig_stat.soc_reconfig_count, reconfig_stat.akf_reconfig_count);
|
||||
|
||||
|
||||
// Enable Reconfig engine
|
||||
rRECONFIG_CONFIGURATION |= (1 << 16);
|
||||
}
|
||||
|
||||
void reconfig_dbg_dump_contents(void)
|
||||
{
|
||||
printf("==== MEM RECONFIG COMMANDS ====\n");
|
||||
printf("INDEX\t\tCMD\t\tDATA\t\tMASK\n");
|
||||
for(uint32_t i = 0; i < reconfig_stat.mem_reconfig_count; i++)
|
||||
{
|
||||
printf("%d\t\t0x%08x\t\t0x%08x\t\t0x%08x\n", i, rRECONFIG_RAM_CMD(i), rRECONFIG_RAM_DATA(i), rRECONFIG_RAM_MASK(i));
|
||||
}
|
||||
printf("==== SOC RECONFIG COMMANDS ====\n");
|
||||
printf("INDEX\t\tCMD\t\tDATA\t\tMASK\n");
|
||||
for(uint32_t i = reconfig_stat.mem_reconfig_count; i < reconfig_stat.mem_reconfig_count + reconfig_stat.soc_reconfig_count; i++)
|
||||
{
|
||||
printf("%d\t\t0x%08x\t\t0x%08x\t\t0x%08x\n", i, rRECONFIG_RAM_CMD(i), rRECONFIG_RAM_DATA(i), rRECONFIG_RAM_MASK(i));
|
||||
}
|
||||
printf("==== AKF RECONFIG COMMANDS ====\n");
|
||||
printf("INDEX\t\tCMD\t\tDATA\t\tMASK\n");
|
||||
for(uint32_t i = reconfig_stat.mem_reconfig_count + reconfig_stat.soc_reconfig_count; i < reconfig_stat.mem_reconfig_count + reconfig_stat.akf_reconfig_count; i++)
|
||||
{
|
||||
printf("%d\t\t0x%08x\t\t0x%08x\t\t0x%08x\n", i, rRECONFIG_RAM_CMD(i), rRECONFIG_RAM_DATA(i), rRECONFIG_RAM_MASK(i));
|
||||
}
|
||||
printf("reconfig_commit: RECONFIG_CONFIG_MEM = 0x%x, CONFIG_SOC = 0x%x, CONFIG_AKF=0x%x\n", rRECONFIG_CONFIG_MEM, rRECONFIG_CONFIG_SOC, rRECONFIG_CONFIG_AKF);
|
||||
}
|
||||
@@ -0,0 +1,17 @@
|
||||
# Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_RECONFIG=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/reconfig.o
|
||||
@@ -0,0 +1,136 @@
|
||||
# Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
# modules implied by this platform
|
||||
MODULES += \
|
||||
platform/defaults \
|
||||
platform/generic \
|
||||
arch/$(ARCH)
|
||||
|
||||
ARM_CPU := cortex-a7
|
||||
|
||||
# Devmap chip ID
|
||||
DEVMAP_CHIP_ID := 7002
|
||||
|
||||
IRQ_STACK_SIZE := 4096
|
||||
|
||||
# srom is always defined in here
|
||||
ifeq ($(TEXT_BANK),srom)
|
||||
TEXT_BASE := 0x00000000
|
||||
endif
|
||||
|
||||
# Overriding SRAM_LEN is not allowed.
|
||||
ifeq ($(TEXT_BANK),sram)
|
||||
# SRAM TEXT_BASE is fixed by SecureROM.
|
||||
TEXT_BASE := 0x46018000
|
||||
|
||||
# iBSS/LLB memory configuration
|
||||
ifeq ($(TEXT_FOOTPRINT),)
|
||||
TEXT_FOOTPRINT:= 180*1024
|
||||
endif
|
||||
endif
|
||||
|
||||
# platform target can override sdram config by specifying this in target config file (apps/iBoot/$target-config.mk)
|
||||
ifeq ($(SDRAM_LEN),)
|
||||
SDRAM_LEN := 512*1024*1024
|
||||
|
||||
# iBoot/iBEC memory configuration
|
||||
ifeq ($(TEXT_BANK),sdram)
|
||||
# SDRAM TEXT_BASE is now set such that you don't have to do lots of math to
|
||||
# calulate the correct value if you change any of the other region sizes:
|
||||
# TEXT_BASE = SDRAM_BASE + SDRAM_LEN - 64MB
|
||||
TEXT_BASE := 0x9C000000
|
||||
|
||||
ifeq ($(TEXT_FOOTPRINT),)
|
||||
TEXT_FOOTPRINT := 1024*1024
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(TEXT_BANK),srom)
|
||||
MAX_DFU_SIZE := 128*1024
|
||||
endif
|
||||
ifeq ($(TEXT_BANK),sram)
|
||||
MAX_DFU_SIZE := 192*1024
|
||||
endif
|
||||
|
||||
# platform target can override display size config by specifying this in target config file (apps/iBoot/$target-config.mk)
|
||||
ifeq ($(DISPLAY_SIZE),)
|
||||
DISPLAY_SIZE := 4*1024*1024
|
||||
endif
|
||||
|
||||
OPTIONS += \
|
||||
AIC_CPU_ID=0 \
|
||||
L2_CACHE_SIZE=256*1024 \
|
||||
L2_CACHE_SETS=9 \
|
||||
WITH_NON_COHERENT_DMA=1 \
|
||||
ANC_PPNNPL_DS_DRIVE_STRENGTH=6 \
|
||||
ANC_LINK_CMD_ADDR_PULSE_TIMING_CA_HOLD_TIME=1 \
|
||||
ANC_LINK_CMD_ADDR_PULSE_TIMING_CA_SETUP_TIME=1 \
|
||||
ANC_LINK_SDR_REN_HOLD_TIME=2 \
|
||||
ANC_LINK_SDR_REN_SETUP_TIME=3 \
|
||||
ANC_LINK_SDR_WEN_HOLD_TIME=2 \
|
||||
ANC_LINK_SDR_WEN_SETUP_TIME=3 \
|
||||
ANC_LINK_SDR_DATA_CAPTURE_DELAY=0 \
|
||||
ANC_LINK_SDR_CLE_ALE_SETUP_TIME=0 \
|
||||
ANC_BOOT_CONTROLLERS=1 \
|
||||
ANC_TOGGLE_SUPPORTED=0 \
|
||||
ASP_LLB_OVERRIDE_NUM_BLKS=253*2 \
|
||||
DISPLAY_SIZE="($(DISPLAY_SIZE)ULL)" \
|
||||
PLATFORM_ENTROPY_RATIO=200 \
|
||||
PLATFORM_IRQ_COUNT=128 \
|
||||
SDRAM_LEN="$(SDRAM_LEN)ULL" \
|
||||
TEXT_BASE="$(TEXT_BASE)" \
|
||||
TEXT_FOOTPRINT="$(TEXT_FOOTPRINT)" \
|
||||
WITH_CLASSIC_SUSPEND_TO_RAM=1 \
|
||||
WITH_NO_RANDOM_HEAP_COOKIE=1 \
|
||||
WITH_NO_RANDOM_STACK_COOKIE=1 \
|
||||
WITH_PLATFORM_INIT_USB=1 \
|
||||
CLEAN_INV_CACHE_ON_QUIESCE=1
|
||||
|
||||
# This platform contains corecrypto, needs large idle task stack for DFU stages.
|
||||
ifeq ($(PRODUCT),iBSS)
|
||||
OPTIONS += \
|
||||
IDLE_TASK_SIZE=0x3000 \
|
||||
PLATFORM_START_FUNCTION=_platform_start \
|
||||
WITH_BOOT_TRAMPOLINE=1
|
||||
endif
|
||||
|
||||
ifeq ($(PRODUCT),LLB)
|
||||
OPTIONS += \
|
||||
IDLE_TASK_SIZE=0x3000 \
|
||||
PLATFORM_START_FUNCTION=_platform_start \
|
||||
WITH_BOOT_TRAMPOLINE=1
|
||||
endif
|
||||
|
||||
ifeq ($(APPLICATION),SecureROM)
|
||||
DATA_BASE := 0x46000000
|
||||
OPTIONS += \
|
||||
IDLE_TASK_SIZE=0x3000
|
||||
WITH_ROM_TRAMPOLINE=1 \
|
||||
DATA_BASE="$(DATA_BASE)"
|
||||
|
||||
GLOBAL_LDFLAGS += \
|
||||
-segaddr __DATA $(DATA_BASE)
|
||||
ifeq ($(CONFIGS),fpga)
|
||||
OPTIONS += \
|
||||
SUPPORT_FPGA=1
|
||||
endif
|
||||
endif
|
||||
|
||||
GLOBAL_LDFLAGS += \
|
||||
-seg1addr $(TEXT_BASE)
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/asm.o \
|
||||
$(LOCAL_DIR)/init.o
|
||||
Reference in new issue
Block a user