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@@ -0,0 +1,13 @@
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# Copyright (C) 2014 Apple Inc. All rights reserved.
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#
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# This document is the property of Apple Computer, Inc.
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# It is considered confidential and proprietary.
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#
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# This document may not be reproduced or transmitted in any form,
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# in whole or in part, without the express written permission of
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# Apple Computer, Inc.
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#
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LOCAL_DIR := $(GET_LOCAL_DIR)
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ALL_OBJS += \
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$(LOCAL_DIR)/apcie_v2.o \
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@@ -0,0 +1,36 @@
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/*
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* Copyright (c) 2013-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <platform.h>
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#include <platform/memmap.h>
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#include <platform/soc/hwregbase.h>
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#include SUB_PLATFORM_SPDS_HEADER(minipmgr)
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.text
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.balign 4
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.globl _platform_start
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_platform_start:
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#if !APPLICATION_SECUREROM
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////////////////////////////////////////////////
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// Must preserve X0 and X1
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////////////////////////////////////////////////
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// Enable the L2 cache load/store prefetcher.
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mrs x2, s3_0_c15_c5_0 // HID5
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and x2, x2, #~(3<<44) // Enable L2C load (bit 44)/store (bit 45) prefetch
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msr s3_0_c15_c5_0, x2 // HID5
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isb
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#endif
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ret
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.balign 8
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@@ -0,0 +1,349 @@
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/*
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* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
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*
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||||
* This document is the property of Apple Inc.
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||||
* It is considered confidential and proprietary.
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||||
*
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||||
* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <platform.h>
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#include <platform/pmgr.h>
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#include <platform/soc/chipid.h>
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#include <platform/soc/hwclocks.h>
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#if SUB_PLATFORM_S8000
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#define MINIMUM_FUSE_REVISION 0x8
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#elif SUB_PLATFORM_S8001
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#define MINIMUM_FUSE_REVISION 0x6
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#elif SUB_PLATFORM_S8003
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#define MINIMUM_FUSE_REVISION 0x3
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#else
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#error "Unknown platform"
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#endif
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bool chipid_get_current_production_mode(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_XTRCT(rCFG_FUSE0) != 0;
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}
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bool chipid_get_raw_production_mode(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_XTRCT(rCFG_FUSE0_RAW) != 0;
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}
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void chipid_clear_production_mode(void)
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{
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rCFG_FUSE0 &= ~MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_UMASK;
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}
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bool chipid_get_secure_mode(void)
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{
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// demotion only applies to the SEP, so iBoot always reads
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// the raw value for secure mode (<rdar://problem/15182573>)
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return MINIPMGR_FUSE_CFG_FUSE0_SECURE_MODE_XTRCT(rCFG_FUSE0_RAW);
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}
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uint32_t chipid_get_security_domain(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_SECURITY_DOMAIN_XTRCT(rCFG_FUSE0);
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}
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uint32_t chipid_get_board_id(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_BID_XTRCT(rCFG_FUSE0);
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}
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uint32_t chipid_get_minimum_epoch(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_MINIMUM_EPOCH_XTRCT(rCFG_FUSE0);
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}
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uint32_t chipid_get_chip_id(void)
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{
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#if SUB_PLATFORM_S8000
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return 0x8000;
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#elif SUB_PLATFORM_S8001
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return 0x8001;
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#elif SUB_PLATFORM_S8003
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return 0x8003;
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#else
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#error "Unknown platform"
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#endif
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}
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uint32_t chipid_get_chip_revision(void)
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{
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// we use 4 bits for base layer and 4 bits for metal,
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// the fuses use 3 for each
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#if defined(MINIPMGR_FUSE_CFG_FUSE4_DEV_VERSION_XTRCT)
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uint32_t fuse_val = MINIPMGR_FUSE_CFG_FUSE4_DEV_VERSION_XTRCT(rCFG_FUSE4);
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return (fuse_val & 0x7) | (((fuse_val >> 3) & 0x7) << 4);
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#elif defined(MINIPMGR_FUSE_CFG_FUSE4_CHIP_REV_MAJOR_XTRCT)
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uint32_t fuse = rCFG_FUSE4;
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return ((MINIPMGR_FUSE_CFG_FUSE4_CHIP_REV_MAJOR_XTRCT(fuse) << 4) |
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(MINIPMGR_FUSE_CFG_FUSE4_CHIP_REV_MINOR_XTRCT(fuse)));
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#else
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#error "SPDS doesn't contain expected chip rev extraction defines"
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#endif
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}
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uint32_t chipid_get_osc_frequency(void)
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{
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return OSC_FREQ;
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}
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uint64_t chipid_get_ecid_id(void)
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{
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return ((uint64_t)rECIDHI << 32) | rECIDLO;
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}
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uint64_t chipid_get_die_id(void)
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{
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return ((uint64_t)rECIDHI << 32) | rECIDLO;
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}
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uint32_t chipid_get_cpu_voltage(uint32_t index)
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{
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uint32_t voltage = pmgr_binning_get_mv(index, false, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid CPU voltage index %d\n", index);
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return voltage;
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}
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uint32_t chipid_get_cpu_sram_voltage(uint32_t index)
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{
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uint32_t voltage = pmgr_binning_get_mv(index, true, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid CPU SRAM voltage index %d\n", index);
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return voltage;
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}
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uint32_t chipid_get_soc_voltage(uint32_t index)
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{
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uint32_t voltage;
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#if SUB_PLATFORM_S8001
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#if SUB_TARGET_J99A | SUB_TARGET_J98A
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index = CHIPID_SOC_VOLTAGE_VMIN;
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#else
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index = CHIPID_SOC_VOLTAGE_VNOM;
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#endif
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#endif
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voltage = pmgr_binning_get_mv(index, false, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid SOC voltage index %d\n", index);
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return voltage;
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}
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uint32_t chipid_get_gpu_voltage(uint32_t index)
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{
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uint32_t voltage = pmgr_binning_get_mv(index, false, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid GPU voltage index %d\n", index);
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return voltage;
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}
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uint32_t chipid_get_gpu_sram_voltage(uint32_t index)
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{
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uint32_t voltage = pmgr_binning_get_mv(index, true, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid GPU SRAM voltage index %d\n", index);
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return voltage;
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}
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uint32_t chipid_get_sram_voltage(uint32_t index)
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{
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uint32_t voltage = pmgr_binning_get_mv(CHIPID_VOLTAGE_FIXED, true, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid SRAM voltage index %d\n", index);
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return voltage;
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}
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bool chipid_get_fuse_lock(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE1_AP_LOCK_XTRCT(rCFG_FUSE1) != 0;
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}
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void chipid_set_fuse_lock(bool locked)
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{
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if (locked) {
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rCFG_FUSE1 |= MINIPMGR_FUSE_CFG_FUSE1_AP_LOCK_INSRT(1);
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asm("dsb sy");
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if (!chipid_get_fuse_lock()) {
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panic("Failed to lock fuses\n");
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}
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}
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}
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bool chipid_get_fuse_seal(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE1_SEAL_FUSES_XTRCT(rCFG_FUSE1) != 0;
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}
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uint32_t chipid_get_lpo_trim(void)
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{
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#if SUB_PLATFORM_S8000
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// <rdar://problem/18530570> LPO clock doesn't lock with fused TRIM value but does with 0 trim
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if (chipid_get_fuse_revision() < 3)
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return 0x20;
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else
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#endif
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return MINIPMGR_FUSE_CFG_FUSE2_LPO_TRIM_XTRCT(rCFG_FUSE2);
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}
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#if SUB_PLATFORM_S8000
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uint32_t chipid_get_pcie_txpll_vco_v2i_i_set(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE3_PCIE_TXPLL_VCO_V2I_I_SET_XTRCT(rCFG_FUSE3);
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}
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uint32_t chipid_get_pcie_txpll_vco_v2i_pi_set(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE3_PCIE_TXPLL_VCO_V2I_PI_SET_XTRCT(rCFG_FUSE3);
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}
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uint32_t chipid_get_pcie_refpll_vco_v2i_i_set(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE4_PCIE_REFPLL_VCO_V2I_I_SET_XTRCT(rCFG_FUSE4);
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}
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uint32_t chipid_get_pcie_refpll_vco_v2i_pi_set(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE4_PCIE_REFPLL_VCO_V2I_PI_SET_XTRCT(rCFG_FUSE4);
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}
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uint32_t chipid_get_pcie_rx_ldo(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE3_PCIE_RX_LDO_XTRCT(rCFG_FUSE3);
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}
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#elif SUB_PLATFORM_S8001 || SUB_PLATFORM_S8003
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uint32_t chipid_get_pcie_refpll_fcal_vco_digctrl(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE4_PCIE_REFPLL_FCAL_VCO_DIGCTRL_XTRCT(rCFG_FUSE4);
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}
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#endif
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uint32_t chipid_get_soc_temp_sensor_trim(uint32_t sensor_index)
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{
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uint32_t sensor_trim;
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#if SUB_PLATFORM_S8000 && defined(MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_TRIMG_UMASK)
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// S8000 A1
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if (chipid_get_chip_revision() == CHIP_REVISION_A1) {
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switch (sensor_index) {
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case 0:
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return MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_XTRCT_V1(rCFG_FUSE2);
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case 1:
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return MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN1_XTRCT_V1(rCFG_FUSE2);
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case 2:
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return MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN2_XTRCT_V1(rCFG_FUSE3);
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default:
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panic("invalid thermal sensor %u", sensor_index);
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}
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}
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#endif
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// S8000 B0/C0, S8001 A0/B0, S8003 A0/A1
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switch (sensor_index) {
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case 0:
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sensor_trim = rCFG_FUSE2;
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sensor_trim &= MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_TRIMG_UMASK | MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_TRIMO_UMASK;
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sensor_trim >>= MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_TRIMG_SHIFT;
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return sensor_trim;
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case 1:
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sensor_trim = rCFG_FUSE2;
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sensor_trim &= MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN1_TRIMG_UMASK | MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN1_TRIMO_UMASK;
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sensor_trim >>= MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN1_TRIMG_SHIFT;
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return sensor_trim;
|
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case 2:
|
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sensor_trim = rCFG_FUSE3;
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sensor_trim &= MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN2_TRIMG_UMASK | MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN2_TRIMO_UMASK;
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sensor_trim >>= MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN2_TRIMG_SHIFT;
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return sensor_trim;
|
||||
|
||||
#if SUB_PLATFORM_S8001
|
||||
case 3:
|
||||
sensor_trim = rCFG_FUSE3;
|
||||
sensor_trim &= MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN3_TRIMG_UMASK | MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN3_TRIMO_UMASK;
|
||||
sensor_trim >>= MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN3_TRIMG_SHIFT;
|
||||
return sensor_trim;
|
||||
#endif
|
||||
|
||||
default:
|
||||
panic("invalid thermal sensor %u", sensor_index);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t chipid_get_fuse_revision(void)
|
||||
{
|
||||
uint32_t version = pmgr_binning_get_revision();
|
||||
if (version == PMGR_BINNING_NOTFOUND) {
|
||||
return 0;
|
||||
}
|
||||
return version;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_total_rails_leakage()
|
||||
{
|
||||
// FIXME
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
|
||||
#define FPGA_HAS_INT3 (FPGA_HAS_DISP | FPGA_HAS_MEDIA | FPGA_HAS_JPEG | FPGA_HAS_MSR | FPGA_HAS_VXD)
|
||||
|
||||
uint32_t chipid_get_fpga_block_instantiation(void)
|
||||
{
|
||||
// Hardware blocks instantiated.
|
||||
uint32_t blocks = (rECID_FUSE3 >> 18) & 0xF;
|
||||
uint32_t mask = FPGA_HAS_ALWAYS;
|
||||
|
||||
switch (blocks) {
|
||||
// INT2 := ACC + AF + AMC + SouthBridge + PCIE
|
||||
case 0x1:
|
||||
break;
|
||||
|
||||
// INT2GFX := INT2 + GFX
|
||||
case 0x2:
|
||||
mask |= FPGA_HAS_GFX;
|
||||
break;
|
||||
|
||||
// INT3 := INT2 + DISP + MEDIA + JPEG + MSR + VXD
|
||||
case 0x8:
|
||||
mask |= FPGA_HAS_INT3;
|
||||
break;
|
||||
|
||||
// INT3GFX := INT3 + GFX
|
||||
case 0xA:
|
||||
mask |= (FPGA_HAS_INT3 | FPGA_HAS_GFX);
|
||||
break;
|
||||
|
||||
default:
|
||||
panic("Unknown hardware block instantiation: 0x%x", blocks);
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,276 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is only a database of the performance sate for CPU and GPU, regarding the kind of chip
|
||||
* or board, it has no access to the chip.
|
||||
*/
|
||||
#include <platform.h>
|
||||
#include <platform/soc/dvfmperf.h>
|
||||
|
||||
// These array are the first iteration, the next part will include reference to board id, board rev, fuse rev.
|
||||
|
||||
static const enum chipid_voltage_index s8000_cpu[] = {
|
||||
CHIPID_CPU_VOLTAGE_BYPASS,
|
||||
CHIPID_CPU_VOLTAGE_SECUREROM,
|
||||
CHIPID_CPU_VOLTAGE_396,
|
||||
CHIPID_CPU_VOLTAGE_600,
|
||||
CHIPID_CPU_VOLTAGE_912,
|
||||
CHIPID_CPU_VOLTAGE_1200,
|
||||
CHIPID_CPU_VOLTAGE_1512,
|
||||
CHIPID_CPU_VOLTAGE_1800,
|
||||
CHIPID_CPU_VOLTAGE_1848,
|
||||
CHIPID_CPU_VOLTAGE_396,
|
||||
CHIPID_CPU_VOLTAGE_396,
|
||||
CHIPID_CPU_VOLTAGE_396,
|
||||
CHIPID_CPU_VOLTAGE_396,
|
||||
CHIPID_CPU_VOLTAGE_1512_WA,
|
||||
CHIPID_CPU_VOLTAGE_1200_WA,
|
||||
CHIPID_CPU_VOLTAGE_396_WA,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8003_cpu[] = {
|
||||
CHIPID_CPU_VOLTAGE_BYPASS,
|
||||
CHIPID_CPU_VOLTAGE_SECUREROM,
|
||||
CHIPID_CPU_VOLTAGE_396,
|
||||
CHIPID_CPU_VOLTAGE_600,
|
||||
CHIPID_CPU_VOLTAGE_912,
|
||||
CHIPID_CPU_VOLTAGE_1200,
|
||||
CHIPID_CPU_VOLTAGE_1512,
|
||||
CHIPID_CPU_VOLTAGE_1800,
|
||||
CHIPID_CPU_VOLTAGE_1848,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8000a1_cpu[] = {
|
||||
CHIPID_CPU_VOLTAGE_BYPASS,
|
||||
CHIPID_CPU_VOLTAGE_SECUREROM,
|
||||
CHIPID_CPU_VOLTAGE_396,
|
||||
CHIPID_CPU_VOLTAGE_600,
|
||||
CHIPID_CPU_VOLTAGE_912,
|
||||
CHIPID_CPU_VOLTAGE_1200,
|
||||
CHIPID_CPU_VOLTAGE_1512,
|
||||
CHIPID_CPU_VOLTAGE_1800,
|
||||
CHIPID_CPU_VOLTAGE_1896,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8000_gpu[] = {
|
||||
CHIPID_GPU_VOLTAGE_OFF,
|
||||
CHIPID_GPU_VOLTAGE_340,
|
||||
CHIPID_GPU_VOLTAGE_474,
|
||||
CHIPID_GPU_VOLTAGE_550,
|
||||
CHIPID_GPU_VOLTAGE_723,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8003_gpu[] = {
|
||||
CHIPID_GPU_VOLTAGE_OFF,
|
||||
CHIPID_GPU_VOLTAGE_340,
|
||||
CHIPID_GPU_VOLTAGE_474,
|
||||
CHIPID_GPU_VOLTAGE_550,
|
||||
CHIPID_GPU_VOLTAGE_723,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8000a1_gpu[] = {
|
||||
CHIPID_GPU_VOLTAGE_OFF,
|
||||
CHIPID_GPU_VOLTAGE_340,
|
||||
CHIPID_GPU_VOLTAGE_474,
|
||||
CHIPID_GPU_VOLTAGE_550,
|
||||
CHIPID_GPU_VOLTAGE_616,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_cpu[] = {
|
||||
CHIPID_CPU_VOLTAGE_BYPASS,
|
||||
CHIPID_CPU_VOLTAGE_SECUREROM,
|
||||
CHIPID_CPU_VOLTAGE_396,
|
||||
CHIPID_CPU_VOLTAGE_720,
|
||||
CHIPID_CPU_VOLTAGE_1080,
|
||||
CHIPID_CPU_VOLTAGE_1440,
|
||||
CHIPID_CPU_VOLTAGE_1800,
|
||||
CHIPID_CPU_VOLTAGE_2160,
|
||||
CHIPID_CPU_VOLTAGE_2256_1core,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_gpu[] = {
|
||||
CHIPID_GPU_VOLTAGE_OFF,
|
||||
CHIPID_GPU_VOLTAGE_360,
|
||||
CHIPID_GPU_VOLTAGE_520,
|
||||
CHIPID_GPU_VOLTAGE_650,
|
||||
CHIPID_GPU_VOLTAGE_723,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8000_soc[] = {
|
||||
CHIPID_SOC_VOLTAGE_BYPASS,
|
||||
CHIPID_SOC_VOLTAGE_SECUREROM,
|
||||
CHIPID_SOC_VOLTAGE_VMIN,
|
||||
CHIPID_SOC_VOLTAGE_VNOM,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8003_soc[] = {
|
||||
CHIPID_SOC_VOLTAGE_BYPASS,
|
||||
CHIPID_SOC_VOLTAGE_SECUREROM,
|
||||
CHIPID_SOC_VOLTAGE_VMIN,
|
||||
CHIPID_SOC_VOLTAGE_VNOM,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_soc[] = {
|
||||
CHIPID_SOC_VOLTAGE_BYPASS,
|
||||
CHIPID_SOC_VOLTAGE_SECUREROM,
|
||||
CHIPID_SOC_VOLTAGE_VMIN,
|
||||
CHIPID_SOC_VOLTAGE_VMIN,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_j127_gpu[] = {
|
||||
CHIPID_GPU_VOLTAGE_OFF,
|
||||
CHIPID_GPU_VOLTAGE_360,
|
||||
CHIPID_GPU_VOLTAGE_520,
|
||||
CHIPID_GPU_VOLTAGE_650,
|
||||
CHIPID_GPU_VOLTAGE_723,
|
||||
CHIPID_GPU_VOLTAGE_804,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_j105_cpu[] = {
|
||||
CHIPID_CPU_VOLTAGE_BYPASS,
|
||||
CHIPID_CPU_VOLTAGE_SECUREROM,
|
||||
CHIPID_CPU_VOLTAGE_2256,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_j105_soc[] = {
|
||||
CHIPID_SOC_VOLTAGE_BYPASS,
|
||||
CHIPID_SOC_VOLTAGE_SECUREROM,
|
||||
CHIPID_SOC_VOLTAGE_VMIN,
|
||||
CHIPID_SOC_VOLTAGE_VMIN,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_j105_gpu[] = {
|
||||
CHIPID_GPU_VOLTAGE_OFF,
|
||||
CHIPID_GPU_VOLTAGE_723,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_j127_soc[] = {
|
||||
CHIPID_SOC_VOLTAGE_BYPASS,
|
||||
CHIPID_SOC_VOLTAGE_SECUREROM,
|
||||
CHIPID_SOC_VOLTAGE_VNOM,
|
||||
CHIPID_SOC_VOLTAGE_VNOM,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_j99a_soc[] = {
|
||||
CHIPID_SOC_VOLTAGE_BYPASS,
|
||||
CHIPID_SOC_VOLTAGE_SECUREROM,
|
||||
CHIPID_SOC_VOLTAGE_VMIN,
|
||||
CHIPID_SOC_VOLTAGE_VMIN,
|
||||
};
|
||||
|
||||
struct dvfmperf {
|
||||
uint32_t chip_id;
|
||||
uint32_t chip_rev;
|
||||
uint32_t board_id;
|
||||
const enum chipid_voltage_index *voltage_indexes;
|
||||
uint32_t size;
|
||||
};
|
||||
|
||||
|
||||
// The dvfmperfs arays must be sorted to have :
|
||||
// - BOARD_ID_NONE always coming last for chip/chip revision
|
||||
// - Highest chip revision coming first
|
||||
static const struct dvfmperf dvfmperfs_cpu[] = { // Entry with highest chip revision must come first
|
||||
{0x8000, CHIP_REVISION_B0, BOARD_ID_NONE, s8000_cpu, sizeof(s8000_cpu)/sizeof(s8000_cpu[0])},
|
||||
{0x8000, CHIP_REVISION_A1, BOARD_ID_NONE, s8000a1_cpu, sizeof(s8000a1_cpu)/sizeof(s8000a1_cpu[0])},
|
||||
{0x8003, CHIP_REVISION_A0, BOARD_ID_NONE, s8003_cpu, sizeof(s8003_cpu)/sizeof(s8003_cpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J105_AP_BOARD_ID, s8001_j105_cpu, sizeof(s8001_j105_cpu)/sizeof(s8001_j105_cpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J105_DEV_BOARD_ID, s8001_j105_cpu, sizeof(s8001_j105_cpu)/sizeof(s8001_j105_cpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, BOARD_ID_NONE, s8001_cpu, sizeof(s8001_cpu)/sizeof(s8000_cpu[0])},
|
||||
};
|
||||
|
||||
static const struct dvfmperf dvfmperfs_gpu[] = { // Entry with highest chip revision must come first
|
||||
{0x8000, CHIP_REVISION_B0, BOARD_ID_NONE, s8000_gpu, sizeof(s8000_gpu)/sizeof(s8000_gpu[0])},
|
||||
{0x8000, CHIP_REVISION_A1, BOARD_ID_NONE, s8000a1_gpu, sizeof(s8000a1_gpu)/sizeof(s8000a1_gpu[0])},
|
||||
{0x8003, CHIP_REVISION_A0, BOARD_ID_NONE, s8003_gpu, sizeof(s8003_gpu)/sizeof(s8003_gpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J128_AP_BOARD_ID, s8001_j127_gpu, sizeof(s8001_j127_gpu)/sizeof(s8001_j127_gpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J128_DEV_BOARD_ID, s8001_j127_gpu, sizeof(s8001_j127_gpu)/sizeof(s8001_j127_gpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J127_AP_BOARD_ID, s8001_j127_gpu, sizeof(s8001_j127_gpu)/sizeof(s8001_j127_gpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J127_DEV_BOARD_ID, s8001_j127_gpu, sizeof(s8001_j127_gpu)/sizeof(s8001_j127_gpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J105_AP_BOARD_ID, s8001_j105_gpu, sizeof(s8001_j105_gpu)/sizeof(s8001_j105_gpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J105_DEV_BOARD_ID, s8001_j105_gpu, sizeof(s8001_j105_gpu)/sizeof(s8001_j105_gpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, BOARD_ID_NONE, s8001_gpu, sizeof(s8001_gpu)/sizeof(s8001_gpu[0])},
|
||||
};
|
||||
|
||||
static const struct dvfmperf dvfmperfs_soc[] = { // Entry with highest chip revision must come first
|
||||
{0x8000, CHIP_REVISION_B0, BOARD_ID_NONE, s8000_soc, sizeof(s8000_soc)/sizeof(s8000_soc[0])},
|
||||
{0x8003, CHIP_REVISION_A0, BOARD_ID_NONE, s8003_soc, sizeof(s8003_soc)/sizeof(s8003_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J105_AP_BOARD_ID, s8001_j105_soc, sizeof(s8001_j105_soc)/sizeof(s8001_j105_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J105_DEV_BOARD_ID, s8001_j105_soc, sizeof(s8001_j105_soc)/sizeof(s8001_j105_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J128_AP_BOARD_ID, s8001_j127_soc, sizeof(s8001_j127_soc)/sizeof(s8001_j127_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J128_DEV_BOARD_ID, s8001_j127_soc, sizeof(s8001_j127_soc)/sizeof(s8001_j127_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J127_AP_BOARD_ID, s8001_j127_soc, sizeof(s8001_j127_soc)/sizeof(s8001_j127_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J127_DEV_BOARD_ID, s8001_j127_soc, sizeof(s8001_j127_soc)/sizeof(s8001_j127_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J99A_AP_BOARD_ID, s8001_j99a_soc, sizeof(s8001_j99a_soc)/sizeof(s8001_j99a_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J99A_DEV_BOARD_ID, s8001_j99a_soc, sizeof(s8001_j99a_soc)/sizeof(s8001_j99a_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J98A_AP_BOARD_ID, s8001_j99a_soc, sizeof(s8001_j99a_soc)/sizeof(s8001_j99a_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J98A_DEV_BOARD_ID, s8001_j99a_soc, sizeof(s8001_j99a_soc)/sizeof(s8001_j99a_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, BOARD_ID_NONE, s8001_soc, sizeof(s8001_soc)/sizeof(s8001_soc[0])},
|
||||
};
|
||||
|
||||
enum chipid_voltage_index dvfmperf_get_voltage_index(uint32_t index, enum chipid_voltage_type voltage_type)
|
||||
{
|
||||
const struct dvfmperf *dvfmperfs;
|
||||
enum chipid_voltage_index voltage_index_for_filling;
|
||||
uint32_t chip_id = chipid_get_chip_id();
|
||||
uint32_t chip_rev = chipid_get_chip_revision();
|
||||
uint32_t board_id = platform_get_board_id();
|
||||
uint32_t i;
|
||||
uint32_t size = 0;
|
||||
|
||||
switch (voltage_type) {
|
||||
case CHIPID_CPU_VOLTAGE:
|
||||
dvfmperfs = dvfmperfs_cpu;
|
||||
voltage_index_for_filling = CHIPID_CPU_VOLTAGE_396;
|
||||
size = sizeof(dvfmperfs_cpu)/sizeof(dvfmperfs_cpu[0]);
|
||||
break;
|
||||
case CHIPID_GPU_VOLTAGE:
|
||||
dvfmperfs = dvfmperfs_gpu;
|
||||
size = sizeof(dvfmperfs_gpu)/sizeof(dvfmperfs_gpu[0]);
|
||||
voltage_index_for_filling = CHIPID_GPU_VOLTAGE_OFF;
|
||||
break;
|
||||
case CHIPID_SOC_VOLTAGE:
|
||||
dvfmperfs = dvfmperfs_soc;
|
||||
size = sizeof(dvfmperfs_soc)/sizeof(dvfmperfs_soc[0]);
|
||||
break;
|
||||
default:
|
||||
panic("Invalid voltage type\n");
|
||||
voltage_index_for_filling = CHIPID_GPU_VOLTAGE_OFF; // prevent compiler warning
|
||||
dvfmperfs = NULL; // Prevent compiler warning
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (chip_id != dvfmperfs[i].chip_id) {
|
||||
continue;
|
||||
}
|
||||
if (chip_rev < dvfmperfs[i].chip_rev) {
|
||||
continue;
|
||||
}
|
||||
if ((board_id != dvfmperfs[i].board_id) && (dvfmperfs[i].board_id != BOARD_ID_NONE)) {
|
||||
continue;
|
||||
}
|
||||
if (index >= dvfmperfs[i].size) {
|
||||
if (voltage_type == CHIPID_SOC_VOLTAGE) {
|
||||
if (dvfmperfs[i].size < 4) {
|
||||
panic("Invalid number of SOC perf states");
|
||||
}
|
||||
voltage_index_for_filling = dvfmperfs[i].voltage_indexes[2];
|
||||
}
|
||||
return voltage_index_for_filling;
|
||||
}
|
||||
return dvfmperfs[i].voltage_indexes[index];
|
||||
}
|
||||
panic("Unknown voltage for current chip\n");
|
||||
return CHIPID_GPU_VOLTAGE_OFF; // Never reach this code
|
||||
}
|
||||
@@ -0,0 +1,210 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is only a database of the frequencies used by CPU and GPU, it has no access
|
||||
* To the chip.
|
||||
*/
|
||||
#include <platform.h>
|
||||
#include <platform/soc/operating_point.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
|
||||
#define CHIP_ID_ALL 0
|
||||
#define DELIMITER CHIPID_ALL_VOLTAGE_LAST
|
||||
|
||||
static const struct operating_point_params operating_point_params[] = {
|
||||
// GPU
|
||||
{.chipid_max = DELIMITER, .chip_id = 0x8000, .voltage_type = CHIPID_GPU_VOLTAGE},
|
||||
// P M S
|
||||
// | | |
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_OFF,0,0, 0, 0, 0}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_340,0,0, 2,170, 5}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_474,0,0, 2,158, 3}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_550,0,0, 3,275, 3}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_616,0,0, 3,154, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_723,0,0, 1, 90, 2}}}, // It's 720 now for <rdar://problem/22294854> Change GPU & SoC PLL settings to recover yield
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_804,0,0, 1, 67, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_850,0,0, 6,425, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_900,0,0, 1, 75, 1}}},
|
||||
|
||||
{.chipid_max = DELIMITER, .chip_id = 0x8003, .voltage_type = CHIPID_GPU_VOLTAGE},
|
||||
// P M S
|
||||
// | | |
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_OFF,0,0, 0, 0, 0}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_340,0,0, 2, 85, 2}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_474,0,0, 2, 79, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_550,0,0, 4,275, 2}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_723,0,0, 4,241, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_804,0,0, 1, 67, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_850,0,0, 6,425, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_900,0,0, 1, 75, 1}}},
|
||||
|
||||
{.chipid_max = DELIMITER, .chip_id = 0x8001, .voltage_type = CHIPID_GPU_VOLTAGE},
|
||||
// P M S
|
||||
// | | |
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_OFF,0,0, 0, 0, 0}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_360,0,0, 1, 60, 3}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_520,0,0, 1, 65, 2}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_650,0,0, 6,325, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_723,0,0, 4,241, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_800,0,0, 3,100, 0}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_804,0,0, 1, 67, 1}}},
|
||||
|
||||
|
||||
// S8000 B0
|
||||
{.chipid_max = DELIMITER, .chip_id = 0x8000, .voltage_type = CHIPID_CPU_VOLTAGE, .chip_rev = CHIP_REVISION_B0},
|
||||
// bypass
|
||||
// | clkSrc
|
||||
// | | P M S biuDiv4HiVol
|
||||
// | | | | | | biuDiv4LoVol
|
||||
// | | | | | | | dvmrMaxWgt
|
||||
// | | | | | | | | iexrfCfgWrData
|
||||
// | | | | | | | | | iexrfCfgWrIdxa
|
||||
// | | | | | | | | | | iexrfCfgWrIdxb
|
||||
// | | | | | | | | | | | exrfCfgWrIdxmuxsel
|
||||
// | | | | | | | | | | | | nrgAccScaleTab(Ext)
|
||||
// | | | | | | | | | | | | | lkgEstTab(Ext)
|
||||
// | | | | | | | | | | | | | | dpe0DvfmTab(Ext)
|
||||
// | | | | | | | | | | | | | | |
|
||||
{{{CHIPID_CPU_VOLTAGE_BYPASS, 0, 0, 0, 0, 0, 2, 2, 0xf, 1, 0, 0, 0, 0x1, 0x1, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_SECUREROM,1, 1, 1, 50, 3, 2, 2, 0xf, 1, 0, 0, 0, 0x1, 0x1, 0xff}}}, // 300MHz
|
||||
{{{CHIPID_CPU_VOLTAGE_396, 0, 1, 1, 66, 3, 2, 2, 0xf, 1, 0, 0, 0, 0x37, 0x30, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_600, 0, 1, 1, 75, 2, 2, 3, 0xf, 1, 0, 0, 0, 0x3e, 0x1f, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_912, 0, 1, 1, 76, 1, 4, 4, 0xf, 1, 0, 0, 0, 0x53, 0x14, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1200, 0, 1, 1, 50, 0, 4, 5, 0xf, 1, 0, 0, 0, 0x66, 0x0f, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1512, 0, 1, 1, 63, 0, 5, 6, 0xf, 1, 0, 0, 0, 0x88, 0x0c, 0xd7}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1800, 0, 1, 1, 75, 0, 6, 7, 0xf, 1, 0, 0, 0, 0xbf, 0x0b, 0x97}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1848, 0, 1, 1, 77, 0, 6, 7, 0x2, 1, 0, 0, 0, 0xbf, 0x0a, 0x93}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1896, 0, 1, 1, 79, 0, 6, 7, 0x2, 1, 0, 0, 0, 0xc5, 0x16, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1992, 0, 1, 1, 83, 0, 6, 7, 0xf, 1, 0, 0, 0, 0xc8, 0x15, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_2112, 0, 1, 1, 88, 0, 7, 0, 0x2, 1, 0, 0, 0, 0xc8, 0x14, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_396_WA, 0, 1, 1, 82, 4, 2, 2, 0xf, 1, 0, 0, 0, 0x37, 0x30, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1200_WA, 0, 1, 1, 76, 1, 4, 5, 0xf, 1, 0, 0, 0, 0x66, 0x0f, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1512_WA, 0, 1, 1, 76, 1, 5, 6, 0xf, 1, 0, 0, 0, 0x88, 0x0c, 0xd7}}},
|
||||
|
||||
// S8000 A1
|
||||
{.chipid_max = DELIMITER, .chip_id = 0x8000, .voltage_type = CHIPID_CPU_VOLTAGE},
|
||||
// bypass
|
||||
// | clkSrc
|
||||
// | | P M S biuDiv4HiVol
|
||||
// | | | | | | biuDiv4LoVol
|
||||
// | | | | | | | dvmrMaxWgt
|
||||
// | | | | | | | | iexrfCfgWrData
|
||||
// | | | | | | | | | iexrfCfgWrIdxa
|
||||
// | | | | | | | | | | iexrfCfgWrIdxb
|
||||
// | | | | | | | | | | | exrfCfgWrIdxmuxsel
|
||||
// | | | | | | | | | | | | nrgAccScaleTab(Ext)
|
||||
// | | | | | | | | | | | | | lkgEstTab(Ext)
|
||||
// | | | | | | | | | | | | | | dpe0DvfmTab(Ext)
|
||||
// | | | | | | | | | | | | | | |
|
||||
{{{CHIPID_CPU_VOLTAGE_BYPASS, 0, 0, 0, 0, 0, 2, 2, 0xf, 0, 0, 0, 0, 0x1, 0x1, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_SECUREROM,1, 1, 1, 50, 3, 2, 2, 0xf, 0, 0, 0, 0, 0x1, 0x1, 0xff}}}, // 300MHz
|
||||
{{{CHIPID_CPU_VOLTAGE_396, 0, 1, 1, 66, 3, 2, 2, 0xf, 0, 0, 0, 0, 0x3e, 0x46, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_600, 0, 1, 1, 50, 1, 2, 3, 0xf, 0, 0, 0, 0, 0x44, 0x2f, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_912, 0, 1, 1, 76, 1, 4, 4, 0xf, 0, 0, 0, 0, 0x5b, 0x1d, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1200, 0, 1, 1, 50, 0, 4, 5, 0xf, 0, 0, 0, 0, 0x74, 0x16, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1512, 0, 1, 1, 63, 0, 5, 6, 0xf, 0, 0, 0, 0, 0x91, 0x11, 0xd7}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1800, 0, 1, 1, 75, 0, 6, 7, 0xf, 0, 0, 0, 0, 0xaf, 0x0f, 0x97}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1896, 0, 1, 1, 79, 0, 6, 7, 0x2, 0, 0, 0, 0, 0xbc, 0x0e, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1992, 0, 1, 1, 83, 0, 6, 7, 0xf, 0, 0, 0, 0, 0xc8, 0x0d, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_2112, 0, 1, 1, 88, 0, 7, 0, 0x2, 0, 0, 0, 0, 0xc8, 0x0c, 0xff}}},
|
||||
|
||||
// S8001
|
||||
{.chipid_max = DELIMITER, .chip_id = 0x8001, .voltage_type = CHIPID_CPU_VOLTAGE},
|
||||
// bypass
|
||||
// | clkSrc
|
||||
// | | P M S biuDiv4HiVol
|
||||
// | | | | | | biuDiv4LoVol
|
||||
// | | | | | | | dvmrMaxWgt
|
||||
// | | | | | | | | iexrfCfgWrData
|
||||
// | | | | | | | | | iexrfCfgWrIdxa
|
||||
// | | | | | | | | | | iexrfCfgWrIdxb
|
||||
// | | | | | | | | | | | exrfCfgWrIdxmuxsel
|
||||
// | | | | | | | | | | | | nrgAccScaleTab(Ext)
|
||||
// | | | | | | | | | | | | | lkgEstTab(Ext)
|
||||
// | | | | | | | | | | | | | | dpe0DvfmTab(Ext)
|
||||
// | | | | | | | | | | | | | | |
|
||||
{{{CHIPID_CPU_VOLTAGE_BYPASS, 0, 0, 0, 0, 0, 2, 2, 0xf, 0, 0, 0, 0, 0x1, 0x1, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_SECUREROM,1, 1, 1, 75, 6, 2, 2, 0xf, 0, 0, 0, 0, 0x1, 0x1, 0xff}}}, // 300MHz
|
||||
{{{CHIPID_CPU_VOLTAGE_396, 0, 1, 1, 66, 3, 2, 2, 0xf, 0, 0, 0, 0, 0x3d, 0x2b, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_720, 0, 1, 1, 90, 2, 2, 2, 0xf, 0, 0, 0, 0, 0x4a, 0x17, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1080, 0, 1, 1, 90, 1, 3, 3, 0xf, 0, 0, 0, 0, 0x58, 0x0e, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1440, 0, 1, 1, 60, 0, 4, 4, 0xf, 0, 0, 0, 0, 0x6b, 0x0a, 0xfb}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1800, 0, 1, 1, 75, 0, 5, 5, 0xf, 0, 0, 0, 0, 0x99, 0x08, 0xa8}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_2160, 0, 1, 1, 90, 0, 5, 5, 0xf, 0, 0, 0, 0, 0xc1, 0x06, 0x7c}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_2256_1core,0,1, 1, 94, 0, 5, 5, 0x2, 0, 0, 0, 0, 0xc1, 0x06, 0x77}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_2256, 0, 1, 1, 94, 0, 5, 5, 0xf, 0, 0, 0, 0, 0xc1, 0x06, 0x77}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_2352, 0, 1, 1, 98, 0, 5, 5, 0xf, 0, 0, 0, 0, 0xe0, 0x0d, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_2448, 0, 1, 1, 102,0, 6, 6, 0x2, 0, 0, 0, 0, 0xe0, 0x0d, 0xff}}},
|
||||
|
||||
// S8003
|
||||
{.chipid_max = DELIMITER, .chip_id = 0x8003, .voltage_type = CHIPID_CPU_VOLTAGE},
|
||||
// bypass
|
||||
// | clkSrc
|
||||
// | | P M S biuDiv4HiVol
|
||||
// | | | | | | biuDiv4LoVol
|
||||
// | | | | | | | dvmrMaxWgt
|
||||
// | | | | | | | | iexrfCfgWrData
|
||||
// | | | | | | | | | iexrfCfgWrIdxa
|
||||
// | | | | | | | | | | iexrfCfgWrIdxb
|
||||
// | | | | | | | | | | | exrfCfgWrIdxmuxsel
|
||||
// | | | | | | | | | | | | nrgAccScaleTab(Ext)
|
||||
// | | | | | | | | | | | | | lkgEstTab(Ext)
|
||||
// | | | | | | | | | | | | | | dpe0DvfmTab(Ext)
|
||||
// | | | | | | | | | | | | | | |
|
||||
{{{CHIPID_CPU_VOLTAGE_BYPASS, 0, 0, 0, 0, 0, 2, 2, 0xf, 0, 0, 0, 0, 0x1, 0x1, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_SECUREROM,1, 1, 1, 75, 6, 2, 2, 0xf, 0, 0, 0, 0, 0x1, 0x1, 0xff}}}, // 300MHz
|
||||
{{{CHIPID_CPU_VOLTAGE_396, 0, 1, 1, 66, 3, 2, 2, 0xf, 0, 0, 0, 0, 0x3a, 0x2c, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_600, 0, 1, 1, 75, 2, 2, 3, 0xf, 0, 0, 0, 0, 0x40, 0x1c, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_912, 0, 1, 1, 76, 1, 4, 4, 0xf, 0, 0, 0, 0, 0x4f, 0x11, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1200, 0, 1, 1,100, 1, 4, 5, 0xf, 0, 0, 0, 0, 0x5e, 0x0d, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1512, 0, 1, 1, 63, 0, 5, 6, 0xf, 0, 0, 0, 0, 0x73, 0x0a, 0xe7}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1800, 0, 1, 1, 75, 0, 6, 7, 0xf, 0, 0, 0, 0, 0x82, 0x08, 0xb6}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1848, 0, 1, 1, 77, 0, 6, 7, 0x2, 0, 0, 0, 0, 0x82, 0x08, 0xb1}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1896, 0, 1, 1, 79, 0, 6, 7, 0xf, 0, 0, 0, 0, 0xa7, 0x10, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1992, 0, 1, 1, 83, 0, 6, 7, 0xf, 0, 0, 0, 0, 0xb2, 0x10, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_2112, 0, 1, 1, 88, 0, 7, 0, 0x2, 0, 0, 0, 0, 0xbf, 0x0f, 0xff}}},
|
||||
};
|
||||
|
||||
const struct operating_point_params *operating_point_get_params(enum chipid_voltage_index voltage_index, enum chipid_voltage_type voltage_type)
|
||||
{
|
||||
uint64_t chip_id = chipid_get_chip_id();
|
||||
uint64_t chip_rev = chipid_get_chip_revision();
|
||||
uint64_t chip_id_in_array = 0;
|
||||
uint64_t chip_rev_in_array = 0;
|
||||
size_t size = sizeof(operating_point_params)/sizeof(operating_point_params[0]);
|
||||
enum chipid_voltage_type voltage_type_in_array = CHIPID_CPU_VOLTAGE;
|
||||
|
||||
size_t found = size;
|
||||
for (size_t i = 0; i < size; i++) {
|
||||
if (operating_point_params[i].voltage_index == DELIMITER) {
|
||||
chip_id_in_array = operating_point_params[i].chip_id;
|
||||
chip_rev_in_array = operating_point_params[i].chip_rev;
|
||||
voltage_type_in_array = operating_point_params[i].voltage_type;
|
||||
continue;
|
||||
}
|
||||
if ((voltage_type_in_array != voltage_type)) {
|
||||
continue;
|
||||
}
|
||||
if (chip_rev_in_array > chip_rev) {
|
||||
continue;
|
||||
}
|
||||
if ((operating_point_params[i].voltage_index == voltage_index) && ((chip_id_in_array == CHIP_ID_ALL) || (chip_id_in_array == chip_id))) {
|
||||
found = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (found == size) {
|
||||
panic("%s Index %d not found for chipId 0x%llx\n",
|
||||
__func__, voltage_index, chip_id);
|
||||
}
|
||||
return &operating_point_params[found];
|
||||
}
|
||||
@@ -0,0 +1,385 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
//
|
||||
// Please update test plan version to know what is the reference.
|
||||
//
|
||||
// Maui Test Plan Version 2.26
|
||||
// Maui Tunables Specification Revision 0.80
|
||||
//
|
||||
|
||||
#include <platform/pmgr.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
|
||||
//
|
||||
// Fuses in MINIPMGR are linearly mapped
|
||||
//
|
||||
static const struct pmgr_binning_fuse_to_register minipmgr_fuse_register[] = {
|
||||
// binning_low
|
||||
// | binning_high
|
||||
// | | register_low
|
||||
// | | | register_64bit
|
||||
// | | | | register_address
|
||||
// | | | | |
|
||||
{ 0, 369, 0, 0, AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE0_OFFSET},
|
||||
{ 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
//
|
||||
// Fuses in ACC (UDR) are sparsely mapped
|
||||
//
|
||||
static const struct pmgr_binning_fuse_to_register acc_fuse_register[] = {
|
||||
// binning_low
|
||||
// | binning_high
|
||||
// | | register_low
|
||||
// | | | register_64bit
|
||||
// | | | | register_address
|
||||
// | | | | |
|
||||
{ 0, 2, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST0_EXT2_OFFSET},
|
||||
{ 3, 6, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST0_EXT2_OFFSET},
|
||||
{ 7, 9, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST1_EXT2_OFFSET},
|
||||
{ 10, 13, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST1_EXT2_OFFSET},
|
||||
{ 14, 16, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST2_EXT2_OFFSET},
|
||||
{ 17, 20, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST2_EXT2_OFFSET},
|
||||
{ 21, 23, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST3_EXT2_OFFSET},
|
||||
{ 24, 27, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST3_EXT2_OFFSET},
|
||||
{ 28, 30, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST4_EXT2_OFFSET},
|
||||
{ 31, 34, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST4_EXT2_OFFSET},
|
||||
{ 35, 37, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST5_EXT2_OFFSET},
|
||||
{ 38, 41, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST5_EXT2_OFFSET},
|
||||
{ 42, 44, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST6_EXT2_OFFSET},
|
||||
{ 45, 48, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST6_EXT2_OFFSET},
|
||||
{ 40, 51, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST7_EXT2_OFFSET},
|
||||
{ 52, 55, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST7_EXT2_OFFSET},
|
||||
{ 56, 58, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST8_EXT2_OFFSET},
|
||||
{ 59, 62, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST8_EXT2_OFFSET},
|
||||
{ 112, 114,29, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 115, 119,24, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 120, 127,16, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
|
||||
const struct pmgr_binning_mode_to_fuse pmgr_binning_mode_to_fuse_data[] = {
|
||||
//
|
||||
// CPU
|
||||
//
|
||||
|
||||
//type
|
||||
//| mode
|
||||
//| | bingroup
|
||||
//| | | low
|
||||
//| | | | high
|
||||
//| | | | | fuse_to_register
|
||||
//| | | | | |
|
||||
{PMGR_BINNING_CPU, 1, PMGR_BINNING_GROUP_ALL, 7, 13, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 2, PMGR_BINNING_GROUP_ALL, 14, 20, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 3, PMGR_BINNING_GROUP_ALL, 21, 27, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 4, PMGR_BINNING_GROUP_ALL, 28, 34, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 5, PMGR_BINNING_GROUP_ALL, 35, 41, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 6, PMGR_BINNING_GROUP_ALL, 42, 48, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 7, PMGR_BINNING_GROUP_ALL, 49, 55, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 8, PMGR_BINNING_GROUP_ALL, 56, 62, acc_fuse_register},
|
||||
|
||||
//
|
||||
// GPU/SOC
|
||||
//
|
||||
|
||||
//type
|
||||
//| mode
|
||||
//| | bingroup
|
||||
//| | | low
|
||||
//| | | | high
|
||||
//| | | | | fuse_to_register
|
||||
//| | | | | |
|
||||
{PMGR_BINNING_GPU, 1, PMGR_BINNING_GROUP_ALL, 238, 244, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 2, PMGR_BINNING_GROUP_ALL, 245, 251, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 3, PMGR_BINNING_GROUP_ALL, 252, 258, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 4, PMGR_BINNING_GROUP_ALL, 259, 265, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 5, PMGR_BINNING_GROUP_ALL, 217, 223, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_SOC, 1, PMGR_BINNING_GROUP_ALL, 224, 230, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_SOC, 2, PMGR_BINNING_GROUP_ALL, 231, 237, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_BASE, 0, PMGR_BINNING_GROUP_ALL, 115, 119, acc_fuse_register},
|
||||
|
||||
{PMGR_BINNING_REV, 0, PMGR_BINNING_GROUP_ALL, 142, 147, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_GROUP, 0, PMGR_BINNING_GROUP_ALL, 268, 269, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_END_OF_LIST, 0, PMGR_BINNING_GROUP_ALL, 0, 0, NULL},
|
||||
};
|
||||
|
||||
//
|
||||
// Group-specific entries must come before the corresponding entry with PMGR_BINNING_GROUP_ALL.
|
||||
//
|
||||
const struct pmgr_binning_voltage_index_to_config pmgr_binning_voltage_index_to_config_data[] = {
|
||||
// voltage index
|
||||
// | safe voltage
|
||||
// | | mode
|
||||
// | | | type
|
||||
// | | | | binning group
|
||||
// | | | | | fuse revision minimun
|
||||
// | | | | | |
|
||||
{CHIPID_CPU_VOLTAGE_BYPASS, 610, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_SECUREROM, 610, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_396, 610, 1, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_600, 641, 2, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_912, 742, 3, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1200, 836, 4, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1512, 937, 5, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1800, 1090, 6, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1848, 1090, 6, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1896, 1090, 7, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1992, 1100, 8, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
{CHIPID_CPU_VOLTAGE_396_WA, 610, 1, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1200_WA, 836, 4, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1512_WA, 937, 5, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
// SEG-characterization
|
||||
{CHIPID_CPU_VOLTAGE_2112, 1100, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
{CHIPID_SOC_VOLTAGE_BYPASS, 725, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_SOC_VOLTAGE_SECUREROM, 725, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_SOC_VOLTAGE_VMIN, 725, 1, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_SOC_VOLTAGE_VNOM, 825, 2, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
{CHIPID_GPU_VOLTAGE_OFF, 0, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_340, 700, 1, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_474, 800, 2, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_550, 920, 3, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_616, 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_723, 1030, 4, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
// SEG-characterization
|
||||
{CHIPID_GPU_VOLTAGE_804, 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_850, 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_900, 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
};
|
||||
|
||||
//
|
||||
// Safe voltage of 0 and binning mode != PMGR_BINNING_MODE_NONE
|
||||
// means data are store in pmgr_binning_mode_to_const_data
|
||||
//
|
||||
const struct pmgr_binning_voltage_config pmgr_binning_voltage_config_sram_data[] = {
|
||||
// safe voltage (0 means lookup data in pmgr_binning_mode_to_const_data)
|
||||
// | mode
|
||||
// | | type
|
||||
// | | |
|
||||
[CHIPID_CPU_VOLTAGE_BYPASS] = { 800, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_SECUREROM] = { 800, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_396] = { 0, 1, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_600] = { 0, 2, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_912] = { 0, 3, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1200] = { 0, 4, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1512] = { 0, 5, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1800] = { 0, 6, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1848] = { 0, 6, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1896] = {1090, 7, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1992] = {1100, 8, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_2112] = {1100, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_396_WA] = { 0, 1, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1200_WA] = { 0, 4, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1512_WA] = { 0, 5, PMGR_BINNING_CPU_SRAM},
|
||||
|
||||
[CHIPID_GPU_VOLTAGE_OFF] = { 0, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_340] = { 0, 1, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_474] = { 0, 2, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_550] = { 0, 3, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_616] = { 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_723] = { 0, 4, PMGR_BINNING_GPU_SRAM},
|
||||
// SEG-characterization
|
||||
[CHIPID_GPU_VOLTAGE_804] = { 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_850] = { 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_900] = { 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
|
||||
[CHIPID_VOLTAGE_FIXED] = {850, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SRAM},
|
||||
};
|
||||
|
||||
//
|
||||
// Group-specific entries must come before the corresponding entry with PMGR_BINNING_GROUP_ALL.
|
||||
//
|
||||
const struct pmgr_binning_mode_to_const pmgr_binning_mode_to_const_data[] = {
|
||||
// Voltage
|
||||
// | Mode
|
||||
// | | Type
|
||||
// | | | Binning group
|
||||
// | | | | fuse revision minimun
|
||||
// | | | | |
|
||||
{ 810, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_N69U, 15},
|
||||
{ 940, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_N69U, 15},
|
||||
{1055, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_N69U, 15},
|
||||
|
||||
{ 830, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 9},
|
||||
{ 960, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 9},
|
||||
{1025, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 9},
|
||||
|
||||
{ 840, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
|
||||
{ 940, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
|
||||
{1030, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
|
||||
|
||||
{ 800, 1, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 2, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 3, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 836, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 937, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1090, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
{ 830, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69U, 15},
|
||||
{ 855, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69U, 15},
|
||||
{ 965, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69U, 15},
|
||||
|
||||
{ 820, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 9},
|
||||
{ 835, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 9},
|
||||
{ 955, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 9},
|
||||
|
||||
// GPU fuse rev 8 GPU_SRAM = fuse rev 0 (safe voltage)
|
||||
|
||||
{ 800, 1, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 920, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1030, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
};
|
||||
|
||||
static const struct pmgr_binning_voltage_index_to_offset n69u_cpu_offsets[] = {
|
||||
// voltage index
|
||||
// | fuse revision minimum
|
||||
// | | offset
|
||||
// | | |
|
||||
{CHIPID_CPU_VOLTAGE_912, 0, 25},
|
||||
{CHIPID_CPU_VOLTAGE_1200, 0, 15},
|
||||
{CHIPID_CPU_VOLTAGE_1200_WA, 0, 15},
|
||||
};
|
||||
|
||||
static const struct pmgr_binning_voltage_index_to_offset n69u_gpu_offsets[] = {
|
||||
// voltage index
|
||||
// | fuse revision minimum
|
||||
// | | offset
|
||||
// | | |
|
||||
{CHIPID_GPU_VOLTAGE_550, 0, 20},
|
||||
{CHIPID_GPU_VOLTAGE_723, 0, 30},
|
||||
};
|
||||
|
||||
const struct pmgr_binning_board_id_to_offsets pmgr_binning_board_id_to_offsets_data[] = {
|
||||
// type
|
||||
// | voltage offset array
|
||||
// | | voltage offset array size
|
||||
// | | | chip rev
|
||||
// | | | | board id
|
||||
// | | | | | binning group
|
||||
// | | | | | |
|
||||
{PMGR_BINNING_CPU, n69u_cpu_offsets, sizeof(n69u_cpu_offsets)/sizeof(n69u_cpu_offsets[0]), CHIP_REVISION_C0, N69U_AP_BOARD_ID, PMGR_BINNING_GROUP_ALL},
|
||||
{PMGR_BINNING_CPU, n69u_cpu_offsets, sizeof(n69u_cpu_offsets)/sizeof(n69u_cpu_offsets[0]), CHIP_REVISION_C0, N69U_DEV_BOARD_ID, PMGR_BINNING_GROUP_ALL},
|
||||
{PMGR_BINNING_GPU, n69u_gpu_offsets, sizeof(n69u_gpu_offsets)/sizeof(n69u_gpu_offsets[0]), CHIP_REVISION_C0, N69U_AP_BOARD_ID, PMGR_BINNING_NOTFOUND},
|
||||
{PMGR_BINNING_GPU, n69u_gpu_offsets, sizeof(n69u_gpu_offsets)/sizeof(n69u_gpu_offsets[0]), CHIP_REVISION_C0, N69U_DEV_BOARD_ID, PMGR_BINNING_NOTFOUND},
|
||||
};
|
||||
|
||||
// .voltages = {volAdj0, volAdj1, volAdj2, volAdj3, dvfmMaxAdj, dvmrAdj0, dvmrAdj1, dvmrAdj2}
|
||||
|
||||
const struct pmgr_binning_voltadj_entry pmgr_binning_voltadj_entry_data[] = {
|
||||
//
|
||||
// CPU
|
||||
//
|
||||
{CHIPID_CPU_VOLTAGE_BYPASS, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_SOC_VOLTAGE_SECUREROM, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 0, 0, 0, 0}},
|
||||
|
||||
//
|
||||
// volAdj0
|
||||
// | volAdj1
|
||||
// | | volAdj2
|
||||
// | | | volAdj3
|
||||
// | | | | dvfmMaxAdj
|
||||
// | | | | | dvmrAdj0
|
||||
// | | | | | | dvmrAdj1
|
||||
// | | | | | | | dvmrAdj2
|
||||
// | | | | | | | |
|
||||
// S8000 >= C0 (fuse rev >= 10) | | | | | | | |
|
||||
{CHIPID_CPU_VOLTAGE_396, CHIP_REVISION_B0,10, .voltages = { 0, 9375, 18750, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_396_WA,CHIP_REVISION_B0,10,.voltages = { 0, 9375, 18750, 18750, 40625, 0, 0, 0}},
|
||||
// | | | | | | | |
|
||||
// S8000 >= B0 | | | | | | | |
|
||||
{CHIPID_CPU_VOLTAGE_396, CHIP_REVISION_B0, 0, .voltages = { 0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_600, CHIP_REVISION_B0, 0, .voltages = { 0, 3125, 21875, 21875, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_912, CHIP_REVISION_B0, 0, .voltages = { 0, 3125, 18750, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1200, CHIP_REVISION_B0, 0, .voltages = { 0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1512, CHIP_REVISION_B0, 0, .voltages = { 0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1800, CHIP_REVISION_B0, 0, .voltages = { 28125, 28125, 0, 0, 40625, 12500, 12500, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1848, CHIP_REVISION_B0, 0, .voltages = { 28125, 28125, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_396_WA,CHIP_REVISION_B0,0, .voltages = { 0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1200_WA,CHIP_REVISION_B0,0,.voltages = { 0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1512_WA,CHIP_REVISION_B0,0,.voltages = { 0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
|
||||
// S8000 >= A1
|
||||
{CHIPID_CPU_VOLTAGE_396, CHIP_REVISION_A1, 0, .voltages = {0, 9375, 18750, 25000, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_600, CHIP_REVISION_A1, 0, .voltages = {0, 9375, 18750, 25000, 40625, 3125, 3125, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_912, CHIP_REVISION_A1, 0, .voltages = {0, 6250, 12500, 18750, 40625, 6250, 6250, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1200, CHIP_REVISION_A1, 0, .voltages = {0, 6250, 12500, 18750, 40625, 9375, 9375, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1512, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0, 40625, 18750,15625, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_1800, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0, 40625, 25000,21875, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_1896, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0, 40625, 3125, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1992, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0, 40625, 28125,25000, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_2112, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0, 40625, 3125, 0, 0}},
|
||||
|
||||
// S8000 A0
|
||||
{CHIPID_CPU_VOLTAGE_396, CHIP_REVISION_A0, 0, .voltages = {0, 9375, 18750, 25000, 40620, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_600, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 0, 0, 0, 0}},
|
||||
|
||||
//
|
||||
// SOC
|
||||
//
|
||||
// volAdj0
|
||||
// | volAdj1
|
||||
// | | volAdj2
|
||||
// | | | volAdj3
|
||||
// | | | | N/A
|
||||
// | | | | | N/A
|
||||
// | | | | | | N/A
|
||||
// | | | | | | | N/A
|
||||
// | | | | | | | |
|
||||
{CHIPID_SOC_VOLTAGE_VMIN, CHIP_REVISION_B0, 0, .voltages = {0, 0, 18750, 18750,0,0,0,0}},
|
||||
{CHIPID_SOC_VOLTAGE_VNOM, CHIP_REVISION_B0, 0, .voltages = {0, 0, 12500, 12500,0,0,0,0}},
|
||||
|
||||
{CHIPID_SOC_VOLTAGE_VMIN, CHIP_REVISION_A0, 0, .voltages = {0, 12500, 25000, 25000,0,0,0,0}},
|
||||
{CHIPID_SOC_VOLTAGE_VNOM, CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 12500,0,0,0,0}},
|
||||
{CHIPID_SOC_VOLTAGE_BYPASS,CHIP_REVISION_A0,0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
{CHIPID_SOC_VOLTAGE_SECUREROM,CHIP_REVISION_A0,0,.voltages={0, 0, 0, 0,0,0,0,0}},
|
||||
|
||||
//
|
||||
// GFX
|
||||
//
|
||||
// volAdj0
|
||||
// | volAdj1
|
||||
// | | volAdj2
|
||||
// | | | volAdj3
|
||||
// | | | | N/A
|
||||
// | | | | | N/A
|
||||
// | | | | | | N/A
|
||||
// | | | | | | | N/A
|
||||
// | | | | | | | |
|
||||
{CHIPID_GPU_VOLTAGE_340, CHIP_REVISION_B0, 0, .voltages = {0, 12500, 21875, 25000,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_474, CHIP_REVISION_B0, 0, .voltages = {0, 6250, 15625, 12500,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_550, CHIP_REVISION_B0, 0, .voltages = {0, 0, 9375, 0,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_723, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
|
||||
|
||||
{CHIPID_GPU_VOLTAGE_340, CHIP_REVISION_A1, 0, .voltages = {0, 12500, 25000, 25000,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_474, CHIP_REVISION_A1, 0, .voltages = {0, 6250, 12500, 12500,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_550, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_723, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
};
|
||||
|
||||
|
||||
const uint32_t pmgr_binning_voltage_config_sram_data_size =
|
||||
sizeof(pmgr_binning_voltage_config_sram_data)/sizeof(pmgr_binning_voltage_config_sram_data[0]);
|
||||
const uint32_t pmgr_binning_mode_to_const_data_size = sizeof(pmgr_binning_mode_to_const_data)/sizeof(pmgr_binning_mode_to_const_data[0]);
|
||||
const uint32_t pmgr_binning_voltadj_entry_data_size = sizeof(pmgr_binning_voltadj_entry_data) / sizeof(pmgr_binning_voltadj_entry_data[0]);
|
||||
const uint32_t pmgr_binning_voltage_index_to_config_data_size = sizeof(pmgr_binning_voltage_index_to_config_data)/sizeof(pmgr_binning_voltage_index_to_config_data[0]);
|
||||
const uint32_t pmgr_binning_board_id_to_offsets_data_size = sizeof(pmgr_binning_board_id_to_offsets_data)/sizeof(pmgr_binning_board_id_to_offsets_data[0]);
|
||||
@@ -0,0 +1,309 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
//
|
||||
// Please update test plan version to know what is the reference.
|
||||
//
|
||||
// Elba Test Plan Version 1.6
|
||||
// Elba Tunables Specification Revision 0.46
|
||||
//
|
||||
|
||||
#include <platform/pmgr.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
|
||||
//
|
||||
// Fuses in MINIPMGR are linearly mapped
|
||||
//
|
||||
static const struct pmgr_binning_fuse_to_register minipmgr_fuse_register[] = {
|
||||
// binning_low
|
||||
// | binning_high
|
||||
// | | register_low
|
||||
// | | | register_64bit
|
||||
// | | | | register_address
|
||||
// | | | | |
|
||||
{ 0, 369, 0, 0, AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE0_OFFSET},
|
||||
{ 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
//
|
||||
// Fuses in ACC (UDR) are sparsely mapped
|
||||
//
|
||||
static const struct pmgr_binning_fuse_to_register acc_fuse_register[] = {
|
||||
// binning_low
|
||||
// | binning_high
|
||||
// | | register_low
|
||||
// | | | register_64bit
|
||||
// | | | | register_address
|
||||
// | | | | |
|
||||
{ 0, 2, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST0_EXT2_OFFSET},
|
||||
{ 3, 6, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST0_EXT2_OFFSET},
|
||||
{ 7, 9, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST1_EXT2_OFFSET},
|
||||
{ 10, 13, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST1_EXT2_OFFSET},
|
||||
{ 14, 16, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST2_EXT2_OFFSET},
|
||||
{ 17, 20, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST2_EXT2_OFFSET},
|
||||
{ 21, 23, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST3_EXT2_OFFSET},
|
||||
{ 24, 27, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST3_EXT2_OFFSET},
|
||||
{ 28, 30, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST4_EXT2_OFFSET},
|
||||
{ 31, 34, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST4_EXT2_OFFSET},
|
||||
{ 35, 37, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST5_EXT2_OFFSET},
|
||||
{ 38, 41, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST5_EXT2_OFFSET},
|
||||
{ 42, 44, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST6_EXT2_OFFSET},
|
||||
{ 45, 48, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST6_EXT2_OFFSET},
|
||||
{ 40, 51, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST7_EXT2_OFFSET},
|
||||
{ 52, 55, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST7_EXT2_OFFSET},
|
||||
{ 56, 58, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST8_EXT2_OFFSET},
|
||||
{ 59, 62, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST8_EXT2_OFFSET},
|
||||
{ 112, 114,29, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 115, 119,24, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 120, 127,16, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
const struct pmgr_binning_mode_to_fuse pmgr_binning_mode_to_fuse_data[] = {
|
||||
//
|
||||
// CPU
|
||||
//
|
||||
|
||||
//type
|
||||
//| mode
|
||||
//| | bingroup
|
||||
//| | | low
|
||||
//| | | | high
|
||||
//| | | | | fuse_to_register
|
||||
//| | | | | |
|
||||
{PMGR_BINNING_CPU, 1, PMGR_BINNING_GROUP_ALL, 0, 6, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 2, PMGR_BINNING_GROUP_ALL, 7, 13, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 3, PMGR_BINNING_GROUP_ALL, 14, 20, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 4, PMGR_BINNING_GROUP_ALL, 21, 27, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 5, PMGR_BINNING_GROUP_ALL, 28, 34, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 6, PMGR_BINNING_GROUP_ALL, 35, 41, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 7, PMGR_BINNING_GROUP_ALL, 42, 48, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 8, PMGR_BINNING_GROUP_ALL, 49, 55, acc_fuse_register},
|
||||
|
||||
//
|
||||
// GPU/SOC
|
||||
//
|
||||
|
||||
//type
|
||||
//| mode
|
||||
//| | bingroup
|
||||
//| | | low
|
||||
//| | | | high
|
||||
//| | | | | fuse_to_register
|
||||
//| | | | | |
|
||||
{PMGR_BINNING_GPU, 1, PMGR_BINNING_GROUP_ALL, 238, 244, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 2, PMGR_BINNING_GROUP_ALL, 245, 251, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 3, PMGR_BINNING_GROUP_ALL, 252, 258, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 4, PMGR_BINNING_GROUP_ALL, 259, 265, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 5, PMGR_BINNING_GROUP_ALL, 266, 272, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_SOC, 1, PMGR_BINNING_GROUP_ALL, 224, 230, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_SOC, 2, PMGR_BINNING_GROUP_ALL, 231, 237, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_BASE, 0, PMGR_BINNING_GROUP_ALL, 115, 119, acc_fuse_register},
|
||||
|
||||
{PMGR_BINNING_REV, 0, PMGR_BINNING_GROUP_ALL, 142, 147, minipmgr_fuse_register},
|
||||
|
||||
|
||||
{PMGR_BINNING_END_OF_LIST, 0, PMGR_BINNING_GROUP_ALL, 0, 0, NULL},
|
||||
};
|
||||
|
||||
//
|
||||
// Group-specific entries must come before the corresponding entry with PMGR_BINNING_GROUP_ALL.
|
||||
//
|
||||
const struct pmgr_binning_voltage_index_to_config pmgr_binning_voltage_index_to_config_data[] = {
|
||||
// voltage index
|
||||
// | safe voltage
|
||||
// | | mode
|
||||
// | | | type
|
||||
// | | | | binning group
|
||||
// | | | | | fuse revision minimun
|
||||
// | | | | | |
|
||||
{CHIPID_CPU_VOLTAGE_BYPASS, 606, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_SECUREROM, 606, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_396, 606, 1, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_720, 606, 2, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1080, 720, 3, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1440, 833, 4, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1800, 947, 5, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_2160, 1060, 6, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_2256_1core, 1060, 6, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_2256, 1090, 7, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_2352, 1130, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_2448, 1130, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
// There is only one SOC voltage state on S8001
|
||||
// But Test Plan named MS001 for J99a and MS002 for J127
|
||||
// and this is like S8000 which call MS1 for VMIN and MS2 for VNOM
|
||||
{CHIPID_SOC_VOLTAGE_VMIN, 800, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_SOC_VOLTAGE_VNOM, 900, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
{CHIPID_GPU_VOLTAGE_OFF, 0, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_360, 670, 1, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_520, 800, 2, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_650, 920, 3, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_723, 1030, 4, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_800, 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_804, 1100, 5, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
};
|
||||
|
||||
//
|
||||
// Safe voltage of 0 and binning mode != PMGR_BINNING_MODE_NONE
|
||||
// means data are store in pmgr_binning_mode_to_const_data
|
||||
//
|
||||
const struct pmgr_binning_voltage_config pmgr_binning_voltage_config_sram_data[] = {
|
||||
// safe voltage (0 means lookup data in pmgr_binning_mode_to_const_data)
|
||||
// | mode
|
||||
// | | type
|
||||
// | | |
|
||||
[CHIPID_CPU_VOLTAGE_396] = { 0, 1, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_720] = { 0, 2, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1080] = { 0, 3, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1440] = { 0, 4, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1800] = { 0, 5, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_2160] = { 0, 6, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_2256_1core] = { 0, 7, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_2256] = { 1090, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_2352] = { 1130, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_2448] = { 1130, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
|
||||
[CHIPID_GPU_VOLTAGE_OFF] = { 0, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_360] = { 0, 1, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_520] = { 0, 2, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_650] = { 0, 3, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_723] = { 0, 4, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_800] = { 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_804] = { 0, 5, PMGR_BINNING_GPU_SRAM},
|
||||
|
||||
[CHIPID_VOLTAGE_FIXED] = { 900, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SRAM},
|
||||
};
|
||||
|
||||
//
|
||||
// Group-specific entries must come before the corresponding entry with PMGR_BINNING_GROUP_ALL.
|
||||
//
|
||||
const struct pmgr_binning_mode_to_const pmgr_binning_mode_to_const_data[] = {
|
||||
// Voltage
|
||||
// | Mode
|
||||
// | | Type
|
||||
// | | | Binning group
|
||||
// | | | | fuse revision minimun
|
||||
// | | | | |
|
||||
{ 820, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
|
||||
{ 930, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
|
||||
{ 990, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
|
||||
{1000, 7, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
|
||||
|
||||
{ 835, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
|
||||
{ 885, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
|
||||
{1000, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
|
||||
{1000, 7, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
|
||||
|
||||
{ 800, 1, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 2, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 3, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 833, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 947, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1060, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1060, 7, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
{1100, 5, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 10},
|
||||
|
||||
{ 850, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
|
||||
{ 930, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
|
||||
{1000, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
|
||||
|
||||
{ 800, 1, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 920, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1030, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1100, 5, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
};
|
||||
|
||||
const struct pmgr_binning_board_id_to_offsets pmgr_binning_board_id_to_offsets_data[] = {
|
||||
// type
|
||||
// | voltage offset array
|
||||
// | | voltage offset array size
|
||||
// | | | chip rev
|
||||
// | | | | board id
|
||||
// | | | | | binning group
|
||||
// | | | | | |
|
||||
};
|
||||
|
||||
// .voltages = {volAdj0, volAdj1, volAdj2, volAdj3, dvfmMaxAdj, dvmrAdj0, dvmrAdj1, dvmrAdj2}
|
||||
|
||||
const struct pmgr_binning_voltadj_entry pmgr_binning_voltadj_entry_data[] = {
|
||||
//
|
||||
// CPU
|
||||
//
|
||||
// volAdj0
|
||||
// | volAdj1
|
||||
// | | volAdj2
|
||||
// | | | volAdj3
|
||||
// | | | | dvfmMaxAdj
|
||||
// | | | | | dvmrAdj0
|
||||
// | | | | | | dvmrAdj1
|
||||
// | | | | | | | dvmrAdj2
|
||||
// | | | | | | | |
|
||||
{CHIPID_CPU_VOLTAGE_396 , CHIP_REVISION_B0, 0, .voltages = {0, 9375, 18750, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_720 , CHIP_REVISION_B0, 0, .voltages = {0, 0, 18750, 21875, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1080, CHIP_REVISION_B0, 0, .voltages = {0, 0, 15625, 15625, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1440, CHIP_REVISION_B0, 0, .voltages = {0, 0, 12500, 12500, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1800, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_2160, CHIP_REVISION_B0, 0, .voltages = {21875,0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_2256_1core,CHIP_REVISION_B0,0,.voltages={21875,0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_2256, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_2352, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_2448, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
|
||||
|
||||
{CHIPID_CPU_VOLTAGE_BYPASS,CHIP_REVISION_A0,0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_SOC_VOLTAGE_SECUREROM,CHIP_REVISION_A0,0,.voltages={0, 0, 0, 0, 0, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_396 , CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_720 , CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1080, CHIP_REVISION_A0, 0, .voltages = {0, 3125, 6250, 12500, 40625, 6250, 6250, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1440, CHIP_REVISION_A0, 0, .voltages = {0, 3125, 6250, 12500, 40625, 9375, 9375, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1800, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 18750, 15625, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_2160, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 25000, 21875, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_2256_1core,CHIP_REVISION_A0,0,.voltages={0, 0, 0, 0, 40625, 3125, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_2256, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 25000, 21875, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_2352, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 28125, 25000, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_2448, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 3125, 0, 0}},
|
||||
|
||||
// GFX
|
||||
//
|
||||
// volAdj0
|
||||
// | volAdj1
|
||||
// | | volAdj2
|
||||
// | | | volAdj3
|
||||
// | | | | N/A
|
||||
// | | | | | N/A
|
||||
// | | | | | | N/A
|
||||
// | | | | | | | N/A
|
||||
// | | | | | | | |
|
||||
{CHIPID_GPU_VOLTAGE_360, CHIP_REVISION_B0, 0, .voltages = {0, 3125, 18750, 21875,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_520, CHIP_REVISION_B0, 0, .voltages = {0, 0, 12500, 12500,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_650, CHIP_REVISION_B0, 0, .voltages = {0, 0, 6125, 6125,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_723, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_804, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
|
||||
{CHIPID_GPU_VOLTAGE_360, CHIP_REVISION_A0, 0, .voltages = {0, 12500, 25000, 25000,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_520, CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 12500,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_650, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_723, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_804, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
};
|
||||
|
||||
const uint32_t pmgr_binning_voltage_config_sram_data_size =
|
||||
sizeof(pmgr_binning_voltage_config_sram_data)/sizeof(pmgr_binning_voltage_config_sram_data[0]);
|
||||
const uint32_t pmgr_binning_mode_to_const_data_size = sizeof(pmgr_binning_mode_to_const_data)/sizeof(pmgr_binning_mode_to_const_data[0]);
|
||||
const uint32_t pmgr_binning_voltadj_entry_data_size = sizeof(pmgr_binning_voltadj_entry_data) / sizeof(pmgr_binning_voltadj_entry_data[0]);
|
||||
const uint32_t pmgr_binning_voltage_index_to_config_data_size = sizeof(pmgr_binning_voltage_index_to_config_data)/sizeof(pmgr_binning_voltage_index_to_config_data[0]);
|
||||
const uint32_t pmgr_binning_board_id_to_offsets_data_size = sizeof(pmgr_binning_board_id_to_offsets_data)/sizeof(pmgr_binning_board_id_to_offsets_data[0]);
|
||||
@@ -0,0 +1,378 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
//
|
||||
// Please update test plan version to know what is the reference.
|
||||
//
|
||||
// Malta Test Plan Version 1.6
|
||||
// Malta Tunables Specification Revision 0.47 (for volt_adj)
|
||||
//
|
||||
|
||||
#include <platform/pmgr.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
|
||||
//
|
||||
// Fuses in MINIPMGR are linearly mapped
|
||||
//
|
||||
static const struct pmgr_binning_fuse_to_register minipmgr_fuse_register[] = {
|
||||
// binning_low
|
||||
// | binning_high
|
||||
// | | register_low
|
||||
// | | | register_64bit
|
||||
// | | | | register_address
|
||||
// | | | | |
|
||||
{ 0, 369, 0, 0, AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE0_OFFSET},
|
||||
{ 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
//
|
||||
// Fuses in ACC (UDR) are sparsely mapped
|
||||
//
|
||||
static const struct pmgr_binning_fuse_to_register acc_fuse_register[] = {
|
||||
// binning_low
|
||||
// | binning_high
|
||||
// | | register_low
|
||||
// | | | register_64bit
|
||||
// | | | | register_address
|
||||
// | | | | |
|
||||
{ 0, 2, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST0_EXT2_OFFSET},
|
||||
{ 3, 6, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST0_EXT2_OFFSET},
|
||||
{ 7, 9, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST1_EXT2_OFFSET},
|
||||
{ 10, 13, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST1_EXT2_OFFSET},
|
||||
{ 14, 16, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST2_EXT2_OFFSET},
|
||||
{ 17, 20, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST2_EXT2_OFFSET},
|
||||
{ 21, 23, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST3_EXT2_OFFSET},
|
||||
{ 24, 27, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST3_EXT2_OFFSET},
|
||||
{ 28, 30, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST4_EXT2_OFFSET},
|
||||
{ 31, 34, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST4_EXT2_OFFSET},
|
||||
{ 35, 37, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST5_EXT2_OFFSET},
|
||||
{ 38, 41, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST5_EXT2_OFFSET},
|
||||
{ 42, 44, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST6_EXT2_OFFSET},
|
||||
{ 45, 48, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST6_EXT2_OFFSET},
|
||||
{ 49, 51, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST7_EXT2_OFFSET},
|
||||
{ 52, 55, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST7_EXT2_OFFSET},
|
||||
{ 56, 58, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST8_EXT2_OFFSET},
|
||||
{ 59, 62, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST8_EXT2_OFFSET},
|
||||
{ 112, 114,29, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 115, 119,24, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 120, 127,16, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
//
|
||||
// Group-specific entries must come before the corresponding entry with PMGR_BINNING_GROUP_ALL.
|
||||
//
|
||||
|
||||
const struct pmgr_binning_mode_to_fuse pmgr_binning_mode_to_fuse_data[] = {
|
||||
//
|
||||
// CPU
|
||||
//
|
||||
|
||||
//type
|
||||
//| mode
|
||||
//| | bingroup
|
||||
//| | | low
|
||||
//| | | | high
|
||||
//| | | | | fuse_to_register
|
||||
//| | | | | |
|
||||
{PMGR_BINNING_CPU, 1, PMGR_BINNING_GROUP_ALL, 0, 6, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 2, PMGR_BINNING_GROUP_ALL, 7, 13, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 3, PMGR_BINNING_GROUP_ALL, 14, 20, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 4, PMGR_BINNING_GROUP_ALL, 21, 27, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 5, PMGR_BINNING_GROUP_ALL, 28, 34, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 6, PMGR_BINNING_GROUP_ALL, 35, 41, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 7, PMGR_BINNING_GROUP_ALL, 42, 48, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 8, PMGR_BINNING_GROUP_ALL, 49, 55, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 9, PMGR_BINNING_GROUP_ALL, 56, 62, acc_fuse_register},
|
||||
|
||||
//
|
||||
// GPU/SOC
|
||||
//
|
||||
|
||||
//type
|
||||
//| mode
|
||||
//| | bingroup
|
||||
//| | | low
|
||||
//| | | | high
|
||||
//| | | | | fuse_to_register
|
||||
//| | | | | |
|
||||
{PMGR_BINNING_GPU, 1, PMGR_BINNING_GROUP_ALL, 238, 244, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 2, PMGR_BINNING_GROUP_ALL, 245, 251, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 3, PMGR_BINNING_GROUP_ALL, 252, 258, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 4, PMGR_BINNING_GROUP_ALL, 259, 265, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 5, PMGR_BINNING_GROUP_ALL, 266, 272, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_SOC, 1, PMGR_BINNING_GROUP_ALL, 224, 230, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_SOC, 2, PMGR_BINNING_GROUP_ALL, 231, 237, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_BASE, 0, PMGR_BINNING_GROUP_ALL, 115, 119, acc_fuse_register},
|
||||
|
||||
{PMGR_BINNING_REV, 0, PMGR_BINNING_GROUP_ALL, 142, 147, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_GROUP, 0, PMGR_BINNING_GROUP_ALL, 318, 319, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_END_OF_LIST, 0, PMGR_BINNING_GROUP_ALL, 0, 0, NULL},
|
||||
};
|
||||
|
||||
//
|
||||
// Group-specific entries must come before the corresponding entry with PMGR_BINNING_GROUP_ALL.
|
||||
//
|
||||
const struct pmgr_binning_voltage_index_to_config pmgr_binning_voltage_index_to_config_data[] = {
|
||||
// voltage index
|
||||
// | safe voltage
|
||||
// | | mode
|
||||
// | | | type
|
||||
// | | | | binning group
|
||||
// | | | | | fuse revision minimun
|
||||
// | | | | | |
|
||||
{CHIPID_CPU_VOLTAGE_BYPASS, 606, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_SECUREROM, 606, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_396, 606, 1, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_600, 606, 2, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_912, 667, 3, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1200, 757, 4, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1512, 856, 5, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1800, 947, 6, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1848, 977, 6, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
// SEG-characterization
|
||||
{CHIPID_CPU_VOLTAGE_1896, 977, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1992, 1007, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_2112, 1045, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
{CHIPID_SOC_VOLTAGE_BYPASS, 670, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_SOC_VOLTAGE_SECUREROM, 670, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_SOC_VOLTAGE_VMIN, 670, 1, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_SOC_VOLTAGE_VNOM, 800, 2, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
{CHIPID_GPU_VOLTAGE_OFF, 0, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_340, 670, 1, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_474, 800, 2, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_550, 920, 3, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_723, 1030, 4, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_804, 1080, 5, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
// SEG-characterization
|
||||
{CHIPID_GPU_VOLTAGE_850, 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_900, 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
};
|
||||
|
||||
//
|
||||
// Safe voltage of 0 and binning mode != PMGR_BINNING_MODE_NONE
|
||||
// means data are store in pmgr_binning_mode_to_const_data
|
||||
//
|
||||
const struct pmgr_binning_voltage_config pmgr_binning_voltage_config_sram_data[] = {
|
||||
// safe voltage (0 means lookup data in pmgr_binning_mode_to_const_data)
|
||||
// | mode
|
||||
// | | type
|
||||
// | | |
|
||||
[CHIPID_CPU_VOLTAGE_BYPASS] = { 800, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_SECUREROM] = { 800, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_396] = { 0, 1, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_600] = { 0, 2, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_912] = { 0, 3, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1200] = { 0, 4, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1512] = { 0, 5, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1800] = { 0, 6, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1848] = { 0, 6, PMGR_BINNING_CPU_SRAM},
|
||||
// SEG-characterization
|
||||
[CHIPID_CPU_VOLTAGE_1896] = { 977, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1992] = {1007, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_2112] = {1045, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
|
||||
[CHIPID_GPU_VOLTAGE_OFF] = { 0, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_340] = { 0, 1, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_474] = { 0, 2, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_550] = { 0, 3, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_723] = { 0, 4, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_804] = { 0, 5, PMGR_BINNING_GPU_SRAM},
|
||||
// SEG-characterization
|
||||
[CHIPID_GPU_VOLTAGE_850] = {1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_900] = {1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
|
||||
[CHIPID_VOLTAGE_FIXED] = { 900, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SRAM},
|
||||
};
|
||||
|
||||
|
||||
//
|
||||
// SRAM has 3 "safe voltage" one from fuse rev 0,1,2, one for fuse rev 3,4 and one from fuse rev 5.
|
||||
// Group-specific entries must come before the corresponding entry with PMGR_BINNING_GROUP_ALL.
|
||||
//
|
||||
const struct pmgr_binning_mode_to_const pmgr_binning_mode_to_const_data[] = {
|
||||
// voltage
|
||||
// | mode
|
||||
// | | type
|
||||
// | | | binning group
|
||||
// | | | | fuse revision minimun
|
||||
// | | | | |
|
||||
{ 800, 1, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
{ 800, 2, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
{ 800, 3, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
{ 800, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
{ 840, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
{ 915, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
|
||||
{ 800, 1, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
{ 800, 2, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
{ 800, 3, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
{ 840, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
{ 940, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
{ 960, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
|
||||
{ 800, 1, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 2, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 3, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 852, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 947, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 915, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1060, 7, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1130, 8, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
// GPU - N69
|
||||
{ 865, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 5},
|
||||
{ 895, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 5},
|
||||
{1005, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 5},
|
||||
|
||||
{ 865, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 3},
|
||||
{ 895, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 3},
|
||||
{1005, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 3},
|
||||
|
||||
{ 865, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 0},
|
||||
{ 895, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 0},
|
||||
{1005, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 0},
|
||||
|
||||
// GPU - ALL
|
||||
{ 800, 1, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
{ 840, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
{ 875, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
{ 985, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
|
||||
{ 800, 1, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
{ 800, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
{ 920, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
{1025, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
|
||||
{ 800, 1, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 920, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1030, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1080, 5, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
};
|
||||
|
||||
static const struct pmgr_binning_voltage_index_to_offset n69_cpu_offsets[] = {
|
||||
// voltage index
|
||||
// | fuse revision minimum
|
||||
// | | offset
|
||||
// | | |
|
||||
{CHIPID_CPU_VOLTAGE_1200, 0, 15},
|
||||
};
|
||||
|
||||
const struct pmgr_binning_board_id_to_offsets pmgr_binning_board_id_to_offsets_data[] = {
|
||||
// type
|
||||
// | voltage offset array
|
||||
// | | voltage offset array size
|
||||
// | | | chip rev
|
||||
// | | | | board id
|
||||
// | | | | | binning group
|
||||
// | | | | | |
|
||||
{PMGR_BINNING_CPU, n69_cpu_offsets, sizeof(n69_cpu_offsets)/sizeof(n69_cpu_offsets[0]), CHIP_REVISION_A1, N69_AP_BOARD_ID, PMGR_BINNING_GROUP_ALL},
|
||||
{PMGR_BINNING_CPU, n69_cpu_offsets, sizeof(n69_cpu_offsets)/sizeof(n69_cpu_offsets[0]), CHIP_REVISION_A1, N69_DEV_BOARD_ID, PMGR_BINNING_GROUP_ALL},
|
||||
};
|
||||
|
||||
// .voltages = {volAdj0, volAdj1, volAdj2, volAdj3, dvfmMaxAdj, dvmrAdj0, dvmrAdj1, dvmrAdj2}
|
||||
|
||||
const struct pmgr_binning_voltadj_entry pmgr_binning_voltadj_entry_data[] = {
|
||||
//
|
||||
// CPU
|
||||
//
|
||||
// volAdj0
|
||||
// | volAdj1
|
||||
// | | volAdj2
|
||||
// | | | volAdj3
|
||||
// | | | | dvfmMaxAdj
|
||||
// | | | | | dvmrAdj0
|
||||
// | | | | | | dvmrAdj1
|
||||
// | | | | | | | dvmrAdj2
|
||||
// | | | | | | | |
|
||||
{CHIPID_CPU_VOLTAGE_396, CHIP_REVISION_A1, 6, .voltages = {0, 9375, 18750, 18750, 40625, 0, 0, 0}},
|
||||
|
||||
{CHIPID_CPU_VOLTAGE_396, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_600, CHIP_REVISION_A1, 0, .voltages = {0, 0, 18750, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_912, CHIP_REVISION_A1, 0, .voltages = {0, 0, 18750, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1200, CHIP_REVISION_A1, 0, .voltages = {0, 0, 15625, 15625, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1512, CHIP_REVISION_A1, 0, .voltages = {0, 0, 6250, 6250, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1800, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1848, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
|
||||
|
||||
{CHIPID_CPU_VOLTAGE_BYPASS,CHIP_REVISION_A0,0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_SOC_VOLTAGE_SECUREROM,CHIP_REVISION_A0,0,.voltages={0, 0, 0, 0, 0, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_396, CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_600, CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_912, CHIP_REVISION_A0, 0, .voltages = {0, 3125, 6250, 12500, 40625, 3125, 3125, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1200, CHIP_REVISION_A0, 0, .voltages = {0, 3125, 6250, 12500, 40625, 6250, 6250, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1512, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 15625,12500, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_1800, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 18750,15625, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_1848, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 18750,15625, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_1896, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 18750,15625, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_1992, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 21870,18750, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_2112, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 25000,21875, 3125}},
|
||||
|
||||
//
|
||||
// SOC
|
||||
//
|
||||
// volAdj0
|
||||
// | volAdj1
|
||||
// | | volAdj2
|
||||
// | | | volAdj3
|
||||
// | | | | N/A
|
||||
// | | | | | N/A
|
||||
// | | | | | | N/A
|
||||
// | | | | | | | N/A
|
||||
// | | | | | | | |
|
||||
{CHIPID_SOC_VOLTAGE_VMIN, CHIP_REVISION_A1, 0, .voltages = {0, 3125, 15625, 18750,0,0,0,0}},
|
||||
{CHIPID_SOC_VOLTAGE_VNOM, CHIP_REVISION_A1, 0, .voltages = {0, 0, 12500, 12500,0,0,0,0}},
|
||||
|
||||
{CHIPID_SOC_VOLTAGE_VMIN, CHIP_REVISION_A0, 0, .voltages = {0, 12500, 25000, 25000,0,0,0,0}},
|
||||
{CHIPID_SOC_VOLTAGE_VNOM, CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 12500,0,0,0,0}},
|
||||
{CHIPID_SOC_VOLTAGE_BYPASS,CHIP_REVISION_A0, 0, .voltages ={0, 0, 0, 0,0,0,0,0}},
|
||||
{CHIPID_SOC_VOLTAGE_SECUREROM,CHIP_REVISION_A0,0,.voltages={0, 0, 0, 0,0,0,0,0}},
|
||||
|
||||
//
|
||||
// GFX
|
||||
//
|
||||
// volAdj0
|
||||
// | volAdj1
|
||||
// | | volAdj2
|
||||
// | | | volAdj3
|
||||
// | | | | N/A
|
||||
// | | | | | N/A
|
||||
// | | | | | | N/A
|
||||
// | | | | | | | N/A
|
||||
// | | | | | | | |
|
||||
{CHIPID_GPU_VOLTAGE_340, CHIP_REVISION_A1, 0, .voltages = {0, 3125, 15625, 18750,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_474, CHIP_REVISION_A1, 0, .voltages = {0, 0, 12500, 12500,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_550, CHIP_REVISION_A1, 0, .voltages = {0, 0, 3125, 3125,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_723, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_804, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
|
||||
{CHIPID_GPU_VOLTAGE_340, CHIP_REVISION_A0, 0, .voltages = {0, 12500, 25000, 25000,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_474, CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 12500,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_550, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_723, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
};
|
||||
|
||||
|
||||
const uint32_t pmgr_binning_voltage_config_sram_data_size =
|
||||
sizeof(pmgr_binning_voltage_config_sram_data)/sizeof(pmgr_binning_voltage_config_sram_data[0]);
|
||||
const uint32_t pmgr_binning_mode_to_const_data_size = sizeof(pmgr_binning_mode_to_const_data)/sizeof(pmgr_binning_mode_to_const_data[0]);
|
||||
const uint32_t pmgr_binning_voltadj_entry_data_size = sizeof(pmgr_binning_voltadj_entry_data) / sizeof(pmgr_binning_voltadj_entry_data[0]);
|
||||
const uint32_t pmgr_binning_voltage_index_to_config_data_size = sizeof(pmgr_binning_voltage_index_to_config_data)/sizeof(pmgr_binning_voltage_index_to_config_data[0]);
|
||||
const uint32_t pmgr_binning_board_id_to_offsets_data_size = sizeof(pmgr_binning_board_id_to_offsets_data)/sizeof(pmgr_binning_board_id_to_offsets_data[0]);
|
||||
@@ -0,0 +1,42 @@
|
||||
# Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_PLATFORM_CHIPID=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/chipid.o \
|
||||
$(LOCAL_DIR)/operating_point.o \
|
||||
$(LOCAL_DIR)/dvfmperf.o \
|
||||
$(LOCAL_DIR)/tunables_pmgr_product.o
|
||||
|
||||
ifeq ($(SUB_PLATFORM),s8000)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/tunables_pmgr_s8000.o \
|
||||
$(LOCAL_DIR)/pmgr_binning_s8000.o
|
||||
endif
|
||||
|
||||
ifeq ($(SUB_PLATFORM),s8001)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/tunables_pmgr_s8001.o \
|
||||
$(LOCAL_DIR)/pmgr_binning_s8001.o
|
||||
|
||||
ifeq ($(TARGET),ipad6b)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/tunables_pmgr_s8001_ipad6b.o
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(SUB_PLATFORM),s8003)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/tunables_pmgr_s8003.o \
|
||||
$(LOCAL_DIR)/pmgr_binning_s8003.o
|
||||
endif
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* This file contains Tunables for s8001 products without product tunables */
|
||||
|
||||
#include <platform/tunables.h>
|
||||
|
||||
const struct tunable_chip_struct tunables_pmgr_product[] __attribute__((weak)) = {
|
||||
{0, 0, NULL, NULL, 0}
|
||||
};
|
||||
@@ -0,0 +1,323 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* This file contains Tunables for s8000 */
|
||||
|
||||
#include <platform/tunables.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <soc/module/address_map.h>
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_ALL ****************************************/
|
||||
// <rdar://problem/21406702> Maui: Add PMGR_PLL_PCIE_CFG.LOCK_MODE tunable to SPDS
|
||||
// <rdar://problem/21347912> Add support for product / platform specific tunables
|
||||
// <rdar://problem/20536609> Add GFX TVM tunables in PDF tunables to SPDS tunables
|
||||
// <rdar://problem/20537375> Add SOC TVM tunables in PDF tunables to SPDS tunables
|
||||
#define SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_EXTRA \
|
||||
{ /*! PLL0_CFG */ 0x00004, sizeof(uint32_t), 0xc0000000u, 0x40000000u}, \
|
||||
{ /*! PLL1_CFG */ 0x04004, sizeof(uint32_t), 0xc0000000u, 0x40000000u}, \
|
||||
{ /*! PLL_PCIE_CFG */ 0x18004, sizeof(uint32_t), 0xc0000000u, 0x40000000u}, \
|
||||
{ /*! VOLMAN_SOC_DELAY */ 0xa001c, sizeof(uint32_t), 0xfffffcffu, 0xbb81642fu}, \
|
||||
{ /*! VOLMAN_GFX_SRAM_DELAY */ 0xa0020, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_CPU_SRAM_DELAY */ 0xa0024, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_GFX_DELAY */ 0xa0028, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_CPU_DELAY */ 0xa002c, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! SOC_TVM_THRESH0 */ 0xc8004, sizeof(uint32_t), 0x000001ffu, 0x00000000u}, \
|
||||
{ /*! SOC_TVM_THRESH1 */ 0xc8008, sizeof(uint32_t), 0x000001ffu, 0x00000019u}, \
|
||||
{ /*! SOC_TVM_THRESH2 */ 0xc800c, sizeof(uint32_t), 0x000001ffu, 0x00000032u}, \
|
||||
{ /*! SOC_TVM_TEMP0_CFG */ 0xc8010, sizeof(uint32_t), 0x01ff01ffu, 0x001c01f4u}, \
|
||||
{ /*! SOC_TVM_TEMP1_CFG */ 0xc8014, sizeof(uint32_t), 0x01ff01ffu, 0x001c01f4u}, \
|
||||
{ /*! SOC_TVM_TEMP2_CFG */ 0xc8018, sizeof(uint32_t), 0x01ff01ffu, 0x001c01f4u}, \
|
||||
{ /*! GFX_TVM_CTL */ 0xc8200, sizeof(uint32_t), 0x00000f00u, 0x00000f00u}, \
|
||||
{ /*! GFX_TVM_THRESH0 */ 0xc8204, sizeof(uint32_t), 0x000001ffu, 0x00000000u}, \
|
||||
{ /*! GFX_TVM_THRESH1 */ 0xc8208, sizeof(uint32_t), 0x000001ffu, 0x00000019u}, \
|
||||
{ /*! GFX_TVM_THRESH2 */ 0xc820c, sizeof(uint32_t), 0x000001ffu, 0x00000032u}, \
|
||||
{ /*! GFX_TVM_TEMP0_CFG */ 0xc8210, sizeof(uint32_t), 0x01ff01ffu, 0x001501f9u}, \
|
||||
{ /*! GFX_TVM_TEMP1_CFG */ 0xc8214, sizeof(uint32_t), 0x01ff01ffu, 0x001501f9u}, \
|
||||
{ /*! GFX_TVM_TEMP2_CFG */ 0xc8218, sizeof(uint32_t), 0x01ff01ffu, 0x001501f9u}
|
||||
|
||||
// <rdar://problem/20544302> Add CPU TVM tunables in tunables PDF to SPDS tunables
|
||||
// <rdar://problem/20545027> Add DVMR tunables in tunables PDF to SPDS tunables
|
||||
#define ACC_DEFAULT_TUNABLES_S8000_EXTRA \
|
||||
/* Configure temperature ranges and measurement offsets for DVFM/DVTM */ \
|
||||
/* temp_thread0 0x8 temp_thresh1 0x21 temp_offset0 0 temp_offset1 0 */ \
|
||||
{ /* ACC_PWRCTL_DVFM_CFG */ 0x220040, sizeof(uint32_t), 0x0fffffffu, 0x00001088u}, \
|
||||
/* temp_thresh2 0x3a temp_offset2 0 */ \
|
||||
{ /* ACC_PWRCTL_DVFM_CFG1 */ 0x220058, sizeof(uint32_t), 0x001fffffu, 0x0000003au}, \
|
||||
{ /* ACC_PWRCTL_DVMR_SCR */ 0x2206b8, sizeof(uint64_t), 0x00000fffu, 0x000000421}
|
||||
|
||||
#define SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_EXTRA \
|
||||
/* <rdar://problem/20868785> Ensure that LPO OFF_MODE is set appropriately */ \
|
||||
{ /*! MINIPMGR_LPO_CFG */ 0x00004, sizeof(uint32_t), 0xc0000000u, 0x80000000u }
|
||||
|
||||
// <rdar://problem/17755256> SwitchFabric Hash lock bit is not set
|
||||
#define SWITCHFABRIC_DEFAULT_TUNABLES_S8000_EXTRA \
|
||||
{ /*! SWITCHFABRIC_REGS_AMAP_LOCK */ 0x00000, sizeof(uint32_t), 0x00000001u, 0x00000001u }
|
||||
/**************************************** END CHIP_REVISION_ALL ****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_C0 ****************************************/
|
||||
#include <soc/s8000/c0/tunable/minipmgr.h>
|
||||
#include <soc/s8000/c0/tunable/pmgr.h>
|
||||
#include <soc/s8000/c0/tunable/acc.h>
|
||||
#include <soc/s8000/c0/tunable/sbasyncfifo_widgets.h>
|
||||
#include <soc/s8000/c0/tunable/socbusmux.h>
|
||||
#include <soc/s8000/c0/tunable/switchfabric.h>
|
||||
#include <soc/s8000/c0/tunable/pms_csr.h>
|
||||
#include <soc/s8000/c0/tunable/afc_aiu_sb.h>
|
||||
#include <soc/s8000/c0/tunable/sb_glue.h>
|
||||
#include <soc/s8000/c0/tunable/misc1.h>
|
||||
#include <soc/s8000/c0/tunable/cp_com.h>
|
||||
|
||||
static const struct tunable_struct pmsasyncfifo_tunable_c0[] = {
|
||||
SOUTH_BRIDGE_PMSASYNCFIFO_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_c0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct minipmgr_tunable_c0[] = {
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct64 acc_tunable_c0[] = {
|
||||
ACC_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
ACC_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct socbusmux_tunable_c0[] = {
|
||||
SOCBUSMUX_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct switchfabric_tunable_c0[] = {
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct pms_csr_tunable_c0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMS_CSR_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct sb_glue_tunable_c0[] = {
|
||||
SOUTH_BRIDGE_DYNAMIC_CLK_GATING_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct afc_aiu_sb_tunable_c0[] = {
|
||||
SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct asio_misc1_tunable_c0[] = {
|
||||
SOUTH_BRIDGE_ASIO_MISC1_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp_com_tunable_c0[] = {
|
||||
CP_CP_COM_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
/***************************************** END CHIP_REVISION_C0 *****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_B0 ****************************************/
|
||||
#include <soc/s8000/b0/tunable/minipmgr.h>
|
||||
#include <soc/s8000/b0/tunable/pmgr.h>
|
||||
#include <soc/s8000/b0/tunable/acc.h>
|
||||
#include <soc/s8000/b0/tunable/sbasyncfifo_widgets.h>
|
||||
#include <soc/s8000/b0/tunable/socbusmux.h>
|
||||
#include <soc/s8000/b0/tunable/switchfabric.h>
|
||||
#include <soc/s8000/b0/tunable/pms_csr.h>
|
||||
#include <soc/s8000/b0/tunable/afc_aiu_sb.h>
|
||||
#include <soc/s8000/b0/tunable/sb_glue.h>
|
||||
#include <soc/s8000/b0/tunable/misc1.h>
|
||||
#include <soc/s8000/b0/tunable/cp_com.h>
|
||||
|
||||
#define SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_B0_EXTRA \
|
||||
/* <rdar://problem/19929273> Maui MCC EMA setting change to 3% */ \
|
||||
{ /*! EMA_FIXED_SOC1 */ 0xac004, sizeof(uint32_t), 0x07fff000u, 0x030d1000u}
|
||||
|
||||
static const struct tunable_struct pmsasyncfifo_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_PMSASYNCFIFO_DEFAULT_TUNABLES_S8000_B0,
|
||||
};
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_B0_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct minipmgr_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct64 acc_tunable_b0[] = {
|
||||
ACC_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
ACC_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct socbusmux_tunable_b0[] = {
|
||||
SOCBUSMUX_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct switchfabric_tunable_b0[] = {
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct pms_csr_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMS_CSR_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct sb_glue_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_DYNAMIC_CLK_GATING_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct afc_aiu_sb_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct asio_misc1_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_ASIO_MISC1_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp_com_tunable_b0[] = {
|
||||
CP_CP_COM_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
/***************************************** END CHIP_REVISION_B0 *****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_A1 ****************************************/
|
||||
#include <soc/s8000/a1/tunable/minipmgr.h>
|
||||
#include <soc/s8000/a1/tunable/pmgr.h>
|
||||
#include <soc/s8000/a1/tunable/acc.h>
|
||||
#include <soc/s8000/a1/tunable/sbasyncfifo_widgets.h>
|
||||
#include <soc/s8000/a1/tunable/socbusmux.h>
|
||||
#include <soc/s8000/a1/tunable/switchfabric.h>
|
||||
#include <soc/s8000/a1/tunable/pms_csr.h>
|
||||
#include <soc/s8000/a1/tunable/afc_aiu_sb.h>
|
||||
#include <soc/s8000/a1/tunable/sb_glue.h>
|
||||
#include <soc/s8000/a1/tunable/misc1.h>
|
||||
#include <soc/s8000/a1/tunable/cp_com.h>
|
||||
|
||||
#define SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_A1_EXTRA \
|
||||
/* <rdar://problem/18700978> iBoot to set M$ EMAA register to new value to increase Maui Yield */ \
|
||||
{ /*! EMA_FIXED_SOC1 */ 0xac004, sizeof(uint32_t), 0x07fff000u, 0x032d1000u}
|
||||
|
||||
// <rdar://problem/20545899> Maui: Add PMGR THERMAL tunables to SPDS for Maui A1
|
||||
#define SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_A1_THERMAL_EXTRA \
|
||||
{ /*! PMGR_THERMAL_0_PIECE0 */ 0xc0028, sizeof(uint32_t), 0x7ffffu, 0x7943bu }, \
|
||||
{ /*! PMGR_THERMAL_0_PIECE1 */ 0xc002c, sizeof(uint32_t), 0xffc7ffffu, 0x5007d02fu }, \
|
||||
{ /*! PMGR_THERMAL_0_PIECE2 */ 0xc0030, sizeof(uint32_t), 0xffc7ffffu, 0x95c02426u }, \
|
||||
{ /*! PMGR_THERMAL_1_PIECE0 */ 0xc0128, sizeof(uint32_t), 0x7ffffu, 0x7943bu }, \
|
||||
{ /*! PMGR_THERMAL_1_PIECE1 */ 0xc012c, sizeof(uint32_t), 0xffc7ffffu, 0x5007d02fu }, \
|
||||
{ /*! PMGR_THERMAL_1_PIECE2 */ 0xc0130, sizeof(uint32_t), 0xffc7ffffu, 0x95c02426u }, \
|
||||
{ /*! PMGR_THERMAL_2_PIECE0 */ 0xc0228, sizeof(uint32_t), 0x7ffffu, 0x7943bu }, \
|
||||
{ /*! PMGR_THERMAL_2_PIECE1 */ 0xc022c, sizeof(uint32_t), 0xffc7ffffu, 0x5007d02fu }, \
|
||||
{ /*! PMGR_THERMAL_2_PIECE2 */ 0xc0230, sizeof(uint32_t), 0xffc7ffffu, 0x95c02426u }
|
||||
|
||||
#define SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_A1_EXTRA \
|
||||
/* <rdar://problem/19300047> 19300047 */ \
|
||||
{ /*! MINIPMGR_LPO_CFG */ 0x00004, sizeof(uint32_t), 0x30000000u, 0x00000000u }
|
||||
|
||||
static const struct tunable_struct pmsasyncfifo_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_PMSASYNCFIFO_DEFAULT_TUNABLES_S8000_A1,
|
||||
};
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_A1_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_A1_THERMAL_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct minipmgr_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_A1_EXTRA,
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct64 acc_tunable_a1[] = {
|
||||
ACC_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
ACC_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct socbusmux_tunable_a1[] = {
|
||||
SOCBUSMUX_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct switchfabric_tunable_a1[] = {
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct pms_csr_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_PMS_PMS_CSR_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct sb_glue_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_DYNAMIC_CLK_GATING_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct afc_aiu_sb_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct asio_misc1_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_ASIO_MISC1_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp_com_tunable_a1[] = {
|
||||
CP_CP_COM_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
/***************************************** END CHIP_REVISION_A1 *****************************************/
|
||||
|
||||
// For each chip, highest revision must come first.
|
||||
// Notice reconfig == false for minipmgr, since it's an AOP.
|
||||
const struct tunable_chip_struct tunables_pmgr[] = {
|
||||
// C0
|
||||
{CHIP_REVISION_C0, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8000_C0, pmgr_tunable_c0, NULL, true},
|
||||
{CHIP_REVISION_C0, SOUTH_BRIDGE_AOP_MINIPMGR_PADDR_S8000_C0, minipmgr_tunable_c0, NULL, false},
|
||||
{CHIP_REVISION_C0, ACC_PADDR_S8000_C0, NULL, acc_tunable_c0, true},
|
||||
{CHIP_REVISION_C0, SOUTH_BRIDGE_PMSASYNCFIFO_PADDR_S8000_C0, pmsasyncfifo_tunable_c0, NULL, true},
|
||||
{CHIP_REVISION_C0, SOCBUSMUX_PADDR_S8000_C0, socbusmux_tunable_c0, NULL, true},
|
||||
{CHIP_REVISION_C0, SWITCHFABRIC_PADDR_S8000_C0, switchfabric_tunable_c0, NULL, true},
|
||||
{CHIP_REVISION_C0, SOUTH_BRIDGE_PMS_PMS_CSR_PADDR_S8000_C0, pms_csr_tunable_c0, NULL, true},
|
||||
{CHIP_REVISION_C0, SOUTH_BRIDGE_DYNAMIC_CLK_GATING_PADDR_S8000_C0, sb_glue_tunable_c0, NULL, true},
|
||||
{CHIP_REVISION_C0, SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_PADDR_S8000_C0, afc_aiu_sb_tunable_c0, NULL, true},
|
||||
{CHIP_REVISION_C0, SOUTH_BRIDGE_ASIO_MISC1_PADDR_S8000_C0, asio_misc1_tunable_c0, NULL, true},
|
||||
{CHIP_REVISION_C0, CP_CP_COM_PADDR_S8000_C0, cp_com_tunable_c0, NULL, true},
|
||||
|
||||
// B0
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8000_B0, pmgr_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_AOP_MINIPMGR_PADDR_S8000_B0, minipmgr_tunable_b0, NULL, false},
|
||||
{CHIP_REVISION_B0, ACC_PADDR_S8000_B0, NULL, acc_tunable_b0, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_PMSASYNCFIFO_PADDR_S8000_B0, pmsasyncfifo_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOCBUSMUX_PADDR_S8000_B0, socbusmux_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SWITCHFABRIC_PADDR_S8000_B0, switchfabric_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_PMS_PMS_CSR_PADDR_S8000_B0, pms_csr_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_DYNAMIC_CLK_GATING_PADDR_S8000_B0, sb_glue_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_PADDR_S8000_B0, afc_aiu_sb_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_ASIO_MISC1_PADDR_S8000_B0, asio_misc1_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, CP_CP_COM_PADDR_S8000_B0, cp_com_tunable_b0, NULL, true},
|
||||
|
||||
// A1
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8000_A1, pmgr_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_AOP_MINIPMGR_PADDR_S8000_A1, minipmgr_tunable_a1, NULL, false},
|
||||
{CHIP_REVISION_A1, ACC_PADDR_S8000_A1, NULL, acc_tunable_a1, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_PMSASYNCFIFO_PADDR_S8000_A1, pmsasyncfifo_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOCBUSMUX_PADDR_S8000_A1, socbusmux_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SWITCHFABRIC_PADDR_S8000_A1, switchfabric_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_PMS_PMS_CSR_PADDR_S8000_A1, pms_csr_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_DYNAMIC_CLK_GATING_PADDR_S8000_A1, sb_glue_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_PADDR_S8000_A1, afc_aiu_sb_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_ASIO_MISC1_PADDR_S8000_A1, asio_misc1_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, CP_CP_COM_PADDR_S8000_A1, cp_com_tunable_a1, NULL, true},
|
||||
|
||||
{0, 0, NULL, NULL, 0}
|
||||
};
|
||||
@@ -0,0 +1,219 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* This file contains Tunables for s8001 */
|
||||
|
||||
#include <platform/tunables.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <soc/module/address_map.h>
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_ALL ****************************************/
|
||||
// <rdar://problem/21347912> Add support for product / platform specific tunables
|
||||
// <rdar://problem/20619805> Add PMGR MISC_CFG_DISP.SEL_DISP_PMGR_DWI_VSYNC tunable to SPDS tunables
|
||||
#define SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_EXTRA \
|
||||
{ /*! PLL0_CFG */ 0x00004, sizeof(uint32_t), 0xc0000000u, 0x40000000u}, \
|
||||
{ /*! PLL1_CFG */ 0x04004, sizeof(uint32_t), 0xc0000000u, 0x40000000u}, \
|
||||
{ /*! PLL6_CFG */ 0x18004, sizeof(uint32_t), 0xc0000000u, 0x40000000u}, \
|
||||
{ /*! PLL7_CFG */ 0x1c004, sizeof(uint32_t), 0xc0000000u, 0x00000000u}, \
|
||||
{ /*! VOLMAN_SOC_DELAY */ 0xa001c, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_GFX_SRAM_DELAY */ 0xa0020, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_CPU_SRAM_DELAY */ 0xa0024, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_GFX_DELAY */ 0xa0028, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_CPU_DELAY */ 0xa002c, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! MISC_CFG_DISP_OFFSET */ 0xdc040, sizeof(uint32_t), 0x00000001u, 0x00000000u}
|
||||
|
||||
// <rdar://problem/20620055> Add CPU TVM tunables in tunables PDF to SPDS tunables
|
||||
// <rdar://problem/20545557> Add DVMR tunables in tunables PDF to SPDS tunables
|
||||
#define ACC_DEFAULT_TUNABLES_S8001_EXTRA \
|
||||
/* Configure temperature ranges and measurement offsets for DVFM/DVTM */ \
|
||||
/* temp_thread0 0x8 temp_thresh1 0x21 temp_offset0 0 temp_offset1 0 */ \
|
||||
{ /* ACC_PWRCTL_DVFM_CFG */ 0x220040, sizeof(uint32_t), 0x0fffffffu, 0x00001088u}, \
|
||||
/* temp_thresh2 0x3a temp_offset2 0 */ \
|
||||
{ /* ACC_PWRCTL_DVFM_CFG1 */ 0x220058, sizeof(uint32_t), 0x001fffffu, 0x0000003au}, \
|
||||
{ /* ACC_PWRCTL_DVMR_SCR */ 0x2206b8, sizeof(uint64_t), 0x00000fffu, 0x000000421}
|
||||
|
||||
#define SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8001_EXTRA \
|
||||
/* <rdar://problem/20868785> Ensure that LPO OFF_MODE is set appropriately */ \
|
||||
{ /*! MINIPMGR_LPO_CFG */ 0x00004, sizeof(uint32_t), 0xc0000000u, 0x80000000u }
|
||||
|
||||
// <rdar://problem/17755256> SwitchFabric Hash lock bit is not set
|
||||
#define SWITCHFABRIC_DEFAULT_TUNABLES_S8001_EXTRA \
|
||||
{ /*! SWITCHFABRIC_REGS_AMAP_LOCK */ 0x00000, sizeof(uint32_t), 0x00000001u, 0x00000001u }
|
||||
/**************************************** END CHIP_REVISION_ALL ****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_B0 ****************************************/
|
||||
#include <soc/s8001/b0/tunable/minipmgr.h>
|
||||
#include <soc/s8001/b0/tunable/pmgr.h>
|
||||
#include <soc/s8001/b0/tunable/acc.h>
|
||||
#include <soc/s8001/b0/tunable/sbasyncfifo_widgets.h>
|
||||
#include <soc/s8001/b0/tunable/socbusmux.h>
|
||||
#include <soc/s8001/b0/tunable/switchfabric.h>
|
||||
#include <soc/s8001/b0/tunable/pms_csr.h>
|
||||
#include <soc/s8001/b0/tunable/afc_aiu_sb.h>
|
||||
#include <soc/s8001/b0/tunable/sb_glue.h>
|
||||
#include <soc/s8001/b0/tunable/misc1.h>
|
||||
#include <soc/s8001/b0/tunable/cp_com.h>
|
||||
|
||||
|
||||
static const struct tunable_struct pmsasyncfifo_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_PMSASYNCFIFO_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct minipmgr_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8001_EXTRA,
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct64 acc_tunable_b0[] = {
|
||||
ACC_DEFAULT_TUNABLES_S8001_EXTRA,
|
||||
ACC_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct socbusmux_tunable_b0[] = {
|
||||
SOCBUSMUX_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct switchfabric_tunable_b0[] = {
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8001_EXTRA,
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct pms_csr_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMS_CSR_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct sb_glue_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_DYNAMIC_CLK_GATING_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct afc_aiu_sb_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct asio_misc1_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_ASIO_MISC1_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp0_cp_com_tunable_b0[] = {
|
||||
CP0_CP_COM_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp1_cp_com_tunable_b0[] = {
|
||||
CP1_CP_COM_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
/***************************************** END CHIP_REVISION_B0 *****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_A0 ****************************************/
|
||||
#include <soc/s8001/a0/tunable/minipmgr.h>
|
||||
#include <soc/s8001/a0/tunable/pmgr.h>
|
||||
#include <soc/s8001/a0/tunable/acc.h>
|
||||
#include <soc/s8001/a0/tunable/sbasyncfifo_widgets.h>
|
||||
#include <soc/s8001/a0/tunable/socbusmux.h>
|
||||
#include <soc/s8001/a0/tunable/switchfabric.h>
|
||||
#include <soc/s8001/a0/tunable/pms_csr.h>
|
||||
#include <soc/s8001/a0/tunable/afc_aiu_sb.h>
|
||||
#include <soc/s8001/a0/tunable/sb_glue.h>
|
||||
#include <soc/s8001/a0/tunable/misc1.h>
|
||||
#include <soc/s8001/a0/tunable/cp_com.h>
|
||||
|
||||
static const struct tunable_struct pmsasyncfifo_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_PMSASYNCFIFO_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct minipmgr_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8001_EXTRA,
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct64 acc_tunable_a0[] = {
|
||||
ACC_DEFAULT_TUNABLES_S8001_EXTRA,
|
||||
ACC_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct socbusmux_tunable_a0[] = {
|
||||
SOCBUSMUX_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct switchfabric_tunable_a0[] = {
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8001_EXTRA,
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct pms_csr_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMS_CSR_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct sb_glue_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_DYNAMIC_CLK_GATING_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct afc_aiu_sb_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct asio_misc1_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_ASIO_MISC1_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp0_cp_com_tunable_a0[] = {
|
||||
CP0_CP_COM_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp1_cp_com_tunable_a0[] = {
|
||||
CP1_CP_COM_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
/***************************************** END CHIP_REVISION_A0 *****************************************/
|
||||
|
||||
// For each chip, highest revision must come first.
|
||||
// Notice reconfig == false for minipmgr, since it's an AOP.
|
||||
const struct tunable_chip_struct tunables_pmgr[] = {
|
||||
// B0
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8001_B0, pmgr_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_AOP_MINIPMGR_PADDR_S8001_B0, minipmgr_tunable_b0, NULL, false},
|
||||
{CHIP_REVISION_B0, ACC_PADDR_S8001_B0, NULL, acc_tunable_b0, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_PMSASYNCFIFO_PADDR_S8001_B0, pmsasyncfifo_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOCBUSMUX_PADDR_S8001_B0, socbusmux_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SWITCHFABRIC_PADDR_S8001_B0, switchfabric_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_PMS_PMS_CSR_PADDR_S8001_B0, pms_csr_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_DYNAMIC_CLK_GATING_PADDR_S8001_B0, sb_glue_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_PADDR_S8001_B0, afc_aiu_sb_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_ASIO_MISC1_PADDR_S8001_B0, asio_misc1_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, CP0_CP_COM_PADDR_S8001_B0, cp0_cp_com_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, CP1_CP_COM_PADDR_S8001_B0, cp1_cp_com_tunable_b0, NULL, true},
|
||||
|
||||
// A0
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8001_A0, pmgr_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_AOP_MINIPMGR_PADDR_S8001_A0, minipmgr_tunable_a0, NULL, false},
|
||||
{CHIP_REVISION_A0, ACC_PADDR_S8001_A0, NULL, acc_tunable_a0, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_PMSASYNCFIFO_PADDR_S8001_A0, pmsasyncfifo_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOCBUSMUX_PADDR_S8001_A0, socbusmux_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SWITCHFABRIC_PADDR_S8001_A0, switchfabric_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_PMS_PMS_CSR_PADDR_S8001_A0, pms_csr_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_DYNAMIC_CLK_GATING_PADDR_S8001_A0, sb_glue_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_PADDR_S8001_A0, afc_aiu_sb_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_ASIO_MISC1_PADDR_S8001_A0, asio_misc1_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, CP0_CP_COM_PADDR_S8001_A0, cp0_cp_com_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, CP1_CP_COM_PADDR_S8001_A0, cp1_cp_com_tunable_a0, NULL, true},
|
||||
|
||||
{0, 0, NULL, NULL, 0}
|
||||
};
|
||||
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* This file contains Tunables for s8001 ipad6b */
|
||||
|
||||
#include <platform/tunables.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <soc/module/address_map.h>
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_ALL ****************************************/
|
||||
// <rdar://problem/22709991> Update iBoot/PMGR driver settings for enabling UV_WARN for J127/J105
|
||||
#define SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_IPAD6B_EXTRA \
|
||||
{ /*! GFX_THROTTLE_DITHER0_INT */ 0x7403c, sizeof(uint32_t), 0xffffffffu, 0x480000u}, \
|
||||
{ /*! GFX_THROTTLE_DITHER0 */ 0x74040, sizeof(uint32_t), 0xffffffffu, 0x10555u}, \
|
||||
{ /*! GFX_THROTTLE_DITHER1 */ 0x74044, sizeof(uint32_t), 0xffffffffu, 0x106dbu}, \
|
||||
{ /*! GFX_THROTTLE_DITHER2 */ 0x74048, sizeof(uint32_t), 0xffffffffu, 0x10fffu}, \
|
||||
{ /*! GFX_THROTTLE_DITHER3 */ 0x7404c, sizeof(uint32_t), 0xffffffffu, 0x00fffu}, \
|
||||
{ /*! GFX_THROTTLE_DITHER4 */ 0x74050, sizeof(uint32_t), 0xffffffffu, 0x00fffu}, \
|
||||
{ /*! GFX_THROTTLE_DITHER5 */ 0x74054, sizeof(uint32_t), 0xffffffffu, 0x00fffu}, \
|
||||
{ /*! GFX_THROTTLE_SRC2_CTL */ 0x74078, sizeof(uint32_t), 0xffffffffu, 0x00003u}, \
|
||||
{ /*! GFX_THROTTLE_SRC2_ASSERT_COUNT */ 0x7407c, sizeof(uint32_t), 0xffffffffu, 0x00000u}, \
|
||||
{ /*! GFX_THROTTLE_SRC2_DEASSERT_COUNT */ 0x74080, sizeof(uint32_t), 0xffffffffu, 0x00000u}, \
|
||||
{ /*! GFX_THROTTLE_SRC2_MIN_ACTIVE_COUNT */ 0x74084, sizeof(uint32_t), 0xffffffffu, 0x00000u}, \
|
||||
{ /*! GFX_PERF_CFG4 */ 0xfc140, sizeof(uint32_t), 0xffffffffu, 0x10003u}, \
|
||||
{ /*! GFX_PERF_CFG5 */ 0xfc150, sizeof(uint32_t), 0xffffffffu, 0x10001u}, \
|
||||
{ /*! GFX_PERF_CTL */ 0xfc000, sizeof(uint32_t), 0xffffffffu, 0x00003u}, \
|
||||
{ -1, -1, -1, -1 }
|
||||
/**************************************** END CHIP_REVISION_ALL ****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_B0 ****************************************/
|
||||
#include <soc/s8001/b0/tunable/pmgr.h>
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_IPAD6B_EXTRA
|
||||
};
|
||||
|
||||
/***************************************** END CHIP_REVISION_B0 *****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_A0 ****************************************/
|
||||
#include <soc/s8001/a0/tunable/pmgr.h>
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_IPAD6B_EXTRA
|
||||
};
|
||||
|
||||
/***************************************** END CHIP_REVISION_A0 *****************************************/
|
||||
|
||||
// For each chip, highest revision must come first.
|
||||
// Notice reconfig == false for minipmgr, since it's an AOP.
|
||||
const struct tunable_chip_struct tunables_pmgr_product[] = {
|
||||
// B0
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8001_B0, pmgr_tunable_b0, NULL, true},
|
||||
|
||||
// A0
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8001_A0, pmgr_tunable_a0, NULL, true},
|
||||
|
||||
{0, 0, NULL, NULL, 0}
|
||||
};
|
||||
@@ -0,0 +1,203 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* This file contains Tunables for s8003 */
|
||||
|
||||
#include <platform/tunables.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <soc/module/address_map.h>
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_ALL ****************************************/
|
||||
// <rdar://problem/21347912> Add support for product / platform specific tunables
|
||||
#define SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8003_EXTRA \
|
||||
{ /*! PLL0_CFG */ 0x00004, sizeof(uint32_t), 0xc0000000u, 0x40000000u}, \
|
||||
{ /*! PLL1_CFG */ 0x04004, sizeof(uint32_t), 0xc0000000u, 0x40000000u}, \
|
||||
{ /*! VOLMAN_SOC_DELAY */ 0xa001c, sizeof(uint32_t), 0xfffffcffu, 0xbb81642fu}, \
|
||||
{ /*! VOLMAN_GFX_SRAM_DELAY */ 0xa0020, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_CPU_SRAM_DELAY */ 0xa0024, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_GFX_DELAY */ 0xa0028, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_CPU_DELAY */ 0xa002c, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}
|
||||
|
||||
// <rdar://problem/20545478> Add DVMR tunables in tunables PDF to SPDS tunables
|
||||
// <rdar://problem/20620070> Add CPU TVM tunables in tunables PDF to SPDS tunables
|
||||
#define ACC_DEFAULT_TUNABLES_S8003_EXTRA \
|
||||
/* Configure temperature ranges and measurement offsets for DVFM/DVTM */ \
|
||||
/* temp_thread0 0x8 temp_thresh1 0x21 temp_offset0 0 temp_offset1 0 */ \
|
||||
{ /* ACC_PWRCTL_DVFM_CFG */ 0x220040, sizeof(uint32_t), 0x0fffffffu, 0x00001088u}, \
|
||||
/* temp_thresh2 0x3a temp_offset2 0 */ \
|
||||
{ /* ACC_PWRCTL_DVFM_CFG1 */ 0x220058, sizeof(uint32_t), 0x001fffffu, 0x0000003au}, \
|
||||
{ /* ACC_PWRCTL_DVMR_SCR */ 0x2206b8, sizeof(uint64_t), 0x00000fffu, 0x000000421}
|
||||
|
||||
#define SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8003_EXTRA \
|
||||
/* <rdar://problem/20868785> Ensure that LPO OFF_MODE is set appropriately */ \
|
||||
{ /*! MINIPMGR_LPO_CFG */ 0x00004, sizeof(uint32_t), 0xc0000000u, 0x80000000u }
|
||||
|
||||
// <rdar://problem/17755256> SwitchFabric Hash lock bit is not set
|
||||
#define SWITCHFABRIC_DEFAULT_TUNABLES_S8003_EXTRA \
|
||||
{ /*! SWITCHFABRIC_REGS_AMAP_LOCK */ 0x00000, sizeof(uint32_t), 0x00000001u, 0x00000001u }
|
||||
/**************************************** END CHIP_REVISION_ALL ****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_A1 ****************************************/
|
||||
#include <soc/s8003/a1/tunable/minipmgr.h>
|
||||
#include <soc/s8003/a1/tunable/pmgr.h>
|
||||
#include <soc/s8003/a1/tunable/acc.h>
|
||||
#include <soc/s8003/a1/tunable/sbasyncfifo_widgets.h>
|
||||
#include <soc/s8003/a1/tunable/socbusmux.h>
|
||||
#include <soc/s8003/a1/tunable/switchfabric.h>
|
||||
#include <soc/s8003/a1/tunable/pms_csr.h>
|
||||
#include <soc/s8003/a1/tunable/afc_aiu_sb.h>
|
||||
#include <soc/s8003/a1/tunable/sb_glue.h>
|
||||
#include <soc/s8003/a1/tunable/misc1.h>
|
||||
#include <soc/s8003/a1/tunable/cp_com.h>
|
||||
|
||||
static const struct tunable_struct pmsasyncfifo_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_PMSASYNCFIFO_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8003_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct minipmgr_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8003_EXTRA,
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct64 acc_tunable_a1[] = {
|
||||
ACC_DEFAULT_TUNABLES_S8003_EXTRA,
|
||||
ACC_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct socbusmux_tunable_a1[] = {
|
||||
SOCBUSMUX_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct switchfabric_tunable_a1[] = {
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8003_EXTRA,
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct pms_csr_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_PMS_PMS_CSR_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct sb_glue_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_DYNAMIC_CLK_GATING_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct afc_aiu_sb_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct asio_misc1_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_ASIO_MISC1_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp_com_tunable_a1[] = {
|
||||
CP_CP_COM_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
/***************************************** END CHIP_REVISION_A1 *****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_A0 ****************************************/
|
||||
#include <soc/s8003/a0/tunable/minipmgr.h>
|
||||
#include <soc/s8003/a0/tunable/pmgr.h>
|
||||
#include <soc/s8003/a0/tunable/acc.h>
|
||||
#include <soc/s8003/a0/tunable/sbasyncfifo_widgets.h>
|
||||
#include <soc/s8003/a0/tunable/socbusmux.h>
|
||||
#include <soc/s8003/a0/tunable/switchfabric.h>
|
||||
#include <soc/s8003/a0/tunable/pms_csr.h>
|
||||
#include <soc/s8003/a0/tunable/afc_aiu_sb.h>
|
||||
#include <soc/s8003/a0/tunable/sb_glue.h>
|
||||
#include <soc/s8003/a0/tunable/misc1.h>
|
||||
#include <soc/s8003/a0/tunable/cp_com.h>
|
||||
|
||||
static const struct tunable_struct pmsasyncfifo_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_PMSASYNCFIFO_DEFAULT_TUNABLES_S8003_A0,
|
||||
};
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8003_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct minipmgr_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8003_EXTRA,
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct64 acc_tunable_a0[] = {
|
||||
ACC_DEFAULT_TUNABLES_S8003_EXTRA,
|
||||
ACC_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct socbusmux_tunable_a0[] = {
|
||||
SOCBUSMUX_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct switchfabric_tunable_a0[] = {
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8003_EXTRA,
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct pms_csr_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMS_CSR_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct sb_glue_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_DYNAMIC_CLK_GATING_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct afc_aiu_sb_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct asio_misc1_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_ASIO_MISC1_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp_com_tunable_a0[] = {
|
||||
CP_CP_COM_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
/***************************************** END CHIP_REVISION_A0 *****************************************/
|
||||
|
||||
// For each chip, highest revision must come first.
|
||||
// Notice reconfig == false for minipmgr, since it's an AOP.
|
||||
const struct tunable_chip_struct tunables_pmgr[] = {
|
||||
// A1
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8003_A1, pmgr_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_AOP_MINIPMGR_PADDR_S8003_A1, minipmgr_tunable_a1, NULL, false},
|
||||
{CHIP_REVISION_A1, ACC_PADDR_S8003_A1, NULL, acc_tunable_a1, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_PMSASYNCFIFO_PADDR_S8003_A1, pmsasyncfifo_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOCBUSMUX_PADDR_S8003_A1, socbusmux_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SWITCHFABRIC_PADDR_S8003_A1, switchfabric_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_PMS_PMS_CSR_PADDR_S8003_A1, pms_csr_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_DYNAMIC_CLK_GATING_PADDR_S8003_A1, sb_glue_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_PADDR_S8003_A1, afc_aiu_sb_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_ASIO_MISC1_PADDR_S8003_A1, asio_misc1_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, CP_CP_COM_PADDR_S8003_A1, cp_com_tunable_a1, NULL, true},
|
||||
|
||||
// A0
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8003_A0, pmgr_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_AOP_MINIPMGR_PADDR_S8003_A0, minipmgr_tunable_a0, NULL, false},
|
||||
{CHIP_REVISION_A0, ACC_PADDR_S8003_A0, NULL, acc_tunable_a0, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_PMSASYNCFIFO_PADDR_S8003_A0, pmsasyncfifo_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOCBUSMUX_PADDR_S8003_A0, socbusmux_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SWITCHFABRIC_PADDR_S8003_A0, switchfabric_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_PMS_PMS_CSR_PADDR_S8003_A0, pms_csr_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_DYNAMIC_CLK_GATING_PADDR_S8003_A0, sb_glue_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_PADDR_S8003_A0, afc_aiu_sb_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_ASIO_MISC1_PADDR_S8003_A0, asio_misc1_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, CP_CP_COM_PADDR_S8003_A0, cp_com_tunable_a0, NULL, true},
|
||||
|
||||
{0, 0, NULL, NULL, 0}
|
||||
};
|
||||
@@ -0,0 +1,921 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/dcs/dcs.h>
|
||||
#include <drivers/dcs/dcs_regs.h>
|
||||
#include <drivers/dcs/dcs_init_lib.h>
|
||||
#include <drivers/dram.h>
|
||||
#include <drivers/miu.h>
|
||||
#include <drivers/reconfig.h>
|
||||
#include <sys.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
|
||||
int mcu_initialize_dram (bool resume)
|
||||
{
|
||||
dcs_boottype_t boot_type;
|
||||
|
||||
// Don't perform DRAM initializion if the memory controller is already
|
||||
// initialized (e.g., for SecureROM validation testing).
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
if (resume || DCS_REG_READ_CH(0, rDCS_MCU_AMCCTRL) == 0) {
|
||||
#endif
|
||||
clock_gate(CLK_DCS0, true);
|
||||
clock_gate(CLK_DCS1, true);
|
||||
clock_gate(CLK_DCS2, true);
|
||||
clock_gate(CLK_DCS3, true);
|
||||
#if SUB_PLATFORM_S8001 && DCS_NUM_CHANNELS > 4
|
||||
clock_gate(CLK_DCS4, true);
|
||||
clock_gate(CLK_DCS5, true);
|
||||
clock_gate(CLK_DCS6, true);
|
||||
clock_gate(CLK_DCS7, true);
|
||||
#endif
|
||||
clock_gate(CLK_MCC, true);
|
||||
|
||||
boot_type = (resume)? DCS_BOOT_RESUME:DCS_BOOT_COLDBOOT;
|
||||
// NOTE: Boot types AOP_DDR or AOP_AWAKE do not use this Code
|
||||
// For those cases, the Init sequence is executed by the AOP
|
||||
|
||||
// Perform the LPDDR4 Init for this type of Boot
|
||||
dcs_init(boot_type);
|
||||
|
||||
// <rdar://problem/18602531> Maui A1: Samsung 25nm LP4 RBM failures - WA
|
||||
// Can't do this as part of dcs_dram_workarounds because reg value gets overwritten later in the sequence
|
||||
const struct dcs_memory_device_info *dev_info = dcs_get_memory_device_info();
|
||||
if(dev_info->vendor_id == JEDEC_LPDDR4_MANUF_ID_SAMSUNG)
|
||||
if(dev_info->rev_id == 0x3 && dev_info->rev_id2 == 0x0)
|
||||
for(uint32_t channel = 0; channel < DCS_NUM_CHANNELS; channel++)
|
||||
DCS_REG_ACCESS(rDCS_MCU_AREFEN_FREQ(0) + (channel * DCS_SPACING)) = 0x1010013f;
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dcs_lock_down_mcc(void)
|
||||
{
|
||||
// Don't allow MCC as RAM
|
||||
rAMCC_MCCGEN &= ~AMCC_MCCGEN_MCC_RAM_EN;
|
||||
rAMCC_MCCGEN |= AMCC_MCCGEN_MCC_RAM_EN_LOCK;
|
||||
// Don't allow tag RAM reads
|
||||
rAMCC_MCCCFG_TAG_RD_DIS |= 1;
|
||||
#if NUM_AMCCS > 1
|
||||
rAMCC1_MCCGEN &= ~AMCC_MCCGEN_MCC_RAM_EN;
|
||||
rAMCC1_MCCGEN |= AMCC_MCCGEN_MCC_RAM_EN_LOCK;
|
||||
rAMCC1_MCCCFG_TAG_RD_DIS |= 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
void mcu_bypass_prep (int step)
|
||||
{
|
||||
}
|
||||
|
||||
uint64_t mcu_get_memory_size (void)
|
||||
{
|
||||
return dcs_get_memory_size();
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
void dcs_enable_slow_boot (bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
// switch to slow clock
|
||||
clocks_set_performance(kPerformanceMemoryLow);
|
||||
spin(1);
|
||||
}
|
||||
else {
|
||||
#if !SUPPORT_FPGA
|
||||
// switch back to full-speed
|
||||
clocks_set_performance(kPerformanceMemoryFull);
|
||||
spin(1);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// https://seg-docs.ecs.apple.com/projects/malta//release/UserManual/Hx_LPDDR4_RevID_Workaround.pdf
|
||||
void dcs_dram_workarounds(dcs_boottype_t boot_type)
|
||||
{
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
uint32_t autoref_freq1;
|
||||
#endif
|
||||
#if SUB_PLATFORM_S8000
|
||||
uint32_t dqvref_freq1;
|
||||
#endif
|
||||
|
||||
if(boot_type == DCS_BOOT_COLDBOOT) {
|
||||
|
||||
const struct dcs_memory_device_info *dev_info = dcs_get_memory_device_info();
|
||||
|
||||
switch (dev_info->vendor_id) {
|
||||
case JEDEC_LPDDR4_MANUF_ID_SAMSUNG:
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
if(dev_info->rev_id == 5 && dev_info->rev_id2 == 1) {
|
||||
// <rdar://problem/21042636> tRFCpbCyc_freq1 = 0x1c for Samsung
|
||||
autoref_freq1 = DCS_REG_READ_CH(0, rDCS_MCU_AUTOREF_FREQ(1));
|
||||
autoref_freq1 &= 0x00ffffff;
|
||||
autoref_freq1 |= (0x1c << 24);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_FREQ(1), autoref_freq1);
|
||||
}
|
||||
#endif
|
||||
#if SUB_PLATFORM_S8000
|
||||
if(dev_info->rev_id == 5) {
|
||||
dqvref_freq1 = 0x00ec00ec; // Maui
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ0, 1), dqvref_freq1);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ1, 1), dqvref_freq1);
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
|
||||
case JEDEC_LPDDR4_MANUF_ID_HYNIX:
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
if(dev_info->rev_id == 3 && dev_info->rev_id2 == 2) {
|
||||
// <rdar://problem/21042636> tRFCpbCyc_freq1 = 0x1c for Hynix
|
||||
autoref_freq1 = DCS_REG_READ_CH(0, rDCS_MCU_AUTOREF_FREQ(1));
|
||||
autoref_freq1 &= 0x00ffffff;
|
||||
autoref_freq1 |= (0x1c << 24);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_FREQ(1), autoref_freq1);
|
||||
}
|
||||
#endif
|
||||
#if SUB_PLATFORM_S8000
|
||||
if(dev_info->rev_id == 3) {
|
||||
dqvref_freq1 = 0x00df00df; // Maui
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ0, 1), dqvref_freq1);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ1, 1), dqvref_freq1);
|
||||
}
|
||||
#endif
|
||||
|
||||
// <rdar://problem/18183851> Workarounds: Pull Up/Down shift for Maui Hynix 25nm
|
||||
if(dev_info->rev_id == 0x3) {
|
||||
// Test MRS Exit
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0x0);
|
||||
|
||||
// Test MRS Entry
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0xb0);
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0xe0);
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0x90);
|
||||
|
||||
if(dev_info->rev_id2 == 0x0) {
|
||||
// Rising Slew-rate up
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0x87);
|
||||
|
||||
// Self-refresh OSC Min
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0xd0);
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0x90);
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0x86);
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0x81);
|
||||
}
|
||||
|
||||
// For all SoCs that use this particular DRAM
|
||||
if(dev_info->rev_id2 <= 0x1) {
|
||||
// Pull Up RON shift
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0xc4);
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0x90);
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0x8e);
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0x81);
|
||||
|
||||
// Pull Down RON shift
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0xc4);
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0x94);
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0x92);
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0x81);
|
||||
|
||||
// ZQ calibration START MPC cmd
|
||||
dcs_mrcmd(MR_MPC, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x0, 0x4f);
|
||||
// wait 1us for tZQCAL
|
||||
dcs_spin(1, "Workarounds -- tZQCAL");
|
||||
|
||||
// ZQ calibration LATCH MPC cmd
|
||||
dcs_mrcmd(MR_MPC, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x0, 0x51);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case JEDEC_LPDDR4_MANUF_ID_MICRON:
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
if(dev_info->rev_id == 1 && dev_info->rev_id2 == 2) {
|
||||
// <rdar://problem/21042636> tRFCpbCyc_freq1 = 0x20 for Micron
|
||||
autoref_freq1 = DCS_REG_READ_CH(0, rDCS_MCU_AUTOREF_FREQ(1));
|
||||
autoref_freq1 &= 0x00ffffff;
|
||||
autoref_freq1 |= (0x20 << 24);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_FREQ(1), autoref_freq1);
|
||||
}
|
||||
#endif
|
||||
#if SUB_PLATFORM_S8000
|
||||
if(dev_info->rev_id == 1) {
|
||||
dqvref_freq1 = 0x00ea00ea; // Maui
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ0, 1), dqvref_freq1);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ1, 1), dqvref_freq1);
|
||||
}
|
||||
#endif
|
||||
|
||||
if(dev_info->rev_id == 0x1) {
|
||||
// Test MRS Exit
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0x0);
|
||||
|
||||
// <rdar://problem/20303861> Test MRS: Disable VREFDQ TAP code local latch
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0xf1);
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x9, 0x40);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
void dcs_dram_workarounds_step12 ( void )
|
||||
{
|
||||
|
||||
const struct dcs_memory_device_info *dev_info = dcs_get_memory_device_info();
|
||||
|
||||
if ( (dev_info->vendor_id == JEDEC_LPDDR4_MANUF_ID_SAMSUNG) && (dev_info->rev_id == 5) && (dev_info->rev_id2 == 1) )
|
||||
{
|
||||
|
||||
if((dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_C0) || (dcs_cfg.chipID == 0x8003 && dcs_cfg.chipRev >= CHIP_REVISION_A1) ||
|
||||
(dcs_cfg.chipID == 0x8001 && dcs_cfg.chipRev >= CHIP_REVISION_B0) )
|
||||
{
|
||||
dcs_mrcmd(MR_WRITE, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x0b, 0x34);
|
||||
dcs_mrcmd(MR_MPC, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x00, 0x4F);
|
||||
dcs_spin(1, "Workaround-Samsung--step-12-tzQCAL");
|
||||
dcs_mrcmd(MR_MPC, DCS_NUM_CHANNELS, DCS_NUM_RANKS, 0x00, 0x51);
|
||||
dcs_spin(1, "Workaround-Samsung--step-12-tZQLAT");
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL_FREQ(2, 0), 0xb303340b);
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
//================================================================================
|
||||
// Grab (Platform Specific) Tables with Definitions of Values for DCS Init & DCS Tunables
|
||||
#include <platform/dcsconfig.h>
|
||||
|
||||
#if DCS_FIXUP_PARAMS
|
||||
// Grab (Target Specific) Definition of Required Fixups to the Values for DCS Init
|
||||
#include <target/dcsfixup.h>
|
||||
#endif
|
||||
|
||||
// use_dcs_params is already the same as dcs_params, unless we want to override with older chip-rev or target specific values
|
||||
void dcs_init_config_params(dcs_config_params_t *use_dcs_params, dcs_target_t targtype)
|
||||
{
|
||||
#if SUB_PLATFORM_S8000
|
||||
// Maui B0 DCS param table
|
||||
if(platform_get_chip_revision() < CHIP_REVISION_C0)
|
||||
memcpy(use_dcs_params, &dcs_params_b0, sizeof(dcs_config_params_t));
|
||||
#endif
|
||||
|
||||
#if DCS_FIXUP_PARAMS
|
||||
// This gives the particular target a chance to make target-specific changes
|
||||
dcs_init_config_fixup_params(use_dcs_params, targtype);
|
||||
#endif
|
||||
}
|
||||
|
||||
const dcs_tunable_t *dcs_init_tunable_table(uint32_t *table_len)
|
||||
{
|
||||
const dcs_tunable_t *tunables = dcs_tunables;
|
||||
uint32_t tunables_size = sizeof(dcs_tunables);
|
||||
|
||||
#if SUB_PLATFORM_S8000
|
||||
// Maui B0 DCS tunables
|
||||
if(platform_get_chip_revision() < CHIP_REVISION_C0) {
|
||||
tunables = dcs_tunables_b0;
|
||||
tunables_size = sizeof(dcs_tunables_b0);
|
||||
}
|
||||
#endif
|
||||
|
||||
if (table_len)
|
||||
*table_len = tunables_size / sizeof(tunables[0]);
|
||||
|
||||
return tunables;
|
||||
}
|
||||
|
||||
void dcs_aop_ddr_to_awake_post_tunables_insert(void)
|
||||
{
|
||||
uint32_t i, num_tunables = 0;
|
||||
const dcs_tunable_t *tunables = NULL;
|
||||
uintptr_t curr_reg = 0;
|
||||
uint32_t reg_val = 0;
|
||||
|
||||
tunables = dcs_init_tunable_table(&num_tunables);
|
||||
|
||||
// At the time this function is called, tunables values are already expected to be programmed into the registers.
|
||||
// Expected format of the dcs_tunables table: Each field that has a tunable value is 1 entry in the tunables table
|
||||
for(i = 0; i < num_tunables; i++, tunables++) {
|
||||
|
||||
// end of table
|
||||
if(tunables->reg == 0)
|
||||
break;
|
||||
|
||||
// skip over subsequent tunables values for different fields in the same register, since we read out the entire register the first time
|
||||
if(tunables->reg == curr_reg)
|
||||
continue;
|
||||
|
||||
curr_reg = tunables->reg;
|
||||
|
||||
if(dcs_reg_is_outside_dcs_block(curr_reg)) {
|
||||
reg_val = DCS_REG_ACCESS(curr_reg);
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, curr_reg, reg_val, false);
|
||||
} else {
|
||||
// if reg is within DCS hw block, the reg is duplicated for each instance of the hw block, just read out 1st instance
|
||||
// and write that value for all instances
|
||||
reg_val = DCS_REG_READ_CH(0, curr_reg);
|
||||
|
||||
for(uint32_t channel = 0; channel < DCS_NUM_CHANNELS; channel++)
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, (curr_reg + (channel * DCS_SPACING)), reg_val, false);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
//================================================================================
|
||||
// Save off calibration results to AOP_SRAM region (later to be stitched into mcu_aop_awake_reconfig_restore sequence)
|
||||
// Order of registers to be saved matches the order in the reconfig sequence
|
||||
volatile uint32_t *dcs_save_calibration_results(volatile uint32_t *save_region, uint32_t freq)
|
||||
{
|
||||
uint32_t ch, n;
|
||||
|
||||
// Registers to be saved off after calibration in freq 1 has completed
|
||||
if (freq == DCS_FREQ(1)) {
|
||||
// CASDLLCTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_CASDLLCTRL(ch));
|
||||
|
||||
// CSSDLLCTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_CSSDLLCTRL(ch));
|
||||
|
||||
// CKSDLLCTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_CKSDLLCTRL(ch));
|
||||
|
||||
// AMPCAWRLVLSDLLCODE
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_CAWRLVLSDLLCODE(ch));
|
||||
|
||||
// CA_DESKEW_CTRL
|
||||
for(n = 0; n < CA_NUM_BITS; n++)
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_CADESKEW_CTRL(ch, n));
|
||||
|
||||
// CS_DESKEW_CTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_CSDESKEW_CTRL(ch));
|
||||
|
||||
// CK_DESKEW_CTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_CKDESKEW_CTRL(ch));
|
||||
|
||||
// AMPWRLVLSDLLCODE0
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_DQWRLVLSDLLCODE(0, ch));
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_DQWRLVLSDLLCODE(1, ch));
|
||||
}
|
||||
|
||||
// VREF_Fx
|
||||
for(n = 0; n < DCS_FREQUENCY_SLOTS; n++) {
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_VREF_F(AMP_DQ0, n));
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_VREF_F(AMP_DQ1, n));
|
||||
}
|
||||
}
|
||||
|
||||
// AUTOREF_FREQ1
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_MCU_AUTOREF_FREQ(1));
|
||||
|
||||
// CAMDLLVTSCALEREFCONTROL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_CAMDLL_VTSCALE_REFCNTL(AMP_DQ0));
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_CAMDLL_VTSCALE_REFCNTL(AMP_DQ1));
|
||||
}
|
||||
|
||||
// RDMDLLVTSCALEREFCONTROL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_RDMDLL_VTSCALE_REFCNTL(AMP_DQ0));
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_RDMDLL_VTSCALE_REFCNTL(AMP_DQ1));
|
||||
}
|
||||
|
||||
// WRMDLLVTSCALEREFCONTROL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_WRMDLL_VTSCALE_REFCNTL(AMP_DQ0));
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_WRMDLL_VTSCALE_REFCNTL(AMP_DQ1));
|
||||
}
|
||||
|
||||
// FREQCHNGCTL1_FREQ1
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_MCU_FREQCHNGCTL_FREQ(1, 1));
|
||||
|
||||
} else if (freq == DCS_FREQ(0)) {
|
||||
// Registers to be saved off after calibration in freq 0 has completed
|
||||
|
||||
// VREF_F0
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_VREF_F(AMP_DQ0, 0));
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_VREF_F(AMP_DQ1, 0));
|
||||
}
|
||||
|
||||
// FREQCHNGCTL1_FREQ0
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_MCU_FREQCHNGCTL_FREQ(1, 0));
|
||||
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_MCU_FREQCHNGCTL_FREQ(2, 0));
|
||||
} else if (freq == 0) {
|
||||
// <rdar://problem/23355941> Maui/Malta: Samsung DRAM workaround: disable hw zqcal
|
||||
// rGLBTIMER_ZQCTIMER
|
||||
*save_region++ = DCS_REG_ACCESS(rGLBTIMER_ZQCTIMER);
|
||||
}
|
||||
|
||||
return save_region;
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Stitch the saved calibration results into the reconfig sequence
|
||||
// To be called immediately after stitching mcu_aop_awake_reconfig_pre_restore
|
||||
// Uses mcu_aop_awake_reconfig_restore as reference for register order and fields
|
||||
void dcs_restore_calibration_results(volatile uint32_t *save_region)
|
||||
{
|
||||
uint32_t ch, n, f;
|
||||
uint32_t reg_val;
|
||||
|
||||
// CASDLLCTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = ((*save_region) & SDLLOVRVAL_MASK) | RUNSDLLUPDWRRESULT;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rAMP_CASDLLCTRL(ch), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// CSSDLLCTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = ((*save_region) & SDLLOVRVAL_MASK) | RUNSDLLUPDWRRESULT;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rAMP_CSSDLLCTRL(ch), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// CKSDLLCTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = ((*save_region) & SDLLOVRVAL_MASK) | RUNSDLLUPDWRRESULT;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rAMP_CKSDLLCTRL(ch), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// AMPCAWRLVLSDLLCODE
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = ((*save_region) & WRLVLSDLLCODE_MASK) | WRLVLRUNUPDWRRESULT;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rAMP_CAWRLVLSDLLCODE(ch), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// Poll for AMPCAWRLVLSDLLCODE.WRLVLRUNUPDWRRESULT to clear
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
reconfig_command_read(AOP_DDR_AWAKE_POST, rAMP_CAWRLVLSDLLCODE(ch), 0, WRLVLRUNUPDWRRESULT, 0, false);
|
||||
|
||||
// CA_DESKEW_CTRL
|
||||
for(n = 0; n < CA_NUM_BITS; n++) {
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = ((*save_region) & DESKEWCODE_MASK) | RUNDESKEWUPD;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rAMP_CADESKEW_CTRL(ch, n), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
}
|
||||
|
||||
// CS_DESKEW_CTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = ((*save_region) & DESKEWCODE_MASK) | RUNDESKEWUPD;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rAMP_CSDESKEW_CTRL(ch), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// CK_DESKEW_CTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = ((*save_region) & DESKEWCODE_MASK) | RUNDESKEWUPD;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rAMP_CKDESKEW_CTRL(ch), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// AMPWRLVLSDLLCODE0
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
// for DQ0 and DQ1
|
||||
for(n = 0; n < 2; n++) {
|
||||
reg_val = ((*save_region) & WRLVLSDLLCODE_MASK) | WRLVLRUNUPDWRRESULT;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rAMP_DQWRLVLSDLLCODE(n, ch), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
}
|
||||
|
||||
// VREF_Fx
|
||||
for(f = 0; f < DCS_FREQUENCY_SLOTS; f++) {
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
// for DQ0 and DQ1
|
||||
for(n = AMP_DQ0; n < DCS_AMP_NUM_PHYS; n++) {
|
||||
reg_val = (*save_region) & (VREFSEL_MASK | DQSVREFSEL_MASK);
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_AMP_VREF_F(n, f) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// AUTOREF_FREQ1
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = *save_region;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_MCU_AUTOREF_FREQ(1) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// CAMDLLVTSCALEREFCONTROL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
// for DQ0 and DQ1: shift the status field value into the override field
|
||||
for(n = AMP_DQ0; n < DCS_AMP_NUM_PHYS; n++) {
|
||||
reg_val = (((*save_region) & VTSCALEREFSTATUS_MASK) << VTSCALEREFOVERRIDEVAL_SHIFT) | VTSCALEREFUPDATE;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_AMP_CAMDLL_VTSCALE_REFCNTL(n) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
}
|
||||
|
||||
// RDMDLLVTSCALEREFCONTROL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
// for DQ0 and DQ1: shift the status field value into the override field
|
||||
for(n = AMP_DQ0; n < DCS_AMP_NUM_PHYS; n++) {
|
||||
reg_val = (((*save_region) & VTSCALEREFSTATUS_MASK) << VTSCALEREFOVERRIDEVAL_SHIFT) | VTSCALEREFUPDATE;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_AMP_RDMDLL_VTSCALE_REFCNTL(n) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
}
|
||||
|
||||
// WRMDLLVTSCALEREFCONTROL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
// for DQ0 and DQ1: shift the status field value into the override field
|
||||
for(n = AMP_DQ0; n < DCS_AMP_NUM_PHYS; n++) {
|
||||
reg_val = (((*save_region) & VTSCALEREFSTATUS_MASK) << VTSCALEREFOVERRIDEVAL_SHIFT) | VTSCALEREFUPDATE;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_AMP_WRMDLL_VTSCALE_REFCNTL(n) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
}
|
||||
|
||||
// FREQCHNGCTL1_FREQ1
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = *save_region;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_MCU_FREQCHNGCTL_FREQ(1, 1) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// The next set of registers were saved off after freq0 calibration completed
|
||||
|
||||
// VREF_F0
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = *save_region;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_AMP_VREF_F(AMP_DQ0, 0) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
|
||||
reg_val = *save_region;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_AMP_VREF_F(AMP_DQ1, 0) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// FREQCHNGCTL1_FREQ0
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = *save_region;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_MCU_FREQCHNGCTL_FREQ(1, 0) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// FREQCHNGCTL2_FREQ0
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = *save_region;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_MCU_FREQCHNGCTL_FREQ(2, 0) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// <rdar://problem/23355941> Maui/Malta: Samsung DRAM workaround: disable hw zqcal
|
||||
// rGLBTIMER_ZQCTIMER
|
||||
reg_val = *save_region;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rGLBTIMER_ZQCTIMER, reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
#endif // #if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
|
||||
#if SUB_PLATFORM_S8001
|
||||
//================================================================================
|
||||
// Save off calibration results to AOP_SRAM region (later to be stitched into mcu_aop_awake_reconfig_restore sequence)
|
||||
// Order of registers to be saved matches the order in the reconfig sequence
|
||||
volatile uint32_t *dcs_save_calibration_results(volatile uint32_t *save_region, uint32_t freq)
|
||||
{
|
||||
uint32_t ch, n;
|
||||
|
||||
if(freq == DCS_FREQ(0)) {
|
||||
// CASDLLCTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_CASDLLCTRL(ch));
|
||||
|
||||
// CSSDLLCTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_CSSDLLCTRL(ch));
|
||||
|
||||
// CKSDLLCTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_CKSDLLCTRL(ch));
|
||||
|
||||
// AMPCAWRLVLSDLLCODE
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_CAWRLVLSDLLCODE(ch));
|
||||
|
||||
// CA_DESKEW_CTRL
|
||||
for(n = 0; n < CA_NUM_BITS; n++)
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_CADESKEW_CTRL(ch, n));
|
||||
|
||||
// CS_DESKEW_CTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_CSDESKEW_CTRL(ch));
|
||||
|
||||
// CK_DESKEW_CTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_CKDESKEW_CTRL(ch));
|
||||
|
||||
// AMPWRLVLSDLLCODE0
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_DQWRLVLSDLLCODE(0, ch));
|
||||
*save_region++ = DCS_REG_ACCESS(rAMP_DQWRLVLSDLLCODE(1, ch));
|
||||
}
|
||||
|
||||
// VREF_Fx
|
||||
for(n = 0; n < DCS_FREQUENCY_SLOTS; n++) {
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_VREF_F(AMP_DQ0, n));
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_VREF_F(AMP_DQ1, n));
|
||||
}
|
||||
}
|
||||
|
||||
// WRDQCALVREFCODESTATUS
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_WRDQCALVREFCODESTATUS);
|
||||
|
||||
// RDDQCALVREFCODESTATUS
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_RDDQCALVREFCODESTATUS);
|
||||
|
||||
// CAMDLLVTSCALEREFCONTROL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_CAMDLL_VTSCALE_REFCNTL(AMP_DQ0));
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_CAMDLL_VTSCALE_REFCNTL(AMP_DQ1));
|
||||
}
|
||||
|
||||
// RDMDLLVTSCALEREFCONTROL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_RDMDLL_VTSCALE_REFCNTL(AMP_DQ0));
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_RDMDLL_VTSCALE_REFCNTL(AMP_DQ1));
|
||||
}
|
||||
|
||||
// WRMDLLVTSCALEREFCONTROL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_WRMDLL_VTSCALE_REFCNTL(AMP_DQ0));
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_AMP_WRMDLL_VTSCALE_REFCNTL(AMP_DQ1));
|
||||
}
|
||||
|
||||
// FREQCHNGCTL1_FREQ0
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_MCU_FREQCHNGCTL_FREQ(1, 0));
|
||||
|
||||
// FREQCHNGCTL2_FREQ0
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_MCU_FREQCHNGCTL_FREQ(2, 0));
|
||||
|
||||
// FREQCHNGCTL2_FREQ3
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_MCU_FREQCHNGCTL_FREQ(2, 3));
|
||||
|
||||
// FREQCHNGCTL4_FREQ0
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
*save_region++ = DCS_REG_READ_CH(ch, rDCS_MCU_FREQCHNGCTL_FREQ(4, 0));
|
||||
|
||||
// CB_IMPCTL
|
||||
*save_region++ = DCS_REG_READ_CH(0, rDCS_AMPH_CB_IMPCTL);
|
||||
|
||||
// B0_ODT
|
||||
*save_region++ = DCS_REG_READ_CH(0, rDCS_AMPH_B0_ODT);
|
||||
|
||||
// B1_ODT
|
||||
*save_region++ = DCS_REG_READ_CH(0, rDCS_AMPH_B1_ODT);
|
||||
|
||||
// DQS0_ODT
|
||||
*save_region++ = DCS_REG_READ_CH(0, rDCS_AMPH_DQS0_ODT);
|
||||
|
||||
// DQS1_ODT
|
||||
*save_region++ = DCS_REG_READ_CH(0, rDCS_AMPH_DQS1_ODT);
|
||||
} else if(freq == 0) {
|
||||
// <rdar://problem/23244578> Elba: Samsung DRAM workaround: disable hw zqcal
|
||||
// rGLBTIMER_ZQCTIMER
|
||||
*save_region++ = DCS_REG_ACCESS(rGLBTIMER_ZQCTIMER);
|
||||
}
|
||||
|
||||
return save_region;
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Stitch the saved calibration results into the reconfig sequence
|
||||
// To be called immediately after stitching mcu_aop_awake_reconfig_pre_restore
|
||||
// Uses mcu_aop_awake_reconfig_restore as reference for register order and fields
|
||||
void dcs_restore_calibration_results(volatile uint32_t *save_region)
|
||||
{
|
||||
uint32_t ch, n, f;
|
||||
uint32_t reg_val;
|
||||
|
||||
// CASDLLCTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = ((*save_region) & SDLLOVRVAL_MASK) | RUNSDLLUPDWRRESULT;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rAMP_CASDLLCTRL(ch), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// CSSDLLCTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = ((*save_region) & SDLLOVRVAL_MASK) | RUNSDLLUPDWRRESULT;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rAMP_CSSDLLCTRL(ch), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// CKSDLLCTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = ((*save_region) & SDLLOVRVAL_MASK) | RUNSDLLUPDWRRESULT;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rAMP_CKSDLLCTRL(ch), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// AMPCAWRLVLSDLLCODE
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = ((*save_region) & WRLVLSDLLCODE_MASK) | WRLVLRUNUPDWRRESULT;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rAMP_CAWRLVLSDLLCODE(ch), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// Poll for AMPCAWRLVLSDLLCODE.WRLVLRUNUPDWRRESULT to clear
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
reconfig_command_read(AOP_DDR_AWAKE_POST, rAMP_CAWRLVLSDLLCODE(ch), 0, WRLVLRUNUPDWRRESULT, 0, false);
|
||||
|
||||
// CA_DESKEW_CTRL
|
||||
for(n = 0; n < CA_NUM_BITS; n++) {
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = ((*save_region) & DESKEWCODE_MASK) | RUNDESKEWUPD;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rAMP_CADESKEW_CTRL(ch, n), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
}
|
||||
|
||||
// CS_DESKEW_CTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = ((*save_region) & DESKEWCODE_MASK) | RUNDESKEWUPD;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rAMP_CSDESKEW_CTRL(ch), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// CK_DESKEW_CTRL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = ((*save_region) & DESKEWCODE_MASK) | RUNDESKEWUPD;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rAMP_CKDESKEW_CTRL(ch), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// AMPWRLVLSDLLCODE0
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
// for DQ0 and DQ1
|
||||
for(n = 0; n < 2; n++) {
|
||||
reg_val = ((*save_region) & WRLVLSDLLCODE_MASK) | WRLVLRUNUPDWRRESULT;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rAMP_DQWRLVLSDLLCODE(n, ch), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
}
|
||||
|
||||
// VREF_Fx
|
||||
for(f = 0; f < DCS_FREQUENCY_SLOTS; f++) {
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
// for DQ0 and DQ1
|
||||
for(n = AMP_DQ0; n < DCS_AMP_NUM_PHYS; n++) {
|
||||
reg_val = (*save_region) & (VREFSEL_MASK | DQSVREFSEL_MASK);
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_AMP_VREF_F(n, f) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// WRDQCALVREFCODECONTROL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = (*save_region);
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_AMP_WRDQCALVREFCODECONTROL + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// RDDQCALVREFCODECONTROL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = (*save_region);
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_AMP_RDDQCALVREFCODECONTROL + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// CAMDLLVTSCALEREFCONTROL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
// for DQ0 and DQ1: shift the status field value into the override field
|
||||
for(n = AMP_DQ0; n < DCS_AMP_NUM_PHYS; n++) {
|
||||
reg_val = (((*save_region) & VTSCALEREFSTATUS_MASK) << VTSCALEREFOVERRIDEVAL_SHIFT) | VTSCALEREFUPDATE;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_AMP_CAMDLL_VTSCALE_REFCNTL(n) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
}
|
||||
|
||||
// RDMDLLVTSCALEREFCONTROL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
// for DQ0 and DQ1: shift the status field value into the override field
|
||||
for(n = AMP_DQ0; n < DCS_AMP_NUM_PHYS; n++) {
|
||||
reg_val = (((*save_region) & VTSCALEREFSTATUS_MASK) << VTSCALEREFOVERRIDEVAL_SHIFT) | VTSCALEREFUPDATE;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_AMP_RDMDLL_VTSCALE_REFCNTL(n) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
}
|
||||
|
||||
// WRMDLLVTSCALEREFCONTROL
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
// for DQ0 and DQ1: shift the status field value into the override field
|
||||
for(n = AMP_DQ0; n < DCS_AMP_NUM_PHYS; n++) {
|
||||
reg_val = (((*save_region) & VTSCALEREFSTATUS_MASK) << VTSCALEREFOVERRIDEVAL_SHIFT) | VTSCALEREFUPDATE;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_AMP_WRMDLL_VTSCALE_REFCNTL(n) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
}
|
||||
|
||||
// FREQCHNGCTL1_FREQ0
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = *save_region;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_MCU_FREQCHNGCTL_FREQ(1, 0) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// FREQCHNGCTL2_FREQ0
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = *save_region;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_MCU_FREQCHNGCTL_FREQ(2, 0) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// FREQCHNGCTL2_FREQ3
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = *save_region;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_MCU_FREQCHNGCTL_FREQ(2, 3) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// <rdar://problem/23244578> Elba: Samsung DRAM workaround: disable hw zqcal
|
||||
// FREQCHNGCTL4_FREQ0
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++) {
|
||||
reg_val = *save_region;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_MCU_FREQCHNGCTL_FREQ(4, 0) + (ch * DCS_SPACING), reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
|
||||
// CB_IMPCTL
|
||||
reg_val = *save_region;
|
||||
save_region++;
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_AMPH_CB_IMPCTL + (ch * DCS_SPACING), reg_val, false);
|
||||
|
||||
// B0_ODT
|
||||
reg_val = *save_region;
|
||||
save_region++;
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_AMPH_B0_ODT + (ch * DCS_SPACING), reg_val, false);
|
||||
|
||||
// B1_ODT
|
||||
reg_val = *save_region;
|
||||
save_region++;
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_AMPH_B1_ODT + (ch * DCS_SPACING), reg_val, false);
|
||||
|
||||
// DQS0_ODT
|
||||
reg_val = *save_region;
|
||||
save_region++;
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_AMPH_DQS0_ODT + (ch * DCS_SPACING), reg_val, false);
|
||||
|
||||
// DQS1_ODT
|
||||
reg_val = *save_region;
|
||||
save_region++;
|
||||
for(ch = 0; ch < DCS_NUM_CHANNELS; ch++)
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rDCS_AMPH_DQS1_ODT + (ch * DCS_SPACING), reg_val, false);
|
||||
|
||||
// rGLBTIMER_ZQCTIMER
|
||||
reg_val = *save_region;
|
||||
reconfig_command_write(AOP_DDR_AWAKE_POST, rGLBTIMER_ZQCTIMER, reg_val, false);
|
||||
save_region++;
|
||||
}
|
||||
#endif // #if SUB_PLATFORM_S8001
|
||||
|
||||
@@ -0,0 +1,849 @@
|
||||
/*
|
||||
* Copyright (C) 2014-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Init Sequence Library for use in:
|
||||
* Driver for the LPDDR4 compatible DRAM Control Subsystem (DCS) block
|
||||
*/
|
||||
|
||||
/*
|
||||
Summary of Steps from the Spec (Spreadsheet)
|
||||
|
||||
+ (Aa) Steps 0,1,2,3a [need to identify parameterization]
|
||||
+ (Ab) Step 3b [PMGR: set Freq to 50MHz & delay-wait]
|
||||
+ (Ac) Steps 3c,4,5 [need to identify parameterization]
|
||||
+ (B) Step 6 [Change Clk Speed]
|
||||
+ (C) Step 7 [include delay-wait from early Step 8]
|
||||
+ (D) Step 8a [Cal: CA 800MHz Vmin]
|
||||
+ (E) Step 8b [Write Regs]
|
||||
+ (F) Step 8c [Cal: CA 800MHz Vmin] (...again? should it be CS?)
|
||||
+ (G) Step 8d [Write Regs]
|
||||
+ (H) Step 9 [Write Regs]
|
||||
+ (I) Step 10 [Cal: WrLvl, RdDq, WrDq 800MHz Vmin]
|
||||
+ (J) Step 11 [Write Regs]
|
||||
+ (K) Step 12 [Cal: CA 1200MHz Vnom]
|
||||
+ (L) Step 13 [Write Regs]
|
||||
+ (M) Step 14 [Cal: WrLvl, RdDq, WrDq 1200MHz Vmin]
|
||||
+ (N) Steps 15,16,17,18,19,20 [need to identify parameterization]
|
||||
|
||||
Between these steps there is possibly a need/desire for:
|
||||
- Frequency Changes (PMGR)
|
||||
- PMU save/restore
|
||||
- debug messages
|
||||
- register dumps (DV, SiVal)
|
||||
- anything else!
|
||||
|
||||
CONFIG Table:
|
||||
Compile-Time Known:
|
||||
Type of Execution Environment CoreOS, DV, SiVal
|
||||
Type of Target SoC, FPGA, Palladium
|
||||
ChipID 0x8000, 0x8001, etc.
|
||||
Revision A0, B0, B1, etc.
|
||||
Num DCS 4, 8, etc. (Derived...!)
|
||||
Variant Flags Work-arounds, RADAR Ref., et al.
|
||||
|
||||
(Config Info know at Compile time can be subject to #if)
|
||||
|
||||
Run-Time Known:
|
||||
Type of Init ColdBoot, AOP_DDR, AOP_AWAKE
|
||||
Debug Flags Low-Level, Milestone, et al.
|
||||
|
||||
RegValue Table
|
||||
Much like today's: various values for various registers
|
||||
Sensitive to ChipID (also Target type?)
|
||||
(Internal static alloc (Complete Table Fill-in within Init function):
|
||||
Fill in Values (per ChipID/Rev & Target-type)
|
||||
return pointer to caller
|
||||
(Allows customization by caller before use)
|
||||
|
||||
TODO:
|
||||
- Convert to using SPDS for register names, et al
|
||||
|
||||
*/
|
||||
|
||||
//================================================================================
|
||||
// API Definitions
|
||||
#include <drivers/dcs/dcs_init_lib.h>
|
||||
extern dcs_config_t dcs_cfg;
|
||||
extern dcs_config_params_t dcs_params;
|
||||
|
||||
#if izIBOOT
|
||||
extern int debug_level_dcs;
|
||||
#endif
|
||||
|
||||
void dcs_enable_autorefresh(void)
|
||||
{
|
||||
uint32_t arefen_freq0 = 0x1111013f;
|
||||
uint32_t arefen_freq1 = 0x11110000;
|
||||
uint32_t arefen_freq2 = 0x11000000;
|
||||
uint32_t arefen_freq3 = 0x11100000;
|
||||
|
||||
if(dcs_cfg.chipRev < CHIP_REVISION_C0) {
|
||||
arefen_freq0 = 0x1011013f;
|
||||
arefen_freq1 = 0x10110000;
|
||||
arefen_freq2 = 0x10000000;
|
||||
arefen_freq3 = 0x10100000;
|
||||
}
|
||||
|
||||
// Configure auto-refresh. Freq0 has the auto-refresh enable, so do it last.
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(3), arefen_freq3);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(2), arefen_freq2);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(1), arefen_freq1);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(0), arefen_freq0);
|
||||
}
|
||||
|
||||
|
||||
|
||||
//================================================================================
|
||||
// Implementing the Various Steps of the DCS Init, per Specification
|
||||
// Based on AMC Init Spec (Spreadsheet)
|
||||
// - Supporting Maui: Spec (v??)
|
||||
//================================================================================
|
||||
// Step 0: AMC Prolog
|
||||
//================================================================================
|
||||
void dcs_init_Prolog(void)
|
||||
{
|
||||
// NOTE: between the Compiler and the Optimization, this should vanish for non-FPGA builds
|
||||
if (izFPGA && izColdBoot) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 1);
|
||||
delay_for_us(200);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 0);
|
||||
delay_for_us(200);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 1);
|
||||
delay_for_us(200);
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 1: AMC Initial Configuration
|
||||
//================================================================================
|
||||
void dcs_init_AMC_Initial_Config(void)
|
||||
{
|
||||
uint32_t i,n;
|
||||
|
||||
// rdar://problem/19137387: this applies to Maui A1 and B0, as well as other SoCs before Cayman
|
||||
|
||||
dcs_reg_write(rAMCC_MCCCHNLDEC_ADDR, dcs_params.chnldec);
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_CHARGEPUMP, 0x00000068);
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_VCO, dcs_params.spllctrl_vco_1);
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_VCO, dcs_params.spllctrl_vco_2);
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_LDO, 0x00000004);
|
||||
|
||||
// This register write to be skipped for Maui A0/A1, but written to for B0 & later, and all other SoCs
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0))
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_SPLLPWRDNCFG, 0x00000011);
|
||||
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
for (n = 0; n < dcs_params.num_freqchngctl_regs; n++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL_FREQ(n, i), dcs_params.freq[i].freqchngctl[n]);
|
||||
|
||||
// This register write to be skipped for Maui A0/A1, but written to for B0 & later, and all other SoCs
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0))
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGTIM_FREQ(i), dcs_params.freq[i].freqchngtim);
|
||||
}
|
||||
|
||||
if (dcs_cfg.chipRev < CHIP_REVISION_C0)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_RWCFG, dcs_params.rwcfg);
|
||||
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTCTRL(i), dcs_params.dllupdtctrl);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LAT_FREQ(0), dcs_params.freq[0].lat);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LAT_FREQ(1), dcs_params.freq[1].lat);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PHYRDWRTIM_FREQ(i), dcs_params.freq[i].phyrdwrtim);
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_CASPCH_FREQ(i), dcs_params.freq[i].caspch);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ACT_FREQ(i), dcs_params.freq[i].act);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_FREQ(i), dcs_params.freq[i].autoref);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_SELFREF_FREQ(i), dcs_params.freq[i].selfref);
|
||||
|
||||
if (i == 0) dcs_reg_write_all_chan(rDCS_MCU_MODEREG, dcs_params.modereg);
|
||||
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_PARAMS, dcs_params.autoref_params);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PDN, dcs_params.pdn);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_DERATE_FREQ(0), dcs_params.freq[0].derate);
|
||||
|
||||
// These register writes to be skipped for Maui A0/A1, but written to for B0 & later, and all other SoCs
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0))
|
||||
for(i = 1; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_DERATE_FREQ(i), dcs_params.freq[i].derate);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LAT_FREQ(i), dcs_params.freq[i].lat2);
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_TAT_FREQ(i), dcs_params.freq[i].tat);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_RNKCFG, dcs_params.rnkcfg);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MIFQMAXCTRL_FREQ(0), dcs_params.freq[0].mifqmaxctrl);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MIFQMAXCTRL_FREQ(3), dcs_params.freq[3].mifqmaxctrl);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PWRMNGTEN, 0);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, 0x00002000);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCTRL, 0x00000002);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MCPHYUPDTPARAM, 0x15030000);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 2: AMP Initial Configuration
|
||||
//================================================================================
|
||||
void dcs_init_AMP_Initial_Config(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPEN(i), 0x00000001);
|
||||
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_NONDQDSPD_F(i), dcs_params.freq[i].nondqdspd);
|
||||
|
||||
for(i = 1; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_NONDQDS_F(i), dcs_params.freq[i].nondqds);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CACKCSWKDS, dcs_params.cackcswkds);
|
||||
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_CA, i), dcs_params.freq[i].cavref);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_ODTENABLE_F(0), dcs_params.freq[0].odt_enable);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_ODTENABLE_F(1), dcs_params.freq[1].odt_enable);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_ODTENABLE_F(3), dcs_params.freq[3].odt_enable);
|
||||
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
// These register writes to be skipped for Maui A0/A1
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQDS_F(AMP_DQ0,i), dcs_params.freq[i].dqds);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQDS_F(AMP_DQ1,i), dcs_params.freq[i].dqds);
|
||||
}
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQDQSDS_F(AMP_DQ0,i), dcs_params.freq[i].dqdqsds);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQDQSDS_F(AMP_DQ1,i), dcs_params.freq[i].dqdqsds);
|
||||
}
|
||||
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ0, i), dcs_params.freq[i].dqvref);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ1, i), dcs_params.freq[i].dqvref);
|
||||
}
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSPDRES(AMP_DQ0), dcs_params.dqspdres);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSPDRES(AMP_DQ1), dcs_params.dqspdres);
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_CNTL(AMP_CA), dcs_params.casdllupdatectrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_CNTL(AMP_DQ0), dcs_params.dqsdllupdatectrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_CNTL(AMP_DQ1), dcs_params.dqsdllupdatectrl);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DIFFMODE_FREQ(AMP_DQ0, 3), 0x1);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DIFFMODE_FREQ(AMP_DQ1, 3), 0x1);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step2);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step2);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step2 & 0x7, 0x0);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step2 & 0x7, 0x0);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ0), dcs_params.wrdqdqssdllctrl_step2);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ1), dcs_params.wrdqdqssdllctrl_step2);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ0), dcs_params.wrdqdqssdllctrl_step2 & 0x7, 0x0);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ1), dcs_params.wrdqdqssdllctrl_step2 & 0x7, 0x0);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, dcs_params.cawrlvlsdllcode);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, dcs_params.cawrlvlsdllcode & 0x300, 0x000);
|
||||
|
||||
if (!izFPGA)
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLLOCKTIM(i), dcs_params.dlllocktim);
|
||||
|
||||
if(dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSPDENALWYSON(AMP_DQ0), 0x00000001);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSPDENALWYSON(AMP_DQ1), 0x00000001);
|
||||
}
|
||||
|
||||
if((dcs_params.supported_freqs & DCS_FREQ(1)) != 0)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DFICALTIMING, dcs_params.dficaltiming);
|
||||
|
||||
|
||||
// These register writes to be skipped for Maui A0/A1
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
for(i = 1; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMPCA_DFICALTIMING_F(i), dcs_params.freq[i].cadficaltiming);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ0, i), dcs_params.freq[i].dqdficaltiming);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ1, i), dcs_params.freq[i].dqdficaltiming);
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MDLLCODE_CAP_CNTL(AMP_DQ0), 0x00000002);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MDLLCODE_CAP_CNTL(AMP_DQ1), 0x00000002);
|
||||
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALTIMING_F(0), dcs_params.rdwrdqcaltiming_f0);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALSEGLEN_F(0), dcs_params.rdwrdqcalseglen_f0);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALTIMING_F(1), dcs_params.rdwrdqcaltiming_f1);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALSEGLEN_F(1), dcs_params.rdwrdqcalseglen_f1);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDWRDQCALTIMINGCTRL(1), dcs_params.rdwrdqcaltimingctrl1);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDWRDQCALTIMINGCTRL(2), dcs_params.rdwrdqcaltimingctrl2);
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDDQCALPATPRBS4I, dcs_params.rddqcalpatprbs4i);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATPRBS4I, dcs_params.wrdqcalpatprbs4i);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQCALWINDOW_F(0), dcs_params.freq[0].rddqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQCALWINDOW_F(0), dcs_params.freq[0].wrdqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQCALWINDOW_F(1), dcs_params.freq[1].rddqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQCALWINDOW_F(1), dcs_params.freq[1].wrdqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MAXWRDQS_SDLL_MULFACTOR, dcs_params.maxwrdqssdllmulfactor);
|
||||
|
||||
// These register writes to be skipped for Maui A0/A1
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_RDDQSMULFACTOR(AMP_DQ0), 0x20181000);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_RDDQSMULFACTOR(AMP_DQ1), 0x20181000);
|
||||
}
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CAOUTDLLSCL_FREQ(i), dcs_params.freq[i].caoutdllscl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSINDLLSCL_FREQ(AMP_DQ0, i), dcs_params.freq[i].dqsindllscl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSINDLLSCL_FREQ(AMP_DQ1, i), dcs_params.freq[i].dqsindllscl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDCAPCFG_FREQ(AMP_DQ0, i), dcs_params.freq[i].rdcapcfg);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDCAPCFG_FREQ(AMP_DQ1, i), dcs_params.freq[i].rdcapcfg);
|
||||
}
|
||||
|
||||
if (!izFPGA) {
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTCTRL(i), dcs_params.dllupdtctrl1);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_IMPAUTOCAL, 0x00010000);
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTINTVL(AMP_CA), dcs_params.dllupdtintvl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTINTVL(AMP_DQ0), dcs_params.dllupdtintvl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTINTVL(AMP_DQ1), dcs_params.dllupdtintvl);
|
||||
|
||||
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLEN(i), 0x00000100);
|
||||
|
||||
if(!izFPGA)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_AMP_IMPCALCMD, 0x00000000);
|
||||
}
|
||||
|
||||
|
||||
// Workaround for Maui B0
|
||||
if((dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0))
|
||||
dcs_reg_write_all_chan(rDCS_AMP_BISTRXMODE, 0x0000001c);
|
||||
// AMPH configuration
|
||||
|
||||
if(dcs_cfg.chipRev >= CHIP_REVISION_B0)
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_SLC_REG(0), 0x0000003f);
|
||||
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPINIT(i), 0x00000001);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 3: Self-Refresh Exit
|
||||
//================================================================================
|
||||
void dcs_init_Self_Refresh_Exit_a(void)
|
||||
{
|
||||
// Wait 5 us after Impedence Calibration to avoid McPhyPending
|
||||
// preventing the SRFSM from exiting SR.
|
||||
dcs_spin(5, "after Imp. Cal.");
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFPARAM, dcs_params.arefparam);
|
||||
|
||||
for(int i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_FREQ(i), dcs_params.freq[i].autoref2);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_PARAMS, dcs_params.autoref_params2);
|
||||
|
||||
if(izFPGA)
|
||||
if(dcs_cfg.chipRev < CHIP_REVISION_B0)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_PARAMS, dcs_params.autoref_params);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LONGSR, dcs_params.longsr);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MCPHYUPDTPARAM, 0x15030007);
|
||||
|
||||
}
|
||||
|
||||
//========================================
|
||||
// Caller Code should:
|
||||
// - Change Frequency to 50MHz
|
||||
//========================================
|
||||
|
||||
void dcs_init_Self_Refresh_Exit_b(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCTRL, 0x00000003);
|
||||
|
||||
if (!izFPGA) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_IMPCALCMD, 0x00000001);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_IMPCALCMD, 0x01, 0x00);
|
||||
}
|
||||
|
||||
if (izResume)
|
||||
dcs_enable_autorefresh();
|
||||
|
||||
dcs_spin(2200, "After Enable Auto-Refresh");
|
||||
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, dcs_params.freqchngctl_step3);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_FREQCHNGCTL, 0x10000, 0x00000);
|
||||
dcs_spin(2, "After SoC Update");
|
||||
}
|
||||
|
||||
// Resume-Boot and Cold-Boot use different Exit commands for Self-Refresh
|
||||
// Issue self-refresh exit cmd for resume boot with MPC
|
||||
int n = (izColdBoot)? 0x00000000:0x00004000;
|
||||
// Issue self-refresh exit cmd for resume boot with MPC
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MRINITCMD_0, n);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MRINITCMD_0, n | 0x1);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_MRINITCMD_0, 0x01, 0x00);
|
||||
|
||||
dcs_spin(2, NULL);
|
||||
|
||||
dcs_reg_write(rGLBTIMER_CHEN, (1 << dcs_cfg.num_dcs) - 1);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 4: DRAM Reset, ZQ Calibration & Configuration (cold boot only)
|
||||
//================================================================================
|
||||
void dcs_init_ZQ_Cal_Cfg(void)
|
||||
{
|
||||
// ZQ calibration START MPC cmd
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0, 0x4f);
|
||||
// wait 1us for tZQCAL
|
||||
dcs_spin(1, "tZQCAL");
|
||||
|
||||
// ZQ calibration LATCH MPC cmd
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0, 0x51);
|
||||
// wait 10ns for tZQLAT
|
||||
dcs_spin(1, "tZQLAT");
|
||||
|
||||
if (izColdBoot) {
|
||||
// MR2 register (read/write latency)
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x2, 0x0);
|
||||
// MR1 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x1, 0x8e);
|
||||
// MR3 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x3, dcs_params.mr3cmd);
|
||||
// MR22 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x16, 0x0);
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xb, 0x0);
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xd, dcs_params.mr13cmd);
|
||||
// MR12 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xc, 0x59);
|
||||
// MR14 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xe, 0x59);
|
||||
|
||||
// MR23 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x17, 0x80);
|
||||
|
||||
uint32_t patinvertmask = (DCS_REG_READ_CH(0, rDCS_AMP_HWRDDQCALPATPRBS4I) >> 16) & 0xffff;
|
||||
uint32_t prbs = DCS_REG_READ_CH(0, rDCS_AMP_HWWRDQCALPATPRBS4I);
|
||||
|
||||
// MR15 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xf, patinvertmask & 0xff);
|
||||
// MR20 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x14, (patinvertmask >> 8) & 0xff);
|
||||
// MR32 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x20, prbs & 0xff);
|
||||
// MR40 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x28, (prbs >> 8) & 0xff);
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 5a: AddrConfig Configuration
|
||||
//================================================================================
|
||||
void dcs_init_AddrCfg_Cfg(void)
|
||||
{
|
||||
dcs_reg_write(rAMCC_ADDRCFG_ADDR, dcs_params.addrcfg);
|
||||
}
|
||||
|
||||
//========================================
|
||||
// Caller Code should:
|
||||
// - Use MR Cmds to Query the Device
|
||||
//========================================
|
||||
|
||||
//================================================================================
|
||||
// Step 5b: Total Mem Size Config
|
||||
//================================================================================
|
||||
void dcs_init_TotalSize_Cfg(uint32_t total_size_Mbytes)
|
||||
{
|
||||
dbgprintf(DCS_DBG_ASSESS_CONFIG, "Memory_size: %llu bytes\n",
|
||||
(((uint64_t)total_size_Mbytes) * MEG * NUM_AMCCS));
|
||||
// (Units of 128 MBs in the register)
|
||||
dcs_reg_write(rAMCC_DRAMACCCTRL_ADDR, ((total_size_Mbytes / NUM_AMCCS) / DCS_NUM_MEG_IN_DRAM_BLK) - 1);
|
||||
dcs_reg_write(rAMCC_MCCCHNLDEC_ADDR, dcs_params.chnldec);
|
||||
|
||||
dbgprintf(DCS_DBG_ASSESS_CONFIG, "rAMCC_DRAMACCCTRL: 0x%08x\n", rAMCC_DRAMACCCTRL);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 6: Switch from boot-clock speed to normal operation speed
|
||||
//================================================================================
|
||||
void dcs_init_Reenable_AMC_Scheduler(void)
|
||||
{
|
||||
// Wait 5 us before freq change to make sure all refreshes have been flushed
|
||||
dcs_spin(5, "After Refresh");
|
||||
|
||||
// Enable (again) the AMC Scheduler
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCTRL, 0x00000003);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 7: Setup registers for CA calibration for bucket 1
|
||||
//================================================================================
|
||||
void dcs_init_CA_Cal_Setup_Freq1(void)
|
||||
{
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xd, dcs_params.mr13cmd_step7);
|
||||
|
||||
if (izColdBoot) {
|
||||
if (izFPGA) {
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xb, 0x00);
|
||||
} else {
|
||||
// MR2 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x2, 0x52);
|
||||
// MR1 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x1, 0xae);
|
||||
// MR3 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x3, dcs_params.mr3cmd_step7);
|
||||
// MR22 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x16, dcs_params.mr22cmd);
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xb, dcs_params.mr11cmd);
|
||||
// MR12 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xc, 0x11);
|
||||
// MR14 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xe, 0x11);
|
||||
}
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x00000200);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x0200, 0x0000);
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 8: AMP Dynamic CA Vref Timing Calibration at Vmin 800MHz
|
||||
//================================================================================
|
||||
void dcs_init_CA_Cal_Freq1(void)
|
||||
{
|
||||
// Nothing to be done at this step for cold boot
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 9: Setup registers for DQ calibration for bucket 1
|
||||
//================================================================================
|
||||
void dcs_init_DQ_Cal_Setup_Freq1_a(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (izColdBoot) {
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xd, dcs_params.mr13cmd_step9);
|
||||
}
|
||||
|
||||
dcs_spin(1, NULL);
|
||||
|
||||
if(izResume) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PWRMNGTEN, 0x00000002);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, 0x01008888);
|
||||
|
||||
for(i = AMP_DQ0 ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(i), 0xFF00000C);
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_DEFER_EN(i), 0x00000000);
|
||||
for(i = AMP_DQ0; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MDLLOVRRD(i), 0x00000000);
|
||||
}
|
||||
}
|
||||
|
||||
// Caller code should change frequency to bucket 1
|
||||
void dcs_init_DQ_Cal_Setup_Freq1_b(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, dcs_params.freqchngctl_step9);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_FREQCHNGCTL, 0x10000, 0x00000);
|
||||
|
||||
// Wait 2us for the soc update to finish
|
||||
dcs_spin(2, NULL);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 10: PHY write DQ calibration
|
||||
//================================================================================
|
||||
void dcs_init_wrdq_skew(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSDQ_SKEWCTL(AMP_DQ0), 0x06000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSDQ_SKEWCTL(AMP_DQ1), 0x06000000);
|
||||
}
|
||||
|
||||
void dcs_init_post_wrlvl(void)
|
||||
{
|
||||
if(dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ0), 0x00000010);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ1), 0x00000010);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 11: Setup registers for CA calibration for bucket 0
|
||||
//================================================================================
|
||||
void dcs_init_CA_Cal_Setup_Freq0(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
|
||||
if(dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ0), 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ1), 0x00000000);
|
||||
}
|
||||
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, dcs_params.mr13cmd_step11);
|
||||
if (!izFPGA) {
|
||||
// MR2 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x02, dcs_params.mr2cmd_step11);
|
||||
// MR1 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x01, dcs_params.mr1cmd_step11);
|
||||
// MR3 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x03, dcs_params.mr3cmd_step11);
|
||||
}
|
||||
|
||||
// MR22 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x16, dcs_params.mr22cmd_step11);
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0b, (izFPGA) ? 0x00 : dcs_params.mr11cmd_step11);
|
||||
// MR12 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0c, dcs_params.mr12cmd_step11);
|
||||
// MR14 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0e, dcs_params.mr14cmd_step11);
|
||||
|
||||
if((dcs_params.supported_freqs & DCS_FREQ(1)) == 0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x00000200);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x200, 0x000);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 12: AMP Dynamic CA Timing Calibration
|
||||
//================================================================================
|
||||
|
||||
//================================================================================
|
||||
// Step 13: Setup registers for DQ calibration for bucket 0
|
||||
//================================================================================
|
||||
void dcs_init_DQ_Cal_Setup_Freq0_a(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, dcs_params.mr13cmd_step13);
|
||||
|
||||
// Wait 1 us
|
||||
dcs_spin(1, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
void dcs_init_DQ_Cal_Setup_Freq0_b(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, 0x00010000);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_FREQCHNGCTL, 0x10000, 0x00000);
|
||||
|
||||
// Wait 2us for the soc update to finish
|
||||
dcs_spin(2, NULL);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 14: AMP Dynamic DQ Calibration
|
||||
//================================================================================
|
||||
|
||||
//================================================================================
|
||||
// Step 15: Setup Registers for Boot
|
||||
//================================================================================
|
||||
void dcs_init_Reg_for_Boot(void)
|
||||
{
|
||||
|
||||
if((dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0))
|
||||
dcs_reg_write_all_chan(rDCS_AMP_BISTRXMODE, 0x00000000);
|
||||
|
||||
if(dcs_cfg.chipRev >= CHIP_REVISION_C0)
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_SLC_REG(0), 0x0000013f);
|
||||
|
||||
#ifndef DCS_RUN_AT_50MHZ
|
||||
if (izColdBoot) {
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, dcs_params.mr13cmd_step15);
|
||||
}
|
||||
#endif
|
||||
|
||||
if(izFPGA && !(dcs_params.supported_freqs & DCS_FREQ(1)))
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, 0x50);
|
||||
|
||||
// Wait 1 us
|
||||
dcs_spin(1, NULL);
|
||||
|
||||
if (izColdBoot) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, dcs_params.freqchngctl_step15);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ0), 0xff000008);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ1), 0xff000008);
|
||||
|
||||
#if !DCS_DO_CALIBRATION
|
||||
// skip these for all silicon targets, where calibration is performed, also skip for any Maui A1 target
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step15);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step15);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step15 & 0x7, 0x0);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step15 & 0x7, 0x0);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDWRDQCALFULLSCANEN, 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDWRDQCALFULLSCANEN, 0x00000003);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 16: Enable Other Features
|
||||
//================================================================================
|
||||
void dcs_init_MoreFeatures(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFPARAM, dcs_params.arefparam);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc2);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_QBREN, dcs_params.qbren_step16);
|
||||
|
||||
if (izColdBoot)
|
||||
dcs_enable_autorefresh();
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 17: Enable Fast Critical Word Forwarding Feature
|
||||
//================================================================================
|
||||
void dcs_init_Fast_Critical_Word_Forwarding(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_MCU_QBRPARAM, dcs_params.qbrparam);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_QBREN, dcs_params.qbren);
|
||||
|
||||
dcs_reg_poll(rAMCC_MCCPWRONWAYCNTSTATUS_ADDR, 0x7fff7fff, 0x42104210);
|
||||
dcs_reg_write(rAMCC_MCC0QPROPCTRL_ADDR, 0x300011a2);
|
||||
dcs_reg_write(rAMCC_MCC1QPROPCTRL_ADDR, 0x300011a2);
|
||||
dcs_reg_write(rAMCC_MCCGEN_ADDR, dcs_params.mccgen);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 18: Enable Power- and Clock-Gating Features; Config MCC and Global Timers
|
||||
//================================================================================
|
||||
void dcs_init_Gating_Global_Timers(void)
|
||||
{
|
||||
const struct dcs_memory_device_info *dev_info = dcs_get_memory_device_info();
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPCLK(AMP_CA), dcs_params.caampclk);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPCLK(AMP_DQ0), dcs_params.dqampclk);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPCLK(AMP_DQ1), dcs_params.dqampclk);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PWRMNGTEN, dcs_params.pwrmngten);
|
||||
|
||||
if(!izFPGA) {
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PWRMNGTPARAM_FREQ(0), 0x01800000);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PSQWQCTL1, 0x01640120);
|
||||
}
|
||||
|
||||
// Global Timer Setup
|
||||
|
||||
if(dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev < CHIP_REVISION_B0) {
|
||||
dcs_reg_write(rGLBTIMER_PMGRWAKEUPCFG, 0x0000ff);
|
||||
dcs_reg_write(rGLBTIMER_MDLLTIMER, 0x000bb8); // 3000
|
||||
dcs_reg_write(rGLBTIMER_MDLLVOLTRAMPTIMER, 0x00004b); // 75
|
||||
dcs_reg_write(rGLBTIMER_CTRLUPDMASKTIMER, 0x00000f); // 15
|
||||
dcs_reg_write(rGLBTIMER_RDCALTIMER, 0x2dc6c0); // 3000000
|
||||
dcs_reg_write(rGLBTIMER_WRCALTIMER, 0x2dc6c0); // 3000000
|
||||
dcs_reg_write(rGLBTIMER_ZQCTIMER, 0x3d0900); // 4000000
|
||||
dcs_reg_write(rGLBTIMER_PERCAL_FREQCHNGTIMER, 0x000001); // 300000
|
||||
dcs_reg_write(rGLBTIMER_VOLTRAMPTIMER, 0x000001); // 300000
|
||||
dcs_reg_write(rGLBTIMER_IMPCALTIMER, 0x002ee0); // 12000
|
||||
} else {
|
||||
dcs_reg_write(rGLBTIMER_PMGRWAKEUPCFG, 0x0000ff);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQ2ALLBANKDLY(0), 0x01500150);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQ2ALLBANKDLY(1), 0x01500150);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQCHNG2FREQCHNGDLY(0), 0x02a002a0);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQCHNG2FREQCHNGDLY(1), 0x02a002a0);
|
||||
|
||||
dcs_reg_write(rGLBTIMER_CAL2PREFREQCHNGDLY(0), 0x00900090);
|
||||
dcs_reg_write(rGLBTIMER_CAL2PREFREQCHNGDLY(1), 0x00900090);
|
||||
dcs_reg_write(rGLBTIMER_FREQCHNG2PSTCALDLY(0), 0x01200120);
|
||||
dcs_reg_write(rGLBTIMER_FREQCHNG2PSTCALDLY(1), 0x01200120);
|
||||
|
||||
dcs_reg_write(rGLBTIMER_MDLLTIMER, 0x000bb8); // 3000
|
||||
dcs_reg_write(rGLBTIMER_MDLLVOLTRAMPTIMER, 0x00004b); // 75
|
||||
dcs_reg_write(rGLBTIMER_CTRLUPDMASKTIMER, 0x00000f); // 15
|
||||
// skip IDTTIMER setup per spec
|
||||
//dcs_reg_write(rGLBTIMER_IDTTIMER, 0x007530); // 30000
|
||||
dcs_reg_write(rGLBTIMER_RDCALTIMER, 0x2dc6c0); // 3000000
|
||||
dcs_reg_write(rGLBTIMER_WRCALTIMER, 0x2dc6c0); // 3000000
|
||||
|
||||
// <rdar://problem/23355941> Maui/Malta: Samsung DRAM workaround: disable hw zqcal
|
||||
if(! ((dev_info->vendor_id == JEDEC_LPDDR4_MANUF_ID_SAMSUNG) && (dev_info->rev_id == 5) && (dev_info->rev_id2 <= 1)) )
|
||||
dcs_reg_write(rGLBTIMER_ZQCTIMER, 0x3d0900); // 4000000
|
||||
|
||||
dcs_reg_write(rGLBTIMER_PERCAL_FREQCHNGTIMER, 0x0493e0); //
|
||||
dcs_reg_write(rGLBTIMER_VOLTRAMPTIMER, 0x0493e0); //
|
||||
dcs_reg_write(rGLBTIMER_IMPCALTIMER, 0x002ee0); // 12000
|
||||
|
||||
dcs_reg_write(rGLBTIMER_VOLTRAMP2ALLBANKDLY(0), 0x00d800d8);
|
||||
dcs_reg_write(rGLBTIMER_VOLTRAMP2ALLBANKDLY(1), 0x00d800d8);
|
||||
dcs_reg_write(rGLBTIMER_ALLBANK2PMGRACKDLY(0), 0x00900090);
|
||||
dcs_reg_write(rGLBTIMER_ALLBANK2PMGRACKDLY(1), 0x00900090);
|
||||
}
|
||||
|
||||
// Dynamic Clk & Power Gating
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCLKPWRGATE, 0x050a0000);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 19: ODTS read & set interval for periodic MR4 on-die Temp sensor reading
|
||||
//================================================================================
|
||||
void dcs_init_ODTS(void)
|
||||
{
|
||||
uint8_t temp[16*8]; // Far more Channels/Ranks than we are likely ever to have/need
|
||||
// INSTEAD OF: uint8_t temp[dcs_cfg.num_dcs * dcs_cfg.num_rank];
|
||||
|
||||
// MR4 read to bring memory out of self-refresh
|
||||
dcs_mrcmd(MR_READ, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x4, (uintptr_t)temp);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc3);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
@@ -0,0 +1,963 @@
|
||||
/*
|
||||
* Copyright (C) 2014-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Init Sequence Library for use in:
|
||||
* Driver for the LPDDR4 compatible DRAM Control Subsystem (DCS) block
|
||||
*/
|
||||
|
||||
/*
|
||||
Summary of Steps from the Spec (Spreadsheet)
|
||||
|
||||
+ (Aa) Steps 0,1,2,3a [need to identify parameterization]
|
||||
+ (Ab) Step 3b [PMGR: set Freq to 50MHz & delay-wait]
|
||||
+ (Ac) Steps 3c,4,5 [need to identify parameterization]
|
||||
+ (B) Step 6 [Change Clk Speed]
|
||||
+ (C) Step 7 [include delay-wait from early Step 8]
|
||||
+ (D) Step 8a [Cal: CA 800MHz Vmin]
|
||||
+ (E) Step 8b [Write Regs]
|
||||
+ (F) Step 8c [Cal: CA 800MHz Vmin] (...again? should it be CS?)
|
||||
+ (G) Step 8d [Write Regs]
|
||||
+ (H) Step 9 [Write Regs]
|
||||
+ (I) Step 10 [Cal: WrLvl, RdDq, WrDq 800MHz Vmin]
|
||||
+ (J) Step 11 [Write Regs]
|
||||
+ (K) Step 12 [Cal: CA 1200MHz Vnom]
|
||||
+ (L) Step 13 [Write Regs]
|
||||
+ (M) Step 14 [Cal: WrLvl, RdDq, WrDq 1200MHz Vmin]
|
||||
+ (N) Steps 15,16,17,18,19,20 [need to identify parameterization]
|
||||
|
||||
Between these steps there is possibly a need/desire for:
|
||||
- Frequency Changes (PMGR)
|
||||
- PMU save/restore
|
||||
- debug messages
|
||||
- register dumps (DV, SiVal)
|
||||
- anything else!
|
||||
|
||||
CONFIG Table:
|
||||
Compile-Time Known:
|
||||
Type of Execution Environment CoreOS, DV, SiVal
|
||||
Type of Target SoC, FPGA, Palladium
|
||||
ChipID 0x8000, 0x8001, etc.
|
||||
Revision A0, B0, B1, etc.
|
||||
Num DCS 4, 8, etc. (Derived...!)
|
||||
Variant Flags Work-arounds, RADAR Ref., et al.
|
||||
|
||||
(Config Info know at Compile time can be subject to #if)
|
||||
|
||||
Run-Time Known:
|
||||
Type of Init ColdBoot, AOP_DDR, AOP_AWAKE
|
||||
Debug Flags Low-Level, Milestone, et al.
|
||||
|
||||
RegValue Table
|
||||
Much like today's: various values for various registers
|
||||
Sensitive to ChipID (also Target type?)
|
||||
(Internal static alloc (Complete Table Fill-in within Init function):
|
||||
Fill in Values (per ChipID/Rev & Target-type)
|
||||
return pointer to caller
|
||||
(Allows customization by caller before use)
|
||||
|
||||
TODO:
|
||||
- Convert to using SPDS for register names, et al
|
||||
|
||||
*/
|
||||
|
||||
//================================================================================
|
||||
// API Definitions
|
||||
#include <drivers/dcs/dcs_init_lib.h>
|
||||
|
||||
extern dcs_config_t dcs_cfg;
|
||||
extern dcs_config_params_t dcs_params;
|
||||
|
||||
#if izIBOOT
|
||||
extern int debug_level_dcs;
|
||||
#endif
|
||||
|
||||
// <rdar://problem/23244578>: To track throughout the sequence whether we should apply the Samsung DRAM workarounds
|
||||
static bool apply_samsung_workaround = false;
|
||||
|
||||
void dcs_enable_autorefresh(void)
|
||||
{
|
||||
uint32_t arefen_freq0 = 0x1011013f;
|
||||
uint32_t arefen_freq1 = 0x10010000;
|
||||
|
||||
// Configure auto-refresh. Freq0 has the auto-refresh enable, so do it last.
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(3), 0x10100000);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(2), 0x10000000);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(1), arefen_freq1);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(0), arefen_freq0);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Implementing the Various Steps of the DCS Init, per Specification
|
||||
// Based on AMC Init Spec (Spreadsheet)
|
||||
// - Supporting Maui: Spec (v??)
|
||||
//================================================================================
|
||||
// Step 0: AMC Prolog
|
||||
//================================================================================
|
||||
void dcs_init_Prolog(void)
|
||||
{
|
||||
// NOTE: between the Compiler and the Optimization, this should vanish for non-FPGA builds
|
||||
if (izFPGA && izColdBoot) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 1);
|
||||
delay_for_us(200);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 0);
|
||||
delay_for_us(200);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 1);
|
||||
delay_for_us(200);
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 1: AMC Initial Configuration
|
||||
//================================================================================
|
||||
void dcs_init_AMC_Initial_Config(void)
|
||||
{
|
||||
uint32_t i,n;
|
||||
|
||||
// rdar://problem/19137387: this applies to Maui A1 and B0, as well as other SoCs before Cayman
|
||||
|
||||
dcs_reg_write(rAMCC_MCCCHNLDEC_ADDR, dcs_params.chnldec);
|
||||
#if NUM_AMCCS == 2
|
||||
dcs_reg_write(rAMCC1_MCCCHNLDEC_ADDR, dcs_params.chnldec);
|
||||
#endif
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_CHARGEPUMP, 0x00000068);
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_MODEREG, 0x1);
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_VCO, dcs_params.spllctrl_vco_1);
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_VCO, dcs_params.spllctrl_vco_2);
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_LDO, 0x00000004);
|
||||
|
||||
// This register write to be skipped for Maui A0/A1, but written to for B0 & later, and all other SoCs
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0))
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_SPLLPWRDNCFG, 0x00000011);
|
||||
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
for (n = 0; n < dcs_params.num_freqchngctl_regs; n++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL_FREQ(n, i), dcs_params.freq[i].freqchngctl[n]);
|
||||
|
||||
// This register write to be skipped for Maui A0/A1, but written to for B0 & later, and all other SoCs
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0))
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGTIM_FREQ(i), dcs_params.freq[i].freqchngtim);
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQCALVREFCODECONTROL, dcs_params.wrdqcalvrefcodecontrol);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQCALVREFCODECONTROL, dcs_params.rddqcalvrefcodecontrol);
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDDQCALVREFCONTROL, 0x01d0b060);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDDQCALVREFOFFSETCONTROL(1), 0x06040200);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDDQCALVREFOFFSETCONTROL(2), 0x00fafcfe);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALVREFCONTROL, 0x02200060);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALVREFOFFSETCONTROL(1), 0x06040200);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALVREFOFFSETCONTROL(2), 0x00fafcfe);
|
||||
dcs_reg_write(rGLBTIMER_PERVREFCALCFG, 0x00000003);
|
||||
dcs_reg_write(rGLBTIMER_VREFCNTRL, 0x00060006);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MODEREG, 0x120c90b8);
|
||||
|
||||
if (dcs_cfg.chipRev < CHIP_REVISION_B0)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_MCU_RWCFG, dcs_params.rwcfg);
|
||||
}
|
||||
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTCTRL(i), dcs_params.dllupdtctrl);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LAT_FREQ(0), dcs_params.freq[0].lat);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LAT_FREQ(1), dcs_params.freq[1].lat);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PHYRDWRTIM_FREQ(i), dcs_params.freq[i].phyrdwrtim);
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_CASPCH_FREQ(i), dcs_params.freq[i].caspch);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ACT_FREQ(i), dcs_params.freq[i].act);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_FREQ(i), dcs_params.freq[i].autoref);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_SELFREF_FREQ(i), dcs_params.freq[i].selfref);
|
||||
|
||||
if (i == 0) dcs_reg_write_all_chan(rDCS_MCU_MODEREG, dcs_params.modereg);
|
||||
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_PARAMS, dcs_params.autoref_params);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PDN, dcs_params.pdn);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_DERATE_FREQ(0), dcs_params.freq[0].derate);
|
||||
|
||||
// These register writes to be skipped for Maui A0/A1, but written to for B0 & later, and all other SoCs
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0))
|
||||
for(i = 1; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_DERATE_FREQ(i), dcs_params.freq[i].derate);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LAT_FREQ(i), dcs_params.freq[i].lat2);
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_TAT_FREQ(i), dcs_params.freq[i].tat);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_RNKCFG, dcs_params.rnkcfg);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MIFQMAXCTRL_FREQ(0), dcs_params.freq[0].mifqmaxctrl);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MIFQMAXCTRL_FREQ(3), dcs_params.freq[3].mifqmaxctrl);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PWRMNGTEN, 0);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, 0x00002000);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCTRL, 0x00000002);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MCPHYUPDTPARAM, 0x15030000);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 2: AMP Initial Configuration
|
||||
//================================================================================
|
||||
void dcs_init_AMP_Initial_Config(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (dcs_cfg.chipRev < CHIP_REVISION_B0)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DCC_BYPCK, 0x00003f3f);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DCC_BYPCS, 0x00003f3f);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DCC_BYPB0, 0x00003f3f);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DCC_BYPDQS0, 0x00003f3f);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DCC_BYPB1, 0x00003f3f);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DCC_BYPDQS1, 0x00003f3f);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DCC_BYPCA, 0x00003f3f);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DCC_BYPCK, 0x00013f3f);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DCC_BYPCS, 0x00013f3f);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DCC_BYPB0, 0x00013f3f);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DCC_BYPDQS0, 0x00013f3f);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DCC_BYPB1, 0x00013f3f);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DCC_BYPDQS1, 0x00013f3f);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DCC_BYPCA, 0x00013f3f);
|
||||
}
|
||||
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPEN(i), 0x00000001);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_CA, i), dcs_params.freq[i].cavref);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_ODTENABLE_F(0), dcs_params.freq[0].odt_enable);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_ODTENABLE_F(1), dcs_params.freq[1].odt_enable);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_ODTENABLE_F(3), dcs_params.freq[3].odt_enable);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ0, i), dcs_params.freq[i].dqvref);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ1, i), dcs_params.freq[i].dqvref);
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_CNTL(AMP_CA), dcs_params.casdllupdatectrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_CNTL(AMP_DQ0), dcs_params.dqsdllupdatectrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_CNTL(AMP_DQ1), dcs_params.dqsdllupdatectrl);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step2);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step2);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step2 & 0x7, 0x0);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step2 & 0x7, 0x0);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ0), dcs_params.wrdqdqssdllctrl_step2);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ1), dcs_params.wrdqdqssdllctrl_step2);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ0), dcs_params.wrdqdqssdllctrl_step2 & 0x7, 0x0);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ1), dcs_params.wrdqdqssdllctrl_step2 & 0x7, 0x0);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, dcs_params.cawrlvlsdllcode);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, dcs_params.cawrlvlsdllcode & 0x300, 0x000);
|
||||
|
||||
if (!izFPGA)
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLLOCKTIM(i), dcs_params.dlllocktim);
|
||||
|
||||
if(dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSPDENALWYSON(AMP_DQ0), 0x00000001);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSPDENALWYSON(AMP_DQ1), 0x00000001);
|
||||
}
|
||||
|
||||
if((dcs_params.supported_freqs & DCS_FREQ(1)) != 0)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DFICALTIMING, dcs_params.dficaltiming);
|
||||
|
||||
|
||||
if (dcs_cfg.chipRev < CHIP_REVISION_B0)
|
||||
{
|
||||
for(i = 1; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMPCA_DFICALTIMING_F(i), dcs_params.freq[i].cadficaltiming);
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ0, i), dcs_params.freq[i].dqdficaltiming);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ1, i), dcs_params.freq[i].dqdficaltiming);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_AMPCA_DFICALTIMING_F(1), 0x04000710);
|
||||
dcs_reg_write_all_chan(rDCS_AMPCA_DFICALTIMING_F(2), 0x04000710);
|
||||
dcs_reg_write_all_chan(rDCS_AMPCA_DFICALTIMING_F(3), 0x04000510);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ0, 0), 0x06020704);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ0, 1), 0x04020702);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ0, 2), 0x04020702);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ0, 3), 0x04020504);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ1, 0), 0x06020704);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ1, 1), 0x04020702);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ1, 2), 0x04020702);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ1, 3), 0x04020504);
|
||||
dcs_reg_write_all_chan(rDCS_AMPCA_DFICALTIMING_RDDQCAL2, 0x00000019);
|
||||
}
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MDLLCODE_CAP_CNTL(AMP_DQ0), 0x00000002);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MDLLCODE_CAP_CNTL(AMP_DQ1), 0x00000002);
|
||||
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALTIMING_F(0), dcs_params.rdwrdqcaltiming_f0);
|
||||
|
||||
if (dcs_cfg.chipRev < CHIP_REVISION_B0)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALSEGLEN_F(0), dcs_params.rdwrdqcalseglen_f0);
|
||||
else
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALSEGLEN_F(0), 0x00040008);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALTIMING_F(1), dcs_params.rdwrdqcaltiming_f1);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALSEGLEN_F(1), dcs_params.rdwrdqcalseglen_f1);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALTIMING_F(3), dcs_params.rdwrdqcaltiming_f3);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDWRDQCALTIMINGCTRL(1), dcs_params.rdwrdqcaltimingctrl1);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDWRDQCALTIMINGCTRL(2), dcs_params.rdwrdqcaltimingctrl2);
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDDQCALPATPRBS4I, dcs_params.rddqcalpatprbs4i);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATPRBS4I, dcs_params.wrdqcalpatprbs4i);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATPRBS7(0), 0x87654321);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATPRBS7(1), 0xcdedcba9);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATPRBS7(2), 0x456789ab);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATPRBS7(3), 0x5fa63123);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATINVERTMASK, 0x55550000);
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQCALWINDOW_F(0), dcs_params.freq[0].rddqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQCALWINDOW_F(0), dcs_params.freq[0].wrdqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQCALWINDOW_F(1), dcs_params.freq[1].rddqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQCALWINDOW_F(1), dcs_params.freq[1].wrdqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MAXRDDQS_SDLL_MULFACTOR, dcs_params.maxrddqssdllmulfactor);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MAXWRDQS_SDLL_MULFACTOR, dcs_params.maxwrdqssdllmulfactor);
|
||||
|
||||
// These register writes to be skipped for Maui A0/A1
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_RDDQSMULFACTOR(AMP_DQ0), 0x20181000);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_RDDQSMULFACTOR(AMP_DQ1), 0x20181000);
|
||||
}
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDCAPCFG_FREQ(AMP_DQ0, i), dcs_params.freq[i].rdcapcfg);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDCAPCFG_FREQ(AMP_DQ1, i), dcs_params.freq[i].rdcapcfg);
|
||||
}
|
||||
|
||||
if (!izFPGA) {
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTCTRL(i), dcs_params.dllupdtctrl1);
|
||||
}
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTINTVL(AMP_CA), dcs_params.dllupdtintvl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTINTVL(AMP_DQ0), dcs_params.dllupdtintvl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTINTVL(AMP_DQ1), dcs_params.dllupdtintvl);
|
||||
|
||||
for(i = AMP_DQ0 ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLEN(i), 0x00000100);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DCCCONTROL, dcs_params.dcccontrol);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DCCTIMER, 0x00000190);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALDYNHALFCLKDLYCTRL, 0x00000001);
|
||||
|
||||
|
||||
// AMPH configuration
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CB_WKPUPD, 0);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CB_DRIVESTR, dcs_params.cbdrivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CB_IOCTL, dcs_params.cbioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CK_WKPUPD, 0);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CK_ZDETBIASEN, 0);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CK_DRIVESTR, dcs_params.ckdrivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CK_IOCTL, dcs_params.ckioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_DRIVESTR, dcs_params.b0drivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_WKPUPD, 0);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_IOCTL, dcs_params.b0ioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_ODT, dcs_params.b0odt);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_ODTCTRL, dcs_params.b0odtctrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_DRIVESTR, dcs_params.b1drivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_ODTCTRL, dcs_params.b1odtctrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_WKPUPD, 0);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_IOCTL, dcs_params.b1ioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_ODT, dcs_params.b1odt);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_WKPUPD, 0x00000782);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_DRIVESTR, dcs_params.dqs0drivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_IOCTL, dcs_params.dqs0ioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_ODT, dcs_params.dqs0odt);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_ZDETBIASEN, dcs_params.dqs0zdetbiasen);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_ODTCTRL, dcs_params.dqs0odtctrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_WKPUPD, 0x00000782);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_DRIVESTR, dcs_params.dqs1drivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_IOCTL, dcs_params.dqs1ioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_ODT, dcs_params.dqs1odt);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_ZDETBIASEN, dcs_params.dqs1zdetbiasen);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_ODTCTRL, dcs_params.dqs1odtctrl);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DBG_REG0, 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_ZCAL_FSM(1), dcs_params.zcalfsm1);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_ZCAL_FSM(0), dcs_params.zcalfsm0);
|
||||
|
||||
if (dcs_cfg.chipRev < CHIP_REVISION_B0)
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_SPARE(0), dcs_params.spare0);
|
||||
else
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_SPARE(0), 0x00000816);
|
||||
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPINIT(i), 0x00000001);
|
||||
|
||||
if (dcs_cfg.chipRev < CHIP_REVISION_B0)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DFICALTIMING, dcs_params.dficaltiming);
|
||||
else
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DFICALTIMING, 0x06001604);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ0, 0), 0x06021604);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ1, 0), 0x06021604);
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDDQCALTVREF, dcs_params.hwrddqcaltvref);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 3: Self-Refresh Exit
|
||||
//================================================================================
|
||||
void dcs_init_Self_Refresh_Exit_a(void)
|
||||
{
|
||||
// Wait 5 us after Impedence Calibration to avoid McPhyPending
|
||||
// preventing the SRFSM from exiting SR.
|
||||
dcs_spin(5, "after Imp. Cal.");
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFPARAM, dcs_params.arefparam);
|
||||
|
||||
for(int i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_FREQ(i), dcs_params.freq[i].autoref2);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_PARAMS, dcs_params.autoref_params2);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc);
|
||||
// M8 Bug radar #20346417, two writes to ensure propogation
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LONGSR, dcs_params.longsr);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LONGSR, dcs_params.longsr);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MCPHYUPDTPARAM, 0x15030004);
|
||||
|
||||
}
|
||||
|
||||
//========================================
|
||||
// Caller Code should:
|
||||
// - Change Frequency to 50MHz
|
||||
//========================================
|
||||
|
||||
void dcs_init_Self_Refresh_Exit_b(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCTRL, 0x00000003);
|
||||
|
||||
|
||||
if (!izFPGA) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_IMPCALCMD, 0x00000001);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_IMPCALCMD, 0x01, 0x00);
|
||||
}
|
||||
|
||||
if (izResume)
|
||||
dcs_enable_autorefresh();
|
||||
|
||||
dcs_spin(2200, "After Enable Auto-Refresh");
|
||||
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, dcs_params.freqchngctl_step3);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_FREQCHNGCTL, 0x10000, 0x00000);
|
||||
dcs_spin(2, "After SoC Update");
|
||||
}
|
||||
|
||||
// Resume-Boot and Cold-Boot use different Exit commands for Self-Refresh
|
||||
// Issue self-refresh exit cmd for resume boot with MPC
|
||||
int n = (izColdBoot)? 0x00000000:0x00004000;
|
||||
// Issue self-refresh exit cmd for resume boot with MPC
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MRINITCMD_0, n);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MRINITCMD_0, n | 0x1);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_MRINITCMD_0, 0x01, 0x00);
|
||||
|
||||
dcs_spin(2, NULL);
|
||||
|
||||
dcs_reg_write(rGLBTIMER_CHEN, (1 << dcs_cfg.num_dcs) - 1);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 4: DRAM Reset, ZQ Calibration & Configuration (cold boot only)
|
||||
//================================================================================
|
||||
void dcs_init_ZQ_Cal_Cfg(void)
|
||||
{
|
||||
// ZQ calibration START MPC cmd
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0, 0x4f);
|
||||
// wait 1us for tZQCAL
|
||||
dcs_spin(1, "tZQCAL");
|
||||
|
||||
// ZQ calibration LATCH MPC cmd
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0, 0x51);
|
||||
// wait 10ns for tZQLAT
|
||||
dcs_spin(1, "tZQLAT");
|
||||
|
||||
if (izColdBoot) {
|
||||
// MR2 register (read/write latency)
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x2, 0x0);
|
||||
// MR1 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x1, 0x8e);
|
||||
// MR3 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x3, dcs_params.mr3cmd);
|
||||
// MR22 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x16, 0x0);
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xb, 0x0);
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xd, dcs_params.mr13cmd);
|
||||
// MR12 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xc, 0x59);
|
||||
// MR14 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xe, 0x59);
|
||||
|
||||
// MR23 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x17, 0x80);
|
||||
|
||||
uint32_t patinvertmask = (DCS_REG_READ_CH(0, rDCS_AMP_HWRDDQCALPATPRBS4I) >> 16) & 0xffff;
|
||||
uint32_t prbs = DCS_REG_READ_CH(0, rDCS_AMP_HWWRDQCALPATPRBS4I);
|
||||
|
||||
// MR15 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xf, patinvertmask & 0xff);
|
||||
// MR20 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x14, (patinvertmask >> 8) & 0xff);
|
||||
// MR32 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x20, prbs & 0xff);
|
||||
// MR40 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x28, (prbs >> 8) & 0xff);
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 5a: AddrConfig Configuration
|
||||
//================================================================================
|
||||
void dcs_init_AddrCfg_Cfg(void)
|
||||
{
|
||||
|
||||
dcs_reg_write(rAMCC_ADDRCFG_ADDR, dcs_params.addrcfg);
|
||||
#if NUM_AMCCS == 2
|
||||
dcs_reg_write(rAMCC1_ADDRCFG_ADDR, dcs_params.addrcfg);
|
||||
#endif
|
||||
}
|
||||
|
||||
//========================================
|
||||
// Caller Code should:
|
||||
// - Use MR Cmds to Query the Device
|
||||
//========================================
|
||||
|
||||
//================================================================================
|
||||
// Step 5b: Total Mem Size Config
|
||||
//================================================================================
|
||||
void dcs_init_TotalSize_Cfg(uint32_t total_size_Mbytes)
|
||||
{
|
||||
dbgprintf(DCS_DBG_ASSESS_CONFIG, "Memory_size: %llu bytes\n",
|
||||
(((uint64_t)total_size_Mbytes) * MEG * NUM_AMCCS));
|
||||
// (Units of 128 MBs in the register)
|
||||
dcs_reg_write(rAMCC_DRAMACCCTRL_ADDR, ((total_size_Mbytes / NUM_AMCCS) / DCS_NUM_MEG_IN_DRAM_BLK) - 1);
|
||||
dcs_reg_write(rAMCC_MCCCHNLDEC_ADDR, dcs_params.chnldec);
|
||||
|
||||
#if NUM_AMCCS == 2
|
||||
dcs_reg_write(rAMCC1_DRAMACCCTRL_ADDR, ((total_size_Mbytes / NUM_AMCCS) / DCS_NUM_MEG_IN_DRAM_BLK) - 1);
|
||||
dcs_reg_write(rAMCC1_MCCCHNLDEC_ADDR, dcs_params.chnldec);
|
||||
#endif
|
||||
|
||||
dbgprintf(DCS_DBG_ASSESS_CONFIG, "rAMCC_DRAMACCCTRL: 0x%08x\n", rAMCC_DRAMACCCTRL);
|
||||
|
||||
const struct dcs_memory_device_info *dev_info = dcs_get_memory_device_info();
|
||||
if((dev_info->vendor_id == JEDEC_LPDDR4_MANUF_ID_SAMSUNG) && (dev_info->rev_id == 5) && (dev_info->rev_id2 <= 1))
|
||||
apply_samsung_workaround = true;
|
||||
|
||||
if(apply_samsung_workaround) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ0, 0), 0x00d800d8);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ1, 0), 0x00d800d8);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ0, 1), 0x00d800d8);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ1, 1), 0x00d800d8);
|
||||
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x3, 0xf2);
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0, 0x4f);
|
||||
|
||||
dcs_spin(1, " For tZQCAL");
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0, 0x51);
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL_FREQ(2, 0), 0xb203330b);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL_FREQ(4, 0), 0x00000316);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL_FREQ(2, 3), 0xf203000b);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CB_IMPCTL, 0x01001c2b);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_ODT, 0x01c00339);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_ODT, 0x01c00339);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_ODT, 0x01c00339);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_ODT, 0x01c00339);
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 6: Switch from boot-clock speed to normal operation speed
|
||||
//================================================================================
|
||||
void dcs_init_Reenable_AMC_Scheduler(void)
|
||||
{
|
||||
// Wait 5 us before freq change to make sure all refreshes have been flushed
|
||||
dcs_spin(5, "After Refresh");
|
||||
|
||||
// Enable (again) the AMC Scheduler
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCTRL, 0x00000003);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 7: Setup registers for CA calibration for bucket 1
|
||||
//================================================================================
|
||||
void dcs_init_CA_Cal_Setup_Freq1(void)
|
||||
{
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xd, dcs_params.mr13cmd_step7);
|
||||
|
||||
if (izColdBoot) {
|
||||
if (izFPGA) {
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xb, 0x00);
|
||||
} else {
|
||||
// MR2 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x2, 0x52);
|
||||
// MR1 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x1, 0xae);
|
||||
// MR3 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x3, dcs_params.mr3cmd_step7);
|
||||
// MR22 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x16, dcs_params.mr22cmd);
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xb, dcs_params.mr11cmd);
|
||||
// MR12 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xc, 0x11);
|
||||
// MR14 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xe, 0x11);
|
||||
}
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x00000200);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x0200, 0x0000);
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 8: AMP Dynamic CA Vref Timing Calibration at Vmin 800MHz
|
||||
//================================================================================
|
||||
void dcs_init_CA_Cal_Freq1(void)
|
||||
{
|
||||
// Nothing to be done at this step for cold boot
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 9: Setup registers for DQ calibration for bucket 1
|
||||
//================================================================================
|
||||
void dcs_init_DQ_Cal_Setup_Freq1_a(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (izColdBoot) {
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xd, dcs_params.mr13cmd_step9);
|
||||
}
|
||||
|
||||
dcs_spin(1, NULL);
|
||||
|
||||
if(izResume) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PWRMNGTEN, 0x00000002);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, 0x01008888);
|
||||
|
||||
for(i = AMP_DQ0 ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(i), 0xFF00000C);
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_DEFER_EN(i), 0x00000000);
|
||||
for(i = AMP_DQ0; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MDLLOVRRD(i), 0x00000000);
|
||||
}
|
||||
}
|
||||
|
||||
// Caller code should change frequency to bucket 1
|
||||
void dcs_init_DQ_Cal_Setup_Freq1_b(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, dcs_params.freqchngctl_step9);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_FREQCHNGCTL, 0x10000, 0x00000);
|
||||
|
||||
// Wait 2us for the soc update to finish
|
||||
dcs_spin(2, NULL);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 10: PHY write DQ calibration
|
||||
//================================================================================
|
||||
void dcs_init_wrdq_skew(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSDQ_SKEWCTL(AMP_DQ0), 0x06000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSDQ_SKEWCTL(AMP_DQ1), 0x06000000);
|
||||
}
|
||||
|
||||
|
||||
|
||||
//================================================================================
|
||||
// Step 11: Setup registers for CA calibration for bucket 0
|
||||
//================================================================================
|
||||
void dcs_init_CA_Cal_Setup_Freq0(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
|
||||
if(dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ0), 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ1), 0x00000000);
|
||||
}
|
||||
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, dcs_params.mr13cmd_step11);
|
||||
if (!izFPGA) {
|
||||
// MR2 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x02, dcs_params.mr2cmd_step11);
|
||||
// MR1 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x01, dcs_params.mr1cmd_step11);
|
||||
// MR3 register
|
||||
if(apply_samsung_workaround)
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x03, 0xb2);
|
||||
else
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x03, dcs_params.mr3cmd_step11);
|
||||
}
|
||||
|
||||
if(apply_samsung_workaround) {
|
||||
// MR22 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x16, 0x03);
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0b, 0x33);
|
||||
} else {
|
||||
// MR22 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x16, dcs_params.mr22cmd_step11);
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0b, (izFPGA) ? 0x00 : dcs_params.mr11cmd_step11);
|
||||
}
|
||||
|
||||
// MR12 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0c, dcs_params.mr12cmd_step11);
|
||||
// MR14 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0e, dcs_params.mr14cmd_step11);
|
||||
|
||||
if((dcs_params.supported_freqs & DCS_FREQ(1)) == 0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x00000200);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x200, 0x000);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 12: AMP Dynamic CA Timing Calibration
|
||||
//================================================================================
|
||||
|
||||
//================================================================================
|
||||
// Step 13: Setup registers for DQ calibration for bucket 0
|
||||
//================================================================================
|
||||
void dcs_init_DQ_Cal_Setup_Freq0_a(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, dcs_params.mr13cmd_step13);
|
||||
|
||||
// Wait 1 us
|
||||
dcs_spin(1, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
void dcs_init_DQ_Cal_Setup_Freq0_b(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, 0x00010000);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_FREQCHNGCTL, 0x10000, 0x00000);
|
||||
|
||||
// Wait 2us for the soc update to finish
|
||||
dcs_spin(2, NULL);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 14: AMP Dynamic DQ Calibration
|
||||
//================================================================================
|
||||
void dcs_init_post_wrlvl(void)
|
||||
{
|
||||
if(dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ0), 0x00000010);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ1), 0x00000010);
|
||||
}
|
||||
if (!izFPGA)
|
||||
{
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_WKPUPD, dcs_params.dqs0wkpupd);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_WKPUPD, dcs_params.dqs1wkpupd);
|
||||
}
|
||||
}
|
||||
//================================================================================
|
||||
// Step 15: Setup Registers for Boot
|
||||
//================================================================================
|
||||
void dcs_init_Reg_for_Boot(void)
|
||||
{
|
||||
if (dcs_cfg.chipRev >= CHIP_REVISION_B0)
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_SPARE(0), 0xc16);
|
||||
|
||||
#ifndef DCS_RUN_AT_50MHZ
|
||||
if (izColdBoot) {
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, dcs_params.mr13cmd_step15);
|
||||
}
|
||||
#endif
|
||||
|
||||
if(izFPGA && !(dcs_params.supported_freqs & DCS_FREQ(1)))
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, 0x50);
|
||||
|
||||
// Wait 1 us
|
||||
dcs_spin(1, NULL);
|
||||
|
||||
if (izColdBoot) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, dcs_params.freqchngctl_step15);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ0), 0xff000008);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ1), 0xff000008);
|
||||
|
||||
|
||||
#if !DCS_DO_CALIBRATION
|
||||
// skip these for all silicon targets, where calibration is performed, also skip for any Maui A1 target
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQSDLL_DLYSEL(AMP_DQ0), 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQSDLL_DLYSEL(AMP_DQ1), 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step15);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step15);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step15 & 0x7, 0x0);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step15 & 0x7, 0x0);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
if(!izFPGA)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDWRDQCALFULLSCANEN, 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDWRDQCALFULLSCANEN, 0x00000003);
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDDQCALVREFCONTROL, 0x01D0B061);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALVREFCONTROL, 0x02200061);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 16: Enable Other Features
|
||||
//================================================================================
|
||||
void dcs_init_MoreFeatures(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFPARAM, dcs_params.arefparam);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc2);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_QBREN, dcs_params.qbren_step16);
|
||||
if (izColdBoot)
|
||||
dcs_enable_autorefresh();
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_DYN_ISEL_ASRTIME, dcs_params.b0dyniselasrtime);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_DYN_ISEL, dcs_params.b0dynisel);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_DYN_ISEL, dcs_params.b1dynisel);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 17: Enable Fast Critical Word Forwarding Feature
|
||||
//================================================================================
|
||||
void dcs_init_Fast_Critical_Word_Forwarding(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_MCU_QBRPARAM, dcs_params.qbrparam);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_QBREN, dcs_params.qbren);
|
||||
dcs_reg_write(rAMCC_MCCGEN_ADDR, dcs_params.mccgen);
|
||||
dcs_reg_write(rAMCC_MCC0QPROPCTRL_ADDR, 0x300011a2);
|
||||
dcs_reg_write(rAMCC_MCC1QPROPCTRL_ADDR, 0x300011a2);
|
||||
|
||||
#if NUM_AMCCS == 2
|
||||
dcs_reg_write(rAMCC1_MCCGEN_ADDR, dcs_params.mccgen);
|
||||
dcs_reg_write(rAMCC1_MCC0QPROPCTRL_ADDR, 0x300011a2);
|
||||
dcs_reg_write(rAMCC1_MCC1QPROPCTRL_ADDR, 0x300011a2);
|
||||
#endif // #if NUM_AMCCS == 2
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 18: Enable Power- and Clock-Gating Features; Config MCC and Global Timers
|
||||
//================================================================================
|
||||
void dcs_init_Gating_Global_Timers(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPCLK(AMP_CA), dcs_params.caampclk);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPCLK(AMP_DQ0), dcs_params.dqampclk);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPCLK(AMP_DQ1), dcs_params.dqampclk);
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_MDLLPWRDNCFG(0), 0x00000001);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PWRMNGTEN, dcs_params.pwrmngten);
|
||||
|
||||
// Global Timer Setup
|
||||
|
||||
dcs_reg_write(rGLBTIMER_PMGRWAKEUPCFG, 0x0001ff);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQ2ALLBANKDLY(0), 0x00f000f0);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQ2ALLBANKDLY(1), 0x00f000f0);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQCHNG2FREQCHNGDLY(0), 0x02400240);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQCHNG2FREQCHNGDLY(1), 0x02400240);
|
||||
|
||||
dcs_reg_write(rGLBTIMER_CALSEG2ALLBANK(0), 0x00fa0120);
|
||||
dcs_reg_write(rGLBTIMER_ALLBANK2CALSEG(0), 0x00fa0120);
|
||||
|
||||
dcs_reg_write(rGLBTIMER_MDLLTIMER, 0x000bb8);
|
||||
dcs_reg_write(rGLBTIMER_DCCTIMER, 0x000bb8);
|
||||
dcs_reg_write(rGLBTIMER_MDLLVOLTRAMPTIMER, 0x00004b);
|
||||
dcs_reg_write(rGLBTIMER_CTRLUPDMASKTIMER, 0x00000f);
|
||||
// <rdar://problem/19573098> Elba A0: Samsung 20nm Rev0 LPDDR4 work-around(disable IDT cal)
|
||||
//dcs_reg_write(rGLBTIMER_IDTTIMER, 0x007530); // 30000
|
||||
dcs_reg_write(rGLBTIMER_RDCALTIMER, 0x002dc6bb);
|
||||
dcs_reg_write(rGLBTIMER_WRCALTIMER, 0x002dc6c0);
|
||||
|
||||
// <rdar://problem/23244578> Elba: Samsung DRAM workaround: disable hw zqcal
|
||||
if(!apply_samsung_workaround)
|
||||
dcs_reg_write(rGLBTIMER_ZQCTIMER, 0x3d0900);
|
||||
|
||||
dcs_reg_write(rGLBTIMER_PERCAL_FREQCHNGTIMER, 0x000001);
|
||||
dcs_reg_write(rGLBTIMER_IMPCALTIMER, 0x002ee0);
|
||||
|
||||
// Dynamic Clk & Power Gating
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCLKPWRGATE, 0x050a0000);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 19: ODTS read & set interval for periodic MR4 on-die Temp sensor reading
|
||||
//================================================================================
|
||||
void dcs_init_ODTS(void)
|
||||
{
|
||||
uint8_t temp[16*8]; // Far more Channels/Ranks than we are likely ever to have/need
|
||||
// INSTEAD OF: uint8_t temp[dcs_cfg.num_dcs * dcs_cfg.num_rank];
|
||||
|
||||
// MR4 read to bring memory out of self-refresh
|
||||
dcs_mrcmd(MR_READ, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x4, (uintptr_t)temp);
|
||||
// M8 Bug radar #20346417, two writes to ensure propogation
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc3);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc3);
|
||||
|
||||
}
|
||||
|
||||
// <rdar://problem/23244578>: This function used in calibration code for Elba
|
||||
bool shim_apply_samsung_workaround(void)
|
||||
{
|
||||
return apply_samsung_workaround;
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
@@ -0,0 +1,889 @@
|
||||
/*
|
||||
* Copyright (C) 2014-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Init Sequence Library for use in:
|
||||
* Driver for the LPDDR4 compatible DRAM Control Subsystem (DCS) block
|
||||
*/
|
||||
|
||||
/*
|
||||
Summary of Steps from the Spec (Spreadsheet)
|
||||
|
||||
+ (Aa) Steps 0,1,2,3a [need to identify parameterization]
|
||||
+ (Ab) Step 3b [PMGR: set Freq to 50MHz & delay-wait]
|
||||
+ (Ac) Steps 3c,4,5 [need to identify parameterization]
|
||||
+ (B) Step 6 [Change Clk Speed]
|
||||
+ (C) Step 7 [include delay-wait from early Step 8]
|
||||
+ (D) Step 8a [Cal: CA 800MHz Vmin]
|
||||
+ (E) Step 8b [Write Regs]
|
||||
+ (F) Step 8c [Cal: CA 800MHz Vmin] (...again? should it be CS?)
|
||||
+ (G) Step 8d [Write Regs]
|
||||
+ (H) Step 9 [Write Regs]
|
||||
+ (I) Step 10 [Cal: WrLvl, RdDq, WrDq 800MHz Vmin]
|
||||
+ (J) Step 11 [Write Regs]
|
||||
+ (K) Step 12 [Cal: CA 1200MHz Vnom]
|
||||
+ (L) Step 13 [Write Regs]
|
||||
+ (M) Step 14 [Cal: WrLvl, RdDq, WrDq 1200MHz Vmin]
|
||||
+ (N) Steps 15,16,17,18,19,20 [need to identify parameterization]
|
||||
|
||||
Between these steps there is possibly a need/desire for:
|
||||
- Frequency Changes (PMGR)
|
||||
- PMU save/restore
|
||||
- debug messages
|
||||
- register dumps (DV, SiVal)
|
||||
- anything else!
|
||||
|
||||
CONFIG Table:
|
||||
Compile-Time Known:
|
||||
Type of Execution Environment CoreOS, DV, SiVal
|
||||
Type of Target SoC, FPGA, Palladium
|
||||
ChipID 0x8000, 0x8001, etc.
|
||||
Revision A0, B0, B1, etc.
|
||||
Num DCS 4, 8, etc. (Derived...!)
|
||||
Variant Flags Work-arounds, RADAR Ref., et al.
|
||||
|
||||
(Config Info know at Compile time can be subject to #if)
|
||||
|
||||
Run-Time Known:
|
||||
Type of Init ColdBoot, AOP_DDR, AOP_AWAKE
|
||||
Debug Flags Low-Level, Milestone, et al.
|
||||
|
||||
RegValue Table
|
||||
Much like today's: various values for various registers
|
||||
Sensitive to ChipID (also Target type?)
|
||||
(Internal static alloc (Complete Table Fill-in within Init function):
|
||||
Fill in Values (per ChipID/Rev & Target-type)
|
||||
return pointer to caller
|
||||
(Allows customization by caller before use)
|
||||
|
||||
TODO:
|
||||
- Convert to using SPDS for register names, et al
|
||||
|
||||
*/
|
||||
|
||||
//================================================================================
|
||||
// API Definitions
|
||||
#include <drivers/dcs/dcs_init_lib.h>
|
||||
|
||||
extern dcs_config_t dcs_cfg;
|
||||
extern dcs_config_params_t dcs_params;
|
||||
|
||||
#if izIBOOT
|
||||
extern int debug_level_dcs;
|
||||
#endif
|
||||
|
||||
void dcs_enable_autorefresh(void)
|
||||
{
|
||||
// Configure auto-refresh. Freq0 has the auto-refresh enable, so do it last.
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(3), 0x11100000);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(2), 0x11000000);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(1), 0x11110000);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(0), 0x1111013f);
|
||||
}
|
||||
|
||||
|
||||
|
||||
//================================================================================
|
||||
// Implementing the Various Steps of the DCS Init, per Specification
|
||||
// Based on AMC Init Spec (Spreadsheet)
|
||||
// - Supporting Maui: Spec (v??)
|
||||
//================================================================================
|
||||
// Step 0: AMC Prolog
|
||||
//================================================================================
|
||||
void dcs_init_Prolog(void)
|
||||
{
|
||||
// NOTE: between the Compiler and the Optimization, this should vanish for non-FPGA builds
|
||||
if (izFPGA && izColdBoot) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 1);
|
||||
delay_for_us(200);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 0);
|
||||
delay_for_us(200);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 1);
|
||||
delay_for_us(200);
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 1: AMC Initial Configuration
|
||||
//================================================================================
|
||||
void dcs_init_AMC_Initial_Config(void)
|
||||
{
|
||||
uint32_t i,n;
|
||||
|
||||
// rdar://problem/19137387: this applies to Maui A1 and B0, as well as other SoCs before Cayman
|
||||
|
||||
dcs_reg_write(rAMCC_MCCCHNLDEC_ADDR, dcs_params.chnldec);
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_CHARGEPUMP, 0x00000068);
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_VCO, dcs_params.spllctrl_vco_1);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_VCO, dcs_params.spllctrl_vco_2);
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_LDO, 0x00000004);
|
||||
|
||||
// This register write to be skipped for Maui A0/A1, but written to for B0 & later, and all other SoCs
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0))
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_SPLLPWRDNCFG, 0x00000011);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
for (n = 0; n < dcs_params.num_freqchngctl_regs; n++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL_FREQ(n, i), dcs_params.freq[i].freqchngctl[n]);
|
||||
|
||||
// This register write to be skipped for Maui A0/A1, but written to for B0 & later, and all other SoCs
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0))
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGTIM_FREQ(i), dcs_params.freq[i].freqchngtim);
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_RWCFG, dcs_params.rwcfg);
|
||||
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTCTRL(i), dcs_params.dllupdtctrl);
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LAT_FREQ(0), dcs_params.freq[0].lat);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LAT_FREQ(1), dcs_params.freq[1].lat);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PHYRDWRTIM_FREQ(i), dcs_params.freq[i].phyrdwrtim);
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_CASPCH_FREQ(i), dcs_params.freq[i].caspch);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ACT_FREQ(i), dcs_params.freq[i].act);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_FREQ(i), dcs_params.freq[i].autoref);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_SELFREF_FREQ(i), dcs_params.freq[i].selfref);
|
||||
|
||||
if (i == 0) dcs_reg_write_all_chan(rDCS_MCU_MODEREG, dcs_params.modereg);
|
||||
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_PARAMS, dcs_params.autoref_params);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PDN, dcs_params.pdn);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_DERATE_FREQ(0), dcs_params.freq[0].derate);
|
||||
|
||||
// These register writes to be skipped for Maui A0/A1, but written to for B0 & later, and all other SoCs
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0))
|
||||
for(i = 1; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_DERATE_FREQ(i), dcs_params.freq[i].derate);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LAT_FREQ(i), dcs_params.freq[i].lat2);
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_TAT_FREQ(i), dcs_params.freq[i].tat);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_RNKCFG, dcs_params.rnkcfg);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MIFQMAXCTRL_FREQ(0), dcs_params.freq[0].mifqmaxctrl);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MIFQMAXCTRL_FREQ(3), dcs_params.freq[3].mifqmaxctrl);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PWRMNGTEN, 0);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, 0x00002000);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCTRL, 0x00000002);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MCPHYUPDTPARAM, 0x15030000);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 2: AMP Initial Configuration
|
||||
//================================================================================
|
||||
void dcs_init_AMP_Initial_Config(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPEN(i), 0x00000001);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_NONDQDSPD_F(i), dcs_params.freq[i].nondqdspd);
|
||||
|
||||
for(i = 1; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_NONDQDS_F(i), dcs_params.freq[i].nondqds);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CACKCSWKDS, dcs_params.cackcswkds);
|
||||
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_CA, i), dcs_params.freq[i].cavref);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_ODTENABLE_F(0), dcs_params.freq[0].odt_enable);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_ODTENABLE_F(1), dcs_params.freq[1].odt_enable);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_ODTENABLE_F(3), dcs_params.freq[3].odt_enable);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
// These register writes to be skipped for Maui A0/A1
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQDS_F(AMP_DQ0,i), dcs_params.freq[i].dqds);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQDS_F(AMP_DQ1,i), dcs_params.freq[i].dqds);
|
||||
}
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQDQSDS_F(AMP_DQ0,i), dcs_params.freq[i].dqdqsds);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQDQSDS_F(AMP_DQ1,i), dcs_params.freq[i].dqdqsds);
|
||||
}
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ0, i), dcs_params.freq[i].dqvref);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ1, i), dcs_params.freq[i].dqvref);
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSPDRES(AMP_DQ0), dcs_params.dqspdres);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSPDRES(AMP_DQ1), dcs_params.dqspdres);
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_CNTL(AMP_CA), dcs_params.casdllupdatectrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_CNTL(AMP_DQ0), dcs_params.dqsdllupdatectrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_CNTL(AMP_DQ1), dcs_params.dqsdllupdatectrl);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step2);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step2);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step2 & 0x7, 0x0);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step2 & 0x7, 0x0);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ0), dcs_params.wrdqdqssdllctrl_step2);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ1), dcs_params.wrdqdqssdllctrl_step2);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ0), dcs_params.wrdqdqssdllctrl_step2 & 0x7, 0x0);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ1), dcs_params.wrdqdqssdllctrl_step2 & 0x7, 0x0);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, dcs_params.cawrlvlsdllcode);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, dcs_params.cawrlvlsdllcode & 0x300, 0x000);
|
||||
|
||||
if (!izFPGA)
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLLOCKTIM(i), dcs_params.dlllocktim);
|
||||
|
||||
if(dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSPDENALWYSON(AMP_DQ0), 0x00000001);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSPDENALWYSON(AMP_DQ1), 0x00000001);
|
||||
}
|
||||
|
||||
if((dcs_params.supported_freqs & DCS_FREQ(1)) != 0)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DFICALTIMING, dcs_params.dficaltiming);
|
||||
|
||||
// These register writes to be skipped for Maui A0/A1
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
for(i = 1; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMPCA_DFICALTIMING_F(i), dcs_params.freq[i].cadficaltiming);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ0, i), dcs_params.freq[i].dqdficaltiming);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ1, i), dcs_params.freq[i].dqdficaltiming);
|
||||
}
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MDLLCODE_CAP_CNTL(AMP_DQ0), 0x00000002);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MDLLCODE_CAP_CNTL(AMP_DQ1), 0x00000002);
|
||||
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALTIMING_F(0), dcs_params.rdwrdqcaltiming_f0);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALSEGLEN_F(0), dcs_params.rdwrdqcalseglen_f0);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALTIMING_F(1), dcs_params.rdwrdqcaltiming_f1);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALSEGLEN_F(1), dcs_params.rdwrdqcalseglen_f1);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDWRDQCALTIMINGCTRL(1), dcs_params.rdwrdqcaltimingctrl1);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDWRDQCALTIMINGCTRL(2), dcs_params.rdwrdqcaltimingctrl2);
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDDQCALPATPRBS4I, dcs_params.rddqcalpatprbs4i);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATPRBS4I, dcs_params.wrdqcalpatprbs4i);
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQCALWINDOW_F(0), dcs_params.freq[0].rddqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQCALWINDOW_F(0), dcs_params.freq[0].wrdqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQCALWINDOW_F(1), dcs_params.freq[1].rddqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQCALWINDOW_F(1), dcs_params.freq[1].wrdqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MAXRDDQS_SDLL_MULFACTOR, dcs_params.maxrddqssdllmulfactor);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MAXWRDQ_SDLL_MULFACTOR, 0x00a00a0f);
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MAXWRDQS_SDLL_MULFACTOR, dcs_params.maxwrdqssdllmulfactor);
|
||||
|
||||
// These register writes to be skipped for Maui A0/A1
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_RDDQSMULFACTOR(AMP_DQ0), 0x20181000);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_RDDQSMULFACTOR(AMP_DQ1), 0x20181000);
|
||||
}
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CAOUTDLLSCL_FREQ(i), dcs_params.freq[i].caoutdllscl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSINDLLSCL_FREQ(AMP_DQ0, i), dcs_params.freq[i].dqsindllscl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSINDLLSCL_FREQ(AMP_DQ1, i), dcs_params.freq[i].dqsindllscl);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDCAPCFG_FREQ(AMP_DQ0, i), dcs_params.freq[i].rdcapcfg);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDCAPCFG_FREQ(AMP_DQ1, i), dcs_params.freq[i].rdcapcfg);
|
||||
}
|
||||
|
||||
if (!izFPGA) {
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTCTRL(i), dcs_params.dllupdtctrl1);
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_IMPAUTOCAL, 0x00010000);
|
||||
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTINTVL(AMP_CA), dcs_params.dllupdtintvl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTINTVL(AMP_DQ0), dcs_params.dllupdtintvl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTINTVL(AMP_DQ1), dcs_params.dllupdtintvl);
|
||||
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLEN(i), 0x00000100);
|
||||
|
||||
if(!izFPGA) {
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_IMPCALCMD, 0x00000000);
|
||||
}
|
||||
|
||||
// Workaround for Maui B0
|
||||
if((dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0))
|
||||
dcs_reg_write_all_chan(rDCS_AMP_BISTRXMODE, 0x0000001c);
|
||||
|
||||
|
||||
|
||||
// AMPH configuration
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CB_WKPUPD, 0);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CB_DRIVESTR, dcs_params.cbdrivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CB_IOCTL, dcs_params.cbioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CK_WKPUPD, 0);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CK_ZDETBIASEN, 0);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CK_DRIVESTR, dcs_params.ckdrivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CK_IOCTL, dcs_params.ckioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_DRIVESTR, dcs_params.b0drivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_IMPCTL, 0x00201c2b);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_WKPUPD, 0);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_IOCTL, dcs_params.b0ioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_ODT, dcs_params.b0odt);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_ODTCTRL, dcs_params.b0odtctrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_DRIVESTR, dcs_params.b1drivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_ODTCTRL, dcs_params.b1odtctrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_IMPCTL, 0x00201c2b);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_WKPUPD, 0);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_IOCTL, dcs_params.b1ioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_ODT, dcs_params.b1odt);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_WKPUPD, 0x00000788);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_DRIVESTR, dcs_params.dqs0drivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_IMPCTL, 0x00201c2b);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_IOCTL, dcs_params.dqs0ioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_ODT, dcs_params.dqs0odt);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_ZDETBIASEN, dcs_params.dqs0zdetbiasen);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_ODTCTRL, dcs_params.dqs0odtctrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_WKPUPD, 0x00000788);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_DRIVESTR, dcs_params.dqs1drivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_IMPCTL, 0x00201c2b);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_IOCTL, dcs_params.dqs1ioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_ODT, dcs_params.dqs1odt);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_ZDETBIASEN, dcs_params.dqs1zdetbiasen);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_ODTCTRL, dcs_params.dqs1odtctrl);
|
||||
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DBG_REG0, 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_ZCAL_FSM(1), dcs_params.zcalfsm1);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_ZCAL_FSM(0), dcs_params.zcalfsm0);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_SPARE(0), dcs_params.spare0);
|
||||
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPINIT(i), 0x00000001);
|
||||
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 3: Self-Refresh Exit
|
||||
//================================================================================
|
||||
void dcs_init_Self_Refresh_Exit_a(void)
|
||||
{
|
||||
// Wait 5 us after Impedence Calibration to avoid McPhyPending
|
||||
// preventing the SRFSM from exiting SR.
|
||||
dcs_spin(5, "after Imp. Cal.");
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFPARAM, dcs_params.arefparam);
|
||||
|
||||
for(int i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_FREQ(i), dcs_params.freq[i].autoref2);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_PARAMS, dcs_params.autoref_params2);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LONGSR, dcs_params.longsr);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MCPHYUPDTPARAM, 0x15030007);
|
||||
|
||||
|
||||
}
|
||||
|
||||
//========================================
|
||||
// Caller Code should:
|
||||
// - Change Frequency to 50MHz
|
||||
//========================================
|
||||
|
||||
void dcs_init_Self_Refresh_Exit_b(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCTRL, 0x00000003);
|
||||
|
||||
|
||||
if (!izFPGA) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_IMPCALCMD, 0x00000001);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_IMPCALCMD, 0x01, 0x00);
|
||||
}
|
||||
|
||||
if (izResume)
|
||||
dcs_enable_autorefresh();
|
||||
|
||||
dcs_spin(2200, "After Enable Auto-Refresh");
|
||||
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, dcs_params.freqchngctl_step3);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_FREQCHNGCTL, 0x10000, 0x00000);
|
||||
dcs_spin(2, "After SoC Update");
|
||||
}
|
||||
|
||||
// Resume-Boot and Cold-Boot use different Exit commands for Self-Refresh
|
||||
// Issue self-refresh exit cmd for resume boot with MPC
|
||||
int n = (izColdBoot)? 0x00000000:0x00004000;
|
||||
// Issue self-refresh exit cmd for resume boot with MPC
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MRINITCMD_0, n);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MRINITCMD_0, n | 0x1);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_MRINITCMD_0, 0x01, 0x00);
|
||||
|
||||
dcs_spin(2, NULL);
|
||||
|
||||
dcs_reg_write(rGLBTIMER_CHEN, (1 << dcs_cfg.num_dcs) - 1);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 4: DRAM Reset, ZQ Calibration & Configuration (cold boot only)
|
||||
//================================================================================
|
||||
void dcs_init_ZQ_Cal_Cfg(void)
|
||||
{
|
||||
// ZQ calibration START MPC cmd
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0, 0x4f);
|
||||
// wait 1us for tZQCAL
|
||||
dcs_spin(1, "tZQCAL");
|
||||
|
||||
// ZQ calibration LATCH MPC cmd
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0, 0x51);
|
||||
// wait 10ns for tZQLAT
|
||||
dcs_spin(1, "tZQLAT");
|
||||
|
||||
if (izColdBoot) {
|
||||
// MR2 register (read/write latency)
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x2, 0x0);
|
||||
// MR1 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x1, 0x8e);
|
||||
// MR3 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x3, dcs_params.mr3cmd);
|
||||
// MR22 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x16, 0x0);
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xb, 0x0);
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xd, dcs_params.mr13cmd);
|
||||
// MR12 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xc, 0x59);
|
||||
// MR14 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xe, 0x59);
|
||||
|
||||
// MR23 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x17, 0x80);
|
||||
|
||||
uint32_t patinvertmask = (DCS_REG_READ_CH(0, rDCS_AMP_HWRDDQCALPATPRBS4I) >> 16) & 0xffff;
|
||||
uint32_t prbs = DCS_REG_READ_CH(0, rDCS_AMP_HWWRDQCALPATPRBS4I);
|
||||
|
||||
// MR15 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xf, patinvertmask & 0xff);
|
||||
// MR20 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x14, (patinvertmask >> 8) & 0xff);
|
||||
// MR32 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x20, prbs & 0xff);
|
||||
// MR40 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x28, (prbs >> 8) & 0xff);
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 5a: AddrConfig Configuration
|
||||
//================================================================================
|
||||
void dcs_init_AddrCfg_Cfg(void)
|
||||
{
|
||||
|
||||
dcs_reg_write(rAMCC_ADDRCFG_ADDR, dcs_params.addrcfg);
|
||||
}
|
||||
|
||||
//========================================
|
||||
// Caller Code should:
|
||||
// - Use MR Cmds to Query the Device
|
||||
//========================================
|
||||
|
||||
//================================================================================
|
||||
// Step 5b: Total Mem Size Config
|
||||
//================================================================================
|
||||
void dcs_init_TotalSize_Cfg(uint32_t total_size_Mbytes)
|
||||
{
|
||||
|
||||
dbgprintf(DCS_DBG_ASSESS_CONFIG, "Memory_size: %llu bytes\n",
|
||||
(((uint64_t)total_size_Mbytes) * MEG * NUM_AMCCS));
|
||||
|
||||
// (Units of 128 MBs in the register)
|
||||
dcs_reg_write(rAMCC_DRAMACCCTRL_ADDR, ((total_size_Mbytes / NUM_AMCCS) / DCS_NUM_MEG_IN_DRAM_BLK) - 1);
|
||||
dcs_reg_write(rAMCC_MCCCHNLDEC_ADDR, dcs_params.chnldec);
|
||||
|
||||
dbgprintf(DCS_DBG_ASSESS_CONFIG, "rAMCC_DRAMACCCTRL: 0x%08x\n", rAMCC_DRAMACCCTRL);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 6: Switch from boot-clock speed to normal operation speed
|
||||
//================================================================================
|
||||
void dcs_init_Reenable_AMC_Scheduler(void)
|
||||
{
|
||||
// Wait 5 us before freq change to make sure all refreshes have been flushed
|
||||
dcs_spin(5, "After Refresh");
|
||||
|
||||
// Enable (again) the AMC Scheduler
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCTRL, 0x00000003);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 7: Setup registers for CA calibration for bucket 1
|
||||
//================================================================================
|
||||
void dcs_init_CA_Cal_Setup_Freq1(void)
|
||||
{
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xd, dcs_params.mr13cmd_step7);
|
||||
|
||||
if (izColdBoot) {
|
||||
if (izFPGA) {
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xb, 0x00);
|
||||
} else {
|
||||
// MR2 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x2, 0x52);
|
||||
// MR1 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x1, 0xae);
|
||||
// MR3 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x3, dcs_params.mr3cmd_step7);
|
||||
// MR22 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x16, dcs_params.mr22cmd);
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xb, dcs_params.mr11cmd);
|
||||
// MR12 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xc, 0x11);
|
||||
// MR14 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xe, 0x11);
|
||||
}
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x00000200);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x0200, 0x0000);
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 8: AMP Dynamic CA Vref Timing Calibration at Vmin 800MHz
|
||||
//================================================================================
|
||||
void dcs_init_CA_Cal_Freq1(void)
|
||||
{
|
||||
// Nothing to be done at this step for cold boot
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 9: Setup registers for DQ calibration for bucket 1
|
||||
//================================================================================
|
||||
void dcs_init_DQ_Cal_Setup_Freq1_a(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (izColdBoot) {
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xd, dcs_params.mr13cmd_step9);
|
||||
}
|
||||
|
||||
dcs_spin(1, NULL);
|
||||
|
||||
if(izResume) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PWRMNGTEN, 0x00000002);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, 0x01008888);
|
||||
|
||||
for(i = AMP_DQ0 ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(i), 0xFF00000C);
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_DEFER_EN(i), 0x00000000);
|
||||
for(i = AMP_DQ0; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MDLLOVRRD(i), 0x00000000);
|
||||
}
|
||||
}
|
||||
|
||||
// Caller code should change frequency to bucket 1
|
||||
void dcs_init_DQ_Cal_Setup_Freq1_b(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, dcs_params.freqchngctl_step9);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_FREQCHNGCTL, 0x10000, 0x00000);
|
||||
|
||||
// Wait 2us for the soc update to finish
|
||||
dcs_spin(2, NULL);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 10: PHY write DQ calibration
|
||||
//================================================================================
|
||||
void dcs_init_wrdq_skew(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSDQ_SKEWCTL(AMP_DQ0), 0x06000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSDQ_SKEWCTL(AMP_DQ1), 0x06000000);
|
||||
}
|
||||
|
||||
void dcs_init_post_wrlvl(void)
|
||||
{
|
||||
if(dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ0), 0x00000010);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ1), 0x00000010);
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_WKPUPD, dcs_params.dqs0wkpupd);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_WKPUPD, dcs_params.dqs1wkpupd);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 11: Setup registers for CA calibration for bucket 0
|
||||
//================================================================================
|
||||
void dcs_init_CA_Cal_Setup_Freq0(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
|
||||
if(dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ0), 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ1), 0x00000000);
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_WKPUPD, 0x00000788);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_WKPUPD, 0x00000788);
|
||||
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, dcs_params.mr13cmd_step11);
|
||||
if (!izFPGA) {
|
||||
// MR2 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x02, dcs_params.mr2cmd_step11);
|
||||
// MR1 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x01, dcs_params.mr1cmd_step11);
|
||||
// MR3 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x03, dcs_params.mr3cmd_step11);
|
||||
}
|
||||
|
||||
// MR22 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x16, dcs_params.mr22cmd_step11);
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0b, (izFPGA) ? 0x00 : dcs_params.mr11cmd_step11);
|
||||
// MR12 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0c, dcs_params.mr12cmd_step11);
|
||||
// MR14 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0e, dcs_params.mr14cmd_step11);
|
||||
|
||||
if((dcs_params.supported_freqs & DCS_FREQ(1)) == 0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x00000200);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x200, 0x000);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 12: AMP Dynamic CA Timing Calibration
|
||||
//================================================================================
|
||||
|
||||
//================================================================================
|
||||
// Step 13: Setup registers for DQ calibration for bucket 0
|
||||
//================================================================================
|
||||
void dcs_init_DQ_Cal_Setup_Freq0_a(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, dcs_params.mr13cmd_step13);
|
||||
|
||||
// Wait 1 us
|
||||
dcs_spin(1, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
void dcs_init_DQ_Cal_Setup_Freq0_b(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, 0x00010000);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_FREQCHNGCTL, 0x10000, 0x00000);
|
||||
|
||||
// Wait 2us for the soc update to finish
|
||||
dcs_spin(2, NULL);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 14: AMP Dynamic DQ Calibration
|
||||
//================================================================================
|
||||
|
||||
//================================================================================
|
||||
// Step 15: Setup Registers for Boot
|
||||
//================================================================================
|
||||
void dcs_init_Reg_for_Boot(void)
|
||||
{
|
||||
if (dcs_cfg.chipRev > CHIP_REVISION_A0)
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_SPARE(0), 0x0000040e);
|
||||
|
||||
#ifndef DCS_RUN_AT_50MHZ
|
||||
if (izColdBoot) {
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, dcs_params.mr13cmd_step15);
|
||||
}
|
||||
#endif
|
||||
|
||||
if(izFPGA && !(dcs_params.supported_freqs & DCS_FREQ(1)))
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, 0x50);
|
||||
|
||||
// Wait 1 us
|
||||
dcs_spin(1, NULL);
|
||||
|
||||
if (izColdBoot) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, dcs_params.freqchngctl_step15);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ0), 0xff000008);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ1), 0xff000008);
|
||||
|
||||
|
||||
#if !DCS_DO_CALIBRATION
|
||||
// skip these for all silicon targets, where calibration is performed, also skip for any Maui A1 target
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step15);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step15);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step15 & 0x7, 0x0);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step15 & 0x7, 0x0);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDWRDQCALFULLSCANEN, 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDWRDQCALFULLSCANEN, 0x00000003);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 16: Enable Other Features
|
||||
//================================================================================
|
||||
void dcs_init_MoreFeatures(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFPARAM, dcs_params.arefparam);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc2);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_QBREN, dcs_params.qbren_step16);
|
||||
|
||||
if (izColdBoot)
|
||||
dcs_enable_autorefresh();
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_DYN_ISEL_ASRTIME, dcs_params.b0dyniselasrtime);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_DYN_ISEL, dcs_params.b0dynisel);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_DYN_ISEL, dcs_params.b1dynisel);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_DCD_IOCTL, 0x00030000);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_DCD_IOCTL, 0x00030000);
|
||||
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 17: Enable Fast Critical Word Forwarding Feature
|
||||
//================================================================================
|
||||
void dcs_init_Fast_Critical_Word_Forwarding(void)
|
||||
{
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_QBRPARAM, dcs_params.qbrparam);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_QBREN, dcs_params.qbren);
|
||||
|
||||
dcs_reg_poll(rAMCC_MCCPWRONWAYCNTSTATUS_ADDR, 0x7fff7fff, 0x42104210);
|
||||
dcs_reg_write(rAMCC_MCC0QPROPCTRL_ADDR, 0x300011a2);
|
||||
dcs_reg_write(rAMCC_MCC1QPROPCTRL_ADDR, 0x300011a2);
|
||||
dcs_reg_write(rAMCC_MCCGEN_ADDR, dcs_params.mccgen);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 18: Enable Power- and Clock-Gating Features; Config MCC and Global Timers
|
||||
//================================================================================
|
||||
void dcs_init_Gating_Global_Timers(void)
|
||||
{
|
||||
const struct dcs_memory_device_info *dev_info = dcs_get_memory_device_info();
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPCLK(AMP_CA), dcs_params.caampclk);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPCLK(AMP_DQ0), dcs_params.dqampclk);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPCLK(AMP_DQ1), dcs_params.dqampclk);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PWRMNGTEN, dcs_params.pwrmngten);
|
||||
|
||||
|
||||
if(!izFPGA) {
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PWRMNGTPARAM_FREQ(0), 0x01800000);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PSQWQCTL1, 0x01640120);
|
||||
}
|
||||
|
||||
// Global Timer Setup
|
||||
|
||||
if(dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev < CHIP_REVISION_B0) {
|
||||
dcs_reg_write(rGLBTIMER_PMGRWAKEUPCFG, 0x0000ff);
|
||||
dcs_reg_write(rGLBTIMER_MDLLTIMER, 0x000bb8); // 3000
|
||||
dcs_reg_write(rGLBTIMER_MDLLVOLTRAMPTIMER, 0x00004b); // 75
|
||||
dcs_reg_write(rGLBTIMER_CTRLUPDMASKTIMER, 0x00000f); // 15
|
||||
dcs_reg_write(rGLBTIMER_RDCALTIMER, 0x2dc6c0); // 3000000
|
||||
dcs_reg_write(rGLBTIMER_WRCALTIMER, 0x2dc6c0); // 3000000
|
||||
dcs_reg_write(rGLBTIMER_ZQCTIMER, 0x3d0900); // 4000000
|
||||
dcs_reg_write(rGLBTIMER_PERCAL_FREQCHNGTIMER, 0x000001); // 300000
|
||||
dcs_reg_write(rGLBTIMER_VOLTRAMPTIMER, 0x000001); // 300000
|
||||
dcs_reg_write(rGLBTIMER_IMPCALTIMER, 0x002ee0); // 12000
|
||||
} else {
|
||||
dcs_reg_write(rGLBTIMER_PMGRWAKEUPCFG, 0x0000ff);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQ2ALLBANKDLY(0), 0x01500150);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQ2ALLBANKDLY(1), 0x01500150);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQCHNG2FREQCHNGDLY(0), 0x02a002a0);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQCHNG2FREQCHNGDLY(1), 0x02a002a0);
|
||||
|
||||
dcs_reg_write(rGLBTIMER_CAL2PREFREQCHNGDLY(0), 0x00900090);
|
||||
dcs_reg_write(rGLBTIMER_CAL2PREFREQCHNGDLY(1), 0x00900090);
|
||||
dcs_reg_write(rGLBTIMER_FREQCHNG2PSTCALDLY(0), 0x01200120);
|
||||
dcs_reg_write(rGLBTIMER_FREQCHNG2PSTCALDLY(1), 0x01200120);
|
||||
|
||||
dcs_reg_write(rGLBTIMER_MDLLTIMER, 0x000bb8); // 3000
|
||||
dcs_reg_write(rGLBTIMER_MDLLVOLTRAMPTIMER, 0x00004b); // 75
|
||||
dcs_reg_write(rGLBTIMER_CTRLUPDMASKTIMER, 0x00000f); // 15
|
||||
// skip IDTTIMER setup per spec
|
||||
//dcs_reg_write(rGLBTIMER_IDTTIMER, 0x007530); // 30000
|
||||
dcs_reg_write(rGLBTIMER_RDCALTIMER, 0x2dc6c0); // 3000000
|
||||
dcs_reg_write(rGLBTIMER_WRCALTIMER, 0x2dc6c0); // 3000000
|
||||
|
||||
// <rdar://problem/23355941> Maui/Malta: Samsung DRAM workaround: disable hw zqcal
|
||||
if(! ((dev_info->vendor_id == JEDEC_LPDDR4_MANUF_ID_SAMSUNG) && (dev_info->rev_id == 5) && (dev_info->rev_id2 <= 1)) )
|
||||
dcs_reg_write(rGLBTIMER_ZQCTIMER, 0x3d0900); // 4000000
|
||||
|
||||
dcs_reg_write(rGLBTIMER_PERCAL_FREQCHNGTIMER, 0x0493e0); //
|
||||
dcs_reg_write(rGLBTIMER_VOLTRAMPTIMER, 0x0493e0); //
|
||||
dcs_reg_write(rGLBTIMER_IMPCALTIMER, 0x002ee0); // 12000
|
||||
|
||||
dcs_reg_write(rGLBTIMER_VOLTRAMP2ALLBANKDLY(0), 0x00d800d8);
|
||||
dcs_reg_write(rGLBTIMER_VOLTRAMP2ALLBANKDLY(1), 0x00d800d8);
|
||||
dcs_reg_write(rGLBTIMER_ALLBANK2PMGRACKDLY(0), 0x00900090);
|
||||
dcs_reg_write(rGLBTIMER_ALLBANK2PMGRACKDLY(1), 0x00900090);
|
||||
}
|
||||
// Dynamic Clk & Power Gating
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCLKPWRGATE, 0x050a0000);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 19: ODTS read & set interval for periodic MR4 on-die Temp sensor reading
|
||||
//================================================================================
|
||||
void dcs_init_ODTS(void)
|
||||
{
|
||||
uint8_t temp[16*8]; // Far more Channels/Ranks than we are likely ever to have/need
|
||||
// INSTEAD OF: uint8_t temp[dcs_cfg.num_dcs * dcs_cfg.num_rank];
|
||||
|
||||
// MR4 read to bring memory out of self-refresh
|
||||
dcs_mrcmd(MR_READ, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x4, (uintptr_t)temp);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc3);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
@@ -0,0 +1,26 @@
|
||||
# Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_DCS=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/dcs.o
|
||||
|
||||
ifeq ($(SUB_PLATFORM),s8000)
|
||||
ALL_OBJS += $(LOCAL_DIR)/dcs_init_lib_s8000.o
|
||||
else ifeq ($(SUB_PLATFORM),s8001)
|
||||
ALL_OBJS += $(LOCAL_DIR)/dcs_init_lib_s8001.o
|
||||
else ifeq ($(SUB_PLATFORM),s8003)
|
||||
ALL_OBJS += $(LOCAL_DIR)/dcs_init_lib_s8003.o
|
||||
else
|
||||
$(error "Unrecognized SUB_PLATFORM \"$(SUB_PLATFORM)\"")
|
||||
endif
|
||||
@@ -0,0 +1,121 @@
|
||||
/*
|
||||
* Copyright (C) 2011-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <platform.h>
|
||||
#include <platform/int.h>
|
||||
#include <platform/error_handler.h>
|
||||
#include <platform/soc/hwisr.h>
|
||||
#include <platform/soc/miu.h>
|
||||
#include SUB_PLATFORM_SPDS_HEADER(amcc)
|
||||
|
||||
#define rAMCC_INTEN(n) (*(volatile uint32_t *)(AMCC_BASE_ADDR(n) + AMCC_IRERRDBG_INTEN_OFFSET))
|
||||
#define rAMCC_INTSTATUS(n) (*(volatile uint32_t *)(AMCC_BASE_ADDR(n) + AMCC_IRERRDBG_INTSTS_OFFSET))
|
||||
#define rAMCC_MCCAFERRLOG2(n) (*(volatile uint32_t *)(AMCC_BASE_ADDR(n) + AMCC_IRERRDBG_MCC_AF_ERR_LOG2_OFFSET))
|
||||
|
||||
// Enables all errors (the remaining bits are perf counters)
|
||||
#define AMCC_IRERRDBG_INTEN_ALLERRORS ( AMCC_IRERRDBG_INTSTS_MCC_TP_PAR_ERR_UMASK \
|
||||
| AMCC_IRERRDBG_INTSTS_MCC_DAT_ONE_BIT_ERR_UMASK \
|
||||
| AMCC_IRERRDBG_INTSTS_MCC_DAT_MULTI_BITS_ERR_UMASK \
|
||||
| AMCC_IRERRDBG_INTSTS_MCC_SCE_CLR_DONE_UMASK \
|
||||
| AMCC_IRERRDBG_INTSTS_MCC_AF_ERR_UMASK \
|
||||
| AMCC_IRERRDBG_INTSTS_MCC_TP_MULTI_PAR_ERR_UMASK )
|
||||
|
||||
#define AMCC_INTSTATUS_ALLERRORS AMCC_IRERRDBG_INTEN_ALLERRORS
|
||||
|
||||
#define AMCC_IERRDBG_INTSTS_DRAM_ONE_BIT_ERR AMCC_IRERRDBG_INTSTS_MCC_DAT_ONE_BIT_ERR_UMASK
|
||||
#define AMCC_IERRDBG_INTSTS_DRAM_MULTI_BIT_ERR AMCC_IRERRDBG_INTSTS_MCC_DAT_MULTI_BITS_ERR_UMASK
|
||||
|
||||
#define AMCC_IRERRDBG_MCCAFERRLOG2_AGENT_IODAP (0x87)
|
||||
|
||||
#define CP_COM_NORM_MSK_CLR_ALL (0xFFFFFFFF)
|
||||
#define CP_COM_NORM_MSK_ILLEGAL_COH_INTS ((1<<0) | (1<<14))
|
||||
|
||||
static void amc_int_handler(void *arg)
|
||||
{
|
||||
uint32_t amcc = (uint32_t)(uintptr_t)arg;
|
||||
uint32_t intsts = rAMCC_INTSTATUS(amcc);
|
||||
|
||||
if ((intsts & (AMCC_IERRDBG_INTSTS_DRAM_ONE_BIT_ERR | AMCC_IERRDBG_INTSTS_DRAM_ONE_BIT_ERR)) == 0) {
|
||||
// Whitelist errors caused by the IODAP agent (Astris) since
|
||||
// these are most likely caused by user input errors.
|
||||
uint32_t agent_id = AMCC_IRERRDBG_MCC_AF_ERR_LOG2_MCC_AF_ERR_AID_LOG_XTRCT(rAMCC_MCCAFERRLOG2(amcc));
|
||||
if (agent_id == AMCC_IRERRDBG_MCCAFERRLOG2_AGENT_IODAP) {
|
||||
dprintf(DEBUG_INFO, "AMC error from IODAP (ignored): 0x%x\n", rAMCC_INTSTATUS(amcc));
|
||||
|
||||
// Clear the interrupt and continue on.
|
||||
rAMCC_INTSTATUS(amcc) = intsts;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
panic("Received unexpected AMC error. AMC_IERRDBG_INTSTATUS = 0x%lx\n", rAMCC_INTSTATUS(amcc));
|
||||
}
|
||||
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
static void cp_int_handler(void *arg __unused) {
|
||||
panic("Received unexpected Coherency Point error. CP_COM_INT_NORM_REQUEST = 0x%x\n", rCP_COM_INT_NORM_REQUEST);
|
||||
}
|
||||
#else
|
||||
static void cp_int_handler(void *arg) {
|
||||
panic("Received unexpected Coherency Point %d error. CP_COM_INT_NORM_REQUEST = 0x%x\n",
|
||||
(uint32_t)arg,
|
||||
(((uint32_t)arg) == 0) ? rCP0_COM_INT_NORM_REQUEST : rCP1_COM_INT_NORM_REQUEST);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void enable_cp_checks()
|
||||
{
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
install_int_handler(INT_COHERENCE_PNT_ERR, cp_int_handler, NULL);
|
||||
rCP_COM_INT_NORM_MASK_CLR = CP_COM_NORM_MSK_CLR_ALL;
|
||||
unmask_int(INT_COHERENCE_PNT_ERR);
|
||||
#elif SUB_PLATFORM_S8001
|
||||
install_int_handler(INT_COHERENCE_PNT0_ERR, cp_int_handler, (void*)0);
|
||||
rCP0_COM_INT_NORM_MASK_CLR = CP_COM_NORM_MSK_CLR_ALL;
|
||||
unmask_int(INT_COHERENCE_PNT0_ERR);
|
||||
|
||||
install_int_handler(INT_COHERENCE_PNT1_ERR, cp_int_handler, (void*)1);
|
||||
rCP1_COM_INT_NORM_MASK_CLR = CP_COM_NORM_MSK_CLR_ALL;
|
||||
unmask_int(INT_COHERENCE_PNT1_ERR);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void enable_amc_checks()
|
||||
{
|
||||
for (unsigned i = 0; i < NUM_AMCCS; i++) {
|
||||
uint32_t vector;
|
||||
#if NUM_AMCCS == 1
|
||||
vector = INT_MEM_CONTROLLER0;
|
||||
#elif NUM_AMCCS == 2
|
||||
// Amusingly enough, INT_MEM_CONTROLLER1 is the 1st interrupt of the
|
||||
// 2nd AMCC on Elba, but the 2nd interrupt of the first/only AMCC on Maui
|
||||
if (i == 0) vector = INT_MEM_CONTROLLER0;
|
||||
else vector = INT_MEM_CONTROLLER1;
|
||||
#else
|
||||
#error "Unsupported number of AMCCs"
|
||||
#endif
|
||||
install_int_handler(vector, amc_int_handler, (void *)(uintptr_t)i);
|
||||
rAMCC_INTEN(i) = AMCC_IRERRDBG_INTEN_ALLERRORS;
|
||||
if (rAMCC_INTSTATUS(i) & AMCC_INTSTATUS_ALLERRORS) {
|
||||
// AMC Interrupts, unlike the CP ones, don't seem to stick. If an error already exists
|
||||
// this early in bootup, we won't get an interrupt upon unmask.
|
||||
amc_int_handler((void *)(uintptr_t)i);
|
||||
}
|
||||
rAMCC_INTSTATUS(i) = AMCC_INTSTATUS_ALLERRORS;
|
||||
unmask_int(vector);
|
||||
}
|
||||
}
|
||||
|
||||
void platform_enable_error_handler() {
|
||||
enable_amc_checks();
|
||||
enable_cp_checks();
|
||||
}
|
||||
|
||||
@@ -0,0 +1,16 @@
|
||||
# Copyright (C) 2011-2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_PLATFORM_ERROR_HANDLER=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/error_handler.o
|
||||
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* Copyright (c) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef PLATFORM_APCIE_H
|
||||
#define PLATFORM_APCIE_H
|
||||
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
#define APCIE_LANE_CFG_X1_X1_X1_X1 (0)
|
||||
#define APCIE_LANE_CFG_X2_X1_X1 (1)
|
||||
#define APCIE_LANE_CFG_X2_X1_X2 (3)
|
||||
|
||||
#define APCIE_LANE_CONFIG_NVME0_X1 APCIE_LANE_CFG_X1_X1_X1_X1
|
||||
#define APCIE_LANE_CONFIG_NVME0_X2 APCIE_LANE_CFG_X2_X1_X1
|
||||
|
||||
#elif SUB_PLATFORM_S8001
|
||||
#define APCIE_LANE_CFG_X1_X1_X1_X1_X1_X1 (0)
|
||||
#define APCIE_LANE_CFG_X2_X1_X1_X1_X1 (1)
|
||||
#define APCIE_LANE_CFG_X1_X1_X2_X1_X1 (2)
|
||||
#define APCIE_LANE_CFG_X2_X2_X1_X1 (3)
|
||||
#define APCIE_LANE_CFG_X1_X1_X1_X1_X2 (4)
|
||||
#define APCIE_LANE_CFG_X2_X1_X1_X2 (5)
|
||||
#define APCIE_LANE_CFG_X1_X1_X2_X2 (6)
|
||||
#define APCIE_LANE_CFG_X2_X2_X2 (7)
|
||||
|
||||
#define APCIE_LANE_CONFIG_NVME0_X1 APCIE_LANE_CFG_X1_X1_X1_X1_X1_X1
|
||||
#define APCIE_LANE_CONFIG_NVME0_X2 APCIE_LANE_CFG_X2_X1_X1_X1_X1
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,60 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef _APCIE_REGS_H
|
||||
#define _APCIE_REGS_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define APCIE_COUNTER_PORT_STRIDE (0x40)
|
||||
#define APCIE_NUM_COUNTERS (8)
|
||||
|
||||
#define rAPCIE_COUNTER_VALUE(port, n) (*(volatile uint32_t *)(APCIE_COUNTER_BASE_ADDR + (port) * APCIE_COUNTER_PORT_STRIDE + (n) * 4))
|
||||
#define rAPCIE_COUNTER_COMMAND(port) (*(volatile uint32_t *)(APCIE_COUNTER_BASE_ADDR + (port) * APCIE_COUNTER_PORT_STRIDE + 0x20))
|
||||
|
||||
#define APCIE_COUNTER_ENABLE (1)
|
||||
#define APCIE_COUNTER_CLEAR (2)
|
||||
#define APCIE_COUNTER_CAPTURE (4)
|
||||
|
||||
#define APCIE_PORT_BASE_ADDR(port) (APCIE_CONFIG_BASE_ADDR + APCIE_CONFIG_PORT_STRIDE * (port))
|
||||
#define PCIE_PORT_BASE_ADDR(port) (PCI_CONFIG_BASE + ((port) << PCI_DEVICE_SHIFT))
|
||||
|
||||
#define rAPCIE_CONFIG_LINKCFG(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x080))
|
||||
#define rAPCIE_CONFIG_LINKCTRL(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x084))
|
||||
#define rAPCIE_CONFIG_LINKSTS(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x088))
|
||||
#define rAPCIE_CONFIG_PMETO(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x08c))
|
||||
#define rAPCIE_CONFIG_PMETOACK_TMOTLIM(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x090))
|
||||
|
||||
#define rAPCIE_CONFIG_INBCTRL(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x130))
|
||||
#define rAPCIE_CONFIG_OUTBCTRL(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x134))
|
||||
#define rAPCIE_CONFIG_LINKPMGRSTS(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x804))
|
||||
#define rAPCIE_CONFIG_LINKCDMSTS(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x808))
|
||||
|
||||
#define APCIE_CONFIG_LINKCFG_LTSSM_EN (1 << 0)
|
||||
#define APCIE_CONFIG_LINKSTS_LINK_STATUS (1 << 0)
|
||||
#define APCIE_CONFIG_LINKSTS_CORE_RST_PEND (1 << 1)
|
||||
#define APCIE_CONFIG_LINKSTS_PIPE_CLK_ACTIVE (1 << 2)
|
||||
#define APCIE_CONFIG_LINKSTS_CLKREQ_N (1 << 3)
|
||||
#define APCIE_CONFIG_LINKSTS_L1_STATE (1 << 4)
|
||||
#define APCIE_CONFIG_LINKSTS_L1_SUBSTATE (1 << 5)
|
||||
#define APCIE_CONFIG_LINKSTS_L2_STATE (1 << 6)
|
||||
|
||||
#define APCIE_CONFIG_INBCTRL_CPL_MUST_PUSH_EN (1 << 1)
|
||||
#define APCIE_CONFIG_OUTBCTRL_EARLY_PT_RESP_EN (1 << 0)
|
||||
|
||||
#define rAPCIE_CONFIG_SPACE8(port, offset) (*(volatile uint8_t *)(PCIE_PORT_BASE_ADDR(port) + (offset)))
|
||||
#define rAPCIE_CONFIG_SPACE16(port, offset) (*(volatile uint16_t *)(PCIE_PORT_BASE_ADDR(port) + (offset)))
|
||||
#define rAPCIE_CONFIG_SPACE32(port, offset) (*(volatile uint32_t *)(PCIE_PORT_BASE_ADDR(port) + (offset)))
|
||||
|
||||
#define rAPCIE_PCIE_CAP_LINK_CONTROL2(port) rAPCIE_CONFIG_SPACE16(port, 0xa0)
|
||||
#define rAPCIE_PORT_LOGIC_PORT_LINK_CTRL(port) rAPCIE_CONFIG_SPACE32(port, 0x710)
|
||||
#define rAPCIE_PORT_LOGIC_GEN2_CTRL(port) rAPCIE_CONFIG_SPACE32(port, 0x80c)
|
||||
|
||||
#endif /* _APCIE_REGS_H */
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __DCSCONFIG_H
|
||||
#define __DCSCONFIG_H
|
||||
|
||||
// Needful defnitions for the initializers below
|
||||
#include <drivers/dcs/dcs.h>
|
||||
#include <drivers/dcs/dcs_regs.h>
|
||||
#include <drivers/dcs/dcs_init_lib.h>
|
||||
#include <drivers/dcs/dcs_calibration.h>
|
||||
|
||||
#include SUB_PLATFORM_HEADER(dcsconfig)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,653 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __DCSCONFIG_S8000_H
|
||||
#define __DCSCONFIG_S8000_H
|
||||
|
||||
// Macros for tunables
|
||||
#define BIT32_MASKFULL (0xFFFFFFFF)
|
||||
#define BIT32_MASK(_n) (BIT32_MASKFULL >> (32 - (_n)))
|
||||
#define BIT32_MASK_VAL(_h,_l,_d) (((_d) & BIT32_MASK((_h) - (_l) + 1)) << (_l))
|
||||
#define BIT32_MASK_HI_LO(_h,_l) BIT32_MASK_VAL(_h,_l,BIT32_MASKFULL)
|
||||
#define DCS_MASK_VAL(_h,_l,_d) BIT32_MASK_HI_LO(_h,_l) , BIT32_MASK_VAL(_h,_l,_d)
|
||||
|
||||
// Maui C0 dcs param table
|
||||
dcs_config_params_t dcs_params = {
|
||||
.supported_freqs = DCS_FREQ(0) | DCS_FREQ(1) | DCS_FREQ(3),
|
||||
.num_freqchngctl_regs = 5,
|
||||
.spllctrl_vco_1 = 0x00000076,
|
||||
.spllctrl_vco_2 = 0x00000078,
|
||||
.dllupdtctrl = 0x50017350,
|
||||
.modereg = 0x140a90b4,
|
||||
.autoref_params = 0x0015005d,
|
||||
.pdn = 0x62265295,
|
||||
.rnkcfg = 0x00006061,
|
||||
.cackcswkds = 0x000000db,
|
||||
.dqspdres = 0x00000031,
|
||||
.casdllupdatectrl = 0x0303030b,
|
||||
.dqsdllupdatectrl = 0x0003000b,
|
||||
.rdsdllctrl_step2 = 0x00ff0004,
|
||||
.wrdqdqssdllctrl_step2 = 0xff000004,
|
||||
.cawrlvlsdllcode = 0x00ff02ff,
|
||||
.dlllocktim = 0x012c012c,
|
||||
.dficaltiming = 0x04000410,
|
||||
.rdwrdqcaltiming_f0 = 0x00001426,
|
||||
.rdwrdqcalseglen_f0 = 0x00010002,
|
||||
.rdwrdqcaltiming_f1 = 0x00001422,
|
||||
.rdwrdqcalseglen_f1 = 0x00010002,
|
||||
.rdwrdqcaltimingctrl1 = 0x0000301e,
|
||||
.rdwrdqcaltimingctrl2 = 0x03111004,
|
||||
.rddqcalpatprbs4i = 0x55555e26,
|
||||
.wrdqcalpatprbs4i = 0x55555e26,
|
||||
.maxwrdqssdllmulfactor = 0xa0a0080c,
|
||||
.dllupdtctrl1 = 0x50017550,
|
||||
.dllupdtintvl = 0x10200020,
|
||||
.arefparam = 0x08010019,
|
||||
.autoref_params2 = 0x0017005d,
|
||||
.odtszqc = 0x00001000,
|
||||
.longsr = 0x01012008,
|
||||
.freqchngctl_step3 = 0x00010000,
|
||||
.mr3cmd = 0xf3,
|
||||
.mr13cmd = 0x18,
|
||||
.addrcfg = 0x00030201,
|
||||
.chnldec = 0x00050220,
|
||||
.mr13cmd_step7 = 0x58,
|
||||
.mr3cmd_step7 = 0xf3,
|
||||
.mr22cmd = 0x04,
|
||||
.mr11cmd = 0x02,
|
||||
.mr13cmd_step9 = 0xd8,
|
||||
.freqchngctl_step9 = 0x00010000,
|
||||
.mr13cmd_step11 = 0x98,
|
||||
.mr2cmd_step11 = 0x24,
|
||||
.mr1cmd_step11 = 0xce,
|
||||
.mr3cmd_step11 = 0xb3,
|
||||
.mr22cmd_step11 = 0x04,
|
||||
.mr11cmd_step11 = 0x44,
|
||||
.mr12cmd_step11 = 0x11,
|
||||
.mr14cmd_step11 = 0x11,
|
||||
.mr13cmd_step13 = 0x18,
|
||||
.mr13cmd_step15 = 0x50,
|
||||
.freqchngctl_step15 = 0x00009999,
|
||||
.rdsdllctrl_step15 = 0x00150004,
|
||||
.odtszqc2 = 0xc0001000,
|
||||
.qbren_step16 = 0x0000000d,
|
||||
.qbrparam = 0x000061a5,
|
||||
.qbren = 0x0000000f,
|
||||
.mccgen = 0x00000126,
|
||||
.caampclk = 0x00000000,
|
||||
.dqampclk = 0x00000000,
|
||||
.pwrmngten = 0x00000133,
|
||||
.odtszqc3 = 0xc0003320,
|
||||
|
||||
.freq = {
|
||||
{ // 1200MHz
|
||||
.clk_period = CLK_PERIOD_1200,
|
||||
.freqchngctl = {0x18cd104d, 0x110c110e, 0xb303440b, 0xce012402, 0x00000416},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.lat = 0x00103306,
|
||||
.phyrdwrtim = 0x00050c0a,
|
||||
.caspch = 0x531a060b,
|
||||
.act = 0x18060d0b,
|
||||
.autoref = 0x366c0078,
|
||||
.selfref = 0x78071012,
|
||||
.derate = 0x38c486cc,
|
||||
.lat2 = 0x00113306,
|
||||
.tat = 0x01312222,
|
||||
.mifqmaxctrl = 0x00000100,
|
||||
.nondqdspd = 0x000b316b,
|
||||
.cavref = 0x00000003,
|
||||
.odt_enable = 0x00000001,
|
||||
.dqds = 0x000c0b08,
|
||||
.dqdqsds = 0x00030b08,
|
||||
.dqvref = 0x00c000c0,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.rddqcalwindow = 0x00aa01d1,
|
||||
.wrdqcalwindow = 0x00ca0160,
|
||||
.caoutdllscl = 0x00000008,
|
||||
.dqsindllscl = 0x00000008,
|
||||
.rdcapcfg = 0x0100070d,
|
||||
.autoref2 = 0x366c006e,
|
||||
},
|
||||
{ // 800MHz
|
||||
.clk_period = CLK_PERIOD_800,
|
||||
.freqchngctl = {0x18cd104d, 0x110c110e, 0xf303020b, 0xae015202, 0x00000416},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.lat = 0x00102206,
|
||||
.phyrdwrtim = 0x00050b06,
|
||||
.caspch = 0x42110408,
|
||||
.act = 0x10040908,
|
||||
.autoref = 0x24480050,
|
||||
.selfref = 0x5004b012,
|
||||
.derate = 0x28835488,
|
||||
.lat2 = 0x00112206,
|
||||
.tat = 0x01312222,
|
||||
.nondqdspd = 0x000b216b,
|
||||
.nondqds = 0x00000000,
|
||||
.cavref = 0x00000003,
|
||||
.odt_enable = 0x00000000,
|
||||
.dqds = 0x00080b00,
|
||||
.dqdqsds = 0x00010b00,
|
||||
.dqvref = 0x00df00df,
|
||||
.cadficaltiming = 0x04000410,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.rddqcalwindow = 0x00aa01d1,
|
||||
.wrdqcalwindow = 0x00ca0160,
|
||||
#ifdef TARGET_DDR_800M
|
||||
.caoutdllscl = 0x0000000c,
|
||||
.dqsindllscl = 0x0000000c,
|
||||
#else
|
||||
.caoutdllscl = 0x0000000d,
|
||||
.dqsindllscl = 0x0000000d,
|
||||
#endif
|
||||
.rdcapcfg = 0x2100060a,
|
||||
.autoref2 = 0x24480049,
|
||||
},
|
||||
{ // 200MHz
|
||||
.freqchngctl = {0x18cd104d, 0x590c590e, 0xf303000b, 0x8e010002, 0x00000016},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.phyrdwrtim = 0x00010b01,
|
||||
.caspch = 0x40c50402,
|
||||
.act = 0x04020302,
|
||||
.autoref = 0x09120014,
|
||||
.selfref = 0x28013012,
|
||||
.derate = 0x0c212142,
|
||||
.lat2 = 0x001110c2,
|
||||
.tat = 0x01212222,
|
||||
.nondqdspd = 0x000b3d6b,
|
||||
.nondqds = 0x00083d08,
|
||||
.cavref = 0x00000003,
|
||||
.dqds = 0x00080b00,
|
||||
.dqdqsds = 0x00080b00,
|
||||
.dqvref = 0x00000000,
|
||||
.cadficaltiming = 0x04000410,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.caoutdllscl = 0x00000030,
|
||||
.dqsindllscl = 0x00000030,
|
||||
.rdcapcfg = 0x41000406,
|
||||
.autoref2 = 0x09120013,
|
||||
},
|
||||
{ // 50MHz
|
||||
.freqchngctl = {0x18cd104d, 0x590c590e, 0xf303000b, 0x8e010002, 0x00000016},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.phyrdwrtim = 0x00010901,
|
||||
.caspch = 0x40c20402,
|
||||
.act = 0x02020404,
|
||||
.autoref = 0x03050005,
|
||||
.selfref = 0x28006012,
|
||||
.derate = 0x10412082,
|
||||
.lat2 = 0x001110c2,
|
||||
.tat = 0x01212222,
|
||||
.mifqmaxctrl = 0x00000001,
|
||||
.nondqdspd = 0x000b3d6b,
|
||||
.nondqds = 0x00083d08,
|
||||
.cavref = 0x00000003,
|
||||
.odt_enable = 0x00000000,
|
||||
.dqds = 0x00080b00,
|
||||
.dqdqsds = 0x00080b00,
|
||||
.dqvref = 0x00000000,
|
||||
.cadficaltiming = 0x04000410,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.caoutdllscl = 0x0000003f,
|
||||
.dqsindllscl = 0x0000003f,
|
||||
.rdcapcfg = 0x61000406,
|
||||
.autoref2 = 0x03050005,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
// DCS Tunables for s8000 C0
|
||||
// Tunables Spec versions:
|
||||
// MCU: https://seg-docs.ecs.apple.com/projects/maui//release/UserManual/tunables_b0/MCU.html dated 2015/06/13 10:26:02
|
||||
// AMPSCA: https://seg-docs.ecs.apple.com/projects/maui//release/UserManual/tunables_b0/AMPSCA.html dated 2015/05/14 16:66:34
|
||||
// Notes:
|
||||
// All 4 channels are tuned in exactly the same way
|
||||
// Registers with all fields' tunable values matching the reset value omitted
|
||||
const dcs_tunable_t dcs_tunables[] = {
|
||||
// AMC Clk
|
||||
{ rDCS_MCU_AMCCLKPWRGATE, DCS_MASK_VAL(12, 12, 0x0) },
|
||||
{ rDCS_MCU_AMCCLKPWRGATE, DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
|
||||
// PSQ RQ (Part I)
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(31, 24, 0xFF) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(20, 20, 0x0) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(16, 16, 0x1) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(12, 12, 0x0) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL( 4, 4, 0x1) },
|
||||
|
||||
// PSQ Freq 0
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(0), DCS_MASK_VAL(29, 16, 0x3f4b) },
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(0), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(0), DCS_MASK_VAL( 8, 0, 0x0B4) },
|
||||
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(0), DCS_MASK_VAL(29, 16, 0x3f4b) },
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(0), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(0), DCS_MASK_VAL( 8, 0, 0x0B4) },
|
||||
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(0), DCS_MASK_VAL(29, 16, 0x3f4b) },
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(0), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(0), DCS_MASK_VAL( 8, 0, 0x0B4) },
|
||||
|
||||
// PSQ Freq 1
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(1), DCS_MASK_VAL(29, 16, 0x3f87) },
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(1), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(1), DCS_MASK_VAL( 8, 0, 0x078) },
|
||||
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(1), DCS_MASK_VAL(29, 16, 0x3f87) },
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(1), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(1), DCS_MASK_VAL( 8, 0, 0x078) },
|
||||
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(1), DCS_MASK_VAL(29, 16, 0x3f87) },
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(1), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(1), DCS_MASK_VAL( 8, 0, 0x078) },
|
||||
|
||||
// PSQ RQ (Part II)
|
||||
{ rDCS_MCU_PSQRQTIMER0, DCS_MASK_VAL(27, 16, 0x014) },
|
||||
{ rDCS_MCU_PSQRQTIMER0, DCS_MASK_VAL(11, 0, 0x040) },
|
||||
|
||||
{ rDCS_MCU_PSQRQTIMER1, DCS_MASK_VAL(27, 16, 0x00F) },
|
||||
{ rDCS_MCU_PSQRQTIMER1, DCS_MASK_VAL(11, 0, 0x040) },
|
||||
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL(28, 24, 0x04) },
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL(20, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL(12, 8, 0x04) },
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL( 4, 0, 0x10) },
|
||||
|
||||
{ rDCS_MCU_PSQRQSCHCRD, DCS_MASK_VAL(23, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQRQSCHCRD, DCS_MASK_VAL(15, 8, 0x14) },
|
||||
{ rDCS_MCU_PSQRQSCHCRD, DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
// PSQ WQ
|
||||
{ rDCS_MCU_PSQWQ_CTL(0), DCS_MASK_VAL(16, 16, 0x1) },
|
||||
{ rDCS_MCU_PSQWQ_CTL(0), DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
|
||||
// part of init sequence, so have to apply tunables even if same as reset values
|
||||
#if DISPLAY_D620_TUNABLES
|
||||
{ rDCS_MCU_PSQWQ_CTL(1), DCS_MASK_VAL(31, 16, 0x0944) },
|
||||
#else
|
||||
{ rDCS_MCU_PSQWQ_CTL(1), DCS_MASK_VAL(31, 16, 0x0494) },
|
||||
#endif
|
||||
{ rDCS_MCU_PSQWQ_CTL(1), DCS_MASK_VAL(15, 0, 0x0224) },
|
||||
|
||||
{ rDCS_MCU_PSQWQ_CTL(2), DCS_MASK_VAL(31, 16, 0x002B) },
|
||||
{ rDCS_MCU_PSQWQ_CTL(2), DCS_MASK_VAL(15, 0, 0x0158) },
|
||||
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL(28, 24, 0x04) },
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL(20, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL(12, 8, 0x04) },
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL( 4, 0, 0x10) },
|
||||
|
||||
{ rDCS_MCU_PSQWQSCHCRD, DCS_MASK_VAL(23, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQWQSCHCRD, DCS_MASK_VAL(15, 8, 0x14) },
|
||||
{ rDCS_MCU_PSQWQSCHCRD, DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
// QoS
|
||||
{ rDCS_MCU_QOSLLT, DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
{ rDCS_MCU_QOSLLT, DCS_MASK_VAL( 4, 0, 0x1F) },
|
||||
|
||||
{ rDCS_MCU_SBQOSUPGCTL, DCS_MASK_VAL(31, 31, 0x1) },
|
||||
{ rDCS_MCU_SBQOSUPGCTL, DCS_MASK_VAL( 7, 0, 0x6E) },
|
||||
|
||||
// DRAM Cfg
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(0), DCS_MASK_VAL(31, 16, 0x0240) },
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(0), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
#if DISPLAY_D620_TUNABLES
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(1), DCS_MASK_VAL(31, 16, 0x0960) },
|
||||
#else
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(1), DCS_MASK_VAL(31, 16, 0x04b0) },
|
||||
#endif
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(1), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(2), DCS_MASK_VAL(31, 16, 0x0180) },
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(2), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(3), DCS_MASK_VAL(31, 16, 0x0030) },
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(3), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_ROWHAM_CTL(0), DCS_MASK_VAL(31, 16, 0x4002) },
|
||||
{ rDCS_MCU_ROWHAM_CTL(0), DCS_MASK_VAL( 0, 0, 0x0) },
|
||||
|
||||
{ rDCS_MCU_ROWHAM_CTL(1), DCS_MASK_VAL(31, 16, 0x4a38) },
|
||||
{ rDCS_MCU_ROWHAM_CTL(1), DCS_MASK_VAL(15, 0, 0x22d5) },
|
||||
|
||||
{ rDCS_MCU_ROWHAM_CTL(2), DCS_MASK_VAL(15, 0, 0x4a33) },
|
||||
|
||||
// AMP
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(0), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(0), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(1), DCS_MASK_VAL(31, 16, 0x1) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(1), DCS_MASK_VAL(15, 0, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(2), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(2), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(3), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(3), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
// Alternate End Marker
|
||||
// { 0, 0, 0 }
|
||||
};
|
||||
|
||||
// Maui B0 dcs param table
|
||||
dcs_config_params_t dcs_params_b0 = {
|
||||
.supported_freqs = DCS_FREQ(0) | DCS_FREQ(1) | DCS_FREQ(3),
|
||||
.num_freqchngctl_regs = 5,
|
||||
.spllctrl_vco_1 = 0x00000076,
|
||||
.spllctrl_vco_2 = 0x00000078,
|
||||
.rwcfg = 0x000210ef,
|
||||
.dllupdtctrl = 0x50017350,
|
||||
.modereg = 0x140a90b4,
|
||||
.autoref_params = 0x0015005d,
|
||||
.pdn = 0x62265295,
|
||||
.rnkcfg = 0x00006061,
|
||||
.cackcswkds = 0x000000db,
|
||||
.dqspdres = 0x00000031,
|
||||
.casdllupdatectrl = 0x0303030b,
|
||||
.dqsdllupdatectrl = 0x0003000b,
|
||||
.rdsdllctrl_step2 = 0x00ff0004,
|
||||
.wrdqdqssdllctrl_step2 = 0xff000004,
|
||||
.cawrlvlsdllcode = 0x00ff02ff,
|
||||
.dlllocktim = 0x012c012c,
|
||||
.dficaltiming = 0x04000410,
|
||||
.rdwrdqcaltiming_f0 = 0x00001426,
|
||||
.rdwrdqcalseglen_f0 = 0x00010002,
|
||||
.rdwrdqcaltiming_f1 = 0x00001422,
|
||||
.rdwrdqcalseglen_f1 = 0x00010002,
|
||||
.rdwrdqcaltimingctrl1 = 0x0000301e,
|
||||
.rdwrdqcaltimingctrl2 = 0x03111004,
|
||||
.rddqcalpatprbs4i = 0x55555e26,
|
||||
.wrdqcalpatprbs4i = 0x55555e26,
|
||||
.maxwrdqssdllmulfactor = 0xa0a0080c,
|
||||
.dllupdtctrl1 = 0x50017550,
|
||||
.dllupdtintvl = 0x10200020,
|
||||
.arefparam = 0x0d010019,
|
||||
.autoref_params2 = 0x0017005d,
|
||||
.odtszqc = 0x00001000,
|
||||
.longsr = 0x01022008,
|
||||
.freqchngctl_step3 = 0x00010000,
|
||||
.mr3cmd = 0xf3,
|
||||
.mr13cmd = 0x18,
|
||||
.addrcfg = 0x00030201,
|
||||
.chnldec = 0x00050220,
|
||||
.mr13cmd_step7 = 0x58,
|
||||
.mr3cmd_step7 = 0xf3,
|
||||
.mr22cmd = 0x04,
|
||||
.mr11cmd = 0x02,
|
||||
.mr13cmd_step9 = 0xd8,
|
||||
.freqchngctl_step9 = 0x00010000,
|
||||
.mr13cmd_step11 = 0x98,
|
||||
.mr2cmd_step11 = 0x24,
|
||||
.mr1cmd_step11 = 0xce,
|
||||
.mr3cmd_step11 = 0xb3,
|
||||
.mr22cmd_step11 = 0x04,
|
||||
.mr11cmd_step11 = 0x44,
|
||||
.mr12cmd_step11 = 0x11,
|
||||
.mr14cmd_step11 = 0x11,
|
||||
.mr13cmd_step13 = 0x18,
|
||||
.mr13cmd_step15 = 0x50,
|
||||
.freqchngctl_step15 = 0x00009999,
|
||||
.rdsdllctrl_step15 = 0x00150004,
|
||||
.odtszqc2 = 0xc0001000,
|
||||
.qbren_step16 = 0x0000000d,
|
||||
.qbrparam = 0x000061a5,
|
||||
.qbren = 0x0000000f,
|
||||
.mccgen = 0x00000126,
|
||||
.caampclk = 0x00000000,
|
||||
.dqampclk = 0x00000000,
|
||||
.pwrmngten = 0x00000133,
|
||||
.odtszqc3 = 0xc0003320,
|
||||
|
||||
.freq = {
|
||||
{ // 1200MHz
|
||||
.clk_period = CLK_PERIOD_1200,
|
||||
.freqchngctl = {0x18cd104d, 0x110c110e, 0xb303440b, 0xce012402, 0x00000416},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.lat = 0x00103306,
|
||||
.phyrdwrtim = 0x00050c0a,
|
||||
.caspch = 0x531a060b,
|
||||
.act = 0x18060d0b,
|
||||
.autoref = 0x366c0078,
|
||||
.selfref = 0x78071012,
|
||||
.derate = 0x38c486cc,
|
||||
.lat2 = 0x00113306,
|
||||
.tat = 0x01312222,
|
||||
.mifqmaxctrl = 0x00000100,
|
||||
.nondqdspd = 0x000b316b,
|
||||
.cavref = 0x00000003,
|
||||
.odt_enable = 0x00000001,
|
||||
.dqds = 0x000c0b08,
|
||||
.dqdqsds = 0x00030b08,
|
||||
.dqvref = 0x00c000c0,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.rddqcalwindow = 0x00aa01d1,
|
||||
.wrdqcalwindow = 0x00ca0160,
|
||||
.caoutdllscl = 0x00000008,
|
||||
.dqsindllscl = 0x00000008,
|
||||
.rdcapcfg = 0x0100070d,
|
||||
.autoref2 = 0x366c006e,
|
||||
},
|
||||
{ // 800MHz
|
||||
.clk_period = CLK_PERIOD_800,
|
||||
.freqchngctl = {0x18cd104d, 0x110c110e, 0xf303020b, 0xae015202, 0x00000416},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.lat = 0x00102206,
|
||||
.phyrdwrtim = 0x00050b06,
|
||||
.caspch = 0x42110408,
|
||||
.act = 0x10040908,
|
||||
.autoref = 0x24480050,
|
||||
.selfref = 0x5004b012,
|
||||
.derate = 0x28835488,
|
||||
.lat2 = 0x00112206,
|
||||
.tat = 0x01312222,
|
||||
.nondqdspd = 0x000b216b,
|
||||
.nondqds = 0x00000000,
|
||||
.cavref = 0x00000003,
|
||||
.odt_enable = 0x00000000,
|
||||
.dqds = 0x00080b00,
|
||||
.dqdqsds = 0x00010b00,
|
||||
.dqvref = 0x00df00df,
|
||||
.cadficaltiming = 0x04000410,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.rddqcalwindow = 0x00aa01d1,
|
||||
.wrdqcalwindow = 0x00ca0160,
|
||||
#ifdef TARGET_DDR_800M
|
||||
.caoutdllscl = 0x0000000c,
|
||||
.dqsindllscl = 0x0000000c,
|
||||
#else
|
||||
.caoutdllscl = 0x0000000d,
|
||||
.dqsindllscl = 0x0000000d,
|
||||
#endif
|
||||
.rdcapcfg = 0x2100060a,
|
||||
.autoref2 = 0x24480049,
|
||||
},
|
||||
{ // 200MHz
|
||||
.freqchngctl = {0x18cd104d, 0x590c590e, 0xf303000b, 0x8e010002, 0x00000016},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.phyrdwrtim = 0x00010b01,
|
||||
.caspch = 0x40c50402,
|
||||
.act = 0x04020302,
|
||||
.autoref = 0x09120014,
|
||||
.selfref = 0x28013012,
|
||||
.derate = 0x0c212142,
|
||||
.lat2 = 0x001110c2,
|
||||
.tat = 0x01212222,
|
||||
.nondqdspd = 0x000b3d6b,
|
||||
.nondqds = 0x00083d08,
|
||||
.cavref = 0x00000003,
|
||||
.dqds = 0x00080b00,
|
||||
.dqdqsds = 0x00080b00,
|
||||
.dqvref = 0x00000000,
|
||||
.cadficaltiming = 0x04000410,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.caoutdllscl = 0x00000030,
|
||||
.dqsindllscl = 0x00000030,
|
||||
.rdcapcfg = 0x41000406,
|
||||
.autoref2 = 0x09120013,
|
||||
},
|
||||
{ // 50MHz
|
||||
.freqchngctl = {0x18cd104d, 0x590c590e, 0xf303000b, 0x8e010002, 0x00000016},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.phyrdwrtim = 0x00010901,
|
||||
.caspch = 0x40c20402,
|
||||
.act = 0x02020404,
|
||||
.autoref = 0x03050005,
|
||||
.selfref = 0x28006012,
|
||||
.derate = 0x10412082,
|
||||
.lat2 = 0x001110c2,
|
||||
.tat = 0x01212222,
|
||||
.mifqmaxctrl = 0x00000001,
|
||||
.nondqdspd = 0x000b3d6b,
|
||||
.nondqds = 0x00083d08,
|
||||
.cavref = 0x00000003,
|
||||
.odt_enable = 0x00000000,
|
||||
.dqds = 0x00080b00,
|
||||
.dqdqsds = 0x00080b00,
|
||||
.dqvref = 0x00000000,
|
||||
.cadficaltiming = 0x04000410,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.caoutdllscl = 0x0000003f,
|
||||
.dqsindllscl = 0x0000003f,
|
||||
.rdcapcfg = 0x61000406,
|
||||
.autoref2 = 0x03050005,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
// DCS Tunables for s8000 B0
|
||||
// Tunables Spec versions:
|
||||
// MCU: https://seg-docs.ecs.apple.com/projects/maui//release/UserManual/tunables_b0/MCU.html dated 2015/06/09 22:44:29
|
||||
// AMPSCA: https://seg-docs.ecs.apple.com/projects/maui//release/UserManual/tunables_b0/AMPSCA.html dated 2014/11/07 14:45:21
|
||||
// Notes:
|
||||
// All 4 channels are tuned in exactly the same way
|
||||
// Registers with all fields' tunable values matching the reset value omitted
|
||||
const dcs_tunable_t dcs_tunables_b0[] = {
|
||||
// AMC Clk
|
||||
{ rDCS_MCU_AMCCLKPWRGATE, DCS_MASK_VAL(12, 12, 0x0) },
|
||||
{ rDCS_MCU_AMCCLKPWRGATE, DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
|
||||
// PSQ RQ (Part I)
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(31, 24, 0xFF) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(20, 20, 0x0) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(16, 16, 0x1) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(12, 12, 0x0) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL( 8, 8, 0x0) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL( 4, 4, 0x0) },
|
||||
|
||||
// PSQ Freq 0
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(0), DCS_MASK_VAL(29, 16, 0x0) },
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(0), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(0), DCS_MASK_VAL( 8, 0, 0x0B4) },
|
||||
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(0), DCS_MASK_VAL(29, 16, 0x0) },
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(0), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(0), DCS_MASK_VAL( 8, 0, 0x0B4) },
|
||||
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(0), DCS_MASK_VAL(29, 16, 0x0) },
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(0), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(0), DCS_MASK_VAL( 8, 0, 0x0B4) },
|
||||
|
||||
// PSQ Freq 1
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(1), DCS_MASK_VAL(29, 16, 0x0) },
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(1), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(1), DCS_MASK_VAL( 8, 0, 0x078) },
|
||||
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(1), DCS_MASK_VAL(29, 16, 0x0) },
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(1), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(1), DCS_MASK_VAL( 8, 0, 0x078) },
|
||||
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(1), DCS_MASK_VAL(29, 16, 0x0) },
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(1), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(1), DCS_MASK_VAL( 8, 0, 0x078) },
|
||||
|
||||
// PSQ RQ (Part II)
|
||||
{ rDCS_MCU_PSQRQTIMER0, DCS_MASK_VAL(27, 16, 0x014) },
|
||||
{ rDCS_MCU_PSQRQTIMER0, DCS_MASK_VAL(11, 0, 0x040) },
|
||||
|
||||
{ rDCS_MCU_PSQRQTIMER1, DCS_MASK_VAL(27, 16, 0x00F) },
|
||||
{ rDCS_MCU_PSQRQTIMER1, DCS_MASK_VAL(11, 0, 0x040) },
|
||||
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL(28, 24, 0x04) },
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL(20, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL(12, 8, 0x04) },
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL( 4, 0, 0x10) },
|
||||
|
||||
{ rDCS_MCU_PSQRQSCHCRD, DCS_MASK_VAL(23, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQRQSCHCRD, DCS_MASK_VAL(15, 8, 0x14) },
|
||||
{ rDCS_MCU_PSQRQSCHCRD, DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
// PSQ WQ
|
||||
{ rDCS_MCU_PSQWQ_CTL(0), DCS_MASK_VAL(16, 16, 0x1) },
|
||||
{ rDCS_MCU_PSQWQ_CTL(0), DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
|
||||
// part of init sequence, so have to apply tunables even if same as reset values
|
||||
#if DISPLAY_D620_TUNABLES
|
||||
{ rDCS_MCU_PSQWQ_CTL(1), DCS_MASK_VAL(31, 16, 0x0944) },
|
||||
#else
|
||||
{ rDCS_MCU_PSQWQ_CTL(1), DCS_MASK_VAL(31, 16, 0x0494) },
|
||||
#endif
|
||||
{ rDCS_MCU_PSQWQ_CTL(1), DCS_MASK_VAL(15, 0, 0x0224) },
|
||||
|
||||
{ rDCS_MCU_PSQWQ_CTL(2), DCS_MASK_VAL(31, 16, 0x002B) },
|
||||
{ rDCS_MCU_PSQWQ_CTL(2), DCS_MASK_VAL(15, 0, 0x0158) },
|
||||
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL(28, 24, 0x04) },
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL(20, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL(12, 8, 0x04) },
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL( 4, 0, 0x10) },
|
||||
|
||||
{ rDCS_MCU_PSQWQSCHCRD, DCS_MASK_VAL(23, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQWQSCHCRD, DCS_MASK_VAL(15, 8, 0x14) },
|
||||
{ rDCS_MCU_PSQWQSCHCRD, DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
// QoS
|
||||
{ rDCS_MCU_QOSLLT, DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
{ rDCS_MCU_QOSLLT, DCS_MASK_VAL( 4, 0, 0x1F) },
|
||||
|
||||
{ rDCS_MCU_SBQOSUPGCTL, DCS_MASK_VAL(31, 31, 0x1) },
|
||||
{ rDCS_MCU_SBQOSUPGCTL, DCS_MASK_VAL( 7, 0, 0x6E) },
|
||||
|
||||
// DRAM Cfg
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(0), DCS_MASK_VAL(31, 16, 0x0240) },
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(0), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
#if DISPLAY_D620_TUNABLES
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(1), DCS_MASK_VAL(31, 16, 0x0960) },
|
||||
#else
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(1), DCS_MASK_VAL(31, 16, 0x04b0) },
|
||||
#endif
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(1), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(2), DCS_MASK_VAL(31, 16, 0x0180) },
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(2), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(3), DCS_MASK_VAL(31, 16, 0x0030) },
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(3), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_ROWHAM_CTL(0), DCS_MASK_VAL(31, 16, 0x4002) },
|
||||
{ rDCS_MCU_ROWHAM_CTL(0), DCS_MASK_VAL( 0, 0, 0x0) },
|
||||
|
||||
{ rDCS_MCU_ROWHAM_CTL(1), DCS_MASK_VAL(31, 16, 0x4a38) },
|
||||
{ rDCS_MCU_ROWHAM_CTL(1), DCS_MASK_VAL(15, 0, 0x22d4) },
|
||||
|
||||
{ rDCS_MCU_ROWHAM_CTL(2), DCS_MASK_VAL(15, 0, 0x4a33) },
|
||||
|
||||
// AMP
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(0), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(0), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(1), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(1), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(2), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(2), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(3), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(3), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
// Alternate End Marker
|
||||
// { 0, 0, 0 }
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,298 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __DCSCONFIG_S8001_H
|
||||
#define __DCSCONFIG_S8001_H
|
||||
|
||||
dcs_config_params_t dcs_params = {
|
||||
.supported_freqs = DCS_FREQ(0) | DCS_FREQ(3),
|
||||
.num_freqchngctl_regs = 5,
|
||||
.spllctrl_vco_1 = 0x00000016,
|
||||
.spllctrl_vco_2 = 0x00000015,
|
||||
.wrdqcalvrefcodecontrol = 0x19191111,
|
||||
.rddqcalvrefcodecontrol = 0x19191191,
|
||||
.rwcfg = 0x000210ef,
|
||||
.dllupdtctrl = 0x50017350,
|
||||
.modereg = 0x1a0cc0f4,
|
||||
.autoref_params = 0x0015005d,
|
||||
.pdn = 0x722762c6,
|
||||
.rnkcfg = 0x00006061,
|
||||
.casdllupdatectrl = 0x03030305,
|
||||
.dqsdllupdatectrl = 0x00030005,
|
||||
.rdsdllctrl_step2 = 0x00ff0002,
|
||||
.wrdqdqssdllctrl_step2 = 0xff000002,
|
||||
.cawrlvlsdllcode = 0x00ff01ff,
|
||||
.dlllocktim = 0x00c801f4,
|
||||
.rdwrdqcaltiming_f0 = 0x01040508,
|
||||
.rdwrdqcalseglen_f0 = 0x000c0012,
|
||||
.rdwrdqcaltiming_f1 = 0x01040402,
|
||||
.rdwrdqcalseglen_f1 = 0x000c0012,
|
||||
.rdwrdqcaltiming_f3 = 0x01040508,
|
||||
.rdwrdqcaltimingctrl1 = 0x0000381e,
|
||||
.rdwrdqcaltimingctrl2 = 0x01141101,
|
||||
.rddqcalpatprbs4i = 0x55553c5a,
|
||||
.wrdqcalpatprbs4i = 0x00003c5a,
|
||||
.maxrddqssdllmulfactor = 0x00a01414,
|
||||
.maxwrdqssdllmulfactor = 0xa0a00c0d,
|
||||
.dllupdtctrl1 = 0x80017580,
|
||||
.dllupdtintvl = 0x10200020,
|
||||
.dcccontrol = 0x10050b27,
|
||||
.dcccal = 0x40401320,
|
||||
.cbdrivestr = 0x33838317,
|
||||
.cbioctl = 0x00020023,
|
||||
.ckdrivestr = 0x33838317,
|
||||
.ckioctl = 0x00000027,
|
||||
.b0drivestr = 0x33838317,
|
||||
.b0ioctl = 0x71500027,
|
||||
.b0odt = 0x01c00333,
|
||||
.b0odtctrl = 0x00000007,
|
||||
.b1drivestr = 0x33838317,
|
||||
.b1ioctl = 0x71500027,
|
||||
.b1odt = 0x01c00333,
|
||||
.b1odtctrl = 0x00000007,
|
||||
.dqs0drivestr = 0x33838317,
|
||||
.dqs0ioctl = 0x71500007,
|
||||
.dqs0odt = 0x01c00336,
|
||||
.dqs0zdetbiasen = 0x00060028,
|
||||
.dqs0odtctrl = 0x00000007,
|
||||
.dqs1drivestr = 0x33838317,
|
||||
.dqs1ioctl = 0x71500007,
|
||||
.dqs1odt = 0x01c00336,
|
||||
.dqs1zdetbiasen = 0x00060028,
|
||||
.dqs1odtctrl = 0x00000007,
|
||||
.zcalfsm1 = 0x00887f7f,
|
||||
.zcalfsm0 = 0x000f031b,
|
||||
.spare0 = 0x00000016,
|
||||
.dficaltiming = 0x06000504,
|
||||
.hwrddqcaltvref = 0x08080808,
|
||||
.arefparam = 0x0d012019,
|
||||
.autoref_params2 = 0x0017005d,
|
||||
.odtszqc = 0x00001000,
|
||||
.longsr = 0x01022008,
|
||||
.freqchngctl_step3 = 0x01010000,
|
||||
.mr3cmd = 0xf3,
|
||||
.mr13cmd = 0x18,
|
||||
.addrcfg = 0x00030201,
|
||||
.chnldec = 0x00050120,
|
||||
// steps 7-10 are skipped for Elba since freq bucket 1 not used
|
||||
.mr13cmd_step11 = 0x58,
|
||||
.mr2cmd_step11 = 0x2d,
|
||||
.mr1cmd_step11 = 0xde,
|
||||
.mr3cmd_step11 = 0xb3,
|
||||
.mr22cmd_step11 = 0x04,
|
||||
.mr11cmd_step11 = 0x44,
|
||||
.mr12cmd_step11 = 0x11,
|
||||
.mr14cmd_step11 = 0x11,
|
||||
.mr13cmd_step13 = 0x98,
|
||||
.dqs0wkpupd = 0x00010782,
|
||||
.dqs1wkpupd = 0x00010782,
|
||||
.mr13cmd_step15 = 0x90,
|
||||
.freqchngctl_step15 = 0x00009999,
|
||||
.rdsdllctrl_step15 = 0x00140004,
|
||||
.odtszqc2 = 0xc0001000,
|
||||
.qbren_step16 = 0x0000000d,
|
||||
.b0dyniselasrtime = 0x00000019,
|
||||
.b0dynisel = 0x00000001,
|
||||
.b1dynisel = 0x00000000,
|
||||
.qbrparam = 0x000000a8,
|
||||
.qbren = 0x0000000f,
|
||||
.mccgen = 0x00000126,
|
||||
.caampclk = 0x00000000,
|
||||
.dqampclk = 0x00000000,
|
||||
.pwrmngten = 0x00000133,
|
||||
.odtszqc3 = 0xc0003320,
|
||||
|
||||
.freq = {
|
||||
{ // 1600MHz
|
||||
.clk_period = CLK_PERIOD_1600,
|
||||
.freqchngctl = {0x18cd104d, 0x110c110e, 0xb303440b, 0xde012d02, 0x00000416},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.lat = 0x00103387,
|
||||
.phyrdwrtim = 0x00060d0c,
|
||||
.caspch = 0x63e2080f,
|
||||
.act = 0x2008110f,
|
||||
.autoref = 0x48900078,
|
||||
.selfref = 0xa0096012,
|
||||
.derate = 0x4d05a910,
|
||||
.lat2 = 0x00123387,
|
||||
.tat = 0x01412222,
|
||||
.mifqmaxctrl = 0x00000100,
|
||||
.cavref = 0x00000003,
|
||||
.odt_enable = 0x00000001,
|
||||
.dqvref = 0x00c000c0,
|
||||
.dqdficaltiming = 0x06020404,
|
||||
.rddqcalwindow = 0x00ff01d1,
|
||||
.wrdqcalwindow = 0x00ff0160,
|
||||
.rdcapcfg = 0x01000810,
|
||||
.autoref2 = 0x48900092,
|
||||
},
|
||||
{ // 800MHz
|
||||
.freqchngctl = {0x18cd104d, 0x110c110e, 0xd303220b, 0xae015202, 0x00000216},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.lat = 0x00102206,
|
||||
.phyrdwrtim = 0x00050b06,
|
||||
.caspch = 0x42110408,
|
||||
.act = 0x10040908,
|
||||
.autoref = 0x24480050,
|
||||
.selfref = 0x5004b012,
|
||||
.derate = 0x28835488,
|
||||
.lat2 = 0x00112206,
|
||||
.tat = 0x01312222,
|
||||
.cavref = 0x00000003,
|
||||
.odt_enable = 0x00000001,
|
||||
.dqvref = 0x00c000c0,
|
||||
.cadficaltiming = 0x04000410,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.rddqcalwindow = 0x00ff01d1,
|
||||
.wrdqcalwindow = 0x00ff0160,
|
||||
.rdcapcfg = 0x2100060a,
|
||||
.autoref2 = 0x24480049,
|
||||
},
|
||||
{ // 200MHz
|
||||
.freqchngctl = {0x18cd104d, 0x590c590e, 0xf303000b, 0x8e010002, 0x00000016},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.phyrdwrtim = 0x00010b01,
|
||||
.caspch = 0x40c50402,
|
||||
.act = 0x04020302,
|
||||
.autoref = 0x09120014,
|
||||
.selfref = 0x28013012,
|
||||
.derate = 0x0c212142,
|
||||
.lat2 = 0x001110c2,
|
||||
.tat = 0x01212222,
|
||||
.cavref = 0x00000003,
|
||||
.dqvref = 0x00000000,
|
||||
.cadficaltiming = 0x04000410,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.rdcapcfg = 0x41000408,
|
||||
.autoref2 = 0x09120013,
|
||||
},
|
||||
{ // 50MHz
|
||||
.freqchngctl = {0x18cd104d, 0x590c590e, 0xf303000b, 0x8e010002, 0x00000016},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.phyrdwrtim = 0x00010901,
|
||||
.caspch = 0x40c20402,
|
||||
.act = 0x02020404,
|
||||
.autoref = 0x03050005,
|
||||
.selfref = 0x28006012,
|
||||
.derate = 0x10412082,
|
||||
.lat2 = 0x001110c2,
|
||||
.tat = 0x01212222,
|
||||
.mifqmaxctrl = 0x00000001,
|
||||
.cavref = 0x00000003,
|
||||
.odt_enable = 0x00000000,
|
||||
.dqvref = 0x00000000,
|
||||
.cadficaltiming = 0x04000410,
|
||||
.dqdficaltiming = 0x04020404,
|
||||
.rdcapcfg = 0x61000408,
|
||||
.autoref2 = 0x03050005,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
#define BIT32_MASKFULL (0xFFFFFFFF)
|
||||
#define BIT32_MASK(_n) (BIT32_MASKFULL >> (32 - (_n)))
|
||||
#define BIT32_MASK_VAL(_h,_l,_d) (((_d) & BIT32_MASK((_h) - (_l) + 1)) << (_l))
|
||||
#define BIT32_MASK_HI_LO(_h,_l) BIT32_MASK_VAL(_h,_l,BIT32_MASKFULL)
|
||||
#define DCS_MASK_VAL(_h,_l,_d) BIT32_MASK_HI_LO(_h,_l) , BIT32_MASK_VAL(_h,_l,_d)
|
||||
|
||||
// DCS Tunables for s8001 B0
|
||||
// Tunables Spec versions:
|
||||
// MCU: https://seg-docs.ecs.apple.com/projects/elba//release/UserManual/tunables_a0/MCU.html v14.2.0
|
||||
// AMPSCA: https://seg-docs.ecs.apple.com/projects/elba//release/UserManual/tunables_a0/AMPSCA.html dated 2014/11/10 13:03:48
|
||||
// Notes:
|
||||
// All channels are tuned in exactly the same way
|
||||
// Registers with all fields' tunable values matching the reset value omitted
|
||||
const dcs_tunable_t dcs_tunables[] = {
|
||||
{ rDCS_MCU_AMCCLKPWRGATE, DCS_MASK_VAL(12, 12, 0x0) },
|
||||
{ rDCS_MCU_AMCCLKPWRGATE, DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(31, 24, 0xFF) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(20, 20, 0x0) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(16, 16, 0x1) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(12, 12, 0x0) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL( 4, 4, 0x1) },
|
||||
|
||||
{ rDCS_MCU_PSQRQTIMER0, DCS_MASK_VAL(27, 16, 0x014) },
|
||||
{ rDCS_MCU_PSQRQTIMER0, DCS_MASK_VAL(11, 0, 0x040) },
|
||||
|
||||
{ rDCS_MCU_PSQRQTIMER1, DCS_MASK_VAL(27, 16, 0x00F) },
|
||||
{ rDCS_MCU_PSQRQTIMER1, DCS_MASK_VAL(11, 0, 0x040) },
|
||||
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL(28, 24, 0x04) },
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL(20, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL(12, 8, 0x04) },
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL( 4, 0, 0x10) },
|
||||
|
||||
{ rDCS_MCU_PSQRQSCHCRD, DCS_MASK_VAL(23, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQRQSCHCRD, DCS_MASK_VAL(15, 8, 0x14) },
|
||||
{ rDCS_MCU_PSQRQSCHCRD, DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_PSQWQ_CTL(0), DCS_MASK_VAL(16, 16, 0x1) },
|
||||
{ rDCS_MCU_PSQWQ_CTL(0), DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
|
||||
// part of init sequence, so have to apply tunables even if same as reset values
|
||||
{ rDCS_MCU_PSQWQ_CTL(1), DCS_MASK_VAL(31, 16, 0x0164) },
|
||||
{ rDCS_MCU_PSQWQ_CTL(1), DCS_MASK_VAL(15, 0, 0x02DA) },
|
||||
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL(28, 24, 0x04) },
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL(20, 16, 0x08) },
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL(12, 8, 0x04) },
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL( 4, 0, 0x10) },
|
||||
|
||||
{ rDCS_MCU_PSQWQSCHCRD, DCS_MASK_VAL(23, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQWQSCHCRD, DCS_MASK_VAL(15, 8, 0x14) },
|
||||
{ rDCS_MCU_PSQWQSCHCRD, DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_QOSLLT, DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
{ rDCS_MCU_QOSLLT, DCS_MASK_VAL( 4, 0, 0x1F) },
|
||||
|
||||
{ rDCS_MCU_SBQOSUPGCTL, DCS_MASK_VAL(31, 31, 0x1) },
|
||||
{ rDCS_MCU_SBQOSUPGCTL, DCS_MASK_VAL(15, 8, 0x6F) },
|
||||
{ rDCS_MCU_SBQOSUPGCTL, DCS_MASK_VAL( 7, 0, 0x6E) },
|
||||
|
||||
// DRAM Cfg
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(0), DCS_MASK_VAL(31, 16, 0x0300) },
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(0), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(1), DCS_MASK_VAL(31, 16, 0x0180) },
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(1), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(2), DCS_MASK_VAL(31, 16, 0x0180) },
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(2), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(3), DCS_MASK_VAL(31, 16, 0x0030) },
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(3), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_ROWHAM_CTL(0), DCS_MASK_VAL(31, 16, 0x4002) },
|
||||
{ rDCS_MCU_ROWHAM_CTL(0), DCS_MASK_VAL( 0, 0, 0x0) },
|
||||
|
||||
{ rDCS_MCU_ROWHAM_CTL(1), DCS_MASK_VAL(31, 16, 0x4A38) },
|
||||
{ rDCS_MCU_ROWHAM_CTL(1), DCS_MASK_VAL(15, 0, 0x22D5) },
|
||||
|
||||
{ rDCS_MCU_ROWHAM_CTL(2), DCS_MASK_VAL(15, 0, 0x4A33) },
|
||||
|
||||
// AMP
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(0), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(0), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(1), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(1), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(2), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(2), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(3), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(3), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
// Alternate End Marker
|
||||
// { 0, 0, 0 }
|
||||
};
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,365 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __DCSCONFIG_S8003_H
|
||||
#define __DCSCONFIG_S8003_H
|
||||
|
||||
dcs_config_params_t dcs_params = {
|
||||
.supported_freqs = DCS_FREQ(0) | DCS_FREQ(1) | DCS_FREQ(3),
|
||||
.num_freqchngctl_regs = 5,
|
||||
.spllctrl_vco_1 = 0x00000076,
|
||||
.spllctrl_vco_2 = 0x00000078,
|
||||
.rwcfg = 0x000410ef,
|
||||
.dllupdtctrl = 0x50017350,
|
||||
.modereg = 0x140a90b4,
|
||||
.autoref_params = 0x0015005d,
|
||||
.pdn = 0x62265295,
|
||||
.rnkcfg = 0x00006061,
|
||||
.cackcswkds = 0x000000db,
|
||||
.dqspdres = 0x00000001,
|
||||
.casdllupdatectrl = 0x0303030b,
|
||||
.dqsdllupdatectrl = 0x0003000b,
|
||||
.rdsdllctrl_step2 = 0x00ff0004,
|
||||
.wrdqdqssdllctrl_step2 = 0xff000004,
|
||||
.cawrlvlsdllcode = 0x00ff02ff,
|
||||
.dlllocktim = 0x012c012c,
|
||||
.dficaltiming = 0x04000410,
|
||||
.rdwrdqcaltiming_f0 = 0x00001426,
|
||||
.rdwrdqcalseglen_f0 = 0x00010002,
|
||||
.rdwrdqcaltiming_f1 = 0x00001422,
|
||||
.rdwrdqcalseglen_f1 = 0x00010002,
|
||||
.rdwrdqcaltimingctrl1 = 0x0000301e,
|
||||
.rdwrdqcaltimingctrl2 = 0x03111004,
|
||||
.rddqcalpatprbs4i = 0x55555e26,
|
||||
.wrdqcalpatprbs4i = 0x55555e26,
|
||||
.maxrddqssdllmulfactor = 0x00a01414,
|
||||
.maxwrdqssdllmulfactor = 0xa0a00c0c,
|
||||
.dllupdtctrl1 = 0x50017550,
|
||||
.dllupdtintvl = 0x10200020,
|
||||
.cbdrivestr = 0x33831717,
|
||||
.cbioctl = 0x000200a3,
|
||||
.ckdrivestr = 0x33831717,
|
||||
.ckioctl = 0x000000a7,
|
||||
.b0drivestr = 0x33831717,
|
||||
.b0ioctl = 0x715000a7,
|
||||
.b0odt = 0x01c00333,
|
||||
.b0odtctrl = 0x00000005,
|
||||
.b1drivestr = 0x33831717,
|
||||
.b1ioctl = 0x715000a7,
|
||||
.b1odt = 0x01c00333,
|
||||
.b1odtctrl = 0x00000005,
|
||||
.dqs0drivestr = 0x33831717,
|
||||
.dqs0ioctl = 0x715000a7,
|
||||
.dqs0odt = 0x01c00333,
|
||||
.dqs0zdetbiasen = 0x00060028,
|
||||
.dqs0odtctrl = 0x00000007,
|
||||
.dqs1drivestr = 0x33831717,
|
||||
.dqs1ioctl = 0x715000a7,
|
||||
.dqs1odt = 0x01c00333,
|
||||
.dqs1zdetbiasen = 0x00060028,
|
||||
.dqs1odtctrl = 0x00000007,
|
||||
.zcalfsm1 = 0x00667f7f,
|
||||
.zcalfsm0 = 0x000f0315,
|
||||
.spare0 = 0x0000000e,
|
||||
.arefparam = 0x08010019,
|
||||
.autoref_params2 = 0x0017005d,
|
||||
.odtszqc = 0x00001000,
|
||||
.longsr = 0x01012008,
|
||||
.freqchngctl_step3 = 0x00010000,
|
||||
.mr3cmd = 0xf3,
|
||||
.mr13cmd = 0x18,
|
||||
.addrcfg = 0x00030201,
|
||||
.chnldec = 0x00050220,
|
||||
.mr13cmd_step7 = 0x58,
|
||||
.mr3cmd_step7 = 0xf3,
|
||||
.mr22cmd = 0x04,
|
||||
.mr11cmd = 0x03,
|
||||
.mr13cmd_step9 = 0xd8,
|
||||
.freqchngctl_step9 = 0x00010000,
|
||||
.dqs0wkpupd = 0x00030788,
|
||||
.dqs1wkpupd = 0x00030788,
|
||||
.mr13cmd_step11 = 0x98,
|
||||
.mr2cmd_step11 = 0x24,
|
||||
.mr1cmd_step11 = 0xce,
|
||||
.mr3cmd_step11 = 0xb3,
|
||||
.mr22cmd_step11 = 0x04,
|
||||
.mr11cmd_step11 = 0x44,
|
||||
.mr12cmd_step11 = 0x11,
|
||||
.mr14cmd_step11 = 0x11,
|
||||
.mr13cmd_step13 = 0x18,
|
||||
.mr13cmd_step15 = 0x50,
|
||||
.freqchngctl_step15 = 0x00009999,
|
||||
.rdsdllctrl_step15 = 0x001a0004,
|
||||
.odtszqc2 = 0xc0001000,
|
||||
.qbrparam = 0x000061a5,
|
||||
.qbren_step16 = 0x0000000d,
|
||||
.b0dyniselasrtime = 0x00001117,
|
||||
.b0dynisel = 0x00000003,
|
||||
.b1dynisel = 0x00000003,
|
||||
.qbren = 0x0000000f,
|
||||
.mccgen = 0x00000126,
|
||||
.caampclk = 0x00000000,
|
||||
.dqampclk = 0x00000000,
|
||||
.pwrmngten = 0x00000133,
|
||||
.odtszqc3 = 0xc0003320,
|
||||
|
||||
.freq = {
|
||||
{ // 1200MHz
|
||||
.clk_period = CLK_PERIOD_1200,
|
||||
.freqchngctl = {0x18cd104d, 0x110c110e, 0xb303440b, 0xce012402, 0x00000416},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.lat = 0x00103306,
|
||||
.phyrdwrtim = 0x00050d0a,
|
||||
.caspch = 0x531a060b,
|
||||
.act = 0x18060d0b,
|
||||
.autoref = 0x366c0078,
|
||||
.selfref = 0x78071012,
|
||||
.derate = 0x38c486cc,
|
||||
.lat2 = 0x00113306,
|
||||
.tat = 0x01312222,
|
||||
.mifqmaxctrl = 0x00000100,
|
||||
.nondqdspd = 0x000b316b,
|
||||
.cavref = 0x00000003,
|
||||
.odt_enable = 0x00000001,
|
||||
.dqds = 0x000c0b08,
|
||||
.dqdqsds = 0x000c0b08,
|
||||
.dqvref = 0x00c000c0,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.rddqcalwindow = 0x00b101d1,
|
||||
.wrdqcalwindow = 0x012f0360,
|
||||
.caoutdllscl = 0x00000008,
|
||||
.dqsindllscl = 0x00000008,
|
||||
.rdcapcfg = 0x0100080d,
|
||||
.autoref2 = 0x366c006e,
|
||||
},
|
||||
{ // 800MHz
|
||||
.clk_period = CLK_PERIOD_800,
|
||||
.freqchngctl = {0x18cd104d, 0x110c110e, 0xf303030b, 0xae015202, 0x00000416},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.lat = 0x00102206,
|
||||
.phyrdwrtim = 0x00050c06,
|
||||
.caspch = 0x42110408,
|
||||
.act = 0x10040908,
|
||||
.autoref = 0x24480050,
|
||||
.selfref = 0x5004b012,
|
||||
.derate = 0x28835488,
|
||||
.lat2 = 0x00112206,
|
||||
.tat = 0x01312222,
|
||||
.nondqdspd = 0x000b216b,
|
||||
.nondqds = 0x00080508,
|
||||
.cavref = 0x00000003,
|
||||
.odt_enable = 0x00000001,
|
||||
.dqds = 0x00080b00,
|
||||
.dqdqsds = 0x00080b00,
|
||||
.dqvref = 0x00c000c0,
|
||||
.cadficaltiming = 0x04000410,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.rddqcalwindow = 0x00f801d1,
|
||||
.wrdqcalwindow = 0x012f0360,
|
||||
#ifdef TARGET_DDR_800M
|
||||
.caoutdllscl = 0x0000000c,
|
||||
.dqsindllscl = 0x0000000c,
|
||||
#else
|
||||
.caoutdllscl = 0x0000000d,
|
||||
.dqsindllscl = 0x0000000d,
|
||||
#endif
|
||||
.rdcapcfg = 0x2100070a,
|
||||
.autoref2 = 0x24480049,
|
||||
},
|
||||
{ // 200MHz
|
||||
.freqchngctl = {0x18cd104d, 0x590c590e, 0xf303000b, 0x8e010002, 0x00000016},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.phyrdwrtim = 0x00010c01,
|
||||
.caspch = 0x40c50402,
|
||||
.act = 0x04020302,
|
||||
.autoref = 0x09120014,
|
||||
.selfref = 0x28013012,
|
||||
.derate = 0x0c212142,
|
||||
.lat2 = 0x001110c2,
|
||||
.tat = 0x01212222,
|
||||
.nondqdspd = 0x000b3d6b,
|
||||
.nondqds = 0x00083d08,
|
||||
.cavref = 0x00000003,
|
||||
.dqds = 0x00080b00,
|
||||
.dqdqsds = 0x00080b00,
|
||||
.dqvref = 0x00800080,
|
||||
.cadficaltiming = 0x04000410,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.caoutdllscl = 0x00000030,
|
||||
.dqsindllscl = 0x00000030,
|
||||
.rdcapcfg = 0x41000508,
|
||||
.autoref2 = 0x09120013,
|
||||
},
|
||||
{ // 50MHz
|
||||
.freqchngctl = {0x18cd104d, 0x590c590e, 0xf303000b, 0x8e010002, 0x00000016},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.phyrdwrtim = 0x00010a01,
|
||||
.caspch = 0x40c20402,
|
||||
.act = 0x02020404,
|
||||
.autoref = 0x03050005,
|
||||
.selfref = 0x28006012,
|
||||
.derate = 0x10412082,
|
||||
.lat2 = 0x001110c2,
|
||||
.tat = 0x01212222,
|
||||
.mifqmaxctrl = 0x00000001,
|
||||
.nondqdspd = 0x000b3d6b,
|
||||
.nondqds = 0x00083d08,
|
||||
.cavref = 0x00000003,
|
||||
.odt_enable = 0x00000000,
|
||||
.dqds = 0x00080b00,
|
||||
.dqdqsds = 0x00080b00,
|
||||
.dqvref = 0x00800080,
|
||||
.cadficaltiming = 0x04000410,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.caoutdllscl = 0x0000003f,
|
||||
.dqsindllscl = 0x0000003f,
|
||||
.rdcapcfg = 0x61000508,
|
||||
.autoref2 = 0x03050005,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
#define BIT32_MASKFULL (0xFFFFFFFF)
|
||||
#define BIT32_MASK(_n) (BIT32_MASKFULL >> (32 - (_n)))
|
||||
#define BIT32_MASK_VAL(_h,_l,_d) (((_d) & BIT32_MASK((_h) - (_l) + 1)) << (_l))
|
||||
#define BIT32_MASK_HI_LO(_h,_l) BIT32_MASK_VAL(_h,_l,BIT32_MASKFULL)
|
||||
#define DCS_MASK_VAL(_h,_l,_d) BIT32_MASK_HI_LO(_h,_l) , BIT32_MASK_VAL(_h,_l,_d)
|
||||
|
||||
// DCS Tunables for s8003
|
||||
// Tunables Spec versions:
|
||||
// MCU: https://seg-docs.ecs.apple.com/projects/malta//release/UserManual/tunables/MCU.html dated 2015/06/09 22:36:07
|
||||
// AMPSCA: https://seg-docs.ecs.apple.com/projects/malta//release/UserManual/tunables/AMPSCA.html dated 2014/11/10
|
||||
// All 4 channels are tuned in exactly the same way
|
||||
const dcs_tunable_t dcs_tunables[] = {
|
||||
// AMC Clk
|
||||
{ rDCS_MCU_AMCCLKPWRGATE, DCS_MASK_VAL(12, 12, 0x0) },
|
||||
{ rDCS_MCU_AMCCLKPWRGATE, DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
|
||||
// PSQ RQ (Part I)
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(31, 24, 0xFF) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(20, 20, 0x0) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(16, 16, 0x1) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL( 4, 4, 0x1) },
|
||||
|
||||
// PSQ Freq 0
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(0), DCS_MASK_VAL(29, 16, 0x3f4b) },
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(0), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(0), DCS_MASK_VAL( 8, 0, 0x0b4) },
|
||||
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(0), DCS_MASK_VAL(29, 16, 0x3f4b) },
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(0), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(0), DCS_MASK_VAL( 8, 0, 0x0b4) },
|
||||
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(0), DCS_MASK_VAL(29, 16, 0x3f4b) },
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(0), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(0), DCS_MASK_VAL( 8, 0, 0x0b4) },
|
||||
|
||||
// PSQ Freq 1
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(1), DCS_MASK_VAL(29, 16, 0x3f87) },
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(1), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQCPU0LLT_FREQ(1), DCS_MASK_VAL( 8, 0, 0x078) },
|
||||
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(1), DCS_MASK_VAL(29, 16, 0x3f87) },
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(1), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQCPU1LLT_FREQ(1), DCS_MASK_VAL( 8, 0, 0x078) },
|
||||
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(1), DCS_MASK_VAL(29, 16, 0x3f87) },
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(1), DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_PSQSOCLLT_FREQ(1), DCS_MASK_VAL( 8, 0, 0x078) },
|
||||
|
||||
// PSQ RQ (Part II)
|
||||
{ rDCS_MCU_PSQRQTIMER0, DCS_MASK_VAL(27, 16, 0x014) },
|
||||
{ rDCS_MCU_PSQRQTIMER0, DCS_MASK_VAL(11, 0, 0x040) },
|
||||
|
||||
{ rDCS_MCU_PSQRQTIMER1, DCS_MASK_VAL(27, 16, 0x00f) },
|
||||
{ rDCS_MCU_PSQRQTIMER1, DCS_MASK_VAL(11, 0, 0x040) },
|
||||
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL(28, 24, 0x04) },
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL(20, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL(12, 8, 0x04) },
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL( 4, 0, 0x10) },
|
||||
|
||||
{ rDCS_MCU_PSQRQSCHCRD, DCS_MASK_VAL(23, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQRQSCHCRD, DCS_MASK_VAL(15, 8, 0x14) },
|
||||
{ rDCS_MCU_PSQRQSCHCRD, DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
// PSQ WQ
|
||||
{ rDCS_MCU_PSQWQ_CTL(0), DCS_MASK_VAL(16, 16, 0x1) },
|
||||
{ rDCS_MCU_PSQWQ_CTL(0), DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
|
||||
// part of init sequence, so have to apply tunables even if same as reset values
|
||||
#if DISPLAY_D620_TUNABLES
|
||||
{ rDCS_MCU_PSQWQ_CTL(1), DCS_MASK_VAL(31, 16, 0x0944) },
|
||||
#else
|
||||
{ rDCS_MCU_PSQWQ_CTL(1), DCS_MASK_VAL(31, 16, 0x0494) },
|
||||
#endif
|
||||
{ rDCS_MCU_PSQWQ_CTL(1), DCS_MASK_VAL(15, 0, 0x0224) },
|
||||
|
||||
{ rDCS_MCU_PSQWQ_CTL(2), DCS_MASK_VAL(31, 16, 0x002b) },
|
||||
{ rDCS_MCU_PSQWQ_CTL(2), DCS_MASK_VAL(15, 0, 0x0158) },
|
||||
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL(28, 24, 0x04) },
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL(20, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL(12, 8, 0x04) },
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL( 4, 0, 0x10) },
|
||||
|
||||
{ rDCS_MCU_PSQWQSCHCRD, DCS_MASK_VAL(23, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQWQSCHCRD, DCS_MASK_VAL(15, 8, 0x14) },
|
||||
{ rDCS_MCU_PSQWQSCHCRD, DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
// QoS
|
||||
{ rDCS_MCU_QOSLLT, DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
{ rDCS_MCU_QOSLLT, DCS_MASK_VAL( 4, 0, 0x1f) },
|
||||
|
||||
{ rDCS_MCU_SBQOSUPGCTL, DCS_MASK_VAL(31, 31, 0x1) },
|
||||
{ rDCS_MCU_SBQOSUPGCTL, DCS_MASK_VAL( 7, 0, 0x6e) },
|
||||
|
||||
// DRAM Cfg
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(0), DCS_MASK_VAL(31, 16, 0x0240) },
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(0), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
#if DISPLAY_D620_TUNABLES
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(1), DCS_MASK_VAL(31, 16, 0x0960) },
|
||||
#else
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(1), DCS_MASK_VAL(31, 16, 0x04b0) },
|
||||
#endif
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(1), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(2), DCS_MASK_VAL(31, 16, 0x0180) },
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(2), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(3), DCS_MASK_VAL(31, 16, 0x0030) },
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(3), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_ROWHAM_CTL(0), DCS_MASK_VAL(31, 16, 0x4002) },
|
||||
{ rDCS_MCU_ROWHAM_CTL(0), DCS_MASK_VAL( 0, 0, 0x0) },
|
||||
|
||||
{ rDCS_MCU_ROWHAM_CTL(1), DCS_MASK_VAL(31, 16, 0x4a38) },
|
||||
{ rDCS_MCU_ROWHAM_CTL(1), DCS_MASK_VAL(15, 0, 0x22d5) },
|
||||
|
||||
{ rDCS_MCU_ROWHAM_CTL(2), DCS_MASK_VAL(15, 0, 0x4a33) },
|
||||
|
||||
// AMP
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(0), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(0), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(1), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(1), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(2), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(2), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(3), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(3), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
// Alternate End Marker
|
||||
// { 0, 0, 0 }
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_ERROR_HANDLER_H
|
||||
#define __PLATFORM_ERROR_HANDLER_H
|
||||
|
||||
void platform_enable_error_handler();
|
||||
|
||||
#endif // __PLATFORM_ERROR_HANDLER_H
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_GPIODEF_H
|
||||
#define __PLATFORM_GPIODEF_H
|
||||
|
||||
#include <platform.h>
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#if WITH_TARGET_CONFIG
|
||||
# include <target/gpiodef.h>
|
||||
#endif
|
||||
|
||||
#if SUB_PLATFORM_S8003
|
||||
#include <platform/gpiodef_s8000.h>
|
||||
#else
|
||||
#include SUB_PLATFORM_HEADER(gpiodef)
|
||||
#endif
|
||||
|
||||
#endif /* ! __PLATFORM_GPIODEF_H */
|
||||
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_GPIODEF_S8000_H
|
||||
#define __PLATFORM_GPIODEF_S8000_H
|
||||
|
||||
#if !SUB_PLATFORM_S8000 && !SUB_PLATFORM_S8003
|
||||
#error "Only include for S8000 platform"
|
||||
#endif
|
||||
|
||||
/* S8000 specific gpio -> pin mappings - Fiji I/O Spreadsheet v9.3 */
|
||||
|
||||
/* define platform-specific gpios in a generic fashion here. */
|
||||
#define GPIO_BOARD_ID0 GPIO(103)
|
||||
#define GPIO_BOARD_ID1 GPIO(104)
|
||||
#define GPIO_BOARD_ID2 GPIO(105)
|
||||
#define GPIO_BOARD_ID3 GPIO(80)
|
||||
#define GPIO_BOARD_ID4 GPIO(138)
|
||||
|
||||
/* Boot configuration pins */
|
||||
#define GPIO_BOOT_CONFIG0 GPIO(82)
|
||||
#define GPIO_BOOT_CONFIG1 GPIO(122)
|
||||
#define GPIO_BOOT_CONFIG2 GPIO(137)
|
||||
|
||||
/* Boot configuration pin encodings */
|
||||
#define BOOT_CONFIG_SPI0 (0)
|
||||
#define BOOT_CONFIG_SPI0_TEST (1)
|
||||
#define BOOT_CONFIG_NVME0_X2 (2)
|
||||
#define BOOT_CONFIG_NVME0_X2_TEST (3)
|
||||
#define BOOT_CONFIG_NVME0_X1 (4)
|
||||
#define BOOT_CONFIG_NVME0_X1_TEST (5)
|
||||
#define BOOT_CONFIG_SLOW_SPI0_TEST (6)
|
||||
#define BOOT_CONFIG_FAST_SPI0_TEST (7)
|
||||
|
||||
#define GPIO_REQUEST_DFU1 GPIO(97) // HOLD_KEY
|
||||
#define GPIO_REQUEST_DFU2 GPIO(96) // MENU_KEY
|
||||
#define GPIO_FORCE_DFU GPIO(123) // FORCE_DFU
|
||||
#define GPIO_DFU_STATUS GPIO(136) // DFU_STATUS
|
||||
|
||||
#define SPI_NOR0 (0)
|
||||
|
||||
#define GPIO_SPI0_SCLK GPIO(103)
|
||||
#define GPIO_SPI0_MOSI GPIO(104)
|
||||
#define GPIO_SPI0_MISO GPIO(105)
|
||||
#define GPIO_SPI0_SSIN GPIO(106)
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define GPIO_SPI0_CS GPIO(GPIO_PAD_SPI, 0)
|
||||
#else
|
||||
#define GPIO_SPI0_CS GPIO(106) // Alias of GPIO_SPI0_SSIN
|
||||
#endif
|
||||
|
||||
#define GPIO_IIC0_SCL GPIO(46)
|
||||
#define GPIO_IIC0_SDA GPIO(45)
|
||||
#define GPIO_IIC1_SCL GPIO(115)
|
||||
#define GPIO_IIC1_SDA GPIO(114)
|
||||
#define GPIO_IIC2_SCL GPIO(23)
|
||||
#define GPIO_IIC2_SDA GPIO(22)
|
||||
|
||||
#define GPIO_PCIE0_PERST GPIO(160)
|
||||
#define GPIO_PCIE1_PERST GPIO(161)
|
||||
#define GPIO_PCIE2_PERST GPIO(162)
|
||||
#define GPIO_PCIE3_PERST GPIO(163)
|
||||
#define GPIO_PCIE0_CLKREQ GPIO(164)
|
||||
#define GPIO_PCIE1_CLKREQ GPIO(165)
|
||||
#define GPIO_PCIE2_CLKREQ GPIO(166)
|
||||
#define GPIO_PCIE3_CLKREQ GPIO(167)
|
||||
|
||||
#define GPIO_NAND_SYS_CLK GPIO(196)
|
||||
|
||||
#endif /* ! __PLATFORM_GPIODEF_S8000_H */
|
||||
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Copyright (C) 20124 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_GPIODEF_S8001_H
|
||||
#define __PLATFORM_GPIODEF_S8001_H
|
||||
|
||||
#if !SUB_PLATFORM_S8001
|
||||
#error "Only include for S8001 platform"
|
||||
#endif
|
||||
|
||||
/* S8001 specific gpio -> pin mappings - Elba I/O Spreadsheet v.27 */
|
||||
|
||||
/* define platform-specific gpios in a generic fashion here. */
|
||||
#define GPIO_BOARD_ID0 GPIO(94)
|
||||
#define GPIO_BOARD_ID1 GPIO(95)
|
||||
#define GPIO_BOARD_ID2 GPIO(96)
|
||||
#define GPIO_BOARD_ID3 GPIO(16)
|
||||
#define GPIO_BOARD_ID4 GPIO(203)
|
||||
|
||||
/* Boot configuration pins */
|
||||
#define GPIO_BOOT_CONFIG0 GPIO(18)
|
||||
#define GPIO_BOOT_CONFIG1 GPIO(185)
|
||||
#define GPIO_BOOT_CONFIG2 GPIO(202)
|
||||
|
||||
/* Boot configuration pin encodings */
|
||||
#define BOOT_CONFIG_SPI0 (0)
|
||||
#define BOOT_CONFIG_SPI0_TEST (1)
|
||||
#define BOOT_CONFIG_NVME0_X2 (2)
|
||||
#define BOOT_CONFIG_NVME0_X2_TEST (3)
|
||||
#define BOOT_CONFIG_NVME0_X1 (4)
|
||||
#define BOOT_CONFIG_NVME0_X1_TEST (5)
|
||||
#define BOOT_CONFIG_SLOW_SPI0_TEST (6)
|
||||
#define BOOT_CONFIG_FAST_SPI0_TEST (7)
|
||||
|
||||
#define GPIO_REQUEST_DFU1 GPIO(123) // HOLD_KEY
|
||||
#define GPIO_REQUEST_DFU2 GPIO(122) // MENU_KEY
|
||||
#define GPIO_FORCE_DFU GPIO(186) // FORCE_DFU
|
||||
#define GPIO_DFU_STATUS GPIO(201) // DFU_STATUS
|
||||
|
||||
#define SPI_NOR0 (0)
|
||||
|
||||
#define GPIO_SPI0_SCLK GPIO(94)
|
||||
#define GPIO_SPI0_MOSI GPIO(95)
|
||||
#define GPIO_SPI0_MISO GPIO(96)
|
||||
#define GPIO_SPI0_SSIN GPIO(97)
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define GPIO_SPI0_CS GPIO(GPIO_PAD_SPI, 0)
|
||||
#else
|
||||
#define GPIO_SPI0_CS GPIO(97) // Alias of GPIO_SPI0_SSIN
|
||||
#endif
|
||||
|
||||
#define GPIO_IIC0_SCL GPIO(165)
|
||||
#define GPIO_IIC0_SDA GPIO(164)
|
||||
#define GPIO_IIC1_SCL GPIO(178)
|
||||
#define GPIO_IIC1_SDA GPIO(177)
|
||||
#define GPIO_IIC2_SCL GPIO(132)
|
||||
#define GPIO_IIC2_SDA GPIO(131)
|
||||
#define GPIO_IIC3_SCL GPIO(115)
|
||||
#define GPIO_IIC3_SDA GPIO(114)
|
||||
|
||||
#define GPIO_PCIE0_PERST GPIO(98)
|
||||
#define GPIO_PCIE1_PERST GPIO(99)
|
||||
#define GPIO_PCIE2_PERST GPIO(100)
|
||||
#define GPIO_PCIE3_PERST GPIO(101)
|
||||
#define GPIO_PCIE4_PERST GPIO(102)
|
||||
#define GPIO_PCIE5_PERST GPIO(103)
|
||||
#define GPIO_PCIE0_CLKREQ GPIO(104)
|
||||
#define GPIO_PCIE1_CLKREQ GPIO(105)
|
||||
#define GPIO_PCIE2_CLKREQ GPIO(106)
|
||||
#define GPIO_PCIE3_CLKREQ GPIO(107)
|
||||
#define GPIO_PCIE4_CLKREQ GPIO(108)
|
||||
#define GPIO_PCIE5_CLKREQ GPIO(109)
|
||||
|
||||
#define GPIO_NAND_SYS_CLK GPIO(24)
|
||||
|
||||
#endif /* ! __PLATFORM_GPIODEF_S8001_H */
|
||||
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_IMAGE_DEVICES_H
|
||||
#define __PLATFORM_IMAGE_DEVICES_H
|
||||
|
||||
static const struct image_device platform_image_devices[] = {
|
||||
#if defined(WITH_HW_ASP)
|
||||
{ "asp_fw", 0x00000 },
|
||||
#elif defined(WITH_ANC_FIRMWARE)
|
||||
{ "anc_firmware", 0x00000 },
|
||||
#endif
|
||||
#if defined(WITH_NVME)
|
||||
{ "nvme_firmware0", 0x0000 },
|
||||
#endif
|
||||
#if !defined(WITH_HW_ASP) && !defined(WITH_ANC_FIRMWARE) && !defined(WITH_NVME)
|
||||
{ "nor0", 0x00000 },
|
||||
#endif
|
||||
};
|
||||
|
||||
#if WITH_SYSCFG
|
||||
static const struct image_device platform_syscfg_devices[] = {
|
||||
#if defined(WITH_NAND_BOOT)
|
||||
{ "nand_syscfg", 0x00000 },
|
||||
#endif
|
||||
#if defined(WITH_NVME)
|
||||
{ "nvme_syscfg0", 0x0000 },
|
||||
#endif
|
||||
#if !defined(WITH_NAND_BOOT) && !defined(WITH_NVME)
|
||||
{ "nor0", 0x00000 },
|
||||
#endif
|
||||
};
|
||||
#endif /* WITH_SYSCFG */
|
||||
|
||||
#endif /* ! __PLATFORM_IMAGE_DEVICES_H */
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_MEMCONFIG_H
|
||||
#define __PLATFORM_MEMCONFIG_H
|
||||
|
||||
/* S8000 SoC Mem Pin Configuration */
|
||||
|
||||
static const gpio_t memory_interface_gpios[] = {
|
||||
/* Not needed */
|
||||
};
|
||||
#endif /* ! __PLATFORM_MEMCONFIG_H */
|
||||
@@ -0,0 +1,348 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_MEMMAP_H
|
||||
#define __PLATFORM_MEMMAP_H
|
||||
|
||||
#include <platform/memmap_defaults.h>
|
||||
|
||||
/* S8000 specific memory map */
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
// 0x800000000 + dram_size -------------------------------
|
||||
// | NVMe (12MiB) |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | TZ0 (varies) |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | TZ1 (512KiB) |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | Consistent Debug (16KiB) |
|
||||
// |-----------------------------|
|
||||
// | Sleep Token Buffer (16KiB) |
|
||||
// |-----------------------------|
|
||||
// | DRAM Config Sequence (16KiB)|
|
||||
// |-----------------------------|
|
||||
// | Panic (512KiB) |
|
||||
// |-----------------------------|
|
||||
// | Display |
|
||||
// | (Framebuffer + scratch) |
|
||||
// | |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | |
|
||||
// | iBoot (Heap) |
|
||||
// | (Variable size depending |
|
||||
// (Elba) (Maui) | on DISPLAY_SIZE) |
|
||||
// 0x8F0180000 / 0x870180000 --> |-----------------------------|
|
||||
// | iBoot (Stacks) |
|
||||
// (Elba) (Maui) | (STACKS_SIZE) |
|
||||
// 0x8F017C000 / 0x87017C000 --> |-----------------------------|
|
||||
// | iBoot (Page Tables) |
|
||||
// (Elba) (Maui) | (PAGE_TABLES_SIZE) |
|
||||
// 0x8F0100000 / 0x870100000 --> |-----------------------------|
|
||||
// | iBoot (Text + Data) |
|
||||
// (Elba) (Maui) | (TEXT_FOOTPRINT) |
|
||||
// 0x8F0000000 / 0x870000000 --> |-----------------------------| <-- 0x800000000 + dram_size - 256MB
|
||||
// | |
|
||||
// | Unused |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | |
|
||||
// | (Ramdisk) |
|
||||
// | (Kernel + DeviceTree) |
|
||||
// | Secure memory |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | |
|
||||
// | Load region / |
|
||||
// | Insecure Memory |
|
||||
// | (overlaps with TZ0) |
|
||||
// | |
|
||||
// 0x800000000 --> -------------------------------
|
||||
//
|
||||
// Note that Elba A0/B0 instead moves TZ0/TZ1 to the bottom of DRAM. See
|
||||
// TZ0_BASE_A0 / TZ1_BASE_A0 below for more info
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define SDRAM_BASE (0x800000000ULL)
|
||||
#define SDRAM_BANK_LEN (SDRAM_LEN)
|
||||
#define SDRAM_BANK_COUNT (1)
|
||||
#define SDRAM_END (SDRAM_BASE + SDRAM_LEN)
|
||||
|
||||
#define VROM_BASE (0x100000000ULL)
|
||||
#define VROM_BANK_LEN (0x02000000ULL)
|
||||
#define VROM_LEN (0x00080000ULL)
|
||||
#define SRAM_BASE (0x180000000ULL)
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
#define VROM_RSVD (0x00100000ULL) // 512 KiB reserved for SecureROM testing, remaining 512 KiB for Data and book-keeping
|
||||
#define SRAM_LEN (0x00400000ULL) // 4 MiB
|
||||
#define SRAM_BANK_LEN (SRAM_LEN) // Starting with Elba and Cayman, SRAM should be in a 32 MB decode region
|
||||
#elif SUB_PLATFORM_S8001
|
||||
#define VROM_RSVD (0ULL)
|
||||
#define SRAM_LEN (0x00080000ULL) // 512 KiB
|
||||
#define SRAM_BANK_LEN (0x02000000ULL)
|
||||
#endif
|
||||
#define SRAM_BANK_COUNT (1)
|
||||
#define SRAM_END (SRAM_BASE + SRAM_LEN)
|
||||
|
||||
#define IO_BASE (0x200000000ULL)
|
||||
#define IO_SIZE (0x020000000ULL)
|
||||
|
||||
#define PCI_REG_BASE (0x600000000ULL)
|
||||
#define PCI_REG_LEN (0x00C000000ULL)
|
||||
#define PCI_CONFIG_BASE (0x610000000ULL)
|
||||
#define PCI_CONFIG_LEN (0x010000000ULL)
|
||||
#define PCI_32BIT_BASE (0x7C0000000ULL)
|
||||
#define PCI_32BIT_LEN (0x002000000ULL) // 32 MiB fits nicely into a 32 MiB L2 MMU block
|
||||
|
||||
#define SECUREROM_LOAD_ADDRESS (VROM_BASE)
|
||||
|
||||
/* reserved for ASP/NVMe */
|
||||
// NOTE ASP_SIZE is now defined by the platform or target makefile.
|
||||
#define ASP_BASE (SDRAM_END - ASP_SIZE)
|
||||
|
||||
#define CONSISTENT_DEBUG_SIZE (0x00004000ULL)
|
||||
#define TZ1_SIZE (0x00080000ULL)
|
||||
|
||||
#if SUB_PLATFORM_S8001
|
||||
// Elba A0 and B0 both have SEPROM bugs that prevent TZ0/TZ1
|
||||
// from being located high in DRAM. (<rdar://problem/21748486> Streamline Elba B0 memory map)
|
||||
//
|
||||
// So for these chips, we are placing TZ0/TZ1 at the base of DRAM
|
||||
// before the kernel base.
|
||||
//
|
||||
// Actual TZ0/TZ1 reservation happens later
|
||||
|
||||
#define CONSISTENT_DEBUG_BASE (ASP_BASE - CONSISTENT_DEBUG_SIZE)
|
||||
|
||||
#else
|
||||
// Reserved for TZ0/SEP
|
||||
// TZ0_SIZE is defined by the platform or target makefile
|
||||
#define TZ0_BASE (ASP_BASE - TZ0_SIZE)
|
||||
|
||||
// Reserved for TZ1/AP Monitor
|
||||
#define TZ1_BASE (TZ0_BASE - TZ1_SIZE)
|
||||
|
||||
#define CONSISTENT_DEBUG_BASE (TZ1_BASE - CONSISTENT_DEBUG_SIZE)
|
||||
#endif
|
||||
|
||||
/* reserved area for sleep token info */
|
||||
#define SLEEP_TOKEN_BUFFER_SIZE (0x00004000ULL)
|
||||
#define SLEEP_TOKEN_BUFFER_BASE (CONSISTENT_DEBUG_BASE - SLEEP_TOKEN_BUFFER_SIZE)
|
||||
|
||||
/* reserved area for config sequence region */
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
#define DRAM_CONFIG_SEQ_SIZE (0x00004000ULL)
|
||||
#elif SUB_PLATFORM_S8001
|
||||
#define DRAM_CONFIG_SEQ_SIZE (0x00008000ULL)
|
||||
#endif
|
||||
#define DRAM_CONFIG_SEQ_BASE (SLEEP_TOKEN_BUFFER_BASE - DRAM_CONFIG_SEQ_SIZE)
|
||||
|
||||
/* reserved area for panic info */
|
||||
#define PANIC_SIZE (0x00080000ULL)
|
||||
#define PANIC_BASE (DRAM_CONFIG_SEQ_BASE - PANIC_SIZE)
|
||||
|
||||
/* reserved area for display */
|
||||
// DISPLAY_SIZE comes from platform's rules.mk
|
||||
#define DISPLAY_BASE (PANIC_BASE - DISPLAY_SIZE)
|
||||
|
||||
#if SUB_PLATFORM_S8001
|
||||
#define TZ0_BASE (SDRAM_BASE)
|
||||
#define TZ1_BASE (TZ0_BASE + TZ0_SIZE)
|
||||
|
||||
|
||||
// For Elba, the kernel starts at 32MB alignment above TZ0/TZ1
|
||||
#define KERNEL_BASE (((TZ1_BASE + TZ1_SIZE) + 32*1024*1024 - 1) & ~(32*1024*1024-1))
|
||||
|
||||
#else
|
||||
|
||||
// For non-Elba systems, KERNEL_BASE simply starts at SDRAM_BASE
|
||||
#define KERNEL_BASE (SDRAM_BASE)
|
||||
#endif
|
||||
|
||||
/* where to stick heap and insecure memory */
|
||||
#if APPLICATION_SECUREROM
|
||||
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
|
||||
#define HEAP_BASE (SRAM_BASE + VROM_RSVD)
|
||||
#define HEAP_SIZE (0x00100000ULL)
|
||||
#define HEAP_END (HEAP_BASE + HEAP_SIZE)
|
||||
// XXX for future platforms, include a guard page after the heap
|
||||
|
||||
// DATA_BASE comes from rules.mk
|
||||
#define DATA_SIZE (0x00040000ULL)
|
||||
|
||||
#define PAGE_TABLES_BASE (DATA_BASE + DATA_SIZE)
|
||||
#define PAGE_TABLES_SIZE (0x00008000ULL)
|
||||
|
||||
#define BOOT_TRAMPOLINE_BASE (DATA_BASE + DATA_SIZE)
|
||||
#define BOOT_TRAMPOLINE_SIZE (0x00004000ULL)
|
||||
|
||||
#define STACKS_BASE (PAGE_TABLES_BASE + PAGE_TABLES_SIZE)
|
||||
#define STACKS_SIZE (0x00004000ULL)
|
||||
|
||||
// XXX for future platforms, this should be increased to allow larger images
|
||||
// to be loaded, with a guard between it and the stacks
|
||||
#define INSECURE_MEMORY_SIZE (0x00080000ULL)
|
||||
#define INSECURE_MEMORY_BASE (SRAM_BASE + SRAM_LEN - INSECURE_MEMORY_SIZE)
|
||||
|
||||
#elif SUB_PLATFORM_S8001
|
||||
|
||||
// DFU SPACE 0x00000 - 0x40000
|
||||
// BOOT TRAMPOLINE 0x40000 - 0x44000 (read-execute, acts as write guard between load area and data area)
|
||||
// DATA 0x44000 - 0x50000
|
||||
// PAGE TABLES 0x50000 - 0x58000 (not mapped, acts as guard between data area and stacks)
|
||||
// STACKS 0x58000 - 0x5c000
|
||||
// HEAP 0x5c000 - 0x80000
|
||||
|
||||
#define INSECURE_MEMORY_SIZE (0x00040000ULL)
|
||||
#define INSECURE_MEMORY_BASE (SRAM_BASE)
|
||||
|
||||
#define BOOT_TRAMPOLINE_BASE (INSECURE_MEMORY_BASE + INSECURE_MEMORY_SIZE)
|
||||
#define BOOT_TRAMPOLINE_SIZE (0x00004000ULL)
|
||||
|
||||
// DATA_BASE comes from rules.mk
|
||||
#define DATA_SIZE (0x0000C000ULL)
|
||||
|
||||
#define PAGE_TABLES_BASE (DATA_BASE + DATA_SIZE)
|
||||
#define PAGE_TABLES_SIZE (0x00008000ULL)
|
||||
|
||||
#define STACKS_BASE (PAGE_TABLES_BASE + PAGE_TABLES_SIZE)
|
||||
#define STACKS_SIZE (0x00004000ULL)
|
||||
|
||||
#define HEAP_BASE (STACKS_BASE + STACKS_SIZE)
|
||||
#define HEAP_SIZE (SRAM_BASE + SRAM_LEN - HEAP_BASE)
|
||||
#define HEAP_END (HEAP_BASE + HEAP_SIZE)
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* APPLICATION_SECUREROM */
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
|
||||
#if WITH_DFU_MODE
|
||||
/* LLB, iBSS DFU */
|
||||
|
||||
/* reserved area for iBoot */
|
||||
#define IBOOT_SIZE (0x01400000ULL)
|
||||
#define IBOOT_BASE (DISPLAY_BASE - IBOOT_SIZE)
|
||||
|
||||
#define INSECURE_MEMORY_SIZE (IBOOT_SIZE)
|
||||
#define INSECURE_MEMORY_BASE (IBOOT_BASE)
|
||||
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
|
||||
// SRAM memory map
|
||||
//
|
||||
// ROM Testing 0x000000 - 0x0fffff (1024 KiB)
|
||||
// Heap 0x100000 - 0x1fbfff (1008 KiB)
|
||||
// Guard 0x1fc000 - 0x1fffff ( 16 KiB)
|
||||
// Unused 0x200000 - 0x37ffff (1536 KiB)
|
||||
// Code/Data 0x380000 - 0x3e7fff ( 416 KiB)
|
||||
// Trampoline 0x3e8000 - 0x3ebfff ( 16 KiB)
|
||||
// Page Tables 0x3ec000 - 0x3fbfff ( 64 KiB = 4 pages @ 16 KiB each)
|
||||
// Stacks 0x3fc000 - 0x3fffff ( 16 KiB)
|
||||
|
||||
#define HEAP_BASE (SRAM_BASE + VROM_RSVD)
|
||||
#define HEAP_SIZE (0x00100000ULL - PAGE_SIZE)
|
||||
#define HEAP_END (HEAP_BASE + HEAP_SIZE)
|
||||
#define HEAP_GUARD (HEAP_END)
|
||||
|
||||
#define BOOT_TRAMPOLINE_BASE (TEXT_BASE + TEXT_FOOTPRINT)
|
||||
#define BOOT_TRAMPOLINE_SIZE (PAGE_SIZE)
|
||||
#define PAGE_TABLES_BASE (BOOT_TRAMPOLINE_BASE + BOOT_TRAMPOLINE_SIZE)
|
||||
#define PAGE_TABLES_SIZE (STACKS_BASE - PAGE_TABLES_BASE)
|
||||
#define STACKS_BASE (SRAM_BASE + SRAM_LEN - STACKS_SIZE)
|
||||
#define STACKS_SIZE (EXCEPTION_STACK_SIZE + BOOTSTRAP_STACK_SIZE + INTERRUPT_STACK_SIZE)
|
||||
|
||||
#elif SUB_PLATFORM_S8001
|
||||
|
||||
// Elba (S8001) offsets from SRAM_BASE
|
||||
// Code/data 0x00000 - 0x4bfff ( 304 KiB)
|
||||
// Boot trampoline 0x4c000 - 0x4ffff ( 16 KiB)
|
||||
// Heap 0x50000 - 0x73fff ( 144 KiB)
|
||||
// Page tables 0x74000 - 0x7Bfff ( 32 KiB)
|
||||
// Stacks 0x7C000 - 0x7ffff ( 16 KiB)
|
||||
|
||||
#define BOOT_TRAMPOLINE_BASE (SRAM_BASE + TEXT_FOOTPRINT)
|
||||
#define BOOT_TRAMPOLINE_SIZE (PAGE_SIZE)
|
||||
|
||||
#define HEAP_BASE (BOOT_TRAMPOLINE_BASE + BOOT_TRAMPOLINE_SIZE)
|
||||
#define HEAP_SIZE (0x00024000ULL)
|
||||
#define HEAP_END (HEAP_BASE + HEAP_SIZE)
|
||||
|
||||
#define PAGE_TABLES_BASE (HEAP_BASE + HEAP_SIZE)
|
||||
#define PAGE_TABLES_SIZE (0x00008000ULL)
|
||||
|
||||
#define STACKS_BASE (PAGE_TABLES_BASE + PAGE_TABLES_SIZE)
|
||||
#define STACKS_SIZE (0x00004000ULL)
|
||||
|
||||
#endif
|
||||
|
||||
#else /* !WITH_DFU_MODE */
|
||||
|
||||
/* iBoot, iBEC */
|
||||
|
||||
// SDRAM memory map will usually look like the following for S8000/S8003:
|
||||
//
|
||||
// iBoot Text 0x870000000 - 0x8700FFFFF ( 1 MiB)
|
||||
// Page Tables 0x870100000 - 0x870177FFF (480 KiB)
|
||||
// Stacks 0x870178000 - 0x87017BFFF ( 16 KiB)
|
||||
// Boot trampoline 0x87017C000 - 0x87017FFFF ( 16 KiB)
|
||||
// Heap 0x870180000 - (DISPLAY_BASE - 1 page)
|
||||
// Guard (DISPLAY_BASE - 1 page) - DISPLAY_BASE
|
||||
|
||||
// And for S8001:
|
||||
//
|
||||
// iBoot Text 0x8f0000000 - 0x8f00FFFFF ( 1 MiB)
|
||||
// Page Tables 0x8f0100000 - 0x8f0177FFF (480 KiB)
|
||||
// Stacks 0x8f0178000 - 0x8f017BFFF ( 16 KiB)
|
||||
// Boot trampoline 0x8f017C000 - 0x8f017FFFF ( 16 KiB)
|
||||
// Heap 0x8f0180000 - (DISPLAY_BASE - 1 page)
|
||||
// Guard (DISPLAY_BASE - 1 page) - DISPLAY_BASE
|
||||
|
||||
/* reserved area for iBoot */
|
||||
#define IBOOT_BASE (TEXT_BASE)
|
||||
#define IBOOT_SIZE (HEAP_END - IBOOT_BASE)
|
||||
|
||||
#define PAGE_TABLES_BASE (IBOOT_BASE + TEXT_FOOTPRINT)
|
||||
#define PAGE_TABLES_SIZE (0x00078000ULL)
|
||||
#define STACKS_BASE (PAGE_TABLES_BASE + PAGE_TABLES_SIZE)
|
||||
#define STACKS_SIZE (EXCEPTION_STACK_SIZE + BOOTSTRAP_STACK_SIZE + INTERRUPT_STACK_SIZE)
|
||||
#define BOOT_TRAMPOLINE_BASE (STACKS_BASE + STACKS_SIZE)
|
||||
#define BOOT_TRAMPOLINE_SIZE (PAGE_SIZE)
|
||||
|
||||
#define HEAP_BASE (BOOT_TRAMPOLINE_BASE + BOOT_TRAMPOLINE_SIZE)
|
||||
#define HEAP_SIZE (DISPLAY_BASE - HEAP_BASE - PAGE_SIZE)
|
||||
#define HEAP_END (HEAP_BASE + HEAP_SIZE)
|
||||
#define HEAP_GUARD (HEAP_END)
|
||||
#if (HEAP_GUARD != (DISPLAY_BASE - PAGE_SIZE))
|
||||
#error "Memory map configuration error"
|
||||
#endif
|
||||
|
||||
#define INSECURE_MEMORY_BASE (SDRAM_BASE)
|
||||
#define INSECURE_MEMORY_SIZE (DEFAULT_LOAD_SIZE)
|
||||
|
||||
#define SECURE_MEMORY_BASE (INSECURE_MEMORY_BASE + INSECURE_MEMORY_SIZE)
|
||||
#define SECURE_MEMORY_SIZE (DEFAULT_FREE_ADDRESS - SECURE_MEMORY_BASE)
|
||||
|
||||
/* unused area */
|
||||
#define UNUSED_MEMORY_BASE (SECURE_MEMORY_BASE + SECURE_MEMORY_SIZE)
|
||||
#define UNUSED_MEMORY_SIZE (IBOOT_BASE - UNUSED_MEMORY_BASE)
|
||||
|
||||
#endif /* !WITH_DFU_MODE */
|
||||
|
||||
#endif /* APPLICATION_IBOOT */
|
||||
|
||||
#endif /* ! __PLATFORM_MEMMAP_H */
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_PCIMAP_H
|
||||
#define __PLATFORM_PCIMAP_H
|
||||
|
||||
/* S8000 specific bus/device/function and PCI base address map */
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define PCIE_PORT0_MEMORY_BASE (PCIE_MEMORY_BASE_ADDR)
|
||||
#define PCIE_PORT0_MEMORY_LEN (0x100000ULL)
|
||||
|
||||
#define NVME0_PCI_BDF (PCI_BDF(1, 0, 0))
|
||||
#define NVME0_BASE_ADDR (PCIE_PORT0_MEMORY_BASE)
|
||||
#define NVME0_SIZE (0x2000)
|
||||
#define NVME0_DART_ID (PCIE_PORT0_DART_ID)
|
||||
|
||||
|
||||
#endif /* ! __PLATFORM_PCIMAP_H */
|
||||
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#if SUB_PLATFORM_S8003
|
||||
#include <platform/pinconfig_s8000.h>
|
||||
#else
|
||||
#include SUB_PLATFORM_HEADER(pinconfig)
|
||||
#endif
|
||||
@@ -0,0 +1,311 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_PINCONFIG_H
|
||||
#define __PLATFORM_PINCONFIG_H
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED, // 0 : SWD_TMS2 ->
|
||||
CFG_DISABLED, // 1 : SWD_TMS3 ->
|
||||
CFG_DISABLED, // 2 : UART5_RTXD ->
|
||||
CFG_DISABLED, // 3 : I2S4_MCK ->
|
||||
CFG_DISABLED, // 4 : I2S4_BCLK ->
|
||||
CFG_DISABLED, // 5 : I2S4_LRCK ->
|
||||
CFG_DISABLED, // 6 : I2S4_DIN ->
|
||||
CFG_DISABLED, // 7 : I2S4_DOUT ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED, // 8 : I2S2_MCK ->
|
||||
CFG_DISABLED, // 9 : I2S2_BCLK ->
|
||||
CFG_DISABLED, // 10 : I2S2_LRCK ->
|
||||
CFG_DISABLED, // 11 : I2S2_DIN ->
|
||||
CFG_DISABLED, // 12 : I2S2_DOUT ->
|
||||
CFG_DISABLED, // 13 : SPI1_SCLK ->
|
||||
CFG_DISABLED, // 14 : SPI1_MOSI ->
|
||||
CFG_DISABLED, // 15 : SPI1_MISO ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // 16 : SPI1_SSIN ->
|
||||
CFG_DISABLED, // 17 : I2S0_MCK ->
|
||||
CFG_DISABLED, // 18 : I2S0_BCLK ->
|
||||
CFG_DISABLED, // 19 : I2S0_LRCK ->
|
||||
CFG_DISABLED, // 20 : I2S0_DIN ->
|
||||
CFG_DISABLED, // 21 : I2S0_DOUT ->
|
||||
CFG_DISABLED, // 22 : I2C2_SDA ->
|
||||
CFG_DISABLED, // 23 : I2C2_SCL ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // 24 : UART1_TXD ->
|
||||
CFG_DISABLED, // 25 : UART1_RXD ->
|
||||
CFG_DISABLED, // 26 : UART1_RTSN ->
|
||||
CFG_DISABLED, // 27 : UART1_CTSN ->
|
||||
CFG_DISABLED, // 28 : UART4_TXD ->
|
||||
CFG_DISABLED, // 29 : UART4_RXD ->
|
||||
CFG_DISABLED, // 30 : UART4_RTSN ->
|
||||
CFG_DISABLED, // 31 : UART4_CTSN ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED, // 32 : UART7_TXD ->
|
||||
CFG_DISABLED, // 33 : UART7_RXD ->
|
||||
CFG_DISABLED, // 34 : CLK32K_OUT ->
|
||||
CFG_DISABLED, // 35 : DP_WAKEUP ->
|
||||
CFG_DISABLED, // 36 : MIPICSI_MUXSEL ->
|
||||
CFG_DISABLED, // 37 : ISP_I2C1_SDA ->
|
||||
CFG_DISABLED, // 38 : ISP_I2C1_SCL ->
|
||||
CFG_DISABLED, // 39 : ISP_I2C0_SDA ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED, // 40 : ISP_I2C0_SCL ->
|
||||
CFG_DISABLED, // 41 : SPI2_SCLK ->
|
||||
CFG_DISABLED, // 42 : SPI2_MOSI ->
|
||||
CFG_DISABLED, // 43 : SPI2_MISO ->
|
||||
CFG_DISABLED, // 44 : SPI2_SSIN ->
|
||||
CFG_DISABLED, // 45 : I2C0_SDA ->
|
||||
CFG_DISABLED, // 46 : I2C0_SCL ->
|
||||
CFG_DISABLED, // 47 : SENSOR0_ISTRB ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED, // 48 : SENSOR0_RST ->
|
||||
CFG_DISABLED, // 49 : SENSOR0_CLK ->
|
||||
CFG_DISABLED, // 50 : SENSOR0_XSHUTDOWN ->
|
||||
CFG_DISABLED, // 51 : SENSOR1_ISTRB ->
|
||||
CFG_DISABLED, // 52 : SENSOR1_RST ->
|
||||
CFG_DISABLED, // 53 : SENSOR1_CLK ->
|
||||
CFG_DISABLED, // 54 : SENSOR1_XSHUTDOWN ->
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // 64 : GPIO[0] ->
|
||||
CFG_DISABLED, // 65 : GPIO[1] ->
|
||||
CFG_DISABLED, // 66 : GPIO[2] ->
|
||||
CFG_DISABLED, // 67 : GPIO[3] ->
|
||||
CFG_DISABLED, // 68 : GPIO[4] ->
|
||||
CFG_DISABLED, // 69 : GPIO[5] ->
|
||||
CFG_DISABLED, // 70 : GPIO[6] ->
|
||||
CFG_DISABLED, // 71 : GPIO[7] ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // 72 : GPIO[8] ->
|
||||
CFG_DISABLED, // 73 : GPIO[9] ->
|
||||
CFG_DISABLED, // 74 : GPIO[10] ->
|
||||
CFG_DISABLED, // 75 : GPIO[11] ->
|
||||
CFG_DISABLED, // 76 : GPIO[12] ->
|
||||
CFG_DISABLED, // 77 : GPIO[13] ->
|
||||
CFG_DISABLED, // 78 : GPIO[14] ->
|
||||
CFG_DISABLED, // 79 : GPIO[15] ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // 80 : GPIO[16] -> BOARD_ID[3]
|
||||
CFG_DISABLED, // 81 : GPIO[17] ->
|
||||
CFG_DISABLED, // 82 : GPIO[18] -> BOOT_CONFIG[0]
|
||||
CFG_DISABLED, // 83 : I2S1_MCK ->
|
||||
CFG_DISABLED, // 84 : I2S1_BCLK ->
|
||||
CFG_DISABLED, // 85 : I2S1_LRCK ->
|
||||
CFG_DISABLED, // 86 : I2S1_DIN ->
|
||||
CFG_DISABLED, // 87 : I2S1_DOUT ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // 88 : UART3_TXD ->
|
||||
CFG_DISABLED, // 89 : UART3_RXD ->
|
||||
CFG_DISABLED, // 90 : UART3_RTSN ->
|
||||
CFG_DISABLED, // 91 : UART3_CTSN ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 12 */
|
||||
CFG_IN, // 96 : MENU_KEY_L -> REQUEST_DFU2
|
||||
CFG_IN, // 97 : HOLD_KEY_L -> REQUEST_DFU1
|
||||
CFG_DISABLED, // 98 : SKEY_L ->
|
||||
CFG_DISABLED, // 99 : SPI3_SCLK ->
|
||||
CFG_DISABLED, // 100 : SPI3_MOSI ->
|
||||
CFG_DISABLED, // 101 : SPI3_MISO ->
|
||||
CFG_DISABLED, // 102 : SPI3_SSIN ->
|
||||
CFG_DISABLED, // 103 : SPI0_SCLK -> SPI0_SCLK/BOARD_ID[0]
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // 104 : SPI0_MOSI -> SPI0_MOSI/BOARD_ID[1]
|
||||
CFG_DISABLED, // 105 : SPI0_MISO -> SPI0_MISO/BOARD_ID[2]
|
||||
CFG_DISABLED, // 106 : SPI0_SSIN -> SPI0_CS
|
||||
CFG_DISABLED, // 107 : UART0_TXD ->
|
||||
CFG_DISABLED, // 108 : UART0_RXD ->
|
||||
CFG_DISABLED, // 109 : UART6_TXD ->
|
||||
CFG_DISABLED, // 110 : UART6_RXD ->
|
||||
CFG_DISABLED, // 111 : TMR32_PWM0 ->
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : TMR32_PWM1 ->
|
||||
CFG_DISABLED, // 113 : TMR32_PWM2 ->
|
||||
CFG_DISABLED, // 114 : I2C1_SDA ->
|
||||
CFG_DISABLED, // 115 : I2C1_SCL ->
|
||||
CFG_DISABLED, // 116 : GPIO[19] ->
|
||||
CFG_DISABLED, // 117 : GPIO[20] ->
|
||||
CFG_DISABLED, // 118 : GPIO[21] ->
|
||||
CFG_DISABLED, // 119 : GPIO[22] ->
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // 120 : GPIO[23] ->
|
||||
CFG_DISABLED, // 121 : GPIO[24] ->
|
||||
CFG_DISABLED, // 122 : GPIO[25] -> BOOT_CONFIG[1]
|
||||
CFG_IN | PULL_DOWN, // 123 : GPIO[26] -> FORCE_DFU
|
||||
CFG_DISABLED | PULL_DOWN, // 124 : PMGR_MOSI -> DFU_STATUS
|
||||
CFG_DISABLED, // 125 : PMGR_MISO ->
|
||||
CFG_DISABLED, // 126 : PMGR_SCLK0 ->
|
||||
CFG_DISABLED, // 127 : PMGR_SSCLK1 ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED, // 128 : SOCHOT0 ->
|
||||
CFG_DISABLED, // 129 : SOCHOT1 ->
|
||||
CFG_DISABLED, // 130 : EDP_HPD ->
|
||||
CFG_DISABLED, // 131 : I2S3_MCK ->
|
||||
CFG_DISABLED, // 132 : I2S3_BCLK ->
|
||||
CFG_DISABLED, // 133 : I2S3_LRCK ->
|
||||
CFG_DISABLED, // 134 : I2S3_DOUT ->
|
||||
CFG_DISABLED, // 135 : I2S3_DIN ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // 136 : GPIO[27] ->
|
||||
CFG_DISABLED, // 137 : GPIO[28] -> BOOT_CONFIG[2]
|
||||
CFG_DISABLED, // 138 : GPIO[29] -> BOARD_ID[4]
|
||||
CFG_DISABLED, // 139 : GPIO[30] ->
|
||||
CFG_DISABLED, // 140 : GPIO[31] ->
|
||||
CFG_DISABLED, // 141 : GPIO[32] ->
|
||||
CFG_DISABLED, // 142 : GPIO[33] ->
|
||||
CFG_DISABLED, // 143 : GPIO[34] ->
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED, // 144 : GPIO[35] ->
|
||||
CFG_DISABLED, // 145 : GPIO[36] ->
|
||||
CFG_DISABLED, // 146 : GPIO[37] ->
|
||||
CFG_DISABLED, // 147 : GPIO[38] ->
|
||||
CFG_DISABLED, // 148 : GPIO[39] ->
|
||||
CFG_DISABLED, // 149 : GPIO[40] ->
|
||||
CFG_DISABLED, // 150 : GPIO[41] ->
|
||||
CFG_DISABLED, // 151 : GPIO[42] ->
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // 160 : PCIE_PERST0_N -> NAND_PERST
|
||||
CFG_DISABLED, // 161 : PCIE_PERST1_N ->
|
||||
CFG_DISABLED, // 162 : PCIE_PERST2_N ->
|
||||
CFG_DISABLED, // 163 : PCIE_PERST3_N ->
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 164 : PCIE_CLKREQ0_N -> NAND_CLKREQ
|
||||
CFG_DISABLED, // 165 : PCIE_CLKREQ1_N ->
|
||||
CFG_DISABLED, // 166 : PCIE_CLKREQ2_N ->
|
||||
CFG_DISABLED, // 167 : PCIE_CLKREQ3_N ->
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED, // 192 : UART2_TXD ->
|
||||
CFG_DISABLED, // 193 : UART2_RXD ->
|
||||
CFG_DISABLED, // 194 : UART2_RTSN ->
|
||||
CFG_DISABLED, // 195 : UART2_CTSN ->
|
||||
CFG_DISABLED, // 196 : NAND_SYS_CLK -> NAND_SYS_CLK
|
||||
CFG_DISABLED, // 197 : S3E_RESETN -> NAND_RESET
|
||||
CFG_DISABLED, // 198 : TST_CLKOUT ->
|
||||
CFG_DISABLED,
|
||||
};
|
||||
|
||||
static const uint32_t gpio_1_default_cfg[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED, // 0 : AOP_SPI_SCLK ->
|
||||
CFG_DISABLED, // 1 : AOP_SPI_MOSI ->
|
||||
CFG_DISABLED, // 2 : AOP_SPI_MISO ->
|
||||
CFG_DISABLED, // 3 : AOP_UART1_TXD ->
|
||||
CFG_DISABLED, // 4 : AOP_UART1_RXD ->
|
||||
CFG_DISABLED, // 5 : AOP_UART0_TXD ->
|
||||
CFG_DISABLED, // 6 : AOP_UART0_RXD ->
|
||||
CFG_DISABLED, // 7 : AOP_UART2_TXD ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED, // 8 : AOP_UART2_RXD ->
|
||||
CFG_DISABLED, // 9 : AOP_I2CM_SDA ->
|
||||
CFG_DISABLED, // 10 : AOP_I2CM_SCL ->
|
||||
CFG_DISABLED, // 11 : AOP_FUNC[0] ->
|
||||
CFG_DISABLED, // 12 : AOP_FUNC[1] ->
|
||||
CFG_DISABLED, // 13 : AOP_FUNC[2] ->
|
||||
CFG_DISABLED, // 14 : AOP_FUNC[3] ->
|
||||
CFG_DISABLED, // 15 : AOP_FUNC[4] ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // 16 : AOP_FUNC[5] ->
|
||||
CFG_DISABLED, // 17 : AOP_FUNC[6] ->
|
||||
CFG_DISABLED, // 18 : AOP_FUNC[7] ->
|
||||
CFG_DISABLED, // 19 : AOP_FUNC[8] ->
|
||||
CFG_DISABLED, // 20 : AOP_FUNC[9] ->
|
||||
CFG_DISABLED, // 21 : AOP_SWD_TCK_OUT ->
|
||||
CFG_DISABLED, // 22 : AOP_SWD_TMS0 ->
|
||||
CFG_DISABLED, // 23 : AOP_SWD_TMS1 ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // 24 : AOP_I2S_MCK ->
|
||||
CFG_DISABLED, // 25 : AOP_I2S_BCLK ->
|
||||
CFG_DISABLED, // 26 : AOP_I2S_LRCK ->
|
||||
CFG_DISABLED, // 27 : AOP_I2S_DIN ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
};
|
||||
|
||||
#endif /* ! __PLATFORM_PINCONFIG_H */
|
||||
@@ -0,0 +1,341 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_PINCONFIG_H
|
||||
#define __PLATFORM_PINCONFIG_H
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED | DRIVE_S4, // 0 : SPI1_SCLK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 1 : SPI1_MOSI ->
|
||||
CFG_DISABLED | DRIVE_S4, // 2 : SPI1_MISO ->
|
||||
CFG_DISABLED | DRIVE_S4, // 3 : SPI1_SSIN ->
|
||||
CFG_DISABLED | DRIVE_S4, // 4 : ISP_I2C0_SDA ->
|
||||
CFG_DISABLED | DRIVE_S4, // 5 : ISP_I2C0_SCL ->
|
||||
CFG_DISABLED | DRIVE_S4, // 6 : ISP_I2C0_SDA ->
|
||||
CFG_DISABLED | DRIVE_S4, // 7 : ISP_I2C0_SCL ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED | DRIVE_S4, // 8 : SENSOR0_ISTRB ->
|
||||
CFG_DISABLED | DRIVE_S4, // 9 : SENSOR0_RST ->
|
||||
CFG_DISABLED | DRIVE_S4, // 10 : SENSOR0_CLK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 11 : SENSOR0_XSHUTDOWN ->
|
||||
CFG_DISABLED | DRIVE_S4, // 12 : SENSOR1_ISTRB ->
|
||||
CFG_DISABLED | DRIVE_S4, // 13 : SENSOR1_RST ->
|
||||
CFG_DISABLED | DRIVE_S4, // 14 : SENSOR1_CLK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 15 : SENSOR1_XSHUTDOWN ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED | DRIVE_S4, // 16 : GPIO[16] -> BOARD_ID[3]
|
||||
CFG_DISABLED | DRIVE_S4, // 17 : GPIO[17] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 18 : GPIO[18] -> BOOT_CONFIG[0]
|
||||
CFG_DISABLED | DRIVE_S4, // 19 : I2S1_MCK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 20 : I2S1_BLCK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 21 : I2S1_LRCK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 22 : I2S1_DIN ->
|
||||
CFG_DISABLED | DRIVE_S4, // 23 : I2S1_DOUT ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED | DRIVE_S4, // 24 : NAND_SYS_CLK -> NAND_SYS_CLK
|
||||
CFG_DISABLED | DRIVE_S4, // 25 : S3E0_RESETN -> NAND_RESET
|
||||
CFG_DISABLED | DRIVE_S4, // 26 : S3E1_RESETN ->
|
||||
CFG_DISABLED | DRIVE_S4, // 27 : UART1_TXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 28 : UART1_RXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 29 : UART1_RTSN ->
|
||||
CFG_DISABLED | DRIVE_S4, // 30 : UART1_CTSN ->
|
||||
CFG_DISABLED | DRIVE_S4, // 31 : GPIO43 ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED | DRIVE_S4, // 32 : I2S0_BCLK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 33 : I2S0_LRCK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 34 : I2S0_DIN ->
|
||||
CFG_DISABLED | DRIVE_S4, // 35 : I2S0_DOUT ->
|
||||
CFG_DISABLED | DRIVE_S4, // 36 : I2S0_MCK ->
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED | DRIVE_S4, // 64 : I2S4_MCK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 65 : I2S4_BCLK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 66 : I2S4_LRCK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 67 : I2S4_DIN ->
|
||||
CFG_DISABLED | DRIVE_S4, // 68 : I2S4_DOUT ->
|
||||
CFG_DISABLED | DRIVE_S4, // 69 : I2S2_MCK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 70 : I2S2_BCLK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 71 : I2S2_LRCK ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED | DRIVE_S4, // 72 : I2S2_DIN ->
|
||||
CFG_DISABLED | DRIVE_S4, // 73 : I2S2_DOUT ->
|
||||
CFG_DISABLED | DRIVE_S4, // 74 : GPIO[0] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 75 : GPIO[1] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 76 : GPIO[2] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 77 : GPIO[3] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 78 : GPIO[4] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 79 : GPIO[5] ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED | DRIVE_S4, // 80 : GPIO[6] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 81 : GPIO[7] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 82 : GPIO[8] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 83 : GPIO[9] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 84 : GPIO[10] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 85 : GPIO[11] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 86 : GPIO[12] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 87 : GPIO[13] ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED | DRIVE_S4, // 88 : GPIO[14] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 89 : GPIO[15] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 90 : UART3_TXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 91 : UART3_RXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 92 : UART3_RTSN ->
|
||||
CFG_DISABLED | DRIVE_S4, // 93 : UART3_CTSN ->
|
||||
CFG_FUNC0 | DRIVE_S4, // 94 : SPI0_SCLK -> SPI0_SCLK/BOARD_ID[0]
|
||||
CFG_FUNC0 | DRIVE_S4, // 95 : SPI0_MOSI -> SPI0_MOSI/BOARD_ID[1]
|
||||
|
||||
/* Port 12 */
|
||||
CFG_FUNC0 | DRIVE_S4, // 96 : SPI0_MISO -> SPI0_MISO/BOARD_ID[2]
|
||||
CFG_OUT_1 | DRIVE_S4, // 97 : SPI0_SSIN -> SPI0_CS
|
||||
CFG_DISABLED | DRIVE_S4, // 98 : PCIE_PERST0_N -> NAND_PERST
|
||||
CFG_DISABLED | DRIVE_S4, // 99 : PCIE_PERST1_N ->
|
||||
CFG_DISABLED | DRIVE_S4, // 100 : PCIE_PERST2_N ->
|
||||
CFG_DISABLED | DRIVE_S4, // 101 : PCIE_PERST3_N ->
|
||||
CFG_DISABLED | DRIVE_S4, // 102 : PCIE_PERST4_N ->
|
||||
CFG_DISABLED | DRIVE_S4, // 103 : PCIE_PERST5_N ->
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED | INPUT_SCHMITT | SLOW_SLEW | DRIVE_S4, // 104 : PCIE_CLKREQ0_N -> NAND_CLKREQ
|
||||
CFG_DISABLED | DRIVE_S4, // 105 : PCIE_CLKREQ1_N ->
|
||||
CFG_DISABLED | DRIVE_S4, // 106 : PCIE_CLKREQ2_N ->
|
||||
CFG_DISABLED | DRIVE_S4, // 107 : PCIE_CLKREQ3_N ->
|
||||
CFG_DISABLED | DRIVE_S4, // 108 : PCIE_CLKREQ4_N ->
|
||||
CFG_DISABLED | DRIVE_S4, // 109 : PCIE_CLKREQ5_N ->
|
||||
CFG_DISABLED | DRIVE_S4, // 110 : UART2_TXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 111 : UART2_RXD ->
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED | DRIVE_S4, // 112 : UART2_RTSN ->
|
||||
CFG_DISABLED | DRIVE_S4, // 113 : UART2_CTSN ->
|
||||
CFG_DISABLED | DRIVE_S4, // 114 : I2C3_SDA ->
|
||||
CFG_DISABLED | DRIVE_S4, // 115 : I2C3_SCL ->
|
||||
CFG_DISABLED | DRIVE_S4, // 116 : GPIO[44] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 117 : GPIO[45] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 118 : GPIO[46] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 119 : GPIO[47] ->
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED | DRIVE_S4, // 120 : GPIO[48] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 121 : GPIO[49] ->
|
||||
CFG_IN | DRIVE_S4, // 122 : MENU_KEY_L -> REQUEST_DFU2
|
||||
CFG_IN | DRIVE_S4, // 123 : HOLD_KEY_L -> REQUEST_DFU1
|
||||
CFG_DISABLED | DRIVE_S4, // 124 : SKEY_L ->
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED | DRIVE_S4, // 128 : SWD_TMS2 ->
|
||||
CFG_DISABLED | DRIVE_S4, // 129 : SWD_TMS3 ->
|
||||
CFG_DISABLED | DRIVE_S4, // 130 : UART5_RTXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 131 : I2C2_SDA ->
|
||||
CFG_DISABLED | DRIVE_S4, // 132 : I2C2_SCL ->
|
||||
CFG_DISABLED | DRIVE_S4, // 133 : UART4_TXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 134 : UART4_RXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 135 : UART4_RTSN ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED | DRIVE_S4, // 136 : UART4_CTSN ->
|
||||
CFG_DISABLED | DRIVE_S4, // 137 : UART7_TXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 138 : UART7_RXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 139 : CLK32K_OUT ->
|
||||
CFG_DISABLED | DRIVE_S4, // 140 : DP_WAKEUP0 ->
|
||||
CFG_DISABLED | DRIVE_S4, // 141 : DP_WAKEUP1 ->
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED | DRIVE_S4, // 160 : SPI2_SCLK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 161 : SPI2_MOSI ->
|
||||
CFG_DISABLED | DRIVE_S4, // 162 : SPI2_MISO ->
|
||||
CFG_DISABLED | DRIVE_S4, // 163 : SPI2_SSIN ->
|
||||
CFG_DISABLED | DRIVE_S4, // 164 : I2C0_SDA ->
|
||||
CFG_DISABLED | DRIVE_S4, // 165 : I2C0_SCL ->
|
||||
CFG_DISABLED | DRIVE_S4, // 166 : SPI3_SCLK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 167 : SPI3_MOSI ->
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED | DRIVE_S4, // 168 : SPI3_MISO ->
|
||||
CFG_DISABLED | DRIVE_S4, // 169 : SPI3_SSIN ->
|
||||
CFG_DISABLED | DRIVE_S4, // 170 : UART0_TXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 171 : UART0_RXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 172 : UART6_TXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 173 : UART6_RXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 174 : TMR32_PWM0 ->
|
||||
CFG_DISABLED | DRIVE_S4, // 175 : TMR32_PWM1 ->
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED | DRIVE_S4, // 176 : TMR32_PWM2 ->
|
||||
CFG_DISABLED | DRIVE_S4, // 177 : I2C1_SDA ->
|
||||
CFG_DISABLED | DRIVE_S4, // 178 : I2C1_SCL ->
|
||||
CFG_DISABLED | DRIVE_S4, // 179 : GPIO[19] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 180 : GPIO[20] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 181 : GPIO[21] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 182 : GPIO[22] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 183 : GPIO[23] ->
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED | DRIVE_S4, // 184 : GPIO[24] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 185 : GPIO[25] -> BOOT_CONFIG[1]
|
||||
CFG_IN | PULL_DOWN | DRIVE_S4, // 186 : GPIO[26] -> FORCE_DFU
|
||||
CFG_DISABLED | DRIVE_S4, // 187 : PSPI_MOSI ->
|
||||
CFG_DISABLED | DRIVE_S4, // 188 : DWI_DO ->
|
||||
CFG_DISABLED | DRIVE_S4, // 189 : PMGR_MISO ->
|
||||
CFG_DISABLED | DRIVE_S4, // 190 : PMGR_SCLK0 ->
|
||||
CFG_DISABLED | DRIVE_S4, // 191 : PMGR_SSCLK1 ->
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED | DRIVE_S4, // 192 : DROOP ->
|
||||
CFG_DISABLED | DRIVE_S4, // 193 : SOCHOT1 ->
|
||||
CFG_DISABLED | DRIVE_S4, // 194 : EDP_HPD0 ->
|
||||
CFG_DISABLED | DRIVE_S4, // 195 : EDP_HPD1 ->
|
||||
CFG_DISABLED | DRIVE_S4, // 196 : I2S3_MCK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 197 : I2S3_BCLK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 198 : I2S3_LRCK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 199 : I2S3_DOUT ->
|
||||
|
||||
/* Port 25 */
|
||||
CFG_DISABLED | DRIVE_S4, // 200 : I2S3_DIN ->
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_S4, // 201 : GPIO[27] -> DFU_STATUS
|
||||
CFG_DISABLED | DRIVE_S4, // 202 : GPIO[28] -> BOOT_CONFIG[2]
|
||||
CFG_DISABLED | DRIVE_S4, // 203 : GPIO[29] -> BOARD_ID[4]
|
||||
CFG_DISABLED | DRIVE_S4, // 204 : GPIO[30] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 205 : GPIO[31] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 206 : GPIO[32] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 207 : GPIO[33] ->
|
||||
|
||||
/* Port 26 */
|
||||
CFG_DISABLED | DRIVE_S4, // 208 : GPIO[34] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 209 : GPIO[35] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 210 : GPIO[36] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 211 : GPIO[37] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 212 : GPIO[38] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 213 : GPIO[39] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 214 : GPIO[40] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 215 : GPIO[41] ->
|
||||
|
||||
/* Port 27 */
|
||||
CFG_DISABLED | DRIVE_S4, // 216 : GPIO[42] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 217 : TST_CLKOUT ->
|
||||
CFG_DISABLED | DRIVE_S4, // 218 : GPU_TRIGGER1 ->
|
||||
CFG_DISABLED | DRIVE_S4, // 219 : GPU_TRIGGER2 ->
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
};
|
||||
|
||||
static const uint32_t gpio_1_default_cfg[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED | DRIVE_S4, // 0 : AOP_SPI_SCLK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 1 : AOP_SPI_MOSI ->
|
||||
CFG_DISABLED | DRIVE_S4, // 2 : AOP_SPI_MISO ->
|
||||
CFG_DISABLED | DRIVE_S4, // 3 : AOP_UART1_TXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 4 : AOP_UART1_RXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 5 : AOP_UART0_TXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 6 : AOP_UART0_RXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 7 : AOP_UART2_TXD ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED | DRIVE_S4, // 8 : AOP_UART2_RXD ->
|
||||
CFG_DISABLED | DRIVE_S4, // 9 : AOP_I2CM_SDA ->
|
||||
CFG_DISABLED | DRIVE_S4, // 10 : AOP_I2CM_SCL ->
|
||||
CFG_DISABLED | DRIVE_S4, // 11 : AOP_FUNC[0] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 12 : AOP_FUNC[1] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 13 : AOP_FUNC[2] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 14 : AOP_FUNC[3] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 15 : AOP_FUNC[4] ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED | DRIVE_S4, // 16 : AOP_FUNC[5] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 17 : AOP_FUNC[6] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 18 : AOP_FUNC[7] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 19 : AOP_FUNC[8] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 20 : AOP_FUNC[9] ->
|
||||
CFG_DISABLED | DRIVE_S4, // 21 : AOP_SWD_TCK_OUT ->
|
||||
CFG_DISABLED | DRIVE_S4, // 22 : AOP_SWD_TMS0 ->
|
||||
CFG_DISABLED | DRIVE_S4, // 23 : AOP_SWD_TMS1 ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED | DRIVE_S4, // 24 : AOP_I2S_MCK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 25 : AOP_I2S_BCLK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 26 : AOP_I2S_LRCK ->
|
||||
CFG_DISABLED | DRIVE_S4, // 27 : AOP_I2S_DIN ->
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
CFG_DISABLED | DRIVE_S4,
|
||||
};
|
||||
|
||||
#endif /* ! __PLATFORM_PINCONFIG_H */
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_SOC_CCC_H
|
||||
#define __PLATFORM_SOC_CCC_H
|
||||
|
||||
#define rCCC_CPU0_IMPL_IORVBAR (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + 0x000))
|
||||
#define rCCC_CPU0_IMPL_CPU_IOACC_CTL_EL3 (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + 0x008))
|
||||
#define rCCC_CPU0_IMPL_FED_ERR_STS (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + 0x010))
|
||||
#define rCCC_CPU0_IMPL_LSU_ERR_STS (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + 0x018))
|
||||
#define rCCC_CPU0_IMPL_MMU_ERR_STS (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + 0x020))
|
||||
|
||||
#define CCC0_IMPL_BASE_ADDR (CCC0_SYS_BASE_ADDR + 0x40000)
|
||||
#define rCCC_CCC_IMPL_CPM_IOACC_CTL_EL3 (*(volatile u_int64_t *)(CCC0_IMPL_BASE_ADDR + 0x000))
|
||||
#define rCCC_CCC_IMPL_L2C_ERR_STS (*(volatile u_int64_t *)(CCC0_IMPL_BASE_ADDR + 0x008))
|
||||
#define rCCC_CCC_IMPL_L2C_ERR_ADR (*(volatile u_int64_t *)(CCC0_IMPL_BASE_ADDR + 0x010))
|
||||
#define rCCC_CCC_IMPL_L2C_ERR_INF (*(volatile u_int64_t *)(CCC0_IMPL_BASE_ADDR + 0x018))
|
||||
|
||||
#define rCCC_CPU1_IMPL_IORVBAR (*(volatile u_int64_t *)(CCC_CPU1_SYS_BASE_ADDR + 0x000))
|
||||
#define rCCC_CPU2_IMPL_IORVBAR (*(volatile u_int64_t *)(CCC_CPU2_SYS_BASE_ADDR + 0x000))
|
||||
|
||||
#endif /* __PLATFORM_SOC_CCC_H */
|
||||
@@ -0,0 +1,167 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_CHIPID_H
|
||||
#define __PLATFORM_SOC_CHIPID_H
|
||||
|
||||
#include <platform/chipid.h>
|
||||
#include <platform/soc/pmgr.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include SUB_PLATFORM_SPDS_HEADER(minipmgr)
|
||||
|
||||
#define rCFG_FUSE0 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE0_OFFSET))
|
||||
#define rCFG_FUSE1 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE1_OFFSET))
|
||||
#define rCFG_FUSE2 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE2_OFFSET))
|
||||
#define rCFG_FUSE3 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE3_OFFSET))
|
||||
#define rCFG_FUSE4 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE4_OFFSET))
|
||||
#define rCFG_FUSE5 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE5_OFFSET))
|
||||
#define rCFG_FUSE9 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE9_OFFSET))
|
||||
|
||||
#define CFG_FUSE9_PLL_VCO_RCTRL_SEL (0x8) // VCO_RCTRL_OW value is valid if set
|
||||
#define CFG_FUSE9_PLL_VCO_RCTRL_OW_MASK (0x7) // PLL analog override value if valid
|
||||
|
||||
#define rECIDLO (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_ECID_FUSE0_OFFSET))
|
||||
#define rECIDHI (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_ECID_FUSE1_OFFSET))
|
||||
|
||||
#define rSEP_SECURITY (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_SEP_SECURITY_OFFSET))
|
||||
|
||||
#define rCFG_FUSE0_RAW (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE0_RAW_OFFSET))
|
||||
|
||||
#define BOARD_ID_NONE (0xff)
|
||||
#define J105_AP_BOARD_ID (0x04)
|
||||
#define J105_DEV_BOARD_ID (0x05)
|
||||
#define J98A_AP_BOARD_ID (0x10)
|
||||
#define J98A_DEV_BOARD_ID (0x11)
|
||||
#define J99A_AP_BOARD_ID (0x12)
|
||||
#define J99A_DEV_BOARD_ID (0x13)
|
||||
#define J127_AP_BOARD_ID (0x8)
|
||||
#define J127_DEV_BOARD_ID (0x9)
|
||||
#define J128_AP_BOARD_ID (0xA)
|
||||
#define J128_DEV_BOARD_ID (0xB)
|
||||
#define J111_AP_BOARD_ID (0x8)
|
||||
#define J111_DEV_BOARD_ID (0x9)
|
||||
#define J112_AP_BOARD_ID (0xA)
|
||||
#define J112_DEV_BOARD_ID (0xB)
|
||||
#define N69_AP_BOARD_ID (0x2)
|
||||
#define N69_DEV_BOARD_ID (0x3)
|
||||
#define N69U_AP_BOARD_ID (0x2)
|
||||
#define N69U_DEV_BOARD_ID (0x3)
|
||||
|
||||
enum chipid_voltage_index {
|
||||
CHIPID_SOC_VOLTAGE_BYPASS = 0,
|
||||
CHIPID_SOC_VOLTAGE_SECUREROM = 1,
|
||||
CHIPID_SOC_VOLTAGE_VMIN = 2,
|
||||
CHIPID_SOC_VOLTAGE_VNOM = 3,
|
||||
|
||||
CHIPID_CPU_VOLTAGE_BYPASS,
|
||||
CHIPID_CPU_VOLTAGE_SECUREROM,
|
||||
CHIPID_CPU_VOLTAGE_396,
|
||||
|
||||
CHIPID_CPU_VOLTAGE_600,
|
||||
CHIPID_CPU_VOLTAGE_912,
|
||||
CHIPID_CPU_VOLTAGE_1200,
|
||||
CHIPID_CPU_VOLTAGE_1512,
|
||||
CHIPID_CPU_VOLTAGE_1800,
|
||||
CHIPID_CPU_VOLTAGE_1848,
|
||||
CHIPID_CPU_VOLTAGE_1896,
|
||||
CHIPID_CPU_VOLTAGE_1992,
|
||||
CHIPID_CPU_VOLTAGE_2112,
|
||||
|
||||
CHIPID_CPU_VOLTAGE_396_WA,
|
||||
CHIPID_CPU_VOLTAGE_1200_WA,
|
||||
CHIPID_CPU_VOLTAGE_1512_WA,
|
||||
|
||||
CHIPID_CPU_VOLTAGE_720,
|
||||
CHIPID_CPU_VOLTAGE_1080,
|
||||
CHIPID_CPU_VOLTAGE_1440,
|
||||
CHIPID_CPU_VOLTAGE_2160,
|
||||
CHIPID_CPU_VOLTAGE_2256_1core,
|
||||
CHIPID_CPU_VOLTAGE_2256,
|
||||
CHIPID_CPU_VOLTAGE_2352,
|
||||
CHIPID_CPU_VOLTAGE_2448,
|
||||
|
||||
CHIPID_GPU_VOLTAGE_OFF,
|
||||
|
||||
CHIPID_GPU_VOLTAGE_340,
|
||||
CHIPID_GPU_VOLTAGE_474,
|
||||
CHIPID_GPU_VOLTAGE_550,
|
||||
CHIPID_GPU_VOLTAGE_723,
|
||||
CHIPID_GPU_VOLTAGE_616,
|
||||
CHIPID_GPU_VOLTAGE_804,
|
||||
CHIPID_GPU_VOLTAGE_850,
|
||||
CHIPID_GPU_VOLTAGE_900,
|
||||
|
||||
CHIPID_GPU_VOLTAGE_360,
|
||||
CHIPID_GPU_VOLTAGE_520,
|
||||
CHIPID_GPU_VOLTAGE_650,
|
||||
CHIPID_GPU_VOLTAGE_800,
|
||||
|
||||
CHIPID_VOLTAGE_FIXED,
|
||||
|
||||
CHIPID_ALL_VOLTAGE_LAST,
|
||||
};
|
||||
|
||||
enum chipid_voltage_type {
|
||||
CHIPID_CPU_VOLTAGE,
|
||||
CHIPID_GPU_VOLTAGE,
|
||||
CHIPID_SOC_VOLTAGE,
|
||||
};
|
||||
|
||||
uint32_t chipid_get_cpu_voltage(uint32_t index);
|
||||
|
||||
uint32_t chipid_get_cpu_sram_voltage(uint32_t index);
|
||||
|
||||
uint32_t chipid_get_soc_voltage(uint32_t index);
|
||||
|
||||
uint32_t chipid_get_gpu_voltage(uint32_t index);
|
||||
|
||||
uint32_t chipid_get_gpu_sram_voltage(uint32_t index);
|
||||
|
||||
uint32_t chipid_get_sram_voltage(uint32_t index);
|
||||
|
||||
int32_t chipid_get_cpu_temp_offset(uint32_t cpu_number);
|
||||
|
||||
uint32_t chipid_get_soc_temp_sensor_trim(uint32_t sensor_index);
|
||||
|
||||
uint32_t chipid_get_fuse_revision(void);
|
||||
|
||||
uint32_t chipid_get_total_rails_leakage();
|
||||
|
||||
uint32_t chipid_get_lpo_trim(void);
|
||||
|
||||
#if SUB_PLATFORM_S8000
|
||||
uint32_t chipid_get_pcie_txpll_vco_v2i_i_set(void);
|
||||
uint32_t chipid_get_pcie_txpll_vco_v2i_pi_set(void);
|
||||
uint32_t chipid_get_pcie_refpll_vco_v2i_i_set(void);
|
||||
uint32_t chipid_get_pcie_refpll_vco_v2i_pi_set(void);
|
||||
uint32_t chipid_get_pcie_rx_ldo(void);
|
||||
#elif SUB_PLATFORM_S8001 || SUB_PLATFORM_S8003
|
||||
uint32_t chipid_get_pcie_refpll_fcal_vco_digctrl(void);
|
||||
#endif
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
|
||||
#define FPGA_HAS_ALWAYS (1 << 0)
|
||||
#define FPGA_HAS_VXD (1 << 1)
|
||||
#define FPGA_HAS_AVE (1 << 2)
|
||||
#define FPGA_HAS_ISP (1 << 3)
|
||||
#define FPGA_HAS_DISP (1 << 4)
|
||||
#define FPGA_HAS_MSR (1 << 6)
|
||||
#define FPGA_HAS_JPEG (1 << 7)
|
||||
#define FPGA_HAS_GFX (1 << 8)
|
||||
#define FPGA_HAS_MEDIA (1 << 9)
|
||||
|
||||
#define rECID_FUSE3 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_ECID_FUSE3_OFFSET))
|
||||
|
||||
uint32_t chipid_get_fpga_block_instantiation(void);
|
||||
|
||||
#endif // SUPPORT_FPGA
|
||||
|
||||
#endif /* __PLATFORM_SOC_CHIPID_H */
|
||||
@@ -0,0 +1,11 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include SUB_PLATFORM_HEADER(soc/display)
|
||||
@@ -0,0 +1,122 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_H
|
||||
#define __APPLE_DISPLAY_H
|
||||
|
||||
// Platform-specific displaypipe tunables
|
||||
|
||||
// XXX - disp_dpcafclkgate is listed as TBD
|
||||
// D620 is most likely something new based on the values. Update once we know more.
|
||||
|
||||
static struct adfe_v2_tuneable adfe_tuneables[] =
|
||||
{
|
||||
#if DISPLAY_IPHONE_TUNABLES
|
||||
#if DISPLAY_D620_TUNABLES
|
||||
{
|
||||
.name = "D620",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x60) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x637),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x7f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x1b1d) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x635),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x62d),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x491),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x489),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x159) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQARRG_OPPORTUNISMENAB | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0) | \
|
||||
ADPAFDYNCLKGATEEN),
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
|
||||
#endif //DISPLAY_D620_TUNABLES
|
||||
|
||||
#if DISPLAY_D520_TUNABLES
|
||||
{
|
||||
.name = "D520",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x60) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x321),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x7f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x2d3a) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x31f),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x317),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x24d),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x245),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0xa6) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQARRG_OPPORTUNISMENAB | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0) | \
|
||||
ADPAFDYNCLKGATEEN),
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
#endif //DISPLAY_D520_TUNABLES
|
||||
|
||||
#if DISPLAY_D403_TUNABLES
|
||||
{
|
||||
.name = "D403",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x60) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x321),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x7f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x2d3a) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x31f),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x317),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x24d),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x245),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0xa6) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQARRG_OPPORTUNISMENAB | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0) | \
|
||||
ADPAFDYNCLKGATEEN),
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
|
||||
#endif //DISPLAY_D403_TUNABLES
|
||||
|
||||
#endif //DISPLAY_IPHONE_TUNABLES
|
||||
|
||||
};
|
||||
|
||||
|
||||
#endif /* ! __APPLE_DISPLAY_H */
|
||||
@@ -0,0 +1,194 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_H
|
||||
#define __APPLE_DISPLAY_H
|
||||
|
||||
// Platform-specific displaypipe tunables
|
||||
|
||||
// XXX - disp_dpcafclkgate is listed as TBD
|
||||
// D620 is most likely something new based on the values. Update once we know more.
|
||||
|
||||
static struct adfe_v2_tuneable adfe_tuneables[] =
|
||||
{
|
||||
//Tunables for targets using the the timing based on landscape ipads
|
||||
#if DISPLAY_LANDSCAPE_IPAD_TUNABLES || DISPLAY_FPGA_TUNABLES || DISPLAY_APPLE_TV_TUNABLES
|
||||
{
|
||||
.name = "ipad4",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x20) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x547),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0xff8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x15b5) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x545),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x53d),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x3a1),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x399),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x4b) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0x30) | \
|
||||
ADPAFDYNCLKGATEEN),
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
{
|
||||
.name = "ipad6",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x60) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x6c3),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x7f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0xaac) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x6c1),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x6b9),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x579),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x571),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNAGGR),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x1a9) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQARRG_OPPORTUNISMENAB | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0x0) | \
|
||||
ADPAFDYNCLKGATEEN),
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
{
|
||||
.name = "ipad6_A1",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x60) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x7a1),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x7f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0xaac) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x797),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x78f),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x725),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x71d),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNAGGR | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x131) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQARRG_OPPORTUNISMENAB | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0x0) | \
|
||||
ADPAFDYNCLKGATEEN),
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
{
|
||||
.name = "ipad6b",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x20) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x8ab),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x1ff0),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x3840) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x8aa),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x8a2),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x6b2),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x6aa),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x14f) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQARRG_OPPORTUNISMENAB | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0x30) | \
|
||||
ADPAFDYNCLKGATEEN),
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
{
|
||||
.name = "ipad6d",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x20) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0xe61),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x1ff0),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x3840) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0xe60),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0xe58),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0xb1a),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0xb12),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x29d) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQARRG_OPPORTUNISMENAB | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0x30) | \
|
||||
ADPAFDYNCLKGATEEN),
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
{
|
||||
.name = "720p",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x20) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x246),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x1ff0),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x3840) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x244),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x23c),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x1ac),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x1a4),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x59) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQARRG_OPPORTUNISMENAB | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0x30) | \
|
||||
ADPAFDYNCLKGATEEN),
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
#endif //DISPLAY_LANDSCAPE_IPAD_TUNABLES || DISPLAY_APPLE_TV_TUNABLES || DISPLAY_FPGA_TUNABLES
|
||||
};
|
||||
|
||||
#endif /* ! __APPLE_DISPLAY_H */
|
||||
@@ -0,0 +1,120 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_H
|
||||
#define __APPLE_DISPLAY_H
|
||||
|
||||
// Platform-specific displaypipe tunables
|
||||
|
||||
// XXX - disp_dpcafclkgate is listed as TBD
|
||||
// D620 is most likely something new based on the values. Update once we know more.
|
||||
|
||||
static struct adfe_v2_tuneable adfe_tuneables[] =
|
||||
{
|
||||
#if DISPLAY_IPHONE_TUNABLES
|
||||
#if DISPLAY_D620_TUNABLES
|
||||
{
|
||||
.name = "D620",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x60) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x637),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x7f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x1b1d) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x635),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x62d),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x491),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x489),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x159) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQARRG_OPPORTUNISMENAB | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0) | \
|
||||
ADPAFDYNCLKGATEEN),
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
|
||||
#endif //DISPLAY_D620_TUNABLES
|
||||
|
||||
#if DISPLAY_D520_TUNABLES
|
||||
{
|
||||
.name = "D520",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x60) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x321),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x7f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x2d3a) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x31f),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x317),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x24d),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x245),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0xa6) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQARRG_OPPORTUNISMENAB | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0) | \
|
||||
ADPAFDYNCLKGATEEN),
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
#endif //DISPLAY_D520_TUNABLES
|
||||
|
||||
#if DISPLAY_D403_TUNABLES
|
||||
{
|
||||
.name = "D403",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x60) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x321),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x7f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x2d3a) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x31f),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x317),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x24d),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x245),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0xa6) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQARRG_OPPORTUNISMENAB | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0) | \
|
||||
ADPAFDYNCLKGATEEN),
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
|
||||
#endif //DISPLAY_D403_TUNABLES
|
||||
#endif //DISPLAY_IPHONE_TUNABLES
|
||||
};
|
||||
|
||||
|
||||
#endif /* ! __APPLE_DISPLAY_H */
|
||||
@@ -0,0 +1,202 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_TIMINGS_H
|
||||
#define __APPLE_DISPLAY_TIMINGS_H
|
||||
|
||||
//Supported timings by this platform
|
||||
static struct display_timing timing_list[] =
|
||||
{
|
||||
#if DEBUG_BUILD || TARGET_DISPLAY_D520
|
||||
{
|
||||
.display_name = "D520",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 100000000,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 750,
|
||||
.h_pulse_width = 32,
|
||||
.h_back_porch = 4,
|
||||
.h_front_porch = 102,
|
||||
.v_active = 1334,
|
||||
.v_pulse_width = 3,
|
||||
.v_back_porch = 4,
|
||||
.v_front_porch = 536,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_PINOT,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || TARGET_DISPLAY_D620
|
||||
{
|
||||
.display_name = "D620",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 200000000,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 1080,
|
||||
.h_pulse_width = 32,
|
||||
.h_back_porch = 4,
|
||||
.h_front_porch = 116,
|
||||
.v_active = 1920,
|
||||
.v_pulse_width = 3,
|
||||
.v_back_porch = 5,
|
||||
.v_front_porch = 778,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_PINOT,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || TARGET_DISPLAY_D403
|
||||
{
|
||||
.display_name = "D403",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 61540000,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 640,
|
||||
.h_pulse_width = 32,
|
||||
.h_back_porch = 4,
|
||||
.h_front_porch = 6,
|
||||
.v_active = 1136,
|
||||
.v_pulse_width = 3,
|
||||
.v_back_porch = 13,
|
||||
.v_front_porch = 352,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_PINOT,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || SUB_TARGET_S8000FPGA || SUB_TARGET_S8001FPGA
|
||||
{
|
||||
.display_name = "fpga-wsvga",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 5000000,
|
||||
.dot_pitch = 243,
|
||||
.h_active = 1024,
|
||||
.h_pulse_width = 50,
|
||||
.h_back_porch = 50,
|
||||
.h_front_porch = 51,
|
||||
.v_active = 600,
|
||||
.v_pulse_width = 50,
|
||||
.v_back_porch = 218,
|
||||
.v_front_porch = 6,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 18,
|
||||
.display_type = DISPLAY_TYPE_DUMB,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || SUB_TARGET_S8001SIM
|
||||
{
|
||||
.display_name = "ipad4",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 200000000,
|
||||
.dot_pitch = 264,
|
||||
.h_active = 1536,
|
||||
.h_pulse_width = 15,
|
||||
.h_back_porch = 52,
|
||||
.h_front_porch = 16,
|
||||
.v_active = 2048,
|
||||
.v_pulse_width = 1,
|
||||
.v_back_porch = 3,
|
||||
.v_front_porch = 7,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_EDP,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || SUB_TARGET_J127 || SUB_TARGET_J128
|
||||
{
|
||||
.display_name = "ipad6",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 240000000,
|
||||
.dot_pitch = 264,
|
||||
.h_active = 1536,
|
||||
.h_pulse_width = 32,
|
||||
.h_back_porch = 4,
|
||||
.h_front_porch = 126,
|
||||
.v_active = 2048,
|
||||
.v_pulse_width = 2,
|
||||
.v_back_porch = 4,
|
||||
.v_front_porch = 302,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_EDP,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || SUB_TARGET_J98A || SUB_TARGET_J99A
|
||||
{
|
||||
.display_name = "ipad6d",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 400000000,
|
||||
.dot_pitch = 264,
|
||||
.h_active = 2732,
|
||||
.h_pulse_width = 20,
|
||||
.h_back_porch = 56,
|
||||
.h_front_porch = 16,
|
||||
.v_active = 2048,
|
||||
.v_pulse_width = 2,
|
||||
.v_back_porch = 4,
|
||||
.v_front_porch = 307, // No IFP
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_EDP,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || WITH_HW_DISPLAY_DISPLAYPORT
|
||||
{
|
||||
.display_name = "720p",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 74250000,
|
||||
.dot_pitch = 243,
|
||||
.h_active = 1280,
|
||||
.h_pulse_width = 40,
|
||||
.h_back_porch = 110,
|
||||
.h_front_porch = 220,
|
||||
.v_active = 720,
|
||||
.v_pulse_width = 5,
|
||||
.v_back_porch = 5,
|
||||
.v_front_porch = 20,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_DP,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
#endif /* ! __APPLE_DISPLAY_TIMINGS_H */
|
||||
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_DVFMPERF_H
|
||||
#define __PLATFORM_SOC_DVFMPERF_H
|
||||
#include <platform/soc/chipid.h>
|
||||
|
||||
enum chipid_voltage_index dvfmperf_get_voltage_index(uint32_t index, enum chipid_voltage_type voltage_type);
|
||||
|
||||
#endif /* __PLATFORM_SOC_DVFMPERF_H */
|
||||
@@ -0,0 +1,278 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWCLOCKS_H
|
||||
#define __PLATFORM_SOC_HWCLOCKS_H
|
||||
|
||||
#include <platform.h>
|
||||
#include <platform/clocks.h>
|
||||
#include SUB_PLATFORM_SPDS_HEADER(pmgr)
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define OSC_FREQ (5000000UL)
|
||||
#define LPO_FREQ (OSC_FREQ)
|
||||
#else
|
||||
#define OSC_FREQ (24000000UL)
|
||||
#define LPO_FREQ (192000000UL)
|
||||
#endif
|
||||
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
/*
|
||||
* S8000 clock gate devices.
|
||||
*/
|
||||
enum {
|
||||
// Mini-PMGR
|
||||
CLK_AOP = HWCLOCK_BASE,
|
||||
CLK_DEBUG,
|
||||
CLK_AOP_GPIO,
|
||||
CLK_AOP_UART0,
|
||||
CLK_AOP_UART1,
|
||||
CLK_AOP_UART2,
|
||||
CLK_AOP_I2CM,
|
||||
CLK_AOP_MCA0,
|
||||
CLK_AOP_CPU,
|
||||
CLK_AOP_FILTER,
|
||||
CLK_AOP_BUSIF,
|
||||
|
||||
// PMGR
|
||||
CLK_SBR,
|
||||
CLK_AIC,
|
||||
CLK_DWI,
|
||||
CLK_GPIO,
|
||||
CLK_PMS,
|
||||
CLK_HSIC0PHY,
|
||||
CLK_HSIC1PHY,
|
||||
CLK_ISPSENS0,
|
||||
CLK_ISPSENS1,
|
||||
CLK_PCIE_REF,
|
||||
CLK_SIO_BUSIF,
|
||||
CLK_SIO_P,
|
||||
CLK_SIO,
|
||||
CLK_MCA0,
|
||||
CLK_MCA1,
|
||||
CLK_MCA2,
|
||||
CLK_MCA3,
|
||||
CLK_MCA4,
|
||||
CLK_PWM0,
|
||||
CLK_I2C0,
|
||||
CLK_I2C1,
|
||||
CLK_I2C2,
|
||||
CLK_I2C3,
|
||||
CLK_SPI0,
|
||||
CLK_SPI1,
|
||||
CLK_SPI2,
|
||||
CLK_SPI3,
|
||||
CLK_UART0,
|
||||
CLK_UART1,
|
||||
CLK_UART2,
|
||||
CLK_UART3,
|
||||
CLK_UART4,
|
||||
CLK_UART5,
|
||||
CLK_UART6,
|
||||
CLK_UART7,
|
||||
CLK_UART8,
|
||||
CLK_AES0,
|
||||
CLK_MCC,
|
||||
CLK_DCS0,
|
||||
CLK_DCS1,
|
||||
CLK_DCS2,
|
||||
CLK_DCS3,
|
||||
CLK_USB,
|
||||
CLK_USBCTLREG,
|
||||
CLK_USB2HOST0,
|
||||
CLK_USB2HOST0_OHCI,
|
||||
CLK_USB2HOST1,
|
||||
CLK_USB2HOST1_OHCI,
|
||||
CLK_USB2HOST2,
|
||||
CLK_USB2HOST2_OHCI,
|
||||
CLK_USB_OTG,
|
||||
CLK_SMX,
|
||||
CLK_SF,
|
||||
CLK_RTMUX,
|
||||
CLK_DISP0,
|
||||
CLK_MIPI_DSI,
|
||||
CLK_MIPI = CLK_MIPI_DSI,
|
||||
CLK_DP,
|
||||
CLK_EDPLINK = CLK_DP,
|
||||
CLK_DPLINK = CLK_DP,
|
||||
CLK_ISP,
|
||||
CLK_MEDIA,
|
||||
CLK_JPG,
|
||||
CLK_MSR,
|
||||
CLK_PMP,
|
||||
CLK_PMS_SRAM,
|
||||
CLK_VDEC0,
|
||||
CLK_VENC_CPU,
|
||||
CLK_PCIE,
|
||||
CLK_PCIE_AUX,
|
||||
CLK_PCIE_LINK0,
|
||||
CLK_PCIE_LINK1,
|
||||
CLK_PCIE_LINK2,
|
||||
CLK_PCIE_LINK3,
|
||||
CLK_GFX,
|
||||
|
||||
// Unmanaged
|
||||
CLK_CPU0,
|
||||
CLK_CPU1,
|
||||
CLK_CPM,
|
||||
CLK_SEP,
|
||||
CLK_VENC_PIPE,
|
||||
CLK_VENC_ME0,
|
||||
CLK_VENC_ME1,
|
||||
|
||||
CLK_LAST,
|
||||
};
|
||||
|
||||
#elif SUB_PLATFORM_S8001
|
||||
/*
|
||||
* S8001 clock gate devices.
|
||||
*/
|
||||
enum {
|
||||
// Mini-PMGR
|
||||
CLK_AOP = HWCLOCK_BASE,
|
||||
CLK_DEBUG,
|
||||
CLK_AOP_GPIO,
|
||||
CLK_AOP_UART0,
|
||||
CLK_AOP_UART1,
|
||||
CLK_AOP_UART2,
|
||||
CLK_AOP_I2CM,
|
||||
CLK_AOP_MCA0,
|
||||
CLK_AOP_CPU,
|
||||
CLK_AOP_FILTER,
|
||||
CLK_AOP_BUSIF,
|
||||
|
||||
// PMGR
|
||||
CLK_SBR,
|
||||
CLK_AIC,
|
||||
CLK_DWI,
|
||||
CLK_GPIO,
|
||||
CLK_PMS,
|
||||
CLK_HSIC0PHY,
|
||||
CLK_ISPSENS0,
|
||||
CLK_ISPSENS1,
|
||||
CLK_PCIE_REF,
|
||||
CLK_SIO_BUSIF,
|
||||
CLK_SIO_P,
|
||||
CLK_SIO,
|
||||
CLK_MCA0,
|
||||
CLK_MCA1,
|
||||
CLK_MCA2,
|
||||
CLK_MCA3,
|
||||
CLK_MCA4,
|
||||
CLK_PWM0,
|
||||
CLK_I2C0,
|
||||
CLK_I2C1,
|
||||
CLK_I2C2,
|
||||
CLK_I2C3,
|
||||
CLK_SPI0,
|
||||
CLK_SPI1,
|
||||
CLK_SPI2,
|
||||
CLK_SPI3,
|
||||
CLK_UART0,
|
||||
CLK_UART1,
|
||||
CLK_UART2,
|
||||
CLK_UART3,
|
||||
CLK_UART4,
|
||||
CLK_UART5,
|
||||
CLK_UART6,
|
||||
CLK_UART7,
|
||||
CLK_UART8,
|
||||
CLK_AES0,
|
||||
CLK_DPA0,
|
||||
CLK_DPA1,
|
||||
CLK_MCC,
|
||||
CLK_DCS0,
|
||||
CLK_DCS1,
|
||||
CLK_DCS2,
|
||||
CLK_DCS3,
|
||||
CLK_DCS4,
|
||||
CLK_DCS5,
|
||||
CLK_DCS6,
|
||||
CLK_DCS7,
|
||||
CLK_USB,
|
||||
CLK_USBCTLREG,
|
||||
CLK_USB2HOST0,
|
||||
CLK_USB2HOST0_OHCI,
|
||||
CLK_USB2HOST1,
|
||||
CLK_USB2HOST1_OHCI,
|
||||
CLK_USB2HOST2,
|
||||
CLK_USB2HOST2_OHCI,
|
||||
CLK_USB_OTG,
|
||||
CLK_SMX,
|
||||
CLK_SF,
|
||||
CLK_RTMUX,
|
||||
CLK_DISP0,
|
||||
CLK_DP0,
|
||||
CLK_EDPLINK = CLK_DP0,
|
||||
CLK_DPLINK = CLK_DP0,
|
||||
CLK_DISP1MUX,
|
||||
CLK_DISP1,
|
||||
CLK_DP1,
|
||||
CLK_ISP,
|
||||
CLK_MEDIA,
|
||||
CLK_JPG,
|
||||
CLK_MSR,
|
||||
CLK_PMP,
|
||||
CLK_PMS_SRAM,
|
||||
CLK_VDEC0,
|
||||
CLK_VENC_CPU,
|
||||
CLK_PCIE,
|
||||
CLK_PCIE_AUX,
|
||||
CLK_PCIE_LINK0,
|
||||
CLK_PCIE_LINK1,
|
||||
CLK_PCIE_LINK2,
|
||||
CLK_PCIE_LINK3,
|
||||
CLK_PCIE_LINK4,
|
||||
CLK_PCIE_LINK5,
|
||||
CLK_GFX,
|
||||
CLK_SRS,
|
||||
|
||||
// Unmanaged
|
||||
CLK_CPU0,
|
||||
CLK_CPU1,
|
||||
CLK_CPM,
|
||||
CLK_SEP,
|
||||
CLK_VENC_PIPE,
|
||||
CLK_VENC_ME0,
|
||||
CLK_VENC_ME1,
|
||||
|
||||
CLK_LAST,
|
||||
};
|
||||
#endif
|
||||
|
||||
#define PMGR_DEVICE_INDEX(_clk) ((_clk) - HWCLOCK_BASE)
|
||||
#define PMGR_DEVICE_COUNT (CLK_LAST - HWCLOCK_BASE)
|
||||
|
||||
#define PMGR_FIRST_DEVICE CLK_AOP
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
#define PMGR_LAST_DEVICE CLK_GFX
|
||||
#elif SUB_PLATFORM_S8001
|
||||
#define PMGR_LAST_DEVICE CLK_SRS
|
||||
#else
|
||||
#error Unknown Platform
|
||||
#endif
|
||||
|
||||
#define PMGR_VALID_DEVICE(_clk) ((_clk) >= PMGR_FIRST_DEVICE && (_clk) <= PMGR_LAST_DEVICE)
|
||||
|
||||
// Legacy clocks, no associated device or PS register
|
||||
enum {
|
||||
CLK_FCLK = CLK_LAST,
|
||||
CLK_ACLK,
|
||||
CLK_HCLK,
|
||||
CLK_PCLK,
|
||||
CLK_VCLK0,
|
||||
CLK_VCLK1,
|
||||
CLK_MCLK,
|
||||
CLK_NCLK,
|
||||
CLK_USBPHYCLK,
|
||||
CLK_NCOREF,
|
||||
};
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWCLOCKS_H */
|
||||
@@ -0,0 +1,564 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWISR_H
|
||||
#define __PLATFORM_SOC_HWISR_H
|
||||
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
|
||||
#define INT_SW0 0 // Software 0 Interrupt
|
||||
#define INT_SW1 1 // Software 1 Interrupt
|
||||
#define INT_SW2 2 // Software 2 Interrupt
|
||||
#define INT_SW3 3 // Software 3 Interrupt
|
||||
#define INT_WDT 4 // Watchdog Timer Interrupt
|
||||
#define INT_DWI1 5 // DWI Interrupt
|
||||
#define INT_DWI2 6 // DWI Interrupt
|
||||
#define INT_PMGR_PERF_CNTRS 7 // PMGR Performace Counters Interrupt
|
||||
#define INT_THERM_TEMP0 8 // Thermal Temp 0 Interrupt
|
||||
#define INT_THERM_ALARM0 9 // Thermal Alarm 0 Interrupt
|
||||
#define INT_THERM_TEMP1 10 // Thermal Temp 1 Interrupt
|
||||
#define INT_THERM_ALARM1 11 // Thermal Alarm 1 Interrupt
|
||||
#define INT_THERM_TEMP2 12 // Thermal Temp 2 Interrupt
|
||||
#define INT_THERM_ALARM2 13 // Thermal Alarm 2 Interrupt
|
||||
|
||||
// Reserved 14 - 15
|
||||
|
||||
#define INT_CPM_THERM_TEMP 16 // CPM Thermal temp Interrupt
|
||||
#define INT_CPM_THERM_ALARM 17 // CPM Thermal alarm Interrupt
|
||||
#define INT_CPU0_THERM_TEMP 18 // CPU0 Thermal temp Interrupt
|
||||
#define INT_CPU0_THERM_ALARM 19 // CPU0 Thermal alarm Interrupt
|
||||
#define INT_CPU1_THERM_TEMP 20 // CPU1 Thermal temp Interrupt
|
||||
#define INT_CPU1_THERM_ALARM 21 // CPU1 Thermal alarm Interrupt
|
||||
|
||||
// Reserved 21 - 26
|
||||
|
||||
#define INT_THERM_FS_ACT0 27 // Thermal Failsafe Active 0 Interrupt
|
||||
#define INT_THERM_FS_ACT1 28 // Thermal Failsafe Active 1 Interrupt
|
||||
#define INT_THERM_FS_EXT0 29 // Thermal Failsafe Exit 0 Interrupt
|
||||
#define INT_THERM_FS_EXT1 30 // Thermal Failsafe Exit 1 Interrupt
|
||||
#define INT_SOC_THERM_FS_ACT0 31 // SoC Thermal Failsafe Active 0 Interrupt
|
||||
#define INT_SOC_THERM_FS_ACT1 32 // SoC Thermal Failsafe Active 1 Interrupt
|
||||
|
||||
// Reserved 33 - 34
|
||||
|
||||
#define INT_CTM_TRIGGER0 35 // CTM Trigger 0 Interrupt
|
||||
#define INT_CTM_TRIGGER1 36 // CTM Trigger 1 Interrupt
|
||||
#define INT_CTM_TRIGGER2 37 // CTM Trigger 2 Interrupt
|
||||
#define INT_CTM_TRIGGER3 38 // CTM Trigger 3 Interrupt
|
||||
#define INT_COHERENCE_PNT_ERR 39 // Coherence Point Error Interrupt
|
||||
#define INT_COHERENCE_PNT_PERF_CNTRS 40 // Coherence Point Performance Counters Interrupt
|
||||
|
||||
// Reserved 41
|
||||
|
||||
#define INT_GPIO_CLASS0 42 // GPIO Class 0 Interrupt
|
||||
#define INT_GPIO_CLASS1 43 // GPIO Class 1 Interrupt
|
||||
#define INT_GPIO_CLASS2 44 // GPIO Class 2 Interrupt
|
||||
#define INT_GPIO_CLASS3 45 // GPIO Class 3 Interrupt
|
||||
#define INT_GPIO_CLASS4 46 // GPIO Class 4 Interrupt
|
||||
#define INT_GPIO_CLASS5 47 // GPIO Class 5 Interrupt
|
||||
#define INT_GPIO_CLASS6 48 // GPIO Class 6 Interrupt
|
||||
|
||||
// Reserved 49-58
|
||||
|
||||
#define INT_MEM_CONTROLLER0 59 // Memory Controller MCC Interrupt
|
||||
#define INT_MEM_CONTROLLER1 60 // Memory Controller MCC Interrupt
|
||||
// XXX: TBD DSC interrupts
|
||||
|
||||
// Reserved 73
|
||||
|
||||
#define INT_CPU0_COMM_TX 74 // CPU 0 COMM TX Interrupt
|
||||
#define INT_CPU0_COMM_RX 75 // CPU 0 COMM RX Interrupt
|
||||
#define INT_CPU0_PMU_IRQ 76 // CPU 0 PMU IRQ Interrupt
|
||||
#define INT_CPU1_COMM_TX 77 // CPU 1 COMM TX Interrupt
|
||||
#define INT_CPU1_COMM_RX 78 // CPU 1 COMM RX Interrupt
|
||||
#define INT_CPU1_PMU_IRQ 79 // CPU 1 PMU IRQ Interrupt
|
||||
|
||||
// Reserved 80 - 85
|
||||
|
||||
#define INT_CCC_UNIFIED_TRIGGER 86 // CCC Unified Trigger Interrupt
|
||||
|
||||
// Reserved 87
|
||||
|
||||
#define INT_ISP_KF_INBOX_EMPTY 88 // ISP KF Inbox Empty Interrupt
|
||||
#define INT_ISP_KF_INBOX_NOTEMPTY 89 // ISP KF Inbox Not Empty Interrupt
|
||||
#define INT_ISP_KF_OUTBOX_EMPTY 90 // ISP KF Outbox Empty Interrupt
|
||||
#define INT_ISP_KF_OUTBOX_NOTEMPTY 91 // ISP KF Outbox Not Empty Interrupt
|
||||
#define INT_ISP0 92 // ISP 0 Interrupt
|
||||
#define INT_ISP1 93 // ISP 1 Interrupt
|
||||
#define INT_ISP2 94 // ISP 2 Interrupt
|
||||
#define INT_ISP3 95 // ISP 3 Interrupt
|
||||
#define INT_ISP_DART 96 // ISP DART Interrupt
|
||||
|
||||
// Reserved 97
|
||||
|
||||
#define INT_SEP_KF_INBOX_EMPTY 98 // SEP KF Inbox Empty Interrupt
|
||||
#define INT_SEP_KF_INBOX_NOTEMPTY 99 // SEP KF Inbox Not Empty Interrupt
|
||||
#define INT_SEP_KF_OUTBOX_EMPTY 100 // SEP KF Outbox Empty Interrupt
|
||||
#define INT_SEP_KF_OUTBOX_NOTEMPTY 101 // SEP KF Outbox Not Empty Interrupt
|
||||
#define INT_SEP_AUTH_ERROR 102 // SEP Authentication Error Interrupt
|
||||
#define INT_SEP_CRIT_PATH_MONITOR 103 // SEP Critical Path Monitor Interrupt
|
||||
|
||||
// Reserved 104 - 105
|
||||
|
||||
// XXX JF: AOP interrupts
|
||||
|
||||
// Reserved 138 - 139
|
||||
|
||||
#define INT_DISP0 140 // Display 0 Interrupt
|
||||
#define INT_DISP0_DART 141 // Display 0 DART Interrupt
|
||||
#define INT_DISP0_SMMU 142 // Display 0 SMMU Interrupt
|
||||
#define INT_DISP0_BACK_END_BLU 143 // Display 0 Back End Back Light Update Interrupt
|
||||
#define INT_DISP0_BACK_END_VBI 144 // Display 0 Back End VBI Interrupt
|
||||
#define INT_DISP0_BACK_END_VFTG 145 // Display 0 Back End VFTG Idle Interrupt
|
||||
#define INT_DISP0_BACK_END_VBL 146 // Display 0 Back End VBL counter Interrupt
|
||||
#define INT_MIPIDSI0 147 // MIPI DSI 0 Interrupt
|
||||
#define INT_MIPIDSI1 148 // MIPI DSI 1 Interrupt
|
||||
#define INT_DISPLAY_PORT 149 // Display Port
|
||||
#define INT_EDP0 INT_DISPLAY_PORT
|
||||
#define INT_DPORT0 INT_DISPLAY_PORT
|
||||
|
||||
// Reserved 151
|
||||
|
||||
// XXX: PMP
|
||||
|
||||
// Reserved 156
|
||||
|
||||
#define INT_VDEC0 157 // Video Decoder 0 Interrupt
|
||||
|
||||
// Reserved 158
|
||||
|
||||
#define INT_AVE_KF_INBOX_EMPTY 159 // AVE KF Inbox Empty Interrupt
|
||||
#define INT_AVE_KF_INBOX_NOTEMPTY 160 // AVE KF Inbox Not Empty Interrupt
|
||||
#define INT_AVE_KF_OUTBOX_EMPTY 161 // AVE KF Outbox Empty Interrupt
|
||||
#define INT_AVE_KF_OUTBOX_NOTEMPTY 162 // AVE KF Outbox Not Empty Interrupt
|
||||
#define INT_AVE_DART 163 // AVE DART Interrupt
|
||||
#define INT_AVE_SMMU 164 // AVE SMMU Interrupt
|
||||
#define INT_AVE 165 // AVE Interrupt
|
||||
#define INT_SVE_SYNC 166 // SVE Driver Synchronization Interrupt
|
||||
|
||||
// Reserved 167 - 169
|
||||
|
||||
#define INT_GFX 170 // GFX Interrupt
|
||||
#define INT_GFX_SLEEP 171 // GFX Sleep Interrupt
|
||||
#define INT_GFX_WAKE 172 // GFX Wake Interrupt
|
||||
#define INT_GFX_CHG 173 // GFX Change Interrupt
|
||||
|
||||
// Reserved 174
|
||||
|
||||
#define INT_JPEG 175 // JPEG Interrupt
|
||||
#define INT_JPEG_DART 176 // JPEG DART Interrupt
|
||||
#define INT_JPEG_DART_PERF 177 // JPEG DART Performance Interrupt
|
||||
|
||||
// Reserved 178
|
||||
|
||||
#define INT_MSR 179 // MSR Interrupt
|
||||
#define INT_MSR_SMMU 180 // MSR SMMU Interrupt
|
||||
#define INT_MSR_DART 181 // MSR DART Interrupt
|
||||
#define INT_MSR_DAR_PERF 182 // MSR DART Performance Interrupt
|
||||
|
||||
// Reserved 183
|
||||
|
||||
#define INT_SIO_KF_INBOX_EMPTY 184 // SIO KF Inbox Empty Interrupt
|
||||
#define INT_SIO_KF_INBOX_NOTEMPTY 185 // SIO KF Inbox Not Empty Interrupt
|
||||
#define INT_SIO_KF_OUTBOX_EMPTY 186 // SIO KF Outbox Empty Interrupt
|
||||
#define INT_SIO_KF_OUTBOX_NOTEMPTY 187 // SIO KF Outbox Not Empty Interrupt
|
||||
#define INT_SPI0 188 // SPI 0 Interrupt
|
||||
#define INT_SPI1 189 // SPI 1 Interrupt
|
||||
#define INT_SPI2 190 // SPI 2 Interrupt
|
||||
#define INT_SPI3 191 // SPI 3 Interrupt
|
||||
#define INT_UART0 192 // UART 0 Interrupt
|
||||
#define INT_UART1 193 // UART 1 Interrupt
|
||||
#define INT_UART2 194 // UART 2 Interrupt
|
||||
#define INT_UART3 195 // UART 3 Interrupt
|
||||
#define INT_UART4 196 // UART 4 Interrupt
|
||||
#define INT_UART5 197 // UART 5 Interrupt
|
||||
#define INT_UART6 198 // UART 6 Interrupt
|
||||
#define INT_UART7 199 // UART 7 Interrupt
|
||||
#define INT_UART8 200 // UART 8 Interrupt
|
||||
#define INT_MCA0 201 // Multi-Channel Audio 0 Interrupt
|
||||
#define INT_MCA1 202 // Multi-Channel Audio 1 Interrupt
|
||||
#define INT_MCA2 203 // Multi-Channel Audio 2 Interrupt
|
||||
#define INT_MCA3 204 // Multi-Channel Audio 3 Interrupt
|
||||
#define INT_MCA4 205 // Multi-Channel Audio 4 Interrupt
|
||||
#define INT_IIC0 206 // I2C 0 Interrupt
|
||||
#define INT_IIC1 207 // I2C 1 Interrupt
|
||||
#define INT_IIC2 208 // I2C 2 Interrupt
|
||||
#define INT_IIC3 209 // I2C 3 Interrupt
|
||||
#define INT_PWM 210 // PWM Interrupt
|
||||
#define INT_AES0 211 // AES 0 Interrupt
|
||||
|
||||
// Reserved 212 - 213
|
||||
|
||||
#define INT_USB_OTG 214 // USB OTG Interrupt
|
||||
#define INT_USB2HOST0_EHCI 215 // USB EHCI 0 Interrupt
|
||||
#define INT_USB2HOST0_OHCI 216 // USB OHCI 0 Interrupt
|
||||
#define INT_USB2HOST1_EHCI 217 // USB EHCI 1 Interrupt
|
||||
#define INT_USB2HOST2_EHCI 218 // USB EHCI 2 Interrupt
|
||||
#define INT_USBOTG_RESUME 219 // USB OTG Resume Interrupt
|
||||
#define INT_USB_20_BATT_CHRG_DET 220 // USB 2.0 Battery Charge Detect Interrupt
|
||||
#define INT_USB2HOST0_PHY_RESUME 221 // USB Host 0 Resume Interrupt
|
||||
#define INT_USB2HOST1_PHY_RESUME 222 // USB Host 1 Resume Interrupt
|
||||
#define INT_USB2HOST2_PHY_RESUME 223 // USB Host 2 Resume Interrupt
|
||||
#define INT_OTG_IN_EP0 224 // OTG IN Endpoint 0 Interrupt
|
||||
#define INT_OTG_IN_EP1 225 // OTG IN Endpoint 1 Interrupt
|
||||
#define INT_OTG_IN_EP2 226 // OTG IN Endpoint 2 Interrupt
|
||||
#define INT_OTG_IN_EP3 227 // OTG IN Endpoint 3 Interrupt
|
||||
#define INT_OTG_IN_EP4 228 // OTG IN Endpoint 4 Interrupt
|
||||
#define INT_OTG_IN_EP5 229 // OTG IN Endpoint 5 Interrupt
|
||||
#define INT_OTG_IN_EP6 230 // OTG IN Endpoint 6 Interrupt
|
||||
#define INT_OTG_IN_EP7 231 // OTG IN Endpoint 7 Interrupt
|
||||
#define INT_OTG_IN_EP8 232 // OTG IN Endpoint 8 Interrupt
|
||||
#define INT_OTG_OUT_EP0 233 // OTG OUT Endpoint 0 Interrupt
|
||||
#define INT_OTG_OUT_EP1 234 // OTG OUT Endpoint 1 Interrupt
|
||||
#define INT_OTG_OUT_EP2 235 // OTG OUT Endpoint 2 Interrupt
|
||||
#define INT_OTG_OUT_EP3 236 // OTG OUT Endpoint 3 Interrupt
|
||||
#define INT_OTG_OUT_EP4 237 // OTG OUT Endpoint 4 Interrupt
|
||||
#define INT_OTG_OUT_EP5 238 // OTG OUT Endpoint 5 Interrupt
|
||||
#define INT_OTG_OUT_EP6 239 // OTG OUT Endpoint 6 Interrupt
|
||||
#define INT_OTG_OUT_EP7 240 // OTG OUT Endpoint 7 Interrupt
|
||||
#define INT_OTG_OUT_EP8 241 // OTG OUT Endpoint 8 Interrupt
|
||||
|
||||
// Reserved 242 - 243
|
||||
|
||||
#define PCIE_LINK0 244 // PCIE Link 0 Interrupt
|
||||
#define PCIE_LINK0_DART 245 // PCIE Link 0 DART Interrupt
|
||||
#define PCIE_LINK0_MMU 246 // PCIE Link 0 MMU Interrupt
|
||||
#define PCIE_LINK1 247 // PCIE Link 1 Interrupt
|
||||
#define PCIE_LINK1_DART 248 // PCIE Link 1 DART Interrupt
|
||||
#define PCIE_LINK1_MMU 249 // PCIE Link 1 MMU Interrupt
|
||||
#define PCIE_LINK2 250 // PCIE Link 1 Interrupt
|
||||
#define PCIE_LINK2_DART 251 // PCIE Link 1 DART Interrupt
|
||||
#define PCIE_LINK2_MMU 252 // PCIE Link 1 MMU Interrupt
|
||||
#define PCIE_LINK3 253 // PCIE Link 1 Interrupt
|
||||
#define PCIE_LINK3_DART 254 // PCIE Link 1 DART Interrupt
|
||||
#define PCIE_LINK3_MMU 255 // PCIE Link 1 MMU Interrupt
|
||||
|
||||
#define PCIE_MSI0 256 // PCIE MSI 0 Interrupt
|
||||
#define PCIE_MSI1 257 // PCIE MSI 1 Interrupt
|
||||
#define PCIE_MSI2 258 // PCIE MSI 2 Interrupt
|
||||
#define PCIE_MSI3 259 // PCIE MSI 3 Interrupt
|
||||
#define PCIE_MSI4 260 // PCIE MSI 4 Interrupt
|
||||
#define PCIE_MSI5 261 // PCIE MSI 5 Interrupt
|
||||
#define PCIE_MSI6 262 // PCIE MSI 6 Interrupt
|
||||
#define PCIE_MSI7 263 // PCIE MSI 7 Interrupt
|
||||
#define PCIE_MSI8 264 // PCIE MSI 8 Interrupt
|
||||
#define PCIE_MSI9 265 // PCIE MSI 9 Interrupt
|
||||
#define PCIE_MSI10 266 // PCIE MSI 10 Interrupt
|
||||
#define PCIE_MSI11 267 // PCIE MSI 11 Interrupt
|
||||
#define PCIE_MSI12 268 // PCIE MSI 12 Interrupt
|
||||
#define PCIE_MSI13 269 // PCIE MSI 13 Interrupt
|
||||
#define PCIE_MSI14 270 // PCIE MSI 14 Interrupt
|
||||
#define PCIE_MSI15 271 // PCIE MSI 15 Interrupt
|
||||
#define PCIE_MSI16 272 // PCIE MSI 16 Interrupt
|
||||
#define PCIE_MSI17 273 // PCIE MSI 17 Interrupt
|
||||
#define PCIE_MSI18 274 // PCIE MSI 18 Interrupt
|
||||
#define PCIE_MSI19 275 // PCIE MSI 19 Interrupt
|
||||
#define PCIE_MSI20 276 // PCIE MSI 20 Interrupt
|
||||
#define PCIE_MSI21 277 // PCIE MSI 21 Interrupt
|
||||
#define PCIE_MSI22 278 // PCIE MSI 22 Interrupt
|
||||
#define PCIE_MSI23 279 // PCIE MSI 23 Interrupt
|
||||
#define PCIE_MSI24 280 // PCIE MSI 24 Interrupt
|
||||
#define PCIE_MSI25 281 // PCIE MSI 25 Interrupt
|
||||
#define PCIE_MSI26 282 // PCIE MSI 26 Interrupt
|
||||
#define PCIE_MSI27 283 // PCIE MSI 27 Interrupt
|
||||
#define PCIE_MSI28 284 // PCIE MSI 28 Interrupt
|
||||
#define PCIE_MSI29 285 // PCIE MSI 29 Interrupt
|
||||
#define PCIE_MSI30 286 // PCIE MSI 30 Interrupt
|
||||
#define PCIE_MSI31 287 // PCIE MSI 31 Interrupt
|
||||
|
||||
#elif SUB_PLATFORM_S8001
|
||||
|
||||
#define INT_SW0 0 // Software 0 Interrupt
|
||||
#define INT_SW1 1 // Software 1 Interrupt
|
||||
#define INT_SW2 2 // Software 2 Interrupt
|
||||
#define INT_SW3 3 // Software 3 Interrupt
|
||||
#define INT_WDT 4 // Watchdog Timer Interrupt
|
||||
#define INT_DWI1 5 // DWI Interrupt
|
||||
#define INT_DWI2 6 // DWI Interrupt
|
||||
#define INT_PMGR_PERF_CNTRS 7 // PMGR Performace Counters Interrupt
|
||||
#define INT_THERM_TEMP0 8 // Thermal Temp 0 Interrupt
|
||||
#define INT_THERM_ALARM0 9 // Thermal Alarm 0 Interrupt
|
||||
#define INT_THERM_TEMP1 10 // Thermal Temp 1 Interrupt
|
||||
#define INT_THERM_ALARM1 11 // Thermal Alarm 1 Interrupt
|
||||
#define INT_THERM_TEMP2 12 // Thermal Temp 2 Interrupt
|
||||
#define INT_THERM_ALARM2 13 // Thermal Alarm 2 Interrupt
|
||||
#define INT_THERM_TEMP3 14 // Thermal Temp 3 Interrupt
|
||||
#define INT_THERM_ALARM3 15 // Thermal Alarm 3 Interrupt
|
||||
#define INT_CPM_THERM_TEMP 16 // CPM Thermal temp Interrupt
|
||||
#define INT_CPM_THERM_ALARM 17 // CPM Thermal alarm Interrupt
|
||||
#define INT_CPU0_THERM_TEMP 18 // CPU0 Thermal temp Interrupt
|
||||
#define INT_CPU0_THERM_ALARM 19 // CPU0 Thermal alarm Interrupt
|
||||
#define INT_CPU1_THERM_TEMP 20 // CPU1 Thermal temp Interrupt
|
||||
#define INT_CPU1_THERM_ALARM 21 // CPU1 Thermal alarm Interrupt
|
||||
|
||||
// Reserved 22 - 25
|
||||
|
||||
#define INT_THERM_FS_ACT0 26 // Thermal Failsafe Active 0 Interrupt
|
||||
#define INT_THERM_FS_ACT1 27 // Thermal Failsafe Active 1 Interrupt
|
||||
#define INT_THERM_FS_EXT0 28 // Thermal Failsafe Exit 0 Interrupt
|
||||
#define INT_THERM_FS_EXT1 29 // Thermal Failsafe Exit 1 Interrupt
|
||||
#define INT_SOC_THERM_FS_ACT0 30 // SoC Thermal Failsafe Active 0 Interrupt
|
||||
#define INT_SOC_THERM_FS_ACT1 31 // SoC Thermal Failsafe Active 1 Interrupt
|
||||
#define INT_PMGR_EVENT 32 // PMGR Event Interrupt
|
||||
#define INT_CTM_TRIGGER0 33 // CTM Trigger 0 Interrupt
|
||||
#define INT_CTM_TRIGGER1 34 // CTM Trigger 1 Interrupt
|
||||
#define INT_CTM_TRIGGER2 35 // CTM Trigger 2 Interrupt
|
||||
#define INT_CTM_TRIGGER3 36 // CTM Trigger 3 Interrupt
|
||||
#define INT_COHERENCE_PNT0_ERR 37 // Coherence Point Error Interrupt
|
||||
#define INT_COHERENCE_PNT0_PERF_CNTRS 38 // Coherence Point Performance Counters Interrupt
|
||||
#define INT_COHERENCE_PNT1_ERR 39 // Coherence Point Error Interrupt
|
||||
#define INT_COHERENCE_PNT1_PERF_CNTRS 40 // Coherence Point Performance Counters Interrupt
|
||||
|
||||
// Reserved 41
|
||||
|
||||
#define INT_GPIO_CLASS0 42 // GPIO Class 0 Interrupt
|
||||
#define INT_GPIO_CLASS1 43 // GPIO Class 1 Interrupt
|
||||
#define INT_GPIO_CLASS2 44 // GPIO Class 2 Interrupt
|
||||
#define INT_GPIO_CLASS3 45 // GPIO Class 3 Interrupt
|
||||
#define INT_GPIO_CLASS4 46 // GPIO Class 4 Interrupt
|
||||
#define INT_GPIO_CLASS5 47 // GPIO Class 5 Interrupt
|
||||
#define INT_GPIO_CLASS6 48 // GPIO Class 6 Interrupt
|
||||
|
||||
// Reserved 49
|
||||
|
||||
#define INT_MINI_PMGR_PERF_CNTRS 50 // MINIPMGR PerfCounter Interrupt
|
||||
#define INT_GFX_PERF_CNTRS 51 // GFX Perf Counter Interrupt
|
||||
#define INT_MEM_CONTROLLER0 52 // Memory Controller MCC Interrupt
|
||||
#define INT_MEM_CONTROLLER0_1 53 // Memory Controller MCC Interrupt
|
||||
#define INT_MEM_CONTROLLER1 54 // Memory Controller MCC Interrupt
|
||||
#define INT_MEM_CONTROLLER1_1 55 // Memory Controller MCC Interrupt
|
||||
|
||||
// Reserved 56 - 80
|
||||
|
||||
#define INT_CPU0_COMM_TX 57 // CPU 0 COMM TX Interrupt
|
||||
#define INT_CPU0_COMM_RX 58 // CPU 0 COMM RX Interrupt
|
||||
#define INT_CPU0_PMU_IRQ 59 // CPU 0 PMU IRQ Interrupt
|
||||
#define INT_CPU1_COMM_TX 60 // CPU 1 COMM TX Interrupt
|
||||
#define INT_CPU1_COMM_RX 61 // CPU 1 COMM RX Interrupt
|
||||
#define INT_CPU1_PMU_IRQ 62 // CPU 1 PMU IRQ Interrupt
|
||||
|
||||
// Reserved 87 - 92
|
||||
|
||||
#define INT_CCC_UNIFIED_TRIGGER 93 // CCC Unified Trigger Interrupt
|
||||
|
||||
// Reserved 94 - 103
|
||||
|
||||
#define INT_ISP_KF_INBOX_EMPTY 104 // ISP KF Inbox Empty Interrupt
|
||||
#define INT_ISP_KF_INBOX_NOTEMPTY 105 // ISP KF Inbox Not Empty Interrupt
|
||||
#define INT_ISP_KF_OUTBOX_EMPTY 106 // ISP KF Outbox Empty Interrupt
|
||||
#define INT_ISP_KF_OUTBOX_NOTEMPTY 107 // ISP KF Outbox Not Empty Interrupt
|
||||
#define INT_ISP0 108 // ISP 0 Interrupt
|
||||
#define INT_ISP1 109 // ISP 1 Interrupt
|
||||
#define INT_ISP2 110 // ISP 2 Interrupt
|
||||
#define INT_ISP3 111 // ISP 3 Interrupt
|
||||
#define INT_ISP_DART 112 // ISP DART Interrupt
|
||||
|
||||
// Reserved 113
|
||||
|
||||
#define INT_SEP_KF_INBOX_EMPTY 114 // SEP KF Inbox Empty Interrupt
|
||||
#define INT_SEP_KF_INBOX_NOTEMPTY 115 // SEP KF Inbox Not Empty Interrupt
|
||||
#define INT_SEP_KF_OUTBOX_EMPTY 116 // SEP KF Outbox Empty Interrupt
|
||||
#define INT_SEP_KF_OUTBOX_NOTEMPTY 117 // SEP KF Outbox Not Empty Interrupt
|
||||
#define INT_SEP_AUTH_ERROR 118 // SEP Authentication Error Interrupt
|
||||
#define INT_SEP_CRIT_PATH_MONITOR 119 // SEP Critical Path Monitor Interrupt
|
||||
|
||||
// Reserved 120
|
||||
|
||||
// XXX JF: AOP interrupts
|
||||
|
||||
// Reserved 153
|
||||
|
||||
#define INT_DISP0 154 // Display 0 Interrupt
|
||||
#define INT_DISP0_DART 155 // Display 0 DART Interrupt
|
||||
#define INT_DISP0_SMMU 156 // Display 0 SMMU Interrupt
|
||||
#define INT_DISP0_BACK_END_BLU 157 // Display 0 Back End Back Light Update Interrupt
|
||||
#define INT_DISP0_BACK_END_VBI 158 // Display 0 Back End VBI Interrupt
|
||||
#define INT_DISP0_BACK_END_VFTG 159 // Display 0 Back End VFTG Idle Interrupt
|
||||
#define INT_DISP0_BACK_END_VBL 160 // Display 0 Back End VBL counter Interrupt
|
||||
#define INT_DISPLAY_PORT0 161 // Display Port 0
|
||||
#define INT_EDP0 INT_DISPLAY_PORT0
|
||||
#define INT_DPORT0 INT_DISPLAY_PORT0
|
||||
|
||||
// Reserved 162
|
||||
|
||||
#define INT_DISP1 163 // Display 1 Interrupt
|
||||
#define INT_DISP1_DART 164 // Display 1 DART Interrupt
|
||||
#define INT_DISP1_SMMU 165 // Display 1 SMMU Interrupt
|
||||
#define INT_DISP1_BACK_END_BLU 166 // Display 1 Back End Back Light Update Interrupt
|
||||
#define INT_DISP1_BACK_END_VBI 167 // Display 1 Back End VBI Interrupt
|
||||
#define INT_DISP1_BACK_END_VFTG 168 // Display 1 Back End VFTG Idle Interrupt
|
||||
#define INT_DISP1_BACK_END_VBL 169 // Display 1 Back End VBL counter Interrupt
|
||||
#define INT_DISPLAY_PORT1 170 // Display Port 1
|
||||
|
||||
// Reserved 171
|
||||
|
||||
// XXX: PMP
|
||||
|
||||
// Reserved 176
|
||||
|
||||
#define INT_VDEC0 177 // Video Decoder 0 Interrupt
|
||||
|
||||
// Reserved 178
|
||||
|
||||
#define INT_AVE_KF_INBOX_EMPTY 179 // AVE KF Inbox Empty Interrupt
|
||||
#define INT_AVE_KF_INBOX_NOTEMPTY 180 // AVE KF Inbox Not Empty Interrupt
|
||||
#define INT_AVE_KF_OUTBOX_EMPTY 181 // AVE KF Outbox Empty Interrupt
|
||||
#define INT_AVE_KF_OUTBOX_NOTEMPTY 182 // AVE KF Outbox Not Empty Interrupt
|
||||
#define INT_AVE_DART 183 // AVE DART Interrupt
|
||||
#define INT_AVE_SMMU 184 // AVE SMMU Interrupt
|
||||
#define INT_AVE 185 // AVE Interrupt
|
||||
#define INT_SVE_SYNC 186 // SVE Driver Synchronization Interrupt
|
||||
|
||||
// Reserved 187 - 189
|
||||
|
||||
#define INT_GFX 190 // GFX Interrupt
|
||||
#define INT_GFX_SLEEP 191 // GFX Sleep Interrupt
|
||||
#define INT_GFX_WAKE 192 // GFX Wake Interrupt
|
||||
#define INT_GFX_CHG 193 // GFX Change Interrupt
|
||||
#define INT_GFX_FW 194 // GFX Change Interrupt
|
||||
|
||||
#define INT_SRS 195 // SRS Interrupt
|
||||
#define INT_SRS_STG1 196 // SRS STG1 Interrupt
|
||||
#define INT_SRS_BWM 197 // SRS BWM Interrupt
|
||||
#define INT_SRS_NM 198 // SRS NM Interrupt
|
||||
#define INT_SRS_DART 199 // SRS DART Interrupt
|
||||
#define INT_SRS_STT 200 // SRS STT Interrupt
|
||||
|
||||
#define INT_JPEG 201 // JPEG Interrupt
|
||||
#define INT_JPEG_DART 202 // JPEG DART Interrupt
|
||||
#define INT_JPEG_DART_PERF 203 // JPEG DART Performance Interrupt
|
||||
|
||||
// Reserved 204
|
||||
|
||||
#define INT_MSR 205 // MSR Interrupt
|
||||
#define INT_MSR_SMMU 206 // MSR SMMU Interrupt
|
||||
#define INT_MSR_DART 207 // MSR DART Interrupt
|
||||
#define INT_MSR_DAR_PERF 208 // MSR DART Performance Interrupt
|
||||
|
||||
// Reserved 209
|
||||
|
||||
#define INT_SIO_KF_INBOX_EMPTY 210 // SIO KF Inbox Empty Interrupt
|
||||
#define INT_SIO_KF_INBOX_NOTEMPTY 211 // SIO KF Inbox Not Empty Interrupt
|
||||
#define INT_SIO_KF_OUTBOX_EMPTY 212 // SIO KF Outbox Empty Interrupt
|
||||
#define INT_SIO_KF_OUTBOX_NOTEMPTY 213 // SIO KF Outbox Not Empty Interrupt
|
||||
#define INT_SPI0 214 // SPI 0 Interrupt
|
||||
#define INT_SPI1 215 // SPI 1 Interrupt
|
||||
#define INT_SPI2 216 // SPI 2 Interrupt
|
||||
#define INT_SPI3 217 // SPI 3 Interrupt
|
||||
#define INT_UART0 218 // UART 0 Interrupt
|
||||
#define INT_UART1 219 // UART 1 Interrupt
|
||||
#define INT_UART2 220 // UART 2 Interrupt
|
||||
#define INT_UART3 221 // UART 3 Interrupt
|
||||
#define INT_UART4 222 // UART 4 Interrupt
|
||||
#define INT_UART5 223 // UART 5 Interrupt
|
||||
#define INT_UART6 224 // UART 6 Interrupt
|
||||
#define INT_UART7 225 // UART 7 Interrupt
|
||||
#define INT_UART8 226 // UART 8 Interrupt
|
||||
#define INT_MCA0 227 // Multi-Channel Audio 0 Interrupt
|
||||
#define INT_MCA1 228 // Multi-Channel Audio 1 Interrupt
|
||||
#define INT_MCA2 229 // Multi-Channel Audio 2 Interrupt
|
||||
#define INT_MCA3 230 // Multi-Channel Audio 3 Interrupt
|
||||
#define INT_MCA4 231 // Multi-Channel Audio 4 Interrupt
|
||||
#define INT_IIC0 232 // I2C 0 Interrupt
|
||||
#define INT_IIC1 233 // I2C 1 Interrupt
|
||||
#define INT_IIC2 234 // I2C 2 Interrupt
|
||||
#define INT_IIC3 235 // I2C 3 Interrupt
|
||||
#define INT_PWM 236 // PWM Interrupt
|
||||
#define INT_AES0 237 // AES 0 Interrupt
|
||||
|
||||
// Reserved 238 - 240
|
||||
|
||||
#define INT_USB_OTG 241 // USB OTG Interrupt
|
||||
#define INT_USB2HOST0_EHCI 242 // USB EHCI 0 Interrupt
|
||||
#define INT_USB2HOST0_OHCI 243 // USB OHCI 0 Interrupt
|
||||
#define INT_USB2HOST1_EHCI 244 // USB EHCI 1 Interrupt
|
||||
#define INT_USB2HOST2_EHCI 245 // USB EHCI 2 Interrupt
|
||||
#define INT_USBOTG_RESUME 246 // USB OTG Resume Interrupt
|
||||
#define INT_USB_20_BATT_CHRG_DET 247 // USB 2.0 Battery Charge Detect Interrupt
|
||||
#define INT_USB2HOST0_PHY_RESUME 248 // USB Host 0 Resume Interrupt
|
||||
#define INT_USB2HOST1_PHY_RESUME 249 // USB Host 1 Resume Interrupt
|
||||
#define INT_USB2HOST2_PHY_RESUME 250 // USB Host 2 Resume Interrupt
|
||||
#define INT_OTG_IN_EP0 251 // OTG IN Endpoint 0 Interrupt
|
||||
#define INT_OTG_IN_EP1 252 // OTG IN Endpoint 1 Interrupt
|
||||
#define INT_OTG_IN_EP2 253 // OTG IN Endpoint 2 Interrupt
|
||||
#define INT_OTG_IN_EP3 254 // OTG IN Endpoint 3 Interrupt
|
||||
#define INT_OTG_IN_EP4 255 // OTG IN Endpoint 4 Interrupt
|
||||
#define INT_OTG_IN_EP5 256 // OTG IN Endpoint 5 Interrupt
|
||||
#define INT_OTG_IN_EP6 257 // OTG IN Endpoint 6 Interrupt
|
||||
#define INT_OTG_IN_EP7 258 // OTG IN Endpoint 7 Interrupt
|
||||
#define INT_OTG_IN_EP8 259 // OTG IN Endpoint 8 Interrupt
|
||||
#define INT_OTG_OUT_EP0 260 // OTG OUT Endpoint 0 Interrupt
|
||||
#define INT_OTG_OUT_EP1 261 // OTG OUT Endpoint 1 Interrupt
|
||||
#define INT_OTG_OUT_EP2 262 // OTG OUT Endpoint 2 Interrupt
|
||||
#define INT_OTG_OUT_EP3 263 // OTG OUT Endpoint 3 Interrupt
|
||||
#define INT_OTG_OUT_EP4 264 // OTG OUT Endpoint 4 Interrupt
|
||||
#define INT_OTG_OUT_EP5 265 // OTG OUT Endpoint 5 Interrupt
|
||||
#define INT_OTG_OUT_EP6 266 // OTG OUT Endpoint 6 Interrupt
|
||||
#define INT_OTG_OUT_EP7 267 // OTG OUT Endpoint 7 Interrupt
|
||||
#define INT_OTG_OUT_EP8 268 // OTG OUT Endpoint 8 Interrupt
|
||||
|
||||
// Reserved 269
|
||||
|
||||
#define PCIE_LINK0 270 // PCIE Link 0 Interrupt
|
||||
#define PCIE_LINK0_DART 271 // PCIE Link 0 DART Interrupt
|
||||
#define PCIE_LINK0_MMU 272 // PCIE Link 0 MMU Interrupt
|
||||
#define PCIE_LINK1 273 // PCIE Link 1 Interrupt
|
||||
#define PCIE_LINK1_DART 274 // PCIE Link 1 DART Interrupt
|
||||
#define PCIE_LINK1_MMU 275 // PCIE Link 1 MMU Interrupt
|
||||
#define PCIE_LINK2 276 // PCIE Link 2 Interrupt
|
||||
#define PCIE_LINK2_DART 277 // PCIE Link 2 DART Interrupt
|
||||
#define PCIE_LINK2_MMU 278 // PCIE Link 2 MMU Interrupt
|
||||
#define PCIE_LINK3 279 // PCIE Link 3 Interrupt
|
||||
#define PCIE_LINK3_DART 280 // PCIE Link 3 DART Interrupt
|
||||
#define PCIE_LINK3_MMU 281 // PCIE Link 3 MMU Interrupt
|
||||
#define PCIE_LINK4 282 // PCIE Link 4 Interrupt
|
||||
#define PCIE_LINK4_DART 283 // PCIE Link 4 DART Interrupt
|
||||
#define PCIE_LINK4_MMU 284 // PCIE Link 4 MMU Interrupt
|
||||
#define PCIE_LINK5 285 // PCIE Link 5 Interrupt
|
||||
#define PCIE_LINK5_DART 286 // PCIE Link 5 DART Interrupt
|
||||
#define PCIE_LINK5_MMU 287 // PCIE Link 5 MMU Interrupt
|
||||
#define PCIE_MSI0 288 // PCIE MSI 0 Interrupt
|
||||
#define PCIE_MSI1 289 // PCIE MSI 1 Interrupt
|
||||
#define PCIE_MSI2 290 // PCIE MSI 2 Interrupt
|
||||
#define PCIE_MSI3 291 // PCIE MSI 3 Interrupt
|
||||
#define PCIE_MSI4 292 // PCIE MSI 4 Interrupt
|
||||
#define PCIE_MSI5 293 // PCIE MSI 5 Interrupt
|
||||
#define PCIE_MSI6 294 // PCIE MSI 6 Interrupt
|
||||
#define PCIE_MSI7 295 // PCIE MSI 7 Interrupt
|
||||
#define PCIE_MSI8 296 // PCIE MSI 8 Interrupt
|
||||
#define PCIE_MSI9 297 // PCIE MSI 9 Interrupt
|
||||
#define PCIE_MSI10 298 // PCIE MSI 10 Interrupt
|
||||
#define PCIE_MSI11 299 // PCIE MSI 11 Interrupt
|
||||
#define PCIE_MSI12 300 // PCIE MSI 12 Interrupt
|
||||
#define PCIE_MSI13 301 // PCIE MSI 13 Interrupt
|
||||
#define PCIE_MSI14 302 // PCIE MSI 14 Interrupt
|
||||
#define PCIE_MSI15 303 // PCIE MSI 15 Interrupt
|
||||
#define PCIE_MSI16 304 // PCIE MSI 16 Interrupt
|
||||
#define PCIE_MSI17 305 // PCIE MSI 17 Interrupt
|
||||
#define PCIE_MSI18 306 // PCIE MSI 18 Interrupt
|
||||
#define PCIE_MSI19 307 // PCIE MSI 19 Interrupt
|
||||
#define PCIE_MSI20 308 // PCIE MSI 20 Interrupt
|
||||
#define PCIE_MSI21 309 // PCIE MSI 21 Interrupt
|
||||
#define PCIE_MSI22 310 // PCIE MSI 22 Interrupt
|
||||
#define PCIE_MSI23 311 // PCIE MSI 23 Interrupt
|
||||
#define PCIE_MSI24 312 // PCIE MSI 24 Interrupt
|
||||
#define PCIE_MSI25 313 // PCIE MSI 25 Interrupt
|
||||
#define PCIE_MSI26 314 // PCIE MSI 26 Interrupt
|
||||
#define PCIE_MSI27 315 // PCIE MSI 27 Interrupt
|
||||
#define PCIE_MSI28 316 // PCIE MSI 28 Interrupt
|
||||
#define PCIE_MSI29 317 // PCIE MSI 29 Interrupt
|
||||
#define PCIE_MSI30 318 // PCIE MSI 30 Interrupt
|
||||
#define PCIE_MSI31 319 // PCIE MSI 31 Interrupt
|
||||
|
||||
#else
|
||||
#error Unsupported Platform
|
||||
#endif
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWISR_H */
|
||||
@@ -0,0 +1,607 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWREGBASE_H
|
||||
#define __PLATFORM_SOC_HWREGBASE_H
|
||||
|
||||
#include <platform/memmap.h>
|
||||
|
||||
/*
|
||||
* DCS_REG_VERSION mapping used in iBoot for various platforms
|
||||
* Maui: 1
|
||||
* s8003: 2
|
||||
* Elba: 3
|
||||
*/
|
||||
#if SUB_PLATFORM_S8000
|
||||
#define DCS_REG_VERSION (1)
|
||||
#elif SUB_PLATFORM_S8003
|
||||
#define DCS_REG_VERSION (2)
|
||||
#elif SUB_PLATFORM_S8001
|
||||
#define DCS_REG_VERSION (3)
|
||||
#else
|
||||
#error "Unknown SUB_PLATFORM"
|
||||
#endif
|
||||
|
||||
/* S8000 and S8001 Reg Base Defs */
|
||||
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
|
||||
#define AMCC_BASE_ADDR(_n) (IO_BASE + ((_n) * 0x000200000)) // AMCC Config
|
||||
#define NUM_AMCCS (1)
|
||||
|
||||
#define DCS_BASE_ADDR (IO_BASE + 0x000200000) // DCS
|
||||
|
||||
#define DCS_SPACING (0x40000)
|
||||
#define SPLLCTRL_SPACING (0x00000C000)
|
||||
#define AMP_CA_SPACING (0x000020000)
|
||||
#define AMP_DQ_SPACING (0x000008000)
|
||||
#define AMP_SPACING (DCS_SPACING)
|
||||
#define AMP_BASE_ADDR (DCS_BASE_ADDR + AMP_CA_SPACING)
|
||||
#define AMPH_BASE_ADDR (AMP_BASE_ADDR + 3 * AMP_DQ_SPACING)
|
||||
|
||||
#define SWTCH_FAB_BASE_ADDR (IO_BASE + 0x000800000) // Switch Fabric Config
|
||||
|
||||
#define CP_COM_BASE_ADDR (IO_BASE + 0x000D00000) // CP Common Registers
|
||||
#define CP_COM_INT_BASE_ADDR (CP_COM_BASE_ADDR + 0x10000) // CP Common Interrupt Config Registers
|
||||
|
||||
#define CP_0_DT_DBG_CA0_ADDR (IO_BASE + 0x000D40000) // Dup Tag Debug backdoor Ram Access For CP0/CA0
|
||||
#define CP_1_DT_DBG_CA0_ADDR (IO_BASE + 0x000E40000) // Dup Tag Debug backdoor Ram Access For CP1/CA0
|
||||
|
||||
#define RGX_CR_BASE_ADDR (IO_BASE + 0x001000000) // Templar4 Space
|
||||
|
||||
#define GPC_BASE_ADDR (IO_BASE + 0x001e00000) // Templar4 Power Controller Space
|
||||
|
||||
#define IMGV42AF_AFC_AIU_BASE_ADDR (IO_BASE + 0x001f00000) // IMGv42AF0: Local PIO Config Space of AF AIU Block
|
||||
#define IMGV42AF_AFUSR_BASE_ADDR (IO_BASE + 0x001f02000) // IMGv42AF0: Bridge PIO Space
|
||||
|
||||
#define ACC_BASE_ADDR (IO_BASE + 0x002000000) // Apple Compute Complex
|
||||
#define CCC_CPU0_SYS_BASE_ADDR (IO_BASE + 0x002050000) // Twister CPU0 Implementation Specific Registers
|
||||
#define CCC_CPU1_SYS_BASE_ADDR (IO_BASE + 0x002150000) // Twister CPU1 Implementation Specific Registers
|
||||
|
||||
#define CCC0_SYS_BASE_ADDR (IO_BASE + 0x002200000) // Twister Core Complex Registers
|
||||
|
||||
#define CCC_SOC_BUSMUX_BASE_ADDR (IO_BASE + 0x004000000) // AF SoC BusMux Config
|
||||
#define SOC_BUSMUX_BASE_ADDR (IO_BASE + 0x004000000) // AF SoC BusMux Config
|
||||
// XXX JF
|
||||
#if SUB_PLATFORM_T7000
|
||||
#define CCC_CAM_BUSMUX_BASE_ADDR (IO_BASE + 0x005000000) // AF Camera BusMux Config
|
||||
#endif
|
||||
|
||||
#define ISP_AFC_AIU_0_BASE_ADDR (IO_BASE + 0x005B00000) // ISP AXI to AF Bridge
|
||||
// XXX JF
|
||||
#if SUB_PLATFORM_T7000
|
||||
#define ISP_AFC_AIU_1_BASE_ADDR (IO_BASE + 0x005B10000) // ISP AXI to AF Bridge
|
||||
#endif
|
||||
#define ISP_INTR2AXI_BASE_ADDR (IO_BASE + 0x005B20000) // ISP Interrupt to AXI Widget
|
||||
#define ISP_DART_BASE_ADDR (IO_BASE + 0x005B22000) // ISP DART
|
||||
#define ISP_SMMU_BASE_ADDR (IO_BASE + 0x005B24000) // ISP SMMU
|
||||
#define ISP_ISPCTRL_R0_BASE_ADDR (IO_BASE + 0x005B40000) // SISP Region 0 Control
|
||||
#define ISP_MIPI_CSI_0_BASE_ADDR (IO_BASE + 0x005B80000) // MIPI CSI Controller
|
||||
#define ISP_MIPI_CSI_1_BASE_ADDR (IO_BASE + 0x005B81000) // MIPI CSI Controller
|
||||
#define ISP_SMB_0_BASE_ADDR (IO_BASE + 0x005B82000) // SMB Controller
|
||||
#define ISP_SMB_1_BASE_ADDR (IO_BASE + 0x005B83000) // SMB Controller
|
||||
#define ISP_FD_BASE_ADDR (IO_BASE + 0x005B84000) // Face Detect
|
||||
#define ISP_AISP_BASE_ADDR (IO_BASE + 0x005BA0000) // AISP
|
||||
#define ISP_ISPCTRL_R1_BASE_ADDR (IO_BASE + 0x005BC0000) // SISP Region 1 Control
|
||||
#define ISP_AKF_BASE_ADDR (IO_BASE + 0x005C00000) // SISP KF Widgets and Config
|
||||
|
||||
// XXX JF
|
||||
#if SUB_PLATFORM_T7000
|
||||
#define DISP_BUSMUX_BASE_ADDR (IO_BASE + 0x006000000) // AF Display BusMux Config
|
||||
#endif
|
||||
#define DISP0_FAB_BASE_ADDR (IO_BASE + 0x006100000) // DisplayPipe0 AF and AXI Config
|
||||
#define DISP0_BASE_ADDR (IO_BASE + 0x006200000) // DisplayPipe0
|
||||
#define DISP0_ADP_BASE_ADDR (IO_BASE + 0x006200000) // DisplayPipe0 Configuration
|
||||
#define DISP0_SMMU_BASE_ADDR (IO_BASE + 0x006300000) // DisplayPipe0 SMMU Configuration
|
||||
#define DISP0_ADBE_BASE_ADDR (IO_BASE + 0x006400000) // DisplayPipe0 Backend Config
|
||||
#define DISP0_AAP_BASE_ADDR (IO_BASE + 0x006440000) // DisplayPipe0 Ambient-Adaptive Pixel Config
|
||||
#define DISP0_DPB_BASE_ADDR (IO_BASE + 0x006480000) // DisplayPipe0 Pixel Backlight Config
|
||||
#define DISP0_DITHER_BASE_ADDR (IO_BASE + 0x0064C0000) // DisplayPipe0 Dither Config
|
||||
#define DITHER_BASE_ADDR DISP0_DITHER_BASE_ADDR
|
||||
#define DITHER_VERSION (3)
|
||||
|
||||
#define DISP0_MIPI_DSI_BASE_ADDR (IO_BASE + 0x006600000) // DisplayPipe0 MIPI DSI Config
|
||||
#define DISP0_DPTX_BASE_ADDR (IO_BASE + 0x006700000) // DisplayPipe0 DisplayPort TX Config
|
||||
|
||||
#define MSR_AFC_AIU_BASE_ADDR (IO_BASE + 0x007800000) // MSR AXI2AF AFC_AIU
|
||||
#define MSR_BASE_ADDR (IO_BASE + 0x007900000) // Memory Scalar Rotator
|
||||
#define MSR_SMMU_BASE_ADDR (IO_BASE + 0x007904000) // MSR SMMU
|
||||
#define MSR_DART_BASE_ADDR (IO_BASE + 0x007908000) // DART for MSR SMMU
|
||||
#define MSR_INTR2AXI_BASE_ADDR (IO_BASE + 0x00790C000) // MSR Interrupt to AXI Widget
|
||||
|
||||
#define AJPEG_AFC_AIU_BASE_ADDR (IO_BASE + 0x007A00000) // AJPEG AXI2AF AFC_AIU
|
||||
#define AJPEG_BASE_ADDR (IO_BASE + 0x007B00000) // AJPEG Wrap
|
||||
#define AJPEG_DART_BASE_ADDR (IO_BASE + 0x007B02000) // AJPEG DART
|
||||
#define AJPEG_INTR2AXI_BASE_ADDR (IO_BASE + 0x007B04000) // AJPEG Interrupt to AXI Widget
|
||||
|
||||
#define SVE_BASE_ADDR (IO_BASE + 0x007C00000) // SVE Video Encoder Subsystem
|
||||
#define SVE_AVE_AXI2AF (IO_BASE + 0x007C00000) // SVE AVE AXI to Apple Fabric Bridge
|
||||
#define SVE_AFC_AIU_BASE_ADDR (IO_BASE + 0x007C00000) // SVE AXI2AF AFC_AIU
|
||||
#define SVE_INTR2AXI_BASE_ADDR (IO_BASE + 0x007C10000) // SVE VENC Interrupt to AXI Widget
|
||||
#define SVE_SMMU_BASE_ADDR (IO_BASE + 0x007C20000) // SVE Streaming MMU for AVE
|
||||
#define SVE_DART_BASE_ADDR (IO_BASE + 0x007C30000) // SVE DART for AVE SMMU
|
||||
#define SVE_PL301_BASE_ADDR (IO_BASE + 0x007C40000) // SVE PL301 Config
|
||||
#define SVE_AKF_BASE_ADDR (IO_BASE + 0x007C80000) // SVE Kingfisher Wrapper Configuration
|
||||
// XXX #define SVE_AVE_KF_DBG_BASE_ADDR (IO_BASE + 0x007CA0000) // SVE Kingfisher Wrapper Debug APB
|
||||
#define SVE_CTRL_BASE_ADDR (IO_BASE + 0x007CC0000) // SVE Control Registers
|
||||
|
||||
#define VXD_AFC_AIU_BASE_ADDR (IO_BASE + 0x007E00000) // VXD AXI2AF AFC_AIU
|
||||
#define VXD_INTR2AXI_BASE_ADDR (IO_BASE + 0x007E10000) // VXD Interrupt to AXI Widget
|
||||
#define VXD_PL301_BASE_ADDR (IO_BASE + 0x007E20000) // VXD PL301 Config
|
||||
#define VXD_CFG_BASE_ADDR (IO_BASE + 0x007F00000) // VXD Config Registers
|
||||
|
||||
#define IOBUSMUX_BASE_ADDR (IO_BASE + 0x009000000) // IO BusMux Config
|
||||
|
||||
#define SB_BASE_ADDR (IO_BASE + 0x00A000000) // South Bridge
|
||||
|
||||
#define ASIO_MISC_0_BASE_ADDR (IO_BASE + 0x00A000000) // ASIO Shim0 Misc Registers
|
||||
#define ASIO_AUD_MUX_BASE_ADDR (IO_BASE + 0x00A003000) // ASIO Audio I2S Switch Config
|
||||
#define ASIO_SPI_BASE_ADDR (IO_BASE + 0x00A080000) // ASIO SPI Device
|
||||
#define ASIO_SPI_TX_CFG_BASE_ADDR (IO_BASE + 0x00A081000) // ASIO SPI TX DMA Channel
|
||||
#define ASIO_SPI_RX_CFG_BASE_ADDR (IO_BASE + 0x00A081800) // ASIO SPI RX DMA Channel
|
||||
#define ASIO_SPI_TX_FIFO_BASE_ADDR (IO_BASE + 0x00A082000) // ASIO SPI TX DMA Shim FIFO
|
||||
#define ASIO_SPI_RX_FIFO_BASE_ADDR (IO_BASE + 0x00A083000) // ASIO SPI RX DMA Shim FIFO
|
||||
#define ASIO_MCA_BASE_ADDR (IO_BASE + 0x00A0A0000) // ASIO MCA Device
|
||||
#define ASIO_MCA_TX_CFG_BASE_ADDR (IO_BASE + 0x00A0A1000) // ASIO MCA TX DMA Channel
|
||||
#define ASIO_MCA_RX_CFG_BASE_ADDR (IO_BASE + 0x00A0A1800) // ASIO MCA RX DMA Channel
|
||||
#define ASIO_MCA_TX_FIFO_BASE_ADDR (IO_BASE + 0x00A0A2000) // ASIO MCA TX DMA Shim FIFO
|
||||
#define ASIO_MCA_RX_FIFO_BASE_ADDR (IO_BASE + 0x00A0A3000) // ASIO MCA RX DMA Shim FIFO
|
||||
#define ASIO_UART_BASE_ADDR (IO_BASE + 0x00A0C0000) // ASIO UART Device
|
||||
#define ASIO_UART_TX_CFG_BASE_ADDR (IO_BASE + 0x00A0C1000) // ASIO UART TX DMA Channel
|
||||
#define ASIO_UART_RX_CFG_BASE_ADDR (IO_BASE + 0x00A0C1800) // ASIO UART RX DMA Channel
|
||||
#define ASIO_UART_TX_FIFO_BASE_ADDR (IO_BASE + 0x00A0C2000) // ASIO UART TX DMA Shim FIFO
|
||||
#define ASIO_UART_RX_FIFO_BASE_ADDR (IO_BASE + 0x00A0C3000) // ASIO UART RX DMA Shim FIFO
|
||||
#define ASIO_MISC_1_BASE_ADDR (IO_BASE + 0x00A100000) // ASIO Shim1 Misc Registers
|
||||
#define ASIO_AES_BASE_ADDR (IO_BASE + 0x00A108000) // ASIO AES Config and DMA Registers
|
||||
#define ASIO_SMB_0_BASE_ADDR (IO_BASE + 0x00A110000) // ASIO I2C 0 Device
|
||||
#define ASIO_SMB_1_BASE_ADDR (IO_BASE + 0x00A111000) // ASIO I2C 1 Device
|
||||
#define ASIO_SMB_2_BASE_ADDR (IO_BASE + 0x00A112000) // ASIO I2C 2 Device
|
||||
#define ASIO_SMB_3_BASE_ADDR (IO_BASE + 0x00A113000) // ASIO I2C 3 Device
|
||||
#define ASIO_PWM_BASE_ADDR (IO_BASE + 0x00A118000) // ASIO PWM
|
||||
#define ASIO_DNSZ_AXI_0_BASE_ADDR (IO_BASE + 0x00A141000) // ASIO Downsizer 0 Configuration Registers
|
||||
#define ASIO_DNSZ_AXI_1_BASE_ADDR (IO_BASE + 0x00A142000) // ASIO Downsizer 1 Configuration Registers
|
||||
#define ASIO_AKF_BASE_ADDR (IO_BASE + 0x00AE00000) // ASIO KF Wrapper
|
||||
// XXX ASIO AKF DBG
|
||||
|
||||
#define AUSB_CTL_REG_BASE_ADDR (IO_BASE + 0x00C000000) // USBCTL Config
|
||||
#define AUSB_CTL_USB20PHY_REG_OFFSET (0x30) // USB20PHY Register offset within AUSBCTL registers
|
||||
#define AUSB_OTG_BASE_ADDR (IO_BASE + 0x00C100000) // USB OTG
|
||||
#define AUSB_USB2HOST0_EHCI_BASE_ADDR (IO_BASE + 0x00C200000) // EHCI0
|
||||
#define AUSB_USB2HOST0_OHCI_BASE_ADDR (IO_BASE + 0x00C300000) // OHCI0
|
||||
#define AUSB_USB2HOST1_EHCI_BASE_ADDR (IO_BASE + 0x00C400000) // EHCI1
|
||||
#define AUSB_USB2HOST1_OHCI_BASE_ADDR (IO_BASE + 0x00C500000) // OHCI1
|
||||
#define AUSB_PL301_BASE_ADDR (IO_BASE + 0x00C800000) // AUSB PL301 4-AHB Master to 1-AXI Slave
|
||||
#define AUSB_PL301_WIDGET_BASE_ADDR (IO_BASE + 0x00C900000) // AUSB PL301 Widget
|
||||
#define AUSB_INTR2AXI_BASE_ADDR (IO_BASE + 0x00CA00000) // AUSB Interrupt to AXI Widget
|
||||
#define AUSB_AFIFO_WIDGET_BASE_ADDR (IO_BASE + 0x00CB00000) // AUSB Async FIFO
|
||||
|
||||
#define ASEP_AKF_BASE_ADDR (IO_BASE + 0x00DA00000) // ASEP AKF control Registers
|
||||
|
||||
#define PMGR_BASE_ADDR (IO_BASE + 0x00E000000) // PMGR
|
||||
|
||||
#define AIC_BASE_ADDR (IO_BASE + 0x00E100000) // AIC
|
||||
#define AIC_WIRE_VIRT_BASE_ADDR (IO_BASE + 0x00E110000) // AIC Wrapper
|
||||
|
||||
#define DWI_BASE_ADDR (IO_BASE + 0x00E200000) // DWI
|
||||
|
||||
#define LIO_MEM_PL301_BASE_ADDR (IO_BASE + 0x00E900000) // PL310 for pd_lio memory
|
||||
#define LIO_PIO_PL310_BASE_ADDR (IO_BASE + 0x00E940000) // PL310 for pd_lio PIO
|
||||
#define LIO_DNSZ_AXI_BASE_ADDR (IO_BASE + 0x00E9C8000) // PL310 for pd_lio downsizer
|
||||
#define LIO_SIO_AFIFO_WIDGETS_BASE_ADDR (IO_BASE + 0x00E9C0000) // SIO Async FIFO for pd_lio
|
||||
#define LIO_DAP_AFIFO_WIDGETS_BASE_ADDR (IO_BASE + 0x00E9E0000) // DAP Async FIFO for pd_lio
|
||||
#define LIO_AFC_AIU_BASE_ADDR (IO_BASE + 0x00F010000) // LIO AXI to AF Bridge
|
||||
|
||||
#define GPIO_BASE_ADDR (IO_BASE + 0x00F100000) // GPIO
|
||||
#define GLBTIMER_BASE_ADDR (IO_BASE + 0x00F140000) // Global Timer
|
||||
|
||||
#define ERR_REFLECTION_BASE_ADDR (IO_BASE + 0x00FFFC000)
|
||||
|
||||
#define AOP_BASE_ADDR (IO_BASE + 0x010000000)
|
||||
#define AOP_MINIPMGR_BASE_ADDR (IO_BASE + 0x010200000)
|
||||
#define DBG_WRP_BASE_ADDR (IO_BASE + 0x010300000) // Debug Sub-system Config
|
||||
#define AOP_GPIO_BASE_ADDR (IO_BASE + 0x0100f0000)
|
||||
#define AOP_SRAM_BASE_ADDR (IO_BASE + 0x010E00000)
|
||||
#define AOP_RECONFIG_REGION_BASE_ADDR (IO_BASE + 0x010E9B000)
|
||||
#define AOP_RECONFIG_REGION_SIZE (IO_BASE + 0x010EA0000 - AOP_RECONFIG_REGION_BASE_ADDR)
|
||||
#define AOP_RECONFIG_REGION_DIAGS_BASE_ADDR (IO_BASE + 0x010E90000)
|
||||
#define AOP_RECONFIG_REGION_DIAGS_SIZE (IO_BASE + 0x010EA0000 - AOP_RECONFIG_REGION_DIAGS_BASE_ADDR)
|
||||
#define MEMORY_CALIB_SAVE_BASE_ADDR AOP_SRAM_BASE_ADDR // Temporarily save cold boot memcal results in AOP_SRAM
|
||||
|
||||
#define APCIE_VERSION (2)
|
||||
#define APCIE_COMMON_BASE_ADDR (PCI_REG_BASE + 0x00000000)
|
||||
#define APCIE_PHY_BASE_ADDR (PCI_REG_BASE + 0x00008000)
|
||||
#if SUB_PLATFORM_S8000
|
||||
#define APCIE_PHY_AUSP_SHM_BASE_ADDR (PCI_REG_BASE + 0x00009a00)
|
||||
#define APCIE_PHY_AUST0_SHM_CFG_BASE_ADDR (PCI_REG_BASE + 0x8100)
|
||||
#define APCIE_PHY_AUST1_SHM_CFG_BASE_ADDR (PCI_REG_BASE + 0x8300)
|
||||
#define APCIE_PHY_AUST2_SHM_CFG_BASE_ADDR (PCI_REG_BASE + 0x8500)
|
||||
#define APCIE_PHY_AUST3_SHM_CFG_BASE_ADDR (PCI_REG_BASE + 0x8700)
|
||||
#define APCIE_PHY_AUST4_SHM_CFG_BASE_ADDR (PCI_REG_BASE + 0x8900)
|
||||
#define APCIE_PHY_AUSR0_CFG_BASE_ADDR (PCI_REG_BASE + 0x8a00)
|
||||
#define APCIE_PHY_AUSR0_SHM_CFG_BASE_ADDR (PCI_REG_BASE + 0x8b00)
|
||||
#define APCIE_PHY_AUSR1_CFG_BASE_ADDR (PCI_REG_BASE + 0x8c00)
|
||||
#define APCIE_PHY_AUSR1_SHM_CFG_BASE_ADDR (PCI_REG_BASE + 0x8d00)
|
||||
#define APCIE_PHY_AUSR2_CFG_BASE_ADDR (PCI_REG_BASE + 0x8e00)
|
||||
#define APCIE_PHY_AUSR2_SHM_CFG_BASE_ADDR (PCI_REG_BASE + 0x8f00)
|
||||
#define APCIE_PHY_AUSR3_CFG_BASE_ADDR (PCI_REG_BASE + 0x9000)
|
||||
#define APCIE_PHY_AUSR3_SHM_CFG_BASE_ADDR (PCI_REG_BASE + 0x9100)
|
||||
#define APCIE_PHY_AUSR4_CFG_BASE_ADDR (PCI_REG_BASE + 0x9200)
|
||||
#define APCIE_PHY_AUSR4_SHM_CFG_BASE_ADDR (PCI_REG_BASE + 0x9300)
|
||||
#elif SUB_PLATFORM_S8003
|
||||
#define APCIE_PHY_PMA_COMMON_BASE_ADDR (PCI_REG_BASE + 0x0a000000)
|
||||
#define APCIE_PHY_PMA_TX_LANE_BASE_ADDR (PCI_REG_BASE + 0x0a010000)
|
||||
#define APCIE_PHY_PMA_TX_LANE_STRIDE (0x800)
|
||||
#define APCIE_PHY_PMA_RX_LANE_BASE_ADDR (PCI_REG_BASE + 0x0a020000)
|
||||
#define APCIE_PHY_PMA_RX_LANE_STRIDE (0x800)
|
||||
#endif
|
||||
#define APCIE_COUNTER_BASE_ADDR (PCI_REG_BASE + 0x4000)
|
||||
#define APCIE_CONFIG_BASE_ADDR (PCI_REG_BASE + 0x01000000)
|
||||
#define APCIE_CONFIG_PORT_STRIDE (0x01000000)
|
||||
|
||||
/* iBoot Specific Defs */
|
||||
|
||||
#define AKF_VERSION (2)
|
||||
|
||||
#define UART0_BASE_ADDR (ASIO_UART_BASE_ADDR)
|
||||
#define UART1_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x04000)
|
||||
#define UART2_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x08000)
|
||||
#define UART3_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x0C000)
|
||||
#define UART4_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x10000)
|
||||
#define UART5_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x14000)
|
||||
#define UART6_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x18000)
|
||||
#define UART7_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x1C000)
|
||||
#define UART8_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x20000)
|
||||
#define UARTS_COUNT (9)
|
||||
#define UART_VERSION (1)
|
||||
|
||||
#define SPI0_BASE_ADDR (ASIO_SPI_BASE_ADDR)
|
||||
#define SPI1_BASE_ADDR (ASIO_SPI_BASE_ADDR + 0x04000)
|
||||
#define SPI2_BASE_ADDR (ASIO_SPI_BASE_ADDR + 0x08000)
|
||||
#define SPI3_BASE_ADDR (ASIO_SPI_BASE_ADDR + 0x0C000)
|
||||
#define SPI_VERSION (1)
|
||||
#define SPIS_COUNT (4)
|
||||
|
||||
#define IIC_BASE_ADDR (ASIO_SMB_0_BASE_ADDR)
|
||||
#define IIC_SPACING (0x00001000)
|
||||
#define IICS_COUNT (3)
|
||||
|
||||
#define USBPHY_VERSION (4)
|
||||
|
||||
#define DSIM_BASE_ADDR (DISP0_MIPI_DSI_BASE_ADDR)
|
||||
#define DSIM_LANE_COUNT (4)
|
||||
#define DSIM_VERSION (2)
|
||||
|
||||
#define EDP_BASE_ADDR (DISP0_DPTX_BASE_ADDR)
|
||||
#define DP_BASE_ADDR (DISP0_DPTX_BASE_ADDR)
|
||||
#define LPDP_PHY_BASE_ADDR (DISP0_DPTX_BASE_ADDR + 0x080000)
|
||||
#define DISPLAYPORT_VERSION (4)
|
||||
#define LPDP_PHY_VERSION (1)
|
||||
|
||||
#define ADBE_DISPLAYPIPE_BASE_ADDR (DISP0_BASE_ADDR)
|
||||
#define DISP_VERSION (5)
|
||||
#define ADP_VERSION (2)
|
||||
|
||||
#define GPIOC_COUNT (2)
|
||||
#define GPIO_VERSION (4)
|
||||
#define GPIO_0_GROUP_COUNT (25)
|
||||
#define GPIO_1_BASE_ADDR (AOP_GPIO_BASE_ADDR)
|
||||
#define GPIO_1_GROUP_COUNT (4)
|
||||
#define GPIO_AP (GPIOC_0)
|
||||
#define GPIO_AOP (GPIOC_1)
|
||||
#define GPIO_GROUP_COUNT (GPIO_0_GROUP_COUNT)
|
||||
#define GPIO_PAD_SPI (GPIO_GROUP_COUNT)
|
||||
|
||||
#define AIC_VERSION (1)
|
||||
#define AIC_INT_COUNT (256)
|
||||
|
||||
#define PMGR_WDG_VERSION (1)
|
||||
|
||||
#define USBOTG_BASE_ADDR (AUSB_OTG_BASE_ADDR)
|
||||
|
||||
#define APCIE_NUM_LINKS (4)
|
||||
|
||||
#define DART0_BASE_ADDR (PCI_REG_BASE + 0x1008000)
|
||||
#define DART0_ADDR_MASK (0x3FFFFFFF)
|
||||
#define DART1_BASE_ADDR (PCI_REG_BASE + 0x2008000)
|
||||
#define DART1_ADDR_MASK (0x3FFFFFFF)
|
||||
#define DART2_BASE_ADDR (PCI_REG_BASE + 0x3008000)
|
||||
#define DART2_ADDR_MASK (0x3FFFFFFF)
|
||||
#define DART3_BASE_ADDR (PCI_REG_BASE + 0x4008000)
|
||||
#define DART3_ADDR_MASK (0x3FFFFFFF)
|
||||
|
||||
#define PCIE_PORT0_DART_ID (0)
|
||||
#define PCIE_PORT1_DART_ID (1)
|
||||
#define PCIE_PORT2_DART_ID (2)
|
||||
#define PCIE_PORT3_DART_ID (3)
|
||||
#define NUM_DARTS (4)
|
||||
|
||||
#define AES_AP_BASE_ADDR (ASIO_AES_BASE_ADDR)
|
||||
#define AES_AP_VERSION (0)
|
||||
|
||||
#elif SUB_PLATFORM_S8001
|
||||
|
||||
#define AMCC_BASE_ADDR(_n) (IO_BASE + ((_n) * 0x000200000)) // AMCC Config
|
||||
#define NUM_AMCCS (2)
|
||||
|
||||
#define DCS_BASE_ADDR (IO_BASE + 0x000400000) // DCS
|
||||
|
||||
#define DCS_SPACING (0x40000)
|
||||
#define SPLLCTRL_SPACING (0x00000C000)
|
||||
#define AMP_CA_SPACING (0x000020000)
|
||||
#define AMP_DQ_SPACING (0x000008000)
|
||||
#define AMP_SPACING (DCS_SPACING)
|
||||
#define AMP_BASE_ADDR (DCS_BASE_ADDR + AMP_CA_SPACING)
|
||||
#define AMPH_BASE_ADDR (AMP_BASE_ADDR + 3 * AMP_DQ_SPACING)
|
||||
|
||||
#define SWTCH_FAB_BASE_ADDR (IO_BASE + 0x000800000) // Switch Fabric Config
|
||||
|
||||
#define CP0_COM_BASE_ADDR (IO_BASE + 0x000A00000) // CP0 Common Registers
|
||||
#define CP0_COM_INT_BASE_ADDR (CP0_COM_BASE_ADDR + 0x10000) // CP0 Common Interrupt Config Registers
|
||||
|
||||
#define CP0_0_DT_DBG_CA0_ADDR (IO_BASE + 0x000A40000) // Dup Tag Debug backdoor Ram Access For CP0/CA0
|
||||
#define CP0_1_DT_DBG_CA0_ADDR (IO_BASE + 0x000B40000) // Dup Tag Debug backdoor Ram Access For CP0/CA0
|
||||
|
||||
#define CP1_COM_BASE_ADDR (IO_BASE + 0x000C00000) // CP1 Common Registers
|
||||
#define CP1_COM_INT_BASE_ADDR (CP1_COM_BASE_ADDR + 0x10000) // CP1 Common Interrupt Config Registers
|
||||
|
||||
#define CP1_0_DT_DBG_CA0_ADDR (IO_BASE + 0x000C40000) // Dup Tag Debug backdoor Ram Access For CP1/CA0
|
||||
#define CP1_1_DT_DBG_CA0_ADDR (IO_BASE + 0x000D40000) // Dup Tag Debug backdoor Ram Access For CP1/CA0
|
||||
|
||||
#define RGX_CR_BASE_ADDR (IO_BASE + 0x001000000) // Templar4 Space
|
||||
|
||||
#define GPC_BASE_ADDR (IO_BASE + 0x001d00000) // Templar4 Power Controller Space
|
||||
|
||||
#define IMGV42AF_AFC_AIU_BASE_ADDR (IO_BASE + 0x001f00000) // IMGv42AF0: Local PIO Config Space of AF AIU Block
|
||||
#define IMGV42AF_AFUSR_BASE_ADDR (IO_BASE + 0x001f40000) // IMGv42AF0: Bridge PIO Space
|
||||
#define IMGV42AF1_AFC_AIU_BASE_ADDR (IO_BASE + 0x001f80000) // IMGv42AF1: Local PIO Config Space of AF AIU Block
|
||||
#define IMGV42AF1_AFUSR_BASE_ADDR (IO_BASE + 0x001fC0000) // IMGv42AF1: Bridge PIO Space
|
||||
|
||||
#define ACC_BASE_ADDR (IO_BASE + 0x002000000) // Apple Compute Complex
|
||||
#define CCC_CPU0_SYS_BASE_ADDR (IO_BASE + 0x002050000) // Twister CPU0 Implementation Specific Registers
|
||||
#define CCC_CPU1_SYS_BASE_ADDR (IO_BASE + 0x002150000) // Twister CPU1 Implementation Specific Registers
|
||||
#define CCC0_SYS_BASE_ADDR (IO_BASE + 0x002200000) // Twister Core Complex Registers
|
||||
|
||||
#define CCC_SOC_BUSMUX_BASE_ADDR (IO_BASE + 0x004000000) // AF SoC BusMux Config
|
||||
#define SOC_BUSMUX_BASE_ADDR (IO_BASE + 0x004000000) // AF SoC BusMux Config
|
||||
|
||||
#define ISP_AFC_AIU_0_BASE_ADDR (IO_BASE + 0x005B00000) // ISP AXI to AF Bridge
|
||||
#define ISP_INTR2AXI_BASE_ADDR (IO_BASE + 0x005B20000) // ISP Interrupt to AXI Widget
|
||||
#define ISP_DART_BASE_ADDR (IO_BASE + 0x005B22000) // ISP DART
|
||||
#define ISP_SMMU_BASE_ADDR (IO_BASE + 0x005B24000) // ISP SMMU
|
||||
#define ISP_ISPCTRL_R0_BASE_ADDR (IO_BASE + 0x005B40000) // SISP Region 0 Control
|
||||
#define ISP_SMB_0_BASE_ADDR (IO_BASE + 0x005B82000) // SMB Controller
|
||||
#define ISP_SMB_1_BASE_ADDR (IO_BASE + 0x005B83000) // SMB Controller
|
||||
#define ISP_FD_BASE_ADDR (IO_BASE + 0x005B84000) // Face Detect
|
||||
#define ISP_AISP_BASE_ADDR (IO_BASE + 0x005BA0000) // AISP
|
||||
#define ISP_ISPCTRL_R1_BASE_ADDR (IO_BASE + 0x005BC0000) // SISP Region 1 Control
|
||||
#define ISP_AKF_BASE_ADDR (IO_BASE + 0x005C00000) // SISP KF Widgets and Config
|
||||
|
||||
#define RT_BUSMUX_BASE_ADDR (IO_BASE + 0x006000000) // RT BusMux Config
|
||||
|
||||
#define DISP0_FAB_BASE_ADDR (IO_BASE + 0x006100000) // DisplayPipe0 AF and AXI Config
|
||||
#define DISP0_BASE_ADDR (IO_BASE + 0x006200000) // DisplayPipe0
|
||||
#define DISP0_ADP_BASE_ADDR (IO_BASE + 0x006200000) // DisplayPipe0 Configuration
|
||||
#define DISP0_SMMU_BASE_ADDR (IO_BASE + 0x006300000) // DisplayPipe0 SMMU Configuration
|
||||
#define DISP0_ADBE_BASE_ADDR (IO_BASE + 0x006400000) // DisplayPipe0 Backend Config
|
||||
#define DISP0_AAP_BASE_ADDR (IO_BASE + 0x006440000) // DisplayPipe0 Ambient-Adaptive Pixel Config
|
||||
#define DISP0_DPB_BASE_ADDR (IO_BASE + 0x006480000) // DisplayPipe0 Pixel Backlight Config
|
||||
#define DISP0_WPC_BASE_ADDR (IO_BASE + 0x0064C0000) // DisplayPipe0 Whitepoint Correction
|
||||
#define DISP0_PRC_BASE_ADDR (IO_BASE + 0x006500000)
|
||||
#define DISP0_DITHER_BASE_ADDR (IO_BASE + 0x006540000) // DisplayPipe0 Dither Config
|
||||
#define DITHER_BASE_ADDR DISP0_DITHER_BASE_ADDR
|
||||
#define DITHER_VERSION (4)
|
||||
|
||||
#define DISP0_DPTX_BASE_ADDR (IO_BASE + 0x006700000) // DisplayPipe0 DisplayPort TX Config
|
||||
|
||||
#define DISP1_FAB_BASE_ADDR (IO_BASE + 0x006900000) // DisplayPipe1 AF and AXI Config
|
||||
#define DISP1_BASE_ADDR (IO_BASE + 0x006A00000) // DisplayPipe1
|
||||
#define DISP1_ADP_BASE_ADDR (IO_BASE + 0x006A00000) // DisplayPipe1 Ambient-Adaptive Pixel Config
|
||||
#define DISP1_SMMU_BASE_ADDR (IO_BASE + 0x006B00000) // DisplayPipe1 SMMU Configuration
|
||||
|
||||
#define MEDIA_BUS_MUX (IO_BASE + 0x007000000) // Media Bus Mux
|
||||
#define DISP1_MEDIA_BUSMUX_BASE_ADDR (IO_BASE + 0x008000000) // DisplayPipe1 AF Media BusMux Config
|
||||
|
||||
#define MSR_AFC_AIU_BASE_ADDR (IO_BASE + 0x007800000) // MSR AXI2AF AFC_AIU
|
||||
#define MSR_BASE_ADDR (IO_BASE + 0x007900000) // Memory Scalar Rotator
|
||||
#define MSR_SMMU_BASE_ADDR (IO_BASE + 0x007904000) // MSR SMMU
|
||||
#define MSR_DART_BASE_ADDR (IO_BASE + 0x007908000) // DART for MSR SMMU
|
||||
#define MSR_INTR2AXI_BASE_ADDR (IO_BASE + 0x00790C000) // MSR Interrupt to AXI Widget
|
||||
|
||||
#define AJPEG_AFC_AIU_BASE_ADDR (IO_BASE + 0x007A00000) // AJPEG AXI2AF AFC_AIU
|
||||
#define AJPEG_BASE_ADDR (IO_BASE + 0x007B00000) // AJPEG Wrap
|
||||
#define AJPEG_DART_BASE_ADDR (IO_BASE + 0x007B04000) // AJPEG DART
|
||||
#define AJPEG_INTR2AXI_BASE_ADDR (IO_BASE + 0x007B08000) // AJPEG Interrupt to AXI Widget
|
||||
|
||||
#define SVE_BASE_ADDR (IO_BASE + 0x007C00000) // SVE Video Encoder Subsystem
|
||||
#define SVE_AVE_AXI2AF (IO_BASE + 0x007C00000) // SVE AVE AXI to Apple Fabric Bridge
|
||||
#define SVE_AFC_AIU_BASE_ADDR (IO_BASE + 0x007C00000) // SVE AXI2AF AFC_AIU
|
||||
#define SVE_INTR2AXI_BASE_ADDR (IO_BASE + 0x007C10000) // SVE VENC Interrupt to AXI Widget
|
||||
#define SVE_SMMU_BASE_ADDR (IO_BASE + 0x007C20000) // SVE Streaming MMU for AVE
|
||||
#define SVE_DART_BASE_ADDR (IO_BASE + 0x007C30000) // SVE DART for AVE SMMU
|
||||
#define SVE_PL301_BASE_ADDR (IO_BASE + 0x007C40000) // SVE PL301 Config
|
||||
#define SVE_AKF_BASE_ADDR (IO_BASE + 0x007C80000) // SVE Kingfisher Wrapper Configuration
|
||||
// XXX #define SVE_AVE_KF_DBG_BASE_ADDR (IO_BASE + 0x007CA0000) // SVE Kingfisher Wrapper Debug APB
|
||||
#define SVE_CTRL_BASE_ADDR (IO_BASE + 0x007CC0000) // SVE Control Registers
|
||||
|
||||
#define VXD_AFC_AIU_BASE_ADDR (IO_BASE + 0x007E00000) // VXD AXI2AF AFC_AIU
|
||||
#define VXD_CFG_BASE_ADDR (IO_BASE + 0x007F00000) // VXD Config Registers
|
||||
|
||||
#define SB_BASE_ADDR (IO_BASE + 0x00A000000) // South Bridge
|
||||
|
||||
#define ASIO_MISC_0_BASE_ADDR (IO_BASE + 0x00A000000) // ASIO Shim0 Misc Registers
|
||||
#define ASIO_AUD_MUX_BASE_ADDR (IO_BASE + 0x00A003000) // ASIO Audio I2S Switch Config
|
||||
#define ASIO_SPI_BASE_ADDR (IO_BASE + 0x00A080000) // ASIO SPI Device
|
||||
#define ASIO_SPI_TX_CFG_BASE_ADDR (IO_BASE + 0x00A081000) // ASIO SPI TX DMA Channel
|
||||
#define ASIO_SPI_RX_CFG_BASE_ADDR (IO_BASE + 0x00A081800) // ASIO SPI RX DMA Channel
|
||||
#define ASIO_SPI_TX_FIFO_BASE_ADDR (IO_BASE + 0x00A082000) // ASIO SPI TX DMA Shim FIFO
|
||||
#define ASIO_SPI_RX_FIFO_BASE_ADDR (IO_BASE + 0x00A083000) // ASIO SPI RX DMA Shim FIFO
|
||||
#define ASIO_MCA_BASE_ADDR (IO_BASE + 0x00A0A0000) // ASIO MCA Device
|
||||
#define ASIO_MCA_TX_CFG_BASE_ADDR (IO_BASE + 0x00A0A1000) // ASIO MCA TX DMA Channel
|
||||
#define ASIO_MCA_RX_CFG_BASE_ADDR (IO_BASE + 0x00A0A1800) // ASIO MCA RX DMA Channel
|
||||
#define ASIO_MCA_TX_FIFO_BASE_ADDR (IO_BASE + 0x00A0A2000) // ASIO MCA TX DMA Shim FIFO
|
||||
#define ASIO_MCA_RX_FIFO_BASE_ADDR (IO_BASE + 0x00A0A3000) // ASIO MCA RX DMA Shim FIFO
|
||||
#define ASIO_UART_BASE_ADDR (IO_BASE + 0x00A0C0000) // ASIO UART Device
|
||||
#define ASIO_UART_TX_CFG_BASE_ADDR (IO_BASE + 0x00A0C1000) // ASIO UART TX DMA Channel
|
||||
#define ASIO_UART_RX_CFG_BASE_ADDR (IO_BASE + 0x00A0C1800) // ASIO UART RX DMA Channel
|
||||
#define ASIO_UART_TX_FIFO_BASE_ADDR (IO_BASE + 0x00A0C2000) // ASIO UART TX DMA Shim FIFO
|
||||
#define ASIO_UART_RX_FIFO_BASE_ADDR (IO_BASE + 0x00A0C3000) // ASIO UART RX DMA Shim FIFO
|
||||
#define ASIO_MISC_1_BASE_ADDR (IO_BASE + 0x00A100000) // ASIO Shim1 Misc Registers
|
||||
#define ASIO_AES_BASE_ADDR (IO_BASE + 0x00A108000) // ASIO AES Config and DMA Registers
|
||||
#define ASIO_SMB_0_BASE_ADDR (IO_BASE + 0x00A110000) // ASIO I2C 0 Device
|
||||
#define ASIO_SMB_1_BASE_ADDR (IO_BASE + 0x00A111000) // ASIO I2C 1 Device
|
||||
#define ASIO_SMB_2_BASE_ADDR (IO_BASE + 0x00A112000) // ASIO I2C 2 Device
|
||||
#define ASIO_SMB_3_BASE_ADDR (IO_BASE + 0x00A113000) // ASIO I2C 3 Device
|
||||
#define ASIO_PWM_BASE_ADDR (IO_BASE + 0x00A118000) // ASIO PWM
|
||||
#define ASIO_DNSZ_AXI_0_BASE_ADDR (IO_BASE + 0x00A141000) // ASIO Downsizer 0 Configuration Registers
|
||||
#define ASIO_DNSZ_AXI_1_BASE_ADDR (IO_BASE + 0x00A142000) // ASIO Downsizer 1 Configuration Registers
|
||||
#define ASIO_AKF_BASE_ADDR (IO_BASE + 0x00AE00000) // ASIO KF Wrapper
|
||||
// XXX ASIO AKF DBG
|
||||
|
||||
#define AUSB_CTL_REG_BASE_ADDR (IO_BASE + 0x00C000000) // USBCTL Config
|
||||
#define AUSB_CTL_USB20PHY_REG_OFFSET (0x30) // USB20PHY Register offset within AUSBCTL registers
|
||||
#define AUSB_OTG_BASE_ADDR (IO_BASE + 0x00C100000) // USB OTG
|
||||
#define AUSB_USB2HOST0_EHCI_BASE_ADDR (IO_BASE + 0x00C200000) // EHCI0
|
||||
#define AUSB_USB2HOST0_OHCI_BASE_ADDR (IO_BASE + 0x00C300000) // OHCI0
|
||||
#define AUSB_USB2HOST1_EHCI_BASE_ADDR (IO_BASE + 0x00C400000) // EHCI1
|
||||
#define AUSB_USB2HOST1_OHCI_BASE_ADDR (IO_BASE + 0x00C500000) // OHCI1
|
||||
#define AUSB_PL301_BASE_ADDR (IO_BASE + 0x00C800000) // AUSB PL301 4-AHB Master to 1-AXI Slave
|
||||
#define AUSB_PL301_WIDGET_BASE_ADDR (IO_BASE + 0x00C900000) // AUSB PL301 Widget
|
||||
#define AUSB_INTR2AXI_BASE_ADDR (IO_BASE + 0x00CA00000) // AUSB Interrupt to AXI Widget
|
||||
#define AUSB_AFIFO_WIDGET_BASE_ADDR (IO_BASE + 0x00CB00000) // AUSB Async FIFO
|
||||
|
||||
#define ASEP_AKF_BASE_ADDR (IO_BASE + 0x00DA00000) // ASEP AKF control Registers
|
||||
|
||||
#define PMGR_BASE_ADDR (IO_BASE + 0x00E000000) // PMGR
|
||||
|
||||
#define AIC_BASE_ADDR (IO_BASE + 0x00E100000) // AIC
|
||||
#define AIC_WIRE_VIRT_BASE_ADDR (IO_BASE + 0x00E110000) // AIC Wrapper
|
||||
|
||||
#define DWI_BASE_ADDR (IO_BASE + 0x00E200000) // DWI
|
||||
|
||||
#define LIO_MEM_PL301_BASE_ADDR (IO_BASE + 0x00F160000) // PL310 for pd_lio memory
|
||||
#define LIO_PIO_PL310_BASE_ADDR (IO_BASE + 0x00F180000) // PL310 for pd_lio PIO
|
||||
#define LIO_NIC_PL301_BASE_ADDR (IO_BASE + 0x00F1A0000) // PL310 for pd_lio downsizer
|
||||
#define LIO_PMS_AFIFO_WIDGETS_BASE_ADDR (IO_BASE + 0x00F1E0000) // PMS Async FIFO for pd_lio
|
||||
#define LIO_AFC_AIU_BASE_ADDR (IO_BASE + 0x00F000000) // LIO AXI to AF Bridge
|
||||
#define SBR_AFC_AIU_BASE_ADDR (LIO_AFC_AIU_BASE_ADDR)
|
||||
|
||||
#define GPIO_BASE_ADDR (IO_BASE + 0x00F100000) // GPIO
|
||||
#define GLBTIMER_BASE_ADDR (IO_BASE + 0x00F140000) // Global Timer
|
||||
|
||||
#define ERR_REFLECTION_BASE_ADDR (IO_BASE + 0x00FFFC000)
|
||||
|
||||
#define AOP_BASE_ADDR (IO_BASE + 0x010000000)
|
||||
#define AOP_MINIPMGR_BASE_ADDR (IO_BASE + 0x010200000)
|
||||
#define DBG_WRP_BASE_ADDR (IO_BASE + 0x010300000) // Debug Sub-system Config
|
||||
#define AOP_GPIO_BASE_ADDR (IO_BASE + 0x0100f0000)
|
||||
#define AOP_SRAM_BASE_ADDR (IO_BASE + 0x010E00000)
|
||||
#define AOP_RECONFIG_REGION_BASE_ADDR (IO_BASE + 0x010E9B000)
|
||||
#define AOP_RECONFIG_REGION_SIZE (IO_BASE + 0x010EA0000 - AOP_RECONFIG_REGION_BASE_ADDR)
|
||||
#define AOP_RECONFIG_REGION_DIAGS_BASE_ADDR (IO_BASE + 0x010E90000)
|
||||
#define AOP_RECONFIG_REGION_DIAGS_SIZE (IO_BASE + 0x010EA0000 - AOP_RECONFIG_REGION_DIAGS_BASE_ADDR)
|
||||
#define MEMORY_CALIB_SAVE_BASE_ADDR AOP_SRAM_BASE_ADDR // Temporarily save cold boot memcal results in AOP_SRAM
|
||||
|
||||
#define APCIE_VERSION (2)
|
||||
#define APCIE_COMMON_BASE_ADDR (PCI_REG_BASE + 0x00000000)
|
||||
#define APCIE_COUNTER_BASE_ADDR (PCI_REG_BASE + 0x4000)
|
||||
#define APCIE_PHY_BASE_ADDR (PCI_REG_BASE + 0x8000)
|
||||
#define APCIE_CONFIG_BASE_ADDR (PCI_REG_BASE + 0x01000000)
|
||||
#define APCIE_CONFIG_PORT_STRIDE (0x01000000)
|
||||
#define APCIE_PHY_PMA_COMMON_BASE_ADDR (PCI_REG_BASE + 0x0a000000)
|
||||
#define APCIE_PHY_PMA_TX_LANE_BASE_ADDR (PCI_REG_BASE + 0x0a010000)
|
||||
#define APCIE_PHY_PMA_TX_LANE_STRIDE (0x800)
|
||||
#define APCIE_PHY_PMA_RX_LANE_BASE_ADDR (PCI_REG_BASE + 0x0a020000)
|
||||
#define APCIE_PHY_PMA_RX_LANE_STRIDE (0x800)
|
||||
|
||||
/* iBoot Specific Defs */
|
||||
|
||||
#define AKF_VERSION (2)
|
||||
|
||||
#define UART0_BASE_ADDR (ASIO_UART_BASE_ADDR)
|
||||
#define UART1_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x04000)
|
||||
#define UART2_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x08000)
|
||||
#define UART3_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x0C000)
|
||||
#define UART4_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x10000)
|
||||
#define UART5_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x14000)
|
||||
#define UART6_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x18000)
|
||||
#define UART7_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x1C000)
|
||||
#define UART8_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x20000)
|
||||
#define UARTS_COUNT (9)
|
||||
#define UART_VERSION (1)
|
||||
|
||||
#define SPI0_BASE_ADDR (ASIO_SPI_BASE_ADDR)
|
||||
#define SPI1_BASE_ADDR (ASIO_SPI_BASE_ADDR + 0x04000)
|
||||
#define SPI2_BASE_ADDR (ASIO_SPI_BASE_ADDR + 0x08000)
|
||||
#define SPI3_BASE_ADDR (ASIO_SPI_BASE_ADDR + 0x0C000)
|
||||
#define SPI_VERSION (1)
|
||||
#define SPIS_COUNT (4)
|
||||
|
||||
#define IIC_BASE_ADDR (ASIO_SMB_0_BASE_ADDR)
|
||||
#define IIC_SPACING (0x00001000)
|
||||
#define IICS_COUNT (4)
|
||||
|
||||
#define USBPHY_VERSION (4)
|
||||
|
||||
#define EDP_BASE_ADDR (DISP0_DPTX_BASE_ADDR)
|
||||
#define DP_BASE_ADDR (DISP0_DPTX_BASE_ADDR)
|
||||
#define LPDP_PHY_BASE_ADDR (DISP0_DPTX_BASE_ADDR + 0x080000)
|
||||
#define DISPLAYPORT_VERSION (5)
|
||||
#define LPDP_PHY_VERSION (2)
|
||||
|
||||
#define ADBE_DISPLAYPIPE_BASE_ADDR (DISP0_BASE_ADDR)
|
||||
#define DISP_VERSION (5)
|
||||
#define ADP_VERSION (2)
|
||||
|
||||
#define GPIOC_COUNT (2)
|
||||
#define GPIO_VERSION (5)
|
||||
#define GPIO_0_GROUP_COUNT (28)
|
||||
#define GPIO_1_BASE_ADDR (AOP_GPIO_BASE_ADDR)
|
||||
#define GPIO_1_GROUP_COUNT (4)
|
||||
#define GPIO_AP (GPIOC_0)
|
||||
#define GPIO_AOP (GPIOC_1)
|
||||
#define GPIO_GROUP_COUNT (GPIO_0_GROUP_COUNT)
|
||||
#define GPIO_PAD_SPI (GPIO_GROUP_COUNT)
|
||||
|
||||
#define AIC_VERSION (1)
|
||||
#define AIC_INT_COUNT (256)
|
||||
|
||||
#define PMGR_WDG_VERSION (1)
|
||||
|
||||
#define USBOTG_BASE_ADDR (AUSB_OTG_BASE_ADDR)
|
||||
|
||||
#define APCIE_NUM_LINKS (6)
|
||||
|
||||
#define DART0_BASE_ADDR (PCI_REG_BASE + 0x1008000)
|
||||
#define DART0_ADDR_MASK (0x3FFFFFFF)
|
||||
#define DART1_BASE_ADDR (PCI_REG_BASE + 0x2008000)
|
||||
#define DART1_ADDR_MASK (0x3FFFFFFF)
|
||||
#define DART2_BASE_ADDR (PCI_REG_BASE + 0x3008000)
|
||||
#define DART2_ADDR_MASK (0x3FFFFFFF)
|
||||
#define DART3_BASE_ADDR (PCI_REG_BASE + 0x4008000)
|
||||
#define DART3_ADDR_MASK (0x3FFFFFFF)
|
||||
#define DART4_BASE_ADDR (PCI_REG_BASE + 0x5008000)
|
||||
#define DART4_ADDR_MASK (0x3FFFFFFF)
|
||||
#define DART5_BASE_ADDR (PCI_REG_BASE + 0x6008000)
|
||||
#define DART5_ADDR_MASK (0x3FFFFFFF)
|
||||
|
||||
#define PCIE_PORT0_DART_ID (0)
|
||||
#define PCIE_PORT1_DART_ID (1)
|
||||
#define PCIE_PORT2_DART_ID (2)
|
||||
#define PCIE_PORT3_DART_ID (3)
|
||||
#define PCIE_PORT4_DART_ID (4)
|
||||
#define PCIE_PORT5_DART_ID (5)
|
||||
#define NUM_DARTS (6)
|
||||
|
||||
#define AES_AP_BASE_ADDR (ASIO_AES_BASE_ADDR)
|
||||
#define AES_AP_VERSION (0)
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWREGBASE_H */
|
||||
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_MIU_H
|
||||
#define __PLATFORM_SOC_MIU_H
|
||||
|
||||
#include <lib/devicetree.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rSECUREROMCTRL_ROMADDRREMAP (*(volatile u_int32_t *)(AOP_MINIPMGR_BASE_ADDR + 0xd0014))
|
||||
|
||||
#define MCCLOCKREGION_TZ0BASEADDR(_n) (AMCC_BASE_ADDR(_n) + 0x480)
|
||||
#define MCCLOCKREGION_TZ0ENDADDR(_n) (AMCC_BASE_ADDR(_n) + 0x484)
|
||||
#define MCCLOCKREGION_TZ1BASEADDR(_n) (AMCC_BASE_ADDR(_n) + 0x488)
|
||||
#define MCCLOCKREGION_TZ1ENDADDR(_n) (AMCC_BASE_ADDR(_n) + 0x48c)
|
||||
#define MCCLOCKREGION_TZ0LOCK(_n) (AMCC_BASE_ADDR(_n) + 0x490)
|
||||
#define MCCLOCKREGION_TZ1LOCK(_n) (AMCC_BASE_ADDR(_n) + 0x494)
|
||||
|
||||
#define rMCCLOCKREGION_TZ0BASEADDR(_n) (*(volatile u_int32_t *)(MCCLOCKREGION_TZ0BASEADDR(_n)))
|
||||
#define rMCCLOCKREGION_TZ0ENDADDR(_n) (*(volatile u_int32_t *)(MCCLOCKREGION_TZ0ENDADDR(_n)))
|
||||
#define rMCCLOCKREGION_TZ1BASEADDR(_n) (*(volatile u_int32_t *)(MCCLOCKREGION_TZ1BASEADDR(_n)))
|
||||
#define rMCCLOCKREGION_TZ1ENDADDR(_n) (*(volatile u_int32_t *)(MCCLOCKREGION_TZ1ENDADDR(_n)))
|
||||
#define rMCCLOCKREGION_TZ0LOCK(_n) (*(volatile u_int32_t *)(MCCLOCKREGION_TZ0LOCK(_n)))
|
||||
#define rMCCLOCKREGION_TZ1LOCK(_n) (*(volatile u_int32_t *)(MCCLOCKREGION_TZ1LOCK(_n)))
|
||||
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
#define CP_COM_DYN_CLK_GATING_CTRL (0x000c)
|
||||
#define rCP_COM_DYN_CLK_GATING_CTRL (*(volatile u_int32_t *)(CP_COM_BASE_ADDR + CP_COM_DYN_CLK_GATING_CTRL))
|
||||
#define CPCOM_INT_NORM_REQUEST (0x0000)
|
||||
#define rCP_COM_INT_NORM_REQUEST (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CPCOM_INT_NORM_REQUEST))
|
||||
#define CPCOM_INT_NORM_MASK_SET (0x0004)
|
||||
#define rCP_COM_INT_NORM_MASK_SET (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CPCOM_INT_NORM_MASK_SET))
|
||||
#define CPCOM_INT_NORM_MASK_CLR (0x0008)
|
||||
#define rCP_COM_INT_NORM_MASK_CLR (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CPCOM_INT_NORM_MASK_CLR))
|
||||
#else
|
||||
#define CPCOM_INT_NORM_REQUEST (0x0000)
|
||||
#define rCP0_COM_INT_NORM_REQUEST (*(volatile u_int32_t *)(CP0_COM_INT_BASE_ADDR + CPCOM_INT_NORM_REQUEST))
|
||||
#define rCP1_COM_INT_NORM_REQUEST (*(volatile u_int32_t *)(CP1_COM_INT_BASE_ADDR + CPCOM_INT_NORM_REQUEST))
|
||||
#define CPCOM_INT_NORM_MASK_SET (0x0004)
|
||||
#define rCP0_COM_INT_NORM_MASK_SET (*(volatile u_int32_t *)(CP0_COM_INT_BASE_ADDR + CPCOM_INT_NORM_MASK_SET))
|
||||
#define rCP1_COM_INT_NORM_MASK_SET (*(volatile u_int32_t *)(CP1_COM_INT_BASE_ADDR + CPCOM_INT_NORM_MASK_SET))
|
||||
#define CPCOM_INT_NORM_MASK_CLR (0x0008)
|
||||
#define rCP0_COM_INT_NORM_MASK_CLR (*(volatile u_int32_t *)(CP0_COM_INT_BASE_ADDR + CPCOM_INT_NORM_MASK_CLR))
|
||||
#define rCP1_COM_INT_NORM_MASK_CLR (*(volatile u_int32_t *)(CP1_COM_INT_BASE_ADDR + CPCOM_INT_NORM_MASK_CLR))
|
||||
#endif
|
||||
|
||||
// removed all the random registers used to set tunables
|
||||
// we should grab these from the SPDS when we do Maui tunables
|
||||
|
||||
enum remap_select {
|
||||
REMAP_SRAM = 0,
|
||||
REMAP_SDRAM
|
||||
};
|
||||
|
||||
extern void miu_select_remap(enum remap_select sel);
|
||||
extern void miu_bypass_prep(void);
|
||||
extern void miu_update_device_tree(DTNode *pmgr_node);
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_MIU_H */
|
||||
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_OPERATING_POINT_H
|
||||
#define __PLATFORM_SOC_OPERATING_POINT_H
|
||||
|
||||
#include <platform/soc/chipid.h>
|
||||
struct operating_point_params {
|
||||
union {
|
||||
struct {
|
||||
uint64_t voltage_index:9;
|
||||
uint64_t bypass:1;
|
||||
uint64_t clkSrc:1;
|
||||
uint64_t preDivP:6;
|
||||
uint64_t fbkDivM:9;
|
||||
uint64_t pstDivS:6;
|
||||
uint64_t biuDiv4HiVol:3;
|
||||
uint64_t biuDiv4LoVol:3;
|
||||
uint64_t dvmrMaxWgt:7;
|
||||
uint64_t iexrfCfgWrData:2;
|
||||
uint64_t iexrfCfgWrIdxa:2;
|
||||
uint64_t iexrfCfgWrIdxb:2;
|
||||
uint64_t exrfCfgWrIdxmuxsel:2;
|
||||
uint64_t nrgAccScaleTab:8;
|
||||
uint64_t lkgEstTab:8;
|
||||
uint64_t dpe0DvfmTab:8;
|
||||
};
|
||||
struct {
|
||||
uint64_t voltage_index:9;
|
||||
uint64_t bypass:1;
|
||||
uint64_t clkSrc:1;
|
||||
uint64_t preDivP:6;
|
||||
uint64_t fbkDivM:9;
|
||||
uint64_t pstDivS:6;
|
||||
} gpu;
|
||||
struct {
|
||||
uint64_t chipid_max:9; // must contains CHIPID_MAX
|
||||
uint64_t chip_id:16;
|
||||
uint64_t voltage_type:3;
|
||||
uint64_t chip_rev:16;
|
||||
uint64_t reserved:18;
|
||||
};
|
||||
};
|
||||
};
|
||||
extern const struct operating_point_params *operating_point_get_params(enum chipid_voltage_index voltage_index, enum chipid_voltage_type voltage_type);
|
||||
|
||||
|
||||
|
||||
#endif /* __PLATFORM_SOC_CHIPID_H */
|
||||
@@ -0,0 +1,690 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_PMGR_H
|
||||
#define __PLATFORM_SOC_PMGR_H
|
||||
|
||||
#include <lib/devicetree.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include SUB_PLATFORM_SPDS_HEADER(acc)
|
||||
#include SUB_PLATFORM_SPDS_HEADER(minipmgr)
|
||||
#include SUB_PLATFORM_SPDS_HEADER(pmgr)
|
||||
|
||||
////////////////////////////////////////////////////////////
|
||||
//
|
||||
// PMGR specific
|
||||
//
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#define PMGR_BINNING_GROUP_N69 (0x1)
|
||||
#define PMGR_BINNING_GROUP_J111 (0x2)
|
||||
|
||||
#define PMGR_BINNING_GROUP_N69U (0x1)
|
||||
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
#define PMGR_PLL_COUNT (7)
|
||||
#elif SUB_PLATFORM_S8001
|
||||
#define PMGR_PLL_COUNT (9)
|
||||
#endif
|
||||
|
||||
#define PMGR_PLL_REG_STRIDE (PMGR_PLL1_OFFSET - PMGR_PLL0_OFFSET)
|
||||
|
||||
#define rPMGR_PLL_CTL(_p) (*(volatile uint32_t *)(PMGR_BASE_ADDR + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
|
||||
#define PMGR_PLL_ENABLE (1 << PMGR_PLL0_CTL_ENABLE_SHIFT)
|
||||
#define PMGR_PLL_LOAD (1 << PMGR_PLL0_CTL_LOAD_SHIFT)
|
||||
#define PMGR_PLL_BYPASS (1 << PMGR_PLL0_CTL_BYPASS_SHIFT)
|
||||
#define PMGR_PLL_PENDING (1 << PMGR_PLL0_CTL_PLL_PENDING_SHIFT)
|
||||
#define PMGR_PLL_M_SHIFT PMGR_PLL0_CTL_FB_DIVN_SHIFT
|
||||
#define PMGR_PLL_M_MASK PMGR_PLL0_CTL_FB_DIVN_SMASK
|
||||
#define PMGR_PLL_P_SHIFT PMGR_PLL0_CTL_PRE_DIVN_SHIFT
|
||||
#define PMGR_PLL_P_MASK PMGR_PLL0_CTL_PRE_DIVN_SMASK
|
||||
#define PMGR_PLL_S_SHIFT PMGR_PLL0_CTL_OP_DIVN_SHIFT
|
||||
#define PMGR_PLL_S_MASK PMGR_PLL0_CTL_OP_DIVN_SMASK
|
||||
#define PMGR_PLL_PCIE_S_MASK PMGR_PLL_PCIE_CTL_OP_DIVN_SMASK
|
||||
#define PMGR_PLL_M(_m) (((_m) & PMGR_PLL_M_MASK) << PMGR_PLL_M_SHIFT)
|
||||
#define PMGR_PLL_P(_p) (((_p) & PMGR_PLL_P_MASK) << PMGR_PLL_P_SHIFT)
|
||||
#define PMGR_PLL_S(_s) (((_s) & PMGR_PLL_S_MASK) << PMGR_PLL_S_SHIFT)
|
||||
#define PMGR_PLL_PCIE_S(_s) (((_s) & PMGR_PLL_PCIE_S_MASK) << PMGR_PLL_S_SHIFT)
|
||||
#define PMGR_PLL_FREQ(_m, _p, _s) ((((_m) * OSC_FREQ) / (_p))/((_s) + 1))
|
||||
|
||||
#define rPMGR_PLL_CFG(_p) (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0004 + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
|
||||
#define PMGR_PLL_OFF_MODE(_n) PMGR_PLL0_CFG_OFF_MODE_INSRT(_n)
|
||||
#define PMGR_PLL_OFF_MODE_RESET (0)
|
||||
#define PMGR_PLL_OFF_MODE_CLOCK_GATED (1)
|
||||
#define PMGR_PLL_OFF_MODE_POWER_DOWN (2)
|
||||
#define PMGR_PLL_LOCK_MODE(_n) PMGR_PLL0_CFG_LOCK_MODE_INSRT(_n)
|
||||
#define PMGR_PLL_LOCK_MODE_COUNTER (0)
|
||||
#define PMGR_PLL_LOCK_MODE_LOCK (1)
|
||||
#define PMGR_PLL_AUTO_DISABLE (1 << PMGR_PLL0_CFG_AUTO_DISABLE_SHIFT)
|
||||
#define PMGR_PLL_RELOCK_MODE_SHIFT PMGR_PLL0_CFG_RELOCK_MODE_SHIFT
|
||||
#define PMGR_PLL_RELOCK_MODE_MASK PMGR_PLL0_CFG_RELOCK_MODE_SMASK
|
||||
#define PMGR_PLL_RELOCK_MODE_STOP (0)
|
||||
#define PMGR_PLL_RELOCK_MODE_BYPASS (1)
|
||||
#define PMGR_PLL_FRAC_LOCK_TIME(_n) PMGR_PLL0_CFG_FRAC_LOCK_TIME_INSRT(_n)
|
||||
#define PMGR_PLL_LOCK_TIME(_n) PMGR_PLL0_CFG_LOCK_TIME_INSRT(_n)
|
||||
|
||||
#define rPMGR_PLL_ANA_PARAMS1(_p) (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x000c + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
|
||||
#define rPMGR_PLL_ANA_PARAMS2(_p) (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0010 + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
|
||||
#define rPMGR_PLL_ANA_PARAMS3(_p) (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0014 + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
|
||||
|
||||
#define rPMGR_PLL_DEBUG1(_p) (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0014 + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
|
||||
#define PMGR_PLL_DEBUG1_RESERVE_IN_SHIFT (20)
|
||||
#define PMGR_PLL_DEBUG1_RESERVE_IN_MASK (0x3f)
|
||||
|
||||
#define rPMGR_PLL_PCIE_DELAY_CTL0(_p) (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0028 + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
|
||||
|
||||
#define rPMGR_CLK_CFG(_x) (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_CLKCFG_##_x##_CLK_CFG_OFFSET))
|
||||
|
||||
#define PMGR_CLK_CFG_ENABLE (1 << 31)
|
||||
#define PMGR_CLK_CFG_PENDING (1 << 30)
|
||||
#define PMGR_CLK_CFG_PENDING_SHIFT (30)
|
||||
#define PMGR_CLK_CFG_SRC_SEL_MASK (0xF)
|
||||
#define PMGR_CLK_CFG_SRC_SEL_SHIFT (24)
|
||||
#define PMGR_CLK_CFG_DIVISOR_MASK (0x3F)
|
||||
#define PMGR_CLK_CFG_WAIT_COUNTER_UMASK (0xf00000)
|
||||
|
||||
#define PMGR_SPARE_COUNT (6)
|
||||
|
||||
#define rPMGR_CLK_DIVIDER_ACG_CFG (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_CLKCFG_CLK_DIVIDER_ACG_CFG_OFFSET))
|
||||
|
||||
#define PMGR_NCO_REG_STRIDE (PMGR_NCO_1_CLK_CFG_OFFSET - PMGR_NCO_0_CLK_CFG_OFFSET)
|
||||
|
||||
#define rPMGR_NCO_CLK_CFG(_n) (*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * PMGR_NCO_REG_STRIDE + PMGR_NCO_0_CLK_CFG_OFFSET))
|
||||
#define rPMGR_NCO_DIV_INT(_n) (*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * PMGR_NCO_REG_STRIDE + PMGR_NCO_0_DIV_INT_OFFSET))
|
||||
#define rPMGR_NCO_DIV_FRAC_N1(_n) (*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * PMGR_NCO_REG_STRIDE + PMGR_NCO_0_DIV_FRAC_N1_OFFSET))
|
||||
#define rPMGR_NCO_DIV_FRAC_N2(_n) (*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * PMGR_NCO_REG_STRIDE + PMGR_NCO_0_DIV_FRAC_N2_OFFSET))
|
||||
#define rPMGR_NCO_DIV_FRAC_PRIME(_n) (*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * PMGR_NCO_REG_STRIDE + PMGR_NCO_0_DIV_FRAC_PRIME_OFFSET))
|
||||
|
||||
#define PMGR_NCO_CLK_CFG_ENABLE (1 << PMGR_NCO_0_CLK_CFG_ENABLE_SHIFT)
|
||||
#define PMGR_NCO_CLK_CFG_PENDING (1 << PMGR_NCO_0_CLK_CFG_PENDING_SHIFT)
|
||||
|
||||
#define PMGR_NUM_NCO 5
|
||||
|
||||
#define kSOC_PERF_STATE_BYPASS (0)
|
||||
#define kSOC_PERF_STATE_SECUREROM (kSOC_PERF_STATE_BYPASS + 1)
|
||||
#define kSOC_PERF_STATE_IBOOT (kSOC_PERF_STATE_BYPASS + 2)
|
||||
#define kSOC_PERF_STATE_VMIN (kSOC_PERF_STATE_IBOOT + 0)
|
||||
#define kSOC_PERF_STATE_VNOM (kSOC_PERF_STATE_IBOOT + 1)
|
||||
|
||||
#define kSOC_PERF_STATE_VMAX (kSOC_PERF_STATE_VNOM)
|
||||
|
||||
#define kSOC_PERF_STATE_IBOOT_CNT (kSOC_PERF_STATE_VMAX + 1)
|
||||
#define kSOC_PERF_STATE_MAX_CNT (14)
|
||||
|
||||
#define rPMGR_SOC_PERF_STATE_CTL (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SOC_PERF_STATE_CTL_OFFSET))
|
||||
#define PMGR_SOC_PERF_STATE_CTL_PENDING_MASK (1 << PMGR_SOC_PERF_STATE_CTL_PENDING_SHIFT)
|
||||
|
||||
#define PMGR_SOC_PERF_STATE_STRIDE (PMGR_SOC_PERF_STATE_ENTRY_1A_OFFSET - PMGR_SOC_PERF_STATE_ENTRY_0A_OFFSET)
|
||||
|
||||
#define rPMGR_SOC_PERF_STATE_ENTRY_A(_n) (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SOC_PERF_STATE_ENTRY_0A_OFFSET + (_n) * PMGR_SOC_PERF_STATE_STRIDE))
|
||||
#define rPMGR_SOC_PERF_STATE_ENTRY_B(_n) (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SOC_PERF_STATE_ENTRY_0B_OFFSET + (_n) * PMGR_SOC_PERF_STATE_STRIDE))
|
||||
#define rPMGR_SOC_PERF_STATE_ENTRY_C(_n) (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SOC_PERF_STATE_ENTRY_0C_OFFSET + (_n) * PMGR_SOC_PERF_STATE_STRIDE))
|
||||
#define rPMGR_SOC_PERF_STATE_ENTRY_D(_n) (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SOC_PERF_STATE_ENTRY_0D_OFFSET + (_n) * PMGR_SOC_PERF_STATE_STRIDE))
|
||||
|
||||
#define PMGR_SOC_PERF_STATE_ENTRY_MCU_REF_MASK (PMGR_SOC_PERF_STATE_ENTRY_0A_MCU_REF_SRC_SEL_UMASK | PMGR_SOC_PERF_STATE_ENTRY_0A_MCU_REF_CFG_SEL_UMASK)
|
||||
#define PMGR_SOC_PERF_STATE_ENTRY_MCU_REF(_cfg, _src) (PMGR_SOC_PERF_STATE_ENTRY_0A_MCU_REF_CFG_SEL_INSRT(_cfg) | PMGR_SOC_PERF_STATE_ENTRY_0A_MCU_REF_SRC_SEL_INSRT(_src))
|
||||
#define PMGR_SOC_PERF_STATE_ENTRY_VID0(_src) (PMGR_SOC_PERF_STATE_ENTRY_0B_VID0_SRC_SEL_INSRT(_src))
|
||||
#define PMGR_SOC_PERF_STATE_ENTRY_VOLTAGE(_v) (PMGR_SOC_PERF_STATE_ENTRY_0C_VOLTAGE_INSRT(_v))
|
||||
|
||||
#define PMGR_SOC_PERF_STATE_ENTRY_COUNT (16)
|
||||
// First two entries used by AOP Config Engine
|
||||
#define PMGR_SOC_PERF_STATE_FIRST_ENTRY (PMGR_SOC_PERF_STATE_ENTRY_COUNT - kSOC_PERF_STATE_MAX_CNT)
|
||||
#define PMGR_SOC_PERF_STATE_TO_ENTRY(_s) (PMGR_SOC_PERF_STATE_ENTRY_COUNT - (_s) - 1)
|
||||
|
||||
#define kPMGR_GFX_STATE_MAX (16)
|
||||
#define rPMGR_GFX_PERF_STATE_ENTRY_A(_n) (*(volatile uint32_t *)(PMGR_BASE_ADDR + (_n) * 0x10 + PMGR_GFX_PERF_STATE_ENTRY0A_OFFSET))
|
||||
#define rPMGR_GFX_PERF_STATE_ENTRY_B(_n) (*(volatile uint32_t *)(PMGR_BASE_ADDR + (_n) * 0x10 + PMGR_GFX_PERF_STATE_ENTRY0B_OFFSET))
|
||||
#define rPMGR_GFX_PERF_STATE_ENTRY_C(_n) (*(volatile uint32_t *)(PMGR_BASE_ADDR + (_n) * 0x10 + PMGR_GFX_PERF_STATE_ENTRY0C_OFFSET))
|
||||
#define rPMGR_GFX_PERF_STATE_CTL (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_GFX_PERF_STATE_CTL_OFFSET))
|
||||
#define PMGR_GFX_PERF_STATE_CTL_ENABLE (1 << PMGR_GFX_PERF_STATE_CTL_ENABLE_SHIFT)
|
||||
#define rPMGR_GFX_PERF_STATE_SOCHOT (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_GFX_PERF_STATE_SOCHOT_OFFSET))
|
||||
|
||||
#define rPMGR_PS(_x) (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_PS_##_x##_PS_OFFSET))
|
||||
|
||||
#define PMGR_PS_RESET (1 << 31)
|
||||
#define PMGR_PS_AUTO_PM_EN (1 << 28)
|
||||
#define PMGR_PS_FORCE_NOACCESS (1 << 10)
|
||||
#define PMGR_PS_ACTUAL_PS_SHIFT (4)
|
||||
#define PMGR_PS_ACTUAL_PS_MASK (0xF)
|
||||
#define PMGR_PS_MANUAL_PS_MASK (0xF)
|
||||
#define PMGR_PS_RUN_MAX (0xF)
|
||||
#define PMGR_PS_CLOCK_OFF (0x4)
|
||||
#define PMGR_PS_POWER_OFF (0x0)
|
||||
|
||||
#define rPMGR_PWRGATE_MCC_CFG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_MCC_CFG0_OFFSET))
|
||||
#define rPMGR_PWRGATE_MCC_CFG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_MCC_CFG1_OFFSET))
|
||||
#define rPMGR_PWRGATE_MCC_CFG2 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_MCC_CFG2_OFFSET))
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
#define rPMGR_PWRGATE_DCS01_CFG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_DCS01_CFG0_OFFSET))
|
||||
#define rPMGR_PWRGATE_DCS01_CFG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_DCS01_CFG1_OFFSET))
|
||||
#define rPMGR_PWRGATE_DCS01_CFG2 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_DCS01_CFG2_OFFSET))
|
||||
#define rPMGR_PWRGATE_DCS23_CFG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_DCS23_CFG0_OFFSET))
|
||||
#define rPMGR_PWRGATE_DCS23_CFG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_DCS23_CFG1_OFFSET))
|
||||
#define rPMGR_PWRGATE_DCS23_CFG2 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_DCS23_CFG2_OFFSET))
|
||||
#elif SUB_PLATFORM_S8001
|
||||
#define rPMGR_PWRGATE_DCS0123_CFG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_DCS0123_CFG0_OFFSET))
|
||||
#define rPMGR_PWRGATE_DCS0123_CFG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_DCS0123_CFG1_OFFSET))
|
||||
#define rPMGR_PWRGATE_DCS0123_CFG2 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_DCS0123_CFG2_OFFSET))
|
||||
#define rPMGR_PWRGATE_DCS4567_CFG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_DCS4567_CFG0_OFFSET))
|
||||
#define rPMGR_PWRGATE_DCS4567_CFG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_DCS4567_CFG1_OFFSET))
|
||||
#define rPMGR_PWRGATE_DCS4567_CFG2 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_DCS4567_CFG2_OFFSET))
|
||||
#endif
|
||||
#define rPMGR_PWRGATE_ACS_CFG0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_ACS_CFG0_OFFSET))
|
||||
#define rPMGR_PWRGATE_ACS_CFG1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_ACS_CFG1_OFFSET))
|
||||
#define rPMGR_PWRGATE_ACS_CFG2 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PWRGATE_PWR_ACS_CFG2_OFFSET))
|
||||
|
||||
#define rPMGR_VOLMAN_CTL (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_CTL_OFFSET))
|
||||
#define rPMGR_VOLMAN_BUCK_MAP (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_BUCK_MAP_OFFSET))
|
||||
#define rPMGR_VOLMAN_SOC_VOLTAGE (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_SOC_VOLTAGE_OFFSET))
|
||||
#define rPMGR_VOLMAN_GFX_SRAM_VOLTAGE (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_GFX_SRAM_VOLTAGE_OFFSET))
|
||||
#define rPMGR_VOLMAN_CPU_SRAM_VOLTAGE (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_CPU_SRAM_VOLTAGE_OFFSET))
|
||||
#define rPMGR_VOLMAN_GFX_VOLTAGE (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_GFX_VOLTAGE_OFFSET))
|
||||
#define rPMGR_VOLMAN_CPU_VOLTAGE (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_CPU_VOLTAGE_OFFSET))
|
||||
#define rPMGR_VOLMAN_SOC_DELAY (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_SOC_DELAY_OFFSET))
|
||||
#define rPMGR_VOLMAN_GFX_SRAM_DELAY (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_GFX_SRAM_DELAY_OFFSET))
|
||||
#define rPMGR_VOLMAN_CPU_SRAM_DELAY (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_CPU_SRAM_DELAY_OFFSET))
|
||||
#define rPMGR_VOLMAN_GFX_DELAY (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_GFX_DELAY_OFFSET))
|
||||
#define rPMGR_VOLMAN_CPU_DELAY (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_CPU_DELAY_OFFSET))
|
||||
|
||||
#define PMGR_VOLMAN_DISABLE_CPU_VOL_CHANGE (1 << PMGR_VOLMAN_CTL_DISABLE_CPU_VOL_CHANGE_SHIFT)
|
||||
#define PMGR_VOLMAN_DISABLE_GFX_VOL_CHANGE (1 << PMGR_VOLMAN_CTL_DISABLE_GFX_VOL_CHANGE_SHIFT)
|
||||
#define PMGR_VOLMAN_DISABLE_CPU_SRAM_VOL_CHANGE (1 << PMGR_VOLMAN_CTL_DISABLE_CPU_SRAM_VOL_CHANGE_SHIFT)
|
||||
#define PMGR_VOLMAN_DISABLE_GFX_SRAM_VOL_CHANGE (1 << PMGR_VOLMAN_CTL_DISABLE_GFX_SRAM_VOL_CHANGE_SHIFT)
|
||||
#define PMGR_VOLMAN_DISABLE_SOC_VOL_CHANGE (1 << PMGR_VOLMAN_CTL_DISABLE_SOC_VOL_CHANGE_SHIFT)
|
||||
|
||||
#define PMGR_VOLMAN_VOLTAGE_PENDING (1 << 31)
|
||||
|
||||
#define rPMGR_EMA_FIXED_SOC0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_EMA_FIXED_SOC0_OFFSET))
|
||||
#define rPMGR_EMA_FIXED_SOC1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_EMA_FIXED_SOC1_OFFSET))
|
||||
#define rPMGR_EMA_GPU_SRAM_GFX (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_EMA_FIXED_GPU_SRAM_GFX_OFFSET))
|
||||
#define rPMGR_EMA_FIXED_GFX (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_EMA_FIXED_FIXED_GFX_OFFSET))
|
||||
#define rPMGR_EMA_FIXED_SEP0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_EMA_FIXED_FIXED_SEP0_OFFSET))
|
||||
|
||||
#define rPMGR_SCRATCH(_n) (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SCRATCH_0_OFFSET + ((_n)*4)))
|
||||
#define rPMGR_SCRATCH0 rPMGR_SCRATCH(0) /* Flags */
|
||||
#define rPMGR_SCRATCH1 rPMGR_SCRATCH(1)
|
||||
#define rPMGR_SCRATCH2 rPMGR_SCRATCH(2)
|
||||
#define rPMGR_SCRATCH3 rPMGR_SCRATCH(3)
|
||||
#define rPMGR_SCRATCH4 rPMGR_SCRATCH(4)
|
||||
#define rPMGR_SCRATCH5 rPMGR_SCRATCH(5)
|
||||
#define rPMGR_SCRATCH6 rPMGR_SCRATCH(6)
|
||||
#define rPMGR_SCRATCH7 rPMGR_SCRATCH(7)
|
||||
#define rPMGR_SCRATCH8 rPMGR_SCRATCH(8)
|
||||
#define rPMGR_SCRATCH9 rPMGR_SCRATCH(9)
|
||||
#define rPMGR_SCRATCH10 rPMGR_SCRATCH(10)
|
||||
#define rPMGR_SCRATCH11 rPMGR_SCRATCH(11)
|
||||
#define rPMGR_SCRATCH12 rPMGR_SCRATCH(12)
|
||||
#define rPMGR_SCRATCH13 rPMGR_SCRATCH(13) /* Memory info */
|
||||
#define rPMGR_SCRATCH14 rPMGR_SCRATCH(14) /* Boot Nonce 0 */
|
||||
#define rPMGR_SCRATCH15 rPMGR_SCRATCH(15) /* Boot Nonce 1 */
|
||||
#define rPMGR_SCRATCH16 rPMGR_SCRATCH(16) /* Boot Manifest Hash 0 */
|
||||
#define rPMGR_SCRATCH17 rPMGR_SCRATCH(17) /* Boot Manifest Hash 1 */
|
||||
#define rPMGR_SCRATCH18 rPMGR_SCRATCH(18) /* Boot Manifest Hash 2 */
|
||||
#define rPMGR_SCRATCH19 rPMGR_SCRATCH(19) /* Boot Manifest Hash 3 */
|
||||
#define rPMGR_SCRATCH20 rPMGR_SCRATCH(20) /* Boot Manifest Hash 4 */
|
||||
#define rPMGR_SCRATCH21 rPMGR_SCRATCH(21)
|
||||
#define rPMGR_SCRATCH22 rPMGR_SCRATCH(22)
|
||||
#define rPMGR_SCRATCH23 rPMGR_SCRATCH(23)
|
||||
|
||||
#define rMINIPMGR_SCRATCH(_n) (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_SCRATCH_OFFSET + ((_n)*4)))
|
||||
#define rMINIPMGR_SCRATCH0 rMINIPMGR_SCRATCH(0)
|
||||
#define rMINIPMGR_SCRATCH1 rMINIPMGR_SCRATCH(1) /* Consistent debug root pointer */
|
||||
#define rMINIPMGR_SCRATCH2 rMINIPMGR_SCRATCH(2)
|
||||
#define rMINIPMGR_SCRATCH3 rMINIPMGR_SCRATCH(3)
|
||||
#define rMINIPMGR_SCRATCH4 rMINIPMGR_SCRATCH(4)
|
||||
#define rMINIPMGR_SCRATCH5 rMINIPMGR_SCRATCH(5)
|
||||
#define rMINIPMGR_SCRATCH6 rMINIPMGR_SCRATCH(6)
|
||||
#define rMINIPMGR_SCRATCH7 rMINIPMGR_SCRATCH(7)
|
||||
#define rMINIPMGR_SCRATCH8 rMINIPMGR_SCRATCH(8)
|
||||
#define rMINIPMGR_SCRATCH9 rMINIPMGR_SCRATCH(9)
|
||||
#define rMINIPMGR_SCRATCH10 rMINIPMGR_SCRATCH(10)
|
||||
#define rMINIPMGR_SCRATCH11 rMINIPMGR_SCRATCH(11) /* Reconfig sequence debug */
|
||||
|
||||
|
||||
#define PMGR_THERMAL0_CTL0_SET (PMGR_BASE_ADDR + PMGR_THERMAL_0_CTL0_SET_OFFSET)
|
||||
#define PMGR_THERMAL0_CTL0_CLR (PMGR_BASE_ADDR + PMGR_THERMAL_0_CTL0_CLR_OFFSET)
|
||||
#define PMGR_THERMAL0_CTL1 (PMGR_BASE_ADDR + PMGR_THERMAL_0_CTL1_OFFSET)
|
||||
#define PMGR_THERMAL0_CTL2 (PMGR_BASE_ADDR + PMGR_THERMAL_0_CTL2_OFFSET)
|
||||
#define PMGR_THERMAL0_STATUS (PMGR_BASE_ADDR + PMGR_THERMAL_0_STATUS_OFFSET)
|
||||
#define PMGR_THERMAL0_PARAM (PMGR_BASE_ADDR + PMGR_THERMAL_0_PARAM_OFFSET)
|
||||
#define PMGR_THERMAL0_RDBK0 (PMGR_BASE_ADDR + PMGR_THERMAL_0_RDBK0_OFFSET)
|
||||
#define PMGR_THERMAL0_RDBK1 (PMGR_BASE_ADDR + PMGR_THERMAL_0_RDBK1_OFFSET)
|
||||
#define PMGR_THERMAL0_SUM (PMGR_BASE_ADDR + PMGR_THERMAL_0_SUM_OFFSET)
|
||||
#define PMGR_THERMAL0_SUM_CNT (PMGR_BASE_ADDR + PMGR_THERMAL_0_SUM_CNT_OFFSET)
|
||||
#define PMGR_THERMAL0_PIECE0 (PMGR_BASE_ADDR + PMGR_THERMAL_0_PIECE0_OFFSET)
|
||||
#define PMGR_THERMAL0_PIECE1 (PMGR_BASE_ADDR + PMGR_THERMAL_0_PIECE1_OFFSET)
|
||||
#define PMGR_THERMAL0_PIECE2 (PMGR_BASE_ADDR + PMGR_THERMAL_0_PIECE2_OFFSET)
|
||||
#define PMGR_THERMAL0_ALARM0 (PMGR_BASE_ADDR + PMGR_THERMAL_0_ALARM0_OFFSET)
|
||||
#define PMGR_THERMAL0_ALARM1 (PMGR_BASE_ADDR + PMGR_THERMAL_0_ALARM1_OFFSET)
|
||||
#define PMGR_THERMAL0_ALARM2 (PMGR_BASE_ADDR + PMGR_THERMAL_0_ALARM2_OFFSET)
|
||||
#define PMGR_THERMAL0_ALARM3 (PMGR_BASE_ADDR + PMGR_THERMAL_0_ALARM3_OFFSET)
|
||||
#define PMGR_THERMAL0_FAILSAFE_TRIP_TEMP_0 (PMGR_BASE_ADDR + PMGR_THERMAL_0_FAILSAFE_TRIP_TEMP_0_OFFSET)
|
||||
#define PMGR_THERMAL0_FAILSAFE_TRIP_TEMP_1 (PMGR_BASE_ADDR + PMGR_THERMAL_0_FAILSAFE_TRIP_TEMP_1_OFFSET)
|
||||
#define PMGR_THERMAL1_CTL0_SET (PMGR_BASE_ADDR + PMGR_THERMAL_1_CTL0_SET_OFFSET)
|
||||
#define PMGR_THERMAL1_CTL0_CLR (PMGR_BASE_ADDR + PMGR_THERMAL_1_CTL0_CLR_OFFSET)
|
||||
#define PMGR_THERMAL1_CTL1 (PMGR_BASE_ADDR + PMGR_THERMAL_1_CTL1_OFFSET)
|
||||
#define PMGR_THERMAL1_CTL2 (PMGR_BASE_ADDR + PMGR_THERMAL_1_CTL2_OFFSET)
|
||||
#define PMGR_THERMAL1_STATUS (PMGR_BASE_ADDR + PMGR_THERMAL_1_STATUS_OFFSET)
|
||||
#define PMGR_THERMAL1_PARAM (PMGR_BASE_ADDR + PMGR_THERMAL_1_PARAM_OFFSET)
|
||||
#define PMGR_THERMAL1_RDBK0 (PMGR_BASE_ADDR + PMGR_THERMAL_1_RDBK0_OFFSET)
|
||||
#define PMGR_THERMAL1_RDBK1 (PMGR_BASE_ADDR + PMGR_THERMAL_1_RDBK1_OFFSET)
|
||||
#define PMGR_THERMAL1_SUM (PMGR_BASE_ADDR + PMGR_THERMAL_1_SUM_OFFSET)
|
||||
#define PMGR_THERMAL1_SUM_CNT (PMGR_BASE_ADDR + PMGR_THERMAL_1_SUM_CNT_OFFSET)
|
||||
#define PMGR_THERMAL1_PIECE0 (PMGR_BASE_ADDR + PMGR_THERMAL_1_PIECE0_OFFSET)
|
||||
#define PMGR_THERMAL1_PIECE1 (PMGR_BASE_ADDR + PMGR_THERMAL_1_PIECE1_OFFSET)
|
||||
#define PMGR_THERMAL1_PIECE2 (PMGR_BASE_ADDR + PMGR_THERMAL_1_PIECE2_OFFSET)
|
||||
#define PMGR_THERMAL1_ALARM0 (PMGR_BASE_ADDR + PMGR_THERMAL_1_ALARM0_OFFSET)
|
||||
#define PMGR_THERMAL1_ALARM1 (PMGR_BASE_ADDR + PMGR_THERMAL_1_ALARM1_OFFSET)
|
||||
#define PMGR_THERMAL1_ALARM2 (PMGR_BASE_ADDR + PMGR_THERMAL_1_ALARM2_OFFSET)
|
||||
#define PMGR_THERMAL1_ALARM3 (PMGR_BASE_ADDR + PMGR_THERMAL_1_ALARM3_OFFSET)
|
||||
#define PMGR_THERMAL1_FAILSAFE_TRIP_TEMP_0 (PMGR_BASE_ADDR + PMGR_THERMAL_1_FAILSAFE_TRIP_TEMP_0_OFFSET)
|
||||
#define PMGR_THERMAL1_FAILSAFE_TRIP_TEMP_1 (PMGR_BASE_ADDR + PMGR_THERMAL_1_FAILSAFE_TRIP_TEMP_1_OFFSET)
|
||||
#define PMGR_THERMAL2_CTL0_SET (PMGR_BASE_ADDR + PMGR_THERMAL_2_CTL0_SET_OFFSET)
|
||||
#define PMGR_THERMAL2_CTL0_CLR (PMGR_BASE_ADDR + PMGR_THERMAL_2_CTL0_CLR_OFFSET)
|
||||
#define PMGR_THERMAL2_CTL1 (PMGR_BASE_ADDR + PMGR_THERMAL_2_CTL1_OFFSET)
|
||||
#define PMGR_THERMAL2_CTL2 (PMGR_BASE_ADDR + PMGR_THERMAL_2_CTL2_OFFSET)
|
||||
#define PMGR_THERMAL2_STATUS (PMGR_BASE_ADDR + PMGR_THERMAL_2_STATUS_OFFSET)
|
||||
#define PMGR_THERMAL2_PARAM (PMGR_BASE_ADDR + PMGR_THERMAL_2_PARAM_OFFSET)
|
||||
#define PMGR_THERMAL2_RDBK0 (PMGR_BASE_ADDR + PMGR_THERMAL_2_RDBK0_OFFSET)
|
||||
#define PMGR_THERMAL2_RDBK1 (PMGR_BASE_ADDR + PMGR_THERMAL_2_RDBK1_OFFSET)
|
||||
#define PMGR_THERMAL2_SUM (PMGR_BASE_ADDR + PMGR_THERMAL_2_SUM_OFFSET)
|
||||
#define PMGR_THERMAL2_SUM_CNT (PMGR_BASE_ADDR + PMGR_THERMAL_2_SUM_CNT_OFFSET)
|
||||
#define PMGR_THERMAL2_PIECE0 (PMGR_BASE_ADDR + PMGR_THERMAL_2_PIECE0_OFFSET)
|
||||
#define PMGR_THERMAL2_PIECE1 (PMGR_BASE_ADDR + PMGR_THERMAL_2_PIECE1_OFFSET)
|
||||
#define PMGR_THERMAL2_PIECE2 (PMGR_BASE_ADDR + PMGR_THERMAL_2_PIECE2_OFFSET)
|
||||
#define PMGR_THERMAL2_ALARM0 (PMGR_BASE_ADDR + PMGR_THERMAL_2_ALARM0_OFFSET)
|
||||
#define PMGR_THERMAL2_ALARM1 (PMGR_BASE_ADDR + PMGR_THERMAL_2_ALARM1_OFFSET)
|
||||
#define PMGR_THERMAL2_ALARM2 (PMGR_BASE_ADDR + PMGR_THERMAL_2_ALARM2_OFFSET)
|
||||
#define PMGR_THERMAL2_ALARM3 (PMGR_BASE_ADDR + PMGR_THERMAL_2_ALARM3_OFFSET)
|
||||
#define PMGR_THERMAL2_FAILSAFE_TRIP_TEMP_0 (PMGR_BASE_ADDR + PMGR_THERMAL_2_FAILSAFE_TRIP_TEMP_0_OFFSET)
|
||||
#define PMGR_THERMAL2_FAILSAFE_TRIP_TEMP_1 (PMGR_BASE_ADDR + PMGR_THERMAL_2_FAILSAFE_TRIP_TEMP_1_OFFSET)
|
||||
#if SUB_PLATFORM_S8001
|
||||
#define PMGR_THERMAL3_CTL0_SET (PMGR_BASE_ADDR + PMGR_THERMAL_3_CTL0_SET_OFFSET)
|
||||
#define PMGR_THERMAL3_CTL0_CLR (PMGR_BASE_ADDR + PMGR_THERMAL_3_CTL0_CLR_OFFSET)
|
||||
#define PMGR_THERMAL3_CTL1 (PMGR_BASE_ADDR + PMGR_THERMAL_3_CTL1_OFFSET)
|
||||
#define PMGR_THERMAL3_CTL2 (PMGR_BASE_ADDR + PMGR_THERMAL_3_CTL2_OFFSET)
|
||||
#define PMGR_THERMAL3_STATUS (PMGR_BASE_ADDR + PMGR_THERMAL_3_STATUS_OFFSET)
|
||||
#define PMGR_THERMAL3_PARAM (PMGR_BASE_ADDR + PMGR_THERMAL_3_PARAM_OFFSET)
|
||||
#define PMGR_THERMAL3_RDBK0 (PMGR_BASE_ADDR + PMGR_THERMAL_3_RDBK0_OFFSET)
|
||||
#define PMGR_THERMAL3_RDBK1 (PMGR_BASE_ADDR + PMGR_THERMAL_3_RDBK1_OFFSET)
|
||||
#define PMGR_THERMAL3_SUM (PMGR_BASE_ADDR + PMGR_THERMAL_3_SUM_OFFSET)
|
||||
#define PMGR_THERMAL3_SUM_CNT (PMGR_BASE_ADDR + PMGR_THERMAL_3_SUM_CNT_OFFSET)
|
||||
#define PMGR_THERMAL3_PIECE0 (PMGR_BASE_ADDR + PMGR_THERMAL_3_PIECE0_OFFSET)
|
||||
#define PMGR_THERMAL3_PIECE1 (PMGR_BASE_ADDR + PMGR_THERMAL_3_PIECE1_OFFSET)
|
||||
#define PMGR_THERMAL3_PIECE2 (PMGR_BASE_ADDR + PMGR_THERMAL_3_PIECE2_OFFSET)
|
||||
#define PMGR_THERMAL3_ALARM0 (PMGR_BASE_ADDR + PMGR_THERMAL_3_ALARM0_OFFSET)
|
||||
#define PMGR_THERMAL3_ALARM1 (PMGR_BASE_ADDR + PMGR_THERMAL_3_ALARM1_OFFSET)
|
||||
#define PMGR_THERMAL3_ALARM2 (PMGR_BASE_ADDR + PMGR_THERMAL_3_ALARM2_OFFSET)
|
||||
#define PMGR_THERMAL3_ALARM3 (PMGR_BASE_ADDR + PMGR_THERMAL_3_ALARM3_OFFSET)
|
||||
#define PMGR_THERMAL3_FAILSAFE_TRIP_TEMP_0 (PMGR_BASE_ADDR + PMGR_THERMAL_3_FAILSAFE_TRIP_TEMP_0_OFFSET)
|
||||
#define PMGR_THERMAL3_FAILSAFE_TRIP_TEMP_1 (PMGR_BASE_ADDR + PMGR_THERMAL_3_FAILSAFE_TRIP_TEMP_1_OFFSET)
|
||||
#endif
|
||||
|
||||
#define rPMGR_THERMAL0_PARAM (*(volatile u_int32_t *)PMGR_THERMAL0_PARAM)
|
||||
#define rPMGR_THERMAL1_PARAM (*(volatile u_int32_t *)PMGR_THERMAL1_PARAM)
|
||||
#define rPMGR_THERMAL2_PARAM (*(volatile u_int32_t *)PMGR_THERMAL2_PARAM)
|
||||
#if SUB_PLATFORM_S8001
|
||||
#define rPMGR_THERMAL3_PARAM (*(volatile u_int32_t *)PMGR_THERMAL3_PARAM)
|
||||
#endif
|
||||
|
||||
#define rPMGR_SOC_TVM_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_CTL_OFFSET))
|
||||
#define rPMGR_SOC_TVM_THRESH0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH0_OFFSET))
|
||||
#define rPMGR_SOC_TVM_THRESH1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH1_OFFSET))
|
||||
#define rPMGR_SOC_TVM_THRESH2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH2_OFFSET))
|
||||
#define rPMGR_SOC_TVM_TEMP0_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_TEMP0_CFG_OFFSET))
|
||||
#define rPMGR_SOC_TVM_TEMP1_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_TEMP1_CFG_OFFSET))
|
||||
#define rPMGR_SOC_TVM_DEBUG0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG0_OFFSET))
|
||||
#define rPMGR_SOC_TVM_DEBUG1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG1_OFFSET))
|
||||
#define rPMGR_SOC_TVM_DEBUG2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG2_OFFSET))
|
||||
|
||||
#define rPMGR_GFX_TVM_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_CTL_OFFSET))
|
||||
#define rPMGR_GFX_TVM_THRESH0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH0_OFFSET))
|
||||
#define rPMGR_GFX_TVM_THRESH1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH1_OFFSET))
|
||||
#define rPMGR_GFX_TVM_THRESH2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH2_OFFSET))
|
||||
#define rPMGR_GFX_TVM_TEMP0_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_TEMP0_CFG_OFFSET))
|
||||
#define rPMGR_GFX_TVM_TEMP1_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_TEMP1_CFG_OFFSET))
|
||||
#define rPMGR_GFX_TVM_DEBUG0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG0_OFFSET))
|
||||
#define rPMGR_GFX_TVM_DEBUG1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG1_OFFSET))
|
||||
#define rPMGR_GFX_TVM_DEBUG2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG2_OFFSET))
|
||||
|
||||
#define PMGR_TVM_THRESH(_t) ((_t) & 0x1FF)
|
||||
#define PMGR_TVM_TEMP_CFG_MAX_OFFSET(_mo) (((_mo) & 0x1FF) << 16)
|
||||
#define PMGR_TVM_TEMP_CFG_MIN_OFFSET(_mo) (((_mo) & 0x1FF) << 0)
|
||||
|
||||
#define rPMGR_MISC_CFG_ACG (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_MISC_CFG_ACG_OFFSET))
|
||||
#define rPMGR_MISC_PCIE_PCIE_CTL (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_MISC_PCIE_PCIE_CTL_OFFSET))
|
||||
|
||||
#define rPMGR_MISC_SPARE0 (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_MISC_SPARE_SPARE0_OFFSET))
|
||||
|
||||
#define rPMGR_DEBUG_PMGR_DEBUG17 (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_DEBUG_17_OFFSET))
|
||||
|
||||
#define rPMGR_CHIP_WDOG_TMR (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_CHIP_WATCHDOG_TIMER_OFFSET))
|
||||
#define rPMGR_CHIP_WDOG_RST_CNT (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_CHIP_WATCHDOG_RESET_COUNT_OFFSET))
|
||||
#define rPMGR_CHIP_WDOG_INTR_CNT (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_CHIP_WATCHDOG_INTERRUPT_COUNT_OFFSET))
|
||||
#define rPMGR_CHIP_WDOG_CTL (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_CHIP_WATCHDOG_CONTROL_OFFSET))
|
||||
#define rPMGR_SYS_WDOG_TMR (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_SYS_WATCHDOG_TIMER_OFFSET))
|
||||
#define rPMGR_SYS_WDOG_RST_CNT (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_SYS_WATCHDOG_RESET_COUNT_OFFSET))
|
||||
#define rPMGR_SYS_WDOG_CTL (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_SYS_WATCHDOG_CONTROL_OFFSET))
|
||||
|
||||
#define rMINIPMGR_LPO_CTL (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_LPO_CTL_OFFSET))
|
||||
#define MINIPMGR_LPO_CTL_ENABLE (1 << MINIPMGR_LPO_CTL_ENABLE_SHIFT)
|
||||
#define MINIPMGR_LPO_CTL_PENDING (1 << MINIPMGR_LPO_CTL_PENDING_SHIFT)
|
||||
#define rMINIPMGR_LPO_CFG (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_LPO_CFG_OFFSET))
|
||||
|
||||
#define rMINIPMGR_CLK_CFG(_x) (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_CLKCFG_##_x##_CLK_CFG_OFFSET))
|
||||
#define rMINIPMGR_CLK_DIVIDER_ACG_CFG (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_CLKCFG_CLK_DIVIDER_ACG_CFG_OFFSET))
|
||||
|
||||
#define rMINIPMGR_PS(_x) (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_PS_##_x##_PS_OFFSET))
|
||||
|
||||
#define rMINIPMGR_MISC_CFG_ACG (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_MISC_CFG_ACG_OFFSET))
|
||||
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
enum {
|
||||
PMGR_CLK_OSC = 0, // 0x00
|
||||
PMGR_CLK_PLL0, // 0x01
|
||||
PMGR_CLK_PLL1, // 0x02
|
||||
PMGR_CLK_PLL2, // 0x03
|
||||
PMGR_CLK_PLL3, // 0x04
|
||||
PMGR_CLK_PLL4, // 0x05
|
||||
PMGR_CLK_PLL5, // 0x06
|
||||
PMGR_CLK_PLL_PCIE, // 0x07
|
||||
PMGR_CLK_CPU, // 0x08
|
||||
PMGR_CLK_GFX_FENDER, // 0x09
|
||||
PMGR_CLK_FIRST = PMGR_CLK_GFX_FENDER,
|
||||
PMGR_CLK_MCU_REF, // 0x0A
|
||||
PMGR_CLK_PMP, // 0x0B
|
||||
PMGR_CLK_TEMP_MIPI_DSI, // 0x0C
|
||||
PMGR_CLK_NCO_REF0, // 0x0D
|
||||
PMGR_CLK_NCO_REF1, // 0x0E
|
||||
PMGR_CLK_NCO_ALG0, // 0x0F
|
||||
PMGR_CLK_NCO_ALG1, // 0x10
|
||||
PMGR_CLK_HSICPHY_REF_12M, // 0x11
|
||||
PMGR_CLK_USB480_0, // 0x12
|
||||
PMGR_CLK_USB480_1, // 0x13
|
||||
PMGR_CLK_USB_OHCI_48M, // 0x14
|
||||
PMGR_CLK_USB, // 0x15
|
||||
PMGR_CLK_USB_FREE_60M, // 0x16
|
||||
PMGR_CLK_SIO_C, // 0x17
|
||||
PMGR_CLK_SIO_P, // 0x18
|
||||
PMGR_CLK_ISP_C, // 0x19
|
||||
PMGR_CLK_ISP, // 0x1A
|
||||
PMGR_CLK_ISP_SENSOR0_REF, // 0x1B
|
||||
PMGR_CLK_ISP_SENSOR1_REF, // 0x1C
|
||||
PMGR_CLK_VDEC, // 0x1D
|
||||
PMGR_CLK_VENC, // 0x1E
|
||||
PMGR_CLK_VID0, // 0x1F
|
||||
PMGR_CLK_DISP0, // 0x20
|
||||
PMGR_CLK_AJPEG_IP, // 0x21
|
||||
PMGR_CLK_AJPEG_WRAP, // 0x22
|
||||
PMGR_CLK_MSR, // 0x23
|
||||
PMGR_CLK_AF, // 0x24
|
||||
PMGR_CLK_SBR, // 0x25
|
||||
PMGR_CLK_MCA0_M, // 0x26
|
||||
PMGR_CLK_MCA1_M, // 0x27
|
||||
PMGR_CLK_MCA2_M, // 0x28
|
||||
PMGR_CLK_MCA3_M, // 0x29
|
||||
PMGR_CLK_MCA4_M, // 0x2A
|
||||
PMGR_CLK_SEP, // 0x2B
|
||||
PMGR_CLK_GPIO, // 0x2C
|
||||
PMGR_CLK_SPI0_N, // 0x2D
|
||||
PMGR_CLK_SPI1_N, // 0x2E
|
||||
PMGR_CLK_SPI2_N, // 0x2F
|
||||
PMGR_CLK_SPI3_N, // 0x30
|
||||
PMGR_CLK_PCIE_APP, // 0x31
|
||||
PMGR_CLK_TMPS, // 0x32
|
||||
PMGR_CLK_UVD, // 0x33
|
||||
PMGR_CLK_LAST = PMGR_CLK_UVD,
|
||||
PMGR_CLK_S0, // 0x34
|
||||
PMGR_CLK_SPARE_FIRST = PMGR_CLK_S0,
|
||||
PMGR_CLK_S1, // 0x35
|
||||
PMGR_CLK_S2, // 0x36
|
||||
PMGR_CLK_S3, // 0x37
|
||||
PMGR_CLK_ISP_REF0, // 0x38
|
||||
PMGR_CLK_ISP_REF1, // 0x39
|
||||
PMGR_CLK_SPARE_LAST = PMGR_CLK_ISP_REF1,
|
||||
PMGR_CLK_LPO, // 0x3A
|
||||
PMGR_CLK_AOP, // 0x3B
|
||||
PMGR_CLK_MINI_FIRST = PMGR_CLK_AOP,
|
||||
PMGR_CLK_UART0, // 0x3C
|
||||
PMGR_CLK_UART1, // 0x3D
|
||||
PMGR_CLK_UART2, // 0x3E
|
||||
PMGR_CLK_AOP_MCA0_M, // 0x3F
|
||||
PMGR_CLK_I2CM, // 0x40
|
||||
PMGR_CLK_PROXY_FABRIC, // 0x41
|
||||
PMGR_CLK_PROXY_MCU_REF, // 0x42
|
||||
PMGR_CLK_MINI_LAST = PMGR_CLK_PROXY_MCU_REF,
|
||||
PMGR_CLK_COUNT, // 0x43
|
||||
PMGR_CLK_NOT_SUPPORTED
|
||||
};
|
||||
|
||||
#elif SUB_PLATFORM_S8001
|
||||
|
||||
enum {
|
||||
PMGR_CLK_OSC = 0, // 0x00
|
||||
PMGR_CLK_PLL0, // 0x01
|
||||
PMGR_CLK_PLL1, // 0x02
|
||||
PMGR_CLK_PLL2, // 0x03
|
||||
PMGR_CLK_PLL3, // 0x04
|
||||
PMGR_CLK_PLL4, // 0x05
|
||||
PMGR_CLK_PLL5, // 0x06
|
||||
PMGR_CLK_PLL6, // 0x07
|
||||
PMGR_CLK_PLL7, // 0x08
|
||||
PMGR_CLK_PLL_PCIE, // 0x09
|
||||
PMGR_CLK_CPU, // 0x0A
|
||||
PMGR_CLK_GFX_FENDER, // 0x0B
|
||||
PMGR_CLK_FIRST = PMGR_CLK_GFX_FENDER,
|
||||
PMGR_CLK_MCU_REF, // 0x0C
|
||||
PMGR_CLK_PMP, // 0x0D
|
||||
PMGR_CLK_NCO_REF0, // 0x0E
|
||||
PMGR_CLK_NCO_REF1, // 0x0F
|
||||
PMGR_CLK_NCO_ALG0, // 0x10
|
||||
PMGR_CLK_NCO_ALG1, // 0x11
|
||||
PMGR_CLK_HSICPHY_REF_12M, // 0x12
|
||||
PMGR_CLK_USB480_0, // 0x13
|
||||
PMGR_CLK_USB_OHCI_48M, // 0x14
|
||||
PMGR_CLK_USB, // 0x15
|
||||
PMGR_CLK_USB_FREE_60M, // 0x16
|
||||
PMGR_CLK_SIO_C, // 0x17
|
||||
PMGR_CLK_SIO_P, // 0x18
|
||||
PMGR_CLK_ISP_C, // 0x19
|
||||
PMGR_CLK_ISP, // 0x1A
|
||||
PMGR_CLK_ISP_SENSOR0_REF, // 0x1B
|
||||
PMGR_CLK_ISP_SENSOR1_REF, // 0x1C
|
||||
PMGR_CLK_VDEC, // 0x1D
|
||||
PMGR_CLK_VENC, // 0x1E
|
||||
PMGR_CLK_VID0, // 0x1F
|
||||
PMGR_CLK_DISP0, // 0x20
|
||||
PMGR_CLK_AJPEG_IP, // 0x21
|
||||
PMGR_CLK_AJPEG_WRAP, // 0x22
|
||||
PMGR_CLK_MSR, // 0x23
|
||||
PMGR_CLK_AF, // 0x24
|
||||
PMGR_CLK_SBR, // 0x25
|
||||
PMGR_CLK_MCA0_M, // 0x26
|
||||
PMGR_CLK_MCA1_M, // 0x27
|
||||
PMGR_CLK_MCA2_M, // 0x28
|
||||
PMGR_CLK_MCA3_M, // 0x29
|
||||
PMGR_CLK_MCA4_M, // 0x2A
|
||||
PMGR_CLK_SEP, // 0x2B
|
||||
PMGR_CLK_GPIO, // 0x2C
|
||||
PMGR_CLK_SPI0_N, // 0x2D
|
||||
PMGR_CLK_SPI1_N, // 0x2E
|
||||
PMGR_CLK_SPI2_N, // 0x2F
|
||||
PMGR_CLK_SPI3_N, // 0x30
|
||||
PMGR_CLK_PCIE_APP, // 0x31
|
||||
PMGR_CLK_TMPS, // 0x32
|
||||
PMGR_CLK_UVD, // 0x33
|
||||
PMGR_CLK_VID1, // 0x34
|
||||
PMGR_CLK_DISP1, // 0x35
|
||||
PMGR_CLK_SRS, // 0x36
|
||||
PMGR_CLK_LAST = PMGR_CLK_SRS,
|
||||
PMGR_CLK_S0, // 0x37
|
||||
PMGR_CLK_SPARE_FIRST = PMGR_CLK_S0,
|
||||
PMGR_CLK_S1, // 0x38
|
||||
PMGR_CLK_S2, // 0x39
|
||||
PMGR_CLK_S3, // 0x3A
|
||||
PMGR_CLK_ISP_REF0, // 0x3B
|
||||
PMGR_CLK_ISP_REF1, // 0x3C
|
||||
PMGR_CLK_SPARE_LAST = PMGR_CLK_ISP_REF1,
|
||||
PMGR_CLK_LPO, // 0x3D
|
||||
PMGR_CLK_AOP, // 0x3E
|
||||
PMGR_CLK_MINI_FIRST = PMGR_CLK_AOP,
|
||||
PMGR_CLK_UART0, // 0x3F
|
||||
PMGR_CLK_UART1, // 0x40
|
||||
PMGR_CLK_UART2, // 0x41
|
||||
PMGR_CLK_AOP_MCA0_M, // 0x42
|
||||
PMGR_CLK_I2CM, // 0x43
|
||||
PMGR_CLK_PROXY_FABRIC, // 0x44
|
||||
PMGR_CLK_PROXY_MCU_REF, // 0x45
|
||||
PMGR_CLK_MINI_LAST = PMGR_CLK_PROXY_MCU_REF,
|
||||
PMGR_CLK_COUNT, // 0x46
|
||||
PMGR_CLK_NOT_SUPPORTED
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
////////////////////////////////////////////////////////////
|
||||
//
|
||||
// CCC specific
|
||||
//
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#define rACC_PRE_TD_TMR (*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_PRE_TD_TMR_OFFSET))
|
||||
#define rACC_PRE_FLUSH_TMR (*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_PRE_FLUSH_TMR_OFFSET))
|
||||
|
||||
#define rACC_APSC_SCR (*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_PWRCTL_APSC_SCR_OFFSET))
|
||||
#define ACC_APSC_PENDING (1 << ACC_PWRCTL_APSC_SCR_MANUAL_PENDING_SHIFT)
|
||||
#define ACC_APSC_MANUAL_CHANGE(_d) ((1 << ACC_PWRCTL_APSC_SCR_MANUAL_CHANGE_SHIFT) | ACC_PWRCTL_APSC_SCR_MANUAL_ST_INSRT((uint64_t)_d))
|
||||
|
||||
#define rACC_DVFM_CFG (*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_DVFM_CFG_OFFSET))
|
||||
|
||||
#define rACC_DVFM_SCR (*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_PWRCTL_DVFM_SCR_OFFSET)) // 64-bit
|
||||
#define ACC_DVFM_SCR_TEMPSENSORMODE (ACC_PWRCTL_DVFM_MODE_INSRT((uint64_t)1))
|
||||
|
||||
#define rACC_DVFM_CFG_SEL (*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_DVFM_CFG_SEL_OFFSET))
|
||||
|
||||
#define rACC_DVFM_CFG1 (*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_DVFM_CFG1_OFFSET))
|
||||
|
||||
#define rACC_MSTR_PLLCTL (*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_MSTR_PLLCTL_OFFSET))
|
||||
|
||||
#define kDVFM_STATE_BYPASS (0)
|
||||
#define kDVFM_STATE_SECUREROM (kDVFM_STATE_BYPASS + 1)
|
||||
#define kDVFM_STATE_IBOOT (kDVFM_STATE_BYPASS + 2)
|
||||
#define kDVFM_STATE_V0 (kDVFM_STATE_IBOOT + 0)
|
||||
#define kDVFM_STATE_V1 (kDVFM_STATE_IBOOT + 1)
|
||||
#define kDVFM_STATE_V2 (kDVFM_STATE_IBOOT + 2)
|
||||
#define kDVFM_STATE_V3 (kDVFM_STATE_IBOOT + 3)
|
||||
#define kDVFM_STATE_V4 (kDVFM_STATE_IBOOT + 4)
|
||||
#define kDVFM_STATE_V5 (kDVFM_STATE_IBOOT + 5)
|
||||
#define kDVFM_STATE_V6 (kDVFM_STATE_IBOOT + 6)
|
||||
|
||||
#define kDVFM_STATE_VMAX (kDVFM_STATE_V6)
|
||||
|
||||
#define kDVFM_STATE_VNOM (kDVFM_STATE_V0)
|
||||
#define kDVFM_STATE_VBOOST (kDVFM_STATE_VNOM + 1)
|
||||
|
||||
#define kDVFM_STATE_IBOOT_CNT (kDVFM_STATE_VMAX + 1)
|
||||
|
||||
#define kVOLTAGE_STATES1_COUNT (kDVFM_STATE_VMAX - kDVFM_STATE_V0 + 1)
|
||||
#define kVOLTAGE_STATES1_SIZE (kVOLTAGE_STATES1_COUNT*2) // Minimum size of voltage-state1 property in devicetree
|
||||
|
||||
#define kDVFM_STATE_MAX_CNT (16)
|
||||
|
||||
#define kDVFM_STATE_IBOOT_VCO_WA (kDVFM_STATE_MAX_CNT - 1)
|
||||
#define kDVFM_STATE_VCO_WA_MAX_CNT (4)
|
||||
|
||||
#define rACC_DVFM_ST(_n) (*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST0_OFFSET + ((_n) < 8 ? ((_n) * 8) : 0x300 + (((_n) - 8) * 8))))
|
||||
#define ACC_DVFM_ST_SAFE_VOL(_sv) (ACC_PWRCTL_DVFM_ST0_SAFE_VOL_INSRT((uint64_t)_sv))
|
||||
#define ACC_DVFM_ST_VOL_ADJ3(_va) (ACC_PWRCTL_DVFM_ST0_VOL_ADJ3_INSRT((uint64_t)_va))
|
||||
#define ACC_DVFM_ST_VOL_ADJ2(_va) (ACC_PWRCTL_DVFM_ST0_VOL_ADJ2_INSRT((uint64_t)_va))
|
||||
#define ACC_DVFM_ST_VOL_ADJ1(_va) (ACC_PWRCTL_DVFM_ST0_VOL_ADJ1_INSRT((uint64_t)_va))
|
||||
#define ACC_DVFM_ST_VOL_ADJ0(_va) (ACC_PWRCTL_DVFM_ST0_VOL_ADJ0_INSRT((uint64_t)_va))
|
||||
#define ACC_DVFM_ST_VOL_BYP(_vb) (ACC_PWRCTL_DVFM_ST0_VOL_BYP_INSRT((uint64_t)_vb))
|
||||
#define ACC_DVFM_ST_CLK_SRC(_s) (ACC_PWRCTL_DVFM_ST0_CLK_SRC_INSRT((uint64_t)_s))
|
||||
#define ACC_DVFM_ST_PLL_P(_p) (ACC_PWRCTL_DVFM_ST0_PRE_DIV_P_INSRT((uint64_t)_p))
|
||||
#define ACC_DVFM_ST_PLL_M(_m) (ACC_PWRCTL_DVFM_ST0_FBK_DIV_M_INSRT((uint64_t)_m))
|
||||
#define ACC_DVFM_ST_PLL_S(_s) (ACC_PWRCTL_DVFM_ST0_PST_DIV_S_INSRT((uint64_t)_s))
|
||||
#define ACC_DVFM_ST_PLL_PMS_MASK (ACC_PWRCTL_DVFM_ST0_PRE_DIV_P_UMASK | ACC_PWRCTL_DVFM_ST0_FBK_DIV_M_UMASK | ACC_PWRCTL_DVFM_ST0_PST_DIV_S_UMASK)
|
||||
|
||||
#define rACC_PLL_SCR1 (*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_PLL_SCR1_OFFSET))
|
||||
#define rACC_PLL_CFG2 (*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_PLL_CFG2_OFFSET))
|
||||
#define rACC_DVMR_SCR (*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_PWRCTL_DVMR_SCR_OFFSET))
|
||||
|
||||
#define rACC_DVFM_ST_EXT(_n) (*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST0_EXT_OFFSET + ((_n) * 8)))
|
||||
#define ACC_DVFM_ST_BIU_DIV_HI_VOL(_d) (ACC_PWRCTL_DVFM_ST0_EXT_BIU_DIV4_HI_VOL_INSRT((uint64_t)(_d)))
|
||||
#define ACC_DVFM_ST_BIU_DIV_LO_VOL(_d) (ACC_PWRCTL_DVFM_ST0_EXT_BIU_DIV4_LO_VOL_INSRT((uint64_t)(_d)))
|
||||
#define ACC_DVFM_ST_DVMR_MAX_WGT(_w) (ACC_PWRCTL_DVFM_ST0_EXT_DVMR_MAX_WGT_INSRT((uint64_t)(_w)))
|
||||
#define ACC_DVFM_ST_SRAM_VOL(_v) (ACC_PWRCTL_DVFM_ST0_EXT_SRAM_VOL_INSRT((uint64_t)(_v)))
|
||||
#define ACC_DVFM_ST_DVFM_MAX_ADJ(_a) (ACC_PWRCTL_DVFM_ST0_EXT_DVFM_MAX_ADJ_INSRT((uint64_t)(_a)))
|
||||
#define ACC_DVFM_ST_DVMR_ADJ2(_a) (ACC_PWRCTL_DVFM_ST0_EXT_DVMR_ADJ2_INSRT((uint64_t)(_a)))
|
||||
#define ACC_DVFM_ST_DVMR_ADJ1(_a) (ACC_PWRCTL_DVFM_ST0_EXT_DVMR_ADJ1_INSRT((uint64_t)(_a)))
|
||||
#define ACC_DVFM_ST_DVMR_ADJ0(_a) (ACC_PWRCTL_DVFM_ST0_EXT_DVMR_ADJ0_INSRT((uint64_t)(_a)))
|
||||
|
||||
#define rACC_NRG_ACC_SCALE_TAB (*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_PWRCTL_NRG_ACC_SCALE_TAB_OFFSET))
|
||||
#define rACC_NRG_ACC_SCALE_TAB_EXT (*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_PWRCTL_NRG_ACC_SCALE_TAB_EXT_OFFSET))
|
||||
#define rACC_LKG_EST_TAB (*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_PWRCTL_LKG_EST_TAB_OFFSET))
|
||||
#define rACC_LKG_EST_TAB_EXT (*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_PWRCTL_LKG_EST_TAB_EXT_OFFSET))
|
||||
#define rACC_DPE0_DVFM_TAB (*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_PWRCTL_DPE0_DVFM_TAB_OFFSET))
|
||||
#define rACC_DPE0_DVFM_TAB_EXT (*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_PWRCTL_DPE0_DVFM_TAB_EXT_OFFSET))
|
||||
|
||||
#define rPMGR_SECURITY (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + 0xD0000))
|
||||
|
||||
#define ACC_THRM0_CTL0_SET (ACC_BASE_ADDR + ACC_THERMAL_THRM0_CTL0_SET_OFFSET)
|
||||
#define ACC_THRM0_CTL0_CLR (ACC_BASE_ADDR + ACC_THERMAL_THRM0_CTL0_CLR_OFFSET)
|
||||
#define ACC_THRM0_CTL1 (ACC_BASE_ADDR + ACC_THERMAL_THRM0_CTL1_OFFSET)
|
||||
#define ACC_THRM0_PARAM (ACC_BASE_ADDR + ACC_THERMAL_THRM0_PARAM_OFFSET)
|
||||
#define ACC_THRM0_PIECE0 (ACC_BASE_ADDR + ACC_THERMAL_THRM0_PIECE0_OFFSET)
|
||||
#define ACC_THRM0_PIECE1 (ACC_BASE_ADDR + ACC_THERMAL_THRM0_PIECE1_OFFSET)
|
||||
#define ACC_THRM0_PIECE2 (ACC_BASE_ADDR + ACC_THERMAL_THRM0_PIECE2_OFFSET)
|
||||
|
||||
#define ACC_THRM1_CTL0_SET (ACC_BASE_ADDR + ACC_THERMAL_THRM1_CTL0_SET_OFFSET)
|
||||
#define ACC_THRM1_CTL0_CLR (ACC_BASE_ADDR + ACC_THERMAL_THRM1_CTL0_CLR_OFFSET)
|
||||
#define ACC_THRM1_CTL1 (ACC_BASE_ADDR + ACC_THERMAL_THRM1_CTL1_OFFSET)
|
||||
#define ACC_THRM1_PARAM (ACC_BASE_ADDR + ACC_THERMAL_THRM1_PARAM_OFFSET)
|
||||
#define ACC_THRM1_PIECE0 (ACC_BASE_ADDR + ACC_THERMAL_THRM1_PIECE0_OFFSET)
|
||||
#define ACC_THRM1_PIECE1 (ACC_BASE_ADDR + ACC_THERMAL_THRM1_PIECE1_OFFSET)
|
||||
#define ACC_THRM1_PIECE2 (ACC_BASE_ADDR + ACC_THERMAL_THRM1_PIECE2_OFFSET)
|
||||
|
||||
#define ACC_THRM2_CTL0_SET (ACC_BASE_ADDR + ACC_THERMAL_THRM2_CTL0_SET_OFFSET)
|
||||
#define ACC_THRM2_CTL0_CLR (ACC_BASE_ADDR + ACC_THERMAL_THRM2_CTL0_CLR_OFFSET)
|
||||
#define ACC_THRM2_CTL1 (ACC_BASE_ADDR + ACC_THERMAL_THRM2_CTL1_OFFSET)
|
||||
#define ACC_THRM2_PARAM (ACC_BASE_ADDR + ACC_THERMAL_THRM2_PARAM_OFFSET)
|
||||
#define ACC_THRM2_PIECE0 (ACC_BASE_ADDR + ACC_THERMAL_THRM2_PIECE0_OFFSET)
|
||||
#define ACC_THRM2_PIECE1 (ACC_BASE_ADDR + ACC_THERMAL_THRM2_PIECE1_OFFSET)
|
||||
#define ACC_THRM2_PIECE2 (ACC_BASE_ADDR + ACC_THERMAL_THRM2_PIECE2_OFFSET)
|
||||
|
||||
#define ACC_DVFM_FSHOT_IDX (ACC_BASE_ADDR + ACC_THERMAL_DVFM_FSHOT_IDX_OFFSET)
|
||||
|
||||
#define ACC_THRM0_PIECE0_MAKE(_c, _o, _s) (ACC_THERMAL_THRM0_PIECE0_START_CODE_INSRT(_c) | ACC_THERMAL_THRM0_PIECE0_OFFSET_INSRT(_o) | ACC_THERMAL_THRM0_PIECE0_SLOPE_INSRT(_s))
|
||||
#define ACC_THRM0_PIECE1_MAKE(_c, _o, _s) (ACC_THERMAL_THRM0_PIECE1_START_CODE_INSRT(_c) | ACC_THERMAL_THRM0_PIECE1_OFFSET_INSRT(_o) | ACC_THERMAL_THRM0_PIECE1_SLOPE_INSRT(_s))
|
||||
#define ACC_THRM0_PIECE2_MAKE(_c, _o, _s) (ACC_THERMAL_THRM0_PIECE2_START_CODE_INSRT(_c) | ACC_THERMAL_THRM0_PIECE2_OFFSET_INSRT(_o) | ACC_THERMAL_THRM0_PIECE2_SLOPE_INSRT(_s))
|
||||
#define ACC_THRM1_PIECE0_MAKE(_c, _o, _s) (ACC_THERMAL_THRM1_PIECE0_START_CODE_INSRT(_c) | ACC_THERMAL_THRM1_PIECE0_OFFSET_INSRT(_o) | ACC_THERMAL_THRM1_PIECE0_SLOPE_INSRT(_s))
|
||||
#define ACC_THRM1_PIECE1_MAKE(_c, _o, _s) (ACC_THERMAL_THRM1_PIECE1_START_CODE_INSRT(_c) | ACC_THERMAL_THRM1_PIECE1_OFFSET_INSRT(_o) | ACC_THERMAL_THRM1_PIECE1_SLOPE_INSRT(_s))
|
||||
#define ACC_THRM1_PIECE2_MAKE(_c, _o, _s) (ACC_THERMAL_THRM1_PIECE2_START_CODE_INSRT(_c) | ACC_THERMAL_THRM1_PIECE2_OFFSET_INSRT(_o) | ACC_THERMAL_THRM1_PIECE2_SLOPE_INSRT(_s))
|
||||
#define ACC_THRM2_PIECE0_MAKE(_c, _o, _s) (ACC_THERMAL_THRM2_PIECE0_START_CODE_INSRT(_c) | ACC_THERMAL_THRM2_PIECE0_OFFSET_INSRT(_o) | ACC_THERMAL_THRM2_PIECE0_SLOPE_INSRT(_s))
|
||||
#define ACC_THRM2_PIECE1_MAKE(_c, _o, _s) (ACC_THERMAL_THRM2_PIECE1_START_CODE_INSRT(_c) | ACC_THERMAL_THRM2_PIECE1_OFFSET_INSRT(_o) | ACC_THERMAL_THRM2_PIECE1_SLOPE_INSRT(_s))
|
||||
#define ACC_THRM2_PIECE2_MAKE(_c, _o, _s) (ACC_THERMAL_THRM2_PIECE2_START_CODE_INSRT(_c) | ACC_THERMAL_THRM2_PIECE2_OFFSET_INSRT(_o) | ACC_THERMAL_THRM2_PIECE2_SLOPE_INSRT(_s))
|
||||
|
||||
////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Externs
|
||||
//
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
extern void pmgr_update_device_tree(DTNode *pmgr_node);
|
||||
extern void pmgr_gfx_update_device_tree(DTNode *gfx_node);
|
||||
extern void pmgr_platform_config_uvwarn(void);
|
||||
|
||||
void pmgr_awake_to_aop_ddr_pre_sequence_insert(void);
|
||||
void pmgr_aop_ddr_to_awake_post_sequence_insert_pll(void);
|
||||
void pmgr_aop_ddr_to_awake_post_sequence_insert(void);
|
||||
void pmgr_s2r_aop_to_aop_ddr_post_sequence_insert_pwrgate(void);
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_PMGR_H */
|
||||
@@ -0,0 +1,90 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_RECONFIG_H
|
||||
#define __PLATFORM_RECONFIG_H
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <platform/memmap.h>
|
||||
|
||||
#define rAOP_GLOBAL(_p) (*(volatile uint32_t *)(AOP_BASE_ADDR + _p))
|
||||
#define rRECONFIG_RAM_BASE(base, count) *(volatile uint32_t *)((base) + (count*4))
|
||||
#define rRECONFIG_RAM_BASE_BYTE(base, count, count_bytes) *(volatile uint32_t *)((base) + (count*4) + (count_bytes))
|
||||
#define ALIGNMENT_MASK_1KB ~(0x3FF)
|
||||
#define RECONFIG_NUMBER_OF_REGS(regs) ((((regs) - 1) & 0xF) << 2)
|
||||
#define AOP_CFG_TABLE (AOP_RECONFIG_REGION_BASE_ADDR)
|
||||
#define AOP_CFG_TABLE_DIAGS (AOP_RECONFIG_REGION_DIAGS_BASE_ADDR)
|
||||
#define WRITE_OFFSETS(addr, values) (((addr) >> 2) & 0xFF) << (((values) % 4) * 8)
|
||||
#define MAX_WRITE_REGS 16
|
||||
|
||||
#define AOP_DDR_S2R_AOP_PRE_MAX_SIZE 0x200
|
||||
#define AOP_DDR_S2R_AOP_POST_MAX_SIZE 0x100
|
||||
#define S2R_AOP_AOP_DDR_PRE_MAX_SIZE 0x100
|
||||
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
#define S2R_AOP_AOP_DDR_POST_MAX_SIZE 0x4000
|
||||
#elif SUB_PLATFORM_S8001
|
||||
#define S2R_AOP_AOP_DDR_POST_MAX_SIZE 0x4b00
|
||||
#endif
|
||||
|
||||
#define AWAKE_AOP_DDR_PRE_MAX_SIZE 0x200
|
||||
#define AWAKE_AOP_DDR_POST_MAX_SIZE 0x600
|
||||
#define AOP_DDR_AWAKE_PRE_MAX_SIZE 0x800
|
||||
|
||||
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
||||
#define AOP_DDR_AWAKE_POST_MAX_SIZE 0x2a00
|
||||
#elif SUB_PLATFORM_S8001
|
||||
#define AOP_DDR_AWAKE_POST_MAX_SIZE 0x4000
|
||||
#endif
|
||||
|
||||
// SRAM sequences
|
||||
#define AOP_DDR_S2R_AOP_PRE_BASE_ADDR (AOP_RECONFIG_REGION_BASE_ADDR + 0x100)
|
||||
#define AOP_DDR_S2R_AOP_POST_BASE_ADDR (AOP_DDR_S2R_AOP_PRE_BASE_ADDR + AOP_DDR_S2R_AOP_PRE_MAX_SIZE)
|
||||
#define S2R_AOP_AOP_DDR_PRE_BASE_ADDR (AOP_DDR_S2R_AOP_POST_BASE_ADDR + AOP_DDR_S2R_AOP_POST_MAX_SIZE)
|
||||
#define S2R_AOP_AOP_DDR_POST_BASE_ADDR (S2R_AOP_AOP_DDR_PRE_BASE_ADDR + S2R_AOP_AOP_DDR_PRE_MAX_SIZE)
|
||||
|
||||
#define AOP_RECONFIG_REGION_USED (S2R_AOP_AOP_DDR_POST_BASE_ADDR + S2R_AOP_AOP_DDR_POST_MAX_SIZE - AOP_RECONFIG_REGION_BASE_ADDR)
|
||||
|
||||
#if AOP_RECONFIG_REGION_USED > AOP_RECONFIG_REGION_SIZE
|
||||
#error "Reconfig engine programs overflow their SRAM allocation
|
||||
#endif
|
||||
|
||||
// DRAM sequences
|
||||
#define AWAKE_AOP_DDR_PRE_BASE_ADDR (DRAM_CONFIG_SEQ_BASE)
|
||||
#define AWAKE_AOP_DDR_POST_BASE_ADDR (AWAKE_AOP_DDR_PRE_BASE_ADDR + AWAKE_AOP_DDR_PRE_MAX_SIZE)
|
||||
#define AOP_DDR_AWAKE_PRE_BASE_ADDR (AWAKE_AOP_DDR_POST_BASE_ADDR + AWAKE_AOP_DDR_POST_MAX_SIZE)
|
||||
#define AOP_DDR_AWAKE_POST_BASE_ADDR (AOP_DDR_AWAKE_PRE_BASE_ADDR + AOP_DDR_AWAKE_PRE_MAX_SIZE)
|
||||
|
||||
#define DRAM_CONFIG_SEQ_USED (AOP_DDR_AWAKE_POST_BASE_ADDR + AOP_DDR_AWAKE_POST_MAX_SIZE - DRAM_CONFIG_SEQ_BASE)
|
||||
|
||||
#if DRAM_CONFIG_SEQ_USED > DRAM_CONFIG_SEQ_SIZE
|
||||
#error "Reconfig engine programs overflow their DRAM allocation
|
||||
#endif
|
||||
|
||||
// For diags, all sequences go in SRAM
|
||||
|
||||
#define AOP_DDR_S2R_AOP_PRE_DIAGS_BASE_ADDR (AOP_RECONFIG_REGION_DIAGS_BASE_ADDR + 0x100)
|
||||
#define AOP_DDR_S2R_AOP_POST_DIAGS_BASE_ADDR (AOP_DDR_S2R_AOP_PRE_DIAGS_BASE_ADDR + AOP_DDR_S2R_AOP_PRE_MAX_SIZE)
|
||||
#define S2R_AOP_AOP_DDR_PRE_DIAGS_BASE_ADDR (AOP_DDR_S2R_AOP_POST_DIAGS_BASE_ADDR + AOP_DDR_S2R_AOP_POST_MAX_SIZE)
|
||||
#define S2R_AOP_AOP_DDR_POST_DIAGS_BASE_ADDR (S2R_AOP_AOP_DDR_PRE_DIAGS_BASE_ADDR + S2R_AOP_AOP_DDR_PRE_MAX_SIZE)
|
||||
|
||||
#define AWAKE_AOP_DDR_PRE_DIAGS_BASE_ADDR (S2R_AOP_AOP_DDR_POST_DIAGS_BASE_ADDR + S2R_AOP_AOP_DDR_POST_MAX_SIZE)
|
||||
#define AWAKE_AOP_DDR_POST_DIAGS_BASE_ADDR (AWAKE_AOP_DDR_PRE_DIAGS_BASE_ADDR + AWAKE_AOP_DDR_PRE_MAX_SIZE)
|
||||
#define AOP_DDR_AWAKE_PRE_DIAGS_BASE_ADDR (AWAKE_AOP_DDR_POST_DIAGS_BASE_ADDR + AWAKE_AOP_DDR_POST_MAX_SIZE)
|
||||
#define AOP_DDR_AWAKE_POST_DIAGS_BASE_ADDR (AOP_DDR_AWAKE_PRE_DIAGS_BASE_ADDR + AOP_DDR_AWAKE_PRE_MAX_SIZE)
|
||||
|
||||
#define AOP_RECONFIG_REGION_DIAGS_USED (AOP_DDR_AWAKE_POST_DIAGS_BASE_ADDR + AOP_DDR_AWAKE_POST_MAX_SIZE - AOP_RECONFIG_REGION_DIAGS_BASE_ADDR)
|
||||
|
||||
#if AOP_RECONFIG_REGION_DIAGS_USED > AOP_RECONFIG_REGION_DIAGS_SIZE
|
||||
#error "Reconfig engine programs overflow their SRAM allocation
|
||||
#endif
|
||||
|
||||
#endif /* __PLATFORM_RECONFIG_H */
|
||||
File diff suppressed because it is too large.
Load diff
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Load diff
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Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_TUNABLE_APCIE_COMMON_H
|
||||
#define SPDS_S8000_TUNABLE_APCIE_COMMON_H
|
||||
|
||||
#include <platform/soc/s8000/b0/tunable/apcie_common.h>
|
||||
#include <platform/soc/s8000/c0/tunable/apcie_common.h>
|
||||
|
||||
#endif /* SPDS_S8000_TUNABLE_APCIE_COMMON_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_TUNABLE_APCIE_CONFIG_H
|
||||
#define SPDS_S8000_TUNABLE_APCIE_CONFIG_H
|
||||
|
||||
#include <platform/soc/s8000/b0/tunable/apcie_config.h>
|
||||
#include <platform/soc/s8000/c0/tunable/apcie_config.h>
|
||||
|
||||
#endif /* SPDS_S8000_TUNABLE_APCIE_CONFIG_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_TUNABLE_AUSR_CFG_H
|
||||
#define SPDS_S8000_TUNABLE_AUSR_CFG_H
|
||||
|
||||
#include <platform/soc/s8000/b0/tunable/ausr_cfg.h>
|
||||
#include <platform/soc/s8000/c0/tunable/ausr_cfg.h>
|
||||
|
||||
#endif /* SPDS_S8000_TUNABLE_AUSR_CFG_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_TUNABLE_AUSR_SHM_CFG_H
|
||||
#define SPDS_S8000_TUNABLE_AUSR_SHM_CFG_H
|
||||
|
||||
#include <platform/soc/s8000/b0/tunable/ausr_shm_cfg.h>
|
||||
#include <platform/soc/s8000/c0/tunable/ausr_shm_cfg.h>
|
||||
|
||||
#endif /* SPDS_S8000_TUNABLE_AUSR_SHM_CFG_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/*!
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_TUNABLE_AUST_SHM_CFG_H
|
||||
#define SPDS_TUNABLE_AUST_SHM_CFG_H
|
||||
|
||||
#include <platform/soc/s8000/b0/tunable/aust_shm_cfg.h>
|
||||
#include <platform/soc/s8000/c0/tunable/aust_shm_cfg.h>
|
||||
|
||||
#endif /*! SPDS_TUNABLE_AUST_SHM_CFG_H */
|
||||
@@ -0,0 +1,179 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_B0_TUNABLE_APCIE_COMMON_H
|
||||
#define SPDS_S8000_B0_TUNABLE_APCIE_COMMON_H
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_FABRIC_TLIMITS_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x7f7f7f7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_FABRIC_TLIMITS_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_LLT_RATE_LIMITER_CTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_LLT_RATE_LIMITER_CTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_COMMON_PRIORITY_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x700)
|
||||
#define PCIE_APCIE_COMMON_BLK_COMMON_PRIORITY_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NANDSYSCLK_TIMING_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xffffff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NANDSYSCLK_TIMING_DEFAULT_TUNABLE_VALUE_S8000_B0 (0xc0800)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NAND_LTR_THRESH_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1fff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NAND_LTR_THRESH_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x92c)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PHY_POWERUP_CTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xffffffff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PHY_POWERUP_CTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x2001000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_REFCLKBUF_TIMING_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_REFCLKBUF_TIMING_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x9)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x31100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1000010)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_FPGA_TUNABLE_UMASK_S8000_B0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_FPGA_TUNABLE_VALUE_S8000_B0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NVME_CTRL_0_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x11)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NVME_CTRL_0_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_PRIORITY_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x7)
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_PRIORITY_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_0_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x333003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_0_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x111000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_0_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_0_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_0_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_0_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_0_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_0_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x31100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1000000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_FPGA_TUNABLE_UMASK_S8000_B0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_FPGA_TUNABLE_VALUE_S8000_B0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_1_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x333003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_1_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x111000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_1_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_1_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_1_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_1_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_1_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_1_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_1_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_1_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x31100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1000000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_FPGA_TUNABLE_UMASK_S8000_B0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_FPGA_TUNABLE_VALUE_S8000_B0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_2_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x333003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_2_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x111000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_2_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_2_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_2_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_2_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_2_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_2_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_2_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_2_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x31100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1000000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_FPGA_TUNABLE_UMASK_S8000_B0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_FPGA_TUNABLE_VALUE_S8000_B0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_3_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x333003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_3_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x111000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_3_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_3_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_3_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_3_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_3_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_3_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_3_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_3_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_COMMON_BLK_FABRIC_TLIMITS */ 0x8, sizeof(uint32_t), 0x7f7f7f7f, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_LLT_RATE_LIMITER_CTRL */ 0xc, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_COMMON_PRIORITY */ 0x10, sizeof(uint32_t), 0x700, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NANDSYSCLK_TIMING */ 0x18, sizeof(uint32_t), 0xffffff, 0xc0800 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NAND_LTR_THRESH */ 0x1c, sizeof(uint32_t), 0x1fff, 0x92c }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PHY_POWERUP_CTRL */ 0x28, sizeof(uint32_t), 0xffffffff, 0x2001000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_REFCLKBUF_TIMING */ 0x30, sizeof(uint32_t), 0xff, 0x9 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_0 */ 0x100, sizeof(uint32_t), 0x31100010, 0x1000010 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NVME_CTRL_0 */ 0x104, sizeof(uint32_t), 0x11, 0x1 }, \
|
||||
{ /* APCIE_COMMON_BLK_NVME_PRIORITY */ 0x108, sizeof(uint32_t), 0x7, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_0 */ 0x10c, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_0 */ 0x110, sizeof(uint32_t), 0x333003f, 0x111000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_0 */ 0x120, sizeof(uint32_t), 0xff, 0x40 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_0 */ 0x128, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_0 */ 0x130, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_0 */ 0x134, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_1 */ 0x180, sizeof(uint32_t), 0x31100010, 0x1000000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_1 */ 0x190, sizeof(uint32_t), 0x333003f, 0x111000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_1 */ 0x1a0, sizeof(uint32_t), 0xff, 0x40 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_1 */ 0x1a8, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_1 */ 0x1b0, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_1 */ 0x1b4, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_2 */ 0x200, sizeof(uint32_t), 0x31100010, 0x1000000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_2 */ 0x210, sizeof(uint32_t), 0x333003f, 0x111000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_2 */ 0x220, sizeof(uint32_t), 0xff, 0x40 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_2 */ 0x228, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_2 */ 0x230, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_2 */ 0x234, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_3 */ 0x280, sizeof(uint32_t), 0x31100010, 0x1000000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_3 */ 0x290, sizeof(uint32_t), 0x333003f, 0x111000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_3 */ 0x2a0, sizeof(uint32_t), 0xff, 0x40 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_3 */ 0x2a8, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_3 */ 0x2b0, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_3 */ 0x2b4, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_COMMON_FPGA_TUNABLES_S8000_B0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_0 */ 0x100, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_1 */ 0x180, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_2 */ 0x200, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_3 */ 0x280, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8000_B0_TUNABLE_APCIE_COMMON_H */
|
||||
@@ -0,0 +1,133 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_B0_TUNABLE_APCIE_CONFIG_H
|
||||
#define SPDS_S8000_B0_TUNABLE_APCIE_CONFIG_H
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xff)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x5)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x3)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xff)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x5)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x3)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xff)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x5)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x3)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xff)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x5)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x3)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8000_B0_TUNABLE_APCIE_CONFIG_H */
|
||||
@@ -0,0 +1,122 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_B0_TUNABLE_AUSR_CFG_H
|
||||
#define SPDS_S8000_B0_TUNABLE_AUSR_CFG_H
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xfc)
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_VALUE_S8000_B0 (0xa0)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xf000)
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x5000)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x7eff)
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x18)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xc0)
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_CFG_BLK_CFG1W_CDR */ 0x24, sizeof(uint32_t), 0xfc, 0xa0 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG5W_CDR */ 0x34, sizeof(uint32_t), 0xf000, 0x5000 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG_COM */ 0x40, sizeof(uint32_t), 0x7eff, 0x18 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG6W_CDR */ 0x44, sizeof(uint32_t), 0xc0, 0x40 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xfc)
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_VALUE_S8000_B0 (0xa0)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xf000)
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x5000)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x7eff)
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x18)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xc0)
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_CFG_BLK_CFG1W_CDR */ 0x24, sizeof(uint32_t), 0xfc, 0xa0 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG5W_CDR */ 0x34, sizeof(uint32_t), 0xf000, 0x5000 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG_COM */ 0x40, sizeof(uint32_t), 0x7eff, 0x18 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG6W_CDR */ 0x44, sizeof(uint32_t), 0xc0, 0x40 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xfc)
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_VALUE_S8000_B0 (0xa0)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xf000)
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x5000)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x7eff)
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x18)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xc0)
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_CFG_BLK_CFG1W_CDR */ 0x24, sizeof(uint32_t), 0xfc, 0xa0 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG5W_CDR */ 0x34, sizeof(uint32_t), 0xf000, 0x5000 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG_COM */ 0x40, sizeof(uint32_t), 0x7eff, 0x18 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG6W_CDR */ 0x44, sizeof(uint32_t), 0xc0, 0x40 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xfc)
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_VALUE_S8000_B0 (0xa0)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xf000)
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x5000)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x7eff)
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x18)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xc0)
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_CFG_BLK_CFG1W_CDR */ 0x24, sizeof(uint32_t), 0xfc, 0xa0 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG5W_CDR */ 0x34, sizeof(uint32_t), 0xf000, 0x5000 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG_COM */ 0x40, sizeof(uint32_t), 0x7eff, 0x18 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG6W_CDR */ 0x44, sizeof(uint32_t), 0xc0, 0x40 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xfc)
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_VALUE_S8000_B0 (0xa0)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xf000)
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x5000)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x7eff)
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x18)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xc0)
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_CFG_BLK_CFG1W_CDR */ 0x24, sizeof(uint32_t), 0xfc, 0xa0 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG5W_CDR */ 0x34, sizeof(uint32_t), 0xf000, 0x5000 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG_COM */ 0x40, sizeof(uint32_t), 0x7eff, 0x18 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG6W_CDR */ 0x44, sizeof(uint32_t), 0xc0, 0x40 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8000_B0_TUNABLE_AUSR_CFG_H */
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_B0_TUNABLE_AUSR_SHM_CFG_H
|
||||
#define SPDS_S8000_B0_TUNABLE_AUSR_SHM_CFG_H
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR0_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1ef)
|
||||
#define PCIE_APCIE_PHY_AUSR0_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_VALUE_S8000_B0 (0xe7)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR0_SHM_CFG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_SHM_CFG_BLK_RXA_CFG2 */ 0x50, sizeof(uint32_t), 0x1ef, 0xe7 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR1_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1ef)
|
||||
#define PCIE_APCIE_PHY_AUSR1_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_VALUE_S8000_B0 (0xe7)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR1_SHM_CFG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_SHM_CFG_BLK_RXA_CFG2 */ 0x50, sizeof(uint32_t), 0x1ef, 0xe7 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR2_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1ef)
|
||||
#define PCIE_APCIE_PHY_AUSR2_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_VALUE_S8000_B0 (0xe7)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR2_SHM_CFG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_SHM_CFG_BLK_RXA_CFG2 */ 0x50, sizeof(uint32_t), 0x1ef, 0xe7 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR3_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1ef)
|
||||
#define PCIE_APCIE_PHY_AUSR3_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_VALUE_S8000_B0 (0xe7)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR3_SHM_CFG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_SHM_CFG_BLK_RXA_CFG2 */ 0x50, sizeof(uint32_t), 0x1ef, 0xe7 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR4_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1ef)
|
||||
#define PCIE_APCIE_PHY_AUSR4_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_VALUE_S8000_B0 (0xe7)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR4_SHM_CFG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_SHM_CFG_BLK_RXA_CFG2 */ 0x50, sizeof(uint32_t), 0x1ef, 0xe7 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8000_B0_TUNABLE_AUSR_SHM_CFG_H */
|
||||
@@ -0,0 +1,82 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_B0_TUNABLE_AUST_SHM_CFG_H
|
||||
#define SPDS_S8000_B0_TUNABLE_AUST_SHM_CFG_H
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST0_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST0_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST0_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST0_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST0_SHM_CFG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG6_TXA */ 0x18, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG7_TXA */ 0x1c, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST1_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST1_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST1_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST1_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST1_SHM_CFG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG6_TXA */ 0x18, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG7_TXA */ 0x1c, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST2_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST2_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST2_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST2_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST2_SHM_CFG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG6_TXA */ 0x18, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG7_TXA */ 0x1c, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST3_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST3_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST3_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST3_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST3_SHM_CFG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG6_TXA */ 0x18, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG7_TXA */ 0x1c, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST4_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST4_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST4_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST4_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST4_SHM_CFG_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG6_TXA */ 0x18, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG7_TXA */ 0x1c, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8000_B0_TUNABLE_AUST_SHM_CFG_H */
|
||||
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_B0_TUNABLE_X1_PCIE_RC_H
|
||||
#define SPDS_S8000_B0_TUNABLE_X1_PCIE_RC_H
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X1_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X1_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8000_B0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1900)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X1_PCIE_RC_X1_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X1_PCIE_RC_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x154, sizeof(uint32_t), 0xf8ff00, 0x1900 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_FPGA_TUNABLES_S8000_B0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X1_PCIE_RC_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x154, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X1_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X1_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8000_B0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1900)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X1_PCIE_RC_X1_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X1_PCIE_RC_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x154, sizeof(uint32_t), 0xf8ff00, 0x1900 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_FPGA_TUNABLES_S8000_B0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X1_PCIE_RC_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x154, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8000_B0_TUNABLE_X1_PCIE_RC_H */
|
||||
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_B0_TUNABLE_X2_PCIE_RC_H
|
||||
#define SPDS_S8000_B0_TUNABLE_X2_PCIE_RC_H
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8000_B0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1900)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x154, sizeof(uint32_t), 0xf8ff00, 0x1900 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_FPGA_TUNABLES_S8000_B0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x154, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8000_B0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8000_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8000_B0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8000_B0 (0x1900)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_DEFAULT_TUNABLES_S8000_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x154, sizeof(uint32_t), 0xf8ff00, 0x1900 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_FPGA_TUNABLES_S8000_B0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x154, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8000_B0_TUNABLE_X2_PCIE_RC_H */
|
||||
@@ -0,0 +1,179 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_C0_TUNABLE_APCIE_COMMON_H
|
||||
#define SPDS_S8000_C0_TUNABLE_APCIE_COMMON_H
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_FABRIC_TLIMITS_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x7f7f7f7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_FABRIC_TLIMITS_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_LLT_RATE_LIMITER_CTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_LLT_RATE_LIMITER_CTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_COMMON_PRIORITY_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x700)
|
||||
#define PCIE_APCIE_COMMON_BLK_COMMON_PRIORITY_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NANDSYSCLK_TIMING_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xffffff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NANDSYSCLK_TIMING_DEFAULT_TUNABLE_VALUE_S8000_C0 (0xc0800)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NAND_LTR_THRESH_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1fff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NAND_LTR_THRESH_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x92c)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PHY_POWERUP_CTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xffffffff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PHY_POWERUP_CTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x2001000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_REFCLKBUF_TIMING_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_REFCLKBUF_TIMING_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x9)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x31100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1000010)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_FPGA_TUNABLE_UMASK_S8000_C0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_FPGA_TUNABLE_VALUE_S8000_C0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NVME_CTRL_0_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x11)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NVME_CTRL_0_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_PRIORITY_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x7)
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_PRIORITY_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_0_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x333003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_0_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x111000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_0_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_0_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_0_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_0_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_0_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_0_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x31100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1000000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_FPGA_TUNABLE_UMASK_S8000_C0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_FPGA_TUNABLE_VALUE_S8000_C0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_1_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x333003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_1_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x111000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_1_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_1_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_1_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_1_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_1_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_1_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_1_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_1_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x31100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1000000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_FPGA_TUNABLE_UMASK_S8000_C0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_FPGA_TUNABLE_VALUE_S8000_C0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_2_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x333003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_2_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x111000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_2_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_2_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_2_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_2_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_2_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_2_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_2_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_2_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x31100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1000000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_FPGA_TUNABLE_UMASK_S8000_C0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_FPGA_TUNABLE_VALUE_S8000_C0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_3_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x333003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_3_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x111000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_3_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_3_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_3_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_3_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_3_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_3_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_3_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_3_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_COMMON_BLK_FABRIC_TLIMITS */ 0x8, sizeof(uint32_t), 0x7f7f7f7f, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_LLT_RATE_LIMITER_CTRL */ 0xc, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_COMMON_PRIORITY */ 0x10, sizeof(uint32_t), 0x700, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NANDSYSCLK_TIMING */ 0x18, sizeof(uint32_t), 0xffffff, 0xc0800 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NAND_LTR_THRESH */ 0x1c, sizeof(uint32_t), 0x1fff, 0x92c }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PHY_POWERUP_CTRL */ 0x28, sizeof(uint32_t), 0xffffffff, 0x2001000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_REFCLKBUF_TIMING */ 0x30, sizeof(uint32_t), 0xff, 0x9 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_0 */ 0x100, sizeof(uint32_t), 0x31100010, 0x1000010 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NVME_CTRL_0 */ 0x104, sizeof(uint32_t), 0x11, 0x1 }, \
|
||||
{ /* APCIE_COMMON_BLK_NVME_PRIORITY */ 0x108, sizeof(uint32_t), 0x7, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_0 */ 0x10c, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_0 */ 0x110, sizeof(uint32_t), 0x333003f, 0x111000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_0 */ 0x120, sizeof(uint32_t), 0xff, 0x40 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_0 */ 0x128, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_0 */ 0x130, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_0 */ 0x134, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_1 */ 0x180, sizeof(uint32_t), 0x31100010, 0x1000000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_1 */ 0x190, sizeof(uint32_t), 0x333003f, 0x111000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_1 */ 0x1a0, sizeof(uint32_t), 0xff, 0x40 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_1 */ 0x1a8, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_1 */ 0x1b0, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_1 */ 0x1b4, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_2 */ 0x200, sizeof(uint32_t), 0x31100010, 0x1000000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_2 */ 0x210, sizeof(uint32_t), 0x333003f, 0x111000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_2 */ 0x220, sizeof(uint32_t), 0xff, 0x40 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_2 */ 0x228, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_2 */ 0x230, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_2 */ 0x234, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_3 */ 0x280, sizeof(uint32_t), 0x31100010, 0x1000000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_3 */ 0x290, sizeof(uint32_t), 0x333003f, 0x111000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_3 */ 0x2a0, sizeof(uint32_t), 0xff, 0x40 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_3 */ 0x2a8, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_3 */ 0x2b0, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_3 */ 0x2b4, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_COMMON_FPGA_TUNABLES_S8000_C0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_0 */ 0x100, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_1 */ 0x180, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_2 */ 0x200, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_3 */ 0x280, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8000_C0_TUNABLE_APCIE_COMMON_H */
|
||||
@@ -0,0 +1,133 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_C0_TUNABLE_APCIE_CONFIG_H
|
||||
#define SPDS_S8000_C0_TUNABLE_APCIE_CONFIG_H
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xff)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x5)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x3)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xff)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x5)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x3)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xff)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x5)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x3)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xff)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x5)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x3)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8000_C0_TUNABLE_APCIE_CONFIG_H */
|
||||
@@ -0,0 +1,122 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_C0_TUNABLE_AUSR_CFG_H
|
||||
#define SPDS_S8000_C0_TUNABLE_AUSR_CFG_H
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xfc)
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0xa0)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf000)
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x5000)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x7eff)
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x18)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xc0)
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR0_CFG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_CFG_BLK_CFG1W_CDR */ 0x24, sizeof(uint32_t), 0xfc, 0xa0 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG5W_CDR */ 0x34, sizeof(uint32_t), 0xf000, 0x5000 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG_COM */ 0x40, sizeof(uint32_t), 0x7eff, 0x18 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG6W_CDR */ 0x44, sizeof(uint32_t), 0xc0, 0x40 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xfc)
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0xa0)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf000)
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x5000)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x7eff)
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x18)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xc0)
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR1_CFG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_CFG_BLK_CFG1W_CDR */ 0x24, sizeof(uint32_t), 0xfc, 0xa0 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG5W_CDR */ 0x34, sizeof(uint32_t), 0xf000, 0x5000 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG_COM */ 0x40, sizeof(uint32_t), 0x7eff, 0x18 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG6W_CDR */ 0x44, sizeof(uint32_t), 0xc0, 0x40 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xfc)
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0xa0)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf000)
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x5000)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x7eff)
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x18)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xc0)
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR2_CFG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_CFG_BLK_CFG1W_CDR */ 0x24, sizeof(uint32_t), 0xfc, 0xa0 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG5W_CDR */ 0x34, sizeof(uint32_t), 0xf000, 0x5000 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG_COM */ 0x40, sizeof(uint32_t), 0x7eff, 0x18 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG6W_CDR */ 0x44, sizeof(uint32_t), 0xc0, 0x40 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xfc)
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0xa0)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf000)
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x5000)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x7eff)
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x18)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xc0)
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR3_CFG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_CFG_BLK_CFG1W_CDR */ 0x24, sizeof(uint32_t), 0xfc, 0xa0 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG5W_CDR */ 0x34, sizeof(uint32_t), 0xf000, 0x5000 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG_COM */ 0x40, sizeof(uint32_t), 0x7eff, 0x18 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG6W_CDR */ 0x44, sizeof(uint32_t), 0xc0, 0x40 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xfc)
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0xa0)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf000)
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x5000)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x7eff)
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x18)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xc0)
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x40)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR4_CFG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_CFG_BLK_CFG1W_CDR */ 0x24, sizeof(uint32_t), 0xfc, 0xa0 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG5W_CDR */ 0x34, sizeof(uint32_t), 0xf000, 0x5000 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG_COM */ 0x40, sizeof(uint32_t), 0x7eff, 0x18 }, \
|
||||
{ /* AUSR_CFG_BLK_CFG6W_CDR */ 0x44, sizeof(uint32_t), 0xc0, 0x40 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8000_C0_TUNABLE_AUSR_CFG_H */
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_C0_TUNABLE_AUSR_SHM_CFG_H
|
||||
#define SPDS_S8000_C0_TUNABLE_AUSR_SHM_CFG_H
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR0_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1ef)
|
||||
#define PCIE_APCIE_PHY_AUSR0_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_VALUE_S8000_C0 (0xe7)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR0_SHM_CFG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_SHM_CFG_BLK_RXA_CFG2 */ 0x50, sizeof(uint32_t), 0x1ef, 0xe7 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR1_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1ef)
|
||||
#define PCIE_APCIE_PHY_AUSR1_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_VALUE_S8000_C0 (0xe7)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR1_SHM_CFG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_SHM_CFG_BLK_RXA_CFG2 */ 0x50, sizeof(uint32_t), 0x1ef, 0xe7 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR2_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1ef)
|
||||
#define PCIE_APCIE_PHY_AUSR2_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_VALUE_S8000_C0 (0xe7)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR2_SHM_CFG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_SHM_CFG_BLK_RXA_CFG2 */ 0x50, sizeof(uint32_t), 0x1ef, 0xe7 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR3_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1ef)
|
||||
#define PCIE_APCIE_PHY_AUSR3_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_VALUE_S8000_C0 (0xe7)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR3_SHM_CFG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_SHM_CFG_BLK_RXA_CFG2 */ 0x50, sizeof(uint32_t), 0x1ef, 0xe7 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR4_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1ef)
|
||||
#define PCIE_APCIE_PHY_AUSR4_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_VALUE_S8000_C0 (0xe7)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUSR4_SHM_CFG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUSR_SHM_CFG_BLK_RXA_CFG2 */ 0x50, sizeof(uint32_t), 0x1ef, 0xe7 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8000_C0_TUNABLE_AUSR_SHM_CFG_H */
|
||||
@@ -0,0 +1,82 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_C0_TUNABLE_AUST_SHM_CFG_H
|
||||
#define SPDS_S8000_C0_TUNABLE_AUST_SHM_CFG_H
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST0_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST0_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST0_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST0_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST0_SHM_CFG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG6_TXA */ 0x18, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG7_TXA */ 0x1c, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST1_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST1_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST1_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST1_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST1_SHM_CFG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG6_TXA */ 0x18, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG7_TXA */ 0x1c, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST2_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST2_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST2_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST2_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST2_SHM_CFG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG6_TXA */ 0x18, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG7_TXA */ 0x1c, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST3_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST3_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST3_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST3_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST3_SHM_CFG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG6_TXA */ 0x18, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG7_TXA */ 0x1c, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST4_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST4_SHM_CFG_BLK_CFG6_TXA_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST4_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_UMASK_S8000_C0 (0x1800)
|
||||
#define PCIE_APCIE_PHY_AUST4_SHM_CFG_BLK_CFG7_TXA_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1800)
|
||||
|
||||
#define PCIE_APCIE_PHY_AUST4_SHM_CFG_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG6_TXA */ 0x18, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ /* AUST_SHM_CFG_BLK_CFG7_TXA */ 0x1c, sizeof(uint32_t), 0x1800, 0x1800 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8000_C0_TUNABLE_AUST_SHM_CFG_H */
|
||||
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_C0_TUNABLE_X1_PCIE_RC_H
|
||||
#define SPDS_S8000_C0_TUNABLE_X1_PCIE_RC_H
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X1_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X1_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8000_C0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1900)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X1_PCIE_RC_X1_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X1_PCIE_RC_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x154, sizeof(uint32_t), 0xf8ff00, 0x1900 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_FPGA_TUNABLES_S8000_C0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X1_PCIE_RC_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x154, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X1_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X1_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8000_C0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1900)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X1_PCIE_RC_X1_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X1_PCIE_RC_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x154, sizeof(uint32_t), 0xf8ff00, 0x1900 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_FPGA_TUNABLES_S8000_C0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X1_PCIE_RC_X1_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x154, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8000_C0_TUNABLE_X1_PCIE_RC_H */
|
||||
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_C0_TUNABLE_X2_PCIE_RC_H
|
||||
#define SPDS_S8000_C0_TUNABLE_X2_PCIE_RC_H
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8000_C0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1900)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x154, sizeof(uint32_t), 0xf8ff00, 0x1900 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_FPGA_TUNABLES_S8000_C0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x154, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8000_C0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8000_C0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x1900)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_DEFAULT_TUNABLES_S8000_C0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x154, sizeof(uint32_t), 0xf8ff00, 0x1900 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_FPGA_TUNABLES_S8000_C0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x154, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8000_C0_TUNABLE_X2_PCIE_RC_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_TUNABLE_X1_PCIE_RC_H
|
||||
#define SPDS_S8000_TUNABLE_X1_PCIE_RC_H
|
||||
|
||||
#include <platform/soc/s8000/b0/tunable/x1_pcie_rc.h>
|
||||
#include <platform/soc/s8000/c0/tunable/x1_pcie_rc.h>
|
||||
|
||||
#endif /* SPDS_S8000_TUNABLE_X1_PCIE_RC_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8000_TUNABLE_X2_PCIE_RC_H
|
||||
#define SPDS_S8000_TUNABLE_X2_PCIE_RC_H
|
||||
|
||||
#include <platform/soc/s8000/b0/tunable/x2_pcie_rc.h>
|
||||
#include <platform/soc/s8000/c0/tunable/x2_pcie_rc.h>
|
||||
|
||||
#endif /* SPDS_S8000_TUNABLE_X2_PCIE_RC_H */
|
||||
@@ -0,0 +1,276 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8001_A0_TUNABLE_APCIE_COMMON_H
|
||||
#define SPDS_S8001_A0_TUNABLE_APCIE_COMMON_H
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_FABRIC_TLIMITS_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x7f7f7f7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_FABRIC_TLIMITS_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_LLT_RATE_LIMITER_CTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_LLT_RATE_LIMITER_CTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_COMMON_PRIORITY_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x700)
|
||||
#define PCIE_APCIE_COMMON_BLK_COMMON_PRIORITY_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NANDSYSCLK_TIMING_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xffffff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NANDSYSCLK_TIMING_DEFAULT_TUNABLE_VALUE_S8001_A0 (0xc0800)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NAND_LTR_THRESH_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x1fff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NAND_LTR_THRESH_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x92c)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PHY_POWERUP_CTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xffffffff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PHY_POWERUP_CTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_REFCLKBUF_TIMING_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_REFCLKBUF_TIMING_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x9)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_NVME_TUNABLE_UMASK_S8001_A0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_NVME_TUNABLE_VALUE_S8001_A0 (0x10)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x30100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_FPGA_TUNABLE_UMASK_S8001_A0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_FPGA_TUNABLE_VALUE_S8001_A0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NVME_CTRL_0_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x11)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NVME_CTRL_0_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_PRIORITY_0_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x7)
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_PRIORITY_0_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_0_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x3003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_0_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x1000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_0_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_0_DEFAULT_TUNABLE_VALUE_S8001_A0 (0xf)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_0_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_0_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_0_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_0_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_NVME_TUNABLE_UMASK_S8001_A0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_NVME_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x30100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_FPGA_TUNABLE_UMASK_S8001_A0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_FPGA_TUNABLE_VALUE_S8001_A0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_1_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x3003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_1_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x1000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_1_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_1_DEFAULT_TUNABLE_VALUE_S8001_A0 (0xf)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_1_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_1_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_1_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_1_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_1_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_1_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_NVME_TUNABLE_UMASK_S8001_A0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_NVME_TUNABLE_VALUE_S8001_A0 (0x10)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x30100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_FPGA_TUNABLE_UMASK_S8001_A0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_FPGA_TUNABLE_VALUE_S8001_A0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NVME_CTRL_2_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x11)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NVME_CTRL_2_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_PRIORITY_2_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x7)
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_PRIORITY_2_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_2_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_2_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_2_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x3003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_2_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x1000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_2_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_2_DEFAULT_TUNABLE_VALUE_S8001_A0 (0xf)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_2_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_2_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_2_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_2_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_2_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_2_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_NVME_TUNABLE_UMASK_S8001_A0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_NVME_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x30100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_FPGA_TUNABLE_UMASK_S8001_A0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_FPGA_TUNABLE_VALUE_S8001_A0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_3_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x3003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_3_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x1000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_3_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_3_DEFAULT_TUNABLE_VALUE_S8001_A0 (0xf)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_3_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_3_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_3_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_3_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_3_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_3_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_4_NVME_TUNABLE_UMASK_S8001_A0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_4_NVME_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_4_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x30100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_4_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_4_FPGA_TUNABLE_UMASK_S8001_A0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_4_FPGA_TUNABLE_VALUE_S8001_A0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_4_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x3003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_4_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x1000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_4_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_4_DEFAULT_TUNABLE_VALUE_S8001_A0 (0xf)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_4_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_4_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_4_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_4_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_4_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_4_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_5_NVME_TUNABLE_UMASK_S8001_A0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_5_NVME_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_5_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x30100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_5_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_5_FPGA_TUNABLE_UMASK_S8001_A0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_5_FPGA_TUNABLE_VALUE_S8001_A0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_5_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x3003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_5_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x1000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_5_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_5_DEFAULT_TUNABLE_VALUE_S8001_A0 (0xf)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_5_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_5_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_5_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_5_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_5_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_5_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_DEFAULT_TUNABLES_S8001_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_COMMON_BLK_FABRIC_TLIMITS */ 0x8, sizeof(uint32_t), 0x7f7f7f7f, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_LLT_RATE_LIMITER_CTRL */ 0xc, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_COMMON_PRIORITY */ 0x10, sizeof(uint32_t), 0x700, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NANDSYSCLK_TIMING */ 0x18, sizeof(uint32_t), 0xffffff, 0xc0800 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NAND_LTR_THRESH */ 0x1c, sizeof(uint32_t), 0x1fff, 0x92c }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PHY_POWERUP_CTRL */ 0x24, sizeof(uint32_t), 0xffffffff, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_REFCLKBUF_TIMING */ 0x2c, sizeof(uint32_t), 0xff, 0x9 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_0 */ 0x100, sizeof(uint32_t), 0x30100010, 0x10 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NVME_CTRL_0 */ 0x108, sizeof(uint32_t), 0x11, 0x1 }, \
|
||||
{ /* APCIE_COMMON_BLK_NVME_PRIORITY_0 */ 0x10c, sizeof(uint32_t), 0x7, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_0 */ 0x110, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_0 */ 0x120, sizeof(uint32_t), 0x3003f, 0x1000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_0 */ 0x130, sizeof(uint32_t), 0xff, 0xf }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_0 */ 0x138, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_0 */ 0x140, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_0 */ 0x144, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_1 */ 0x180, sizeof(uint32_t), 0x30100010, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_1 */ 0x1a0, sizeof(uint32_t), 0x3003f, 0x1000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_1 */ 0x1b0, sizeof(uint32_t), 0xff, 0xf }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_1 */ 0x1b8, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_1 */ 0x1c0, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_1 */ 0x1c4, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_2 */ 0x200, sizeof(uint32_t), 0x30100010, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NVME_CTRL_2 */ 0x208, sizeof(uint32_t), 0x11, 0x1 }, \
|
||||
{ /* APCIE_COMMON_BLK_NVME_PRIORITY_2 */ 0x20c, sizeof(uint32_t), 0x7, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_2 */ 0x210, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_2 */ 0x220, sizeof(uint32_t), 0x3003f, 0x1000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_2 */ 0x230, sizeof(uint32_t), 0xff, 0xf }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_2 */ 0x238, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_2 */ 0x240, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_2 */ 0x244, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_3 */ 0x280, sizeof(uint32_t), 0x30100010, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_3 */ 0x2a0, sizeof(uint32_t), 0x3003f, 0x1000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_3 */ 0x2b0, sizeof(uint32_t), 0xff, 0xf }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_3 */ 0x2b8, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_3 */ 0x2c0, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_3 */ 0x2c4, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_4 */ 0x300, sizeof(uint32_t), 0x30100010, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_4 */ 0x320, sizeof(uint32_t), 0x3003f, 0x1000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_4 */ 0x330, sizeof(uint32_t), 0xff, 0xf }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_4 */ 0x338, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_4 */ 0x340, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_4 */ 0x344, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_5 */ 0x380, sizeof(uint32_t), 0x30100010, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_5 */ 0x3a0, sizeof(uint32_t), 0x3003f, 0x1000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_5 */ 0x3b0, sizeof(uint32_t), 0xff, 0xf }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_5 */ 0x3b8, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_5 */ 0x3c0, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_5 */ 0x3c4, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_COMMON_FPGA_TUNABLES_S8001_A0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_0 */ 0x100, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_1 */ 0x180, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_2 */ 0x200, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_3 */ 0x280, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_4 */ 0x300, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_5 */ 0x380, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_COMMON_NVME_TUNABLES_S8001_A0 \
|
||||
/* Key = nvme_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_0 */ 0x100, sizeof(uint32_t), 0x10, 0x10 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_1 */ 0x180, sizeof(uint32_t), 0x10, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_2 */ 0x200, sizeof(uint32_t), 0x10, 0x10 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_3 */ 0x280, sizeof(uint32_t), 0x10, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_4 */ 0x300, sizeof(uint32_t), 0x10, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_5 */ 0x380, sizeof(uint32_t), 0x10, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8001_A0_TUNABLE_APCIE_COMMON_H */
|
||||
@@ -0,0 +1,215 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8001_A0_TUNABLE_APCIE_CONFIG_H
|
||||
#define SPDS_S8001_A0_TUNABLE_APCIE_CONFIG_H
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xff)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x5)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x1)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x3)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xfff0fff)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x440089)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_DEFAULT_TUNABLES_S8001_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ /* APCIE_CONFIG_BLK_REGS_AMAP */ 0x144, sizeof(uint32_t), 0xfff0fff, 0x440089 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xff)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x5)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x1)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x3)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xfff0fff)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x440089)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_DEFAULT_TUNABLES_S8001_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ /* APCIE_CONFIG_BLK_REGS_AMAP */ 0x144, sizeof(uint32_t), 0xfff0fff, 0x440089 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xff)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x5)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x1)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x3)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xfff0fff)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x440089)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_DEFAULT_TUNABLES_S8001_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ /* APCIE_CONFIG_BLK_REGS_AMAP */ 0x144, sizeof(uint32_t), 0xfff0fff, 0x440089 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xff)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x5)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x1)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x3)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xfff0fff)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x440089)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_DEFAULT_TUNABLES_S8001_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ /* APCIE_CONFIG_BLK_REGS_AMAP */ 0x144, sizeof(uint32_t), 0xfff0fff, 0x440089 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xff)
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x5)
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x1)
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x3)
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xfff0fff)
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x440089)
|
||||
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_DEFAULT_TUNABLES_S8001_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ /* APCIE_CONFIG_BLK_REGS_AMAP */ 0x144, sizeof(uint32_t), 0xfff0fff, 0x440089 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xff)
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x5)
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x1)
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x3)
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xfff0fff)
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x440089)
|
||||
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_DEFAULT_TUNABLES_S8001_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ /* APCIE_CONFIG_BLK_REGS_AMAP */ 0x144, sizeof(uint32_t), 0xfff0fff, 0x440089 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8001_A0_TUNABLE_APCIE_CONFIG_H */
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8001_A0_TUNABLE_APCIE_PHY_GLUE_H
|
||||
#define SPDS_S8001_A0_TUNABLE_APCIE_PHY_GLUE_H
|
||||
|
||||
#define PCIE_APCIE_PHY_GLUE_BLK_REFBUF_CFG0_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x318c)
|
||||
#define PCIE_APCIE_PHY_GLUE_BLK_REFBUF_CFG0_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x2108)
|
||||
|
||||
#define PCIE_APCIE_PHY_GLUE_BLK_REFBUF_CFG1_DEFAULT_TUNABLE_UMASK_S8001_A0 (0x318c)
|
||||
#define PCIE_APCIE_PHY_GLUE_BLK_REFBUF_CFG1_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x2108)
|
||||
|
||||
#define PCIE_APCIE_PHY_GLUE_DEFAULT_TUNABLES_S8001_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_PHY_GLUE_BLK_REFBUF_CFG0 */ 0x0, sizeof(uint32_t), 0x318c, 0x2108 }, \
|
||||
{ /* APCIE_PHY_GLUE_BLK_REFBUF_CFG1 */ 0x4, sizeof(uint32_t), 0x318c, 0x2108 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8001_A0_TUNABLE_APCIE_PHY_GLUE_H */
|
||||
@@ -0,0 +1,149 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8001_A0_TUNABLE_X2_PCIE_RC_H
|
||||
#define SPDS_S8001_A0_TUNABLE_X2_PCIE_RC_H
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8001_A0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_DEFAULT_TUNABLES_S8001_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_FPGA_TUNABLES_S8001_A0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8001_A0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_DEFAULT_TUNABLES_S8001_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_FPGA_TUNABLES_S8001_A0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8001_A0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_DEFAULT_TUNABLES_S8001_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_FPGA_TUNABLES_S8001_A0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8001_A0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_DEFAULT_TUNABLES_S8001_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_FPGA_TUNABLES_S8001_A0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC4_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC4_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC4_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8001_A0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC4_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC4_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC4_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC4_DEFAULT_TUNABLES_S8001_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC4_FPGA_TUNABLES_S8001_A0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC5_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC5_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC5_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8001_A0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC5_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC5_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8001_A0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC5_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8001_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC5_DEFAULT_TUNABLES_S8001_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC5_FPGA_TUNABLES_S8001_A0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8001_A0_TUNABLE_X2_PCIE_RC_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8001_TUNABLE_APCIE_COMMON_H
|
||||
#define SPDS_S8001_TUNABLE_APCIE_COMMON_H
|
||||
|
||||
#include <platform/soc/s8001/a0/tunable/apcie_common.h>
|
||||
#include <platform/soc/s8001/b0/tunable/apcie_common.h>
|
||||
|
||||
#endif /* SPDS_S8001_TUNABLE_APCIE_COMMON_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8001_TUNABLE_APCIE_CONFIG_H
|
||||
#define SPDS_S8001_TUNABLE_APCIE_CONFIG_H
|
||||
|
||||
#include <platform/soc/s8001/a0/tunable/apcie_config.h>
|
||||
#include <platform/soc/s8001/b0/tunable/apcie_config.h>
|
||||
|
||||
#endif /* SPDS_S8001_TUNABLE_APCIE_CONFIG_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8001_TUNABLE_APCIE_PHY_GLUE_H
|
||||
#define SPDS_S8001_TUNABLE_APCIE_PHY_GLUE_H
|
||||
|
||||
#include <platform/soc/s8001/a0/tunable/apcie_phy_glue.h>
|
||||
#include <platform/soc/s8001/b0/tunable/apcie_phy_glue.h>
|
||||
|
||||
#endif /* SPDS_S8001_TUNABLE_APCIE_PHY_GLUE_H */
|
||||
@@ -0,0 +1,276 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8001_B0_TUNABLE_APCIE_COMMON_H
|
||||
#define SPDS_S8001_B0_TUNABLE_APCIE_COMMON_H
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_FABRIC_TLIMITS_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x7f7f7f7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_FABRIC_TLIMITS_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_LLT_RATE_LIMITER_CTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_LLT_RATE_LIMITER_CTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_COMMON_PRIORITY_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x700)
|
||||
#define PCIE_APCIE_COMMON_BLK_COMMON_PRIORITY_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NANDSYSCLK_TIMING_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xffffff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NANDSYSCLK_TIMING_DEFAULT_TUNABLE_VALUE_S8001_B0 (0xc0800)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NAND_LTR_THRESH_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x1fff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NAND_LTR_THRESH_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x92c)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PHY_POWERUP_CTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xffffffff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PHY_POWERUP_CTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_REFCLKBUF_TIMING_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_REFCLKBUF_TIMING_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x9)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_NVME_TUNABLE_UMASK_S8001_B0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_NVME_TUNABLE_VALUE_S8001_B0 (0x10)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x30100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_FPGA_TUNABLE_UMASK_S8001_B0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_FPGA_TUNABLE_VALUE_S8001_B0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NVME_CTRL_0_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x11)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NVME_CTRL_0_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_PRIORITY_0_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x7)
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_PRIORITY_0_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_0_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x3003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_0_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x1000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_0_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_0_DEFAULT_TUNABLE_VALUE_S8001_B0 (0xf)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_0_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_0_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_0_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_0_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_NVME_TUNABLE_UMASK_S8001_B0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_NVME_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x30100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_FPGA_TUNABLE_UMASK_S8001_B0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_FPGA_TUNABLE_VALUE_S8001_B0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_1_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x3003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_1_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x1000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_1_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_1_DEFAULT_TUNABLE_VALUE_S8001_B0 (0xf)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_1_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_1_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_1_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_1_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_1_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_1_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_NVME_TUNABLE_UMASK_S8001_B0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_NVME_TUNABLE_VALUE_S8001_B0 (0x10)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x30100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_FPGA_TUNABLE_UMASK_S8001_B0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_FPGA_TUNABLE_VALUE_S8001_B0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NVME_CTRL_2_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x11)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NVME_CTRL_2_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_PRIORITY_2_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x7)
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_PRIORITY_2_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_2_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_2_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_2_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x3003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_2_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x1000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_2_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_2_DEFAULT_TUNABLE_VALUE_S8001_B0 (0xf)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_2_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_2_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_2_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_2_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_2_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_2_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_NVME_TUNABLE_UMASK_S8001_B0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_NVME_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x30100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_FPGA_TUNABLE_UMASK_S8001_B0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_FPGA_TUNABLE_VALUE_S8001_B0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_3_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x3003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_3_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x1000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_3_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_3_DEFAULT_TUNABLE_VALUE_S8001_B0 (0xf)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_3_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_3_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_3_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_3_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_3_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_3_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_4_NVME_TUNABLE_UMASK_S8001_B0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_4_NVME_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_4_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x30100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_4_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_4_FPGA_TUNABLE_UMASK_S8001_B0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_4_FPGA_TUNABLE_VALUE_S8001_B0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_4_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x3003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_4_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x1000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_4_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_4_DEFAULT_TUNABLE_VALUE_S8001_B0 (0xf)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_4_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_4_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_4_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_4_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_4_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_4_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_5_NVME_TUNABLE_UMASK_S8001_B0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_5_NVME_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_5_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x30100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_5_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_5_FPGA_TUNABLE_UMASK_S8001_B0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_5_FPGA_TUNABLE_VALUE_S8001_B0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_5_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x3003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_5_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x1000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_5_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_5_DEFAULT_TUNABLE_VALUE_S8001_B0 (0xf)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_5_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_5_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_5_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_5_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_5_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_5_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_DEFAULT_TUNABLES_S8001_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_COMMON_BLK_FABRIC_TLIMITS */ 0x8, sizeof(uint32_t), 0x7f7f7f7f, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_LLT_RATE_LIMITER_CTRL */ 0xc, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_COMMON_PRIORITY */ 0x10, sizeof(uint32_t), 0x700, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NANDSYSCLK_TIMING */ 0x18, sizeof(uint32_t), 0xffffff, 0xc0800 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NAND_LTR_THRESH */ 0x1c, sizeof(uint32_t), 0x1fff, 0x92c }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PHY_POWERUP_CTRL */ 0x24, sizeof(uint32_t), 0xffffffff, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_REFCLKBUF_TIMING */ 0x2c, sizeof(uint32_t), 0xff, 0x9 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_0 */ 0x100, sizeof(uint32_t), 0x30100010, 0x10 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NVME_CTRL_0 */ 0x108, sizeof(uint32_t), 0x11, 0x1 }, \
|
||||
{ /* APCIE_COMMON_BLK_NVME_PRIORITY_0 */ 0x10c, sizeof(uint32_t), 0x7, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_0 */ 0x110, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_0 */ 0x120, sizeof(uint32_t), 0x3003f, 0x1000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_0 */ 0x130, sizeof(uint32_t), 0xff, 0xf }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_0 */ 0x138, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_0 */ 0x140, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_0 */ 0x144, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_1 */ 0x180, sizeof(uint32_t), 0x30100010, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_1 */ 0x1a0, sizeof(uint32_t), 0x3003f, 0x1000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_1 */ 0x1b0, sizeof(uint32_t), 0xff, 0xf }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_1 */ 0x1b8, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_1 */ 0x1c0, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_1 */ 0x1c4, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_2 */ 0x200, sizeof(uint32_t), 0x30100010, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NVME_CTRL_2 */ 0x208, sizeof(uint32_t), 0x11, 0x1 }, \
|
||||
{ /* APCIE_COMMON_BLK_NVME_PRIORITY_2 */ 0x20c, sizeof(uint32_t), 0x7, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_2 */ 0x210, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_2 */ 0x220, sizeof(uint32_t), 0x3003f, 0x1000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_2 */ 0x230, sizeof(uint32_t), 0xff, 0xf }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_2 */ 0x238, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_2 */ 0x240, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_2 */ 0x244, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_3 */ 0x280, sizeof(uint32_t), 0x30100010, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_3 */ 0x2a0, sizeof(uint32_t), 0x3003f, 0x1000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_3 */ 0x2b0, sizeof(uint32_t), 0xff, 0xf }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_3 */ 0x2b8, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_3 */ 0x2c0, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_3 */ 0x2c4, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_4 */ 0x300, sizeof(uint32_t), 0x30100010, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_4 */ 0x320, sizeof(uint32_t), 0x3003f, 0x1000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_4 */ 0x330, sizeof(uint32_t), 0xff, 0xf }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_4 */ 0x338, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_4 */ 0x340, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_4 */ 0x344, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_5 */ 0x380, sizeof(uint32_t), 0x30100010, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_5 */ 0x3a0, sizeof(uint32_t), 0x3003f, 0x1000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_5 */ 0x3b0, sizeof(uint32_t), 0xff, 0xf }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_5 */ 0x3b8, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_5 */ 0x3c0, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_5 */ 0x3c4, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_COMMON_FPGA_TUNABLES_S8001_B0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_0 */ 0x100, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_1 */ 0x180, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_2 */ 0x200, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_3 */ 0x280, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_4 */ 0x300, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_5 */ 0x380, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_COMMON_NVME_TUNABLES_S8001_B0 \
|
||||
/* Key = nvme_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_0 */ 0x100, sizeof(uint32_t), 0x10, 0x10 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_1 */ 0x180, sizeof(uint32_t), 0x10, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_2 */ 0x200, sizeof(uint32_t), 0x10, 0x10 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_3 */ 0x280, sizeof(uint32_t), 0x10, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_4 */ 0x300, sizeof(uint32_t), 0x10, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_5 */ 0x380, sizeof(uint32_t), 0x10, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8001_B0_TUNABLE_APCIE_COMMON_H */
|
||||
@@ -0,0 +1,215 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8001_B0_TUNABLE_APCIE_CONFIG_H
|
||||
#define SPDS_S8001_B0_TUNABLE_APCIE_CONFIG_H
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xff)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x5)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x1)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x3)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xfff0fff)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x440089)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_DEFAULT_TUNABLES_S8001_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ /* APCIE_CONFIG_BLK_REGS_AMAP */ 0x144, sizeof(uint32_t), 0xfff0fff, 0x440089 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xff)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x5)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x1)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x3)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xfff0fff)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x440089)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_DEFAULT_TUNABLES_S8001_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ /* APCIE_CONFIG_BLK_REGS_AMAP */ 0x144, sizeof(uint32_t), 0xfff0fff, 0x440089 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xff)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x5)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x1)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x3)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xfff0fff)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x440089)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_DEFAULT_TUNABLES_S8001_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ /* APCIE_CONFIG_BLK_REGS_AMAP */ 0x144, sizeof(uint32_t), 0xfff0fff, 0x440089 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xff)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x5)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x1)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x3)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xfff0fff)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x440089)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_DEFAULT_TUNABLES_S8001_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ /* APCIE_CONFIG_BLK_REGS_AMAP */ 0x144, sizeof(uint32_t), 0xfff0fff, 0x440089 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xff)
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x5)
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x1)
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x3)
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xfff0fff)
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x440089)
|
||||
|
||||
#define PCIE_APCIE_PORT4_APCIE_CONFIG_DEFAULT_TUNABLES_S8001_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ /* APCIE_CONFIG_BLK_REGS_AMAP */ 0x144, sizeof(uint32_t), 0xfff0fff, 0x440089 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xff)
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x5)
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x1)
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x3)
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xfff0fff)
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_BLK_REGS_AMAP_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x440089)
|
||||
|
||||
#define PCIE_APCIE_PORT5_APCIE_CONFIG_DEFAULT_TUNABLES_S8001_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x5, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ /* APCIE_CONFIG_BLK_REGS_AMAP */ 0x144, sizeof(uint32_t), 0xfff0fff, 0x440089 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8001_B0_TUNABLE_APCIE_CONFIG_H */
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8001_B0_TUNABLE_APCIE_PHY_GLUE_H
|
||||
#define SPDS_S8001_B0_TUNABLE_APCIE_PHY_GLUE_H
|
||||
|
||||
#define PCIE_APCIE_PHY_GLUE_BLK_REFBUF_CFG0_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x318c)
|
||||
#define PCIE_APCIE_PHY_GLUE_BLK_REFBUF_CFG0_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x2108)
|
||||
|
||||
#define PCIE_APCIE_PHY_GLUE_BLK_REFBUF_CFG1_DEFAULT_TUNABLE_UMASK_S8001_B0 (0x318c)
|
||||
#define PCIE_APCIE_PHY_GLUE_BLK_REFBUF_CFG1_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x2108)
|
||||
|
||||
#define PCIE_APCIE_PHY_GLUE_DEFAULT_TUNABLES_S8001_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_PHY_GLUE_BLK_REFBUF_CFG0 */ 0x0, sizeof(uint32_t), 0x318c, 0x2108 }, \
|
||||
{ /* APCIE_PHY_GLUE_BLK_REFBUF_CFG1 */ 0x4, sizeof(uint32_t), 0x318c, 0x2108 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8001_B0_TUNABLE_APCIE_PHY_GLUE_H */
|
||||
@@ -0,0 +1,149 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_S8001_B0_TUNABLE_X2_PCIE_RC_H
|
||||
#define SPDS_S8001_B0_TUNABLE_X2_PCIE_RC_H
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8001_B0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_DEFAULT_TUNABLES_S8001_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_FPGA_TUNABLES_S8001_B0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8001_B0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_DEFAULT_TUNABLES_S8001_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_FPGA_TUNABLES_S8001_B0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8001_B0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_DEFAULT_TUNABLES_S8001_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_FPGA_TUNABLES_S8001_B0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8001_B0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_DEFAULT_TUNABLES_S8001_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_FPGA_TUNABLES_S8001_B0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC4_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC4_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC4_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8001_B0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC4_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC4_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC4_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC4_DEFAULT_TUNABLES_S8001_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC4_FPGA_TUNABLES_S8001_B0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC5_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC5_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC5_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_S8001_B0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC5_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC5_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_S8001_B0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC5_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_S8001_B0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC5_DEFAULT_TUNABLES_S8001_B0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC5_FPGA_TUNABLES_S8001_B0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_S8001_B0_TUNABLE_X2_PCIE_RC_H */
|
||||
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