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@@ -0,0 +1,349 @@
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/*
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* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <platform.h>
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#include <platform/pmgr.h>
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#include <platform/soc/chipid.h>
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#include <platform/soc/hwclocks.h>
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#if SUB_PLATFORM_S8000
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#define MINIMUM_FUSE_REVISION 0x8
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#elif SUB_PLATFORM_S8001
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#define MINIMUM_FUSE_REVISION 0x6
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#elif SUB_PLATFORM_S8003
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#define MINIMUM_FUSE_REVISION 0x3
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#else
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#error "Unknown platform"
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#endif
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bool chipid_get_current_production_mode(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_XTRCT(rCFG_FUSE0) != 0;
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}
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bool chipid_get_raw_production_mode(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_XTRCT(rCFG_FUSE0_RAW) != 0;
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}
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void chipid_clear_production_mode(void)
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{
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rCFG_FUSE0 &= ~MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_UMASK;
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}
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bool chipid_get_secure_mode(void)
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{
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// demotion only applies to the SEP, so iBoot always reads
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// the raw value for secure mode (<rdar://problem/15182573>)
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return MINIPMGR_FUSE_CFG_FUSE0_SECURE_MODE_XTRCT(rCFG_FUSE0_RAW);
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}
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uint32_t chipid_get_security_domain(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_SECURITY_DOMAIN_XTRCT(rCFG_FUSE0);
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}
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uint32_t chipid_get_board_id(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_BID_XTRCT(rCFG_FUSE0);
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}
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uint32_t chipid_get_minimum_epoch(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_MINIMUM_EPOCH_XTRCT(rCFG_FUSE0);
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}
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uint32_t chipid_get_chip_id(void)
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{
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#if SUB_PLATFORM_S8000
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return 0x8000;
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#elif SUB_PLATFORM_S8001
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return 0x8001;
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#elif SUB_PLATFORM_S8003
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return 0x8003;
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#else
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#error "Unknown platform"
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#endif
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}
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uint32_t chipid_get_chip_revision(void)
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{
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// we use 4 bits for base layer and 4 bits for metal,
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// the fuses use 3 for each
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#if defined(MINIPMGR_FUSE_CFG_FUSE4_DEV_VERSION_XTRCT)
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uint32_t fuse_val = MINIPMGR_FUSE_CFG_FUSE4_DEV_VERSION_XTRCT(rCFG_FUSE4);
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return (fuse_val & 0x7) | (((fuse_val >> 3) & 0x7) << 4);
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#elif defined(MINIPMGR_FUSE_CFG_FUSE4_CHIP_REV_MAJOR_XTRCT)
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uint32_t fuse = rCFG_FUSE4;
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return ((MINIPMGR_FUSE_CFG_FUSE4_CHIP_REV_MAJOR_XTRCT(fuse) << 4) |
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(MINIPMGR_FUSE_CFG_FUSE4_CHIP_REV_MINOR_XTRCT(fuse)));
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#else
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#error "SPDS doesn't contain expected chip rev extraction defines"
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#endif
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}
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uint32_t chipid_get_osc_frequency(void)
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{
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return OSC_FREQ;
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}
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uint64_t chipid_get_ecid_id(void)
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{
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return ((uint64_t)rECIDHI << 32) | rECIDLO;
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}
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uint64_t chipid_get_die_id(void)
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{
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return ((uint64_t)rECIDHI << 32) | rECIDLO;
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}
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uint32_t chipid_get_cpu_voltage(uint32_t index)
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{
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uint32_t voltage = pmgr_binning_get_mv(index, false, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid CPU voltage index %d\n", index);
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return voltage;
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}
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uint32_t chipid_get_cpu_sram_voltage(uint32_t index)
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{
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uint32_t voltage = pmgr_binning_get_mv(index, true, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid CPU SRAM voltage index %d\n", index);
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return voltage;
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}
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uint32_t chipid_get_soc_voltage(uint32_t index)
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{
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uint32_t voltage;
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#if SUB_PLATFORM_S8001
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#if SUB_TARGET_J99A | SUB_TARGET_J98A
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index = CHIPID_SOC_VOLTAGE_VMIN;
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#else
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index = CHIPID_SOC_VOLTAGE_VNOM;
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#endif
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#endif
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voltage = pmgr_binning_get_mv(index, false, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid SOC voltage index %d\n", index);
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return voltage;
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}
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uint32_t chipid_get_gpu_voltage(uint32_t index)
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{
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uint32_t voltage = pmgr_binning_get_mv(index, false, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid GPU voltage index %d\n", index);
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return voltage;
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}
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uint32_t chipid_get_gpu_sram_voltage(uint32_t index)
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{
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uint32_t voltage = pmgr_binning_get_mv(index, true, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid GPU SRAM voltage index %d\n", index);
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return voltage;
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}
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uint32_t chipid_get_sram_voltage(uint32_t index)
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{
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uint32_t voltage = pmgr_binning_get_mv(CHIPID_VOLTAGE_FIXED, true, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid SRAM voltage index %d\n", index);
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return voltage;
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}
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bool chipid_get_fuse_lock(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE1_AP_LOCK_XTRCT(rCFG_FUSE1) != 0;
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}
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void chipid_set_fuse_lock(bool locked)
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{
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if (locked) {
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rCFG_FUSE1 |= MINIPMGR_FUSE_CFG_FUSE1_AP_LOCK_INSRT(1);
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asm("dsb sy");
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if (!chipid_get_fuse_lock()) {
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panic("Failed to lock fuses\n");
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}
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}
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}
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bool chipid_get_fuse_seal(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE1_SEAL_FUSES_XTRCT(rCFG_FUSE1) != 0;
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}
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uint32_t chipid_get_lpo_trim(void)
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{
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#if SUB_PLATFORM_S8000
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// <rdar://problem/18530570> LPO clock doesn't lock with fused TRIM value but does with 0 trim
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if (chipid_get_fuse_revision() < 3)
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return 0x20;
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else
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#endif
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return MINIPMGR_FUSE_CFG_FUSE2_LPO_TRIM_XTRCT(rCFG_FUSE2);
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}
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#if SUB_PLATFORM_S8000
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uint32_t chipid_get_pcie_txpll_vco_v2i_i_set(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE3_PCIE_TXPLL_VCO_V2I_I_SET_XTRCT(rCFG_FUSE3);
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}
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uint32_t chipid_get_pcie_txpll_vco_v2i_pi_set(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE3_PCIE_TXPLL_VCO_V2I_PI_SET_XTRCT(rCFG_FUSE3);
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}
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uint32_t chipid_get_pcie_refpll_vco_v2i_i_set(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE4_PCIE_REFPLL_VCO_V2I_I_SET_XTRCT(rCFG_FUSE4);
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}
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uint32_t chipid_get_pcie_refpll_vco_v2i_pi_set(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE4_PCIE_REFPLL_VCO_V2I_PI_SET_XTRCT(rCFG_FUSE4);
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}
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uint32_t chipid_get_pcie_rx_ldo(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE3_PCIE_RX_LDO_XTRCT(rCFG_FUSE3);
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}
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#elif SUB_PLATFORM_S8001 || SUB_PLATFORM_S8003
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uint32_t chipid_get_pcie_refpll_fcal_vco_digctrl(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE4_PCIE_REFPLL_FCAL_VCO_DIGCTRL_XTRCT(rCFG_FUSE4);
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}
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#endif
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uint32_t chipid_get_soc_temp_sensor_trim(uint32_t sensor_index)
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{
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uint32_t sensor_trim;
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#if SUB_PLATFORM_S8000 && defined(MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_TRIMG_UMASK)
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// S8000 A1
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if (chipid_get_chip_revision() == CHIP_REVISION_A1) {
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switch (sensor_index) {
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case 0:
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return MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_XTRCT_V1(rCFG_FUSE2);
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case 1:
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return MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN1_XTRCT_V1(rCFG_FUSE2);
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case 2:
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return MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN2_XTRCT_V1(rCFG_FUSE3);
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default:
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panic("invalid thermal sensor %u", sensor_index);
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}
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}
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#endif
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// S8000 B0/C0, S8001 A0/B0, S8003 A0/A1
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switch (sensor_index) {
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case 0:
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sensor_trim = rCFG_FUSE2;
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sensor_trim &= MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_TRIMG_UMASK | MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_TRIMO_UMASK;
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sensor_trim >>= MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_TRIMG_SHIFT;
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return sensor_trim;
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case 1:
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sensor_trim = rCFG_FUSE2;
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sensor_trim &= MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN1_TRIMG_UMASK | MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN1_TRIMO_UMASK;
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sensor_trim >>= MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN1_TRIMG_SHIFT;
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return sensor_trim;
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case 2:
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sensor_trim = rCFG_FUSE3;
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sensor_trim &= MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN2_TRIMG_UMASK | MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN2_TRIMO_UMASK;
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sensor_trim >>= MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN2_TRIMG_SHIFT;
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return sensor_trim;
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#if SUB_PLATFORM_S8001
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case 3:
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sensor_trim = rCFG_FUSE3;
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sensor_trim &= MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN3_TRIMG_UMASK | MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN3_TRIMO_UMASK;
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sensor_trim >>= MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN3_TRIMG_SHIFT;
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return sensor_trim;
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#endif
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default:
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panic("invalid thermal sensor %u", sensor_index);
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}
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}
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uint32_t chipid_get_fuse_revision(void)
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{
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uint32_t version = pmgr_binning_get_revision();
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if (version == PMGR_BINNING_NOTFOUND) {
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return 0;
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}
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return version;
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}
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uint32_t chipid_get_total_rails_leakage()
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{
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// FIXME
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return 0;
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}
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#if SUPPORT_FPGA
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#define FPGA_HAS_INT3 (FPGA_HAS_DISP | FPGA_HAS_MEDIA | FPGA_HAS_JPEG | FPGA_HAS_MSR | FPGA_HAS_VXD)
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uint32_t chipid_get_fpga_block_instantiation(void)
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{
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// Hardware blocks instantiated.
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uint32_t blocks = (rECID_FUSE3 >> 18) & 0xF;
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uint32_t mask = FPGA_HAS_ALWAYS;
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switch (blocks) {
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// INT2 := ACC + AF + AMC + SouthBridge + PCIE
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case 0x1:
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break;
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// INT2GFX := INT2 + GFX
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case 0x2:
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mask |= FPGA_HAS_GFX;
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break;
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// INT3 := INT2 + DISP + MEDIA + JPEG + MSR + VXD
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case 0x8:
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mask |= FPGA_HAS_INT3;
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break;
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// INT3GFX := INT3 + GFX
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case 0xA:
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mask |= (FPGA_HAS_INT3 | FPGA_HAS_GFX);
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break;
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default:
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panic("Unknown hardware block instantiation: 0x%x", blocks);
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}
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return mask;
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}
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#endif
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@@ -0,0 +1,276 @@
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/*
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||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
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* This file is only a database of the performance sate for CPU and GPU, regarding the kind of chip
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* or board, it has no access to the chip.
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*/
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#include <platform.h>
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#include <platform/soc/dvfmperf.h>
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// These array are the first iteration, the next part will include reference to board id, board rev, fuse rev.
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static const enum chipid_voltage_index s8000_cpu[] = {
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CHIPID_CPU_VOLTAGE_BYPASS,
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CHIPID_CPU_VOLTAGE_SECUREROM,
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CHIPID_CPU_VOLTAGE_396,
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CHIPID_CPU_VOLTAGE_600,
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CHIPID_CPU_VOLTAGE_912,
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CHIPID_CPU_VOLTAGE_1200,
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CHIPID_CPU_VOLTAGE_1512,
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CHIPID_CPU_VOLTAGE_1800,
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||||
CHIPID_CPU_VOLTAGE_1848,
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CHIPID_CPU_VOLTAGE_396,
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||||
CHIPID_CPU_VOLTAGE_396,
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CHIPID_CPU_VOLTAGE_396,
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CHIPID_CPU_VOLTAGE_396,
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CHIPID_CPU_VOLTAGE_1512_WA,
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CHIPID_CPU_VOLTAGE_1200_WA,
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CHIPID_CPU_VOLTAGE_396_WA,
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};
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||||
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static const enum chipid_voltage_index s8003_cpu[] = {
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CHIPID_CPU_VOLTAGE_BYPASS,
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CHIPID_CPU_VOLTAGE_SECUREROM,
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CHIPID_CPU_VOLTAGE_396,
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CHIPID_CPU_VOLTAGE_600,
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CHIPID_CPU_VOLTAGE_912,
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CHIPID_CPU_VOLTAGE_1200,
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CHIPID_CPU_VOLTAGE_1512,
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CHIPID_CPU_VOLTAGE_1800,
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CHIPID_CPU_VOLTAGE_1848,
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};
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static const enum chipid_voltage_index s8000a1_cpu[] = {
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CHIPID_CPU_VOLTAGE_BYPASS,
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CHIPID_CPU_VOLTAGE_SECUREROM,
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CHIPID_CPU_VOLTAGE_396,
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||||
CHIPID_CPU_VOLTAGE_600,
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||||
CHIPID_CPU_VOLTAGE_912,
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CHIPID_CPU_VOLTAGE_1200,
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CHIPID_CPU_VOLTAGE_1512,
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CHIPID_CPU_VOLTAGE_1800,
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CHIPID_CPU_VOLTAGE_1896,
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||||
};
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||||
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||||
static const enum chipid_voltage_index s8000_gpu[] = {
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||||
CHIPID_GPU_VOLTAGE_OFF,
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||||
CHIPID_GPU_VOLTAGE_340,
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||||
CHIPID_GPU_VOLTAGE_474,
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||||
CHIPID_GPU_VOLTAGE_550,
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||||
CHIPID_GPU_VOLTAGE_723,
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||||
};
|
||||
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||||
static const enum chipid_voltage_index s8003_gpu[] = {
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||||
CHIPID_GPU_VOLTAGE_OFF,
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||||
CHIPID_GPU_VOLTAGE_340,
|
||||
CHIPID_GPU_VOLTAGE_474,
|
||||
CHIPID_GPU_VOLTAGE_550,
|
||||
CHIPID_GPU_VOLTAGE_723,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8000a1_gpu[] = {
|
||||
CHIPID_GPU_VOLTAGE_OFF,
|
||||
CHIPID_GPU_VOLTAGE_340,
|
||||
CHIPID_GPU_VOLTAGE_474,
|
||||
CHIPID_GPU_VOLTAGE_550,
|
||||
CHIPID_GPU_VOLTAGE_616,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_cpu[] = {
|
||||
CHIPID_CPU_VOLTAGE_BYPASS,
|
||||
CHIPID_CPU_VOLTAGE_SECUREROM,
|
||||
CHIPID_CPU_VOLTAGE_396,
|
||||
CHIPID_CPU_VOLTAGE_720,
|
||||
CHIPID_CPU_VOLTAGE_1080,
|
||||
CHIPID_CPU_VOLTAGE_1440,
|
||||
CHIPID_CPU_VOLTAGE_1800,
|
||||
CHIPID_CPU_VOLTAGE_2160,
|
||||
CHIPID_CPU_VOLTAGE_2256_1core,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_gpu[] = {
|
||||
CHIPID_GPU_VOLTAGE_OFF,
|
||||
CHIPID_GPU_VOLTAGE_360,
|
||||
CHIPID_GPU_VOLTAGE_520,
|
||||
CHIPID_GPU_VOLTAGE_650,
|
||||
CHIPID_GPU_VOLTAGE_723,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8000_soc[] = {
|
||||
CHIPID_SOC_VOLTAGE_BYPASS,
|
||||
CHIPID_SOC_VOLTAGE_SECUREROM,
|
||||
CHIPID_SOC_VOLTAGE_VMIN,
|
||||
CHIPID_SOC_VOLTAGE_VNOM,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8003_soc[] = {
|
||||
CHIPID_SOC_VOLTAGE_BYPASS,
|
||||
CHIPID_SOC_VOLTAGE_SECUREROM,
|
||||
CHIPID_SOC_VOLTAGE_VMIN,
|
||||
CHIPID_SOC_VOLTAGE_VNOM,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_soc[] = {
|
||||
CHIPID_SOC_VOLTAGE_BYPASS,
|
||||
CHIPID_SOC_VOLTAGE_SECUREROM,
|
||||
CHIPID_SOC_VOLTAGE_VMIN,
|
||||
CHIPID_SOC_VOLTAGE_VMIN,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_j127_gpu[] = {
|
||||
CHIPID_GPU_VOLTAGE_OFF,
|
||||
CHIPID_GPU_VOLTAGE_360,
|
||||
CHIPID_GPU_VOLTAGE_520,
|
||||
CHIPID_GPU_VOLTAGE_650,
|
||||
CHIPID_GPU_VOLTAGE_723,
|
||||
CHIPID_GPU_VOLTAGE_804,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_j105_cpu[] = {
|
||||
CHIPID_CPU_VOLTAGE_BYPASS,
|
||||
CHIPID_CPU_VOLTAGE_SECUREROM,
|
||||
CHIPID_CPU_VOLTAGE_2256,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_j105_soc[] = {
|
||||
CHIPID_SOC_VOLTAGE_BYPASS,
|
||||
CHIPID_SOC_VOLTAGE_SECUREROM,
|
||||
CHIPID_SOC_VOLTAGE_VMIN,
|
||||
CHIPID_SOC_VOLTAGE_VMIN,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_j105_gpu[] = {
|
||||
CHIPID_GPU_VOLTAGE_OFF,
|
||||
CHIPID_GPU_VOLTAGE_723,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_j127_soc[] = {
|
||||
CHIPID_SOC_VOLTAGE_BYPASS,
|
||||
CHIPID_SOC_VOLTAGE_SECUREROM,
|
||||
CHIPID_SOC_VOLTAGE_VNOM,
|
||||
CHIPID_SOC_VOLTAGE_VNOM,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index s8001_j99a_soc[] = {
|
||||
CHIPID_SOC_VOLTAGE_BYPASS,
|
||||
CHIPID_SOC_VOLTAGE_SECUREROM,
|
||||
CHIPID_SOC_VOLTAGE_VMIN,
|
||||
CHIPID_SOC_VOLTAGE_VMIN,
|
||||
};
|
||||
|
||||
struct dvfmperf {
|
||||
uint32_t chip_id;
|
||||
uint32_t chip_rev;
|
||||
uint32_t board_id;
|
||||
const enum chipid_voltage_index *voltage_indexes;
|
||||
uint32_t size;
|
||||
};
|
||||
|
||||
|
||||
// The dvfmperfs arays must be sorted to have :
|
||||
// - BOARD_ID_NONE always coming last for chip/chip revision
|
||||
// - Highest chip revision coming first
|
||||
static const struct dvfmperf dvfmperfs_cpu[] = { // Entry with highest chip revision must come first
|
||||
{0x8000, CHIP_REVISION_B0, BOARD_ID_NONE, s8000_cpu, sizeof(s8000_cpu)/sizeof(s8000_cpu[0])},
|
||||
{0x8000, CHIP_REVISION_A1, BOARD_ID_NONE, s8000a1_cpu, sizeof(s8000a1_cpu)/sizeof(s8000a1_cpu[0])},
|
||||
{0x8003, CHIP_REVISION_A0, BOARD_ID_NONE, s8003_cpu, sizeof(s8003_cpu)/sizeof(s8003_cpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J105_AP_BOARD_ID, s8001_j105_cpu, sizeof(s8001_j105_cpu)/sizeof(s8001_j105_cpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J105_DEV_BOARD_ID, s8001_j105_cpu, sizeof(s8001_j105_cpu)/sizeof(s8001_j105_cpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, BOARD_ID_NONE, s8001_cpu, sizeof(s8001_cpu)/sizeof(s8000_cpu[0])},
|
||||
};
|
||||
|
||||
static const struct dvfmperf dvfmperfs_gpu[] = { // Entry with highest chip revision must come first
|
||||
{0x8000, CHIP_REVISION_B0, BOARD_ID_NONE, s8000_gpu, sizeof(s8000_gpu)/sizeof(s8000_gpu[0])},
|
||||
{0x8000, CHIP_REVISION_A1, BOARD_ID_NONE, s8000a1_gpu, sizeof(s8000a1_gpu)/sizeof(s8000a1_gpu[0])},
|
||||
{0x8003, CHIP_REVISION_A0, BOARD_ID_NONE, s8003_gpu, sizeof(s8003_gpu)/sizeof(s8003_gpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J128_AP_BOARD_ID, s8001_j127_gpu, sizeof(s8001_j127_gpu)/sizeof(s8001_j127_gpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J128_DEV_BOARD_ID, s8001_j127_gpu, sizeof(s8001_j127_gpu)/sizeof(s8001_j127_gpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J127_AP_BOARD_ID, s8001_j127_gpu, sizeof(s8001_j127_gpu)/sizeof(s8001_j127_gpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J127_DEV_BOARD_ID, s8001_j127_gpu, sizeof(s8001_j127_gpu)/sizeof(s8001_j127_gpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J105_AP_BOARD_ID, s8001_j105_gpu, sizeof(s8001_j105_gpu)/sizeof(s8001_j105_gpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J105_DEV_BOARD_ID, s8001_j105_gpu, sizeof(s8001_j105_gpu)/sizeof(s8001_j105_gpu[0])},
|
||||
{0x8001, CHIP_REVISION_A0, BOARD_ID_NONE, s8001_gpu, sizeof(s8001_gpu)/sizeof(s8001_gpu[0])},
|
||||
};
|
||||
|
||||
static const struct dvfmperf dvfmperfs_soc[] = { // Entry with highest chip revision must come first
|
||||
{0x8000, CHIP_REVISION_B0, BOARD_ID_NONE, s8000_soc, sizeof(s8000_soc)/sizeof(s8000_soc[0])},
|
||||
{0x8003, CHIP_REVISION_A0, BOARD_ID_NONE, s8003_soc, sizeof(s8003_soc)/sizeof(s8003_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J105_AP_BOARD_ID, s8001_j105_soc, sizeof(s8001_j105_soc)/sizeof(s8001_j105_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J105_DEV_BOARD_ID, s8001_j105_soc, sizeof(s8001_j105_soc)/sizeof(s8001_j105_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J128_AP_BOARD_ID, s8001_j127_soc, sizeof(s8001_j127_soc)/sizeof(s8001_j127_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J128_DEV_BOARD_ID, s8001_j127_soc, sizeof(s8001_j127_soc)/sizeof(s8001_j127_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J127_AP_BOARD_ID, s8001_j127_soc, sizeof(s8001_j127_soc)/sizeof(s8001_j127_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J127_DEV_BOARD_ID, s8001_j127_soc, sizeof(s8001_j127_soc)/sizeof(s8001_j127_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J99A_AP_BOARD_ID, s8001_j99a_soc, sizeof(s8001_j99a_soc)/sizeof(s8001_j99a_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J99A_DEV_BOARD_ID, s8001_j99a_soc, sizeof(s8001_j99a_soc)/sizeof(s8001_j99a_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J98A_AP_BOARD_ID, s8001_j99a_soc, sizeof(s8001_j99a_soc)/sizeof(s8001_j99a_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, J98A_DEV_BOARD_ID, s8001_j99a_soc, sizeof(s8001_j99a_soc)/sizeof(s8001_j99a_soc[0])},
|
||||
{0x8001, CHIP_REVISION_A0, BOARD_ID_NONE, s8001_soc, sizeof(s8001_soc)/sizeof(s8001_soc[0])},
|
||||
};
|
||||
|
||||
enum chipid_voltage_index dvfmperf_get_voltage_index(uint32_t index, enum chipid_voltage_type voltage_type)
|
||||
{
|
||||
const struct dvfmperf *dvfmperfs;
|
||||
enum chipid_voltage_index voltage_index_for_filling;
|
||||
uint32_t chip_id = chipid_get_chip_id();
|
||||
uint32_t chip_rev = chipid_get_chip_revision();
|
||||
uint32_t board_id = platform_get_board_id();
|
||||
uint32_t i;
|
||||
uint32_t size = 0;
|
||||
|
||||
switch (voltage_type) {
|
||||
case CHIPID_CPU_VOLTAGE:
|
||||
dvfmperfs = dvfmperfs_cpu;
|
||||
voltage_index_for_filling = CHIPID_CPU_VOLTAGE_396;
|
||||
size = sizeof(dvfmperfs_cpu)/sizeof(dvfmperfs_cpu[0]);
|
||||
break;
|
||||
case CHIPID_GPU_VOLTAGE:
|
||||
dvfmperfs = dvfmperfs_gpu;
|
||||
size = sizeof(dvfmperfs_gpu)/sizeof(dvfmperfs_gpu[0]);
|
||||
voltage_index_for_filling = CHIPID_GPU_VOLTAGE_OFF;
|
||||
break;
|
||||
case CHIPID_SOC_VOLTAGE:
|
||||
dvfmperfs = dvfmperfs_soc;
|
||||
size = sizeof(dvfmperfs_soc)/sizeof(dvfmperfs_soc[0]);
|
||||
break;
|
||||
default:
|
||||
panic("Invalid voltage type\n");
|
||||
voltage_index_for_filling = CHIPID_GPU_VOLTAGE_OFF; // prevent compiler warning
|
||||
dvfmperfs = NULL; // Prevent compiler warning
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (chip_id != dvfmperfs[i].chip_id) {
|
||||
continue;
|
||||
}
|
||||
if (chip_rev < dvfmperfs[i].chip_rev) {
|
||||
continue;
|
||||
}
|
||||
if ((board_id != dvfmperfs[i].board_id) && (dvfmperfs[i].board_id != BOARD_ID_NONE)) {
|
||||
continue;
|
||||
}
|
||||
if (index >= dvfmperfs[i].size) {
|
||||
if (voltage_type == CHIPID_SOC_VOLTAGE) {
|
||||
if (dvfmperfs[i].size < 4) {
|
||||
panic("Invalid number of SOC perf states");
|
||||
}
|
||||
voltage_index_for_filling = dvfmperfs[i].voltage_indexes[2];
|
||||
}
|
||||
return voltage_index_for_filling;
|
||||
}
|
||||
return dvfmperfs[i].voltage_indexes[index];
|
||||
}
|
||||
panic("Unknown voltage for current chip\n");
|
||||
return CHIPID_GPU_VOLTAGE_OFF; // Never reach this code
|
||||
}
|
||||
@@ -0,0 +1,210 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is only a database of the frequencies used by CPU and GPU, it has no access
|
||||
* To the chip.
|
||||
*/
|
||||
#include <platform.h>
|
||||
#include <platform/soc/operating_point.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
|
||||
#define CHIP_ID_ALL 0
|
||||
#define DELIMITER CHIPID_ALL_VOLTAGE_LAST
|
||||
|
||||
static const struct operating_point_params operating_point_params[] = {
|
||||
// GPU
|
||||
{.chipid_max = DELIMITER, .chip_id = 0x8000, .voltage_type = CHIPID_GPU_VOLTAGE},
|
||||
// P M S
|
||||
// | | |
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_OFF,0,0, 0, 0, 0}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_340,0,0, 2,170, 5}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_474,0,0, 2,158, 3}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_550,0,0, 3,275, 3}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_616,0,0, 3,154, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_723,0,0, 1, 90, 2}}}, // It's 720 now for <rdar://problem/22294854> Change GPU & SoC PLL settings to recover yield
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_804,0,0, 1, 67, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_850,0,0, 6,425, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_900,0,0, 1, 75, 1}}},
|
||||
|
||||
{.chipid_max = DELIMITER, .chip_id = 0x8003, .voltage_type = CHIPID_GPU_VOLTAGE},
|
||||
// P M S
|
||||
// | | |
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_OFF,0,0, 0, 0, 0}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_340,0,0, 2, 85, 2}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_474,0,0, 2, 79, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_550,0,0, 4,275, 2}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_723,0,0, 4,241, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_804,0,0, 1, 67, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_850,0,0, 6,425, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_900,0,0, 1, 75, 1}}},
|
||||
|
||||
{.chipid_max = DELIMITER, .chip_id = 0x8001, .voltage_type = CHIPID_GPU_VOLTAGE},
|
||||
// P M S
|
||||
// | | |
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_OFF,0,0, 0, 0, 0}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_360,0,0, 1, 60, 3}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_520,0,0, 1, 65, 2}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_650,0,0, 6,325, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_723,0,0, 4,241, 1}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_800,0,0, 3,100, 0}}},
|
||||
{{.gpu = {CHIPID_GPU_VOLTAGE_804,0,0, 1, 67, 1}}},
|
||||
|
||||
|
||||
// S8000 B0
|
||||
{.chipid_max = DELIMITER, .chip_id = 0x8000, .voltage_type = CHIPID_CPU_VOLTAGE, .chip_rev = CHIP_REVISION_B0},
|
||||
// bypass
|
||||
// | clkSrc
|
||||
// | | P M S biuDiv4HiVol
|
||||
// | | | | | | biuDiv4LoVol
|
||||
// | | | | | | | dvmrMaxWgt
|
||||
// | | | | | | | | iexrfCfgWrData
|
||||
// | | | | | | | | | iexrfCfgWrIdxa
|
||||
// | | | | | | | | | | iexrfCfgWrIdxb
|
||||
// | | | | | | | | | | | exrfCfgWrIdxmuxsel
|
||||
// | | | | | | | | | | | | nrgAccScaleTab(Ext)
|
||||
// | | | | | | | | | | | | | lkgEstTab(Ext)
|
||||
// | | | | | | | | | | | | | | dpe0DvfmTab(Ext)
|
||||
// | | | | | | | | | | | | | | |
|
||||
{{{CHIPID_CPU_VOLTAGE_BYPASS, 0, 0, 0, 0, 0, 2, 2, 0xf, 1, 0, 0, 0, 0x1, 0x1, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_SECUREROM,1, 1, 1, 50, 3, 2, 2, 0xf, 1, 0, 0, 0, 0x1, 0x1, 0xff}}}, // 300MHz
|
||||
{{{CHIPID_CPU_VOLTAGE_396, 0, 1, 1, 66, 3, 2, 2, 0xf, 1, 0, 0, 0, 0x37, 0x30, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_600, 0, 1, 1, 75, 2, 2, 3, 0xf, 1, 0, 0, 0, 0x3e, 0x1f, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_912, 0, 1, 1, 76, 1, 4, 4, 0xf, 1, 0, 0, 0, 0x53, 0x14, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1200, 0, 1, 1, 50, 0, 4, 5, 0xf, 1, 0, 0, 0, 0x66, 0x0f, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1512, 0, 1, 1, 63, 0, 5, 6, 0xf, 1, 0, 0, 0, 0x88, 0x0c, 0xd7}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1800, 0, 1, 1, 75, 0, 6, 7, 0xf, 1, 0, 0, 0, 0xbf, 0x0b, 0x97}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1848, 0, 1, 1, 77, 0, 6, 7, 0x2, 1, 0, 0, 0, 0xbf, 0x0a, 0x93}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1896, 0, 1, 1, 79, 0, 6, 7, 0x2, 1, 0, 0, 0, 0xc5, 0x16, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1992, 0, 1, 1, 83, 0, 6, 7, 0xf, 1, 0, 0, 0, 0xc8, 0x15, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_2112, 0, 1, 1, 88, 0, 7, 0, 0x2, 1, 0, 0, 0, 0xc8, 0x14, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_396_WA, 0, 1, 1, 82, 4, 2, 2, 0xf, 1, 0, 0, 0, 0x37, 0x30, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1200_WA, 0, 1, 1, 76, 1, 4, 5, 0xf, 1, 0, 0, 0, 0x66, 0x0f, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1512_WA, 0, 1, 1, 76, 1, 5, 6, 0xf, 1, 0, 0, 0, 0x88, 0x0c, 0xd7}}},
|
||||
|
||||
// S8000 A1
|
||||
{.chipid_max = DELIMITER, .chip_id = 0x8000, .voltage_type = CHIPID_CPU_VOLTAGE},
|
||||
// bypass
|
||||
// | clkSrc
|
||||
// | | P M S biuDiv4HiVol
|
||||
// | | | | | | biuDiv4LoVol
|
||||
// | | | | | | | dvmrMaxWgt
|
||||
// | | | | | | | | iexrfCfgWrData
|
||||
// | | | | | | | | | iexrfCfgWrIdxa
|
||||
// | | | | | | | | | | iexrfCfgWrIdxb
|
||||
// | | | | | | | | | | | exrfCfgWrIdxmuxsel
|
||||
// | | | | | | | | | | | | nrgAccScaleTab(Ext)
|
||||
// | | | | | | | | | | | | | lkgEstTab(Ext)
|
||||
// | | | | | | | | | | | | | | dpe0DvfmTab(Ext)
|
||||
// | | | | | | | | | | | | | | |
|
||||
{{{CHIPID_CPU_VOLTAGE_BYPASS, 0, 0, 0, 0, 0, 2, 2, 0xf, 0, 0, 0, 0, 0x1, 0x1, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_SECUREROM,1, 1, 1, 50, 3, 2, 2, 0xf, 0, 0, 0, 0, 0x1, 0x1, 0xff}}}, // 300MHz
|
||||
{{{CHIPID_CPU_VOLTAGE_396, 0, 1, 1, 66, 3, 2, 2, 0xf, 0, 0, 0, 0, 0x3e, 0x46, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_600, 0, 1, 1, 50, 1, 2, 3, 0xf, 0, 0, 0, 0, 0x44, 0x2f, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_912, 0, 1, 1, 76, 1, 4, 4, 0xf, 0, 0, 0, 0, 0x5b, 0x1d, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1200, 0, 1, 1, 50, 0, 4, 5, 0xf, 0, 0, 0, 0, 0x74, 0x16, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1512, 0, 1, 1, 63, 0, 5, 6, 0xf, 0, 0, 0, 0, 0x91, 0x11, 0xd7}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1800, 0, 1, 1, 75, 0, 6, 7, 0xf, 0, 0, 0, 0, 0xaf, 0x0f, 0x97}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1896, 0, 1, 1, 79, 0, 6, 7, 0x2, 0, 0, 0, 0, 0xbc, 0x0e, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1992, 0, 1, 1, 83, 0, 6, 7, 0xf, 0, 0, 0, 0, 0xc8, 0x0d, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_2112, 0, 1, 1, 88, 0, 7, 0, 0x2, 0, 0, 0, 0, 0xc8, 0x0c, 0xff}}},
|
||||
|
||||
// S8001
|
||||
{.chipid_max = DELIMITER, .chip_id = 0x8001, .voltage_type = CHIPID_CPU_VOLTAGE},
|
||||
// bypass
|
||||
// | clkSrc
|
||||
// | | P M S biuDiv4HiVol
|
||||
// | | | | | | biuDiv4LoVol
|
||||
// | | | | | | | dvmrMaxWgt
|
||||
// | | | | | | | | iexrfCfgWrData
|
||||
// | | | | | | | | | iexrfCfgWrIdxa
|
||||
// | | | | | | | | | | iexrfCfgWrIdxb
|
||||
// | | | | | | | | | | | exrfCfgWrIdxmuxsel
|
||||
// | | | | | | | | | | | | nrgAccScaleTab(Ext)
|
||||
// | | | | | | | | | | | | | lkgEstTab(Ext)
|
||||
// | | | | | | | | | | | | | | dpe0DvfmTab(Ext)
|
||||
// | | | | | | | | | | | | | | |
|
||||
{{{CHIPID_CPU_VOLTAGE_BYPASS, 0, 0, 0, 0, 0, 2, 2, 0xf, 0, 0, 0, 0, 0x1, 0x1, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_SECUREROM,1, 1, 1, 75, 6, 2, 2, 0xf, 0, 0, 0, 0, 0x1, 0x1, 0xff}}}, // 300MHz
|
||||
{{{CHIPID_CPU_VOLTAGE_396, 0, 1, 1, 66, 3, 2, 2, 0xf, 0, 0, 0, 0, 0x3d, 0x2b, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_720, 0, 1, 1, 90, 2, 2, 2, 0xf, 0, 0, 0, 0, 0x4a, 0x17, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1080, 0, 1, 1, 90, 1, 3, 3, 0xf, 0, 0, 0, 0, 0x58, 0x0e, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1440, 0, 1, 1, 60, 0, 4, 4, 0xf, 0, 0, 0, 0, 0x6b, 0x0a, 0xfb}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1800, 0, 1, 1, 75, 0, 5, 5, 0xf, 0, 0, 0, 0, 0x99, 0x08, 0xa8}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_2160, 0, 1, 1, 90, 0, 5, 5, 0xf, 0, 0, 0, 0, 0xc1, 0x06, 0x7c}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_2256_1core,0,1, 1, 94, 0, 5, 5, 0x2, 0, 0, 0, 0, 0xc1, 0x06, 0x77}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_2256, 0, 1, 1, 94, 0, 5, 5, 0xf, 0, 0, 0, 0, 0xc1, 0x06, 0x77}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_2352, 0, 1, 1, 98, 0, 5, 5, 0xf, 0, 0, 0, 0, 0xe0, 0x0d, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_2448, 0, 1, 1, 102,0, 6, 6, 0x2, 0, 0, 0, 0, 0xe0, 0x0d, 0xff}}},
|
||||
|
||||
// S8003
|
||||
{.chipid_max = DELIMITER, .chip_id = 0x8003, .voltage_type = CHIPID_CPU_VOLTAGE},
|
||||
// bypass
|
||||
// | clkSrc
|
||||
// | | P M S biuDiv4HiVol
|
||||
// | | | | | | biuDiv4LoVol
|
||||
// | | | | | | | dvmrMaxWgt
|
||||
// | | | | | | | | iexrfCfgWrData
|
||||
// | | | | | | | | | iexrfCfgWrIdxa
|
||||
// | | | | | | | | | | iexrfCfgWrIdxb
|
||||
// | | | | | | | | | | | exrfCfgWrIdxmuxsel
|
||||
// | | | | | | | | | | | | nrgAccScaleTab(Ext)
|
||||
// | | | | | | | | | | | | | lkgEstTab(Ext)
|
||||
// | | | | | | | | | | | | | | dpe0DvfmTab(Ext)
|
||||
// | | | | | | | | | | | | | | |
|
||||
{{{CHIPID_CPU_VOLTAGE_BYPASS, 0, 0, 0, 0, 0, 2, 2, 0xf, 0, 0, 0, 0, 0x1, 0x1, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_SECUREROM,1, 1, 1, 75, 6, 2, 2, 0xf, 0, 0, 0, 0, 0x1, 0x1, 0xff}}}, // 300MHz
|
||||
{{{CHIPID_CPU_VOLTAGE_396, 0, 1, 1, 66, 3, 2, 2, 0xf, 0, 0, 0, 0, 0x3a, 0x2c, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_600, 0, 1, 1, 75, 2, 2, 3, 0xf, 0, 0, 0, 0, 0x40, 0x1c, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_912, 0, 1, 1, 76, 1, 4, 4, 0xf, 0, 0, 0, 0, 0x4f, 0x11, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1200, 0, 1, 1,100, 1, 4, 5, 0xf, 0, 0, 0, 0, 0x5e, 0x0d, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1512, 0, 1, 1, 63, 0, 5, 6, 0xf, 0, 0, 0, 0, 0x73, 0x0a, 0xe7}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1800, 0, 1, 1, 75, 0, 6, 7, 0xf, 0, 0, 0, 0, 0x82, 0x08, 0xb6}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1848, 0, 1, 1, 77, 0, 6, 7, 0x2, 0, 0, 0, 0, 0x82, 0x08, 0xb1}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1896, 0, 1, 1, 79, 0, 6, 7, 0xf, 0, 0, 0, 0, 0xa7, 0x10, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_1992, 0, 1, 1, 83, 0, 6, 7, 0xf, 0, 0, 0, 0, 0xb2, 0x10, 0xff}}},
|
||||
{{{CHIPID_CPU_VOLTAGE_2112, 0, 1, 1, 88, 0, 7, 0, 0x2, 0, 0, 0, 0, 0xbf, 0x0f, 0xff}}},
|
||||
};
|
||||
|
||||
const struct operating_point_params *operating_point_get_params(enum chipid_voltage_index voltage_index, enum chipid_voltage_type voltage_type)
|
||||
{
|
||||
uint64_t chip_id = chipid_get_chip_id();
|
||||
uint64_t chip_rev = chipid_get_chip_revision();
|
||||
uint64_t chip_id_in_array = 0;
|
||||
uint64_t chip_rev_in_array = 0;
|
||||
size_t size = sizeof(operating_point_params)/sizeof(operating_point_params[0]);
|
||||
enum chipid_voltage_type voltage_type_in_array = CHIPID_CPU_VOLTAGE;
|
||||
|
||||
size_t found = size;
|
||||
for (size_t i = 0; i < size; i++) {
|
||||
if (operating_point_params[i].voltage_index == DELIMITER) {
|
||||
chip_id_in_array = operating_point_params[i].chip_id;
|
||||
chip_rev_in_array = operating_point_params[i].chip_rev;
|
||||
voltage_type_in_array = operating_point_params[i].voltage_type;
|
||||
continue;
|
||||
}
|
||||
if ((voltage_type_in_array != voltage_type)) {
|
||||
continue;
|
||||
}
|
||||
if (chip_rev_in_array > chip_rev) {
|
||||
continue;
|
||||
}
|
||||
if ((operating_point_params[i].voltage_index == voltage_index) && ((chip_id_in_array == CHIP_ID_ALL) || (chip_id_in_array == chip_id))) {
|
||||
found = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (found == size) {
|
||||
panic("%s Index %d not found for chipId 0x%llx\n",
|
||||
__func__, voltage_index, chip_id);
|
||||
}
|
||||
return &operating_point_params[found];
|
||||
}
|
||||
@@ -0,0 +1,385 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
//
|
||||
// Please update test plan version to know what is the reference.
|
||||
//
|
||||
// Maui Test Plan Version 2.26
|
||||
// Maui Tunables Specification Revision 0.80
|
||||
//
|
||||
|
||||
#include <platform/pmgr.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
|
||||
//
|
||||
// Fuses in MINIPMGR are linearly mapped
|
||||
//
|
||||
static const struct pmgr_binning_fuse_to_register minipmgr_fuse_register[] = {
|
||||
// binning_low
|
||||
// | binning_high
|
||||
// | | register_low
|
||||
// | | | register_64bit
|
||||
// | | | | register_address
|
||||
// | | | | |
|
||||
{ 0, 369, 0, 0, AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE0_OFFSET},
|
||||
{ 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
//
|
||||
// Fuses in ACC (UDR) are sparsely mapped
|
||||
//
|
||||
static const struct pmgr_binning_fuse_to_register acc_fuse_register[] = {
|
||||
// binning_low
|
||||
// | binning_high
|
||||
// | | register_low
|
||||
// | | | register_64bit
|
||||
// | | | | register_address
|
||||
// | | | | |
|
||||
{ 0, 2, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST0_EXT2_OFFSET},
|
||||
{ 3, 6, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST0_EXT2_OFFSET},
|
||||
{ 7, 9, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST1_EXT2_OFFSET},
|
||||
{ 10, 13, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST1_EXT2_OFFSET},
|
||||
{ 14, 16, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST2_EXT2_OFFSET},
|
||||
{ 17, 20, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST2_EXT2_OFFSET},
|
||||
{ 21, 23, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST3_EXT2_OFFSET},
|
||||
{ 24, 27, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST3_EXT2_OFFSET},
|
||||
{ 28, 30, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST4_EXT2_OFFSET},
|
||||
{ 31, 34, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST4_EXT2_OFFSET},
|
||||
{ 35, 37, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST5_EXT2_OFFSET},
|
||||
{ 38, 41, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST5_EXT2_OFFSET},
|
||||
{ 42, 44, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST6_EXT2_OFFSET},
|
||||
{ 45, 48, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST6_EXT2_OFFSET},
|
||||
{ 40, 51, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST7_EXT2_OFFSET},
|
||||
{ 52, 55, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST7_EXT2_OFFSET},
|
||||
{ 56, 58, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST8_EXT2_OFFSET},
|
||||
{ 59, 62, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST8_EXT2_OFFSET},
|
||||
{ 112, 114,29, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 115, 119,24, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 120, 127,16, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
|
||||
const struct pmgr_binning_mode_to_fuse pmgr_binning_mode_to_fuse_data[] = {
|
||||
//
|
||||
// CPU
|
||||
//
|
||||
|
||||
//type
|
||||
//| mode
|
||||
//| | bingroup
|
||||
//| | | low
|
||||
//| | | | high
|
||||
//| | | | | fuse_to_register
|
||||
//| | | | | |
|
||||
{PMGR_BINNING_CPU, 1, PMGR_BINNING_GROUP_ALL, 7, 13, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 2, PMGR_BINNING_GROUP_ALL, 14, 20, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 3, PMGR_BINNING_GROUP_ALL, 21, 27, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 4, PMGR_BINNING_GROUP_ALL, 28, 34, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 5, PMGR_BINNING_GROUP_ALL, 35, 41, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 6, PMGR_BINNING_GROUP_ALL, 42, 48, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 7, PMGR_BINNING_GROUP_ALL, 49, 55, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 8, PMGR_BINNING_GROUP_ALL, 56, 62, acc_fuse_register},
|
||||
|
||||
//
|
||||
// GPU/SOC
|
||||
//
|
||||
|
||||
//type
|
||||
//| mode
|
||||
//| | bingroup
|
||||
//| | | low
|
||||
//| | | | high
|
||||
//| | | | | fuse_to_register
|
||||
//| | | | | |
|
||||
{PMGR_BINNING_GPU, 1, PMGR_BINNING_GROUP_ALL, 238, 244, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 2, PMGR_BINNING_GROUP_ALL, 245, 251, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 3, PMGR_BINNING_GROUP_ALL, 252, 258, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 4, PMGR_BINNING_GROUP_ALL, 259, 265, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 5, PMGR_BINNING_GROUP_ALL, 217, 223, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_SOC, 1, PMGR_BINNING_GROUP_ALL, 224, 230, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_SOC, 2, PMGR_BINNING_GROUP_ALL, 231, 237, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_BASE, 0, PMGR_BINNING_GROUP_ALL, 115, 119, acc_fuse_register},
|
||||
|
||||
{PMGR_BINNING_REV, 0, PMGR_BINNING_GROUP_ALL, 142, 147, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_GROUP, 0, PMGR_BINNING_GROUP_ALL, 268, 269, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_END_OF_LIST, 0, PMGR_BINNING_GROUP_ALL, 0, 0, NULL},
|
||||
};
|
||||
|
||||
//
|
||||
// Group-specific entries must come before the corresponding entry with PMGR_BINNING_GROUP_ALL.
|
||||
//
|
||||
const struct pmgr_binning_voltage_index_to_config pmgr_binning_voltage_index_to_config_data[] = {
|
||||
// voltage index
|
||||
// | safe voltage
|
||||
// | | mode
|
||||
// | | | type
|
||||
// | | | | binning group
|
||||
// | | | | | fuse revision minimun
|
||||
// | | | | | |
|
||||
{CHIPID_CPU_VOLTAGE_BYPASS, 610, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_SECUREROM, 610, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_396, 610, 1, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_600, 641, 2, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_912, 742, 3, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1200, 836, 4, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1512, 937, 5, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1800, 1090, 6, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1848, 1090, 6, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1896, 1090, 7, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1992, 1100, 8, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
{CHIPID_CPU_VOLTAGE_396_WA, 610, 1, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1200_WA, 836, 4, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1512_WA, 937, 5, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
// SEG-characterization
|
||||
{CHIPID_CPU_VOLTAGE_2112, 1100, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
{CHIPID_SOC_VOLTAGE_BYPASS, 725, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_SOC_VOLTAGE_SECUREROM, 725, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_SOC_VOLTAGE_VMIN, 725, 1, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_SOC_VOLTAGE_VNOM, 825, 2, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
{CHIPID_GPU_VOLTAGE_OFF, 0, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_340, 700, 1, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_474, 800, 2, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_550, 920, 3, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_616, 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_723, 1030, 4, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
// SEG-characterization
|
||||
{CHIPID_GPU_VOLTAGE_804, 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_850, 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_900, 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
};
|
||||
|
||||
//
|
||||
// Safe voltage of 0 and binning mode != PMGR_BINNING_MODE_NONE
|
||||
// means data are store in pmgr_binning_mode_to_const_data
|
||||
//
|
||||
const struct pmgr_binning_voltage_config pmgr_binning_voltage_config_sram_data[] = {
|
||||
// safe voltage (0 means lookup data in pmgr_binning_mode_to_const_data)
|
||||
// | mode
|
||||
// | | type
|
||||
// | | |
|
||||
[CHIPID_CPU_VOLTAGE_BYPASS] = { 800, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_SECUREROM] = { 800, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_396] = { 0, 1, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_600] = { 0, 2, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_912] = { 0, 3, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1200] = { 0, 4, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1512] = { 0, 5, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1800] = { 0, 6, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1848] = { 0, 6, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1896] = {1090, 7, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1992] = {1100, 8, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_2112] = {1100, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_396_WA] = { 0, 1, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1200_WA] = { 0, 4, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1512_WA] = { 0, 5, PMGR_BINNING_CPU_SRAM},
|
||||
|
||||
[CHIPID_GPU_VOLTAGE_OFF] = { 0, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_340] = { 0, 1, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_474] = { 0, 2, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_550] = { 0, 3, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_616] = { 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_723] = { 0, 4, PMGR_BINNING_GPU_SRAM},
|
||||
// SEG-characterization
|
||||
[CHIPID_GPU_VOLTAGE_804] = { 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_850] = { 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_900] = { 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
|
||||
[CHIPID_VOLTAGE_FIXED] = {850, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SRAM},
|
||||
};
|
||||
|
||||
//
|
||||
// Group-specific entries must come before the corresponding entry with PMGR_BINNING_GROUP_ALL.
|
||||
//
|
||||
const struct pmgr_binning_mode_to_const pmgr_binning_mode_to_const_data[] = {
|
||||
// Voltage
|
||||
// | Mode
|
||||
// | | Type
|
||||
// | | | Binning group
|
||||
// | | | | fuse revision minimun
|
||||
// | | | | |
|
||||
{ 810, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_N69U, 15},
|
||||
{ 940, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_N69U, 15},
|
||||
{1055, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_N69U, 15},
|
||||
|
||||
{ 830, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 9},
|
||||
{ 960, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 9},
|
||||
{1025, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 9},
|
||||
|
||||
{ 840, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
|
||||
{ 940, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
|
||||
{1030, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
|
||||
|
||||
{ 800, 1, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 2, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 3, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 836, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 937, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1090, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
{ 830, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69U, 15},
|
||||
{ 855, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69U, 15},
|
||||
{ 965, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69U, 15},
|
||||
|
||||
{ 820, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 9},
|
||||
{ 835, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 9},
|
||||
{ 955, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 9},
|
||||
|
||||
// GPU fuse rev 8 GPU_SRAM = fuse rev 0 (safe voltage)
|
||||
|
||||
{ 800, 1, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 920, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1030, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
};
|
||||
|
||||
static const struct pmgr_binning_voltage_index_to_offset n69u_cpu_offsets[] = {
|
||||
// voltage index
|
||||
// | fuse revision minimum
|
||||
// | | offset
|
||||
// | | |
|
||||
{CHIPID_CPU_VOLTAGE_912, 0, 25},
|
||||
{CHIPID_CPU_VOLTAGE_1200, 0, 15},
|
||||
{CHIPID_CPU_VOLTAGE_1200_WA, 0, 15},
|
||||
};
|
||||
|
||||
static const struct pmgr_binning_voltage_index_to_offset n69u_gpu_offsets[] = {
|
||||
// voltage index
|
||||
// | fuse revision minimum
|
||||
// | | offset
|
||||
// | | |
|
||||
{CHIPID_GPU_VOLTAGE_550, 0, 20},
|
||||
{CHIPID_GPU_VOLTAGE_723, 0, 30},
|
||||
};
|
||||
|
||||
const struct pmgr_binning_board_id_to_offsets pmgr_binning_board_id_to_offsets_data[] = {
|
||||
// type
|
||||
// | voltage offset array
|
||||
// | | voltage offset array size
|
||||
// | | | chip rev
|
||||
// | | | | board id
|
||||
// | | | | | binning group
|
||||
// | | | | | |
|
||||
{PMGR_BINNING_CPU, n69u_cpu_offsets, sizeof(n69u_cpu_offsets)/sizeof(n69u_cpu_offsets[0]), CHIP_REVISION_C0, N69U_AP_BOARD_ID, PMGR_BINNING_GROUP_ALL},
|
||||
{PMGR_BINNING_CPU, n69u_cpu_offsets, sizeof(n69u_cpu_offsets)/sizeof(n69u_cpu_offsets[0]), CHIP_REVISION_C0, N69U_DEV_BOARD_ID, PMGR_BINNING_GROUP_ALL},
|
||||
{PMGR_BINNING_GPU, n69u_gpu_offsets, sizeof(n69u_gpu_offsets)/sizeof(n69u_gpu_offsets[0]), CHIP_REVISION_C0, N69U_AP_BOARD_ID, PMGR_BINNING_NOTFOUND},
|
||||
{PMGR_BINNING_GPU, n69u_gpu_offsets, sizeof(n69u_gpu_offsets)/sizeof(n69u_gpu_offsets[0]), CHIP_REVISION_C0, N69U_DEV_BOARD_ID, PMGR_BINNING_NOTFOUND},
|
||||
};
|
||||
|
||||
// .voltages = {volAdj0, volAdj1, volAdj2, volAdj3, dvfmMaxAdj, dvmrAdj0, dvmrAdj1, dvmrAdj2}
|
||||
|
||||
const struct pmgr_binning_voltadj_entry pmgr_binning_voltadj_entry_data[] = {
|
||||
//
|
||||
// CPU
|
||||
//
|
||||
{CHIPID_CPU_VOLTAGE_BYPASS, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_SOC_VOLTAGE_SECUREROM, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 0, 0, 0, 0}},
|
||||
|
||||
//
|
||||
// volAdj0
|
||||
// | volAdj1
|
||||
// | | volAdj2
|
||||
// | | | volAdj3
|
||||
// | | | | dvfmMaxAdj
|
||||
// | | | | | dvmrAdj0
|
||||
// | | | | | | dvmrAdj1
|
||||
// | | | | | | | dvmrAdj2
|
||||
// | | | | | | | |
|
||||
// S8000 >= C0 (fuse rev >= 10) | | | | | | | |
|
||||
{CHIPID_CPU_VOLTAGE_396, CHIP_REVISION_B0,10, .voltages = { 0, 9375, 18750, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_396_WA,CHIP_REVISION_B0,10,.voltages = { 0, 9375, 18750, 18750, 40625, 0, 0, 0}},
|
||||
// | | | | | | | |
|
||||
// S8000 >= B0 | | | | | | | |
|
||||
{CHIPID_CPU_VOLTAGE_396, CHIP_REVISION_B0, 0, .voltages = { 0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_600, CHIP_REVISION_B0, 0, .voltages = { 0, 3125, 21875, 21875, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_912, CHIP_REVISION_B0, 0, .voltages = { 0, 3125, 18750, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1200, CHIP_REVISION_B0, 0, .voltages = { 0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1512, CHIP_REVISION_B0, 0, .voltages = { 0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1800, CHIP_REVISION_B0, 0, .voltages = { 28125, 28125, 0, 0, 40625, 12500, 12500, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1848, CHIP_REVISION_B0, 0, .voltages = { 28125, 28125, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_396_WA,CHIP_REVISION_B0,0, .voltages = { 0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1200_WA,CHIP_REVISION_B0,0,.voltages = { 0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1512_WA,CHIP_REVISION_B0,0,.voltages = { 0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
|
||||
// S8000 >= A1
|
||||
{CHIPID_CPU_VOLTAGE_396, CHIP_REVISION_A1, 0, .voltages = {0, 9375, 18750, 25000, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_600, CHIP_REVISION_A1, 0, .voltages = {0, 9375, 18750, 25000, 40625, 3125, 3125, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_912, CHIP_REVISION_A1, 0, .voltages = {0, 6250, 12500, 18750, 40625, 6250, 6250, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1200, CHIP_REVISION_A1, 0, .voltages = {0, 6250, 12500, 18750, 40625, 9375, 9375, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1512, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0, 40625, 18750,15625, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_1800, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0, 40625, 25000,21875, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_1896, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0, 40625, 3125, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1992, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0, 40625, 28125,25000, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_2112, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0, 40625, 3125, 0, 0}},
|
||||
|
||||
// S8000 A0
|
||||
{CHIPID_CPU_VOLTAGE_396, CHIP_REVISION_A0, 0, .voltages = {0, 9375, 18750, 25000, 40620, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_600, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 0, 0, 0, 0}},
|
||||
|
||||
//
|
||||
// SOC
|
||||
//
|
||||
// volAdj0
|
||||
// | volAdj1
|
||||
// | | volAdj2
|
||||
// | | | volAdj3
|
||||
// | | | | N/A
|
||||
// | | | | | N/A
|
||||
// | | | | | | N/A
|
||||
// | | | | | | | N/A
|
||||
// | | | | | | | |
|
||||
{CHIPID_SOC_VOLTAGE_VMIN, CHIP_REVISION_B0, 0, .voltages = {0, 0, 18750, 18750,0,0,0,0}},
|
||||
{CHIPID_SOC_VOLTAGE_VNOM, CHIP_REVISION_B0, 0, .voltages = {0, 0, 12500, 12500,0,0,0,0}},
|
||||
|
||||
{CHIPID_SOC_VOLTAGE_VMIN, CHIP_REVISION_A0, 0, .voltages = {0, 12500, 25000, 25000,0,0,0,0}},
|
||||
{CHIPID_SOC_VOLTAGE_VNOM, CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 12500,0,0,0,0}},
|
||||
{CHIPID_SOC_VOLTAGE_BYPASS,CHIP_REVISION_A0,0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
{CHIPID_SOC_VOLTAGE_SECUREROM,CHIP_REVISION_A0,0,.voltages={0, 0, 0, 0,0,0,0,0}},
|
||||
|
||||
//
|
||||
// GFX
|
||||
//
|
||||
// volAdj0
|
||||
// | volAdj1
|
||||
// | | volAdj2
|
||||
// | | | volAdj3
|
||||
// | | | | N/A
|
||||
// | | | | | N/A
|
||||
// | | | | | | N/A
|
||||
// | | | | | | | N/A
|
||||
// | | | | | | | |
|
||||
{CHIPID_GPU_VOLTAGE_340, CHIP_REVISION_B0, 0, .voltages = {0, 12500, 21875, 25000,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_474, CHIP_REVISION_B0, 0, .voltages = {0, 6250, 15625, 12500,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_550, CHIP_REVISION_B0, 0, .voltages = {0, 0, 9375, 0,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_723, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
|
||||
|
||||
{CHIPID_GPU_VOLTAGE_340, CHIP_REVISION_A1, 0, .voltages = {0, 12500, 25000, 25000,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_474, CHIP_REVISION_A1, 0, .voltages = {0, 6250, 12500, 12500,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_550, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_723, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
};
|
||||
|
||||
|
||||
const uint32_t pmgr_binning_voltage_config_sram_data_size =
|
||||
sizeof(pmgr_binning_voltage_config_sram_data)/sizeof(pmgr_binning_voltage_config_sram_data[0]);
|
||||
const uint32_t pmgr_binning_mode_to_const_data_size = sizeof(pmgr_binning_mode_to_const_data)/sizeof(pmgr_binning_mode_to_const_data[0]);
|
||||
const uint32_t pmgr_binning_voltadj_entry_data_size = sizeof(pmgr_binning_voltadj_entry_data) / sizeof(pmgr_binning_voltadj_entry_data[0]);
|
||||
const uint32_t pmgr_binning_voltage_index_to_config_data_size = sizeof(pmgr_binning_voltage_index_to_config_data)/sizeof(pmgr_binning_voltage_index_to_config_data[0]);
|
||||
const uint32_t pmgr_binning_board_id_to_offsets_data_size = sizeof(pmgr_binning_board_id_to_offsets_data)/sizeof(pmgr_binning_board_id_to_offsets_data[0]);
|
||||
@@ -0,0 +1,309 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
//
|
||||
// Please update test plan version to know what is the reference.
|
||||
//
|
||||
// Elba Test Plan Version 1.6
|
||||
// Elba Tunables Specification Revision 0.46
|
||||
//
|
||||
|
||||
#include <platform/pmgr.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
|
||||
//
|
||||
// Fuses in MINIPMGR are linearly mapped
|
||||
//
|
||||
static const struct pmgr_binning_fuse_to_register minipmgr_fuse_register[] = {
|
||||
// binning_low
|
||||
// | binning_high
|
||||
// | | register_low
|
||||
// | | | register_64bit
|
||||
// | | | | register_address
|
||||
// | | | | |
|
||||
{ 0, 369, 0, 0, AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE0_OFFSET},
|
||||
{ 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
//
|
||||
// Fuses in ACC (UDR) are sparsely mapped
|
||||
//
|
||||
static const struct pmgr_binning_fuse_to_register acc_fuse_register[] = {
|
||||
// binning_low
|
||||
// | binning_high
|
||||
// | | register_low
|
||||
// | | | register_64bit
|
||||
// | | | | register_address
|
||||
// | | | | |
|
||||
{ 0, 2, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST0_EXT2_OFFSET},
|
||||
{ 3, 6, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST0_EXT2_OFFSET},
|
||||
{ 7, 9, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST1_EXT2_OFFSET},
|
||||
{ 10, 13, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST1_EXT2_OFFSET},
|
||||
{ 14, 16, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST2_EXT2_OFFSET},
|
||||
{ 17, 20, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST2_EXT2_OFFSET},
|
||||
{ 21, 23, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST3_EXT2_OFFSET},
|
||||
{ 24, 27, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST3_EXT2_OFFSET},
|
||||
{ 28, 30, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST4_EXT2_OFFSET},
|
||||
{ 31, 34, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST4_EXT2_OFFSET},
|
||||
{ 35, 37, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST5_EXT2_OFFSET},
|
||||
{ 38, 41, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST5_EXT2_OFFSET},
|
||||
{ 42, 44, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST6_EXT2_OFFSET},
|
||||
{ 45, 48, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST6_EXT2_OFFSET},
|
||||
{ 40, 51, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST7_EXT2_OFFSET},
|
||||
{ 52, 55, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST7_EXT2_OFFSET},
|
||||
{ 56, 58, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST8_EXT2_OFFSET},
|
||||
{ 59, 62, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST8_EXT2_OFFSET},
|
||||
{ 112, 114,29, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 115, 119,24, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 120, 127,16, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
const struct pmgr_binning_mode_to_fuse pmgr_binning_mode_to_fuse_data[] = {
|
||||
//
|
||||
// CPU
|
||||
//
|
||||
|
||||
//type
|
||||
//| mode
|
||||
//| | bingroup
|
||||
//| | | low
|
||||
//| | | | high
|
||||
//| | | | | fuse_to_register
|
||||
//| | | | | |
|
||||
{PMGR_BINNING_CPU, 1, PMGR_BINNING_GROUP_ALL, 0, 6, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 2, PMGR_BINNING_GROUP_ALL, 7, 13, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 3, PMGR_BINNING_GROUP_ALL, 14, 20, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 4, PMGR_BINNING_GROUP_ALL, 21, 27, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 5, PMGR_BINNING_GROUP_ALL, 28, 34, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 6, PMGR_BINNING_GROUP_ALL, 35, 41, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 7, PMGR_BINNING_GROUP_ALL, 42, 48, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 8, PMGR_BINNING_GROUP_ALL, 49, 55, acc_fuse_register},
|
||||
|
||||
//
|
||||
// GPU/SOC
|
||||
//
|
||||
|
||||
//type
|
||||
//| mode
|
||||
//| | bingroup
|
||||
//| | | low
|
||||
//| | | | high
|
||||
//| | | | | fuse_to_register
|
||||
//| | | | | |
|
||||
{PMGR_BINNING_GPU, 1, PMGR_BINNING_GROUP_ALL, 238, 244, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 2, PMGR_BINNING_GROUP_ALL, 245, 251, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 3, PMGR_BINNING_GROUP_ALL, 252, 258, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 4, PMGR_BINNING_GROUP_ALL, 259, 265, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 5, PMGR_BINNING_GROUP_ALL, 266, 272, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_SOC, 1, PMGR_BINNING_GROUP_ALL, 224, 230, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_SOC, 2, PMGR_BINNING_GROUP_ALL, 231, 237, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_BASE, 0, PMGR_BINNING_GROUP_ALL, 115, 119, acc_fuse_register},
|
||||
|
||||
{PMGR_BINNING_REV, 0, PMGR_BINNING_GROUP_ALL, 142, 147, minipmgr_fuse_register},
|
||||
|
||||
|
||||
{PMGR_BINNING_END_OF_LIST, 0, PMGR_BINNING_GROUP_ALL, 0, 0, NULL},
|
||||
};
|
||||
|
||||
//
|
||||
// Group-specific entries must come before the corresponding entry with PMGR_BINNING_GROUP_ALL.
|
||||
//
|
||||
const struct pmgr_binning_voltage_index_to_config pmgr_binning_voltage_index_to_config_data[] = {
|
||||
// voltage index
|
||||
// | safe voltage
|
||||
// | | mode
|
||||
// | | | type
|
||||
// | | | | binning group
|
||||
// | | | | | fuse revision minimun
|
||||
// | | | | | |
|
||||
{CHIPID_CPU_VOLTAGE_BYPASS, 606, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_SECUREROM, 606, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_396, 606, 1, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_720, 606, 2, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1080, 720, 3, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1440, 833, 4, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1800, 947, 5, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_2160, 1060, 6, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_2256_1core, 1060, 6, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_2256, 1090, 7, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_2352, 1130, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_2448, 1130, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
// There is only one SOC voltage state on S8001
|
||||
// But Test Plan named MS001 for J99a and MS002 for J127
|
||||
// and this is like S8000 which call MS1 for VMIN and MS2 for VNOM
|
||||
{CHIPID_SOC_VOLTAGE_VMIN, 800, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_SOC_VOLTAGE_VNOM, 900, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
{CHIPID_GPU_VOLTAGE_OFF, 0, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_360, 670, 1, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_520, 800, 2, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_650, 920, 3, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_723, 1030, 4, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_800, 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_804, 1100, 5, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
};
|
||||
|
||||
//
|
||||
// Safe voltage of 0 and binning mode != PMGR_BINNING_MODE_NONE
|
||||
// means data are store in pmgr_binning_mode_to_const_data
|
||||
//
|
||||
const struct pmgr_binning_voltage_config pmgr_binning_voltage_config_sram_data[] = {
|
||||
// safe voltage (0 means lookup data in pmgr_binning_mode_to_const_data)
|
||||
// | mode
|
||||
// | | type
|
||||
// | | |
|
||||
[CHIPID_CPU_VOLTAGE_396] = { 0, 1, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_720] = { 0, 2, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1080] = { 0, 3, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1440] = { 0, 4, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1800] = { 0, 5, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_2160] = { 0, 6, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_2256_1core] = { 0, 7, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_2256] = { 1090, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_2352] = { 1130, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_2448] = { 1130, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
|
||||
[CHIPID_GPU_VOLTAGE_OFF] = { 0, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_360] = { 0, 1, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_520] = { 0, 2, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_650] = { 0, 3, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_723] = { 0, 4, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_800] = { 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_804] = { 0, 5, PMGR_BINNING_GPU_SRAM},
|
||||
|
||||
[CHIPID_VOLTAGE_FIXED] = { 900, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SRAM},
|
||||
};
|
||||
|
||||
//
|
||||
// Group-specific entries must come before the corresponding entry with PMGR_BINNING_GROUP_ALL.
|
||||
//
|
||||
const struct pmgr_binning_mode_to_const pmgr_binning_mode_to_const_data[] = {
|
||||
// Voltage
|
||||
// | Mode
|
||||
// | | Type
|
||||
// | | | Binning group
|
||||
// | | | | fuse revision minimun
|
||||
// | | | | |
|
||||
{ 820, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
|
||||
{ 930, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
|
||||
{ 990, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
|
||||
{1000, 7, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
|
||||
|
||||
{ 835, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
|
||||
{ 885, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
|
||||
{1000, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
|
||||
{1000, 7, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
|
||||
|
||||
{ 800, 1, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 2, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 3, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 833, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 947, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1060, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1060, 7, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
{1100, 5, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 10},
|
||||
|
||||
{ 850, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
|
||||
{ 930, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
|
||||
{1000, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
|
||||
|
||||
{ 800, 1, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 920, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1030, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1100, 5, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
};
|
||||
|
||||
const struct pmgr_binning_board_id_to_offsets pmgr_binning_board_id_to_offsets_data[] = {
|
||||
// type
|
||||
// | voltage offset array
|
||||
// | | voltage offset array size
|
||||
// | | | chip rev
|
||||
// | | | | board id
|
||||
// | | | | | binning group
|
||||
// | | | | | |
|
||||
};
|
||||
|
||||
// .voltages = {volAdj0, volAdj1, volAdj2, volAdj3, dvfmMaxAdj, dvmrAdj0, dvmrAdj1, dvmrAdj2}
|
||||
|
||||
const struct pmgr_binning_voltadj_entry pmgr_binning_voltadj_entry_data[] = {
|
||||
//
|
||||
// CPU
|
||||
//
|
||||
// volAdj0
|
||||
// | volAdj1
|
||||
// | | volAdj2
|
||||
// | | | volAdj3
|
||||
// | | | | dvfmMaxAdj
|
||||
// | | | | | dvmrAdj0
|
||||
// | | | | | | dvmrAdj1
|
||||
// | | | | | | | dvmrAdj2
|
||||
// | | | | | | | |
|
||||
{CHIPID_CPU_VOLTAGE_396 , CHIP_REVISION_B0, 0, .voltages = {0, 9375, 18750, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_720 , CHIP_REVISION_B0, 0, .voltages = {0, 0, 18750, 21875, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1080, CHIP_REVISION_B0, 0, .voltages = {0, 0, 15625, 15625, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1440, CHIP_REVISION_B0, 0, .voltages = {0, 0, 12500, 12500, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1800, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_2160, CHIP_REVISION_B0, 0, .voltages = {21875,0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_2256_1core,CHIP_REVISION_B0,0,.voltages={21875,0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_2256, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_2352, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_2448, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
|
||||
|
||||
{CHIPID_CPU_VOLTAGE_BYPASS,CHIP_REVISION_A0,0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_SOC_VOLTAGE_SECUREROM,CHIP_REVISION_A0,0,.voltages={0, 0, 0, 0, 0, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_396 , CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_720 , CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1080, CHIP_REVISION_A0, 0, .voltages = {0, 3125, 6250, 12500, 40625, 6250, 6250, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1440, CHIP_REVISION_A0, 0, .voltages = {0, 3125, 6250, 12500, 40625, 9375, 9375, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1800, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 18750, 15625, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_2160, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 25000, 21875, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_2256_1core,CHIP_REVISION_A0,0,.voltages={0, 0, 0, 0, 40625, 3125, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_2256, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 25000, 21875, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_2352, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 28125, 25000, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_2448, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 3125, 0, 0}},
|
||||
|
||||
// GFX
|
||||
//
|
||||
// volAdj0
|
||||
// | volAdj1
|
||||
// | | volAdj2
|
||||
// | | | volAdj3
|
||||
// | | | | N/A
|
||||
// | | | | | N/A
|
||||
// | | | | | | N/A
|
||||
// | | | | | | | N/A
|
||||
// | | | | | | | |
|
||||
{CHIPID_GPU_VOLTAGE_360, CHIP_REVISION_B0, 0, .voltages = {0, 3125, 18750, 21875,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_520, CHIP_REVISION_B0, 0, .voltages = {0, 0, 12500, 12500,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_650, CHIP_REVISION_B0, 0, .voltages = {0, 0, 6125, 6125,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_723, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_804, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
|
||||
{CHIPID_GPU_VOLTAGE_360, CHIP_REVISION_A0, 0, .voltages = {0, 12500, 25000, 25000,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_520, CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 12500,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_650, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_723, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_804, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
};
|
||||
|
||||
const uint32_t pmgr_binning_voltage_config_sram_data_size =
|
||||
sizeof(pmgr_binning_voltage_config_sram_data)/sizeof(pmgr_binning_voltage_config_sram_data[0]);
|
||||
const uint32_t pmgr_binning_mode_to_const_data_size = sizeof(pmgr_binning_mode_to_const_data)/sizeof(pmgr_binning_mode_to_const_data[0]);
|
||||
const uint32_t pmgr_binning_voltadj_entry_data_size = sizeof(pmgr_binning_voltadj_entry_data) / sizeof(pmgr_binning_voltadj_entry_data[0]);
|
||||
const uint32_t pmgr_binning_voltage_index_to_config_data_size = sizeof(pmgr_binning_voltage_index_to_config_data)/sizeof(pmgr_binning_voltage_index_to_config_data[0]);
|
||||
const uint32_t pmgr_binning_board_id_to_offsets_data_size = sizeof(pmgr_binning_board_id_to_offsets_data)/sizeof(pmgr_binning_board_id_to_offsets_data[0]);
|
||||
@@ -0,0 +1,378 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
//
|
||||
// Please update test plan version to know what is the reference.
|
||||
//
|
||||
// Malta Test Plan Version 1.6
|
||||
// Malta Tunables Specification Revision 0.47 (for volt_adj)
|
||||
//
|
||||
|
||||
#include <platform/pmgr.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
|
||||
//
|
||||
// Fuses in MINIPMGR are linearly mapped
|
||||
//
|
||||
static const struct pmgr_binning_fuse_to_register minipmgr_fuse_register[] = {
|
||||
// binning_low
|
||||
// | binning_high
|
||||
// | | register_low
|
||||
// | | | register_64bit
|
||||
// | | | | register_address
|
||||
// | | | | |
|
||||
{ 0, 369, 0, 0, AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE0_OFFSET},
|
||||
{ 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
//
|
||||
// Fuses in ACC (UDR) are sparsely mapped
|
||||
//
|
||||
static const struct pmgr_binning_fuse_to_register acc_fuse_register[] = {
|
||||
// binning_low
|
||||
// | binning_high
|
||||
// | | register_low
|
||||
// | | | register_64bit
|
||||
// | | | | register_address
|
||||
// | | | | |
|
||||
{ 0, 2, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST0_EXT2_OFFSET},
|
||||
{ 3, 6, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST0_EXT2_OFFSET},
|
||||
{ 7, 9, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST1_EXT2_OFFSET},
|
||||
{ 10, 13, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST1_EXT2_OFFSET},
|
||||
{ 14, 16, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST2_EXT2_OFFSET},
|
||||
{ 17, 20, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST2_EXT2_OFFSET},
|
||||
{ 21, 23, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST3_EXT2_OFFSET},
|
||||
{ 24, 27, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST3_EXT2_OFFSET},
|
||||
{ 28, 30, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST4_EXT2_OFFSET},
|
||||
{ 31, 34, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST4_EXT2_OFFSET},
|
||||
{ 35, 37, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST5_EXT2_OFFSET},
|
||||
{ 38, 41, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST5_EXT2_OFFSET},
|
||||
{ 42, 44, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST6_EXT2_OFFSET},
|
||||
{ 45, 48, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST6_EXT2_OFFSET},
|
||||
{ 49, 51, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST7_EXT2_OFFSET},
|
||||
{ 52, 55, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST7_EXT2_OFFSET},
|
||||
{ 56, 58, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST8_EXT2_OFFSET},
|
||||
{ 59, 62, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST8_EXT2_OFFSET},
|
||||
{ 112, 114,29, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 115, 119,24, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 120, 127,16, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
|
||||
{ 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
//
|
||||
// Group-specific entries must come before the corresponding entry with PMGR_BINNING_GROUP_ALL.
|
||||
//
|
||||
|
||||
const struct pmgr_binning_mode_to_fuse pmgr_binning_mode_to_fuse_data[] = {
|
||||
//
|
||||
// CPU
|
||||
//
|
||||
|
||||
//type
|
||||
//| mode
|
||||
//| | bingroup
|
||||
//| | | low
|
||||
//| | | | high
|
||||
//| | | | | fuse_to_register
|
||||
//| | | | | |
|
||||
{PMGR_BINNING_CPU, 1, PMGR_BINNING_GROUP_ALL, 0, 6, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 2, PMGR_BINNING_GROUP_ALL, 7, 13, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 3, PMGR_BINNING_GROUP_ALL, 14, 20, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 4, PMGR_BINNING_GROUP_ALL, 21, 27, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 5, PMGR_BINNING_GROUP_ALL, 28, 34, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 6, PMGR_BINNING_GROUP_ALL, 35, 41, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 7, PMGR_BINNING_GROUP_ALL, 42, 48, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 8, PMGR_BINNING_GROUP_ALL, 49, 55, acc_fuse_register},
|
||||
{PMGR_BINNING_CPU, 9, PMGR_BINNING_GROUP_ALL, 56, 62, acc_fuse_register},
|
||||
|
||||
//
|
||||
// GPU/SOC
|
||||
//
|
||||
|
||||
//type
|
||||
//| mode
|
||||
//| | bingroup
|
||||
//| | | low
|
||||
//| | | | high
|
||||
//| | | | | fuse_to_register
|
||||
//| | | | | |
|
||||
{PMGR_BINNING_GPU, 1, PMGR_BINNING_GROUP_ALL, 238, 244, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 2, PMGR_BINNING_GROUP_ALL, 245, 251, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 3, PMGR_BINNING_GROUP_ALL, 252, 258, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 4, PMGR_BINNING_GROUP_ALL, 259, 265, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_GPU, 5, PMGR_BINNING_GROUP_ALL, 266, 272, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_SOC, 1, PMGR_BINNING_GROUP_ALL, 224, 230, minipmgr_fuse_register},
|
||||
{PMGR_BINNING_SOC, 2, PMGR_BINNING_GROUP_ALL, 231, 237, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_BASE, 0, PMGR_BINNING_GROUP_ALL, 115, 119, acc_fuse_register},
|
||||
|
||||
{PMGR_BINNING_REV, 0, PMGR_BINNING_GROUP_ALL, 142, 147, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_GROUP, 0, PMGR_BINNING_GROUP_ALL, 318, 319, minipmgr_fuse_register},
|
||||
|
||||
{PMGR_BINNING_END_OF_LIST, 0, PMGR_BINNING_GROUP_ALL, 0, 0, NULL},
|
||||
};
|
||||
|
||||
//
|
||||
// Group-specific entries must come before the corresponding entry with PMGR_BINNING_GROUP_ALL.
|
||||
//
|
||||
const struct pmgr_binning_voltage_index_to_config pmgr_binning_voltage_index_to_config_data[] = {
|
||||
// voltage index
|
||||
// | safe voltage
|
||||
// | | mode
|
||||
// | | | type
|
||||
// | | | | binning group
|
||||
// | | | | | fuse revision minimun
|
||||
// | | | | | |
|
||||
{CHIPID_CPU_VOLTAGE_BYPASS, 606, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_SECUREROM, 606, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_396, 606, 1, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_600, 606, 2, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_912, 667, 3, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1200, 757, 4, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1512, 856, 5, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1800, 947, 6, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1848, 977, 6, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
// SEG-characterization
|
||||
{CHIPID_CPU_VOLTAGE_1896, 977, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_1992, 1007, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_CPU_VOLTAGE_2112, 1045, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
{CHIPID_SOC_VOLTAGE_BYPASS, 670, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_SOC_VOLTAGE_SECUREROM, 670, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_SOC_VOLTAGE_VMIN, 670, 1, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_SOC_VOLTAGE_VNOM, 800, 2, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
{CHIPID_GPU_VOLTAGE_OFF, 0, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_340, 670, 1, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_474, 800, 2, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_550, 920, 3, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_723, 1030, 4, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_804, 1080, 5, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
// SEG-characterization
|
||||
{CHIPID_GPU_VOLTAGE_850, 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{CHIPID_GPU_VOLTAGE_900, 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
|
||||
};
|
||||
|
||||
//
|
||||
// Safe voltage of 0 and binning mode != PMGR_BINNING_MODE_NONE
|
||||
// means data are store in pmgr_binning_mode_to_const_data
|
||||
//
|
||||
const struct pmgr_binning_voltage_config pmgr_binning_voltage_config_sram_data[] = {
|
||||
// safe voltage (0 means lookup data in pmgr_binning_mode_to_const_data)
|
||||
// | mode
|
||||
// | | type
|
||||
// | | |
|
||||
[CHIPID_CPU_VOLTAGE_BYPASS] = { 800, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_SECUREROM] = { 800, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_396] = { 0, 1, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_600] = { 0, 2, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_912] = { 0, 3, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1200] = { 0, 4, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1512] = { 0, 5, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1800] = { 0, 6, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1848] = { 0, 6, PMGR_BINNING_CPU_SRAM},
|
||||
// SEG-characterization
|
||||
[CHIPID_CPU_VOLTAGE_1896] = { 977, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_1992] = {1007, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
[CHIPID_CPU_VOLTAGE_2112] = {1045, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
|
||||
|
||||
[CHIPID_GPU_VOLTAGE_OFF] = { 0, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_340] = { 0, 1, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_474] = { 0, 2, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_550] = { 0, 3, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_723] = { 0, 4, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_804] = { 0, 5, PMGR_BINNING_GPU_SRAM},
|
||||
// SEG-characterization
|
||||
[CHIPID_GPU_VOLTAGE_850] = {1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
[CHIPID_GPU_VOLTAGE_900] = {1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
|
||||
|
||||
[CHIPID_VOLTAGE_FIXED] = { 900, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SRAM},
|
||||
};
|
||||
|
||||
|
||||
//
|
||||
// SRAM has 3 "safe voltage" one from fuse rev 0,1,2, one for fuse rev 3,4 and one from fuse rev 5.
|
||||
// Group-specific entries must come before the corresponding entry with PMGR_BINNING_GROUP_ALL.
|
||||
//
|
||||
const struct pmgr_binning_mode_to_const pmgr_binning_mode_to_const_data[] = {
|
||||
// voltage
|
||||
// | mode
|
||||
// | | type
|
||||
// | | | binning group
|
||||
// | | | | fuse revision minimun
|
||||
// | | | | |
|
||||
{ 800, 1, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
{ 800, 2, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
{ 800, 3, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
{ 800, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
{ 840, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
{ 915, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
|
||||
{ 800, 1, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
{ 800, 2, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
{ 800, 3, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
{ 840, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
{ 940, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
{ 960, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
|
||||
{ 800, 1, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 2, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 3, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 852, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 947, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 915, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1060, 7, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1130, 8, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
|
||||
// GPU - N69
|
||||
{ 865, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 5},
|
||||
{ 895, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 5},
|
||||
{1005, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 5},
|
||||
|
||||
{ 865, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 3},
|
||||
{ 895, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 3},
|
||||
{1005, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 3},
|
||||
|
||||
{ 865, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 0},
|
||||
{ 895, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 0},
|
||||
{1005, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_N69, 0},
|
||||
|
||||
// GPU - ALL
|
||||
{ 800, 1, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
{ 840, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
{ 875, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
{ 985, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 5},
|
||||
|
||||
{ 800, 1, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
{ 800, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
{ 920, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
{1025, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 3},
|
||||
|
||||
{ 800, 1, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 800, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{ 920, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1030, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
{1080, 5, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
|
||||
};
|
||||
|
||||
static const struct pmgr_binning_voltage_index_to_offset n69_cpu_offsets[] = {
|
||||
// voltage index
|
||||
// | fuse revision minimum
|
||||
// | | offset
|
||||
// | | |
|
||||
{CHIPID_CPU_VOLTAGE_1200, 0, 15},
|
||||
};
|
||||
|
||||
const struct pmgr_binning_board_id_to_offsets pmgr_binning_board_id_to_offsets_data[] = {
|
||||
// type
|
||||
// | voltage offset array
|
||||
// | | voltage offset array size
|
||||
// | | | chip rev
|
||||
// | | | | board id
|
||||
// | | | | | binning group
|
||||
// | | | | | |
|
||||
{PMGR_BINNING_CPU, n69_cpu_offsets, sizeof(n69_cpu_offsets)/sizeof(n69_cpu_offsets[0]), CHIP_REVISION_A1, N69_AP_BOARD_ID, PMGR_BINNING_GROUP_ALL},
|
||||
{PMGR_BINNING_CPU, n69_cpu_offsets, sizeof(n69_cpu_offsets)/sizeof(n69_cpu_offsets[0]), CHIP_REVISION_A1, N69_DEV_BOARD_ID, PMGR_BINNING_GROUP_ALL},
|
||||
};
|
||||
|
||||
// .voltages = {volAdj0, volAdj1, volAdj2, volAdj3, dvfmMaxAdj, dvmrAdj0, dvmrAdj1, dvmrAdj2}
|
||||
|
||||
const struct pmgr_binning_voltadj_entry pmgr_binning_voltadj_entry_data[] = {
|
||||
//
|
||||
// CPU
|
||||
//
|
||||
// volAdj0
|
||||
// | volAdj1
|
||||
// | | volAdj2
|
||||
// | | | volAdj3
|
||||
// | | | | dvfmMaxAdj
|
||||
// | | | | | dvmrAdj0
|
||||
// | | | | | | dvmrAdj1
|
||||
// | | | | | | | dvmrAdj2
|
||||
// | | | | | | | |
|
||||
{CHIPID_CPU_VOLTAGE_396, CHIP_REVISION_A1, 6, .voltages = {0, 9375, 18750, 18750, 40625, 0, 0, 0}},
|
||||
|
||||
{CHIPID_CPU_VOLTAGE_396, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_600, CHIP_REVISION_A1, 0, .voltages = {0, 0, 18750, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_912, CHIP_REVISION_A1, 0, .voltages = {0, 0, 18750, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1200, CHIP_REVISION_A1, 0, .voltages = {0, 0, 15625, 15625, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1512, CHIP_REVISION_A1, 0, .voltages = {0, 0, 6250, 6250, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1800, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1848, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
|
||||
|
||||
{CHIPID_CPU_VOLTAGE_BYPASS,CHIP_REVISION_A0,0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||||
{CHIPID_SOC_VOLTAGE_SECUREROM,CHIP_REVISION_A0,0,.voltages={0, 0, 0, 0, 0, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_396, CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_600, CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 18750, 40625, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_912, CHIP_REVISION_A0, 0, .voltages = {0, 3125, 6250, 12500, 40625, 3125, 3125, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1200, CHIP_REVISION_A0, 0, .voltages = {0, 3125, 6250, 12500, 40625, 6250, 6250, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_1512, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 15625,12500, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_1800, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 18750,15625, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_1848, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 18750,15625, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_1896, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 18750,15625, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_1992, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 21870,18750, 3125}},
|
||||
{CHIPID_CPU_VOLTAGE_2112, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 25000,21875, 3125}},
|
||||
|
||||
//
|
||||
// SOC
|
||||
//
|
||||
// volAdj0
|
||||
// | volAdj1
|
||||
// | | volAdj2
|
||||
// | | | volAdj3
|
||||
// | | | | N/A
|
||||
// | | | | | N/A
|
||||
// | | | | | | N/A
|
||||
// | | | | | | | N/A
|
||||
// | | | | | | | |
|
||||
{CHIPID_SOC_VOLTAGE_VMIN, CHIP_REVISION_A1, 0, .voltages = {0, 3125, 15625, 18750,0,0,0,0}},
|
||||
{CHIPID_SOC_VOLTAGE_VNOM, CHIP_REVISION_A1, 0, .voltages = {0, 0, 12500, 12500,0,0,0,0}},
|
||||
|
||||
{CHIPID_SOC_VOLTAGE_VMIN, CHIP_REVISION_A0, 0, .voltages = {0, 12500, 25000, 25000,0,0,0,0}},
|
||||
{CHIPID_SOC_VOLTAGE_VNOM, CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 12500,0,0,0,0}},
|
||||
{CHIPID_SOC_VOLTAGE_BYPASS,CHIP_REVISION_A0, 0, .voltages ={0, 0, 0, 0,0,0,0,0}},
|
||||
{CHIPID_SOC_VOLTAGE_SECUREROM,CHIP_REVISION_A0,0,.voltages={0, 0, 0, 0,0,0,0,0}},
|
||||
|
||||
//
|
||||
// GFX
|
||||
//
|
||||
// volAdj0
|
||||
// | volAdj1
|
||||
// | | volAdj2
|
||||
// | | | volAdj3
|
||||
// | | | | N/A
|
||||
// | | | | | N/A
|
||||
// | | | | | | N/A
|
||||
// | | | | | | | N/A
|
||||
// | | | | | | | |
|
||||
{CHIPID_GPU_VOLTAGE_340, CHIP_REVISION_A1, 0, .voltages = {0, 3125, 15625, 18750,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_474, CHIP_REVISION_A1, 0, .voltages = {0, 0, 12500, 12500,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_550, CHIP_REVISION_A1, 0, .voltages = {0, 0, 3125, 3125,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_723, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_804, CHIP_REVISION_A1, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
|
||||
{CHIPID_GPU_VOLTAGE_340, CHIP_REVISION_A0, 0, .voltages = {0, 12500, 25000, 25000,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_474, CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 12500,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_550, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
{CHIPID_GPU_VOLTAGE_723, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||||
};
|
||||
|
||||
|
||||
const uint32_t pmgr_binning_voltage_config_sram_data_size =
|
||||
sizeof(pmgr_binning_voltage_config_sram_data)/sizeof(pmgr_binning_voltage_config_sram_data[0]);
|
||||
const uint32_t pmgr_binning_mode_to_const_data_size = sizeof(pmgr_binning_mode_to_const_data)/sizeof(pmgr_binning_mode_to_const_data[0]);
|
||||
const uint32_t pmgr_binning_voltadj_entry_data_size = sizeof(pmgr_binning_voltadj_entry_data) / sizeof(pmgr_binning_voltadj_entry_data[0]);
|
||||
const uint32_t pmgr_binning_voltage_index_to_config_data_size = sizeof(pmgr_binning_voltage_index_to_config_data)/sizeof(pmgr_binning_voltage_index_to_config_data[0]);
|
||||
const uint32_t pmgr_binning_board_id_to_offsets_data_size = sizeof(pmgr_binning_board_id_to_offsets_data)/sizeof(pmgr_binning_board_id_to_offsets_data[0]);
|
||||
@@ -0,0 +1,42 @@
|
||||
# Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_PLATFORM_CHIPID=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/chipid.o \
|
||||
$(LOCAL_DIR)/operating_point.o \
|
||||
$(LOCAL_DIR)/dvfmperf.o \
|
||||
$(LOCAL_DIR)/tunables_pmgr_product.o
|
||||
|
||||
ifeq ($(SUB_PLATFORM),s8000)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/tunables_pmgr_s8000.o \
|
||||
$(LOCAL_DIR)/pmgr_binning_s8000.o
|
||||
endif
|
||||
|
||||
ifeq ($(SUB_PLATFORM),s8001)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/tunables_pmgr_s8001.o \
|
||||
$(LOCAL_DIR)/pmgr_binning_s8001.o
|
||||
|
||||
ifeq ($(TARGET),ipad6b)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/tunables_pmgr_s8001_ipad6b.o
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(SUB_PLATFORM),s8003)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/tunables_pmgr_s8003.o \
|
||||
$(LOCAL_DIR)/pmgr_binning_s8003.o
|
||||
endif
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* This file contains Tunables for s8001 products without product tunables */
|
||||
|
||||
#include <platform/tunables.h>
|
||||
|
||||
const struct tunable_chip_struct tunables_pmgr_product[] __attribute__((weak)) = {
|
||||
{0, 0, NULL, NULL, 0}
|
||||
};
|
||||
@@ -0,0 +1,323 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* This file contains Tunables for s8000 */
|
||||
|
||||
#include <platform/tunables.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <soc/module/address_map.h>
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_ALL ****************************************/
|
||||
// <rdar://problem/21406702> Maui: Add PMGR_PLL_PCIE_CFG.LOCK_MODE tunable to SPDS
|
||||
// <rdar://problem/21347912> Add support for product / platform specific tunables
|
||||
// <rdar://problem/20536609> Add GFX TVM tunables in PDF tunables to SPDS tunables
|
||||
// <rdar://problem/20537375> Add SOC TVM tunables in PDF tunables to SPDS tunables
|
||||
#define SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_EXTRA \
|
||||
{ /*! PLL0_CFG */ 0x00004, sizeof(uint32_t), 0xc0000000u, 0x40000000u}, \
|
||||
{ /*! PLL1_CFG */ 0x04004, sizeof(uint32_t), 0xc0000000u, 0x40000000u}, \
|
||||
{ /*! PLL_PCIE_CFG */ 0x18004, sizeof(uint32_t), 0xc0000000u, 0x40000000u}, \
|
||||
{ /*! VOLMAN_SOC_DELAY */ 0xa001c, sizeof(uint32_t), 0xfffffcffu, 0xbb81642fu}, \
|
||||
{ /*! VOLMAN_GFX_SRAM_DELAY */ 0xa0020, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_CPU_SRAM_DELAY */ 0xa0024, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_GFX_DELAY */ 0xa0028, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_CPU_DELAY */ 0xa002c, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! SOC_TVM_THRESH0 */ 0xc8004, sizeof(uint32_t), 0x000001ffu, 0x00000000u}, \
|
||||
{ /*! SOC_TVM_THRESH1 */ 0xc8008, sizeof(uint32_t), 0x000001ffu, 0x00000019u}, \
|
||||
{ /*! SOC_TVM_THRESH2 */ 0xc800c, sizeof(uint32_t), 0x000001ffu, 0x00000032u}, \
|
||||
{ /*! SOC_TVM_TEMP0_CFG */ 0xc8010, sizeof(uint32_t), 0x01ff01ffu, 0x001c01f4u}, \
|
||||
{ /*! SOC_TVM_TEMP1_CFG */ 0xc8014, sizeof(uint32_t), 0x01ff01ffu, 0x001c01f4u}, \
|
||||
{ /*! SOC_TVM_TEMP2_CFG */ 0xc8018, sizeof(uint32_t), 0x01ff01ffu, 0x001c01f4u}, \
|
||||
{ /*! GFX_TVM_CTL */ 0xc8200, sizeof(uint32_t), 0x00000f00u, 0x00000f00u}, \
|
||||
{ /*! GFX_TVM_THRESH0 */ 0xc8204, sizeof(uint32_t), 0x000001ffu, 0x00000000u}, \
|
||||
{ /*! GFX_TVM_THRESH1 */ 0xc8208, sizeof(uint32_t), 0x000001ffu, 0x00000019u}, \
|
||||
{ /*! GFX_TVM_THRESH2 */ 0xc820c, sizeof(uint32_t), 0x000001ffu, 0x00000032u}, \
|
||||
{ /*! GFX_TVM_TEMP0_CFG */ 0xc8210, sizeof(uint32_t), 0x01ff01ffu, 0x001501f9u}, \
|
||||
{ /*! GFX_TVM_TEMP1_CFG */ 0xc8214, sizeof(uint32_t), 0x01ff01ffu, 0x001501f9u}, \
|
||||
{ /*! GFX_TVM_TEMP2_CFG */ 0xc8218, sizeof(uint32_t), 0x01ff01ffu, 0x001501f9u}
|
||||
|
||||
// <rdar://problem/20544302> Add CPU TVM tunables in tunables PDF to SPDS tunables
|
||||
// <rdar://problem/20545027> Add DVMR tunables in tunables PDF to SPDS tunables
|
||||
#define ACC_DEFAULT_TUNABLES_S8000_EXTRA \
|
||||
/* Configure temperature ranges and measurement offsets for DVFM/DVTM */ \
|
||||
/* temp_thread0 0x8 temp_thresh1 0x21 temp_offset0 0 temp_offset1 0 */ \
|
||||
{ /* ACC_PWRCTL_DVFM_CFG */ 0x220040, sizeof(uint32_t), 0x0fffffffu, 0x00001088u}, \
|
||||
/* temp_thresh2 0x3a temp_offset2 0 */ \
|
||||
{ /* ACC_PWRCTL_DVFM_CFG1 */ 0x220058, sizeof(uint32_t), 0x001fffffu, 0x0000003au}, \
|
||||
{ /* ACC_PWRCTL_DVMR_SCR */ 0x2206b8, sizeof(uint64_t), 0x00000fffu, 0x000000421}
|
||||
|
||||
#define SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_EXTRA \
|
||||
/* <rdar://problem/20868785> Ensure that LPO OFF_MODE is set appropriately */ \
|
||||
{ /*! MINIPMGR_LPO_CFG */ 0x00004, sizeof(uint32_t), 0xc0000000u, 0x80000000u }
|
||||
|
||||
// <rdar://problem/17755256> SwitchFabric Hash lock bit is not set
|
||||
#define SWITCHFABRIC_DEFAULT_TUNABLES_S8000_EXTRA \
|
||||
{ /*! SWITCHFABRIC_REGS_AMAP_LOCK */ 0x00000, sizeof(uint32_t), 0x00000001u, 0x00000001u }
|
||||
/**************************************** END CHIP_REVISION_ALL ****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_C0 ****************************************/
|
||||
#include <soc/s8000/c0/tunable/minipmgr.h>
|
||||
#include <soc/s8000/c0/tunable/pmgr.h>
|
||||
#include <soc/s8000/c0/tunable/acc.h>
|
||||
#include <soc/s8000/c0/tunable/sbasyncfifo_widgets.h>
|
||||
#include <soc/s8000/c0/tunable/socbusmux.h>
|
||||
#include <soc/s8000/c0/tunable/switchfabric.h>
|
||||
#include <soc/s8000/c0/tunable/pms_csr.h>
|
||||
#include <soc/s8000/c0/tunable/afc_aiu_sb.h>
|
||||
#include <soc/s8000/c0/tunable/sb_glue.h>
|
||||
#include <soc/s8000/c0/tunable/misc1.h>
|
||||
#include <soc/s8000/c0/tunable/cp_com.h>
|
||||
|
||||
static const struct tunable_struct pmsasyncfifo_tunable_c0[] = {
|
||||
SOUTH_BRIDGE_PMSASYNCFIFO_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_c0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct minipmgr_tunable_c0[] = {
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct64 acc_tunable_c0[] = {
|
||||
ACC_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
ACC_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct socbusmux_tunable_c0[] = {
|
||||
SOCBUSMUX_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct switchfabric_tunable_c0[] = {
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct pms_csr_tunable_c0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMS_CSR_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct sb_glue_tunable_c0[] = {
|
||||
SOUTH_BRIDGE_DYNAMIC_CLK_GATING_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct afc_aiu_sb_tunable_c0[] = {
|
||||
SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct asio_misc1_tunable_c0[] = {
|
||||
SOUTH_BRIDGE_ASIO_MISC1_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp_com_tunable_c0[] = {
|
||||
CP_CP_COM_DEFAULT_TUNABLES_S8000_C0
|
||||
};
|
||||
/***************************************** END CHIP_REVISION_C0 *****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_B0 ****************************************/
|
||||
#include <soc/s8000/b0/tunable/minipmgr.h>
|
||||
#include <soc/s8000/b0/tunable/pmgr.h>
|
||||
#include <soc/s8000/b0/tunable/acc.h>
|
||||
#include <soc/s8000/b0/tunable/sbasyncfifo_widgets.h>
|
||||
#include <soc/s8000/b0/tunable/socbusmux.h>
|
||||
#include <soc/s8000/b0/tunable/switchfabric.h>
|
||||
#include <soc/s8000/b0/tunable/pms_csr.h>
|
||||
#include <soc/s8000/b0/tunable/afc_aiu_sb.h>
|
||||
#include <soc/s8000/b0/tunable/sb_glue.h>
|
||||
#include <soc/s8000/b0/tunable/misc1.h>
|
||||
#include <soc/s8000/b0/tunable/cp_com.h>
|
||||
|
||||
#define SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_B0_EXTRA \
|
||||
/* <rdar://problem/19929273> Maui MCC EMA setting change to 3% */ \
|
||||
{ /*! EMA_FIXED_SOC1 */ 0xac004, sizeof(uint32_t), 0x07fff000u, 0x030d1000u}
|
||||
|
||||
static const struct tunable_struct pmsasyncfifo_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_PMSASYNCFIFO_DEFAULT_TUNABLES_S8000_B0,
|
||||
};
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_B0_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct minipmgr_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct64 acc_tunable_b0[] = {
|
||||
ACC_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
ACC_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct socbusmux_tunable_b0[] = {
|
||||
SOCBUSMUX_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct switchfabric_tunable_b0[] = {
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct pms_csr_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMS_CSR_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct sb_glue_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_DYNAMIC_CLK_GATING_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct afc_aiu_sb_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct asio_misc1_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_ASIO_MISC1_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp_com_tunable_b0[] = {
|
||||
CP_CP_COM_DEFAULT_TUNABLES_S8000_B0
|
||||
};
|
||||
/***************************************** END CHIP_REVISION_B0 *****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_A1 ****************************************/
|
||||
#include <soc/s8000/a1/tunable/minipmgr.h>
|
||||
#include <soc/s8000/a1/tunable/pmgr.h>
|
||||
#include <soc/s8000/a1/tunable/acc.h>
|
||||
#include <soc/s8000/a1/tunable/sbasyncfifo_widgets.h>
|
||||
#include <soc/s8000/a1/tunable/socbusmux.h>
|
||||
#include <soc/s8000/a1/tunable/switchfabric.h>
|
||||
#include <soc/s8000/a1/tunable/pms_csr.h>
|
||||
#include <soc/s8000/a1/tunable/afc_aiu_sb.h>
|
||||
#include <soc/s8000/a1/tunable/sb_glue.h>
|
||||
#include <soc/s8000/a1/tunable/misc1.h>
|
||||
#include <soc/s8000/a1/tunable/cp_com.h>
|
||||
|
||||
#define SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_A1_EXTRA \
|
||||
/* <rdar://problem/18700978> iBoot to set M$ EMAA register to new value to increase Maui Yield */ \
|
||||
{ /*! EMA_FIXED_SOC1 */ 0xac004, sizeof(uint32_t), 0x07fff000u, 0x032d1000u}
|
||||
|
||||
// <rdar://problem/20545899> Maui: Add PMGR THERMAL tunables to SPDS for Maui A1
|
||||
#define SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_A1_THERMAL_EXTRA \
|
||||
{ /*! PMGR_THERMAL_0_PIECE0 */ 0xc0028, sizeof(uint32_t), 0x7ffffu, 0x7943bu }, \
|
||||
{ /*! PMGR_THERMAL_0_PIECE1 */ 0xc002c, sizeof(uint32_t), 0xffc7ffffu, 0x5007d02fu }, \
|
||||
{ /*! PMGR_THERMAL_0_PIECE2 */ 0xc0030, sizeof(uint32_t), 0xffc7ffffu, 0x95c02426u }, \
|
||||
{ /*! PMGR_THERMAL_1_PIECE0 */ 0xc0128, sizeof(uint32_t), 0x7ffffu, 0x7943bu }, \
|
||||
{ /*! PMGR_THERMAL_1_PIECE1 */ 0xc012c, sizeof(uint32_t), 0xffc7ffffu, 0x5007d02fu }, \
|
||||
{ /*! PMGR_THERMAL_1_PIECE2 */ 0xc0130, sizeof(uint32_t), 0xffc7ffffu, 0x95c02426u }, \
|
||||
{ /*! PMGR_THERMAL_2_PIECE0 */ 0xc0228, sizeof(uint32_t), 0x7ffffu, 0x7943bu }, \
|
||||
{ /*! PMGR_THERMAL_2_PIECE1 */ 0xc022c, sizeof(uint32_t), 0xffc7ffffu, 0x5007d02fu }, \
|
||||
{ /*! PMGR_THERMAL_2_PIECE2 */ 0xc0230, sizeof(uint32_t), 0xffc7ffffu, 0x95c02426u }
|
||||
|
||||
#define SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_A1_EXTRA \
|
||||
/* <rdar://problem/19300047> 19300047 */ \
|
||||
{ /*! MINIPMGR_LPO_CFG */ 0x00004, sizeof(uint32_t), 0x30000000u, 0x00000000u }
|
||||
|
||||
static const struct tunable_struct pmsasyncfifo_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_PMSASYNCFIFO_DEFAULT_TUNABLES_S8000_A1,
|
||||
};
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_A1_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_A1_THERMAL_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct minipmgr_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_A1_EXTRA,
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct64 acc_tunable_a1[] = {
|
||||
ACC_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
ACC_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct socbusmux_tunable_a1[] = {
|
||||
SOCBUSMUX_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct switchfabric_tunable_a1[] = {
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8000_EXTRA,
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct pms_csr_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_PMS_PMS_CSR_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct sb_glue_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_DYNAMIC_CLK_GATING_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct afc_aiu_sb_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct asio_misc1_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_ASIO_MISC1_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp_com_tunable_a1[] = {
|
||||
CP_CP_COM_DEFAULT_TUNABLES_S8000_A1
|
||||
};
|
||||
/***************************************** END CHIP_REVISION_A1 *****************************************/
|
||||
|
||||
// For each chip, highest revision must come first.
|
||||
// Notice reconfig == false for minipmgr, since it's an AOP.
|
||||
const struct tunable_chip_struct tunables_pmgr[] = {
|
||||
// C0
|
||||
{CHIP_REVISION_C0, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8000_C0, pmgr_tunable_c0, NULL, true},
|
||||
{CHIP_REVISION_C0, SOUTH_BRIDGE_AOP_MINIPMGR_PADDR_S8000_C0, minipmgr_tunable_c0, NULL, false},
|
||||
{CHIP_REVISION_C0, ACC_PADDR_S8000_C0, NULL, acc_tunable_c0, true},
|
||||
{CHIP_REVISION_C0, SOUTH_BRIDGE_PMSASYNCFIFO_PADDR_S8000_C0, pmsasyncfifo_tunable_c0, NULL, true},
|
||||
{CHIP_REVISION_C0, SOCBUSMUX_PADDR_S8000_C0, socbusmux_tunable_c0, NULL, true},
|
||||
{CHIP_REVISION_C0, SWITCHFABRIC_PADDR_S8000_C0, switchfabric_tunable_c0, NULL, true},
|
||||
{CHIP_REVISION_C0, SOUTH_BRIDGE_PMS_PMS_CSR_PADDR_S8000_C0, pms_csr_tunable_c0, NULL, true},
|
||||
{CHIP_REVISION_C0, SOUTH_BRIDGE_DYNAMIC_CLK_GATING_PADDR_S8000_C0, sb_glue_tunable_c0, NULL, true},
|
||||
{CHIP_REVISION_C0, SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_PADDR_S8000_C0, afc_aiu_sb_tunable_c0, NULL, true},
|
||||
{CHIP_REVISION_C0, SOUTH_BRIDGE_ASIO_MISC1_PADDR_S8000_C0, asio_misc1_tunable_c0, NULL, true},
|
||||
{CHIP_REVISION_C0, CP_CP_COM_PADDR_S8000_C0, cp_com_tunable_c0, NULL, true},
|
||||
|
||||
// B0
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8000_B0, pmgr_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_AOP_MINIPMGR_PADDR_S8000_B0, minipmgr_tunable_b0, NULL, false},
|
||||
{CHIP_REVISION_B0, ACC_PADDR_S8000_B0, NULL, acc_tunable_b0, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_PMSASYNCFIFO_PADDR_S8000_B0, pmsasyncfifo_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOCBUSMUX_PADDR_S8000_B0, socbusmux_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SWITCHFABRIC_PADDR_S8000_B0, switchfabric_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_PMS_PMS_CSR_PADDR_S8000_B0, pms_csr_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_DYNAMIC_CLK_GATING_PADDR_S8000_B0, sb_glue_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_PADDR_S8000_B0, afc_aiu_sb_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_ASIO_MISC1_PADDR_S8000_B0, asio_misc1_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, CP_CP_COM_PADDR_S8000_B0, cp_com_tunable_b0, NULL, true},
|
||||
|
||||
// A1
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8000_A1, pmgr_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_AOP_MINIPMGR_PADDR_S8000_A1, minipmgr_tunable_a1, NULL, false},
|
||||
{CHIP_REVISION_A1, ACC_PADDR_S8000_A1, NULL, acc_tunable_a1, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_PMSASYNCFIFO_PADDR_S8000_A1, pmsasyncfifo_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOCBUSMUX_PADDR_S8000_A1, socbusmux_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SWITCHFABRIC_PADDR_S8000_A1, switchfabric_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_PMS_PMS_CSR_PADDR_S8000_A1, pms_csr_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_DYNAMIC_CLK_GATING_PADDR_S8000_A1, sb_glue_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_PADDR_S8000_A1, afc_aiu_sb_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_ASIO_MISC1_PADDR_S8000_A1, asio_misc1_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, CP_CP_COM_PADDR_S8000_A1, cp_com_tunable_a1, NULL, true},
|
||||
|
||||
{0, 0, NULL, NULL, 0}
|
||||
};
|
||||
@@ -0,0 +1,219 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* This file contains Tunables for s8001 */
|
||||
|
||||
#include <platform/tunables.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <soc/module/address_map.h>
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_ALL ****************************************/
|
||||
// <rdar://problem/21347912> Add support for product / platform specific tunables
|
||||
// <rdar://problem/20619805> Add PMGR MISC_CFG_DISP.SEL_DISP_PMGR_DWI_VSYNC tunable to SPDS tunables
|
||||
#define SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_EXTRA \
|
||||
{ /*! PLL0_CFG */ 0x00004, sizeof(uint32_t), 0xc0000000u, 0x40000000u}, \
|
||||
{ /*! PLL1_CFG */ 0x04004, sizeof(uint32_t), 0xc0000000u, 0x40000000u}, \
|
||||
{ /*! PLL6_CFG */ 0x18004, sizeof(uint32_t), 0xc0000000u, 0x40000000u}, \
|
||||
{ /*! PLL7_CFG */ 0x1c004, sizeof(uint32_t), 0xc0000000u, 0x00000000u}, \
|
||||
{ /*! VOLMAN_SOC_DELAY */ 0xa001c, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_GFX_SRAM_DELAY */ 0xa0020, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_CPU_SRAM_DELAY */ 0xa0024, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_GFX_DELAY */ 0xa0028, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_CPU_DELAY */ 0xa002c, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! MISC_CFG_DISP_OFFSET */ 0xdc040, sizeof(uint32_t), 0x00000001u, 0x00000000u}
|
||||
|
||||
// <rdar://problem/20620055> Add CPU TVM tunables in tunables PDF to SPDS tunables
|
||||
// <rdar://problem/20545557> Add DVMR tunables in tunables PDF to SPDS tunables
|
||||
#define ACC_DEFAULT_TUNABLES_S8001_EXTRA \
|
||||
/* Configure temperature ranges and measurement offsets for DVFM/DVTM */ \
|
||||
/* temp_thread0 0x8 temp_thresh1 0x21 temp_offset0 0 temp_offset1 0 */ \
|
||||
{ /* ACC_PWRCTL_DVFM_CFG */ 0x220040, sizeof(uint32_t), 0x0fffffffu, 0x00001088u}, \
|
||||
/* temp_thresh2 0x3a temp_offset2 0 */ \
|
||||
{ /* ACC_PWRCTL_DVFM_CFG1 */ 0x220058, sizeof(uint32_t), 0x001fffffu, 0x0000003au}, \
|
||||
{ /* ACC_PWRCTL_DVMR_SCR */ 0x2206b8, sizeof(uint64_t), 0x00000fffu, 0x000000421}
|
||||
|
||||
#define SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8001_EXTRA \
|
||||
/* <rdar://problem/20868785> Ensure that LPO OFF_MODE is set appropriately */ \
|
||||
{ /*! MINIPMGR_LPO_CFG */ 0x00004, sizeof(uint32_t), 0xc0000000u, 0x80000000u }
|
||||
|
||||
// <rdar://problem/17755256> SwitchFabric Hash lock bit is not set
|
||||
#define SWITCHFABRIC_DEFAULT_TUNABLES_S8001_EXTRA \
|
||||
{ /*! SWITCHFABRIC_REGS_AMAP_LOCK */ 0x00000, sizeof(uint32_t), 0x00000001u, 0x00000001u }
|
||||
/**************************************** END CHIP_REVISION_ALL ****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_B0 ****************************************/
|
||||
#include <soc/s8001/b0/tunable/minipmgr.h>
|
||||
#include <soc/s8001/b0/tunable/pmgr.h>
|
||||
#include <soc/s8001/b0/tunable/acc.h>
|
||||
#include <soc/s8001/b0/tunable/sbasyncfifo_widgets.h>
|
||||
#include <soc/s8001/b0/tunable/socbusmux.h>
|
||||
#include <soc/s8001/b0/tunable/switchfabric.h>
|
||||
#include <soc/s8001/b0/tunable/pms_csr.h>
|
||||
#include <soc/s8001/b0/tunable/afc_aiu_sb.h>
|
||||
#include <soc/s8001/b0/tunable/sb_glue.h>
|
||||
#include <soc/s8001/b0/tunable/misc1.h>
|
||||
#include <soc/s8001/b0/tunable/cp_com.h>
|
||||
|
||||
|
||||
static const struct tunable_struct pmsasyncfifo_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_PMSASYNCFIFO_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct minipmgr_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8001_EXTRA,
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct64 acc_tunable_b0[] = {
|
||||
ACC_DEFAULT_TUNABLES_S8001_EXTRA,
|
||||
ACC_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct socbusmux_tunable_b0[] = {
|
||||
SOCBUSMUX_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct switchfabric_tunable_b0[] = {
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8001_EXTRA,
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct pms_csr_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMS_CSR_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct sb_glue_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_DYNAMIC_CLK_GATING_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct afc_aiu_sb_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct asio_misc1_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_ASIO_MISC1_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp0_cp_com_tunable_b0[] = {
|
||||
CP0_CP_COM_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp1_cp_com_tunable_b0[] = {
|
||||
CP1_CP_COM_DEFAULT_TUNABLES_S8001_B0
|
||||
};
|
||||
|
||||
/***************************************** END CHIP_REVISION_B0 *****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_A0 ****************************************/
|
||||
#include <soc/s8001/a0/tunable/minipmgr.h>
|
||||
#include <soc/s8001/a0/tunable/pmgr.h>
|
||||
#include <soc/s8001/a0/tunable/acc.h>
|
||||
#include <soc/s8001/a0/tunable/sbasyncfifo_widgets.h>
|
||||
#include <soc/s8001/a0/tunable/socbusmux.h>
|
||||
#include <soc/s8001/a0/tunable/switchfabric.h>
|
||||
#include <soc/s8001/a0/tunable/pms_csr.h>
|
||||
#include <soc/s8001/a0/tunable/afc_aiu_sb.h>
|
||||
#include <soc/s8001/a0/tunable/sb_glue.h>
|
||||
#include <soc/s8001/a0/tunable/misc1.h>
|
||||
#include <soc/s8001/a0/tunable/cp_com.h>
|
||||
|
||||
static const struct tunable_struct pmsasyncfifo_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_PMSASYNCFIFO_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct minipmgr_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8001_EXTRA,
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct64 acc_tunable_a0[] = {
|
||||
ACC_DEFAULT_TUNABLES_S8001_EXTRA,
|
||||
ACC_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct socbusmux_tunable_a0[] = {
|
||||
SOCBUSMUX_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct switchfabric_tunable_a0[] = {
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8001_EXTRA,
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct pms_csr_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMS_CSR_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct sb_glue_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_DYNAMIC_CLK_GATING_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct afc_aiu_sb_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct asio_misc1_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_ASIO_MISC1_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp0_cp_com_tunable_a0[] = {
|
||||
CP0_CP_COM_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp1_cp_com_tunable_a0[] = {
|
||||
CP1_CP_COM_DEFAULT_TUNABLES_S8001_A0
|
||||
};
|
||||
/***************************************** END CHIP_REVISION_A0 *****************************************/
|
||||
|
||||
// For each chip, highest revision must come first.
|
||||
// Notice reconfig == false for minipmgr, since it's an AOP.
|
||||
const struct tunable_chip_struct tunables_pmgr[] = {
|
||||
// B0
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8001_B0, pmgr_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_AOP_MINIPMGR_PADDR_S8001_B0, minipmgr_tunable_b0, NULL, false},
|
||||
{CHIP_REVISION_B0, ACC_PADDR_S8001_B0, NULL, acc_tunable_b0, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_PMSASYNCFIFO_PADDR_S8001_B0, pmsasyncfifo_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOCBUSMUX_PADDR_S8001_B0, socbusmux_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SWITCHFABRIC_PADDR_S8001_B0, switchfabric_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_PMS_PMS_CSR_PADDR_S8001_B0, pms_csr_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_DYNAMIC_CLK_GATING_PADDR_S8001_B0, sb_glue_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_PADDR_S8001_B0, afc_aiu_sb_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_ASIO_MISC1_PADDR_S8001_B0, asio_misc1_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, CP0_CP_COM_PADDR_S8001_B0, cp0_cp_com_tunable_b0, NULL, true},
|
||||
{CHIP_REVISION_B0, CP1_CP_COM_PADDR_S8001_B0, cp1_cp_com_tunable_b0, NULL, true},
|
||||
|
||||
// A0
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8001_A0, pmgr_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_AOP_MINIPMGR_PADDR_S8001_A0, minipmgr_tunable_a0, NULL, false},
|
||||
{CHIP_REVISION_A0, ACC_PADDR_S8001_A0, NULL, acc_tunable_a0, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_PMSASYNCFIFO_PADDR_S8001_A0, pmsasyncfifo_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOCBUSMUX_PADDR_S8001_A0, socbusmux_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SWITCHFABRIC_PADDR_S8001_A0, switchfabric_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_PMS_PMS_CSR_PADDR_S8001_A0, pms_csr_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_DYNAMIC_CLK_GATING_PADDR_S8001_A0, sb_glue_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_PADDR_S8001_A0, afc_aiu_sb_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_ASIO_MISC1_PADDR_S8001_A0, asio_misc1_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, CP0_CP_COM_PADDR_S8001_A0, cp0_cp_com_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, CP1_CP_COM_PADDR_S8001_A0, cp1_cp_com_tunable_a0, NULL, true},
|
||||
|
||||
{0, 0, NULL, NULL, 0}
|
||||
};
|
||||
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* This file contains Tunables for s8001 ipad6b */
|
||||
|
||||
#include <platform/tunables.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <soc/module/address_map.h>
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_ALL ****************************************/
|
||||
// <rdar://problem/22709991> Update iBoot/PMGR driver settings for enabling UV_WARN for J127/J105
|
||||
#define SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_IPAD6B_EXTRA \
|
||||
{ /*! GFX_THROTTLE_DITHER0_INT */ 0x7403c, sizeof(uint32_t), 0xffffffffu, 0x480000u}, \
|
||||
{ /*! GFX_THROTTLE_DITHER0 */ 0x74040, sizeof(uint32_t), 0xffffffffu, 0x10555u}, \
|
||||
{ /*! GFX_THROTTLE_DITHER1 */ 0x74044, sizeof(uint32_t), 0xffffffffu, 0x106dbu}, \
|
||||
{ /*! GFX_THROTTLE_DITHER2 */ 0x74048, sizeof(uint32_t), 0xffffffffu, 0x10fffu}, \
|
||||
{ /*! GFX_THROTTLE_DITHER3 */ 0x7404c, sizeof(uint32_t), 0xffffffffu, 0x00fffu}, \
|
||||
{ /*! GFX_THROTTLE_DITHER4 */ 0x74050, sizeof(uint32_t), 0xffffffffu, 0x00fffu}, \
|
||||
{ /*! GFX_THROTTLE_DITHER5 */ 0x74054, sizeof(uint32_t), 0xffffffffu, 0x00fffu}, \
|
||||
{ /*! GFX_THROTTLE_SRC2_CTL */ 0x74078, sizeof(uint32_t), 0xffffffffu, 0x00003u}, \
|
||||
{ /*! GFX_THROTTLE_SRC2_ASSERT_COUNT */ 0x7407c, sizeof(uint32_t), 0xffffffffu, 0x00000u}, \
|
||||
{ /*! GFX_THROTTLE_SRC2_DEASSERT_COUNT */ 0x74080, sizeof(uint32_t), 0xffffffffu, 0x00000u}, \
|
||||
{ /*! GFX_THROTTLE_SRC2_MIN_ACTIVE_COUNT */ 0x74084, sizeof(uint32_t), 0xffffffffu, 0x00000u}, \
|
||||
{ /*! GFX_PERF_CFG4 */ 0xfc140, sizeof(uint32_t), 0xffffffffu, 0x10003u}, \
|
||||
{ /*! GFX_PERF_CFG5 */ 0xfc150, sizeof(uint32_t), 0xffffffffu, 0x10001u}, \
|
||||
{ /*! GFX_PERF_CTL */ 0xfc000, sizeof(uint32_t), 0xffffffffu, 0x00003u}, \
|
||||
{ -1, -1, -1, -1 }
|
||||
/**************************************** END CHIP_REVISION_ALL ****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_B0 ****************************************/
|
||||
#include <soc/s8001/b0/tunable/pmgr.h>
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_b0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_IPAD6B_EXTRA
|
||||
};
|
||||
|
||||
/***************************************** END CHIP_REVISION_B0 *****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_A0 ****************************************/
|
||||
#include <soc/s8001/a0/tunable/pmgr.h>
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_IPAD6B_EXTRA
|
||||
};
|
||||
|
||||
/***************************************** END CHIP_REVISION_A0 *****************************************/
|
||||
|
||||
// For each chip, highest revision must come first.
|
||||
// Notice reconfig == false for minipmgr, since it's an AOP.
|
||||
const struct tunable_chip_struct tunables_pmgr_product[] = {
|
||||
// B0
|
||||
{CHIP_REVISION_B0, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8001_B0, pmgr_tunable_b0, NULL, true},
|
||||
|
||||
// A0
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8001_A0, pmgr_tunable_a0, NULL, true},
|
||||
|
||||
{0, 0, NULL, NULL, 0}
|
||||
};
|
||||
@@ -0,0 +1,203 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* This file contains Tunables for s8003 */
|
||||
|
||||
#include <platform/tunables.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <soc/module/address_map.h>
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_ALL ****************************************/
|
||||
// <rdar://problem/21347912> Add support for product / platform specific tunables
|
||||
#define SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8003_EXTRA \
|
||||
{ /*! PLL0_CFG */ 0x00004, sizeof(uint32_t), 0xc0000000u, 0x40000000u}, \
|
||||
{ /*! PLL1_CFG */ 0x04004, sizeof(uint32_t), 0xc0000000u, 0x40000000u}, \
|
||||
{ /*! VOLMAN_SOC_DELAY */ 0xa001c, sizeof(uint32_t), 0xfffffcffu, 0xbb81642fu}, \
|
||||
{ /*! VOLMAN_GFX_SRAM_DELAY */ 0xa0020, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_CPU_SRAM_DELAY */ 0xa0024, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_GFX_DELAY */ 0xa0028, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}, \
|
||||
{ /*! VOLMAN_CPU_DELAY */ 0xa002c, sizeof(uint32_t), 0xfffffcffu, 0xbb816405u}
|
||||
|
||||
// <rdar://problem/20545478> Add DVMR tunables in tunables PDF to SPDS tunables
|
||||
// <rdar://problem/20620070> Add CPU TVM tunables in tunables PDF to SPDS tunables
|
||||
#define ACC_DEFAULT_TUNABLES_S8003_EXTRA \
|
||||
/* Configure temperature ranges and measurement offsets for DVFM/DVTM */ \
|
||||
/* temp_thread0 0x8 temp_thresh1 0x21 temp_offset0 0 temp_offset1 0 */ \
|
||||
{ /* ACC_PWRCTL_DVFM_CFG */ 0x220040, sizeof(uint32_t), 0x0fffffffu, 0x00001088u}, \
|
||||
/* temp_thresh2 0x3a temp_offset2 0 */ \
|
||||
{ /* ACC_PWRCTL_DVFM_CFG1 */ 0x220058, sizeof(uint32_t), 0x001fffffu, 0x0000003au}, \
|
||||
{ /* ACC_PWRCTL_DVMR_SCR */ 0x2206b8, sizeof(uint64_t), 0x00000fffu, 0x000000421}
|
||||
|
||||
#define SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8003_EXTRA \
|
||||
/* <rdar://problem/20868785> Ensure that LPO OFF_MODE is set appropriately */ \
|
||||
{ /*! MINIPMGR_LPO_CFG */ 0x00004, sizeof(uint32_t), 0xc0000000u, 0x80000000u }
|
||||
|
||||
// <rdar://problem/17755256> SwitchFabric Hash lock bit is not set
|
||||
#define SWITCHFABRIC_DEFAULT_TUNABLES_S8003_EXTRA \
|
||||
{ /*! SWITCHFABRIC_REGS_AMAP_LOCK */ 0x00000, sizeof(uint32_t), 0x00000001u, 0x00000001u }
|
||||
/**************************************** END CHIP_REVISION_ALL ****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_A1 ****************************************/
|
||||
#include <soc/s8003/a1/tunable/minipmgr.h>
|
||||
#include <soc/s8003/a1/tunable/pmgr.h>
|
||||
#include <soc/s8003/a1/tunable/acc.h>
|
||||
#include <soc/s8003/a1/tunable/sbasyncfifo_widgets.h>
|
||||
#include <soc/s8003/a1/tunable/socbusmux.h>
|
||||
#include <soc/s8003/a1/tunable/switchfabric.h>
|
||||
#include <soc/s8003/a1/tunable/pms_csr.h>
|
||||
#include <soc/s8003/a1/tunable/afc_aiu_sb.h>
|
||||
#include <soc/s8003/a1/tunable/sb_glue.h>
|
||||
#include <soc/s8003/a1/tunable/misc1.h>
|
||||
#include <soc/s8003/a1/tunable/cp_com.h>
|
||||
|
||||
static const struct tunable_struct pmsasyncfifo_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_PMSASYNCFIFO_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8003_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct minipmgr_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8003_EXTRA,
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct64 acc_tunable_a1[] = {
|
||||
ACC_DEFAULT_TUNABLES_S8003_EXTRA,
|
||||
ACC_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct socbusmux_tunable_a1[] = {
|
||||
SOCBUSMUX_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct switchfabric_tunable_a1[] = {
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8003_EXTRA,
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct pms_csr_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_PMS_PMS_CSR_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct sb_glue_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_DYNAMIC_CLK_GATING_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct afc_aiu_sb_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct asio_misc1_tunable_a1[] = {
|
||||
SOUTH_BRIDGE_ASIO_MISC1_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp_com_tunable_a1[] = {
|
||||
CP_CP_COM_DEFAULT_TUNABLES_S8003_A1
|
||||
};
|
||||
/***************************************** END CHIP_REVISION_A1 *****************************************/
|
||||
|
||||
/**************************************** BEGIN CHIP_REVISION_A0 ****************************************/
|
||||
#include <soc/s8003/a0/tunable/minipmgr.h>
|
||||
#include <soc/s8003/a0/tunable/pmgr.h>
|
||||
#include <soc/s8003/a0/tunable/acc.h>
|
||||
#include <soc/s8003/a0/tunable/sbasyncfifo_widgets.h>
|
||||
#include <soc/s8003/a0/tunable/socbusmux.h>
|
||||
#include <soc/s8003/a0/tunable/switchfabric.h>
|
||||
#include <soc/s8003/a0/tunable/pms_csr.h>
|
||||
#include <soc/s8003/a0/tunable/afc_aiu_sb.h>
|
||||
#include <soc/s8003/a0/tunable/sb_glue.h>
|
||||
#include <soc/s8003/a0/tunable/misc1.h>
|
||||
#include <soc/s8003/a0/tunable/cp_com.h>
|
||||
|
||||
static const struct tunable_struct pmsasyncfifo_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_PMSASYNCFIFO_DEFAULT_TUNABLES_S8003_A0,
|
||||
};
|
||||
|
||||
static const struct tunable_struct pmgr_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8003_EXTRA,
|
||||
SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct minipmgr_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8003_EXTRA,
|
||||
SOUTH_BRIDGE_AOP_MINIPMGR_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct64 acc_tunable_a0[] = {
|
||||
ACC_DEFAULT_TUNABLES_S8003_EXTRA,
|
||||
ACC_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct socbusmux_tunable_a0[] = {
|
||||
SOCBUSMUX_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct switchfabric_tunable_a0[] = {
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8003_EXTRA,
|
||||
SWITCHFABRIC_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct pms_csr_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_PMS_PMS_CSR_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct sb_glue_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_DYNAMIC_CLK_GATING_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct afc_aiu_sb_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct asio_misc1_tunable_a0[] = {
|
||||
SOUTH_BRIDGE_ASIO_MISC1_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
|
||||
static const struct tunable_struct cp_com_tunable_a0[] = {
|
||||
CP_CP_COM_DEFAULT_TUNABLES_S8003_A0
|
||||
};
|
||||
/***************************************** END CHIP_REVISION_A0 *****************************************/
|
||||
|
||||
// For each chip, highest revision must come first.
|
||||
// Notice reconfig == false for minipmgr, since it's an AOP.
|
||||
const struct tunable_chip_struct tunables_pmgr[] = {
|
||||
// A1
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8003_A1, pmgr_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_AOP_MINIPMGR_PADDR_S8003_A1, minipmgr_tunable_a1, NULL, false},
|
||||
{CHIP_REVISION_A1, ACC_PADDR_S8003_A1, NULL, acc_tunable_a1, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_PMSASYNCFIFO_PADDR_S8003_A1, pmsasyncfifo_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOCBUSMUX_PADDR_S8003_A1, socbusmux_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SWITCHFABRIC_PADDR_S8003_A1, switchfabric_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_PMS_PMS_CSR_PADDR_S8003_A1, pms_csr_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_DYNAMIC_CLK_GATING_PADDR_S8003_A1, sb_glue_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_PADDR_S8003_A1, afc_aiu_sb_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, SOUTH_BRIDGE_ASIO_MISC1_PADDR_S8003_A1, asio_misc1_tunable_a1, NULL, true},
|
||||
{CHIP_REVISION_A1, CP_CP_COM_PADDR_S8003_A1, cp_com_tunable_a1, NULL, true},
|
||||
|
||||
// A0
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8003_A0, pmgr_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_AOP_MINIPMGR_PADDR_S8003_A0, minipmgr_tunable_a0, NULL, false},
|
||||
{CHIP_REVISION_A0, ACC_PADDR_S8003_A0, NULL, acc_tunable_a0, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_PMSASYNCFIFO_PADDR_S8003_A0, pmsasyncfifo_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOCBUSMUX_PADDR_S8003_A0, socbusmux_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SWITCHFABRIC_PADDR_S8003_A0, switchfabric_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_PMS_PMS_CSR_PADDR_S8003_A0, pms_csr_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_DYNAMIC_CLK_GATING_PADDR_S8003_A0, sb_glue_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_SBR_AXI2AF_AFC_AIU_SB_PADDR_S8003_A0, afc_aiu_sb_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, SOUTH_BRIDGE_ASIO_MISC1_PADDR_S8003_A0, asio_misc1_tunable_a0, NULL, true},
|
||||
{CHIP_REVISION_A0, CP_CP_COM_PADDR_S8003_A0, cp_com_tunable_a0, NULL, true},
|
||||
|
||||
{0, 0, NULL, NULL, 0}
|
||||
};
|
||||
Reference in new issue
Block a user