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@@ -0,0 +1,50 @@
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/*
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* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef _APCIE_COMMON_REGS_H
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#define _APCIE_COMMON_REGS_H
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#include <platform/soc/hwregbase.h>
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#define rAPCIE_PHY_RST_CTRL(n) (*(volatile uint32_t *)(APCIE_COMMON_BASE_ADDR + 0x040 + (n) * 0x010))
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#define rAPCIE_PHY_CLKREQ_CTRL(n) (*(volatile uint32_t *)(APCIE_COMMON_BASE_ADDR + 0x044 + (n) * 0x010))
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#define APCIE_PHY_RST_CTRL_phy_sw_reset (1 << 0)
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#define rAPCIE_NANDSYSCLK_CTRL (*(volatile uint32_t *)(APCIE_COMMON_BASE_ADDR + 0x080))
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#define rAPCIE_PORT_CTRL(n) (*(volatile uint32_t *)(APCIE_COMMON_BASE_ADDR + 0x100 + (n) * 0x80))
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#define rAPCIE_PORT_SQUELCH_CTRL(n) (*(volatile uint32_t *)(APCIE_COMMON_BASE_ADDR + 0x104 + (n) * 0x80))
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#define rAPCIE_PORT_REFCLK_CTRL(n) (*(volatile uint32_t *)(APCIE_COMMON_BASE_ADDR + 0x108 + (n) * 0x80))
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#define rAPCIE_PORT_OVERRIDE_CTRL(n) (*(volatile uint32_t *)(APCIE_COMMON_BASE_ADDR + 0x10c + (n) * 0x80))
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#define rAPCIE_PORT_CLKREQ_CTRL(n) (*(volatile uint32_t *)(APCIE_COMMON_BASE_ADDR + 0x110 + (n) * 0x80))
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#define rAPCIE_PORT_ACG_IDLE_CTRL(n) (*(volatile uint32_t *)(APCIE_COMMON_BASE_ADDR + 0x114 + (n) * 0x80))
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#define rAPCIE_PORT_RST_CTRL(n) (*(volatile uint32_t *)(APCIE_COMMON_BASE_ADDR + 0x118 + (n) * 0x80))
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#define rAPCIE_PIPE_OVERRIDE_VAL(n) (*(volatile uint32_t *)(APCIE_COMMON_BASE_ADDR + 0x11c + (n) * 0x80))
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#define rAPCIE_PORT_PRIORITY(n) (*(volatile uint32_t *)(APCIE_COMMON_BASE_ADDR + 0x120 + (n) * 0x80))
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#define APCIE_PORT_CTRL_port_en (1 << 0)
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#define APCIE_PORT_CTRL_appclk_auto_dis (1 << 8)
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#define APCIE_PORT_CTRL_nvme_en (1 << 16)
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#define APCIE_PORT_CTRL_muxed_auxclk_auto_dis (1 << 20)
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#define APCIE_PORT_REFCLK_CTRL_refclk_en (1 << 0)
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#define APCIE_PORT_REFCLK_CTRL_refclk_auto_dis (1 << 8)
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#define APCIE_PORT_OVERRIDE_CTRL_pipe_ovr_en (1 << 0)
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#define APCIE_PORT_RST_CTRL_perst_n (1 << 0)
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#define APCIE_PHY_BASE_ADDR(port) (PCI_REG_BASE + 0x1000000 * ((port) + 1) + 0x5000)
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#define rAPCIE_PHY_PHY_REF_USE_PAD(port) (*(volatile uint32_t *)(APCIE_PHY_BASE_ADDR(port) + 0xc3c))
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#endif
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@@ -0,0 +1,477 @@
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/*
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* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <arch/arm/arm.h>
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#include <drivers/apcie.h>
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#include <drivers/dart.h>
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#include <drivers/pci.h>
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#include <lib/devicetree.h>
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#include <platform.h>
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#include <platform/apcie_regs.h>
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#include <platform/gpio.h>
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#include <platform/gpiodef.h>
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#include <platform/timer.h>
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#include <platform/soc/hwclocks.h>
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#include <platform/soc/hwisr.h>
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#include <platform/soc/hwregbase.h>
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#include <sys.h>
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#include <sys/menu.h>
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#include "apcie_common_regs.h"
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static bool s3e_mode;
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static bool s3e_reset_on_enable;
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static uint32_t link_enable_count;
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struct apcie_dbi_overrides {
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uint32_t offset;
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uint32_t mask;
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uint32_t value;
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};
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static struct apcie_dbi_overrides apcie_dbi_overrides[] = {
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// Enable 64-bit addresses
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{ 0x024, 0x00000001, 1 },
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// Don't advertise L0s support
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{ 0x07c, 0x00000400, 0 },
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// Set T_POWER_OFF field in the L1_substates register to 2 (<rdar://problem/17813587>)
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{ 0xb44, 0x00000003, 2 },
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};
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bool external_refclk;
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// selects internal vs external refclk. must be called before
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// enabling the first link
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void apcie_use_external_refclk(bool use)
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{
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external_refclk = use;
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}
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void apcie_set_s3e_mode(bool reset_on_enable)
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{
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s3e_mode = true;
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s3e_reset_on_enable = reset_on_enable;
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}
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#if !SUB_PLATFORM_T7000
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static void apcie_enable_phy_clkreq(uint32_t phy)
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{
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// Note, the function number might change for future platforms
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if (phy == 0) {
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gpio_configure(GPIO_PCIE_PHY01_CLKREQ, GPIO_CFG_FUNC1);
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} else if (phy == 1) {
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gpio_configure(GPIO_PCIE_PHY23_CLKREQ, GPIO_CFG_FUNC1);
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} else {
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panic("apcie: unknown phy %u", phy);
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}
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rAPCIE_PHY_CLKREQ_CTRL(phy) |= 1;
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}
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static void apcie_disable_phy_clkreq(uint32_t phy)
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{
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rAPCIE_PHY_CLKREQ_CTRL(phy) &= ~1;
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if (phy == 0) {
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gpio_configure(GPIO_PCIE_PHY01_CLKREQ, GPIO_CFG_DFLT);
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} else if (phy == 1) {
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gpio_configure(GPIO_PCIE_PHY23_CLKREQ, GPIO_CFG_DFLT);
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} else {
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panic("apcie: unknown phy %u", phy);
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}
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}
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#endif
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static void apcie_enable_external_refclk(void)
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{
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// Sequence from section 6.1.5 of Fiji/Capri APCIe spec (updated to r1.04.44)
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// 1) Set APCIE_COMMON_APCIE_RST_CTRL_{0/1}.apcie_phy_sw_reset to place the PHY in reset.
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for (int i = 0; i < APCIE_NUM_LINKS; i += 2)
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rAPCIE_PHY_RST_CTRL(i / 2) |= APCIE_PHY_RST_CTRL_phy_sw_reset;
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// 2) To access the PHY, the link shall be enabled.
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for (int i = 0; i < APCIE_NUM_LINKS; i+= 2)
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rAPCIE_PORT_CTRL(i) |= APCIE_PORT_CTRL_port_en;
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// 3) De-assert PERST# to the root controller
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for (int i = 0; i < APCIE_NUM_LINKS; i+= 2)
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rAPCIE_PORT_RST_CTRL(i) |= APCIE_PORT_RST_CTRL_perst_n;
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// 4) Select the external REFCLK
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for (int i = 0; i < APCIE_NUM_LINKS; i+= 2)
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rAPCIE_PHY_PHY_REF_USE_PAD(i) = 1;
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// c) Insert a DMB barrier instruction to insure that the external REFCLK switch occurs
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// before the port is disabled.
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platform_memory_barrier();
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// 5) Assert PERST# to the root controller
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for (int i = 0; i < APCIE_NUM_LINKS; i+= 2)
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rAPCIE_PORT_RST_CTRL(i) &= ~APCIE_PORT_RST_CTRL_perst_n;
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// 6) Disable the link(s)
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for (int i = 0; i < APCIE_NUM_LINKS; i+= 2)
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rAPCIE_PORT_CTRL(i) &= ~APCIE_PORT_CTRL_port_en;
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// 7) Release the PHY(s) from reset
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for (int i = 0; i < APCIE_NUM_LINKS; i += 2)
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rAPCIE_PHY_RST_CTRL(i / 2) &= ~APCIE_PHY_RST_CTRL_phy_sw_reset;
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}
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static void apcie_enable_root_complex(void)
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{
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clock_gate(CLK_PCIE, true);
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#if SUB_PLATFORM_T7000
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// Fiji uses the clock mesh for refclk, Capri has a dedicated PLL for refclk
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if (!external_refclk)
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clock_gate(CLK_PCIE_REF, true);
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#endif
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clock_gate(CLK_PCIE_AUX, true);
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spin(10);
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if (external_refclk)
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apcie_enable_external_refclk();
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if (s3e_mode) {
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if (s3e_reset_on_enable) {
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gpio_configure(GPIO_S3E_RESETN, GPIO_CFG_OUT_0);
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}
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gpio_configure(GPIO_NAND_SYS_CLK, GPIO_CFG_FUNC0);
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rAPCIE_NANDSYSCLK_CTRL = 1;
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// S3e spec requires 32 24 Mhz clock cycles from NANDSYSCLK to reset deassertion.
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// The Maui spec requires 100 microseconds, so we'll follow that to match the behavior
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// we'll be using in Maui
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spin(100);
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gpio_configure(GPIO_S3E_RESETN, GPIO_CFG_OUT_1);
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}
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}
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static void apcie_disable_root_complex(void)
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{
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clock_set_device_reset(CLK_PCIE, true);
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spin(1);
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clock_gate(CLK_PCIE, false);
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clock_set_device_reset(CLK_PCIE, false);
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}
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// Implements the enable sequence from APCIe spec section 6.1 as it applies to
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// APCIE_COMMON registers. The portion of the sequence that affects the APCIE_CONFIG
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// registers is handled in common code
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static void apcie_enable_link_hardware(uint32_t link)
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{
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ASSERT(link < APCIE_NUM_LINKS);
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dprintf(DEBUG_INFO, "apcie: Enabling link %d%s\n", link, external_refclk ? " with external refclk" : "");
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// Make sure PERST# starts out as asserted
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rAPCIE_PORT_RST_CTRL(link) &= ~APCIE_PORT_RST_CTRL_perst_n;
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// 2) 100Mhz REFCLK is enabled
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if (!external_refclk) {
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rAPCIE_PORT_REFCLK_CTRL(link) |= APCIE_PORT_REFCLK_CTRL_refclk_en;
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#if !SUB_PLATFORM_T7000
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while(!clock_get_pcie_refclk_good())
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spin(10);
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#endif
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} else {
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// On Capri, the PHY asserts an external clkreq enable GPIO
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// when it wants the external refclk to be enabled. On Fiji the
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// external refclk is required to always be enabled
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#if !SUB_PLATFORM_T7000
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apcie_enable_phy_clkreq(link / 2);
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#endif
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}
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// 3) 10 us wait
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spin(10);
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// 4) Target PCIE link is enabled
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rAPCIE_PORT_OVERRIDE_CTRL(link) &= ~APCIE_PORT_OVERRIDE_CTRL_pipe_ovr_en;
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rAPCIE_PORT_CTRL(link) |= APCIE_PORT_CTRL_port_en;
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#if SUPPORT_FPGA
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rAPCIE_PORT_CTRL(link) |= APCIE_PORT_CTRL_muxed_auxclk_auto_dis;
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#endif
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// 5) De-assert PERST# for the target PCIE link.
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rAPCIE_PORT_RST_CTRL(link) |= APCIE_PORT_RST_CTRL_perst_n;
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// 6b) DBI register overrides
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// Unlock access to the readonly registers
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rAPCIE_CONFIG_SPACE32(link, 0x8bc) |= 1;
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for (unsigned i = 0; i < sizeof(apcie_dbi_overrides) / sizeof(apcie_dbi_overrides[0]); i++) {
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uint32_t offset = apcie_dbi_overrides[i].offset;
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uint32_t mask = apcie_dbi_overrides[i].mask;
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uint32_t value = apcie_dbi_overrides[i].value;
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rAPCIE_CONFIG_SPACE32(link, offset) = (rAPCIE_CONFIG_SPACE32(link, offset) & ~mask) | value;
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}
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// Lock access to the readonly registers
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rAPCIE_CONFIG_SPACE32(link, 0x8bc) &= ~1;
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}
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static void apcie_disable_link_hardware(uint32_t link)
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{
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ASSERT(link < APCIE_NUM_LINKS);
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rAPCIE_PORT_RST_CTRL(link) &= ~APCIE_PORT_RST_CTRL_perst_n;
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rAPCIE_PORT_REFCLK_CTRL(link) &= ~APCIE_PORT_REFCLK_CTRL_refclk_en;
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rAPCIE_PORT_CTRL(link) &= ~APCIE_PORT_CTRL_port_en;
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rAPCIE_PORT_OVERRIDE_CTRL(link) |= APCIE_PORT_OVERRIDE_CTRL_pipe_ovr_en;
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#if !SUB_PLATFORM_T7000
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if (external_refclk) {
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// If the other link on this PHY is already disabled, go ahead
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// and disable the external refclk settings and GPIO
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if ((rAPCIE_PORT_CTRL(link ^ 1) & APCIE_PORT_CTRL_port_en) == 0) {
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apcie_disable_phy_clkreq(link / 2);
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}
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}
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#endif
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}
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bool apcie_enable_link(uint32_t link)
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{
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struct apcie_link_config *config = &apcie_link_configs[link];
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struct apcie_link_status *status = &apcie_link_statuses[link];
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utime_t start;
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uint32_t force_width;
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ASSERT(link < APCIE_NUM_LINKS);
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if (status->enabled)
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return true;
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// Clocks to PCIe don't default to on since it isn't used in POR configurations
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if (link_enable_count == 0) {
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apcie_enable_root_complex();
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}
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// Make sure PERST# starts out as asserted
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gpio_configure(config->perst_gpio, GPIO_CFG_OUT_0);
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gpio_configure(config->clkreq_gpio, GPIO_CFG_IN);
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// wait for CLKREQ# to be asserted
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dprintf(DEBUG_INFO, "apcie: waiting for clkreq...");
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start = system_time();
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while (gpio_read(config->clkreq_gpio) != 0) {
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if (time_has_elapsed(start, APCIE_ENABLE_TIMEOUT)) {
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dprintf(DEBUG_CRITICAL, "apcie: timeout waiting for CLKREQ# on link %u\n", link);
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goto cleanup;
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}
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spin(1);
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}
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dprintf(DEBUG_INFO, " done\n");
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gpio_configure(config->clkreq_gpio, GPIO_CFG_FUNC0);
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// Do required initialization in APCIE_COMMON registers
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apcie_enable_link_hardware(link);
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// Apply tunables
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rAPCIE_CONFIG_INBCTRL(link) |= APCIE_CONFIG_INBCTRL_CPL_MUST_PUSH_EN;
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rAPCIE_CONFIG_OUTBCTRL(link) |= APCIE_CONFIG_OUTBCTRL_EARLY_PT_RESP_EN;
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rAPCIE_CONFIG_PMETOACK_TMOTLIM(link) = 0x28;
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// PCIe spec requires a 100 microsecond delay from REFCLK starting
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// to PERST being deasserted
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spin(100);
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// 5) De-assert PERST# for the target PCIE link.
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gpio_configure(config->perst_gpio, GPIO_CFG_OUT_1);
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// Limit link speed to Gen1
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rAPCIE_PCIE_CAP_LINK_CONTROL2(link) = (rAPCIE_PCIE_CAP_LINK_CONTROL2(link) & ~0xfU) | 1;
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// Limit link width if requested by the platform. If the platform returns 0,
|
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// let the hardware autonegotiate the width using its default parameters
|
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force_width = platform_get_pcie_link_width(link);
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if (force_width != 0) {
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ASSERT(force_width <= 2);
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uint32_t gen2_ctrl;
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gen2_ctrl = rAPCIE_PORT_LOGIC_GEN2_CTRL(link);
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gen2_ctrl &= ~(0x1ff << 8);
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gen2_ctrl |= (force_width << 8);
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rAPCIE_PORT_LOGIC_GEN2_CTRL(link) = gen2_ctrl;
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uint32_t port_link_ctrl;
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port_link_ctrl = rAPCIE_PORT_LOGIC_PORT_LINK_CTRL(link);
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port_link_ctrl &= ~(0x3f << 16);
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port_link_ctrl |= ((1 << (force_width - 1)) << 16);
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rAPCIE_PORT_LOGIC_PORT_LINK_CTRL(link) = port_link_ctrl;
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}
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rAPCIE_COUNTER_COMMAND(link) = APCIE_COUNTER_CLEAR | APCIE_COUNTER_ENABLE;
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// 6c) Software sets LINKCFG.ltssm_en to start link training
|
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rAPCIE_CONFIG_LINKCFG(link) |= APCIE_CONFIG_LINKCFG_LTSSM_EN;
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|
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start = system_time();
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while ((rAPCIE_CONFIG_LINKSTS(link) & APCIE_CONFIG_LINKSTS_LINK_STATUS) == 0) {
|
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if (time_has_elapsed(start, APCIE_ENABLE_TIMEOUT)) {
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uint32_t linkpmgrsts;
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dprintf(DEBUG_CRITICAL, "apcie: Timeout waiting for LinkUp on link %u\n", link);
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dprintf(DEBUG_CRITICAL, "apcie: LINKSTS 0x%08x\n", rAPCIE_CONFIG_LINKSTS(link));
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linkpmgrsts = rAPCIE_CONFIG_LINKPMGRSTS(link);
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dprintf(DEBUG_CRITICAL, "apcie: LINKPMGRSTS 0x%08x (LTSSM state %d)\n", linkpmgrsts, (linkpmgrsts >> 9) & 0x1F);
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||||
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goto cleanup;
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||||
}
|
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spin(10);
|
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}
|
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status->enabled = true;
|
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link_enable_count++;
|
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|
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dart_init(config->dart_id);
|
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|
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apcie_setup_root_port_bridge(link, config);
|
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return true;
|
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cleanup:
|
||||
gpio_configure(config->perst_gpio, GPIO_CFG_OUT_0);
|
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spin(10);
|
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gpio_configure(config->perst_gpio, GPIO_CFG_DFLT);
|
||||
gpio_configure(config->clkreq_gpio, GPIO_CFG_DFLT);
|
||||
|
||||
apcie_disable_link_hardware(link);
|
||||
|
||||
if (link_enable_count == 0) {
|
||||
apcie_disable_root_complex();
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
void apcie_disable_link(uint32_t link)
|
||||
{
|
||||
struct apcie_link_config *config = &apcie_link_configs[link];
|
||||
struct apcie_link_status *status = &apcie_link_statuses[link];
|
||||
utime_t start;
|
||||
|
||||
ASSERT(link < APCIE_NUM_LINKS);
|
||||
|
||||
if (!status->enabled)
|
||||
return;
|
||||
|
||||
dprintf(DEBUG_INFO, "apcie: Disabling link %d\n", link);
|
||||
|
||||
rAPCIE_COUNTER_COMMAND(link) = 0;
|
||||
|
||||
// Request PMETO and clear the previous status indications
|
||||
rAPCIE_CONFIG_PMETO(link) = 1 | (3 << 4);
|
||||
|
||||
start = system_time();
|
||||
while (rAPCIE_CONFIG_PMETO(link) & 1) {
|
||||
if (time_has_elapsed(start, 10000)) {
|
||||
dprintf(DEBUG_CRITICAL, "apcie: timeout waiting for PME_To_Ack, continuing\n");
|
||||
break;
|
||||
}
|
||||
spin(10);
|
||||
}
|
||||
|
||||
start = system_time();
|
||||
while ((rAPCIE_CONFIG_LINKSTS(link) & APCIE_CONFIG_LINKSTS_L2_STATE) == 0) {
|
||||
if (time_has_elapsed(start, 10000)) {
|
||||
dprintf(DEBUG_CRITICAL, "apcie: link did not go into L2, continuing\n");
|
||||
break;
|
||||
}
|
||||
spin(10);
|
||||
}
|
||||
|
||||
gpio_configure(config->perst_gpio, GPIO_CFG_OUT_0);
|
||||
// delay to allow PERST# signal to settle before letting the pulldown hold it low
|
||||
// and to allow the endpoint to handle PERST# before removing REFCLK
|
||||
spin(25);
|
||||
gpio_configure(config->perst_gpio, GPIO_CFG_DFLT);
|
||||
gpio_configure(config->clkreq_gpio, GPIO_CFG_DFLT);
|
||||
|
||||
#if DEBUG_BUILD
|
||||
dart_assert_unmapped(config->dart_id);
|
||||
#endif
|
||||
|
||||
apcie_disable_link_hardware(link);
|
||||
|
||||
status->enabled = false;
|
||||
link_enable_count--;
|
||||
|
||||
if (link_enable_count == 0) {
|
||||
apcie_disable_root_complex();
|
||||
}
|
||||
|
||||
apcie_free_port_bridge(link);
|
||||
}
|
||||
|
||||
uint32_t apcie_get_link_enable_count(void)
|
||||
{
|
||||
return link_enable_count;
|
||||
}
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
void apcie_update_devicetree(DTNode *apcie_node)
|
||||
{
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
propName = "dbi-overrides";
|
||||
if (FindProperty(apcie_node, &propName, &propData, &propSize)) {
|
||||
if (propSize < sizeof(apcie_dbi_overrides))
|
||||
panic("dbi-overrides property is too small");
|
||||
memcpy(propData, apcie_dbi_overrides, sizeof(apcie_dbi_overrides));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
struct apcie_link_config platform_apcie_link_configs[APCIE_NUM_LINKS] = {
|
||||
[0] = {
|
||||
.perst_gpio = GPIO_PCIE0_PERST,
|
||||
.clkreq_gpio = GPIO_PCIE0_CLKREQ,
|
||||
.dart_id = PCIE_PORT0_DART_ID,
|
||||
},
|
||||
[1] = {
|
||||
.perst_gpio = GPIO_PCIE1_PERST,
|
||||
.clkreq_gpio = GPIO_PCIE1_CLKREQ,
|
||||
.dart_id = PCIE_PORT1_DART_ID,
|
||||
},
|
||||
#if SUB_PLATFORM_T7001
|
||||
[2] = {
|
||||
.perst_gpio = GPIO_PCIE2_PERST,
|
||||
.clkreq_gpio = GPIO_PCIE2_CLKREQ,
|
||||
.dart_id = PCIE_PORT2_DART_ID,
|
||||
},
|
||||
[3] = {
|
||||
.perst_gpio = GPIO_PCIE3_PERST,
|
||||
.clkreq_gpio = GPIO_PCIE3_CLKREQ,
|
||||
.dart_id = PCIE_PORT3_DART_ID,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
void platform_register_pci_busses(void)
|
||||
{
|
||||
apcie_init();
|
||||
}
|
||||
|
||||
uint64_t platform_map_host_to_pci_addr(uintptr_t addr)
|
||||
{
|
||||
// Right now we're only supporting 32-bit PCI addresses
|
||||
// for aPCIe, so just lop off the top 32 bits
|
||||
return addr & 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
uintptr_t platform_map_pci_to_host_addr(uint64_t addr)
|
||||
{
|
||||
// Right now we're only supporting 32-bit PCI addresses
|
||||
// for aPCIe
|
||||
ASSERT((addr & ~0xFFFFFFFFULL) == 0);
|
||||
return PCI_32BIT_BASE + (addr & (PCI_32BIT_LEN - 1));
|
||||
}
|
||||
@@ -0,0 +1,13 @@
|
||||
# Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Computer, Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Computer, Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/apcie_v1.o \
|
||||
Reference in new issue
Block a user