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@@ -0,0 +1,23 @@
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/*
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* Copyright (c) 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <arch/arm/assembler.h>
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#if APPLICATION_IBOOT && (PRODUCT_IBSS || PRODUCT_LLB)
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.text
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.arm
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.align 12
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.globl _platform_start
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_platform_start:
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// Use VBAR to relocate exception vectors to binary linked address
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mcr p15, 0, r0, c12, c0, 0
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isb
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bx lr
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#endif
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@@ -0,0 +1,146 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <platform.h>
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#include <platform/soc/chipid.h>
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#include <platform/soc/hwclocks.h>
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#include <platform/soc/pmgr.h>
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bool chipid_get_current_production_mode(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_XTRCT(rCFG_FUSE0) != 0;
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}
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bool chipid_get_raw_production_mode(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_XTRCT(rCFG_FUSE0_RAW) != 0;
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}
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void chipid_clear_production_mode(void)
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{
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rCFG_FUSE0 &= ~MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_UMASK;
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}
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bool chipid_get_secure_mode(void)
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{
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// demotion only applies to the SEP, so iBoot always reads
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// the raw value for secure mode (<rdar://problem/15182573>)
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return MINIPMGR_FUSE_CFG_FUSE0_SECURE_MODE_XTRCT(rCFG_FUSE0_RAW);
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}
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uint32_t chipid_get_security_domain(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_SECURITY_DOMAIN_XTRCT(rCFG_FUSE0);
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}
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uint32_t chipid_get_board_id(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_BID_XTRCT(rCFG_FUSE0);
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}
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uint32_t chipid_get_minimum_epoch(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_MINIMUM_EPOCH_XTRCT(rCFG_FUSE0);
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}
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uint32_t chipid_get_chip_id(void)
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{
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return 0x8002;
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}
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uint32_t chipid_get_chip_revision(void)
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{
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uint32_t fuse_val = MINIPMGR_FUSE_CFG_FUSE4_DEV_VERSION_XTRCT(rCFG_FUSE4);
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// we use 4 bits for base layer and 4 bits for metal,
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// the fuses use 3 for each
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return (fuse_val & 0x7) | (((fuse_val >> 3) & 0x7) << 4);
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}
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uint32_t chipid_get_osc_frequency(void)
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{
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return OSC_FREQ;
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}
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uint64_t chipid_get_ecid_id(void)
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{
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return ((uint64_t)rECIDHI << 32) | rECIDLO;
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}
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uint64_t chipid_get_die_id(void)
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{
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return ((uint64_t)rECIDHI << 32) | rECIDLO;
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}
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uint32_t chipid_get_soc_voltage(uint32_t index)
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{
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uint32_t soc_voltage = 0;
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return soc_voltage;
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}
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uint32_t chipid_get_cpu_voltage(uint32_t index)
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{
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uint32_t cpu_voltage = 0;
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return cpu_voltage;
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}
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uint32_t chipid_get_ram_voltage(uint32_t index)
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{
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uint32_t sram_voltage = 0;
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return sram_voltage;
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}
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bool chipid_get_fuse_lock(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE1_AP_LOCK_XTRCT(rCFG_FUSE1) != 0;
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}
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void chipid_set_fuse_lock(bool locked)
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{
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if (locked) {
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rCFG_FUSE1 |= MINIPMGR_FUSE_CFG_FUSE1_AP_LOCK_INSRT(1);
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asm("dsb sy");
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if (!chipid_get_fuse_lock()) {
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panic("Failed to lock fuses\n");
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}
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}
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}
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bool chipid_get_fuse_seal(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE1_SEAL_FUSES_XTRCT(rCFG_FUSE1) != 0;
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}
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uint32_t chipid_get_fuse_revision(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE4_REV_XTRCT(rCFG_FUSE4);
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}
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uint32_t chipid_get_total_rails_leakage()
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{
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uint32_t total_leakage;
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uint32_t leakage_data0;
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uint8_t leakage_data1;
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leakage_data0 = rCFG_FUSE5;
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leakage_data1 = (rCFG_FUSE4 >> 31) & 1;
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total_leakage = ((leakage_data0 >> 28) & 0xf) + 1; // soc_sram: cfg_fuse4[31:28]
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total_leakage += ((leakage_data0 >> 24) & 0xf) + 1; // cpu_sram: cfg_fuse4[27:24]
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total_leakage += ((leakage_data0 >> 16) & 0xff) + 1; // gpu: cfg_fuse4[23:16]
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total_leakage += ((leakage_data0 >> 8) & 0xff) + 1; // soc: cfg_fuse4[15:8]
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total_leakage += ((((leakage_data0 >> 0) & 0xff) << 1) | leakage_data1) + 1; // cpu: cfg_fuse4[7:0], cfg_fuse4[31]
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return total_leakage;
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}
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@@ -0,0 +1,20 @@
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# Copyright (C) 2013 Apple Inc. All rights reserved.
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#
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# This document is the property of Apple Inc.
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# It is considered confidential and proprietary.
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#
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# This document may not be reproduced or transmitted in any form,
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# in whole or in part, without the express written permission of
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# Apple Inc.
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#
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LOCAL_DIR := $(GET_LOCAL_DIR)
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OPTIONS += \
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WITH_HW_PLATFORM_CHIPID=1
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ALL_OBJS += $(LOCAL_DIR)/chipid.o
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ifeq ($(SUB_PLATFORM),t8002)
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ALL_OBJS += \
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$(LOCAL_DIR)/tunables_pmgr_t8002.o
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endif
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@@ -0,0 +1,119 @@
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/*
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* Copyright (C) 2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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/* This file contains Tunables for t8002 */
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#include <platform/tunables.h>
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#include <platform/soc/chipid.h>
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#include <platform/soc/hwregbase.h>
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#include <soc/module/address_map.h>
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/**************************************** BEGIN CHIP_REVISION_B0 ****************************************/
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#include <soc/t8002/b0/tunable/minipmgr.h>
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#include <soc/t8002/b0/tunable/pmgr.h>
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#include <soc/t8002/b0/tunable/cpu_fabric.h>
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#include <soc/t8002/b0/tunable/nrt_fabric.h>
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#include <soc/t8002/b0/tunable/uvdc.h>
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#include <soc/t8002/b0/tunable/pio_wrap.h>
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static const struct tunable_struct pmgr_tunable_t8002_b0[] = {
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PMS_PMGR_DEFAULT_TUNABLES_T8002_B0
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};
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static const struct tunable_struct minipmgr_tunable_t8002_b0[] = {
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AOP_MINIPMGR_DEFAULT_TUNABLES_T8002_B0
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};
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static const struct tunable_struct cpu_fabric_tunable_t8002_b0[] = {
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PIO_CPU_FABRIC_DEFAULT_TUNABLES_T8002_B0
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};
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static const struct tunable_struct nrt_fabric_tunable_t8002_b0[] = {
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PIO_NRT_FABRIC_DEFAULT_TUNABLES_T8002_B0
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};
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static const struct tunable_struct uvdc_tunable_t8002_b0[] = {
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PMS_UVDC_DEFAULT_TUNABLES_T8002_B0
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};
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static const struct tunable_struct pio_wrap_tunable_t8002_b0[] = {
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PIO_PIO_WRAP_DEFAULT_TUNABLES_T8002_B0
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};
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/***************************************** END CHIP_REVISION_B0 *****************************************/
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/**************************************** BEGIN CHIP_REVISION_A0 ****************************************/
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#include <soc/t8002/a0/tunable/minipmgr.h>
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#include <soc/t8002/a0/tunable/pmgr.h>
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#include <soc/t8002/a0/tunable/cpu_fabric.h>
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#include <soc/t8002/a0/tunable/nrt_fabric.h>
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#include <soc/t8002/a0/tunable/uvdc.h>
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#include <soc/t8002/a0/tunable/pio_wrap.h>
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static const struct tunable_struct pmgr_tunable_t8002_a0[] = {
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PMS_PMGR_DEFAULT_TUNABLES_T8002_A0
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};
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static const struct tunable_struct minipmgr_tunable_t8002_a0[] = {
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AOP_MINIPMGR_DEFAULT_TUNABLES_T8002_A0
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};
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static const struct tunable_struct cpu_fabric_tunable_t8002_a0[] = {
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PIO_CPU_FABRIC_DEFAULT_TUNABLES_T8002_A0
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};
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static const struct tunable_struct nrt_fabric_tunable_t8002_a0[] = {
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PIO_NRT_FABRIC_DEFAULT_TUNABLES_T8002_A0
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};
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static const struct tunable_struct uvdc_tunable_t8002_a0[] = {
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PMS_UVDC_DEFAULT_TUNABLES_T8002_A0
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};
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static const struct tunable_struct pio_wrap_tunable_t8002_a0[] = {
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PIO_PIO_WRAP_DEFAULT_TUNABLES_T8002_A0
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};
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/***************************************** END CHIP_REVISION_A0 *****************************************/
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const struct tunable_chip_struct tunables_pmgr[] = {
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// B0
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{CHIP_REVISION_B0, PMS_PMGR_PADDR_T8002_B0, pmgr_tunable_t8002_b0, NULL, true},
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{CHIP_REVISION_B0, AOP_MINIPMGR_PADDR_T8002_B0, minipmgr_tunable_t8002_b0, NULL, false},
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{CHIP_REVISION_B0, PIO_CPU_FABRIC_PADDR_T8002_B0, cpu_fabric_tunable_t8002_b0, NULL, true},
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{CHIP_REVISION_B0, PIO_NRT_FABRIC_PADDR_T8002_B0, nrt_fabric_tunable_t8002_b0, NULL, true},
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{CHIP_REVISION_B0, PMS_UVDC_PADDR_T8002_B0, uvdc_tunable_t8002_b0, NULL, true},
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{CHIP_REVISION_B0, PIO_PIO_WRAP_PADDR_T8002_B0, pio_wrap_tunable_t8002_b0, NULL, true},
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// A0
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{CHIP_REVISION_A0, PMS_PMGR_PADDR_T8002_A0, pmgr_tunable_t8002_a0, NULL, true},
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{CHIP_REVISION_A0, AOP_MINIPMGR_PADDR_T8002_A0, minipmgr_tunable_t8002_a0, NULL, false},
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{CHIP_REVISION_A0, PIO_CPU_FABRIC_PADDR_T8002_A0, cpu_fabric_tunable_t8002_a0, NULL, true},
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{CHIP_REVISION_A0, PIO_NRT_FABRIC_PADDR_T8002_A0, nrt_fabric_tunable_t8002_a0, NULL, true},
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{CHIP_REVISION_A0, PMS_UVDC_PADDR_T8002_A0, uvdc_tunable_t8002_a0, NULL, true},
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{CHIP_REVISION_A0, PIO_PIO_WRAP_PADDR_T8002_A0, pio_wrap_tunable_t8002_a0, NULL, true},
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{-1, -1, NULL, NULL, false},
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};
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const struct tunable_filtered_chip_struct tunables_filtered_pmgr[] = {
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// B0
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// Applied in OS
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{CHIP_REVISION_B0, AOP_MINIPMGR_PADDR_T8002_B0 + MINIPMGR_MINI_CLKCFG_PROXY_OSC_CLK_CFG_OFFSET, AOP_MINIPMGR_PADDR_T8002_B0 + MINIPMGR_MINI_CLKCFG_XI0MUX_CLK_CFG_OFFSET, true, true},
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{CHIP_REVISION_B0, AOP_MINIPMGR_PADDR_T8002_B0 + MINIPMGR_MINI_MISC_CFG_ACG_OFFSET, AOP_MINIPMGR_PADDR_T8002_B0 + MINIPMGR_MINI_MISC_CFG_ACG_OFFSET, true, true},
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{CHIP_REVISION_B0, PMS_PMGR_PADDR_T8002_B0 + PMGR_MISC_CFG_ACG_OFFSET, PMS_PMGR_PADDR_T8002_B0 + PMGR_MISC_CFG_ACG_OFFSET, true, true},
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// A0
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// Applied in OS
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{CHIP_REVISION_A0, AOP_MINIPMGR_PADDR_T8002_A0 + MINIPMGR_MINI_CLKCFG_PROXY_OSC_CLK_CFG_OFFSET, AOP_MINIPMGR_PADDR_T8002_A0 + MINIPMGR_MINI_CLKCFG_XI0MUX_CLK_CFG_OFFSET, true, true},
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{CHIP_REVISION_A0, AOP_MINIPMGR_PADDR_T8002_A0 + MINIPMGR_MINI_MISC_CFG_ACG_OFFSET, AOP_MINIPMGR_PADDR_T8002_A0 + MINIPMGR_MINI_MISC_CFG_ACG_OFFSET, true, true},
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{CHIP_REVISION_A0, PMS_PMGR_PADDR_T8002_A0 + PMGR_MISC_CFG_ACG_OFFSET, PMS_PMGR_PADDR_T8002_A0 + PMGR_MISC_CFG_ACG_OFFSET, true, true},
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||||
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{-1, -1, -1, NULL, false},
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};
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@@ -0,0 +1,119 @@
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/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
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#include <drivers/dcs/dcs.h>
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#include <drivers/dcs/dcs_regs.h>
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#include <drivers/dcs/dcs_init_lib.h>
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#include <drivers/dram.h>
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||||
#include <drivers/miu.h>
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#include <sys.h>
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||||
#include <platform/soc/hwclocks.h>
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||||
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||||
int mcu_initialize_dram (bool resume)
|
||||
{
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||||
dcs_boottype_t boot_type;
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||||
|
||||
// Don't perform DRAM initializion if the memory controller is already
|
||||
// initialized (e.g., for SecureROM validation testing).
|
||||
if (resume || DCS_REG_READ_CH(0, rDCS_MCU_AMCCTRL) == 0) {
|
||||
clock_gate(CLK_AMC, true);
|
||||
|
||||
boot_type = (resume)? DCS_BOOT_RESUME:DCS_BOOT_COLDBOOT;
|
||||
// NOTE: Boot types AOP_DDR or AOP_AWAKE do not use this Code
|
||||
// For those cases, the Init sequence is executed by the AOP
|
||||
|
||||
// Perform the LPDDR4 Init for this type of Boot
|
||||
dcs_init(boot_type);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mcu_bypass_prep (int step)
|
||||
{
|
||||
}
|
||||
|
||||
uint64_t mcu_get_memory_size (void)
|
||||
{
|
||||
return dcs_get_memory_size();
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
void dcs_enable_slow_boot (bool enable)
|
||||
{
|
||||
if (enable) {
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||||
// switch to slow clock
|
||||
clocks_set_performance(kPerformanceMemoryLow);
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||||
spin(1);
|
||||
}
|
||||
else {
|
||||
#if !SUPPORT_FPGA
|
||||
// switch back to full-speed
|
||||
clocks_set_performance(kPerformanceMemoryFull);
|
||||
spin(1);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
void dcs_dram_workarounds(dcs_boottype_t boot_type)
|
||||
{
|
||||
/* No workarounds yet */
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Grab (Platform Specific) Tables with Definitions of Values for DCS Init & DCS Tunables
|
||||
#include <platform/dcsconfig.h>
|
||||
|
||||
#if DCS_FIXUP_PARAMS
|
||||
// Grab (Target Specific) Definition of Required Fixups to the Values for DCS Init
|
||||
#include <target/dcsfixup.h>
|
||||
#endif
|
||||
//================================================================================
|
||||
void dcs_init_config_params(dcs_config_params_t *use_dcs_params, dcs_target_t targtype)
|
||||
{
|
||||
memcpy(use_dcs_params, &dcs_params, sizeof(dcs_config_params_t));
|
||||
|
||||
#if DCS_FIXUP_PARAMS
|
||||
// This gives the particular target a chance to make target-specific changes
|
||||
dcs_init_config_fixup_params(use_dcs_params, targtype);
|
||||
#endif
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
const dcs_tunable_t *dcs_init_tunable_table(uint32_t *table_len)
|
||||
{
|
||||
if (table_len)
|
||||
*table_len = sizeof(dcs_tunables) / sizeof(dcs_tunables[0]);
|
||||
|
||||
return dcs_tunables;
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Save off calibration results to AOP_SRAM region (later to be stitched into reconfig sequence)
|
||||
// Order of registers to be saved must match the order to be restored
|
||||
volatile uint32_t *dcs_save_calibration_results(volatile uint32_t *save_region, uint32_t freq)
|
||||
{
|
||||
/* TBD */
|
||||
return NULL;
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Stitch the saved calibration results into the reconfig sequence
|
||||
// To be called immediately after stitching mcu_aop_awake_reconfig_pre_restore
|
||||
// Order of registers to be restored matches the order in the reconfig sequence
|
||||
void dcs_restore_calibration_results(volatile uint32_t *save_region)
|
||||
{
|
||||
/* TBD */
|
||||
}
|
||||
|
||||
|
||||
//================================================================================
|
||||
@@ -0,0 +1,832 @@
|
||||
/*
|
||||
* Copyright (C) 2014-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Init Sequence Library for use in:
|
||||
* Driver for the LPDDR4 compatible DRAM Control Subsystem (DCS) block
|
||||
*/
|
||||
|
||||
/*
|
||||
Summary of Steps from the Spec (Spreadsheet)
|
||||
|
||||
+ (Aa) Steps 0,1,2,3a [need to identify parameterization]
|
||||
+ (Ab) Step 3b [PMGR: set Freq to 50MHz & delay-wait]
|
||||
+ (Ac) Steps 3c,4,5 [need to identify parameterization]
|
||||
+ (B) Step 6 [Change Clk Speed]
|
||||
+ (C) Step 7 [include delay-wait from early Step 8]
|
||||
+ (D) Step 8a [Cal: CA 800MHz Vmin]
|
||||
+ (E) Step 8b [Write Regs]
|
||||
+ (F) Step 8c [Cal: CA 800MHz Vmin] (...again? should it be CS?)
|
||||
+ (G) Step 8d [Write Regs]
|
||||
+ (H) Step 9 [Write Regs]
|
||||
+ (I) Step 10 [Cal: WrLvl, RdDq, WrDq 800MHz Vmin]
|
||||
+ (J) Step 11 [Write Regs]
|
||||
+ (K) Step 12 [Cal: CA 1200MHz Vnom]
|
||||
+ (L) Step 13 [Write Regs]
|
||||
+ (M) Step 14 [Cal: WrLvl, RdDq, WrDq 1200MHz Vmin]
|
||||
+ (N) Steps 15,16,17,18,19,20 [need to identify parameterization]
|
||||
|
||||
Between these steps there is possibly a need/desire for:
|
||||
- Frequency Changes (PMGR)
|
||||
- PMU save/restore
|
||||
- debug messages
|
||||
- register dumps (DV, SiVal)
|
||||
- anything else!
|
||||
|
||||
CONFIG Table:
|
||||
Compile-Time Known:
|
||||
Type of Execution Environment CoreOS, DV, SiVal
|
||||
Type of Target SoC, FPGA, Palladium
|
||||
ChipID 0x8000, 0x8001, etc.
|
||||
Revision A0, B0, B1, etc.
|
||||
Num DCS 4, 8, etc. (Derived...!)
|
||||
Variant Flags Work-arounds, RADAR Ref., et al.
|
||||
|
||||
(Config Info know at Compile time can be subject to #if)
|
||||
|
||||
Run-Time Known:
|
||||
Type of Init ColdBoot, AOP_DDR, AOP_AWAKE
|
||||
Debug Flags Low-Level, Milestone, et al.
|
||||
|
||||
RegValue Table
|
||||
Much like today's: various values for various registers
|
||||
Sensitive to ChipID (also Target type?)
|
||||
(Internal static alloc (Complete Table Fill-in within Init function):
|
||||
Fill in Values (per ChipID/Rev & Target-type)
|
||||
return pointer to caller
|
||||
(Allows customization by caller before use)
|
||||
|
||||
TODO:
|
||||
- Convert to using SPDS for register names, et al
|
||||
|
||||
*/
|
||||
|
||||
//================================================================================
|
||||
// API Definitions
|
||||
#include <drivers/dcs/dcs_init_lib.h>
|
||||
|
||||
extern dcs_config_t dcs_cfg;
|
||||
extern dcs_config_params_t dcs_params;
|
||||
|
||||
#if izIBOOT
|
||||
extern int debug_level_dcs;
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
void dcs_enable_autorefresh(void)
|
||||
{
|
||||
uint32_t arefen_freq0 = 0x1011013f;
|
||||
uint32_t arefen_freq1 = 0x10010000;
|
||||
|
||||
arefen_freq0 = 0x101101ff;
|
||||
|
||||
// Configure auto-refresh. Freq0 has the auto-refresh enable, so do it last.
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(3), 0x10100000);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(2), 0x10000000);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(1), arefen_freq1);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(0), arefen_freq0);
|
||||
}
|
||||
|
||||
|
||||
|
||||
//================================================================================
|
||||
// Implementing the Various Steps of the DCS Init, per Specification
|
||||
// Based on AMC Init Spec (Spreadsheet)
|
||||
// - Supporting Maui: Spec (v??)
|
||||
//================================================================================
|
||||
// Step 0: AMC Prolog
|
||||
//================================================================================
|
||||
void dcs_init_Prolog(void)
|
||||
{
|
||||
// NOTE: between the Compiler and the Optimization, this should vanish for non-FPGA builds
|
||||
if (izFPGA && izColdBoot) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 1);
|
||||
delay_for_us(200);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 0);
|
||||
delay_for_us(200);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 1);
|
||||
delay_for_us(200);
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 1: AMC Initial Configuration
|
||||
//================================================================================
|
||||
void dcs_init_AMC_Initial_Config(void)
|
||||
{
|
||||
uint32_t i,n;
|
||||
|
||||
// rdar://problem/19137387: this applies to Maui A1 and B0, as well as other SoCs before Cayman
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_CHARGEPUMP, 0x00000068);
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_LDO, 0x00000004);
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_SPLLPWRDNCFG, 0x00000011);
|
||||
|
||||
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
for (n = 0; n < dcs_params.num_freqchngctl_regs; n++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL_FREQ(n, i), dcs_params.freq[i].freqchngctl[n]);
|
||||
|
||||
// This register write to be skipped for Maui A0/A1, but written to for B0 & later, and all other SoCs
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0))
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGTIM_FREQ(i), dcs_params.freq[i].freqchngtim);
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQCALVREFCODECONTROL, dcs_params.wrdqcalvrefcodecontrol);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQCALVREFCODECONTROL, dcs_params.rddqcalvrefcodecontrol);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MODEREG, 0x120c90b8);
|
||||
|
||||
|
||||
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTCTRL(i), dcs_params.dllupdtctrl);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LAT_FREQ(0), dcs_params.freq[0].lat);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LAT_FREQ(1), dcs_params.freq[1].lat);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PHYRDWRTIM_FREQ(i), dcs_params.freq[i].phyrdwrtim);
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_CASPCH_FREQ(i), dcs_params.freq[i].caspch);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ACT_FREQ(i), dcs_params.freq[i].act);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_FREQ(i), dcs_params.freq[i].autoref);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_SELFREF_FREQ(i), dcs_params.freq[i].selfref);
|
||||
|
||||
if (i == 0) dcs_reg_write_all_chan(rDCS_MCU_MODEREG, dcs_params.modereg);
|
||||
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_PARAMS, dcs_params.autoref_params);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PDN, dcs_params.pdn);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_DERATE_FREQ(0), dcs_params.freq[0].derate);
|
||||
|
||||
// These register writes to be skipped for Maui A0/A1, but written to for B0 & later, and all other SoCs
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0))
|
||||
for(i = 1; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_DERATE_FREQ(i), dcs_params.freq[i].derate);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LAT_FREQ(i), dcs_params.freq[i].lat2);
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_TAT_FREQ(i), dcs_params.freq[i].tat);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_RNKCFG, dcs_params.rnkcfg);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MIFQMAXCTRL_FREQ(0), dcs_params.freq[0].mifqmaxctrl);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MIFQMAXCTRL_FREQ(3), dcs_params.freq[3].mifqmaxctrl);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PWRMNGTEN, 0);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, 0x00002000);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCTRL, 0x00000002);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MCPHYUPDTPARAM, 0x15030000);
|
||||
|
||||
dcs_reg_write(rAMC_AMCEN, 0x80010001);
|
||||
dcs_reg_write(rAMC_AIUADDRBANKHASH(2), 0x000036db);
|
||||
dcs_reg_write(rAMC_AIUADDRBANKHASH(1), 0x00005b6d);
|
||||
dcs_reg_write(rAMC_AIUADDRBANKHASH(0), 0x00006db6);
|
||||
dcs_reg_write(rAMC_ADDRMAPMODE, 0x00000002);
|
||||
dcs_reg_write(rAMC_ADDRCFG, 0x00030201);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 2: AMP Initial Configuration
|
||||
//================================================================================
|
||||
void dcs_init_AMP_Initial_Config(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPEN(i), 0x00000001);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_CA, i), dcs_params.freq[i].cavref);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_ODTENABLE_F(0), dcs_params.freq[0].odt_enable);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_ODTENABLE_F(1), dcs_params.freq[1].odt_enable);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_ODTENABLE_F(3), dcs_params.freq[3].odt_enable);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ0, i), dcs_params.freq[i].dqvref);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ1, i), dcs_params.freq[i].dqvref);
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_CNTL(AMP_CA), dcs_params.casdllupdatectrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_CNTL(AMP_DQ0), dcs_params.dqsdllupdatectrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_CNTL(AMP_DQ1), dcs_params.dqsdllupdatectrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step2);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step2);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step2 & 0x7, 0x0);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step2 & 0x7, 0x0);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ0), dcs_params.wrdqdqssdllctrl_step2);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ1), dcs_params.wrdqdqssdllctrl_step2);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ0), dcs_params.wrdqdqssdllctrl_step2 & 0x7, 0x0);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ1), dcs_params.wrdqdqssdllctrl_step2 & 0x7, 0x0);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, dcs_params.cawrlvlsdllcode);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, dcs_params.cawrlvlsdllcode & 0x300, 0x000);
|
||||
|
||||
if (!izFPGA)
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLLOCKTIM(i), dcs_params.dlllocktim);
|
||||
|
||||
if(dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSPDENALWYSON(AMP_DQ0), 0x00000001);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSPDENALWYSON(AMP_DQ1), 0x00000001);
|
||||
}
|
||||
|
||||
// These register writes to be skipped for Maui A0/A1
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
for(i = 1; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMPCA_DFICALTIMING_F(i), dcs_params.freq[i].cadficaltiming);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ0, i), dcs_params.freq[i].dqdficaltiming);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ1, i), dcs_params.freq[i].dqdficaltiming);
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MDLLCODE_CAP_CNTL(AMP_DQ0), 0x00000002);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MDLLCODE_CAP_CNTL(AMP_DQ1), 0x00000002);
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALTIMING_F(0), dcs_params.rdwrdqcaltiming_f0);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALTIMING_F(1), dcs_params.rdwrdqcaltiming_f1);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDWRDQCALTIMINGCTRL(1), dcs_params.rdwrdqcaltimingctrl1);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDWRDQCALTIMINGCTRL(2), dcs_params.rdwrdqcaltimingctrl2);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDDQCALPATPRBS4I, dcs_params.rddqcalpatprbs4i);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATPRBS4I, dcs_params.wrdqcalpatprbs4i);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATPRBS7(0), 0x87654321);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATPRBS7(1), 0xcdedcba9);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATPRBS7(2), 0x456789ab);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATPRBS7(3), 0x5fa63123);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATINVERTMASK, 0x55550000);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQCALWINDOW_F(0), dcs_params.freq[0].rddqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQCALWINDOW_F(0), dcs_params.freq[0].wrdqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQCALWINDOW_F(1), dcs_params.freq[1].rddqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQCALWINDOW_F(1), dcs_params.freq[1].wrdqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MAXRDDQS_SDLL_MULFACTOR, dcs_params.maxrddqssdllmulfactor);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MAXWRDQ_SDLL_MULFACTOR, 0x00a00f0f);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MAXWRDQS_SDLL_MULFACTOR, dcs_params.maxwrdqssdllmulfactor);
|
||||
|
||||
// These register writes to be skipped for Maui A0/A1
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_RDDQSMULFACTOR(AMP_DQ0), 0x20181000);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_RDDQSMULFACTOR(AMP_DQ1), 0x20181000);
|
||||
}
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDCAPCFG_FREQ(AMP_DQ0, i), dcs_params.freq[i].rdcapcfg);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDCAPCFG_FREQ(AMP_DQ1, i), dcs_params.freq[i].rdcapcfg);
|
||||
}
|
||||
|
||||
if (!izFPGA) {
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTCTRL(i), dcs_params.dllupdtctrl1);
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTINTVL(AMP_CA), dcs_params.dllupdtintvl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTINTVL(AMP_DQ0), dcs_params.dllupdtintvl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTINTVL(AMP_DQ1), dcs_params.dllupdtintvl);
|
||||
|
||||
for(i = AMP_DQ0 ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLEN(i), 0x00000100);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_IMPCALCONTROL3, 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DCCCONTROL, dcs_params.dcccontrol);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DCCTIMER, 0x00000190);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALDYNHALFCLKDLYCTRL, 0x00000001);
|
||||
|
||||
|
||||
// AMPH configuration
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CB_DRIVESTR, dcs_params.cbdrivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CB_IMPCTL, 0x0f001c2b);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CK_WKPUPD, 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CB_IOCTL, dcs_params.cbioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CK_DRIVESTR, dcs_params.ckdrivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CK_IOCTL, dcs_params.ckioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_DRIVESTR, dcs_params.b0drivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_IOCTL, dcs_params.b0ioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_ODT, dcs_params.b0odt);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_ODTCTRL, dcs_params.b0odtctrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_DRIVESTR, dcs_params.b1drivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_ODTCTRL, dcs_params.b1odtctrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_IOCTL, dcs_params.b1ioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_ODT, dcs_params.b1odt);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_DRIVESTR, dcs_params.dqs0drivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_IOCTL, dcs_params.dqs0ioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_ODT, dcs_params.dqs0odt);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_ZDETBIASEN, dcs_params.dqs0zdetbiasen);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_ODTCTRL, dcs_params.dqs0odtctrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_DRIVESTR, dcs_params.dqs1drivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_IOCTL, dcs_params.dqs1ioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_ODT, dcs_params.dqs1odt);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_ZDETBIASEN, dcs_params.dqs1zdetbiasen);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_ODTCTRL, dcs_params.dqs1odtctrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DBG_REG0, 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_ZCAL_FSM(1), dcs_params.zcalfsm1);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_ZCAL_FSM(0), dcs_params.zcalfsm0);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_SPARE(0), dcs_params.spare0);
|
||||
|
||||
|
||||
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPINIT(i), 0x00000001);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DFICALTIMING, dcs_params.dficaltiming);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDDQCALTVREF, dcs_params.hwrddqcaltvref);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 3: Self-Refresh Exit
|
||||
//================================================================================
|
||||
void dcs_init_Self_Refresh_Exit_a(void)
|
||||
{
|
||||
// Wait 5 us after Impedence Calibration to avoid McPhyPending
|
||||
// preventing the SRFSM from exiting SR.
|
||||
dcs_spin(5, "after Imp. Cal.");
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFPARAM, dcs_params.arefparam);
|
||||
|
||||
for(int i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_FREQ(i), dcs_params.freq[i].autoref2);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_PARAMS, dcs_params.autoref_params2);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc);
|
||||
// M8 Bug radar #20346417, two writes to ensure propogation
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LONGSR, dcs_params.longsr);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LONGSR, dcs_params.longsr);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MCPHYUPDTPARAM, 0x15030004);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_DIV_CLK_SELECT, 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_RECONFIGSWRESETCONTROL, 0x0000003c);
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_RECONFIGSWRESETTRIGGER, 0x00000001);
|
||||
// Wait 20ns
|
||||
dcs_spin(1, NULL);
|
||||
dcs_reg_poll(rAMC_PIO_ACCESS_CFG, 0x1, 0x1);
|
||||
|
||||
}
|
||||
|
||||
//========================================
|
||||
// Caller Code should:
|
||||
// - Change Frequency to 50MHz
|
||||
//========================================
|
||||
|
||||
void dcs_init_Self_Refresh_Exit_b(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCTRL, 0x00000003);
|
||||
|
||||
|
||||
if (!izFPGA) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_IMPCALCMD, 0x00000001);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_IMPCALCMD, 0x01, 0x00);
|
||||
}
|
||||
|
||||
if (izResume)
|
||||
dcs_enable_autorefresh();
|
||||
|
||||
dcs_spin(2200, "After Enable Auto-Refresh");
|
||||
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, dcs_params.freqchngctl_step3);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_FREQCHNGCTL, 0x10000, 0x00000);
|
||||
dcs_spin(2, "After SoC Update");
|
||||
}
|
||||
|
||||
// Resume-Boot and Cold-Boot use different Exit commands for Self-Refresh
|
||||
// Issue self-refresh exit cmd for resume boot with MPC
|
||||
int n = (izColdBoot)? 0x00000000:0x00004000;
|
||||
// Issue self-refresh exit cmd for resume boot with MPC
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MRINITCMD_0, n);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MRINITCMD_0, n | 0x1);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_MRINITCMD_0, 0x01, 0x00);
|
||||
|
||||
dcs_spin(2, NULL);
|
||||
|
||||
dcs_reg_write(rGLBTIMER_CHEN, (1 << dcs_cfg.num_dcs) - 1);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 4: DRAM Reset, ZQ Calibration & Configuration (cold boot only)
|
||||
//================================================================================
|
||||
void dcs_init_ZQ_Cal_Cfg(void)
|
||||
{
|
||||
// ZQ calibration START MPC cmd
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0, 0x4f);
|
||||
// wait 1us for tZQCAL
|
||||
dcs_spin(1, "tZQCAL");
|
||||
|
||||
// ZQ calibration LATCH MPC cmd
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0, 0x51);
|
||||
// wait 10ns for tZQLAT
|
||||
dcs_spin(1, "tZQLAT");
|
||||
|
||||
if (izColdBoot) {
|
||||
// MR2 register (read/write latency)
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x2, 0x0);
|
||||
// MR1 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x1, 0x8e);
|
||||
// MR3 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x3, dcs_params.mr3cmd);
|
||||
// MR22 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x16, 0x0);
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xb, 0x0);
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xd, dcs_params.mr13cmd);
|
||||
|
||||
// MR12 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xc, 0x4d);
|
||||
// MR14 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xe, 0x4d);
|
||||
// MR23 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x17, 0x80);
|
||||
|
||||
uint32_t patinvertmask = (DCS_REG_READ_CH(0, rDCS_AMP_HWRDDQCALPATPRBS4I) >> 16) & 0xffff;
|
||||
uint32_t prbs = DCS_REG_READ_CH(0, rDCS_AMP_HWWRDQCALPATPRBS4I);
|
||||
|
||||
// MR15 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xf, patinvertmask & 0xff);
|
||||
// MR20 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x14, (patinvertmask >> 8) & 0xff);
|
||||
// MR32 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x20, prbs & 0xff);
|
||||
// MR40 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x28, (prbs >> 8) & 0xff);
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 5a: AddrConfig Configuration
|
||||
//================================================================================
|
||||
void dcs_init_AddrCfg_Cfg(void)
|
||||
{
|
||||
dcs_reg_write(rAMC_ADDRCFG, dcs_params.addrcfg);
|
||||
|
||||
}
|
||||
|
||||
//========================================
|
||||
// Caller Code should:
|
||||
// - Use MR Cmds to Query the Device
|
||||
//========================================
|
||||
|
||||
//================================================================================
|
||||
// Step 5b: Total Mem Size Config
|
||||
//================================================================================
|
||||
void dcs_init_TotalSize_Cfg(uint32_t total_size_Mbytes)
|
||||
{
|
||||
|
||||
dbgprintf(DCS_DBG_ASSESS_CONFIG, "Memory_size: %llu bytes\n",
|
||||
(((uint64_t)total_size_Mbytes) * MEG));
|
||||
dcs_reg_write(rAMC_AIUPRTBADDR, dcs_params.aiuprtbaddr);
|
||||
dcs_reg_write(rAMC_AIUCHNLDEC, dcs_params.chnldec);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 6: Switch from boot-clock speed to normal operation speed
|
||||
//================================================================================
|
||||
void dcs_init_Reenable_AMC_Scheduler(void)
|
||||
{
|
||||
// Wait 5 us before freq change to make sure all refreshes have been flushed
|
||||
dcs_spin(5, "After Refresh");
|
||||
|
||||
// Enable (again) the AMC Scheduler
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCTRL, 0x00000003);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 7: Setup registers for CA calibration for bucket 1
|
||||
//================================================================================
|
||||
void dcs_init_CA_Cal_Setup_Freq1(void)
|
||||
{
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xd, dcs_params.mr13cmd_step7);
|
||||
|
||||
if (izColdBoot) {
|
||||
if (izFPGA) {
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xb, 0x00);
|
||||
} else {
|
||||
// MR2 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x2, 0x52);
|
||||
// MR1 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x1, 0xae);
|
||||
// MR3 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x3, dcs_params.mr3cmd_step7);
|
||||
// MR22 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x16, dcs_params.mr22cmd);
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xb, dcs_params.mr11cmd);
|
||||
// MR12 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xc, 0x11);
|
||||
// MR14 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xe, 0x11);
|
||||
}
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x00000200);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x0200, 0x0000);
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 8: AMP Dynamic CA Vref Timing Calibration at Vmin 800MHz
|
||||
//================================================================================
|
||||
void dcs_init_CA_Cal_Freq1(void)
|
||||
{
|
||||
// Nothing to be done at this step for cold boot
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 9: Setup registers for DQ calibration for bucket 1
|
||||
//================================================================================
|
||||
void dcs_init_DQ_Cal_Setup_Freq1_a(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (izColdBoot) {
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xd, dcs_params.mr13cmd_step9);
|
||||
}
|
||||
|
||||
dcs_spin(1, NULL);
|
||||
|
||||
if(izResume) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PWRMNGTEN, 0x00000002);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, 0x01008888);
|
||||
|
||||
for(i = AMP_DQ0 ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(i), 0xFF00000C);
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_DEFER_EN(i), 0x00000000);
|
||||
for(i = AMP_DQ0; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MDLLOVRRD(i), 0x00000000);
|
||||
}
|
||||
}
|
||||
|
||||
// Caller code should change frequency to bucket 1
|
||||
void dcs_init_DQ_Cal_Setup_Freq1_b(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, dcs_params.freqchngctl_step9);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_FREQCHNGCTL, 0x10000, 0x00000);
|
||||
|
||||
// Wait 2us for the soc update to finish
|
||||
dcs_spin(2, NULL);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 10: PHY write DQ calibration
|
||||
//================================================================================
|
||||
void dcs_init_wrdq_skew(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSDQ_SKEWCTL(AMP_DQ0), 0x06000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSDQ_SKEWCTL(AMP_DQ1), 0x06000000);
|
||||
}
|
||||
|
||||
void dcs_init_post_wrlvl(void)
|
||||
{
|
||||
if(dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ0), 0x00000010);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ1), 0x00000010);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 11: Setup registers for CA calibration for bucket 0
|
||||
//================================================================================
|
||||
void dcs_init_CA_Cal_Setup_Freq0(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
|
||||
if(dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ0), 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ1), 0x00000000);
|
||||
}
|
||||
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, dcs_params.mr13cmd_step11);
|
||||
if (!izFPGA) {
|
||||
// MR2 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x02, dcs_params.mr2cmd_step11);
|
||||
// MR1 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x01, dcs_params.mr1cmd_step11);
|
||||
// MR3 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x03, dcs_params.mr3cmd_step11);
|
||||
}
|
||||
|
||||
// MR22 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x16, dcs_params.mr22cmd_step11);
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0b, (izFPGA) ? 0x00 : dcs_params.mr11cmd_step11);
|
||||
// MR12 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0c, dcs_params.mr12cmd_step11);
|
||||
// MR14 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0e, dcs_params.mr14cmd_step11);
|
||||
|
||||
if((dcs_params.supported_freqs & DCS_FREQ(1)) == 0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x00000200);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x200, 0x000);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 12: AMP Dynamic CA Timing Calibration
|
||||
//================================================================================
|
||||
|
||||
//================================================================================
|
||||
// Step 13: Setup registers for DQ calibration for bucket 0
|
||||
//================================================================================
|
||||
void dcs_init_DQ_Cal_Setup_Freq0_a(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, dcs_params.mr13cmd_step13);
|
||||
|
||||
// Wait 1 us
|
||||
dcs_spin(1, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
void dcs_init_DQ_Cal_Setup_Freq0_b(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, 0x00010000);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_FREQCHNGCTL, 0x10000, 0x00000);
|
||||
|
||||
// Wait 2us for the soc update to finish
|
||||
dcs_spin(2, NULL);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 14: AMP Dynamic DQ Calibration
|
||||
//================================================================================
|
||||
|
||||
//================================================================================
|
||||
// Step 15: Setup Registers for Boot
|
||||
//================================================================================
|
||||
void dcs_init_Reg_for_Boot(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_SPARE(0), 0x0000040b);
|
||||
|
||||
#ifndef DCS_RUN_AT_50MHZ
|
||||
if (izColdBoot) {
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, dcs_params.mr13cmd_step15);
|
||||
}
|
||||
#endif
|
||||
|
||||
if(izFPGA && !(dcs_params.supported_freqs & DCS_FREQ(1)))
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, 0x50);
|
||||
|
||||
// Wait 1 us
|
||||
dcs_spin(1, NULL);
|
||||
|
||||
if (izColdBoot) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, dcs_params.freqchngctl_step15);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ0), 0xff000008);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ1), 0xff000008);
|
||||
|
||||
|
||||
#if !DCS_DO_CALIBRATION
|
||||
// skip these for all silicon targets, where calibration is performed, also skip for any Maui A1 target
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQSDLL_DLYSEL(AMP_DQ0), 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQSDLL_DLYSEL(AMP_DQ1), 0x00000000);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step15);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step15);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step15 & 0x7, 0x0);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step15 & 0x7, 0x0);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 16: Enable Other Features
|
||||
//================================================================================
|
||||
void dcs_init_MoreFeatures(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFPARAM, dcs_params.arefparam);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc2);
|
||||
|
||||
dcs_reg_write(rAMC_QBREN, 0x00110000);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_QBREN, 0x00000001);
|
||||
|
||||
if (izColdBoot)
|
||||
dcs_enable_autorefresh();
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_DYN_ISEL_ASRTIME, dcs_params.b0dyniselasrtime);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_DYN_ISEL, dcs_params.b0dynisel);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_DYN_ISEL, dcs_params.b1dynisel);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_DCD_IOCTL, 0x00010000);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_DCD_IOCTL, 0x00090000);
|
||||
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 17: Enable Fast Critical Word Forwarding Feature
|
||||
//================================================================================
|
||||
void dcs_init_Fast_Critical_Word_Forwarding(void)
|
||||
{
|
||||
|
||||
uint32_t aiuprt_rd_cwf = 0x00121200;
|
||||
uint32_t qbrparam2 = 0x00004555;
|
||||
|
||||
if(izFPGA) {
|
||||
aiuprt_rd_cwf = 0x00000000;
|
||||
qbrparam2 = 0x00000555;
|
||||
}
|
||||
|
||||
dcs_reg_write(rAMC_AIUPRT_RD_CWF, aiuprt_rd_cwf);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_QBRPARAM2, qbrparam2);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_QBRPARAM, dcs_params.qbrparam);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_QBREN, dcs_params.qbren);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 18: Enable Power- and Clock-Gating Features; Config MCC and Global Timers
|
||||
//================================================================================
|
||||
void dcs_init_Gating_Global_Timers(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPCLK(AMP_CA), dcs_params.caampclk);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPCLK(AMP_DQ0), dcs_params.dqampclk);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPCLK(AMP_DQ1), dcs_params.dqampclk);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_MDLLPWRDNCFG(0), 0x00000001);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PWRMNGTEN, dcs_params.pwrmngten);
|
||||
|
||||
if(!izFPGA) {
|
||||
dcs_reg_write(rAMC_IDLE2BCG_CONTROL, 0x00000001);
|
||||
dcs_reg_write_all_chan(rDCS_AON_IDLE2BCG_CONTROL, 0x00000001);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_IDLE_EXTEND_CONTROL, 0x00000001);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCLKPWRGATE, 0x050a1100);
|
||||
dcs_reg_write(rAMC_PWRMNGTPARAM, 0x001d0140);
|
||||
dcs_reg_write(rAMC_PSQWQCTL1, 0x00240100);
|
||||
}
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQCALBURSTLENMODE, 0x00000011);
|
||||
|
||||
|
||||
// Global Timer Setup
|
||||
dcs_reg_poll(rGLBTIMER_FREQCHNG_ACTIVE, 0x1, 0x0);
|
||||
dcs_reg_write(rGLBTIMER_PMGRWAKEUPCFG, 0x0001ff);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQ2ALLBANKDLY(0), 0x00f000f0);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQ2ALLBANKDLY(1), 0x00f000f0);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQCHNG2FREQCHNGDLY(0), 0x02400240);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQCHNG2FREQCHNGDLY(1), 0x02400240);
|
||||
dcs_reg_write(rGLBTIMER_MDLLTIMER, 0x000bb8); // 3000
|
||||
dcs_reg_write(rGLBTIMER_DCCTIMER, 0x000bb8);
|
||||
dcs_reg_write(rGLBTIMER_MDLLVOLTRAMPTIMER, 0x00004b); // 75
|
||||
dcs_reg_write(rGLBTIMER_CTRLUPDMASKTIMER, 0x00000f); // 15
|
||||
dcs_reg_write(rGLBTIMER_RDCALTIMER, 0x2dc6bb); //
|
||||
dcs_reg_write(rGLBTIMER_WRCALTIMER, 0x2dc6c0); // 3000000
|
||||
dcs_reg_write(rGLBTIMER_ZQCTIMER, 0x3d0900); // 4000000
|
||||
dcs_reg_write(rGLBTIMER_PERCAL_FREQCHNGTIMER, 0x000001); // 300000
|
||||
dcs_reg_write(rGLBTIMER_IMPCALTIMER, 0x002ee0); // 12000
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 19: ODTS read & set interval for periodic MR4 on-die Temp sensor reading
|
||||
//================================================================================
|
||||
void dcs_init_ODTS(void)
|
||||
{
|
||||
uint8_t temp[16*8]; // Far more Channels/Ranks than we are likely ever to have/need
|
||||
// INSTEAD OF: uint8_t temp[dcs_cfg.num_dcs * dcs_cfg.num_rank];
|
||||
|
||||
// MR4 read to bring memory out of self-refresh
|
||||
dcs_mrcmd(MR_READ, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x4, (uintptr_t)temp);
|
||||
// M8 Bug radar #20346417, two writes to ensure propogation
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc3);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc3);
|
||||
|
||||
// disable full scan calibrations
|
||||
if(!izFPGA)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDWRDQCALFULLSCANEN, 0x00000000);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
@@ -0,0 +1,17 @@
|
||||
# Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_DCS=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/dcs.o \
|
||||
$(LOCAL_DIR)/dcs_init_lib_t8002.o
|
||||
@@ -0,0 +1,377 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __DCSCONFIG_H
|
||||
#define __DCSCONFIG_H
|
||||
|
||||
// Needful defnitions for the initializers below
|
||||
#include <drivers/dcs/dcs.h>
|
||||
#include <drivers/dcs/dcs_regs.h>
|
||||
#include <drivers/dcs/dcs_init_lib.h>
|
||||
#include <drivers/dcs/dcs_calibration.h>
|
||||
|
||||
dcs_config_params_t dcs_params = {
|
||||
.supported_freqs = DCS_FREQ(0) | DCS_FREQ(3),
|
||||
.num_freqchngctl_regs = 5,
|
||||
.spllctrl_vco_1 = 0x00000018,
|
||||
.spllctrl_vco_2 = 0x00000015,
|
||||
.wrdqcalvrefcodecontrol = 0x0d000019,
|
||||
.rddqcalvrefcodecontrol = 0x0d000099,
|
||||
.dllupdtctrl = 0x50017350,
|
||||
.modereg = 0x120c80a4,
|
||||
.autoref_params = 0x0015005d,
|
||||
.pdn = 0x72274284,
|
||||
.rnkcfg = 0x00006061,
|
||||
.casdllupdatectrl = 0x03030305,
|
||||
.dqsdllupdatectrl = 0x00030005,
|
||||
.rdsdllctrl_step2 = 0x00ff0002,
|
||||
.wrdqdqssdllctrl_step2 = 0xff000002,
|
||||
.cawrlvlsdllcode = 0x00ff01ff,
|
||||
.dlllocktim = 0x00c801f4,
|
||||
.rdwrdqcaltiming_f0 = 0x01040304,
|
||||
.rdwrdqcaltiming_f1 = 0x01040402,
|
||||
.rdwrdqcaltimingctrl1 = 0x0000381e,
|
||||
.rdwrdqcaltimingctrl2 = 0x01100e01,
|
||||
.rddqcalpatprbs4i = 0x55553c5a,
|
||||
.wrdqcalpatprbs4i = 0x00003c5a,
|
||||
.maxrddqssdllmulfactor = 0x00a00c0c,
|
||||
.maxwrdqssdllmulfactor = 0xa0a00c0d,
|
||||
.dllupdtctrl1 = 0x80017580,
|
||||
.dllupdtintvl = 0x10200020,
|
||||
.dcccontrol = 0x10050b27,
|
||||
.cbdrivestr = 0x33838317,
|
||||
.cbioctl = 0x00020021,
|
||||
.ckdrivestr = 0x33838317,
|
||||
.ckioctl = 0x00000021,
|
||||
.b0drivestr = 0x33838317,
|
||||
.b0ioctl = 0x71500021,
|
||||
.b0odt = 0x01c00339,
|
||||
.b0odtctrl = 0x00000007,
|
||||
.b1drivestr = 0x33838317,
|
||||
.b1ioctl = 0x71500021,
|
||||
.b1odt = 0x01c00339,
|
||||
.b1odtctrl = 0x00000007,
|
||||
.dqs0drivestr = 0x33838317,
|
||||
.dqs0ioctl = 0x71500021,
|
||||
.dqs0odt = 0x01c00339,
|
||||
.dqs0zdetbiasen = 0x00060928,
|
||||
.dqs0odtctrl = 0x00000007,
|
||||
.dqs1drivestr = 0x33838317,
|
||||
.dqs1ioctl = 0x71500021,
|
||||
.dqs1odt = 0x01c00339,
|
||||
.dqs1zdetbiasen = 0x00060928,
|
||||
.dqs1odtctrl = 0x00000007,
|
||||
.zcalfsm1 = 0x005b7f7f,
|
||||
.zcalfsm0 = 0x000f0333,
|
||||
.spare0 = 0x0000000b,
|
||||
.dficaltiming = 0x05000504,
|
||||
.hwrddqcaltvref = 0x08080808,
|
||||
.arefparam = 0x0d012019,
|
||||
.autoref_params2 = 0x0015005d,
|
||||
.odtszqc = 0x00003000,
|
||||
.longsr = 0x01022008,
|
||||
.freqchngctl_step3 = 0x01010000,
|
||||
.mr3cmd = 0xf2,
|
||||
.mr13cmd = 0x18,
|
||||
.addrcfg = 0x00030201,
|
||||
.aiuprtbaddr = 0x00000010,
|
||||
.chnldec = 0x00050101,
|
||||
// steps 7-10 are skipped for M8 since freq bucket 1 not used
|
||||
.mr13cmd_step11 = 0x58,
|
||||
.mr2cmd_step11 = 0x1b,
|
||||
.mr1cmd_step11 = 0xbe,
|
||||
.mr3cmd_step11 = 0xb2,
|
||||
.mr22cmd_step11 = 0x03,
|
||||
.mr11cmd_step11 = 0x33,
|
||||
.mr12cmd_step11 = 0x19,
|
||||
.mr14cmd_step11 = 0x19,
|
||||
.mr13cmd_step13 = 0x98,
|
||||
.mr13cmd_step15 = 0x90,
|
||||
.freqchngctl_step15 = 0x00009009,
|
||||
.rdsdllctrl_step15 = 0x001d0004,
|
||||
.odtszqc2 = 0xc0003000,
|
||||
.b0dyniselasrtime = 0x00000014,
|
||||
.b0dynisel = 0x00000001,
|
||||
.b1dynisel = 0x00000009,
|
||||
.qbrparam = 0x00000000,
|
||||
.qbren = 0x00000003,
|
||||
.caampclk = 0x11000000,
|
||||
.dqampclk = 0x11000000,
|
||||
.pwrmngten = 0x00000133,
|
||||
.odtszqc3 = 0xc0003320,
|
||||
|
||||
.freq = {
|
||||
{ // 1066MHz
|
||||
.clk_period = CLK_PERIOD_1600,
|
||||
.freqchngctl = {0x18cd104d, 0x190c190e, 0xb203330b, 0xbe011b02, 0x00000316},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.lat = 0x00103285,
|
||||
.phyrdwrtim = 0x00040c08,
|
||||
.caspch = 0x43d7060a,
|
||||
.act = 0x16060c0a,
|
||||
.autoref = 0x30600078,
|
||||
.selfref = 0x6b064012,
|
||||
.derate = 0x34b3760b,
|
||||
.lat2 = 0x00112285,
|
||||
.tat = 0x01312222,
|
||||
.mifqmaxctrl = 0x00000100,
|
||||
.cavref = 0x00000003,
|
||||
.odt_enable = 0x00000001,
|
||||
.dqvref = 0x00cb00cb,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.rddqcalwindow = 0x00ff01d1,
|
||||
.wrdqcalwindow = 0x00ff0160,
|
||||
.rdcapcfg = 0x0100070c,
|
||||
.autoref2 = 0x30600070,
|
||||
},
|
||||
{ // 800MHz
|
||||
.freqchngctl = {0x18cd104d, 0x110c110e, 0xd303220b, 0xae015202, 0x00000216},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.lat = 0x00112206,
|
||||
.phyrdwrtim = 0x00050b06,
|
||||
.caspch = 0x42110408,
|
||||
.act = 0x10040908,
|
||||
.autoref = 0x24480050,
|
||||
.selfref = 0x5004b012,
|
||||
.derate = 0x28835488,
|
||||
.lat2 = 0x00112206,
|
||||
.tat = 0x01312222,
|
||||
.cavref = 0x00000000,
|
||||
.odt_enable = 0x00000001,
|
||||
.dqvref = 0x00000000,
|
||||
.cadficaltiming = 0x04000410,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.rddqcalwindow = 0x00ff01d1,
|
||||
.wrdqcalwindow = 0x00ff0160,
|
||||
.rdcapcfg = 0x2100060a,
|
||||
.autoref2 = 0x24480054,
|
||||
},
|
||||
{ // 200MHz
|
||||
.freqchngctl = {0x18cd104d, 0x590c590e, 0xf303000b, 0x8e010002, 0x00000016},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.phyrdwrtim = 0x00010b01,
|
||||
.caspch = 0x40c50402,
|
||||
.act = 0x04020302,
|
||||
.autoref = 0x09120014,
|
||||
.selfref = 0x28013012,
|
||||
.derate = 0x0c212142,
|
||||
.lat2 = 0x001110c2,
|
||||
.tat = 0x01212222,
|
||||
.cavref = 0x00000000,
|
||||
.dqvref = 0x00000000,
|
||||
.cadficaltiming = 0x04000410,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.rdcapcfg = 0x41000406,
|
||||
.autoref2 = 0x09120015,
|
||||
},
|
||||
{ // 50MHz
|
||||
.freqchngctl = {0x18cd104d, 0x4d0c4d0e, 0xf203000b, 0x8e010002, 0x00000016},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.phyrdwrtim = 0x00010901,
|
||||
.caspch = 0x40c20402,
|
||||
.act = 0x01020404,
|
||||
.autoref = 0x03050005,
|
||||
.selfref = 0x28005012,
|
||||
.derate = 0x10412082,
|
||||
.lat2 = 0x001110c2,
|
||||
.tat = 0x01212222,
|
||||
.mifqmaxctrl = 0x00000001,
|
||||
.cavref = 0x00000003,
|
||||
.odt_enable = 0x00000000,
|
||||
.dqvref = 0x00000000,
|
||||
.cadficaltiming = 0x04000410,
|
||||
.dqdficaltiming = 0x04020402,
|
||||
.rdcapcfg = 0x61000406,
|
||||
.autoref2 = 0x03050005,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
#define BIT32_MASKFULL (0xFFFFFFFF)
|
||||
#define BIT32_MASK(_n) (BIT32_MASKFULL >> (32 - (_n)))
|
||||
#define BIT32_MASK_VAL(_h,_l,_d) (((_d) & BIT32_MASK((_h) - (_l) + 1)) << (_l))
|
||||
#define BIT32_MASK_HI_LO(_h,_l) BIT32_MASK_VAL(_h,_l,BIT32_MASKFULL)
|
||||
#define DCS_MASK_VAL(_h,_l,_d) BIT32_MASK_HI_LO(_h,_l) , BIT32_MASK_VAL(_h,_l,_d)
|
||||
|
||||
// M8 A0 Tunables Specs:
|
||||
// https://seg-docs.ecs.apple.com/projects/m8//release/UserManual/tunables/amc.html dated 1/16/2015 20:07:00
|
||||
// https://seg-docs.ecs.apple.com/projects/m8//release/UserManual/tunables/amcsys_aon.html dated 1/16/2015 20:06:27
|
||||
// https://seg-docs.ecs.apple.com/projects/m8//release/UserManual/tunables/amcx.html dated 1/16/2015 11:49:17
|
||||
// https://seg-docs.ecs.apple.com/projects/m8//release/UserManual/tunables/dcsh_aon.html dated 1/2/2015 00:30:12
|
||||
// https://seg-docs.ecs.apple.com/projects/m8//release/UserManual/tunables/ampsca.html dated 1/14/2015 19:42:28
|
||||
// https://seg-docs.ecs.apple.com/projects/m8//release/UserManual/tunables/AMPSDQ0.html dated 1/14/2015 19:44:46
|
||||
// https://seg-docs.ecs.apple.com/projects/m8//release/UserManual/tunables/AMPSDQ1.html dated 1/14/2015 19:44:46
|
||||
const dcs_tunable_t dcs_tunables[] = {
|
||||
|
||||
// AMCSYS
|
||||
{ rAMC_AIUPRT_RD_GEN, DCS_MASK_VAL(3, 3, 0x1) },
|
||||
{ rAMC_AIUADDRBANKHASH(0), DCS_MASK_VAL(14, 0, 0x6db6) },
|
||||
{ rAMC_AIUADDRBANKHASH(1), DCS_MASK_VAL(14, 0, 0x5b6d) },
|
||||
{ rAMC_AIUADDRBANKHASH(2), DCS_MASK_VAL(14, 0, 0x36db) },
|
||||
|
||||
{ rAMC_AIUCHNLTM, DCS_MASK_VAL(24, 20, 0x10) },
|
||||
{ rAMC_AIUCHNLTM, DCS_MASK_VAL(16, 16, 0x1) },
|
||||
{ rAMC_AIUCHNLTM, DCS_MASK_VAL(14, 14, 0x0) },
|
||||
{ rAMC_AIUCHNLTM, DCS_MASK_VAL(13, 13, 0x1) },
|
||||
{ rAMC_AIUCHNLTM, DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rAMC_AIUCHNLTM, DCS_MASK_VAL(8, 4, 0x10) },
|
||||
{ rAMC_AIUCHNLTM, DCS_MASK_VAL(0, 0, 0x1) },
|
||||
|
||||
{ rAMC_AIURDBRSTLEN, DCS_MASK_VAL(30, 28, 0x1) },
|
||||
{ rAMC_AIURDBRSTLEN, DCS_MASK_VAL(26, 24, 0x1) },
|
||||
{ rAMC_AIURDBRSTLEN, DCS_MASK_VAL(18, 16, 0x1) },
|
||||
{ rAMC_AIURDBRSTLEN, DCS_MASK_VAL(10, 8, 0x1) },
|
||||
{ rAMC_AIURDBRSTLEN, DCS_MASK_VAL(2, 0, 0x1) },
|
||||
|
||||
{ rAMC_AIURDMAXCRD, DCS_MASK_VAL(30, 24, 0x30) },
|
||||
{ rAMC_AIURDMAXCRD, DCS_MASK_VAL(22, 16, 0x8) },
|
||||
{ rAMC_AIURDMAXCRD, DCS_MASK_VAL(14, 8, 0xc) },
|
||||
{ rAMC_AIURDMAXCRD, DCS_MASK_VAL(6, 0, 0x7f) },
|
||||
|
||||
{ rAMC_AIURDREFL, DCS_MASK_VAL(30, 24, 0x28) },
|
||||
{ rAMC_AIURDREFL, DCS_MASK_VAL(22, 16, 0x7) },
|
||||
{ rAMC_AIURDREFL, DCS_MASK_VAL(14, 8, 0xa) },
|
||||
{ rAMC_AIURDREFL, DCS_MASK_VAL(6, 0, 0x7f) },
|
||||
|
||||
{ rAMC_AIUWRBRSTLEN, DCS_MASK_VAL(30, 28, 0x1) },
|
||||
{ rAMC_AIUWRBRSTLEN, DCS_MASK_VAL(26, 24, 0x1) },
|
||||
{ rAMC_AIUWRBRSTLEN, DCS_MASK_VAL(18, 16, 0x1) },
|
||||
{ rAMC_AIUWRBRSTLEN, DCS_MASK_VAL(10, 8, 0x1) },
|
||||
{ rAMC_AIUWRBRSTLEN, DCS_MASK_VAL(2, 0, 0x1) },
|
||||
|
||||
{ rAMC_AIUWRMAXCRD, DCS_MASK_VAL(30, 24, 0x30) },
|
||||
{ rAMC_AIUWRMAXCRD, DCS_MASK_VAL(22, 16, 0x8) },
|
||||
{ rAMC_AIUWRMAXCRD, DCS_MASK_VAL(14, 8, 0xc) },
|
||||
{ rAMC_AIUWRMAXCRD, DCS_MASK_VAL(6, 0, 0x7f) },
|
||||
|
||||
{ rAMC_AIUWRREFL, DCS_MASK_VAL(30, 24, 0x28) },
|
||||
{ rAMC_AIUWRREFL, DCS_MASK_VAL(22, 16, 0x7) },
|
||||
{ rAMC_AIUWRREFL, DCS_MASK_VAL(14, 8, 0xa) },
|
||||
{ rAMC_AIUWRREFL, DCS_MASK_VAL(6, 0, 0x7f) },
|
||||
|
||||
{ rAMC_AIUCPUSPCREQ, DCS_MASK_VAL(9, 0, 0x13) },
|
||||
{ rAMC_AIUGRXSPCREQ, DCS_MASK_VAL(9, 0, 0x19) },
|
||||
{ rAMC_AIUNRTSPCREQ, DCS_MASK_VAL(9, 0, 0x19) },
|
||||
{ rAMC_AIURLTSPCREQ, DCS_MASK_VAL(9, 0, 0x13) },
|
||||
|
||||
{ rAMC_AIUWPQSCH, DCS_MASK_VAL(30, 24, 0x8) },
|
||||
{ rAMC_AIUWPQSCH, DCS_MASK_VAL(14, 8, 0x8) },
|
||||
|
||||
{ rAMC_AIUTHOTLEN, DCS_MASK_VAL(5, 5, 0x1) },
|
||||
{ rAMC_AIUTHOTLEN, DCS_MASK_VAL(4, 4, 0x1) },
|
||||
|
||||
{ rAMC_AIUTHOTLCPUPARAM, DCS_MASK_VAL(10, 4, 0x8) },
|
||||
{ rAMC_AIUTHOTLCPUPARAM, DCS_MASK_VAL(2, 2, 0x1) },
|
||||
|
||||
{ rAMC_AIUTHOTLRLTPARAM, DCS_MASK_VAL(10, 4, 0x8) },
|
||||
{ rAMC_AIUTHOTLRLTPARAM, DCS_MASK_VAL(2, 2, 0x1) },
|
||||
|
||||
{ rAMC_AIUTHOTLNRTPARAM, DCS_MASK_VAL(10, 4, 0x8) },
|
||||
{ rAMC_AIUTHOTLGRXPARAM, DCS_MASK_VAL(10, 4, 0x8) },
|
||||
|
||||
{ rAMC_AIUPUSHEN, DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rAMC_AIUPUSHEN, DCS_MASK_VAL(8, 8, 0x1) },
|
||||
|
||||
{ rAMC_AIUTHOTLCPUPARAM2, DCS_MASK_VAL(23, 23, 0x1) },
|
||||
{ rAMC_AIUTHOTLCPUPARAM2, DCS_MASK_VAL(22, 22, 0x1) },
|
||||
{ rAMC_AIUTHOTLCPUPARAM2, DCS_MASK_VAL(10, 4, 0x4) },
|
||||
|
||||
{ rAMC_AIUTHOTLRLTPARAM2, DCS_MASK_VAL(23, 23, 0x1) },
|
||||
{ rAMC_AIUTHOTLRLTPARAM2, DCS_MASK_VAL(22, 22, 0x1) },
|
||||
{ rAMC_AIUTHOTLRLTPARAM2, DCS_MASK_VAL(10, 4, 0x4) },
|
||||
|
||||
{ rAMC_AIUTHOTLNRTPARAM2, DCS_MASK_VAL(10, 4, 0x4) },
|
||||
{ rAMC_AIUTHOTLGRXPARAM2, DCS_MASK_VAL(10, 4, 0x4) },
|
||||
|
||||
{ rAMC_AIULLTSCHCTL, DCS_MASK_VAL(0, 0, 0x1) },
|
||||
{ rAMC_AIURDMAXCRD2, DCS_MASK_VAL(6, 0, 0x12) },
|
||||
{ rAMC_AIURDREFL2, DCS_MASK_VAL(6, 0, 0xf) },
|
||||
{ rAMC_AIUWRMAXCRD2, DCS_MASK_VAL(6, 0, 0x12) },
|
||||
{ rAMC_AIUWRMAXCRD2, DCS_MASK_VAL(6, 0, 0x12) },
|
||||
{ rAMC_AIUWRREFL2, DCS_MASK_VAL(6, 0, 0xf) },
|
||||
{ rAMC_AIUMEDSPCREQ, DCS_MASK_VAL(9, 0, 0x19) },
|
||||
{ rAMC_AIUTHOTLMEDPARAM, DCS_MASK_VAL(10, 4, 0x8) },
|
||||
{ rAMC_AIUTHOTLMEDPARAM2, DCS_MASK_VAL(10, 4, 0x4) },
|
||||
{ rAMC_PSQRQCTL0, DCS_MASK_VAL(31, 24, 0x1) },
|
||||
|
||||
{ rAMC_PSQRQCTL1, DCS_MASK_VAL(9, 9, 0x1) },
|
||||
{ rAMC_PSQRQCTL1, DCS_MASK_VAL(5, 5, 0x1) },
|
||||
{ rAMC_PSQRQCTL1, DCS_MASK_VAL(3, 3, 0x1) },
|
||||
{ rAMC_PSQRQCTL1, DCS_MASK_VAL(1, 1, 0x1) },
|
||||
|
||||
{ rAMC_PSQRQTIMER(0), DCS_MASK_VAL(11, 0, 0xa) },
|
||||
{ rAMC_PSQRQTIMER(1), DCS_MASK_VAL(11, 0, 0x5) },
|
||||
{ rAMC_PSQRQTIMER(2), DCS_MASK_VAL(11, 0, 0x20) },
|
||||
|
||||
{ rAMC_PSQRQBRST, DCS_MASK_VAL(28, 24, 0x4) },
|
||||
{ rAMC_PSQRQBRST, DCS_MASK_VAL(12, 8, 0x4) },
|
||||
|
||||
{ rAMC_PSQRQSCHCRD, DCS_MASK_VAL(23, 16, 0x20) },
|
||||
{ rAMC_PSQRQSCHCRD, DCS_MASK_VAL(15, 8, 0x28) },
|
||||
|
||||
{ rAMC_PSQWQCTL1, DCS_MASK_VAL(31, 16, 0x24) },
|
||||
{ rAMC_PSQWQCTL1, DCS_MASK_VAL(15, 0, 0xbb) },
|
||||
|
||||
{ rAMC_PSQWQBRST, DCS_MASK_VAL(28, 24, 0x2) },
|
||||
{ rAMC_PSQWQBRST, DCS_MASK_VAL(20, 16, 0x2) },
|
||||
{ rAMC_PSQWQBRST, DCS_MASK_VAL(12, 8, 0x2) },
|
||||
{ rAMC_PSQWQBRST, DCS_MASK_VAL(4, 0, 0x8) },
|
||||
|
||||
{ rAMC_PSQWQSCHCRD, DCS_MASK_VAL(23, 16, 0x4) },
|
||||
{ rAMC_PSQWQSCHCRD, DCS_MASK_VAL(15, 8, 0x5) },
|
||||
|
||||
{ rAMC_MCUQOS, DCS_MASK_VAL(16, 16, 0x1) },
|
||||
|
||||
{ rAMC_MCUQOSLLT, DCS_MASK_VAL(16, 16, 0x1) },
|
||||
{ rAMC_MCUQOSLLT, DCS_MASK_VAL(4, 0, 0x8) },
|
||||
|
||||
{ rAMC_ADDRMAPMODE, DCS_MASK_VAL(2, 0, 0x2) },
|
||||
|
||||
{ rAMC_PWRMNGTPARAM, DCS_MASK_VAL(31, 16, 0x30) },
|
||||
{ rAMC_PWRMNGTPARAM, DCS_MASK_VAL(15, 0, 0xfa) },
|
||||
|
||||
{ rAMC_IDLE2BCG_CONTROL, DCS_MASK_VAL(0, 0, 0x1) },
|
||||
|
||||
// AMCX
|
||||
{ rDCS_MCU_AMCCLKPWRGATE, DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_AMCCLKPWRGATE, DCS_MASK_VAL(8, 8, 0x1) },
|
||||
|
||||
{ rDCS_MCU_IDLE_EXTEND_CONTROL, DCS_MASK_VAL(0, 0, 0x1) },
|
||||
|
||||
{ rDCS_MCU_ROWHAM_CTL(0), DCS_MASK_VAL(31, 16, 0x4002) },
|
||||
{ rDCS_MCU_ROWHAM_CTL(0), DCS_MASK_VAL(0, 0, 0x1) },
|
||||
{ rDCS_MCU_ROWHAM_CTL(1), DCS_MASK_VAL(31, 16, 0x4a38) },
|
||||
{ rDCS_MCU_ROWHAM_CTL(1), DCS_MASK_VAL(15, 0, 0x22d4) },
|
||||
{ rDCS_MCU_ROWHAM_CTL(2), DCS_MASK_VAL(15, 0, 0x4a33) },
|
||||
|
||||
// DCSH_AON
|
||||
{ rDCS_AON_IDLE2BCG_CONTROL, DCS_MASK_VAL(0, 0, 0x1) },
|
||||
|
||||
// AMSPCA
|
||||
{ rDCS_AMP_AMPCLK(AMP_CA), DCS_MASK_VAL(28, 28, 0x0) },
|
||||
{ rDCS_AMP_AMPCLK(AMP_CA), DCS_MASK_VAL(24, 24, 0x0) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(0), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(0), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(1), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(1), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(2), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(2), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(3), DCS_MASK_VAL(31, 16, 0x2) },
|
||||
{ rDCS_AMP_RDWRDQCALSEGLEN_F(3), DCS_MASK_VAL(15, 0, 0x3) },
|
||||
|
||||
// AMPSDQ
|
||||
{ rDCS_AMP_AMPCLK(AMP_DQ0), DCS_MASK_VAL(28, 28, 0x0) },
|
||||
{ rDCS_AMP_AMPCLK(AMP_DQ0), DCS_MASK_VAL(24, 24, 0x0) },
|
||||
{ rDCS_AMP_AMPCLK(AMP_DQ1), DCS_MASK_VAL(28, 28, 0x0) },
|
||||
{ rDCS_AMP_AMPCLK(AMP_DQ1), DCS_MASK_VAL(24, 24, 0x0) },
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,163 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Dmin.h is provided by the diags team, defining the 'DMin' key's format
|
||||
* The contents below are copy-pasted verbatim from header files supplied by Diags.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _DMin_h_
|
||||
#define _DMin_h_
|
||||
|
||||
/* vim: set ts=4 sw=4 softtabstop=4 noexpandtab */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef MULTICHARACTER_LITERAL
|
||||
# define MULTICHARACTER_LITERAL(a,b,c,d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
|
||||
#endif
|
||||
|
||||
enum {
|
||||
kEnclosureNone = 0,
|
||||
kEnclosureAlumLight6063 = 1,
|
||||
kEnclosureAlumDark6063 = 2,
|
||||
kEnclosureAlumLight7003 = 3,
|
||||
kEnclosureAlumDark7003 = 4,
|
||||
kEnclosureSUSMirror = 5,
|
||||
kEnclosureSUSBrushed = 6,
|
||||
kEnclosureSUSBlackPVD = 7,
|
||||
kEnclosureMaverickYellow = 8,
|
||||
kEnclosureMaverickRose = 9,
|
||||
kEnclosureZirconiaWhite = 10,
|
||||
kEnclosureGlass = 11,
|
||||
};
|
||||
typedef uint32_t EnclosureType_t; // goes with above enum
|
||||
|
||||
enum {
|
||||
kFCMTypeNone = 0,
|
||||
kFCMTypeOnyx = 1,
|
||||
kFCMTypeGlass = 2,
|
||||
};
|
||||
typedef uint32_t FCMType_t; // goes with above
|
||||
|
||||
enum {
|
||||
kBCMWindowTypeNone = 0,
|
||||
kBCMWindowTypeOnyx = 1,
|
||||
kBCMWindowTypeGlass = 2,
|
||||
};
|
||||
typedef uint32_t BCMWindowType_t;
|
||||
|
||||
enum {
|
||||
kBCMLensTypeNone = 0,
|
||||
kBCMLensTypeNormal = 1,
|
||||
kBCMLensTypeFresnel = 2,
|
||||
};
|
||||
typedef uint32_t BCMLensType_t;
|
||||
|
||||
enum {
|
||||
kBCMLEDTypeNone = 0,
|
||||
kBCMLEDTypeNormal = 1,
|
||||
kBCMLEDTypeNew = 2,
|
||||
};
|
||||
typedef uint32_t BCMPTLEDType_t;
|
||||
|
||||
enum {
|
||||
kBCMPlatinumTypeNone = 0,
|
||||
kBCMPlatinumTypeProtoN_34 = 1,
|
||||
kBCMPlatinumTypeProtoC = 2,
|
||||
};
|
||||
typedef uint32_t BCMPTSensorType_t;
|
||||
|
||||
/* Version 2 information - added Lisa Bits */
|
||||
|
||||
enum {
|
||||
kLisaOpAmpNone = 0,
|
||||
kLisaOpAmpMAX4321 = 1,
|
||||
kLisaOpAmpLMV693 = 2,
|
||||
kLisaOpAmpLMV881 = 3,
|
||||
};
|
||||
typedef uint32_t LisaOpAmpType_t;
|
||||
|
||||
enum {
|
||||
kLisaSensorICNone = 0,
|
||||
kLisaSensorICA0 = 1,
|
||||
kLisaSensorICB0 = 2,
|
||||
};
|
||||
typedef uint32_t LisaSensorICType_t;
|
||||
|
||||
enum {
|
||||
kLisaWheelNone = 0,
|
||||
kLisaWheelLF31 = 1,
|
||||
kLisaWheelLF31LowDiffusion = 2,
|
||||
kLisaWheelLF31HighStripeVar = 3,
|
||||
kLisaWheelLF31pSLaser = 4,
|
||||
kLisaWheelLF45 = 5,
|
||||
kLisaWheelSantek = 6,
|
||||
kLisaWheelNisseiBlack = 7,
|
||||
kLisaWheelNissei = 8,
|
||||
kLisaWheelHeptagonGrind = 9,
|
||||
kLisaWheelHeptagonFormed = 10
|
||||
};
|
||||
typedef uint32_t LisaWheelType_t;
|
||||
|
||||
enum {
|
||||
kLisaKnurlNone = 0,
|
||||
kLisaKnurlProtoN = 1,
|
||||
};
|
||||
typedef uint32_t LisaKnurlType_t;
|
||||
|
||||
/* Pack the structure, do not allow compiler padding */
|
||||
typedef struct __attribute__((packed)) {
|
||||
EnclosureType_t topEnclosure; // See enum at the top
|
||||
EnclosureType_t botEnclosure; // Same values here
|
||||
FCMType_t fcmType; // Onyx or Glass
|
||||
uint32_t fcmARCoated; // 0x00000000 = no AR coating, 0x00000001 = AR coating
|
||||
uint32_t fcmInkColor; // 0x00RRGGBB (little endian, 32-bit word, just like DClr)
|
||||
BCMWindowType_t bcmWindow; // Onyx or Glass
|
||||
BCMLensType_t bcmLens; // Normal or Fresnel
|
||||
BCMPTSensorType_t bcmPTSensorType; // 3 or 4
|
||||
BCMPTLEDType_t bcmPTLEDType; // Normal or "New"
|
||||
} DMin_v1_t;
|
||||
|
||||
typedef struct __attribute__((packed)) {
|
||||
EnclosureType_t topEnclosure; // See enum at the top
|
||||
EnclosureType_t botEnclosure; // Same values here
|
||||
FCMType_t fcmType; // Onyx or Glass
|
||||
uint32_t fcmARCoated; // 0x00000000 = no AR coating, 0x00000001 = AR coating
|
||||
uint32_t fcmInkColor; // 0x00RRGGBB (little endian, 32-bit word, just like DClr)
|
||||
BCMWindowType_t bcmWindow; // Onyx or Glass
|
||||
BCMLensType_t bcmLens; // Normal or Fresnel
|
||||
BCMPTSensorType_t bcmPTSensorType; // 3 or 4
|
||||
BCMPTLEDType_t bcmPTLEDType; // Normal or "New"
|
||||
|
||||
// v2 bits
|
||||
LisaOpAmpType_t lisaOAType;
|
||||
LisaSensorICType_t lisaSensorIC;
|
||||
LisaWheelType_t lisaEncoderWheel;
|
||||
LisaKnurlType_t lisaKnurl;
|
||||
} DMin_v2_t;
|
||||
|
||||
#define DMIN_VERSION_1 0x00000001
|
||||
#define DMIN_VERSION_2 0x00000002
|
||||
|
||||
typedef struct {
|
||||
uint32_t version; // Set to DMIN_VERSION_2
|
||||
union {
|
||||
DMin_v1_t v1; // if version == DMIN_VERSION_1, use this struct
|
||||
DMin_v2_t v2; // if version == DMIN_VERSION_2, use this struct
|
||||
}; // Anonymous union to bridge between v1 and any later version
|
||||
}DMin_t;
|
||||
|
||||
#define SYSCFG_DEVICE_MATERIAL_INFO_SIZE (sizeof(DMin_t)) /* v1 = 40 bytes, v2 = 56 bytes */
|
||||
#define SYSCFG_DEVICE_MATERIAL_INFO MULTICHARACTER_LITERAL('D','M','i','n')
|
||||
|
||||
#endif /* _DMin_h_ */
|
||||
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __DOCKCHANNEL_CONFIG_H
|
||||
#define __DOCKCHANNEL_CONFIG_H
|
||||
|
||||
#include <drivers/dockchannel/dockchannel.h>
|
||||
#include <platform/soc/hwisr.h>
|
||||
|
||||
// These values can also be read out from DC_HWCFG register but is fixed for a particular Dockchannel instance
|
||||
#define DOCKCHANNEL_MAX_AGENTS (4)
|
||||
#define DOCKCHANNEL_MAX_CHANNELS (5)
|
||||
|
||||
// Allocation of agents as per AOP Spec
|
||||
// https://seg-docs.ecs.apple.com/projects/m8//release/specs/Apple/AOP/M8%20AOP%20Microarchitecture%20Specification.pdf
|
||||
#define DOCKCHANNEL_DOCK_AGENT_ID (0)
|
||||
#define DOCKCHANNEL_AP_AGENT_ID (1)
|
||||
#define DOCKCHANNEL_AOP_AGENT_ID (2)
|
||||
#define DOCKCHANNEL_RTP_AGENT_ID (3)
|
||||
|
||||
// Software allocation of channels. UART channel is 0 and needs to be the same as what kanzi firmware
|
||||
// uses. Kanzi firmware separates out SWD communication and UART data, and presents a virtual uart device
|
||||
// to users.
|
||||
// The channels are decided by us and we need to make sure the consumers, in this case kanzi or OS driver
|
||||
// for DockChannel is setup as per these assignments
|
||||
#define DOCKCHANNEL_UART (0)
|
||||
#define DOCKCHANNEL_DIAGS (1)
|
||||
#define DOCKCHANNEL_UNUSED_1 (2)
|
||||
#define DOCKCHANNEL_UNUSED_2 (3)
|
||||
#define DOCKCHANNEL_RTP (4)
|
||||
|
||||
#endif /* __DOCKCHANNEL_CONFIG_H */
|
||||
@@ -0,0 +1,81 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_GPIODEF_H
|
||||
#define __PLATFORM_GPIODEF_H
|
||||
|
||||
/* T8002 specific gpio -> pin mappings */
|
||||
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#if WITH_TARGET_CONFIG
|
||||
# include <target/gpiodef.h>
|
||||
#endif
|
||||
|
||||
/* define platform-specific gpios in a generic fashion here. */
|
||||
#define GPIO_BOARD_ID0 GPIOC(GPIO_AP, 8, 1)
|
||||
#define GPIO_BOARD_ID1 GPIOC(GPIO_AP, 8, 2)
|
||||
#define GPIO_BOARD_ID2 GPIOC(GPIO_AP, 8, 3)
|
||||
#define GPIO_BOARD_ID3 GPIOC(GPIO_AP, 0, 6)
|
||||
|
||||
#define GPIO_BOOT_CONFIG0 GPIOC(GPIO_AP, 0, 2)
|
||||
#define GPIO_BOOT_CONFIG1 GPIOC(GPIO_AP, 0, 3)
|
||||
#define GPIO_BOOT_CONFIG2 GPIOC(GPIO_AP, 0, 4)
|
||||
|
||||
#define BOOT_CONFIG_SPI0 (0)
|
||||
#define BOOT_CONFIG_SPI0_TEST (1)
|
||||
#define BOOT_CONFIG_ANS (2)
|
||||
#define BOOT_CONFIG_ANS_TEST (3)
|
||||
#define BOOT_CONFIG_SLOW_SPI0_TEST (6)
|
||||
|
||||
#define GPIO_BOARD_REV0 GPIOC(GPIO_AP, 0, 7)
|
||||
#define GPIO_BOARD_REV1 GPIOC(GPIO_AP, 1, 0)
|
||||
#define GPIO_BOARD_REV2 GPIOC(GPIO_AP, 1, 1)
|
||||
#define GPIO_BOARD_REV3 GPIOC(GPIO_AP, 1, 2)
|
||||
|
||||
#define GPIO_REQUEST_DFU1 GPIOC(GPIO_AP, 12, 4)
|
||||
#define GPIO_REQUEST_DFU2 GPIOC(GPIO_AP, 12, 5)
|
||||
#define GPIO_FORCE_DFU GPIOC(GPIO_AP, 12, 6)
|
||||
#define GPIO_DFU_STATUS GPIOC(GPIO_AP, 17, 0)
|
||||
#define GPIO_DOCK_CONNECT GPIOC(GPIO_AOP, 0, 6)
|
||||
#define GPIO_DOCK_ATTENTION GPIOC(GPIO_AOP, 0, 7)
|
||||
|
||||
#define SPI_NOR0 (0)
|
||||
|
||||
#define GPIO_SPI0_CS GPIOC(GPIO_AP, 8, 4)
|
||||
#define GPIO_SPI0_SSIN GPIO_SPI0_CS
|
||||
#define GPIO_SPI0_SCLK GPIOC(GPIO_AP, 8, 1)
|
||||
#define GPIO_SPI0_MOSI GPIOC(GPIO_AP, 8, 2)
|
||||
#define GPIO_SPI0_MISO GPIOC(GPIO_AP, 8, 3)
|
||||
|
||||
#define GPIO_NAND_CEN0 GPIOC(GPIO_AP, 2, 5)
|
||||
#define GPIO_NAND_CEN1 GPIOC(GPIO_AP, 2, 6)
|
||||
#define GPIO_NAND_CLE GPIOC(GPIO_AP, 4, 1)
|
||||
#define GPIO_NAND_ALE GPIOC(GPIO_AP, 4, 2)
|
||||
#define GPIO_NAND_REN GPIOC(GPIO_AP, 3, 3)
|
||||
#define GPIO_NAND_WEN GPIOC(GPIO_AP, 4, 0)
|
||||
#define GPIO_NAND_IO0 GPIOC(GPIO_AP, 3, 7)
|
||||
#define GPIO_NAND_IO1 GPIOC(GPIO_AP, 3, 6)
|
||||
#define GPIO_NAND_IO2 GPIOC(GPIO_AP, 3, 5)
|
||||
#define GPIO_NAND_IO3 GPIOC(GPIO_AP, 3, 4)
|
||||
#define GPIO_NAND_IO4 GPIOC(GPIO_AP, 3, 2)
|
||||
#define GPIO_NAND_IO5 GPIOC(GPIO_AP, 3, 1)
|
||||
#define GPIO_NAND_IO6 GPIOC(GPIO_AP, 3, 0)
|
||||
#define GPIO_NAND_IO7 GPIOC(GPIO_AP, 2, 7)
|
||||
|
||||
#define GPIO_IIC0_SCL GPIOC(GPIO_AP, 9, 2)
|
||||
#define GPIO_IIC0_SDA GPIOC(GPIO_AP, 9, 1)
|
||||
#define GPIO_IIC1_SCL GPIOC(GPIO_AP, 9, 4)
|
||||
#define GPIO_IIC1_SDA GPIOC(GPIO_AP, 9, 3)
|
||||
#define GPIO_IIC2_SCL GPIOC(GPIO_AP, 9, 6)
|
||||
#define GPIO_IIC2_SDA GPIOC(GPIO_AP, 9, 5)
|
||||
|
||||
#endif /* ! __PLATFORM_GPIODEF_H */
|
||||
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_IMAGE_DEVICES_H
|
||||
#define __PLATFORM_IMAGE_DEVICES_H
|
||||
|
||||
static const struct image_device platform_image_devices[] = {
|
||||
#if defined(WITH_HW_ASP)
|
||||
{ "asp_fw", 0x00000 }
|
||||
#elif defined(WITH_ANC_FIRMWARE)
|
||||
{ "anc_firmware", 0x00000 }
|
||||
#else
|
||||
{ "nor0", 0x00000 }
|
||||
#endif
|
||||
};
|
||||
|
||||
#if WITH_SYSCFG
|
||||
static const struct image_device platform_syscfg_devices[] = {
|
||||
#if defined(WITH_NAND_BOOT)
|
||||
{ "nand_syscfg", 0x00000 }
|
||||
#else
|
||||
{ "nor0", 0x00000 }
|
||||
#endif
|
||||
};
|
||||
#endif /* WITH_SYSCFG */
|
||||
|
||||
#endif /* ! __PLATFORM_IMAGE_DEVICES_H */
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_MEMCONFIG_H
|
||||
#define __PLATFORM_MEMCONFIG_H
|
||||
|
||||
/* Stub */
|
||||
|
||||
static const gpio_t memory_interface_gpios[] = {
|
||||
/* Not needed */
|
||||
};
|
||||
#endif /* ! __PLATFORM_MEMCONFIG_H */
|
||||
@@ -0,0 +1,202 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_MEMMAP_H
|
||||
#define __PLATFORM_MEMMAP_H
|
||||
|
||||
#include <platform/memmap_defaults.h>
|
||||
|
||||
/* T8002 specific memory map */
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
// 0x80000000 + dram_size --> -------------------------------
|
||||
// | TZ0 (varies) |
|
||||
// |-----------------------------|
|
||||
// | ASP (5 MiB) |
|
||||
// |-----------------------------|
|
||||
// | Consistent Debug (16KiB) |
|
||||
// |-----------------------------|
|
||||
// | Sleep Token Buffer (4KiB) |
|
||||
// |-----------------------------|
|
||||
// | DRAM Config Sequence (16KiB)|
|
||||
// |-----------------------------|
|
||||
// | Panic (512KiB) |
|
||||
// |-----------------------------|
|
||||
// | Display (16MiB) |
|
||||
// | (Framebuffer + scratch) |
|
||||
// | |
|
||||
// | |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | iBoot (32MiB) |
|
||||
// | (Text + Data + Stacks ) |
|
||||
// | (Page Tables + Heap) |
|
||||
// | |
|
||||
// |-----------------------------| <-- 0x80000000 + dram_size - 64MB
|
||||
// | Unused |
|
||||
// | |
|
||||
// | |
|
||||
// | |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | |
|
||||
// | (Ramdisk) |
|
||||
// | (Kernel + DeviceTree) |
|
||||
// | Secure memory |
|
||||
// |-----------------------------|
|
||||
// | |
|
||||
// | |
|
||||
// | Load region / |
|
||||
// | Insecure Memory |
|
||||
// | (overlaps with TZ0) |
|
||||
// | | |-----------------------|
|
||||
// | | | TZ0 (varies |
|
||||
// 0x80000000 --> ------------------------------- -------------------------
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define SDRAM_BASE (0x80000000ULL)
|
||||
#define SDRAM_BANK_LEN (SDRAM_LEN)
|
||||
#define SDRAM_BANK_COUNT (1)
|
||||
#define SDRAM_END (SDRAM_BASE + SDRAM_LEN)
|
||||
|
||||
#define VROM_BASE (0x40000000ULL)
|
||||
#define VROM_BANK_LEN (0x00100000ULL)
|
||||
#define VROM_LEN (0x00040000ULL)
|
||||
|
||||
#define SRAM_BASE (0x48800000ULL)
|
||||
#define SRAM_LEN (0x00120000ULL)
|
||||
#define SRAM_BANK_LEN (SRAM_LEN)
|
||||
#define SRAM_BANK_COUNT (1)
|
||||
#define SRAM_END (SRAM_BASE + SRAM_LEN)
|
||||
|
||||
#define IO_BASE (0x40000000ULL)
|
||||
#define IO_SIZE (0x20000000ULL)
|
||||
|
||||
/* custom ROM is stored at first physical page DRAM, and booted by enabling remap */
|
||||
#define SECUREROM_LOAD_ADDRESS (SDRAM_BASE)
|
||||
|
||||
// Reserved for TZ0/SEP
|
||||
// TZ0_SIZE is defined by the platform or target makefile
|
||||
#define TZ0_BASE (SDRAM_END - TZ0_SIZE)
|
||||
|
||||
/* reserved area for ASP */
|
||||
#define ASP_SIZE (0x00500000ULL)
|
||||
#define ASP_BASE (TZ0_BASE - ASP_SIZE)
|
||||
|
||||
#define CONSISTENT_DEBUG_SIZE (0x00004000ULL)
|
||||
#define CONSISTENT_DEBUG_BASE (ASP_BASE - CONSISTENT_DEBUG_SIZE)
|
||||
|
||||
/* reserved area for sleep token info */
|
||||
#define SLEEP_TOKEN_BUFFER_SIZE (0x00001000ULL)
|
||||
#define SLEEP_TOKEN_BUFFER_BASE (CONSISTENT_DEBUG_BASE - SLEEP_TOKEN_BUFFER_SIZE)
|
||||
|
||||
/* reserved area for config sequence region */
|
||||
#define DRAM_CONFIG_SEQ_SIZE (0x00004000ULL)
|
||||
#define DRAM_CONFIG_SEQ_BASE (SLEEP_TOKEN_BUFFER_BASE - DRAM_CONFIG_SEQ_SIZE)
|
||||
|
||||
/* reserved area for panic info */
|
||||
#define PANIC_SIZE (0x00080000ULL)
|
||||
#define PANIC_BASE (DRAM_CONFIG_SEQ_BASE - PANIC_SIZE)
|
||||
|
||||
/* reserved area for display
|
||||
* DISPLAY_SIZE comes from platform's rules.mk
|
||||
*/
|
||||
#define DISPLAY_BASE (PANIC_BASE - DISPLAY_SIZE)
|
||||
|
||||
|
||||
/* where to stick heap and insecure memory */
|
||||
#if APPLICATION_SECUREROM
|
||||
|
||||
// SecureROM SRAM memory map
|
||||
//
|
||||
// Data 0x000000 - 0x007000 ( 28 KiB)
|
||||
// Boot Trampoline 0x007000 - 0x008000 ( 4 KiB)
|
||||
// Page Tables 0x008000 - 0x00C000 ( 16 KiB)
|
||||
// Stacks 0x00C000 - 0x010000 ( 16 KiB)
|
||||
// Heaps 0x010000 - 0x018000 ( 32 KiB)
|
||||
// DFU Region 0x018000 - 0x120000 (1056 KiB)
|
||||
|
||||
#define INSECURE_MEMORY_SIZE (SRAM_END - HEAP_END)
|
||||
#define INSECURE_MEMORY_BASE (HEAP_END)
|
||||
|
||||
// DATA_BASE comes from rules.mk
|
||||
#define DATA_SIZE (0x00007000ULL)
|
||||
|
||||
#define BOOK_KEEPING_BASE (DATA_BASE + DATA_SIZE)
|
||||
#define BOOT_TRAMPOLINE_BASE (BOOK_KEEPING_BASE)
|
||||
#define BOOT_TRAMPOLINE_SIZE (0x00001000ULL)
|
||||
#define MMU_TT_BASE (BOOK_KEEPING_BASE + BOOT_TRAMPOLINE_SIZE)
|
||||
#define MMU_TT_SIZE (0x00004000ULL)
|
||||
#define STACK_BASE (BOOK_KEEPING_BASE + BOOT_TRAMPOLINE_SIZE + MMU_TT_SIZE)
|
||||
#define STACK_SIZE (0x00004000ULL)
|
||||
#define BOOK_KEEPING_SIZE (BOOT_TRAMPOLINE_SIZE + STACK_SIZE + MMU_TT_SIZE)
|
||||
|
||||
#define HEAP_BASE (BOOK_KEEPING_BASE + BOOK_KEEPING_SIZE)
|
||||
#define HEAP_SIZE (0x00008000ULL)
|
||||
#define HEAP_END (HEAP_BASE + HEAP_SIZE)
|
||||
|
||||
#endif /* APPLICATION_SECUREROM */
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
|
||||
#if WITH_DFU_MODE
|
||||
/* LLB, iBSS DFU */
|
||||
|
||||
/* reserved area for iBoot (aligned to 1MB boundary) */
|
||||
#define IBOOT_SIZE (0x02000000ULL + 0x100000ULL - (PANIC_SIZE + DISPLAY_SIZE))
|
||||
#define IBOOT_BASE (DISPLAY_BASE - IBOOT_SIZE)
|
||||
|
||||
#define INSECURE_MEMORY_SIZE (IBOOT_SIZE)
|
||||
#define INSECURE_MEMORY_BASE (IBOOT_BASE)
|
||||
|
||||
#define STACK_SIZE (0x00004000ULL)
|
||||
#define MMU_TT_SIZE (0x00004000ULL)
|
||||
#define BOOK_KEEPING_SIZE (STACK_SIZE + MMU_TT_SIZE)
|
||||
#define BOOK_KEEPING_BASE (SRAM_BASE)
|
||||
#define MMU_TT_BASE (BOOK_KEEPING_BASE)
|
||||
#define STACK_BASE (BOOK_KEEPING_BASE + MMU_TT_SIZE)
|
||||
|
||||
#define HEAP_SIZE (TEXT_BASE - HEAP_BASE)
|
||||
#define HEAP_BASE (BOOK_KEEPING_BASE + BOOK_KEEPING_SIZE)
|
||||
#define HEAP_END (HEAP_BASE + HEAP_SIZE)
|
||||
|
||||
#else /* !WITH_DFU_MODE */
|
||||
/* iBoot, iBEC */
|
||||
|
||||
#define IBOOT_BASE (TEXT_BASE)
|
||||
#define IBOOT_SIZE (HEAP_END - IBOOT_BASE)
|
||||
|
||||
#define BOOK_KEEPING_BASE (IBOOT_BASE + TEXT_FOOTPRINT)
|
||||
#define MMU_TT_BASE (BOOK_KEEPING_BASE)
|
||||
#define MMU_TT_SIZE (0x00004000ULL)
|
||||
#define STACK_BASE (BOOK_KEEPING_BASE + MMU_TT_SIZE)
|
||||
#define STACK_SIZE (0x00004000ULL)
|
||||
#define BOOK_KEEPING_SIZE (STACK_SIZE + MMU_TT_SIZE)
|
||||
|
||||
#define HEAP_BASE (BOOK_KEEPING_BASE + BOOK_KEEPING_SIZE)
|
||||
#define HEAP_SIZE (DISPLAY_BASE - HEAP_BASE - PAGE_SIZE)
|
||||
#define HEAP_END (HEAP_BASE + HEAP_SIZE)
|
||||
#define HEAP_GUARD (HEAP_END)
|
||||
|
||||
#define INSECURE_MEMORY_BASE (SDRAM_BASE)
|
||||
#define INSECURE_MEMORY_SIZE (DEFAULT_LOAD_SIZE)
|
||||
|
||||
#define SECURE_MEMORY_BASE (INSECURE_MEMORY_BASE + INSECURE_MEMORY_SIZE)
|
||||
#define SECURE_MEMORY_SIZE (DEFAULT_FREE_ADDRESS - SECURE_MEMORY_BASE)
|
||||
|
||||
/* unused area */
|
||||
#define UNUSED_MEMORY_BASE (SECURE_MEMORY_BASE + SECURE_MEMORY_SIZE)
|
||||
#define UNUSED_MEMORY_SIZE (IBOOT_BASE - UNUSED_MEMORY_BASE)
|
||||
|
||||
#endif /* !WITH_DFU_MODE */
|
||||
|
||||
#endif /* APPLICATION_IBOOT */
|
||||
|
||||
#endif /* ! __PLATFORM_MEMMAP_H */
|
||||
@@ -0,0 +1,328 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: m8 io list. version 148
|
||||
I/O Spreadsheet tracker: 20260553
|
||||
Conversion command: csvtopinconfig.py --rom --header --soc m8 --config-column 'SecureROM config' --pupd-column PU/PD --copyright 2015 --radar 20260553 --netname-column 'ROM Config' <filename>
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_PINCONFIG_H
|
||||
#define __PLATFORM_PINCONFIG_H
|
||||
|
||||
static const uint32_t gpio_default_cfg_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED, // 0 : GPIO[0] ->
|
||||
CFG_DISABLED, // 1 : GPIO[1] ->
|
||||
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 2 : GPIO[2] -> Boot_config[0]
|
||||
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 3 : GPIO[3] -> Boot_config[1]
|
||||
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 4 : GPIO[4] -> Boot_config[2]
|
||||
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 5 : GPIO[5] -> Boot_config[3]
|
||||
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 6 : GPIO[6] -> Board_ID[3]
|
||||
CFG_DISABLED, // 7 : GPIO[7] ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED, // 8 : GPIO[8] ->
|
||||
CFG_DISABLED, // 9 : GPIO[9] ->
|
||||
CFG_DISABLED, // 10 : GPIO[10] ->
|
||||
CFG_DISABLED, // 11 : GPIO[11] ->
|
||||
CFG_DISABLED, // 12 : GPIO[12] ->
|
||||
CFG_DISABLED, // 13 : GPIO[13] ->
|
||||
CFG_DISABLED, // 14 : GPIO[14] ->
|
||||
CFG_DISABLED, // 15 : GPIO[15] ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // 16 : GPIO[16] ->
|
||||
CFG_DISABLED, // 17 : GPIO[17] ->
|
||||
CFG_DISABLED, // 18 : TMR32_PWM1 ->
|
||||
CFG_DISABLED, // 19 : TMR32_PWM2 ->
|
||||
CFG_DISABLED, // 20 : TMR32_PWM0 ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 21 : NAND_CEN[0] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 22 : NAND_CEN[1] ->
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 23 : NAND_IO[7] ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 24 : NAND_IO[6] ->
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 25 : NAND_IO[5] ->
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 26 : NAND_IO[4] ->
|
||||
CFG_DISABLED | PULL_UP | DRIVE_S4 | SLOW_SLEW, // 27 : NAND_REN ->
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 28 : NAND_IO[3] ->
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 29 : NAND_IO[2] ->
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 30 : NAND_IO[1] ->
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 31 : NAND_IO[0] ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED | PULL_UP | DRIVE_S4 | SLOW_SLEW, // 32 : NAND_WEN ->
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW, // 33 : NAND_CLE ->
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW, // 34 : NAND_ALE ->
|
||||
CFG_DISABLED, // 35 : I2S0_LRCK ->
|
||||
CFG_DISABLED, // 36 : I2S0_BCLK ->
|
||||
CFG_DISABLED, // 37 : I2S0_DOUT ->
|
||||
CFG_DISABLED, // 38 : I2S0_DIN ->
|
||||
CFG_DISABLED, // 39 : I2S1_LRCK ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED, // 40 : I2S1_BCLK ->
|
||||
CFG_DISABLED, // 41 : I2S1_DOUT ->
|
||||
CFG_DISABLED, // 42 : I2S1_DIN ->
|
||||
CFG_DISABLED, // 43 : I2S2_LRCK ->
|
||||
CFG_DISABLED, // 44 : I2S2_BCLK ->
|
||||
CFG_DISABLED, // 45 : I2S2_DOUT ->
|
||||
CFG_DISABLED, // 46 : I2S2_DIN ->
|
||||
CFG_DISABLED, // 47 : SD_CLKOUT ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED, // 48 : sDIO_IRQ ->
|
||||
CFG_DISABLED, // 49 : SD_DATA_IO[0] ->
|
||||
CFG_DISABLED, // 50 : SD_DATA_IO[1] ->
|
||||
CFG_DISABLED, // 51 : SD_DATA_IO[2] ->
|
||||
CFG_DISABLED, // 52 : SD_DATA_IO[3] ->
|
||||
CFG_DISABLED, // 53 : SDIO_IRQ ->
|
||||
CFG_DISABLED, // 54 : WL_HOST_WAKE ->
|
||||
CFG_DISABLED, // 55 : ENET_MDC ->
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED, // 56 : ENET_MDIO ->
|
||||
CFG_DISABLED, // 57 : RMII_RXER ->
|
||||
CFG_DISABLED, // 58 : RMII_TXEN ->
|
||||
CFG_DISABLED, // 59 : RMII_CLK ->
|
||||
CFG_DISABLED, // 60 : RMII_TXD[0] ->
|
||||
CFG_DISABLED, // 61 : RMII_TXD[1] ->
|
||||
CFG_DISABLED, // 62 : RMII_RXD[0] ->
|
||||
CFG_DISABLED, // 63 : RMII_RXD[1] ->
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // 64 : RMII_CRSDV ->
|
||||
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 65 : SPI0_SCLK -> SPI0_SCLK/Board_ID[0]
|
||||
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 66 : SPI0_MOSI -> SPI0_MOSI/Board_ID[1]
|
||||
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 67 : SPI0_MISO -> SPI0_MISO/Board_ID[2]
|
||||
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 68 : SPI0_SSIN -> SPI0_CS
|
||||
CFG_DISABLED, // 69 : SPI1_SCLK ->
|
||||
CFG_DISABLED, // 70 : SPI1_MOSI ->
|
||||
CFG_DISABLED, // 71 : SPI1_MISO ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // 72 : SPI1_SSIN ->
|
||||
CFG_DISABLED, // 73 : I2C0_SDA ->
|
||||
CFG_DISABLED, // 74 : I2C0_SCL ->
|
||||
CFG_DISABLED, // 75 : I2C1_SDA ->
|
||||
CFG_DISABLED, // 76 : I2C1_SCL ->
|
||||
CFG_DISABLED, // 77 : I2C2_0_SDA ->
|
||||
CFG_DISABLED, // 78 : I2C2_0_SCL ->
|
||||
CFG_DISABLED, // 79 : I2C2_1_SDA ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // 80 : I2C2_1_SCL ->
|
||||
CFG_DISABLED, // 81 : UART0_TXD ->
|
||||
CFG_DISABLED, // 82 : UART0_RXD ->
|
||||
CFG_DISABLED, // 83 : UART3_RTXD ->
|
||||
CFG_DISABLED, // 84 : UART4_TXD ->
|
||||
CFG_DISABLED, // 85 : UART4_RXD ->
|
||||
CFG_DISABLED, // 86 : UART5_TXD ->
|
||||
CFG_DISABLED, // 87 : UART5_RXD ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // 88 : UART2_TXD ->
|
||||
CFG_DISABLED, // 89 : UART2_RXD ->
|
||||
CFG_DISABLED, // 90 : UART2_RTSN ->
|
||||
CFG_DISABLED, // 91 : UART2_CTSN ->
|
||||
CFG_DISABLED, // 92 : UART1_TXD ->
|
||||
CFG_DISABLED, // 93 : UART1_RXD ->
|
||||
CFG_DISABLED, // 94 : UART1_RTSN ->
|
||||
CFG_DISABLED, // 95 : UART1_CTSN ->
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : ISP0_SDA ->
|
||||
CFG_DISABLED, // 97 : ISP0_SCL ->
|
||||
CFG_DISABLED, // 98 : DISP_TE ->
|
||||
CFG_DISABLED, // 99 : DISP_VSYNC ->
|
||||
CFG_IN | DRIVE_S4 | VERY_FAST_SLEW | INPUT_SCHMITT, // 100 : REQUEST_DFU1 -> REQUEST_DFU1
|
||||
CFG_IN | DRIVE_S4 | VERY_FAST_SLEW | INPUT_SCHMITT, // 101 : REQUEST_DFU2 -> REQUEST_DFU2
|
||||
CFG_IN | PULL_DOWN | DRIVE_S4 | VERY_FAST_SLEW | INPUT_SCHMITT, // 102 : FORCE_DFU -> FORCE_DFU
|
||||
CFG_DISABLED, // 103 : SWD_TMS2 ->
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // 104 : SWD_TMS3 ->
|
||||
CFG_DISABLED, // 105 : CLK32K_OUT ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED, // 128 : MON[0] ->
|
||||
CFG_DISABLED, // 129 : MON[1] ->
|
||||
CFG_DISABLED, // 130 : MON[2] ->
|
||||
CFG_DISABLED, // 131 : MON[3] ->
|
||||
CFG_DISABLED, // 132 : MON[4] ->
|
||||
CFG_DISABLED, // 133 : MON[5] ->
|
||||
CFG_DISABLED, // 134 : MON[6] ->
|
||||
CFG_DISABLED, // 135 : MON[7] ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | VERY_FAST_SLEW, // 136 : DFU_STATUS -> DFU_STATUS
|
||||
CFG_DISABLED, // 137 : DROOP_N ->
|
||||
CFG_DISABLED, // 138 : TST_CLKOUT ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
};
|
||||
|
||||
static const uint32_t gpio_default_cfg_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED, // 0 : AOP_I2S1_MCK ->
|
||||
CFG_DISABLED, // 1 : AOP_I2S0_MCK ->
|
||||
CFG_DISABLED, // 2 : AOP_PDM_CLK ->
|
||||
CFG_DISABLED, // 3 : AOP_PDM_DAT ->
|
||||
CFG_DISABLED, // 4 : AOP_PLED[0] ->
|
||||
CFG_DISABLED, // 5 : AOP_PLED[1] ->
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_S4 | VERY_FAST_SLEW | INPUT_SCHMITT, // 6 : AOP_DOCK_CONNECT -> DOCK_CONNECT
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | VERY_FAST_SLEW, // 7 : AOP_DOCK_ATTENTION ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED, // 32 : AOP_PLED[2] ->
|
||||
CFG_DISABLED, // 33 : AOP_PLED[3] ->
|
||||
CFG_DISABLED, // 34 : AOP_PLED[4] ->
|
||||
CFG_DISABLED, // 35 : AOP_PLED[5] ->
|
||||
CFG_DISABLED, // 36 : AOP_PLED[6] ->
|
||||
CFG_DISABLED, // 37 : AOP_PLED[7] ->
|
||||
CFG_DISABLED, // 38 : AOP_MON[0] ->
|
||||
CFG_DISABLED, // 39 : AOP_MON[1] ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED, // 40 : AOP_MON[2] ->
|
||||
CFG_DISABLED, // 41 : AOP_MON[3] ->
|
||||
CFG_DISABLED, // 42 : AOP_MON[4] ->
|
||||
CFG_DISABLED, // 43 : AOP_MON[5] ->
|
||||
CFG_DISABLED, // 44 : AOP_MON[6] ->
|
||||
CFG_DISABLED, // 45 : AOP_MON[7] ->
|
||||
CFG_DISABLED, // 46 : AOP_SWD_TCK_OUT ->
|
||||
CFG_DISABLED, // 47 : AOP_SWD_TMS0 ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED, // 48 : AOP_SWD_TMS1 ->
|
||||
CFG_DISABLED, // 49 : AOP_UART0_TXD ->
|
||||
CFG_DISABLED, // 50 : AOP_UART0_RXD ->
|
||||
CFG_DISABLED, // 51 : AOP_UART0_RTSN ->
|
||||
CFG_DISABLED, // 52 : AOP_UART0_CTSN ->
|
||||
CFG_DISABLED, // 53 : AOP_UART1_TXD ->
|
||||
CFG_DISABLED, // 54 : AOP_UART1_RXD ->
|
||||
CFG_DISABLED, // 55 : AOP_UART1_RTSN ->
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED, // 56 : AOP_UART1_CTSN ->
|
||||
CFG_DISABLED, // 57 : AOP_UART2_TXD ->
|
||||
CFG_DISABLED, // 58 : AOP_UART2_RXD ->
|
||||
CFG_DISABLED, // 59 : AOP_SPI_CS_TRIG[0] ->
|
||||
CFG_DISABLED, // 60 : AOP_SPI_CS_TRIG[1] ->
|
||||
CFG_DISABLED, // 61 : AOP_SPI_CS_TRIG[2] ->
|
||||
CFG_DISABLED, // 62 : AOP_SPI_CS_TRIG[3] ->
|
||||
CFG_DISABLED, // 63 : AOP_SPI_CS_TRIG[4] ->
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // 64 : AOP_SPI_CS_TRIG[5] ->
|
||||
CFG_DISABLED, // 65 : AOP_SPI_CS_TRIG[6] ->
|
||||
CFG_DISABLED, // 66 : AOP_SPI_CS_TRIG[7] ->
|
||||
CFG_DISABLED, // 67 : AOP_SPI_CS_TRIG[8] ->
|
||||
CFG_DISABLED, // 68 : AOP_SPI_CS_TRIG[9] ->
|
||||
CFG_DISABLED, // 69 : AOP_SPI_CS_TRIG[10] ->
|
||||
CFG_DISABLED, // 70 : AOP_SPI_CS_TRIG[11] ->
|
||||
CFG_DISABLED, // 71 : AOP_SPI_CS_TRIG[12] ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // 72 : AOP_SPI_CS_TRIG[13] ->
|
||||
CFG_DISABLED, // 73 : AOP_SPI_CS_TRIG[14] ->
|
||||
CFG_DISABLED, // 74 : AOP_SPI_CS_TRIG[15] ->
|
||||
CFG_DISABLED, // 75 : AOP_I2C0_SDA ->
|
||||
CFG_DISABLED, // 76 : AOP_I2C0_SCL ->
|
||||
CFG_DISABLED, // 77 : AOP_I2C1_SDA ->
|
||||
CFG_DISABLED, // 78 : AOP_I2C1_SCL ->
|
||||
CFG_DISABLED, // 79 : AOP_SPI0_SCLK ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // 80 : AOP_SPI0_MOSI ->
|
||||
CFG_DISABLED, // 81 : AOP_SPI0_MISO ->
|
||||
CFG_DISABLED, // 82 : AOP_PSPI_CS_TRIG[3] ->
|
||||
CFG_DISABLED, // 83 : AOP_PSPI_CS_TRIG[4] ->
|
||||
CFG_DISABLED, // 84 : AOP_PSPI_SCLK ->
|
||||
CFG_DISABLED, // 85 : AOP_PSPI_MOSI ->
|
||||
CFG_DISABLED, // 86 : AOP_PSPI_MISO ->
|
||||
CFG_DISABLED, // 87 : AOP_LSPI_SCLK ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // 88 : AOP_LSPI_MOSI ->
|
||||
CFG_DISABLED, // 89 : AOP_LSPI_MISO ->
|
||||
CFG_DISABLED, // 90 : AOP_DETECT[0] ->
|
||||
CFG_DISABLED, // 91 : AOP_DETECT[1] ->
|
||||
CFG_DISABLED, // 92 : AOP_PSENSE_CTRL[4] ->
|
||||
CFG_DISABLED, // 93 : AOP_PSENSE_CTRL[5] ->
|
||||
CFG_DISABLED, // 94 : AOP_PSENSE_CTRL[6] ->
|
||||
CFG_DISABLED, // 95 : AOP_PSENSE_CTRL[7] ->
|
||||
};
|
||||
|
||||
|
||||
#endif /* __PLATFORM_PINCONFIG_H */
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __APPLE_AOP_DMA_H
|
||||
#define __APPLE_AOP_DMA_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <soc/t8002/a0/aop_pl080.h>
|
||||
|
||||
/* AOP PL080 registers */
|
||||
|
||||
#define rAOP_PL080_INTTCCLEAR (*(volatile uint32_t *)(AOP_PL080_BASE_ADDR + AOP_PL080_BLK_DMAC_INTTCCLEAR_OFFSET))
|
||||
#define rAOP_PL080_INTERRCLR (*(volatile uint32_t *)(AOP_PL080_BASE_ADDR + AOP_PL080_BLK_DMAC_INTERRCLR_OFFSET))
|
||||
#define rAOP_PL080_CONFIGURATION (*(volatile uint32_t *)(AOP_PL080_BASE_ADDR + AOP_PL080_BLK_DMAC_CONFIGURATION_OFFSET))
|
||||
#define rAOP_PL080_SYNC (*(volatile uint32_t *)(AOP_PL080_BASE_ADDR + AOP_PL080_BLK_DMAC_SYNC_OFFSET))
|
||||
#define rAOP_PL080_C0_SRCADDR (*(volatile uint32_t *)(AOP_PL080_BASE_ADDR + AOP_PL080_BLK_DMAC_C0_SRCADDR_OFFSET))
|
||||
#define rAOP_PL080_C0_DESTADDR (*(volatile uint32_t *)(AOP_PL080_BASE_ADDR + AOP_PL080_BLK_DMAC_C0_DESTADDR_OFFSET))
|
||||
#define rAOP_PL080_C0_LLI (*(volatile uint32_t *)(AOP_PL080_BASE_ADDR + AOP_PL080_BLK_DMAC_C0_LLI_OFFSET))
|
||||
#define rAOP_PL080_C0_CONTROL (*(volatile uint32_t *)(AOP_PL080_BASE_ADDR + AOP_PL080_BLK_DMAC_C0_CONTROL_OFFSET))
|
||||
#define rAOP_PL080_C0_CONFIGURATION (*(volatile uint32_t *)(AOP_PL080_BASE_ADDR + AOP_PL080_BLK_DMAC_C0_CONFIGURATION_OFFSET))
|
||||
|
||||
#endif /* __APPLE_AOP_DMA_H */
|
||||
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* Copyright (C) 2013 - 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_CHIPID_H
|
||||
#define __PLATFORM_SOC_CHIPID_H
|
||||
|
||||
#include <platform/chipid.h>
|
||||
#include <platform/soc/pmgr.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rCFG_FUSE0 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE0_OFFSET))
|
||||
#define rCFG_FUSE1 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE1_OFFSET))
|
||||
#define rCFG_FUSE2 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE2_OFFSET))
|
||||
#define rCFG_FUSE3 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE3_OFFSET))
|
||||
#define rCFG_FUSE4 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE4_OFFSET))
|
||||
#define rCFG_FUSE5 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE5_OFFSET))
|
||||
#define rCFG_FUSE9 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE9_OFFSET))
|
||||
|
||||
#define rECIDLO (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_ECID_FUSE0_OFFSET))
|
||||
#define rECIDHI (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_ECID_FUSE1_OFFSET))
|
||||
|
||||
#define rSEP_SECURITY (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_SEP_SECURITY_OFFSET))
|
||||
|
||||
#define rCFG_FUSE0_RAW (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE0_RAW_OFFSET))
|
||||
|
||||
uint32_t chipid_get_total_rails_leakage();
|
||||
uint32_t chipid_get_soc_voltage(uint32_t index);
|
||||
uint32_t chipid_get_fuse_revision(void);
|
||||
|
||||
#endif /* __PLATFORM_SOC_CHIPID_H */
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_H
|
||||
#define __APPLE_DISPLAY_H
|
||||
|
||||
// Platform-specific displaypipe tunables
|
||||
|
||||
static struct adfe_v2_tuneable adfe_tuneables[] =
|
||||
{
|
||||
{
|
||||
.name = "default",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x20) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x130),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x1f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x7d0) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x130),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x128),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x118),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x114),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x24) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcenab = ADPCENAB_IDEAL_ARB_ENAB,
|
||||
},
|
||||
};
|
||||
|
||||
#endif /* ! __APPLE_DISPLAY_H */
|
||||
@@ -0,0 +1,107 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_TIMINGS_H
|
||||
#define __APPLE_DISPLAY_TIMINGS_H
|
||||
|
||||
//Supported timings by this platform
|
||||
static struct display_timing timing_list[] =
|
||||
{
|
||||
#if DEBUG_BUILD || SUB_TARGET_N27 || SUB_TARGET_N28 || SUB_TARGET_N27A || SUB_TARGET_N28A
|
||||
{
|
||||
.display_name = "C1",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 6412500,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 232,
|
||||
.h_pulse_width = 2,
|
||||
.h_back_porch = 44,
|
||||
.h_front_porch = 42,
|
||||
.v_active = 288,
|
||||
.v_pulse_width = 1,
|
||||
.v_back_porch = 23,
|
||||
.v_front_porch = 22,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_SUMMIT,
|
||||
.display_config = {0x00000971},
|
||||
}, // 533MHz, 1-lane
|
||||
|
||||
{
|
||||
.display_name = "POR_DISP_S",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 22200000,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 272,
|
||||
.h_pulse_width = 8,
|
||||
.h_back_porch = 8,
|
||||
.h_front_porch = 16,
|
||||
.v_active = 340,
|
||||
.v_pulse_width = 1,
|
||||
.v_back_porch = 1,
|
||||
.v_front_porch = 43,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_SUMMIT,
|
||||
.display_config = {0x00000951},
|
||||
}, // 533MHz, 1-lane
|
||||
|
||||
{
|
||||
.display_name = "POR_DISP_B",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 22200000,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 312,
|
||||
.h_pulse_width = 8,
|
||||
.h_back_porch = 8,
|
||||
.h_front_porch = 16,
|
||||
.v_active = 390,
|
||||
.v_pulse_width = 1,
|
||||
.v_back_porch = 1,
|
||||
.v_front_porch = 38,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_SUMMIT,
|
||||
.display_config = {0x00000951},
|
||||
}, // 533MHz, 1-lane
|
||||
|
||||
{
|
||||
.display_name = "POR_DISP_B_VID",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 12000000,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 312,
|
||||
.h_pulse_width = 4,
|
||||
.h_back_porch = 102,
|
||||
.h_front_porch = 42,
|
||||
.v_active = 390,
|
||||
.v_pulse_width = 1,
|
||||
.v_back_porch = 23,
|
||||
.v_front_porch = 22,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_SUMMIT,
|
||||
.display_config = {0x00000951},
|
||||
}, // 533MHz, 1-lane
|
||||
#endif
|
||||
};
|
||||
#endif /* ! __APPLE_DISPLAY_TIMINGS_H */
|
||||
@@ -0,0 +1,130 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWCLOCKS_H
|
||||
#define __PLATFORM_SOC_HWCLOCKS_H
|
||||
|
||||
#include <platform/clocks.h>
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define OSC_FREQ (5000000UL)
|
||||
#define LPPLL_FREQ (OSC_FREQ)
|
||||
#else
|
||||
#define OSC_FREQ (24000000UL)
|
||||
#define LPPLL_FREQ (96000000UL)
|
||||
#endif
|
||||
|
||||
// Start from an offset of 128. So that we are safely outside the PS indexes.
|
||||
#define CLK_FCLK (HWCLOCK_BASE+128)
|
||||
#define CLK_ACLK (HWCLOCK_BASE+129)
|
||||
#define CLK_HCLK (HWCLOCK_BASE+130)
|
||||
#define CLK_PCLK (HWCLOCK_BASE+131)
|
||||
#define CLK_VCLK0 (HWCLOCK_BASE+132)
|
||||
#define CLK_VCLK1 (HWCLOCK_BASE+133)
|
||||
#define CLK_MCLK (HWCLOCK_BASE+134)
|
||||
#define CLK_NCLK (HWCLOCK_BASE+135)
|
||||
#define CLK_USBPHYCLK (HWCLOCK_BASE+136)
|
||||
#define CLK_NCOREF (HWCLOCK_BASE+137)
|
||||
#define CLK_ANS_LINK (HWCLOCK_BASE+138)
|
||||
|
||||
#define PMGR_DEVICE_INDEX(_clk) ((_clk) - HWCLOCK_BASE)
|
||||
#define PMGR_DEVICE_COUNT (CLK_LAST - HWCLOCK_BASE)
|
||||
|
||||
#define PMGR_FIRST_DEVICE CLK_AOP
|
||||
#define PMGR_LAST_DEVICE CLK_USB2HOST1
|
||||
|
||||
#define PMGR_VALID_DEVICE(_clk) ((_clk) >= PMGR_FIRST_DEVICE && (_clk) <= PMGR_LAST_DEVICE)
|
||||
|
||||
/*
|
||||
* T8002 clock gate devices.
|
||||
*/
|
||||
enum {
|
||||
// Mini-PMGR
|
||||
CLK_AOP = HWCLOCK_BASE,
|
||||
CLK_DEBUG,
|
||||
CLK_AOP_GPIO,
|
||||
CLK_AOP_I2CM1,
|
||||
CLK_AOP_CPU,
|
||||
CLK_AOP_RTCPU,
|
||||
CLK_AOP_FILTER,
|
||||
CLK_AOP_UART0,
|
||||
CLK_AOP_UART1,
|
||||
CLK_AOP_UART2,
|
||||
CLK_AOP_I2CM,
|
||||
CLK_AOP_FILTER_DMA,
|
||||
CLK_AOP_LPD0,
|
||||
CLK_AOP_HPDS,
|
||||
CLK_AOP_HPDSC,
|
||||
CLK_AOP_HPDD,
|
||||
CLK_MARCONI,
|
||||
|
||||
// PMGR
|
||||
CLK_SCU,
|
||||
CLK_CPU0,
|
||||
CLK_CPU1,
|
||||
CLK_PIO,
|
||||
CLK_CPU_FAB,
|
||||
CLK_NRT_FAB,
|
||||
CLK_RT_FAB,
|
||||
CLK_AIC,
|
||||
CLK_GPIO,
|
||||
CLK_ISPSENS0,
|
||||
CLK_UVD,
|
||||
CLK_HSIC0PHY,
|
||||
CLK_AMC,
|
||||
CLK_LIO_FAB,
|
||||
CLK_LIO_LOGIC,
|
||||
CLK_LIO,
|
||||
CLK_AES0,
|
||||
CLK_MCA0,
|
||||
CLK_MCA1,
|
||||
CLK_MCA2,
|
||||
CLK_HFD,
|
||||
CLK_SPI0,
|
||||
CLK_SPI1,
|
||||
CLK_UART0,
|
||||
CLK_UART1,
|
||||
CLK_UART2,
|
||||
CLK_UART3,
|
||||
CLK_UART4,
|
||||
CLK_UART5,
|
||||
CLK_UART6,
|
||||
CLK_UART7,
|
||||
CLK_I2C0,
|
||||
CLK_I2C1,
|
||||
CLK_I2C2,
|
||||
CLK_PWM0,
|
||||
CLK_USB,
|
||||
CLK_USBCTLREG = CLK_USB,
|
||||
CLK_USB_OTG = CLK_USB,
|
||||
CLK_ETH,
|
||||
CLK_ANS,
|
||||
CLK_SDIO,
|
||||
CLK_DISP,
|
||||
CLK_DISP0 = CLK_DISP,
|
||||
CLK_MIPI_DSI,
|
||||
CLK_MIPI = CLK_MIPI_DSI,
|
||||
CLK_ISP,
|
||||
CLK_GFX,
|
||||
CLK_MEDIA_FAB,
|
||||
CLK_MSR,
|
||||
CLK_VDEC,
|
||||
CLK_RESERVED,
|
||||
CLK_JPG,
|
||||
CLK_VENC_CPU,
|
||||
CLK_USB2HOST1,
|
||||
CLK_SEP,
|
||||
CLK_VENC_PIPE,
|
||||
CLK_VENC_ME,
|
||||
|
||||
CLK_LAST,
|
||||
};
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWCLOCKS_H */
|
||||
@@ -0,0 +1,217 @@
|
||||
/*
|
||||
* Copyright (C) 2013 - 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWISR_H
|
||||
#define __PLATFORM_SOC_HWISR_H
|
||||
|
||||
#define INT_SW0 0 // Software 0 Interrupt
|
||||
#define INT_SW1 1 // Software 1 Interrupt
|
||||
#define INT_SW2 2 // Software 2 Interrupt
|
||||
#define INT_SW3 3 // Software 3 Interrupt
|
||||
|
||||
// Reserved 4
|
||||
|
||||
#define INT_PMGR_PERF_CNTRS 5 // PMGR Performace Counters Interrupt
|
||||
#define INT_THERM_TEMP0 6 // Thermal Temp 0 Interrupt
|
||||
#define INT_THERM_ALARM0 7 // Thermal Alarm 0 Interrupt
|
||||
#define INT_UVDC 8 // UVDC Interrupt
|
||||
#define INT_UVDC_TH 9 // UVDC TH interrupt
|
||||
#define INT_DROOP 10 // Droop Interrupt
|
||||
#define INT_DROOP_TH 11 // Droop TH interrupt
|
||||
|
||||
// Reserved 12 - 13
|
||||
|
||||
#define INT_MIPIDPHY 14 // MIPID PHY Interrupt
|
||||
#define INT_CTM_TRIGGER0 15 // CTM Trigger 0 Interrupt
|
||||
#define INT_CTM_TRIGGER1 16 // CTM Trigger 1 Interrupt
|
||||
#define INT_CTM_TRIGGER2 17 // CTM Trigger 2 Interrupt
|
||||
#define INT_CTM_TRIGGER3 18 // CTM Trigger 3 Interrupt
|
||||
|
||||
// Reserved 19
|
||||
|
||||
#define INT_MINI_PMGR_PERF_CNTRS 20 // MINIPMGR PerfCounter Interrupt
|
||||
#define INT_MINI_PMGR_WDT 21 // MINIPMGR Watchdog Interrupt
|
||||
|
||||
// Reserved 22
|
||||
|
||||
#define INT_CPU0_AXI_ERR_IRQ 23 // CPU 0 AXI Error IRQ Interrupt
|
||||
#define INT_CPU0_CX_ETB_FUKK 24 // CPU 0 CXETB Full Interrupt
|
||||
|
||||
// Reserved 25
|
||||
|
||||
#define INT_CPU0_PMU_IRQ 26 // CPU 0 PMU IRQ Interrupt
|
||||
#define INT_CPU0_CTI_IRQ 27 // CPU 0 CTI Interrupt
|
||||
#define INT_CPU0_COMM_RX 28 // CPU 0 COMM RX Interrupt
|
||||
#define INT_CPU0_COMM_TX 29 // CPU 0 COMM TX Interrupt
|
||||
|
||||
// Reserved 30
|
||||
|
||||
#define INT_CPU1_PMU_IRQ 31 // CPU 1 PMU IRQ Interrupt
|
||||
#define INT_CPU1_CTI_IRQ 32 // CPU 1 CTI Interrupt
|
||||
#define INT_CPU1_COMM_RX 33 // CPU 1 COMM RX Interrupt
|
||||
#define INT_CPU1_COMM_TX 34 // CPU 1 COMM TX Interrupt
|
||||
|
||||
// Reserved 35
|
||||
|
||||
#define INT_GPIO_CLASS0 36 // GPIO Class 0 Interrupt
|
||||
#define INT_GPIO_CLASS1 37 // GPIO Class 1 Interrupt
|
||||
#define INT_GPIO_CLASS2 38 // GPIO Class 2 Interrupt
|
||||
#define INT_GPIO_CLASS3 39 // GPIO Class 3 Interrupt
|
||||
#define INT_GPIO_CLASS4 40 // GPIO Class 4 Interrupt
|
||||
#define INT_GPIO_CLASS5 41 // GPIO Class 5 Interrupt
|
||||
#define INT_GPIO_CLASS6 42 // GPIO Class 6 Interrupt
|
||||
|
||||
// Reserved 43
|
||||
|
||||
#define INT_MEM_MCU 44 // Memory Controller MCU Interrupt
|
||||
#define INT_DCS_AMCX0 45 // Memory Controller DCS AMCX0 Interrupt
|
||||
#define INT_DCS_AMCX1 46 // Memory Controller DCS AMCX1 Interrupt
|
||||
#define INT_DCS_AMP_CAL_ERR 47 // Memory Controller DCS AMP Cal Error Interrupt
|
||||
|
||||
// Reserved 48
|
||||
|
||||
#define INT_GFX 49 // GFX Interrupt
|
||||
|
||||
// Reserved 50
|
||||
|
||||
#define INT_ENET 51 // Ethernet IP Interrupt
|
||||
#define INT_USB_OTG 52 // USB OTG Interrupt
|
||||
#define INT_USB_20_BATT_CHRG_DET 53 // USB 2.0 Battery Charge Detect Interrupt
|
||||
#define INT_USBOTG_RESUME 54 // USB OTG Resume Interrupt
|
||||
#define INT_USB_HOST 55 // USB Host Interrupt
|
||||
#define INT_SDIO_KF_INBOX_EMPTY 56 // SDIO KF Inbox Empty Interrupt
|
||||
#define INT_SDIO_KF_INBOX_NOTEMPTY 57 // SDIO KF Inbox Not Empty Interrupt
|
||||
#define INT_SDIO_KF_OUTBOX_EMPTY 58 // SDIO KF Outbox Empty Interrupt
|
||||
#define INT_SDIO_KF_OUTBOX_NOTEMPTY 59 // SDIO KF Outbox Not Empty Interrupt
|
||||
#define INT_SDIO_SDHC_WAKEUP 60 // SDIO SDHC Wakeup
|
||||
#define INT_SDIO_SDHC_INT 61 // SDIO SDHC Tnterrupt
|
||||
#define INT_SDIO_CARD_INT 62 // SDIO SDHC Interrupt
|
||||
#define INT_SDIO_IRQ 63 // SDIO IRQ
|
||||
#define INT_SDIO_WL_HOST_WAKE_INT 64 // SDIO Host Wake Interrupt
|
||||
|
||||
// Reserved 65
|
||||
|
||||
#define INT_ANS_KF_INBOX_EMPTY 66 // ANS KF Inbox Empty Interrupt
|
||||
#define INT_ANS_KF_INBOX_NOTEMPTY 67 // ANS KF Inbox Not Empty Interrupt
|
||||
#define INT_ANS_KF_OUTBOX_EMPTY 68 // ANS KF Outbox Empty Interrupt
|
||||
#define INT_ANS_KF_OUTBOX_NOTEMPTY 69 // ANS KF Outbox Not Empty Interrupt
|
||||
#define INT_ANS_CHNL0 70 // ANS Channel 0 Interrupt
|
||||
|
||||
// Reserved 71
|
||||
|
||||
#define INT_PIO 72 // PIO IRQ
|
||||
|
||||
// Reserved 73
|
||||
|
||||
#define INT_DMA_RX_TC 74 // DMA Rx Transfer Complete Interrupt
|
||||
#define INT_DMA_RX_ERR 75 // DMA Rx Error Interrupt
|
||||
#define INT_DMA_TX_TC 76 // DMA Tx Transfer Complete Interrupt
|
||||
#define INT_DMA_TX_ERR 77 // DMA Tx Error Interrupt
|
||||
|
||||
// Reserved 78
|
||||
|
||||
#define INT_SPI0 79 // SPI 0 Interrupt
|
||||
#define INT_SPI1 80 // SPI 1 Interrupt
|
||||
#define INT_UART0 81 // UART 0 Interrupt
|
||||
#define INT_UART1 82 // UART 1 Interrupt
|
||||
#define INT_UART2 83 // UART 2 Interrupt
|
||||
#define INT_UART3 84 // UART 3 Interrupt
|
||||
#define INT_UART4 85 // UART 4 Interrupt
|
||||
#define INT_UART5 86 // UART 5 Interrupt
|
||||
#define INT_UART6 87 // UART 6 Interrupt
|
||||
#define INT_UART7 88 // UART 7 Interrupt
|
||||
#define INT_PWM0 89 // PWM0 Interrupt
|
||||
#define INT_MCA0 90 // Multi-Channel Audio 0 Interrupt
|
||||
#define INT_MCA1 91 // Multi-Channel Audio 1 Interrupt
|
||||
#define INT_MCA2 92 // Multi-Channel Audio 2 Interrupt
|
||||
#define INT_IIC0 93 // I2C 0 Interrupt
|
||||
#define INT_IIC1 94 // I2C 1 Interrupt
|
||||
#define INT_IIC2 95 // I2C 2 Interrupt
|
||||
#define INT_AES 96 // AES Interrupt
|
||||
|
||||
// Reserved 97
|
||||
|
||||
#define INT_MSR 98 // MSR Interrupt
|
||||
#define INT_MSR_SMMU 99 // MSR SMMU Interrupt
|
||||
#define INT_MSR_DART 100 // MSR DART Interrupt
|
||||
#define INT_MSR_SMMU_PERF 101 // MSR SMMU Performance Interrupt
|
||||
#define INT_MSR_DART_PERF 102 // MSR DART Performance Interrupt
|
||||
|
||||
// Reserved 103
|
||||
|
||||
#define INT_ADP 104 // Display All ADP
|
||||
#define INT_DISP_DART 105 // Display DART Interrupt
|
||||
#define INT_DISP_SMMU 106 // Display SMMU Interrupt
|
||||
#define INT_DISP_BACK_END_VBI 107 // Display Back End VBI Interrupt
|
||||
#define INT_DISP_BACK_END_VFTG_IDLE 108 // Display Back End VFTG Idle Interrupt
|
||||
#define INT_DISP_BACK_END_VBL_CNTR 109 // Display Back End VBL Counter Interrupt
|
||||
#define INT_PIO_DMA 110 // PIO DMA Interrupt
|
||||
|
||||
// Reserved 111
|
||||
|
||||
#define INT_VDEC 112 // Video Decoder
|
||||
|
||||
// Reserved 113
|
||||
|
||||
#define INT_JPEG 114 // MSR Interrupt
|
||||
#define INT_JPEG_DART 115 // MSR SMMU Interrupt
|
||||
#define INT_JPEG_DART_PERF 116 // MSR DART Interrupt
|
||||
|
||||
// Reserved 117
|
||||
|
||||
#define INT_AVE_KF_INBOX_EMPTY 118 // AVE KF Inbox Empty Interrupt
|
||||
#define INT_AVE_KF_INBOX_NOTEMPTY 119 // AVE KF Inbox Not Empty Interrupt
|
||||
#define INT_AVE_KF_OUTBOX_EMPTY 120 // AVE KF Outbox Empty Interrupt
|
||||
#define INT_AVE_KF_OUTBOX_NOTEMPTY 121 // AVE KF Outbox Not Empty Interrupt
|
||||
#define INT_AVE_SMMU 122 // AVE SMMU Interrupt
|
||||
#define INT_AVE_DART 123 // AVE DART Interrupt
|
||||
#define INT_AVE 124 // AVE Interrupt
|
||||
#define INT_SVE 125 // SVE Driver Synchronization Interrupt
|
||||
|
||||
// AVE Reserved 126-127
|
||||
|
||||
// Reserved 128
|
||||
|
||||
#define INT_ISP_KF_INBOX_EMPTY 129 // ISP KF Inbox Empty Interrupt
|
||||
#define INT_ISP_KF_INBOX_NOTEMPTY 130 // ISP KF Inbox Not Empty Interrupt
|
||||
#define INT_ISP_KF_OUTBOX_EMPTY 131 // ISP KF Outbox Empty Interrupt
|
||||
#define INT_ISP_KF_OUTBOX_NOTEMPTY 132 // ISP KF Outbox Not Empty Interrupt
|
||||
#define INT_ISP0 133 // ISP 0 Interrupt
|
||||
#define INT_ISP1 134 // ISP 1 Interrupt
|
||||
#define INT_ISP2 135 // ISP 2 Interrupt
|
||||
#define INT_ISP3 136 // ISP 3 Interrupt
|
||||
#define INT_ISP_DART 137 // ISP DART Interrupt
|
||||
|
||||
// Reserved 138
|
||||
|
||||
#define INT_SEP_KF_INBOX_EMPTY 139 // SEP KF Inbox Empty Interrupt
|
||||
#define INT_SEP_KF_INBOX_NOTEMPTY 140 // SEP KF Inbox Not Empty Interrupt
|
||||
#define INT_SEP_KF_OUTBOX_EMPTY 141 // SEP KF Outbox Empty Interrupt
|
||||
#define INT_SEP_KF_OUTBOX_NOTEMPTY 142 // SEP KF Outbox Not Empty Interrupt
|
||||
#define INT_SEP_CRIT_PATH_MONITOR 143 // SEP Critical Path Monitor Interrupt
|
||||
#define INT_SEP_AUTH_ERROR 144 // SEP Authentication Error Interrupt
|
||||
|
||||
// Reserved 145 - 147
|
||||
|
||||
#define INT_DOCKCHANNELS_AP 148 // DOCKCHANNELS Interrupt:q
|
||||
|
||||
// AOP Interrupts 146 - 211
|
||||
|
||||
// Reserved 221
|
||||
|
||||
#define INT_PDMC 222 // PDMC Interrupt
|
||||
|
||||
// Reserved 223 - 224
|
||||
|
||||
// Marconi Interrupts 225 - 248
|
||||
|
||||
// Reserved 249 - 255
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWISR_H */
|
||||
@@ -0,0 +1,172 @@
|
||||
/*
|
||||
* Copyright (C) 2014-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWREGBASE_H
|
||||
#define __PLATFORM_SOC_HWREGBASE_H
|
||||
|
||||
#include <platform/memmap.h>
|
||||
|
||||
/* T8002 Reg Base Defs */
|
||||
|
||||
// Memory Subsystem
|
||||
#define SECUREROM_BASE_ADDR (IO_BASE + 0x00000000) // SecureROM access through PIO
|
||||
#define PIO_BASE_ADDR (IO_BASE + 0x00100000) // PIO Config
|
||||
#define CPU_FABRIC_BASE_ADDR (IO_BASE + 0x00101000) // CPU Fabric Config
|
||||
#define NRT_FABRIC_BASE_ADDR (IO_BASE + 0x00102000) // NRT Fabric Config
|
||||
#define RT_FABRIC_BASE_ADDR (IO_BASE + 0x00103000) // RT Fabric Config
|
||||
|
||||
#define DCS_REG_VERSION (0x10)
|
||||
|
||||
// AMCSYS Config
|
||||
#define AMC_BASE_ADDR (IO_BASE + 0x00200000) // AMC Config
|
||||
#define NUM_AMCCS (0)
|
||||
|
||||
#define DCS_BASE_ADDR (IO_BASE + 0x00300000) // DCS
|
||||
|
||||
#define DCS_SPACING (0x40000)
|
||||
#define SPLLCTRL_SPACING (0x0000C000)
|
||||
#define DCSH_AON_SPACING (0x00010000)
|
||||
#define AMP_CA_SPACING (0x00020000)
|
||||
#define AMP_DQ_SPACING (0x00008000)
|
||||
#define AMP_SPACING (DCS_SPACING)
|
||||
#define AMP_BASE_ADDR (DCS_BASE_ADDR + AMP_CA_SPACING)
|
||||
#define AMPH_BASE_ADDR (AMP_BASE_ADDR + 3 * AMP_DQ_SPACING)
|
||||
|
||||
// MSR Subsystem
|
||||
#define MSR_BASE_ADDR (IO_BASE + 0x01100000) // MSR Config
|
||||
#define MSR_SMMU_BASE_ADDR (IO_BASE + 0x01104000) // MSR SMMU
|
||||
#define MSR_DART_BASE_ADDR (IO_BASE + 0x01108000) // MSR DART
|
||||
#define VDEC_BASE_ADDR (IO_BASE + 0x01200000) // VXD394 Video Decoder
|
||||
//XXX
|
||||
//#define SGX544_SC_BASE_ADDR (IO_BASE + 0x02800000) // SGX544-SC Space
|
||||
|
||||
// Display Subsystem
|
||||
#define DISP_ADP_BASE_ADDR (IO_BASE + 0x03200000) // Display pipe configuration
|
||||
#define DISP0_BASE_ADDR DISP_ADP_BASE_ADDR
|
||||
#define DISP_ADP_SMMU_BASE_ADDR (IO_BASE + 0x03300000) // Display pipe SMMU configuration
|
||||
#define DISP_ADE_BASE_ADDR (IO_BASE + 0x03400000) // DBE Timing controller
|
||||
#define DISP0_ADBE_BASE_ADDR DISP_ADE_BASE_ADDR
|
||||
//XXX
|
||||
//#define DISP_AAP_BASE_ADDR (IO_BASE + 0x03440000) // DBE Ambient-Adaptive Pixel
|
||||
#define DISP_DITHER_BASE_ADDR (IO_BASE + 0x03540000) // DBE Dither
|
||||
#define DISP_MIPI_DSI_BASE_ADDR (IO_BASE + 0x03800000) // MIPI DSI Core configuration
|
||||
|
||||
// ANS Subsystem
|
||||
#define ANS_PL301_BASE_ADDR (IO_BASE + 0x05010000) // ANS PL301 Configuration
|
||||
#define ANS_PL301_TLIMIT0_BASE_ADDR (IO_BASE + 0x05020000) // ANS Cortex-A7 Transaction Limit
|
||||
#define ANS_PL301_TLIMIT1_BASE_ADDR (IO_BASE + 0x05030000) // ANS NAND controoler Transaction Limit
|
||||
#define ANS_AKF_BASE_ADDR (IO_BASE + 0x05040000) // ANS Cortex-A7 and wrapper
|
||||
// ANS KF Debug registers
|
||||
#define ANS_CFG_BASE_ADDR (IO_BASE + 0x05080000) // ANS Config
|
||||
#define ANS_PPN_N_PL_BASE_ADDR (IO_BASE + 0x05081000)
|
||||
#define ANS_ANC_BASE_ADDR (IO_BASE + 0x05800000) // NAND Controller
|
||||
|
||||
// SDIO Subsystem
|
||||
#define SDIO_PL301_BASE_ADDR (IO_BASE + 0x06010000) // SDIO PL301 Configuration
|
||||
#define SDIO_PL301_TLIMIT0_BASE_ADDR (IO_BASE + 0x06020000) // SDIO Cortex-A7 Transaction Limit
|
||||
#define SDIO_PL301_TLIMIT1_BASE_ADDR (IO_BASE + 0x06030000) // SDIO controller Transaction Limit
|
||||
#define SDIO_AKF_BASE_ADDR (IO_BASE + 0x06080000) // SDIO Cortex-A7 and wrapper
|
||||
// SDIO KF Debug registers
|
||||
#define SDIO_CFG_BASE_ADDR (IO_BASE + 0x060C0000) // SDIO Config
|
||||
|
||||
// LIO Subsystem
|
||||
#define LIO_MISC_BASE_ADDR (IO_BASE + 0x07000000) // Miscellaneous registers
|
||||
#define LIO_AUD_MUX_BASE_ADDR (IO_BASE + 0x07004000) // Audio I2S Switch registers
|
||||
#define LIO_PWM_BASE_ADDR (IO_BASE + 0x07010000) // PWM Device registers
|
||||
#define LIO_SMB_0_BASE_ADDR (IO_BASE + 0x07020000) // I2C Device registers
|
||||
#define LIO_SPI_BASE_ADDR (IO_BASE + 0x07200000) // SPI Device registers
|
||||
#define LIO_UART_BASE_ADDR (IO_BASE + 0x07230000) // UART Device registers
|
||||
#define LIO_MCA_BASE_ADDR (IO_BASE + 0x07260000) // MCA Device registers
|
||||
#define LIO_AES_BASE_ADDR (IO_BASE + 0x07280000) // AES
|
||||
#define LIO_DMAC_BASE_ADDR (IO_BASE + 0x07300000) // PL080 DMAC registers
|
||||
|
||||
// PMS Subsystem
|
||||
#define GPIO_BASE_ADDR (IO_BASE + 0x07500000) // GPIO Device Registers
|
||||
#define PMGR_BASE_ADDR (IO_BASE + 0x07600000) // Power Manager
|
||||
#define AIC_BASE_ADDR (IO_BASE + 0x07700000) // Apple Interrupt Controller
|
||||
#define GLBTIMER_BASE_ADDR (IO_BASE + 0x07710000) // Global Timer
|
||||
|
||||
#define rAIC_TMR_CNT (*(volatile u_int32_t *)(AIC_BASE_ADDR + 0x2014))
|
||||
#define rAIC_TMR_ISR (*(volatile u_int32_t *)(AIC_BASE_ADDR + 0x2018))
|
||||
#define AIC_TMRISR_PCT (1 << 0)
|
||||
#define AIC_TMRISR_ETS (1 << 1)
|
||||
#define AIC_TMRISR_STS (1 << 2)
|
||||
|
||||
// AOP Subsystem
|
||||
// SPU KF Debug registers
|
||||
#define AOP_GPIO_BASE_ADDR (IO_BASE + 0x08088000) // AOP GPIO
|
||||
#define AOP_MINIPMGR_BASE_ADDR (IO_BASE + 0x08100000)
|
||||
// XXX Need to be fixed
|
||||
#define AOP_SRAM (IO_BASE + 0x88000000)
|
||||
#define MEMORY_CALIB_SAVE_BASE_ADDR AOP_SRAM // Temporarily save cold boot memcal results in AOP_SRAM
|
||||
|
||||
// Dockchannels
|
||||
#define DOCKCHANNELS_BASE_ADDR (IO_BASE + 0x08380000) // Dock channel registers
|
||||
|
||||
// AOP PL080 DMA
|
||||
#define AOP_PL080_BASE_ADDR (IO_BASE + 0x08650000)
|
||||
|
||||
// AUE Subsystem
|
||||
#define AUE_USBCONT_BASE_ADDR (IO_BASE + 0x09000000) // USB Control
|
||||
#define AUE_USBOTG_BASE_ADDR (IO_BASE + 0x09100000) // USBOTG
|
||||
|
||||
/* iBoot Specific Defs */
|
||||
|
||||
#define AKF_VERSION (2)
|
||||
|
||||
#define UART0_BASE_ADDR (LIO_UART_BASE_ADDR)
|
||||
#define UART1_BASE_ADDR (LIO_UART_BASE_ADDR + 0x04000)
|
||||
#define UART2_BASE_ADDR (LIO_UART_BASE_ADDR + 0x08000)
|
||||
#define UART3_BASE_ADDR (LIO_UART_BASE_ADDR + 0x0C000)
|
||||
#define UART4_BASE_ADDR (LIO_UART_BASE_ADDR + 0x10000)
|
||||
#define UARTS_COUNT (5)
|
||||
#define UART_VERSION (1)
|
||||
|
||||
#define SPI0_BASE_ADDR (LIO_SPI_BASE_ADDR)
|
||||
#define SPI1_BASE_ADDR (LIO_SPI_BASE_ADDR + 0x04000)
|
||||
#define SPI_VERSION (1)
|
||||
#define SPIS_COUNT (2)
|
||||
|
||||
#define IIC_BASE_ADDR (LIO_SMB_0_BASE_ADDR)
|
||||
#define IIC_SPACING (0x00004000)
|
||||
#define IICS_COUNT (3)
|
||||
|
||||
#define AES_AP_BASE_ADDR (LIO_AES_BASE_ADDR)
|
||||
|
||||
#define DSIM_BASE_ADDR (DISP_MIPI_DSI_BASE_ADDR)
|
||||
#define DSIM_LANE_COUNT (1)
|
||||
#define DSIM_VERSION (3)
|
||||
|
||||
#define ADBE_DISPLAYPIPE_BASE_ADDR (DISP0_BASE_ADDR)
|
||||
#define DISP_VERSION (5)
|
||||
#define ADP_VERSION (1)
|
||||
|
||||
#define PMGR_WDG_VERSION (1)
|
||||
|
||||
#define GPIOC_COUNT (2)
|
||||
#define GPIO_VERSION (5)
|
||||
#define GPIO_0_GROUP_COUNT (18)
|
||||
#define GPIO_GROUP_COUNT (GPIO_0_GROUP_COUNT)
|
||||
#define GPIO_1_BASE_ADDR (AOP_GPIO_BASE_ADDR)
|
||||
#define GPIO_1_GROUP_COUNT (12)
|
||||
#define GPIO_AP (GPIOC_0)
|
||||
#define GPIO_AOP (GPIOC_1)
|
||||
|
||||
#define AIC_VERSION 2
|
||||
#define AIC_INT_COUNT (256)
|
||||
|
||||
#define USBOTG_BASE_ADDR (AUE_USBOTG_BASE_ADDR)
|
||||
#define AUSB_CTL_REG_BASE_ADDR (AUE_USBCONT_BASE_ADDR)
|
||||
#define AUSB_CTL_USB20PHY_REG_OFFSET (0x30)
|
||||
#define AUSB_USB20PHY_ONLY_VERSION (1)
|
||||
|
||||
#define ASEP_AKF_BASE_ADDR (IO_BASE + 0x0AA00000) // ASEP AKF control Registers
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWREGBASE_H */
|
||||
@@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_MIU_H
|
||||
#define __PLATFORM_SOC_MIU_H
|
||||
|
||||
#include <lib/devicetree.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rMCCLOCKREGION_TZ0BASEADDR *(volatile uint32_t *)(AMC_BASE_ADDR + 0x40)
|
||||
#define rMCCLOCKREGION_TZ0ENDADDR *(volatile uint32_t *)(AMC_BASE_ADDR + 0x44)
|
||||
#define rMCCLOCKREGION_TZ0LOCK *(volatile uint32_t *)(AMC_BASE_ADDR + 0x48)
|
||||
|
||||
// CPU Fabric Widget Registers (base address @ CPU_FABRIC_BASE_ADDR)
|
||||
#define CPU_Fabric_pl301Wrap0_AMCRDRATELIMIT (0x0000) // AMC Read Rate Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_AMCWRALIMIT (0x0004) // AMC Write Rate Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_AMCRTRLIMIT (0x0008) // AMC Read Transactions Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_AMCWTRLIMIT (0x000c) // AMC Write Transactions Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_SPURDRATELIMIT (0x0040) // SPU Read Rate Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_SPUWRALIMIT (0x0044) // SPU Write Rate Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_SPURTRLIMIT (0x0048) // SPU Read Transactions Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_SPUWTRLIMIT (0x004c) // SPU Write Transactions Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_SPUWGATHER (0x0050) // SPU Write Gather Register
|
||||
#define CPU_Fabric_pl301Wrap0_LIOWGATHER (0x0090) // LIO Write Gather Register
|
||||
#define CPU_Fabric_pl301Wrap0_AUERDRATELIMIT (0x00c0) // AUE Read Rate Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_AUEWRALIMIT (0x00c4) // AUE Write Rate Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_AUERTRLIMIT (0x00c8) // AUE Read Transactions Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_AUEWTRLIMIT (0x00cc) // AUE Write Transactions Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_AUEWGATHER (0x00d0) // AUE Write Gather Register
|
||||
#define CPU_Fabric_pl301Wrap0_ANSRDRATELIMIT (0x0100) // ANS Read Rate Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_ANSWRALIMIT (0x0104) // ANS Write Rate Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_ANSRTRLIMIT (0x0108) // ANS Read Transactions Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_ANSWTRLIMIT (0x010c) // ANS Write Transactions Limit Register
|
||||
#define CPU_Fabric_pl301Wrap0_ANSWGATHER (0x0110) // ANS Write Gather Register
|
||||
#define CPU_Fabric_pl301Wrap0_AXI0_ARCHANARBMI0 (0x0408) // Configured AR channel arbitration value for MI 0
|
||||
|
||||
// NRT Fabric Widget Registers (base address @ NRT_FABRIC_BASE_ADDR)
|
||||
#define NRT_Fabric_pl301Wrap1_AMCRDRATELIMIT (0x0000) // AMC Read Rate Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_AMCWRALIMIT (0x0004) // AMC Write Rate Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_AMCRTRLIMIT (0x0008) // AMC Read Transactions Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_AMCWTRLIMIT (0x000c) // AMC Write Transactions Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_MSRRDRATELIMIT (0x0040) // MSR Read Rate Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_MSRWRALIMIT (0x0044) // MSR Write Rate Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_MSRRTRLIMIT (0x0048) // MSR Read Transactions Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_MSRWTRLIMIT (0x004c) // MSR Write Transactions Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_SDIORDRATELIMIT (0x0080) // SDIO Read Rate Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_SDIOWRALIMIT (0x0084) // SDIO Write Rate Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_SDIORTRLIMIT (0x0088) // SDIO Read Transactions Limit Register
|
||||
#define NRT_Fabric_pl301Wrap1_SDIOWTRLIMIT (0x008c) // SDIO Write Transactions Limit Register
|
||||
|
||||
#define rPIO_REMAP_CTL *(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_PIOSYS_ROMADDRREMAP_OFFSET)
|
||||
|
||||
enum remap_select {
|
||||
REMAP_SRAM = 1,
|
||||
REMAP_SDRAM
|
||||
};
|
||||
|
||||
extern void miu_select_remap(enum remap_select sel);
|
||||
extern void miu_bypass_prep(void);
|
||||
extern void miu_update_device_tree(DTNode *pmgr_node);
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_MIU_H */
|
||||
@@ -0,0 +1,255 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_PMGR_H
|
||||
#define __PLATFORM_SOC_PMGR_H
|
||||
|
||||
#include <lib/devicetree.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include SUB_PLATFORM_SPDS_HEADER(minipmgr)
|
||||
#include SUB_PLATFORM_SPDS_HEADER(pmgr)
|
||||
|
||||
enum {
|
||||
PMGR_CLK_OSC = 0,
|
||||
PMGR_CLK_PLL0,
|
||||
PMGR_CLK_PLL1,
|
||||
PMGR_CLK_GPIO,
|
||||
PMGR_CLK_SOURCE_FIRST = PMGR_CLK_GPIO,
|
||||
PMGR_CLK_CPU,
|
||||
PMGR_CLK_MCU_REF,
|
||||
PMGR_CLK_GFX,
|
||||
PMGR_CLK_MEDIA_FAB,
|
||||
PMGR_CLK_PIO,
|
||||
PMGR_CLK_SDIO,
|
||||
PMGR_CLK_LIO, // 0xa
|
||||
PMGR_CLK_AES,
|
||||
PMGR_CLK_AUE,
|
||||
PMGR_CLK_SPI0_N,
|
||||
PMGR_CLK_SPI1_N,
|
||||
PMGR_CLK_NCO_REF0,
|
||||
PMGR_CLK_NCO_REF1, // 0x10
|
||||
PMGR_CLK_NCO_ALG0,
|
||||
PMGR_CLK_NCO_ALG1,
|
||||
PMGR_CLK_MCA0_M,
|
||||
PMGR_CLK_MCA1_M,
|
||||
PMGR_CLK_MCA2_M,
|
||||
PMGR_CLK_TMPS,
|
||||
PMGR_CLK_UVD,
|
||||
PMGR_CLK_ISP_C,
|
||||
PMGR_CLK_ISP,
|
||||
PMGR_CLK_RT_FAB, // 0x1a
|
||||
PMGR_CLK_ISP_SENSOR0,
|
||||
PMGR_CLK_VENC,
|
||||
PMGR_CLK_SEP,
|
||||
PMGR_CLK_SEP_FAB,
|
||||
PMGR_CLK_ANS,
|
||||
PMGR_CLK_ANC_LINK, // 0x20
|
||||
PMGR_CLK_VDEC,
|
||||
PMGR_CLK_MSR,
|
||||
PMGR_CLK_AJPEG_IP,
|
||||
PMGR_CLK_AJPEG_WRAP,
|
||||
PMGR_CLK_DISP,
|
||||
PMGR_CLK_MIPI_DSI,
|
||||
PMGR_CLK_VID,
|
||||
PMGR_CLK_HFD,
|
||||
PMGR_CLK_HSICPHY_REF_12M,
|
||||
PMGR_CLK_USB480_0, // 0x2a
|
||||
PMGR_CLK_USB_EHCI,
|
||||
PMGR_CLK_SOURCE_LAST = PMGR_CLK_USB_EHCI,
|
||||
PMGR_CLK_S0,
|
||||
PMGR_CLK_SPARE_FIRST = PMGR_CLK_S0,
|
||||
PMGR_CLK_S1,
|
||||
PMGR_CLK_ISP_REF0,
|
||||
PMGR_CLK_SPARE_LAST = PMGR_CLK_ISP_REF0,
|
||||
PMGR_CLK_LPPLL,
|
||||
PMGR_CLK_AOP, // 0x30
|
||||
PMGR_CLK_MINI_FIRST = PMGR_CLK_AOP,
|
||||
PMGR_CLK_UART0,
|
||||
PMGR_CLK_UART1,
|
||||
PMGR_CLK_UART2,
|
||||
PMGR_CLK_SENSE_X2,
|
||||
PMGR_CLK_DETECT,
|
||||
PMGR_CLK_I2CM,
|
||||
PMGR_CLK_I2CM1,
|
||||
PMGR_CLK_PROXY_FABRIC,
|
||||
PMGR_CLK_PROXY_MCU_REF, // 0x3a
|
||||
PMGR_CLK_MINI_LAST = PMGR_CLK_PROXY_MCU_REF,
|
||||
PMGR_CLK_COUNT,
|
||||
PMGR_CLK_NOT_SUPPORTED,
|
||||
};
|
||||
|
||||
// PLL
|
||||
static const int PMGR_PLL_COUNT = 2;
|
||||
#define PMGR_PLL_REG_STRIDE (PMGR_PLL1_OFFSET - PMGR_PLL0_OFFSET)
|
||||
#define rPMGR_PLL_CTL(_p) (*(volatile uint32_t *)(PMGR_BASE_ADDR + ((_p) * PMGR_PLL_REG_STRIDE)))
|
||||
#define rPMGR_PLL_CFG(_p) (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_PLL0_CFG_OFFSET + ((_p) * PMGR_PLL_REG_STRIDE)))
|
||||
|
||||
#define PMGR_PLL_CTL_PRE_DIVN_INSRT(_f) PMGR_PLL0_CTL_PRE_DIVN_INSRT(_f)
|
||||
#define PMGR_PLL_CTL_FB_DIVN_INSRT(_f) PMGR_PLL0_CTL_FB_DIVN_INSRT(_f)
|
||||
#define PMGR_PLL_CTL_OP_DIVN_INSRT(_f) PMGR_PLL0_CTL_OP_DIVN_INSRT(_f)
|
||||
#define PMGR_PLL_CTL_ENABLE_INSRT(_f) PMGR_PLL0_CTL_ENABLE_INSRT(_f)
|
||||
#define PMGR_PLL_CTL_LOAD_INSRT(_f) PMGR_PLL0_CTL_LOAD_INSRT(_f)
|
||||
#define PMGR_PLL_CTL_BYPASS_INSRT(_f) PMGR_PLL0_CTL_BYPASS_INSRT(_f)
|
||||
#define PMGR_PLL_CFG_VCO_OUT_SEL_INSRT(_f) PMGR_PLL0_CFG_VCO_OUT_SEL_INSRT(_f)
|
||||
#define PMGR_PLL_CFG_OFF_MODE_INSRT(_f) PMGR_PLL0_CFG_OFF_MODE_INSRT(_f)
|
||||
#define PMGR_PLL_CFG_FRAC_LOCK_TIME_INSRT(_f) PMGR_PLL0_CFG_FRAC_LOCK_TIME_INSRT(_f)
|
||||
#define PMGR_PLL_CFG_LOCK_TIME_INSRT(_f) PMGR_PLL0_CFG_LOCK_TIME_INSRT(_f)
|
||||
|
||||
#define PMGR_PLL_CTL_PENDING_XTRCT(_f) PMGR_PLL0_CTL_PLL_PENDING_XTRCT(_f)
|
||||
#define PMGR_PLL_CTL_ENABLE_XTRCT(_f) PMGR_PLL0_CTL_ENABLE_XTRCT(_f)
|
||||
#define PMGR_PLL_CTL_BYPASS_XTRCT(_f) PMGR_PLL0_CTL_BYPASS_XTRCT(_f)
|
||||
#define PMGR_PLL_CTL_PRE_DIVN_XTRCT(_f) PMGR_PLL0_CTL_PRE_DIVN_XTRCT(_f)
|
||||
#define PMGR_PLL_CTL_FB_DIVN_XTRCT(_f) PMGR_PLL0_CTL_FB_DIVN_XTRCT(_f)
|
||||
#define PMGR_PLL_CTL_OP_DIVN_XTRCT(_f) PMGR_PLL0_CTL_OP_DIVN_XTRCT(_f)
|
||||
#define PMGR_PLL_CFG_VCO_OUT_SEL_XTRCT(_f) PMGR_PLL0_CFG_VCO_OUT_SEL_XTRCT(_f)
|
||||
|
||||
enum pmgr_pll_off_mode {
|
||||
PMGR_PLL_OFF_MODE_RESET = 0,
|
||||
PMGR_PLL_OFF_MODE_CLOCK_GATED,
|
||||
PMGR_PLL_OFF_MODE_POWER_DOWN
|
||||
};
|
||||
|
||||
enum pmgr_pll_lock_mode {
|
||||
PMGR_PLL_LOCK_MODE_COUNTER = 0,
|
||||
PMGR_PLL_LOCK_MODE_LOCK
|
||||
};
|
||||
|
||||
enum pmgr_pll_relock_mode {
|
||||
PMGR_PLL_RELOCK_MODE_STOP = 0,
|
||||
PMGR_PLL_RELOCK_MODE_BYPASS
|
||||
};
|
||||
|
||||
// PS
|
||||
#define rPMGR_PS(_x) (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_PS_##_x##_PS_OFFSET))
|
||||
|
||||
#define PMGR_PS_MANUAL_PS_XTRCT(_f) PMGR_PS_DISP_PS_MANUAL_PS_XTRCT(_f)
|
||||
#define PMGR_PS_ACTUAL_PS_XTRCT(_f) PMGR_PS_DISP_PS_ACTUAL_PS_XTRCT(_f)
|
||||
#define PMGR_PS_MANUAL_PS_INSRT(_f) PMGR_PS_DISP_PS_MANUAL_PS_INSRT(_f)
|
||||
#define PMGR_PS_RESET_INSRT(_f) PMGR_PS_DISP_PS_RESET_INSRT(_f)
|
||||
|
||||
enum pmgr_ps_state {
|
||||
PMGR_PS_RUN_MAX = 0xF,
|
||||
PMGR_PS_CLOCK_OFF = 0x4,
|
||||
PMGR_PS_POWER_OFF = 0x0
|
||||
};
|
||||
|
||||
#define rPMGR_CLK_CFG(_x) (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_CLKCFG_##_x##_CLK_CFG_OFFSET))
|
||||
#define PMGR_FIRST_CLK_CFG (&rPMGR_CLK_CFG(GPIO))
|
||||
#define PMGR_LAST_CLK_CFG (&rPMGR_CLK_CFG(USB_EHCI))
|
||||
#define PMGR_FIRST_SPARE_CLK_CFG (&rPMGR_CLK_CFG(S0))
|
||||
#define PMGR_LAST_SPARE_CLK_CFG (&rPMGR_CLK_CFG(ISP_REF0))
|
||||
|
||||
#define PMGR_CLKCFG_ENABLE_UMASK PMGR_CLKCFG_S0_CLK_CFG_ENABLE_UMASK
|
||||
#define PMGR_CLKCFG_SRC_SEL_UMASK PMGR_CLKCFG_MCU_REF_CLK_CFG_SRC_SEL_UMASK // Must have the max width of any CLKCFG SRC_SEL field
|
||||
#define PMGR_CLKCFG_DIVISOR_UMASK PMGR_CLKCFG_S0_CLK_CFG_DIVISOR_UMASK
|
||||
#define PMGR_CLKCFG_WAIT_COUNTER_UMASK PMGR_CLKCFG_MCU_REF_CLK_CFG_WAIT_COUNTER_UMASK
|
||||
#define PMGR_CLKCFG_PENDING_XTRCT(_f) PMGR_CLKCFG_S0_CLK_CFG_PENDING_XTRCT(_f)
|
||||
#define PMGR_CLKCFG_SRC_SEL_XTRCT(_f) PMGR_CLKCFG_MCU_REF_CLK_CFG_SRC_SEL_XTRCT(_f) // Must have the max width of any CLKCFG SRC_SEL field
|
||||
#define PMGR_CLKCFG_ENABLE_XTRCT(_f) PMGR_CLKCFG_MCU_REF_CLK_CFG_ENABLE_XTRCT(_f)
|
||||
#define PMGR_CLKCFG_DIVISOR_XTRCT(_f) PMGR_CLKCFG_S0_CLK_CFG_DIVISOR_XTRCT(_f)
|
||||
#define PMGR_CLKCFG_SRC_SEL_INSRT(_f) PMGR_CLKCFG_MCU_REF_CLK_CFG_SRC_SEL_INSRT(_f) // Must have the max width of any CLKCFG SRC_SEL field
|
||||
|
||||
#define rPMGR_MISC_CFG_ACG (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_MISC_CFG_ACG_OFFSET))
|
||||
#define rPMGR_MISC_CFG_ASYNC_XOVER_ACG (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_MISC_CFG_ASYNC_XOVER_ACG_OFFSET))
|
||||
|
||||
// MiniPMGR PS
|
||||
#define rMINIPMGR_PS(_x) (*(volatile uint32_t *) (AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_PS_##_x##_PS_OFFSET))
|
||||
|
||||
#define rMINIPMGR_CLK_CFG(_x) (*(volatile uint32_t *) (AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_CLKCFG_##_x##_CLK_CFG_OFFSET))
|
||||
#define rMINIPMGR_CLK_DIVIDER_ACG_CFG (*(volatile uint32_t *) (AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_CLKCFG_CLK_DIVIDER_ACG_CFG_OFFSET))
|
||||
|
||||
#define rMINIPMGR_MISC_CFG_ACG (*(volatile uint32_t *) (AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_MISC_CFG_ACG_OFFSET))
|
||||
|
||||
#define rMINIPMGR_LPPLL_CTL (*(volatile uint32_t *) (AOP_MINIPMGR_BASE_ADDR + MINIPMGR_LPPLL_CTL_OFFSET))
|
||||
#define rMINIPMGR_LPPLL_CFG (*(volatile uint32_t *) (AOP_MINIPMGR_BASE_ADDR + MINIPMGR_LPPLL_CFG_OFFSET))
|
||||
|
||||
// MiniPMGR Watchdog
|
||||
#define rPMGR_CHIP_WDOG_TMR (*(volatile uint32_t *) (AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_CHIP_WATCHDOG_TIMER_OFFSET))
|
||||
#define rPMGR_CHIP_WDOG_RST_CNT (*(volatile uint32_t *) (AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_CHIP_WATCHDOG_RESET_COUNT_OFFSET))
|
||||
#define rPMGR_CHIP_WDOG_INTR_CNT (*(volatile uint32_t *) (AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_CHIP_WATCHDOG_INTERRUPT_COUNT_OFFSET))
|
||||
#define rPMGR_CHIP_WDOG_CTL (*(volatile uint32_t *) (AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_CHIP_WATCHDOG_CONTROL_OFFSET))
|
||||
#define rPMGR_SYS_WDOG_TMR (*(volatile uint32_t *) (AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_SYS_WATCHDOG_TIMER_OFFSET))
|
||||
#define rPMGR_SYS_WDOG_RST_CNT (*(volatile uint32_t *) (AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_SYS_WATCHDOG_RESET_COUNT_OFFSET))
|
||||
#define rPMGR_SYS_WDOG_CTL (*(volatile uint32_t *) (AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_SYS_WATCHDOG_CONTROL_OFFSET))
|
||||
|
||||
// PMGR Event Timer
|
||||
#define rPMGR_EVENT_TMR (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_TIMERS_EVENT_TIMER_OFFSET))
|
||||
#define rPMGR_EVENT_TMR_PERIOD (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_TIMERS_EVENT_TIMER_PERIOD_OFFSET))
|
||||
#define rPMGR_EVENT_TMR_CTL (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_TIMERS_EVENT_TIMER_CTL_OFFSET))
|
||||
|
||||
// NCO Config block
|
||||
#define rPMGR_NCO_CLK_CFG(_n) (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_NCO_##_n##_CLK_CFG_OFFSET))
|
||||
|
||||
// Misc Clock Tree Power Saving Regs
|
||||
#define rPMGR_CLK_DIVIDER_ACG_CFG (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_CLKCFG_CLK_DIVIDER_ACG_CFG_OFFSET))
|
||||
#define rPMGR_CLK_POWER_CONFIG (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_CLKCFG_CLK_POWER_CONFIG_OFFSET))
|
||||
|
||||
// SOC Perf State
|
||||
static const int PMGR_SOC_PERF_STATE_ENTRY_COUNT = 8;
|
||||
static const int PMGR_SOC_PERF_STATE_STRIDE = (PMGR_SOC_PERF_STATE_ENTRY_1A_OFFSET - PMGR_SOC_PERF_STATE_ENTRY_0A_OFFSET);
|
||||
static const int kSOC_PERF_STATE_MAX_CNT = 6;
|
||||
#define rPMGR_SOC_PERF_STATE_ENTRY_A(_n) (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_SOC_PERF_STATE_ENTRY_0A_OFFSET + (_n) * PMGR_SOC_PERF_STATE_STRIDE))
|
||||
#define rPMGR_SOC_PERF_STATE_CTL (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_SOC_PERF_STATE_CTL_OFFSET))
|
||||
|
||||
#define PMGR_SOC_PERF_STATE_ENTRY_MCU_REF_MASK (PMGR_SOC_PERF_STATE_ENTRY_0A_MCU_REF_SRC_SEL_UMASK | PMGR_SOC_PERF_STATE_ENTRY_0A_MCU_REF_CFG_SEL_UMASK)
|
||||
#define PMGR_SOC_PERF_STATE_ENTRY_MCU_REF(_cfg, _src) (PMGR_SOC_PERF_STATE_ENTRY_0A_MCU_REF_CFG_SEL_INSRT(_cfg) | PMGR_SOC_PERF_STATE_ENTRY_0A_MCU_REF_SRC_SEL_INSRT(_src))
|
||||
|
||||
// First two entries used by AOP Config Engine
|
||||
#define PMGR_SOC_PERF_STATE_FIRST_ENTRY (PMGR_SOC_PERF_STATE_ENTRY_COUNT - kSOC_PERF_STATE_MAX_CNT)
|
||||
#define PMGR_SOC_PERF_STATE_TO_ENTRY(_s) (PMGR_SOC_PERF_STATE_ENTRY_COUNT - (_s) - 1)
|
||||
|
||||
enum pmgr_soc_perf_state_index {
|
||||
kSOC_PERF_STATE_BYPASS = 0,
|
||||
kSOC_PERF_STATE_SECUREROM,
|
||||
kSOC_PERF_STATE_IBOOT,
|
||||
kSOC_PERF_STATE_VMIN = kSOC_PERF_STATE_IBOOT,
|
||||
kSOC_PERF_STATE_IBOOT_CNT
|
||||
};
|
||||
|
||||
static const int PMGR_SCRATCH_REG_STRIDE = (PMGR_SCRATCH_1_OFFSET - PMGR_SCRATCH_0_OFFSET);
|
||||
#define rPMGR_SCRATCH(_n) (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_SCRATCH_0_OFFSET + ((_n) * PMGR_SCRATCH_REG_STRIDE)))
|
||||
#define rPMGR_SCRATCH0 rPMGR_SCRATCH(0) /* Flags */
|
||||
#define rPMGR_SCRATCH1 rPMGR_SCRATCH(1)
|
||||
#define rPMGR_SCRATCH2 rPMGR_SCRATCH(2)
|
||||
#define rPMGR_SCRATCH3 rPMGR_SCRATCH(3)
|
||||
#define rPMGR_SCRATCH4 rPMGR_SCRATCH(4)
|
||||
#define rPMGR_SCRATCH5 rPMGR_SCRATCH(5)
|
||||
#define rPMGR_SCRATCH6 rPMGR_SCRATCH(6)
|
||||
#define rPMGR_SCRATCH7 rPMGR_SCRATCH(7) /* Consistent debug root pointer */
|
||||
#define rPMGR_SCRATCH8 rPMGR_SCRATCH(8)
|
||||
|
||||
#define rPMGR_SCRATCH_MEM_INFO rPMGR_SCRATCH(9)
|
||||
#define rPMGR_SCRATCH_BOOT_NONCE_0 rPMGR_SCRATCH(10)
|
||||
#define rPMGR_SCRATCH_BOOT_NONCE_1 rPMGR_SCRATCH(11)
|
||||
#define rPMGR_SCRATCH_BOOT_MANIFEST_HASH_FIRST rPMGR_SCRATCH(12)
|
||||
#define rPMGR_SCRATCH_BOOT_MANIFEST_HASH_LAST rPMGR_SCRATCH(23)
|
||||
#define PMGR_SCRATCH_BOOT_MANIFEST_REGISTERS (384 / 32)
|
||||
|
||||
static const int MINIPMGR_SCRATCH_REG_STRIDE = (MINIPMGR_MINI_SCRATCH_SCRATCH1_OFFSET - MINIPMGR_MINI_SCRATCH_SCRATCH0_OFFSET);
|
||||
#define rMINIPMGR_SCRATCH(_n) (*(volatile uint32_t *) (AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_SCRATCH_OFFSET + ((_n) * MINIPMGR_SCRATCH_REG_STRIDE)))
|
||||
#define rMINIPMGR_SCRATCH0 rMINIPMGR_SCRATCH(0)
|
||||
#define rMINIPMGR_SCRATCH1 rMINIPMGR_SCRATCH(1) /* Consistent debug root pointer */
|
||||
#define rMINIPMGR_SCRATCH2 rMINIPMGR_SCRATCH(2)
|
||||
#define rMINIPMGR_SCRATCH3 rMINIPMGR_SCRATCH(3)
|
||||
#define rMINIPMGR_SCRATCH4 rMINIPMGR_SCRATCH(4)
|
||||
#define rMINIPMGR_SCRATCH5 rMINIPMGR_SCRATCH(5)
|
||||
#define rMINIPMGR_SCRATCH6 rMINIPMGR_SCRATCH(6)
|
||||
#define rMINIPMGR_SCRATCH7 rMINIPMGR_SCRATCH(7)
|
||||
#define rMINIPMGR_SCRATCH8 rMINIPMGR_SCRATCH(8)
|
||||
#define rMINIPMGR_SCRATCH9 rMINIPMGR_SCRATCH(9)
|
||||
#define rMINIPMGR_SCRATCH10 rMINIPMGR_SCRATCH(10)
|
||||
#define rMINIPMGR_SCRATCH11 rMINIPMGR_SCRATCH(11)
|
||||
|
||||
#define rPMGR_SECURITY (*(volatile uint32_t *) (AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_OFFSET))
|
||||
|
||||
extern void pmgr_update_device_tree(DTNode *pmgr_node);
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_PMGR_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_TRAMPOLINE_H
|
||||
#define __PLATFORM_TRAMPOLINE_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
/* ROM related registers in PMGR space */
|
||||
|
||||
#define SECURITY_REG (AOP_MINIPMGR_BASE_ADDR + 0xD0010)
|
||||
#define ROM_READ_DISABLE (1 << 0)
|
||||
|
||||
#endif /* ! __PLATFORM_TRAMPOLINE_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_UARTCONFIG_H
|
||||
#define __PLATFORM_UARTCONFIG_H
|
||||
|
||||
/* define one debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (0)
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define UART_OVERSAMPLE_OVERRIDE (11)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_USBCONFIG_H
|
||||
#define __PLATFORM_USBCONFIG_H
|
||||
|
||||
#ifdef WITH_TARGET_USB_CONFIG
|
||||
#include <target/usbconfig.h>
|
||||
#endif /* WITH_TARGET_USB_CONFIG */
|
||||
|
||||
#define USBPHY_OTGTUNE0 (0x37377bc3)
|
||||
#define USBPHY_OTGTUNE1 (0x20c04)
|
||||
|
||||
#define USBOTG_AHB_DMA_BURST (DWCUSB_GAHBCFG_HBST_INCR16)
|
||||
|
||||
#define USBCFG_TURNAROUND_TIME (9)
|
||||
|
||||
#endif /* ! __PLATFORM_USBCONFIG_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,110 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <arch.h>
|
||||
#include <debug.h>
|
||||
#include <drivers/miu.h>
|
||||
#include <platform.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <platform/miu.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <platform/soc/miu.h>
|
||||
#include <platform/soc/pmgr.h>
|
||||
#include <platform/clocks.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <platform/timer.h>
|
||||
|
||||
int miu_initialize_internal_ram(void)
|
||||
{
|
||||
#if APPLICATION_SECUREROM
|
||||
// Ensure that rPMGR_SCRATCH0-3 get cleared
|
||||
rPMGR_SCRATCH0 = 0;
|
||||
rPMGR_SCRATCH1 = 0;
|
||||
rPMGR_SCRATCH2 = 0;
|
||||
rPMGR_SCRATCH3 = 0;
|
||||
#endif /* APPLICATION_SECUREROM */
|
||||
|
||||
// Save the Security Epoch in the top byte of PMGR_SCRATCH0
|
||||
rPMGR_SCRATCH0 &= ~0xFF000000;
|
||||
rPMGR_SCRATCH0 |= (platform_get_security_epoch()) << 24;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int miu_init(void)
|
||||
{
|
||||
#if APPLICATION_IBOOT && !PRODUCT_IBEC
|
||||
// Verify that the Security Epoch in PMGR_SCRATCH0 matches
|
||||
if ((rPMGR_SCRATCH0 >> 24) != platform_get_security_epoch()) {
|
||||
panic("miu_init: Epoch Mismatch\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void miu_suspend(void)
|
||||
{
|
||||
/* nothing required for suspend */
|
||||
}
|
||||
|
||||
int miu_initialize_dram(bool resume)
|
||||
{
|
||||
#if APPLICATION_IBOOT && WITH_HW_DCS
|
||||
mcu_initialize_dram(resume);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
void miu_select_remap(enum remap_select sel)
|
||||
{
|
||||
/*
|
||||
The ROMADDRREMAP[1:0] is responsible for the remap
|
||||
|
||||
1. ROMADDRREMAP[1] = 1’b0 - ROM mapped to PIO
|
||||
1.1. ROMADDRREMAP[0] = 1’b0 - ROM mapped to SECURE ROM
|
||||
1.2. ROMADDRREMAP[0] = 1’b1 - ROM mapped to AOP-SRAM
|
||||
2. ROMADDRREMAP[1] = 1’b1 - ROM mapped to DRAM
|
||||
|
||||
in other words
|
||||
ROMADDRREMAP[1:0]
|
||||
2’b00 - SECURE ROM
|
||||
2’b01 - AOP-SRAM
|
||||
2’b1x - DDR
|
||||
*/
|
||||
|
||||
switch (sel) {
|
||||
case REMAP_SRAM:
|
||||
rPIO_REMAP_CTL = (rPIO_REMAP_CTL & ~3) | (1 << 0);
|
||||
break;
|
||||
|
||||
case REMAP_SDRAM:
|
||||
rPIO_REMAP_CTL = (rPIO_REMAP_CTL & ~3) | (2 << 0);
|
||||
break;
|
||||
|
||||
// reset back to default behavior
|
||||
default:
|
||||
rPIO_REMAP_CTL = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void miu_bypass_prep(void)
|
||||
{
|
||||
}
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
void miu_update_device_tree(DTNode *pmgr_node)
|
||||
{
|
||||
// Nothing to do here
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_MIU=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/miu.o
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,18 @@
|
||||
# Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_CLOCKS=1 \
|
||||
WITH_HW_PLATFORM_POWER=1 \
|
||||
WITH_HW_TIMER=1 \
|
||||
WITH_FIQ_TIMER=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/pmgr.o
|
||||
@@ -0,0 +1,139 @@
|
||||
# Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
# modules implied by this platform
|
||||
MODULES += \
|
||||
platform/defaults \
|
||||
platform/generic \
|
||||
arch/$(ARCH)
|
||||
|
||||
ARM_CPU := cortex-a7
|
||||
|
||||
# Devmap chip ID
|
||||
DEVMAP_CHIP_ID := 8002
|
||||
|
||||
SPDS_CHIP_REV := b0
|
||||
|
||||
IRQ_STACK_SIZE := 4096
|
||||
|
||||
# srom is always defined in here
|
||||
ifeq ($(TEXT_BANK),srom)
|
||||
TEXT_BASE := 0x00000000
|
||||
endif
|
||||
|
||||
# Overriding SRAM_LEN is not allowed.
|
||||
ifeq ($(TEXT_BANK),sram)
|
||||
# SRAM TEXT_BASE is fixed by SecureROM.
|
||||
TEXT_BASE := 0x48818000
|
||||
|
||||
# iBSS/LLB memory configuration
|
||||
ifeq ($(TEXT_FOOTPRINT),)
|
||||
TEXT_FOOTPRINT:= 1024*1024
|
||||
endif
|
||||
endif
|
||||
|
||||
# platform target can override sdram config by specifying this in target config file (apps/iBoot/$target-config.mk)
|
||||
ifeq ($(SDRAM_LEN),)
|
||||
SDRAM_LEN := 512*1024*1024
|
||||
|
||||
# iBoot/iBEC memory configuration
|
||||
ifeq ($(TEXT_BANK),sdram)
|
||||
# SDRAM TEXT_BASE is now set such that you don't have to do lots of math to
|
||||
# calulate the correct value if you change any of the other region sizes:
|
||||
# TEXT_BASE = SDRAM_BASE + SDRAM_LEN - 64MB
|
||||
TEXT_BASE := 0x9C000000
|
||||
|
||||
ifeq ($(TEXT_FOOTPRINT),)
|
||||
TEXT_FOOTPRINT := 1024*1024
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(TEXT_BANK),srom)
|
||||
MAX_DFU_SIZE := 128*1024
|
||||
endif
|
||||
ifeq ($(TEXT_BANK),sram)
|
||||
MAX_DFU_SIZE := 1056*1024
|
||||
endif
|
||||
|
||||
# Platform target can override any of these sizes by specifying in target config file (apps/iBoot/$target-config.mk)
|
||||
ifeq ($(TZ0_SIZE),)
|
||||
TZ0_SIZE := 8*1024*1024
|
||||
endif
|
||||
ifeq ($(DISPLAY_SIZE),)
|
||||
DISPLAY_SIZE := 4*1024*1024
|
||||
endif
|
||||
|
||||
OPTIONS += \
|
||||
AIC_CPU_ID=0 \
|
||||
L2_CACHE_SIZE=512*1024 \
|
||||
L2_CACHE_SETS=10 \
|
||||
WITH_NON_COHERENT_DMA=1 \
|
||||
ANC_PPNNPL_DS_DRIVE_STRENGTH=6 \
|
||||
ANC_LINK_CMD_ADDR_PULSE_TIMING_CA_HOLD_TIME=1 \
|
||||
ANC_LINK_CMD_ADDR_PULSE_TIMING_CA_SETUP_TIME=1 \
|
||||
ANC_LINK_SDR_REN_HOLD_TIME=0 \
|
||||
ANC_LINK_SDR_REN_SETUP_TIME=1 \
|
||||
ANC_LINK_SDR_WEN_HOLD_TIME=0 \
|
||||
ANC_LINK_SDR_WEN_SETUP_TIME=1 \
|
||||
ANC_LINK_SDR_DATA_CAPTURE_DELAY=0 \
|
||||
ANC_LINK_SDR_CLE_ALE_SETUP_TIME=1 \
|
||||
ANC_BOOT_CONTROLLERS=1 \
|
||||
ANC_TOGGLE_SUPPORTED=0 \
|
||||
DISPLAY_SIZE="$(DISPLAY_SIZE)ULL" \
|
||||
PLATFORM_ENTROPY_RATIO=200 \
|
||||
PLATFORM_IRQ_COUNT=256 \
|
||||
PLATFORM_SPDS_CHIP_REV=$(PLATFORM)/$(SPDS_CHIP_REV) \
|
||||
SDRAM_LEN="$(SDRAM_LEN)ULL" \
|
||||
TZ0_SIZE="$(TZ0_SIZE)ULL" \
|
||||
TEXT_BASE="$(TEXT_BASE)" \
|
||||
TEXT_FOOTPRINT="$(TEXT_FOOTPRINT)" \
|
||||
WITH_DPA=1 \
|
||||
WITH_DMA_CLEAR=1
|
||||
|
||||
# This platform contains corecrypto, needs large idle task stack for DFU stages.
|
||||
ifeq ($(PRODUCT),iBSS)
|
||||
OPTIONS += \
|
||||
IDLE_TASK_SIZE=0x3000 \
|
||||
PLATFORM_START_FUNCTION=_platform_start
|
||||
endif
|
||||
|
||||
ifeq ($(PRODUCT),LLB)
|
||||
OPTIONS += \
|
||||
IDLE_TASK_SIZE=0x3000 \
|
||||
PLATFORM_START_FUNCTION=_platform_start
|
||||
endif
|
||||
|
||||
ifeq ($(APPLICATION),SecureROM)
|
||||
DATA_BASE := 0x48800000
|
||||
OPTIONS += \
|
||||
IDLE_TASK_SIZE=0x3000 \
|
||||
WITH_ROM_TRAMPOLINE=1 \
|
||||
DATA_BASE="$(DATA_BASE)"
|
||||
|
||||
GLOBAL_LDFLAGS += \
|
||||
-segaddr __DATA $(DATA_BASE)
|
||||
ifeq ($(CONFIGS),fpga)
|
||||
OPTIONS += \
|
||||
SUPPORT_FPGA=1
|
||||
endif
|
||||
endif
|
||||
|
||||
GLOBAL_LDFLAGS += \
|
||||
-seg1addr $(TEXT_BASE)
|
||||
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/asm.o \
|
||||
$(LOCAL_DIR)/trampoline.o \
|
||||
$(LOCAL_DIR)/init.o
|
||||
@@ -0,0 +1,64 @@
|
||||
|
||||
/*
|
||||
* Copyright (c) 2014 - 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <arch/arm/assembler.h>
|
||||
#include <platform/trampoline.h>
|
||||
|
||||
// iBSS & LLB trampoline
|
||||
#if APPLICATION_IBOOT && (PRODUCT_IBSS || PRODUCT_LLB)
|
||||
.text
|
||||
.arm
|
||||
.align 12
|
||||
.globl _boot_handoff_trampoline, _boot_handoff_trampoline_end
|
||||
_boot_handoff_trampoline:
|
||||
// Reset VBAR to 0
|
||||
mov r1, #0 // iBSS and LLB doesn't pass forward anything to next stage.
|
||||
mcr p15, 0, r1, c12, c0, 0
|
||||
isb
|
||||
bx r0
|
||||
_boot_handoff_trampoline_end:
|
||||
#endif
|
||||
|
||||
// SecureROM trampoline
|
||||
#if WITH_ROM_TRAMPOLINE
|
||||
.text
|
||||
.arm
|
||||
.align 12
|
||||
.globl _boot_handoff_trampoline, _boot_handoff_trampoline_end
|
||||
_boot_handoff_trampoline:
|
||||
ldr r1, _trampoline_reg
|
||||
ldr r2, _trampoline_val
|
||||
ldr r3, [r1]
|
||||
orr r3, r2
|
||||
str r3, [r1]
|
||||
dsb sy
|
||||
ldr r3, [r1]
|
||||
tst r3, r2 // Verify ROM access is disabled
|
||||
beq 1f
|
||||
|
||||
mov r4, r0
|
||||
mov r0, #0
|
||||
mov r1, #0
|
||||
mov r2, #0
|
||||
mov r3, #0
|
||||
bx r4
|
||||
|
||||
1: // trampoline spin function
|
||||
wfi
|
||||
b .
|
||||
|
||||
_trampoline_reg:
|
||||
.word SECURITY_REG
|
||||
_trampoline_val:
|
||||
.word ROM_READ_DISABLE
|
||||
.align CPU_CACHELINE_SHIFT
|
||||
_boot_handoff_trampoline_end:
|
||||
#endif
|
||||
Reference in new issue
Block a user