first and last commit

2023-07-08 13:03:17 -07:00
commit 1bf4efd552
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <platform.h>
+#include <platform/soc/chipid.h>
+#include <platform/soc/hwclocks.h>
+#include <platform/soc/pmgr.h>
+
+bool chipid_get_current_production_mode(void)
+{
+	return MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_XTRCT(rCFG_FUSE0) != 0;
+}
+
+bool chipid_get_raw_production_mode(void)
+{
+	return MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_XTRCT(rCFG_FUSE0_RAW) != 0;
+}
+
+void chipid_clear_production_mode(void)
+{
+	rCFG_FUSE0 &= ~MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_UMASK;
+}
+
+bool chipid_get_secure_mode(void)
+{
+	// demotion only applies to the SEP, so iBoot always reads
+	// the raw value for secure mode (<rdar://problem/15182573>)
+	return MINIPMGR_FUSE_CFG_FUSE0_SECURE_MODE_XTRCT(rCFG_FUSE0_RAW);
+}
+
+uint32_t chipid_get_security_domain(void)
+{
+	return MINIPMGR_FUSE_CFG_FUSE0_SECURITY_DOMAIN_XTRCT(rCFG_FUSE0);
+}
+
+uint32_t chipid_get_board_id(void)
+{
+	return MINIPMGR_FUSE_CFG_FUSE0_BID_XTRCT(rCFG_FUSE0);
+}
+
+uint32_t chipid_get_minimum_epoch(void)
+{
+	return MINIPMGR_FUSE_CFG_FUSE0_MINIMUM_EPOCH_XTRCT(rCFG_FUSE0);
+}
+
+uint32_t chipid_get_chip_id(void)
+{
+	return 0x8002;
+}
+
+uint32_t chipid_get_chip_revision(void)
+{
+	uint32_t fuse_val = MINIPMGR_FUSE_CFG_FUSE4_DEV_VERSION_XTRCT(rCFG_FUSE4);
+
+	// we use 4 bits for base layer and 4 bits for metal,
+	// the fuses use 3 for each
+	return (fuse_val & 0x7) | (((fuse_val >> 3) & 0x7) << 4);
+}
+
+uint32_t chipid_get_osc_frequency(void)
+{
+	return OSC_FREQ;
+}
+
+uint64_t chipid_get_ecid_id(void)
+{
+	return ((uint64_t)rECIDHI << 32) | rECIDLO;
+}
+
+uint64_t chipid_get_die_id(void)
+{
+	return ((uint64_t)rECIDHI << 32) | rECIDLO;
+}
+
+uint32_t chipid_get_soc_voltage(uint32_t index)
+{
+	uint32_t soc_voltage = 0;
+
+	return soc_voltage;
+}
+
+uint32_t chipid_get_cpu_voltage(uint32_t index)
+{
+	uint32_t cpu_voltage = 0;
+
+	return cpu_voltage;
+}
+
+
+uint32_t chipid_get_ram_voltage(uint32_t index)
+{
+	uint32_t sram_voltage = 0;
+
+	return sram_voltage;
+}
+
+bool chipid_get_fuse_lock(void)
+{
+	return MINIPMGR_FUSE_CFG_FUSE1_AP_LOCK_XTRCT(rCFG_FUSE1) != 0;
+}
+
+void chipid_set_fuse_lock(bool locked)
+{
+	if (locked) {
+		rCFG_FUSE1 |= MINIPMGR_FUSE_CFG_FUSE1_AP_LOCK_INSRT(1);
+		asm("dsb sy");
+		if (!chipid_get_fuse_lock()) {
+			panic("Failed to lock fuses\n");
+		}
+	}
+}
+
+bool chipid_get_fuse_seal(void)
+{
+	return MINIPMGR_FUSE_CFG_FUSE1_SEAL_FUSES_XTRCT(rCFG_FUSE1) != 0;
+}
+
+uint32_t chipid_get_fuse_revision(void)
+{
+	return MINIPMGR_FUSE_CFG_FUSE4_REV_XTRCT(rCFG_FUSE4);
+}
+
+uint32_t chipid_get_total_rails_leakage()
+{
+	uint32_t total_leakage;
+	uint32_t leakage_data0; 
+	uint8_t leakage_data1;
+
+	leakage_data0 = rCFG_FUSE5;
+	leakage_data1 = (rCFG_FUSE4 >> 31) & 1;
+
+	total_leakage = ((leakage_data0 >> 28) & 0xf) + 1;				// soc_sram: cfg_fuse4[31:28]
+	total_leakage += ((leakage_data0 >> 24) & 0xf) + 1;				// cpu_sram: cfg_fuse4[27:24]
+	total_leakage += ((leakage_data0 >> 16) & 0xff) + 1;				// gpu: cfg_fuse4[23:16]
+	total_leakage += ((leakage_data0 >> 8) & 0xff) + 1;				// soc: cfg_fuse4[15:8]
+	total_leakage += ((((leakage_data0 >> 0) & 0xff) << 1) | leakage_data1) + 1;	// cpu: cfg_fuse4[7:0], cfg_fuse4[31]
+
+	return total_leakage;
+}
@@ -0,0 +1,20 @@
+# Copyright (C) 2013 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_PLATFORM_CHIPID=1
+
+ALL_OBJS += $(LOCAL_DIR)/chipid.o
+
+ifeq ($(SUB_PLATFORM),t8002)
+ALL_OBJS += \
+	$(LOCAL_DIR)/tunables_pmgr_t8002.o
+endif
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+/* This file contains Tunables for t8002 */
+
+#include <platform/tunables.h>
+#include <platform/soc/chipid.h>
+#include <platform/soc/hwregbase.h>
+#include <soc/module/address_map.h>
+
+/**************************************** BEGIN CHIP_REVISION_B0 ****************************************/
+#include <soc/t8002/b0/tunable/minipmgr.h>
+#include <soc/t8002/b0/tunable/pmgr.h>
+#include <soc/t8002/b0/tunable/cpu_fabric.h>
+#include <soc/t8002/b0/tunable/nrt_fabric.h>
+#include <soc/t8002/b0/tunable/uvdc.h>
+#include <soc/t8002/b0/tunable/pio_wrap.h>
+
+static const struct tunable_struct pmgr_tunable_t8002_b0[] = {
+    PMS_PMGR_DEFAULT_TUNABLES_T8002_B0
+};
+
+static const struct tunable_struct minipmgr_tunable_t8002_b0[] = {
+    AOP_MINIPMGR_DEFAULT_TUNABLES_T8002_B0
+};
+
+static const struct tunable_struct cpu_fabric_tunable_t8002_b0[] = {
+    PIO_CPU_FABRIC_DEFAULT_TUNABLES_T8002_B0
+};
+
+static const struct tunable_struct nrt_fabric_tunable_t8002_b0[] = {
+    PIO_NRT_FABRIC_DEFAULT_TUNABLES_T8002_B0
+};
+
+static const struct tunable_struct uvdc_tunable_t8002_b0[] = {
+    PMS_UVDC_DEFAULT_TUNABLES_T8002_B0
+};
+
+static const struct tunable_struct pio_wrap_tunable_t8002_b0[] = {
+    PIO_PIO_WRAP_DEFAULT_TUNABLES_T8002_B0
+};
+/***************************************** END CHIP_REVISION_B0 *****************************************/
+
+/**************************************** BEGIN CHIP_REVISION_A0 ****************************************/
+#include <soc/t8002/a0/tunable/minipmgr.h>
+#include <soc/t8002/a0/tunable/pmgr.h>
+#include <soc/t8002/a0/tunable/cpu_fabric.h>
+#include <soc/t8002/a0/tunable/nrt_fabric.h>
+#include <soc/t8002/a0/tunable/uvdc.h>
+#include <soc/t8002/a0/tunable/pio_wrap.h>
+
+static const struct tunable_struct pmgr_tunable_t8002_a0[] = {
+    PMS_PMGR_DEFAULT_TUNABLES_T8002_A0
+};
+
+static const struct tunable_struct minipmgr_tunable_t8002_a0[] = {
+    AOP_MINIPMGR_DEFAULT_TUNABLES_T8002_A0
+};
+
+static const struct tunable_struct cpu_fabric_tunable_t8002_a0[] = {
+    PIO_CPU_FABRIC_DEFAULT_TUNABLES_T8002_A0
+};
+
+static const struct tunable_struct nrt_fabric_tunable_t8002_a0[] = {
+    PIO_NRT_FABRIC_DEFAULT_TUNABLES_T8002_A0
+};
+
+static const struct tunable_struct uvdc_tunable_t8002_a0[] = {
+    PMS_UVDC_DEFAULT_TUNABLES_T8002_A0
+};
+
+static const struct tunable_struct pio_wrap_tunable_t8002_a0[] = {
+    PIO_PIO_WRAP_DEFAULT_TUNABLES_T8002_A0
+};
+/***************************************** END CHIP_REVISION_A0 *****************************************/
+
+const struct tunable_chip_struct tunables_pmgr[] = {
+    // B0
+    {CHIP_REVISION_B0,         PMS_PMGR_PADDR_T8002_B0,         pmgr_tunable_t8002_b0,       NULL, true},
+    {CHIP_REVISION_B0,         AOP_MINIPMGR_PADDR_T8002_B0,     minipmgr_tunable_t8002_b0,   NULL, false},
+    {CHIP_REVISION_B0,         PIO_CPU_FABRIC_PADDR_T8002_B0,   cpu_fabric_tunable_t8002_b0, NULL, true},
+    {CHIP_REVISION_B0,         PIO_NRT_FABRIC_PADDR_T8002_B0,   nrt_fabric_tunable_t8002_b0, NULL, true},
+    {CHIP_REVISION_B0,         PMS_UVDC_PADDR_T8002_B0,         uvdc_tunable_t8002_b0,       NULL, true},
+    {CHIP_REVISION_B0,         PIO_PIO_WRAP_PADDR_T8002_B0,     pio_wrap_tunable_t8002_b0,   NULL, true},
+
+    // A0
+    {CHIP_REVISION_A0,         PMS_PMGR_PADDR_T8002_A0,         pmgr_tunable_t8002_a0,       NULL, true},
+    {CHIP_REVISION_A0,         AOP_MINIPMGR_PADDR_T8002_A0,     minipmgr_tunable_t8002_a0,   NULL, false},
+    {CHIP_REVISION_A0,         PIO_CPU_FABRIC_PADDR_T8002_A0,   cpu_fabric_tunable_t8002_a0, NULL, true},
+    {CHIP_REVISION_A0,         PIO_NRT_FABRIC_PADDR_T8002_A0,   nrt_fabric_tunable_t8002_a0, NULL, true},
+    {CHIP_REVISION_A0,         PMS_UVDC_PADDR_T8002_A0,         uvdc_tunable_t8002_a0,       NULL, true},
+    {CHIP_REVISION_A0,         PIO_PIO_WRAP_PADDR_T8002_A0,     pio_wrap_tunable_t8002_a0,   NULL, true},
+
+    {-1, -1, NULL, NULL, false},
+};
+
+const struct tunable_filtered_chip_struct tunables_filtered_pmgr[] = {
+    // B0
+    // Applied in OS
+    {CHIP_REVISION_B0, AOP_MINIPMGR_PADDR_T8002_B0 + MINIPMGR_MINI_CLKCFG_PROXY_OSC_CLK_CFG_OFFSET, AOP_MINIPMGR_PADDR_T8002_B0 + MINIPMGR_MINI_CLKCFG_XI0MUX_CLK_CFG_OFFSET, true, true},
+    {CHIP_REVISION_B0, AOP_MINIPMGR_PADDR_T8002_B0 + MINIPMGR_MINI_MISC_CFG_ACG_OFFSET, AOP_MINIPMGR_PADDR_T8002_B0 + MINIPMGR_MINI_MISC_CFG_ACG_OFFSET, true, true},
+    {CHIP_REVISION_B0, PMS_PMGR_PADDR_T8002_B0 + PMGR_MISC_CFG_ACG_OFFSET, PMS_PMGR_PADDR_T8002_B0 + PMGR_MISC_CFG_ACG_OFFSET, true, true},
+
+    // A0
+    // Applied in OS
+    {CHIP_REVISION_A0, AOP_MINIPMGR_PADDR_T8002_A0 + MINIPMGR_MINI_CLKCFG_PROXY_OSC_CLK_CFG_OFFSET, AOP_MINIPMGR_PADDR_T8002_A0 + MINIPMGR_MINI_CLKCFG_XI0MUX_CLK_CFG_OFFSET, true, true},
+    {CHIP_REVISION_A0, AOP_MINIPMGR_PADDR_T8002_A0 + MINIPMGR_MINI_MISC_CFG_ACG_OFFSET, AOP_MINIPMGR_PADDR_T8002_A0 + MINIPMGR_MINI_MISC_CFG_ACG_OFFSET, true, true},
+    {CHIP_REVISION_A0, PMS_PMGR_PADDR_T8002_A0 + PMGR_MISC_CFG_ACG_OFFSET, PMS_PMGR_PADDR_T8002_A0 + PMGR_MISC_CFG_ACG_OFFSET, true, true},
+
+    {-1, -1, -1, NULL, false},
+};