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/*
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* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifdef APCIE_DEBUG_LEVEL
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#define DEBUG_LEVEL APCIE_DEBUG_LEVEL
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#endif
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#include <debug.h>
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#include <arch/arm/arm.h>
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#include <lib/devicetree.h>
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#include <drivers/apcie.h>
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#include <drivers/dart.h>
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#include <platform.h>
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#include <platform/apcie.h>
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#include <platform/apcie_regs.h>
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#include <platform/gpio.h>
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#include <platform/gpiodef.h>
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#include <platform/timer.h>
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#include <platform/tunables.h>
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#include <platform/soc/chipid.h>
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#include <platform/soc/hwclocks.h>
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#include <platform/soc/hwisr.h>
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#include <platform/soc/hwregbase.h>
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#include <sys.h>
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#include <sys/menu.h>
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#include SUB_PLATFORM_SPDS_HEADER(apcie_common)
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#include SUB_PLATFORM_SPDS_HEADER(apcie_phy_glue)
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#include SUB_PLATFORM_SPDS_HEADER(pma_cmn_registers)
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#include SUB_PLATFORM_SPDS_HEADER(pma_rx_lane_registers)
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#include SUB_PLATFORM_SPDS_HEADER(pma_tx_lane_registers)
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#include SUB_PLATFORM_SPDS_HEADER(x2_pcie_rc)
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#include SUB_PLATFORM_TUNABLE_HEADER(apcie_common)
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#include SUB_PLATFORM_TUNABLE_HEADER(apcie_config)
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#include SUB_PLATFORM_TUNABLE_HEADER(x2_pcie_rc)
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#define MAX_DT_PROPERTY_SIZE 4096
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////////////////////////////////////////////////////////////////////////////////
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// APCIe common tunables
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#if APPLICATION_SECUREROM
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// T8010 A0
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static const struct tunable_struct common_tunables_a0 [] = {
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PCIE_APCIE_COMMON_SECURE_ROM_TUNABLES_T8010_A0
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};
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#else // !APPLICATION_SECUREROM
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// T8010 A0
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static const struct tunable_struct common_tunables_a0 [] = {
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PCIE_APCIE_COMMON_DEFAULT_TUNABLES_T8010_A0
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};
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// APCIe common NVMe tunables
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// T8010 A0
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static const struct tunable_struct common_nvme_tunables_a0 [] = {
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PCIE_APCIE_COMMON_NVME_TUNABLES_T8010_A0
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};
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// T8010 chip revision table
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static const struct tunable_chip_struct tunables_nvme_common [] = {
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{CHIP_REVISION_A0, APCIE_COMMON_BASE_ADDR, common_nvme_tunables_a0 , NULL, false},
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};
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#endif // APPLICATION_SECUREROM
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// T8010 chip revision table
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static const struct tunable_chip_struct tunables_pcie_common [] = {
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{CHIP_REVISION_A0, APCIE_COMMON_BASE_ADDR, common_tunables_a0 , NULL, false},
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};
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////////////////////////////////////////////////////////////////////////////////
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// APCIe config tunables
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#if APPLICATION_SECUREROM
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// T8010 A0
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static const struct tunable_struct port0_config_tunable_a0[] = {
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PCIE_APCIE_PORT0_APCIE_CONFIG_SECURE_ROM_TUNABLES_T8010_A0
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};
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static const struct tunable_struct port1_config_tunable_a0[] = {
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PCIE_APCIE_PORT1_APCIE_CONFIG_SECURE_ROM_TUNABLES_T8010_A0
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};
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static const struct tunable_struct port2_config_tunable_a0[] = {
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PCIE_APCIE_PORT2_APCIE_CONFIG_SECURE_ROM_TUNABLES_T8010_A0
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};
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static const struct tunable_struct port3_config_tunable_a0[] = {
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PCIE_APCIE_PORT3_APCIE_CONFIG_SECURE_ROM_TUNABLES_T8010_A0
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};
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#else // !APPLICATION_SECUREROM
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// T8010 A0
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static const struct tunable_struct port0_config_tunable_a0[] = {
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PCIE_APCIE_PORT0_APCIE_CONFIG_DEFAULT_TUNABLES_T8010_A0
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};
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static const struct tunable_struct port1_config_tunable_a0[] = {
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PCIE_APCIE_PORT1_APCIE_CONFIG_DEFAULT_TUNABLES_T8010_A0
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};
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static const struct tunable_struct port2_config_tunable_a0[] = {
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PCIE_APCIE_PORT2_APCIE_CONFIG_DEFAULT_TUNABLES_T8010_A0
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};
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static const struct tunable_struct port3_config_tunable_a0[] = {
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PCIE_APCIE_PORT3_APCIE_CONFIG_DEFAULT_TUNABLES_T8010_A0
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};
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#endif // !APPLICATION_SECUREROM
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// T8010 chip revision table
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static const struct tunable_chip_struct tunables_pcie_config_port_0[] = {
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{CHIP_REVISION_A0, APCIE_PORT_BASE_ADDR(0), port0_config_tunable_a0, NULL, false},
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};
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static const struct tunable_chip_struct tunables_pcie_config_port_1[] = {
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{CHIP_REVISION_A0, APCIE_PORT_BASE_ADDR(1), port1_config_tunable_a0, NULL, false},
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};
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static const struct tunable_chip_struct tunables_pcie_config_port_2[] = {
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{CHIP_REVISION_A0, APCIE_PORT_BASE_ADDR(2), port2_config_tunable_a0, NULL, false},
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};
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static const struct tunable_chip_struct tunables_pcie_config_port_3[] = {
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{CHIP_REVISION_A0, APCIE_PORT_BASE_ADDR(3), port3_config_tunable_a0, NULL, false},
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};
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// T8010 port chip revision table
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static const struct tunable_chip_array tunables_pcie_config_ports[APCIE_NUM_LINKS] = {
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{ tunables_pcie_config_port_0, ARRAY_SIZE(tunables_pcie_config_port_0), 0 },
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{ tunables_pcie_config_port_1, ARRAY_SIZE(tunables_pcie_config_port_1), 0 },
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{ tunables_pcie_config_port_2, ARRAY_SIZE(tunables_pcie_config_port_2), 0 },
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{ tunables_pcie_config_port_3, ARRAY_SIZE(tunables_pcie_config_port_3), 0 },
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};
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////////////////////////////////////////////////////////////////////////////////
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// PCIe root complex tunables
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#if APPLICATION_SECUREROM
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// T8010 A0
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static const struct tunable_struct rc0_config_tunable_a0[] = {
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PCIE_PCIE_CONFIG_PCIE_RC0_SECURE_ROM_TUNABLES_T8010_A0
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};
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static const struct tunable_struct rc1_config_tunable_a0[] = {
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PCIE_PCIE_CONFIG_PCIE_RC1_SECURE_ROM_TUNABLES_T8010_A0
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};
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static const struct tunable_struct rc2_config_tunable_a0[] = {
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PCIE_PCIE_CONFIG_PCIE_RC2_SECURE_ROM_TUNABLES_T8010_A0
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};
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static const struct tunable_struct rc3_config_tunable_a0[] = {
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PCIE_PCIE_CONFIG_PCIE_RC3_SECURE_ROM_TUNABLES_T8010_A0
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};
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#else // !APPLICATION_SECUREROM
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// T8010 A0
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static const struct tunable_struct rc0_config_tunable_a0[] = {
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PCIE_PCIE_CONFIG_PCIE_RC0_DEFAULT_TUNABLES_T8010_A0
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};
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static const struct tunable_struct rc1_config_tunable_a0[] = {
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PCIE_PCIE_CONFIG_PCIE_RC1_DEFAULT_TUNABLES_T8010_A0
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};
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static const struct tunable_struct rc2_config_tunable_a0[] = {
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PCIE_PCIE_CONFIG_PCIE_RC2_DEFAULT_TUNABLES_T8010_A0
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};
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static const struct tunable_struct rc3_config_tunable_a0[] = {
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PCIE_PCIE_CONFIG_PCIE_RC3_DEFAULT_TUNABLES_T8010_A0
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};
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#endif // !APPLICATION_SECUREROM
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// T8010 chip revision table
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static const struct tunable_chip_struct tunables_pcie_config_rc_0[] = {
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{CHIP_REVISION_A0, PCIE_PORT_BASE_ADDR(0), rc0_config_tunable_a0, NULL, false},
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};
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static const struct tunable_chip_struct tunables_pcie_config_rc_1[] = {
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{CHIP_REVISION_A0, PCIE_PORT_BASE_ADDR(1), rc1_config_tunable_a0, NULL, false},
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};
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static const struct tunable_chip_struct tunables_pcie_config_rc_2[] = {
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{CHIP_REVISION_A0, PCIE_PORT_BASE_ADDR(2), rc2_config_tunable_a0, NULL, false},
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};
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static const struct tunable_chip_struct tunables_pcie_config_rc_3[] = {
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{CHIP_REVISION_A0, PCIE_PORT_BASE_ADDR(3), rc3_config_tunable_a0, NULL, false},
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};
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// T8010 port chip revision table
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static const struct tunable_chip_array tunables_pcie_config_rc[APCIE_NUM_LINKS] = {
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{ tunables_pcie_config_rc_0, ARRAY_SIZE(tunables_pcie_config_rc_0), 0 },
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{ tunables_pcie_config_rc_1, ARRAY_SIZE(tunables_pcie_config_rc_1), 0 },
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{ tunables_pcie_config_rc_2, ARRAY_SIZE(tunables_pcie_config_rc_2), 0 },
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{ tunables_pcie_config_rc_3, ARRAY_SIZE(tunables_pcie_config_rc_3), 0 },
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};
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////////////////////////////////////////////////////////////////////////////////
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// PHY tunables
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// T8010 A0
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static const struct tunable_struct phy_glue_tunable_a0[] = {
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#ifdef PCIE_APCIE_PHY_GLUE_DEFAULT_TUNABLES_T8010_A0
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PCIE_APCIE_PHY_GLUE_DEFAULT_TUNABLES_T8010_A0
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#else
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// Temporary until tunables are actually defined.
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TUNABLE_TABLE_END_MARKER
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#endif
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};
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const struct tunable_chip_struct tunables_pcie_phy[] = {
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{CHIP_REVISION_A0, APCIE_PHY_BASE_ADDR, phy_glue_tunable_a0, NULL, false},
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};
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////////////////////////////////////////////////////////////////////////////////
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static bool s3e_mode;
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static bool s3e_reset_on_enable_disable;
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static uint32_t link_enable_count;
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#define SET_REG(reg, value) set_reg(APCIE_COMMON_BASE_ADDR, APCIE_COMMON_BLK_APCIE_ ## reg ## _OFFSET, (value))
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#define GET_REG(reg) get_reg(APCIE_COMMON_BASE_ADDR, APCIE_COMMON_BLK_APCIE_ ## reg ## _OFFSET)
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#define OR_REG(reg, value) or_reg(APCIE_COMMON_BASE_ADDR, APCIE_COMMON_BLK_APCIE_ ## reg ## _OFFSET, (value))
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#define AND_REG(reg, value) and_reg(APCIE_COMMON_BASE_ADDR, APCIE_COMMON_BLK_APCIE_ ## reg ## _OFFSET, (value))
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#define PORT_STRIDE (APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_OFFSET - APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_OFFSET)
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#define PORT_REG(reg, port) (APCIE_COMMON_BLK_APCIE_ ## reg ## _OFFSET) + (PORT_STRIDE * (port))
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#define SET_PORT_REG(reg, port, value) set_reg(APCIE_COMMON_BASE_ADDR, PORT_REG(reg, port), value)
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#define GET_PORT_REG(reg, port) get_reg(APCIE_COMMON_BASE_ADDR, PORT_REG(reg, port))
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#define OR_PORT_REG(reg, port, value) or_reg(APCIE_COMMON_BASE_ADDR, PORT_REG(reg, port), value)
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#define AND_PORT_REG(reg, port, value) and_reg(APCIE_COMMON_BASE_ADDR, PORT_REG(reg, port), value)
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#define PORT_REG_BIT_SHIFT(reg, bit) (APCIE_COMMON_BLK_APCIE_ ## reg ## _ ## bit ## _SHIFT)
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#define SET_PORT_REG_BIT(reg, port, b) or_reg(APCIE_COMMON_BASE_ADDR, PORT_REG(reg, port), 1 << PORT_REG_BIT_SHIFT(reg, b))
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#define CLR_PORT_REG_BIT(reg, port, b) and_reg(APCIE_COMMON_BASE_ADDR, PORT_REG(reg, port), ~(1 << PORT_REG_BIT_SHIFT(reg, b)))
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#define GET_PORT_REG_BIT(reg, port, b) ((get_reg(APCIE_COMMON_BASE_ADDR, PORT_REG(reg, port)) >> PORT_REG_BIT_SHIFT(reg, b)) & 1)
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#define SET_APCIE_CONFIG_REG(reg, port, value) set_reg(APCIE_PORT_BASE_ADDR(port), (reg), (value))
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#define GET_APCIE_CONFIG_REG(reg, port) get_reg(APCIE_PORT_BASE_ADDR(port), (reg))
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#define OR_APCIE_CONFIG_REG(reg, port, value) or_reg(APCIE_PORT_BASE_ADDR(port), (reg), (value))
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#define AND_APCIE_CONFIG_REG(reg, port, value) and_reg(APCIE_PORT_BASE_ADDR(port), (reg), (value))
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#define PHY_SET_REG(reg, value) set_reg(APCIE_PHY_BASE_ADDR, APCIE_PHY_GLUE_BLK_ ## reg ## _OFFSET, (value))
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#define PHY_GET_REG(reg) get_reg(APCIE_PHY_BASE_ADDR, APCIE_PHY_GLUE_BLK_ ## reg ## _OFFSET)
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#define PHY_OR_REG(reg, value) or_reg(APCIE_PHY_BASE_ADDR, APCIE_PHY_GLUE_BLK_ ## reg ## _OFFSET, (value))
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#define PHY_AND_REG(reg, value) and_reg(APCIE_PHY_BASE_ADDR, APCIE_PHY_GLUE_BLK_ ## reg ## _OFFSET, (value))
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#define SET_PMA_CMN_REG(reg, value) set_reg(APCIE_PHY_PMA_COMMON_BASE_ADDR, PMA_CMN_REGISTERS_BLK_ ## reg ## _OFFSET, (value))
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#define GET_PMA_CMN_REG(reg) get_reg(APCIE_PHY_PMA_COMMON_BASE_ADDR, PMA_CMN_REGISTERS_BLK_ ## reg ## _OFFSET)
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#define OR_PMA_CMN_REG(reg, value) or_reg(APCIE_PHY_PMA_COMMON_BASE_ADDR, PMA_CMN_REGISTERS_BLK_ ## reg ## _OFFSET, (value))
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#define AND_PMA_CMN_REG(reg, value) and_reg(APCIE_PHY_PMA_COMMON_BASE_ADDR, PMA_CMN_REGISTERS_BLK_ ## reg ## _OFFSET, (value))
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#define PMA_RX_REG(reg, lane) (PMA_RX_LANE_REGISTERS_BLK_ ## reg ## _OFFSET) + (APCIE_PHY_PMA_RX_LANE_STRIDE * (lane))
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#define SET_PMA_RX_REG(reg, lane, value) set_reg(APCIE_PHY_PMA_RX_LANE_BASE_ADDR, PMA_RX_REG(reg, lane), value)
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#define GET_PMA_RX_REG(reg, lane) get_reg(APCIE_PHY_PMA_RX_LANE_BASE_ADDR, PMA_RX_REG(reg, lane))
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#define OR_PMA_RX_REG(reg, lane, value) or_reg(APCIE_PHY_PMA_RX_LANE_BASE_ADDR, PMA_RX_REG(reg, lane), value)
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#define AND_PMA_RX_REG(reg, lane, value) and_reg(APCIE_PHY_PMA_RX_LANE_BASE_ADDR, PMA_RX_REG(reg, lane), value)
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#define PMA_TX_REG(reg, lane) (PMA_TX_LANE_REGISTERS_BLK_ ## reg ## _OFFSET) + (APCIE_PHY_PMA_TX_LANE_STRIDE * (lane))
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#define SET_PMA_TX_REG(reg, lane, value) set_reg(APCIE_PHY_PMA_TX_LANE_BASE_ADDR, PMA_TX_REG(reg, lane), value)
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#define GET_PMA_TX_REG(reg, lane) get_reg(APCIE_PHY_PMA_TX_LANE_BASE_ADDR, PMA_TX_REG(reg, lane))
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#define OR_PMA_TX_REG(reg, lane, value) or_reg(APCIE_PHY_PMA_TX_LANE_BASE_ADDR, PMA_TX_REG(reg, lane), value)
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#define AND_PMA_TX_REG(reg, lane, value) and_reg(APCIE_PHY_PMA_TX_LANE_BASE_ADDR, PMA_TX_REG(reg, lane), value)
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static void set_reg(uintptr_t base, uint32_t offset, uint32_t value)
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{
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dprintf(DEBUG_SPEW, "apcie: set_reg[0x%lx] = 0x%x\n", base + offset, value);
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*(volatile uint32_t *)(base + offset) = value;
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}
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static uint32_t get_reg(uintptr_t base, uint32_t offset)
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{
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uint32_t value;
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dprintf(DEBUG_SPEW, "acpie: get_reg[0x%lx]", base + offset);
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value = *(volatile uint32_t *)(base + offset);
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dprintf(DEBUG_SPEW, " = 0x%x\n", value);
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return value;
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}
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static void or_reg(uintptr_t base, uint32_t offset, uint32_t value)
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{
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uint32_t orig;
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orig = get_reg(base, offset);
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set_reg(base, offset, orig | value);
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}
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static void and_reg(uintptr_t base, uint32_t offset, uint32_t value)
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{
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uint32_t orig;
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orig = get_reg(base, offset);
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set_reg(base, offset, orig & value);
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}
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void apcie_set_s3e_mode(bool reset_on_enable)
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{
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s3e_mode = true;
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s3e_reset_on_enable_disable = reset_on_enable;
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}
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static void apcie_enable_root_complex(void)
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{
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// PCIe Initialization Sequence v1.12.02, section 6.1.2:
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// 1. Program PCIE PLL parameters from PMGR fuses done in pmgr.c set_pll().
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// 2. Turn on PCIE in PCIE_PS register
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clock_gate(CLK_PCIE, true);
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// 3. Enable the 24Mhz clock
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clock_gate(CLK_PCIE_AUX, true);
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// 4. Enable the ref clock
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clock_gate(CLK_PCIE_REF, true);
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// Apply common tunables.
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platform_apply_tunables(tunables_pcie_common , ARRAY_SIZE(tunables_pcie_common ), "PCIe common");
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#if !APPLICATION_SECUREROM
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platform_apply_tunables(tunables_nvme_common , ARRAY_SIZE(tunables_nvme_common ), "NVMe common");
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#endif
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// 5. Enable clock auto clock management for the "common" clock domain -- not doing this in iBoot.
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// 6. Enable dynamic clock gating of per-link aux_xlk -- not doing this in iBoot.
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||||
|
||||
// 7. NAND_SYS_CLK/S3E_RESET_N reset sequence defined in Section 5.5.
|
||||
if (s3e_mode) {
|
||||
|
||||
if (s3e_reset_on_enable_disable) {
|
||||
AND_REG(NANDRST_CTRL, ~APCIE_COMMON_BLK_APCIE_NANDRST_CTRL_NANDRST_UMASK);
|
||||
}
|
||||
|
||||
gpio_configure(GPIO_NAND_SYS_CLK, GPIO_CFG_FUNC0);
|
||||
OR_REG(NANDSYSCLK_CTRL, APCIE_COMMON_BLK_APCIE_NANDSYSCLK_CTRL_NANDSYSCLK_EN_UMASK);
|
||||
// S3e spec requires 32 24 Mhz clock cycles from NANDSYSCLK to reset deassertion.
|
||||
// But, APCIe spec requires we wait 100 microseconds (Cayman PCIe spec section 5.5)
|
||||
spin(100);
|
||||
|
||||
// De-assert S3E_RESET_N if it's already asserted. Except when platform specified
|
||||
// s3e_reset_on_enable_disable (for example, in iBEC), we only de-assert the reset,
|
||||
// and then leave it de-asserted
|
||||
OR_REG(NANDRST_CTRL, APCIE_COMMON_BLK_APCIE_NANDRST_CTRL_NANDRST_UMASK);
|
||||
}
|
||||
|
||||
// 8. Select APCIE lane configuration
|
||||
SET_REG(LANE_CFG, APCIE_COMMON_BLK_APCIE_LANE_CFG_VALID_UMASK | platform_get_apcie_lane_cfg());
|
||||
|
||||
// 9. PCIe Phy is powered up:
|
||||
// APCIE_PHY_POWERUP_STS.powerup_done is set by the HW when Phy power-up sequence is completed
|
||||
while((GET_REG(PHY_POWERUP_STS) & APCIE_COMMON_BLK_APCIE_PHY_POWERUP_STS_POWERUP_DONE_UMASK) == 0)
|
||||
spin(1);
|
||||
|
||||
// 10. Software de-asserts phy_apb_reset_n
|
||||
OR_REG(PHY_CONFIG_RST_CTRL, APCIE_COMMON_BLK_APCIE_PHY_CONFIG_RST_CTRL_PHY_CFG_RST_N_UMASK);
|
||||
|
||||
// Apply SPDS-generated PHY tunable values
|
||||
platform_apply_tunables(tunables_pcie_phy, ARRAY_SIZE(tunables_pcie_phy), "PCIe PHY");
|
||||
|
||||
// 11. Select external REFCLK if desired -- not desired.
|
||||
|
||||
// The following is from Section 6.1.3 PCIe link bring-up sequence, step
|
||||
// 1.a.(iii). When internal REFCLK is selected, SW must ensure that REFCLK
|
||||
// provided by PCIe REFCLK PLL is stable before proceeding to link bring-up
|
||||
while ((GET_REG(PHY_POWERUP_STS) & APCIE_COMMON_BLK_APCIE_PHY_POWERUP_STS_PMGR_REFCLK_GOOD_UMASK) == 0)
|
||||
spin(1);
|
||||
}
|
||||
|
||||
static void apcie_disable_root_complex(void)
|
||||
{
|
||||
if (s3e_reset_on_enable_disable) {
|
||||
AND_REG(NANDRST_CTRL, ~APCIE_COMMON_BLK_APCIE_NANDRST_CTRL_NANDRST_UMASK);
|
||||
}
|
||||
|
||||
clock_set_device_reset(CLK_PCIE, true);
|
||||
|
||||
spin(10);
|
||||
|
||||
// WARNING: DO NOT power off PCIe CLK_PCIE_AUX, CLK_PCIE_REF, and CLK_PCIE
|
||||
// here. The SEP and AES blocks will be unhappy if you do that.
|
||||
// Just turn the clock off but leave the power on.
|
||||
power_on(CLK_PCIE_AUX);
|
||||
power_on(CLK_PCIE_REF);
|
||||
power_on(CLK_PCIE);
|
||||
|
||||
clock_set_device_reset(CLK_PCIE, false);
|
||||
}
|
||||
|
||||
// Implements the enable sequence from APCIe spec section 6.1.3 as it applies to
|
||||
// APCIE_COMMON registers. The portion of the sequence that affects the APCIE_CONFIG
|
||||
// registers is handled in common code
|
||||
static void apcie_enable_link_hardware(uint32_t link)
|
||||
{
|
||||
ASSERT(link < APCIE_NUM_LINKS);
|
||||
|
||||
dprintf(DEBUG_INFO, "apcie: Enabling link %d\n", link);
|
||||
|
||||
// Make sure PERST# starts out as asserted
|
||||
CLR_PORT_REG_BIT(PORT_RST_CTRL_0, link, APCIE_PERST_N);
|
||||
|
||||
// 1(i). 100Mhz REFCLK to the link partners is enabled
|
||||
SET_PORT_REG_BIT(PORT_REFCLK_CTRL_0, link, REFCLK_EN);
|
||||
|
||||
// 1(iii). SW must ensure that REFCLK provided by PCIe REFCLK PLL is stable
|
||||
// before proceeding to the next step
|
||||
while (GET_PORT_REG_BIT(PHY_POWERUP_STS, link, PMGR_REFCLK_GOOD) == 0)
|
||||
spin(10);
|
||||
|
||||
// 2. Configure CLKREQ# GPIO for the target link -- done in the common
|
||||
// code before calling this function
|
||||
|
||||
// 3. Wait until the endpoint asserts CLKREQ# -- done in the common
|
||||
// code before calling this function
|
||||
|
||||
// 4. Update link configuration -- skip this step in SecureROM/iBoot
|
||||
|
||||
// 5. Enable target PCIE link by setting APCIE_PORT_CTRL_{0/1/2/3}.port_en
|
||||
SET_PORT_REG_BIT(PORT_CTRL_0, link, PORT_EN);
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
SET_PORT_REG_BIT(PORT_CTRL_0, link, MUXED_AUXCLK_AUTO_DIS);
|
||||
#endif
|
||||
|
||||
// 6. De-assert PERST# for the target PCIE link.
|
||||
SET_PORT_REG_BIT(PORT_RST_CTRL_0, link, APCIE_PERST_N);
|
||||
while (GET_PORT_REG_BIT(PORT_STS_0, link, PORT_STS) == 0)
|
||||
spin(10);
|
||||
|
||||
// 7. Enable dynamic REFCLK clock gating -- skip this step in SecureROM/iBoot
|
||||
}
|
||||
|
||||
static void apcie_disable_link_hardware(uint32_t link)
|
||||
{
|
||||
ASSERT(link < APCIE_NUM_LINKS);
|
||||
|
||||
CLR_PORT_REG_BIT(PORT_RST_CTRL_0, link, APCIE_PERST_N);
|
||||
CLR_PORT_REG_BIT(PORT_REFCLK_CTRL_0, link, REFCLK_EN);
|
||||
CLR_PORT_REG_BIT(PORT_CTRL_0, link, PORT_EN);
|
||||
|
||||
while (GET_PORT_REG_BIT(PORT_STS_0, link, PORT_STS) != 0)
|
||||
spin(10);
|
||||
}
|
||||
|
||||
bool apcie_enable_link(uint32_t link)
|
||||
{
|
||||
struct apcie_link_config *config = &apcie_link_configs[link];
|
||||
struct apcie_link_status *status = &apcie_link_statuses[link];
|
||||
utime_t start;
|
||||
uint32_t counter_command;
|
||||
uint32_t force_width;
|
||||
uint32_t l1sub_cap;
|
||||
uint16_t link_control2;
|
||||
|
||||
ASSERT(link < APCIE_NUM_LINKS);
|
||||
|
||||
if (status->enabled)
|
||||
return true;
|
||||
|
||||
// Clocks to PCIe don't default to on since it isn't used in POR configurations
|
||||
if (link_enable_count == 0) {
|
||||
apcie_enable_root_complex();
|
||||
}
|
||||
|
||||
// Make sure PERST# starts out as asserted
|
||||
gpio_configure(config->perst_gpio, GPIO_CFG_OUT_0);
|
||||
gpio_configure(config->clkreq_gpio, GPIO_CFG_IN);
|
||||
|
||||
// wait for CLKREQ# to be asserted
|
||||
dprintf(DEBUG_INFO, "apcie: waiting for clkreq...");
|
||||
start = system_time();
|
||||
while (gpio_read(config->clkreq_gpio) != 0) {
|
||||
if (time_has_elapsed(start, APCIE_ENABLE_TIMEOUT)) {
|
||||
dprintf(DEBUG_CRITICAL, "apcie: timeout waiting for CLKREQ# on link %u\n", link);
|
||||
goto cleanup;
|
||||
}
|
||||
spin(1);
|
||||
}
|
||||
dprintf(DEBUG_INFO, " done\n");
|
||||
|
||||
gpio_configure(config->clkreq_gpio, GPIO_CFG_FUNC0);
|
||||
|
||||
// Do required initialization in APCIE_COMMON registers
|
||||
apcie_enable_link_hardware(link);
|
||||
|
||||
// Apply root complex config tunables
|
||||
platform_apply_tunables(tunables_pcie_config_rc[link].tunable_chip,
|
||||
tunables_pcie_config_rc[link].num_tunable_chips,
|
||||
"PCIe config");
|
||||
|
||||
// Apply APCIe config port tunables
|
||||
platform_apply_tunables(tunables_pcie_config_ports[link].tunable_chip,
|
||||
tunables_pcie_config_ports[link].num_tunable_chips,
|
||||
"APCIe config");
|
||||
|
||||
// Enable fabric timeout.
|
||||
OR_APCIE_CONFIG_REG(APCIE_CONFIG_BLK_AF_TMOT_CTRL_OFFSET, link, APCIE_CONFIG_BLK_AF_TMOT_CTRL_AF_TMOT_EN_UMASK);
|
||||
|
||||
// PCIe spec requires a 100 microsecond delay from REFCLK starting
|
||||
// to PERST being deasserted
|
||||
spin(100);
|
||||
|
||||
// 5) De-assert PERST# for the target PCIE link.
|
||||
gpio_configure(config->perst_gpio, GPIO_CFG_OUT_1);
|
||||
|
||||
// Limit link speed to Gen1
|
||||
apcie_config_read_raw(&link_control2, PCIE_RC_CAP_LINK_CONTROL2_OFFSET(link), sizeof(link_control2));
|
||||
link_control2 &= ~PCIE_RC_CAP_LINK_CONTROL2_PCIE_TARGET_LINK_SPEED_UMASK;
|
||||
link_control2 |= 1;
|
||||
apcie_config_write_raw(&link_control2, PCIE_RC_CAP_LINK_CONTROL2_OFFSET(link), sizeof(link_control2));
|
||||
|
||||
// Limit link width if requested by the platform. If the platform returns 0,
|
||||
// let the hardware autonegotiate the width using its default parameters
|
||||
force_width = platform_get_pcie_link_width(link);
|
||||
if (force_width != 0) {
|
||||
ASSERT(force_width <= 2);
|
||||
|
||||
uint32_t gen2_ctrl;
|
||||
apcie_config_read_raw(&gen2_ctrl, PCIE_RC_PORT_LOGIC_GEN2_CTRL_OFFSET(link), sizeof(gen2_ctrl));
|
||||
gen2_ctrl &= ~PCIE_RC_PORT_LOGIC_GEN2_CTRL_NUM_OF_LANES_UMASK;
|
||||
gen2_ctrl |= (force_width << PCIE_RC_PORT_LOGIC_GEN2_CTRL_NUM_OF_LANES_SHIFT);
|
||||
apcie_config_write_raw(&gen2_ctrl, PCIE_RC_PORT_LOGIC_GEN2_CTRL_OFFSET(link), sizeof(gen2_ctrl));
|
||||
|
||||
uint32_t port_link_ctrl;
|
||||
apcie_config_read_raw(&port_link_ctrl, PCIE_RC_PORT_LOGIC_PORT_LINK_CTRL_OFFSET(link), sizeof(port_link_ctrl));
|
||||
port_link_ctrl &= ~PCIE_RC_PORT_LOGIC_PORT_LINK_CTRL_LINK_CAPABLE_UMASK;
|
||||
port_link_ctrl |= ((1 << (force_width - 1)) << PCIE_RC_PORT_LOGIC_PORT_LINK_CTRL_LINK_CAPABLE_SHIFT);
|
||||
apcie_config_write_raw(&port_link_ctrl, PCIE_RC_PORT_LOGIC_PORT_LINK_CTRL_OFFSET(link), sizeof(port_link_ctrl));
|
||||
}
|
||||
|
||||
// Update L1 substate capabilites register to indicate the root complex
|
||||
// has the capability of supporting T_POWER_ON=0us.
|
||||
apcie_config_read_raw(&l1sub_cap, PCIE_RC_PORT_LOGIC_L1SUB_CAPABILITY_REG_OFFSET(link), sizeof(l1sub_cap));
|
||||
l1sub_cap &= ~PCIE_RC_PORT_LOGIC_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_UMASK;
|
||||
l1sub_cap &= ~PCIE_RC_PORT_LOGIC_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_UMASK;
|
||||
apcie_config_write_raw(&l1sub_cap, PCIE_RC_PORT_LOGIC_L1SUB_CAPABILITY_REG_OFFSET(link), sizeof(l1sub_cap));
|
||||
|
||||
// Clear the link counters
|
||||
counter_command = get_reg(APCIE_PORT_COUNTER_BASE_ADDR(link), APCIE_LCOUNT_BLK_LCOUNT_COMMAND_0_OFFSET);
|
||||
counter_command |= APCIE_COUNTER_CLEAR | APCIE_COUNTER_ENABLE;
|
||||
set_reg(APCIE_PORT_COUNTER_BASE_ADDR(link), APCIE_LCOUNT_BLK_LCOUNT_COMMAND_0_OFFSET, counter_command);
|
||||
|
||||
// Disable PHY powergating: <rdar://problem/20630305> H9: PCIe Sequence with Disable PHY power gating and disable txboost
|
||||
uint32_t lane_cfg = platform_get_apcie_lane_cfg();
|
||||
uint32_t phy_sig_mask;
|
||||
|
||||
uint32_t link_widths[][4] = {
|
||||
[APCIE_LANE_CFG_X1_X1_X1_X1] = { 1, 1, 1, 1 },
|
||||
[APCIE_LANE_CFG_X2_X1_X1] = { 2, 0, 1, 1 },
|
||||
[APCIE_LANE_CFG_X1_X1_X2] = { 1, 1, 2, 0 },
|
||||
[APCIE_LANE_CFG_X2_X2] = { 2, 0, 2, 0 },
|
||||
};
|
||||
|
||||
ASSERT(lane_cfg < ARRAY_SIZE(link_widths));
|
||||
ASSERT(link < ARRAY_SIZE(link_widths[0]));
|
||||
|
||||
uint32_t link_width = link_widths[lane_cfg][link];
|
||||
ASSERT(link_width != 0);
|
||||
|
||||
phy_sig_mask = ((1 << link_width) - 1) << link;
|
||||
|
||||
// Wait for the phy lanes to power up.
|
||||
while ((PHY_GET_REG(PCIE_PHY_SIG) & phy_sig_mask) != phy_sig_mask) {
|
||||
spin(10);
|
||||
}
|
||||
|
||||
#if APPLICATION_SECUREROM
|
||||
|
||||
// 6) Always enable DFW adapatation for SecureROM.
|
||||
|
||||
// For each lane...
|
||||
for (uint32_t lane = 0; phy_sig_mask != 0; lane++, phy_sig_mask >>= 1) {
|
||||
// ... if we're enabling this lane ...
|
||||
if (phy_sig_mask & 1) {
|
||||
// ... set DFE adapation to always enabled.
|
||||
OR_PMA_RX_REG(RX_REE_GEN_CTRL_EN, lane, PMA_RX_LANE_REGISTERS_BLK_RX_REE_GEN_CTRL_EN_15_UMASK);
|
||||
OR_PMA_RX_REG(RX_REE_FREE0_CFGD, lane, PMA_RX_LANE_REGISTERS_BLK_RX_REE_FREE0_CFGD_6_UMASK);
|
||||
OR_PMA_TX_REG(XCVR_DIAG_DCYA, lane, PMA_TX_LANE_REGISTERS_BLK_XCVR_DIAG_DCYA_0_UMASK);
|
||||
}
|
||||
}
|
||||
|
||||
#else // !APPLICATION_SECUREROM
|
||||
|
||||
// 5) Disable PCIE PHY common block power gating.
|
||||
|
||||
// Disable PCIE PHY power gating.
|
||||
OR_PMA_CMN_REG(CMN_CDIAG_FUNC_PWR_CTRL, PMA_CMN_REGISTERS_BLK_CMN_CDIAG_FUNC_PWR_CTRL_14_UMASK);
|
||||
OR_PMA_CMN_REG(CMN_CDIAG_XCTRL_PWR_CTRL, PMA_CMN_REGISTERS_BLK_CMN_CDIAG_XCTRL_PWR_CTRL_14_UMASK);
|
||||
|
||||
// Update common PHY PLL timers.
|
||||
uint32_t phy_reg;
|
||||
phy_reg = GET_PMA_CMN_REG(CMN_SSM_PLLPRE_TMR);
|
||||
phy_reg &= ~PMA_CMN_REGISTERS_BLK_CMN_SSM_PLLPRE_TMR_11_0_UMASK;
|
||||
phy_reg |= PMA_CMN_REGISTERS_BLK_CMN_SSM_PLLPRE_TMR_11_0_INSRT(0x64);
|
||||
SET_PMA_CMN_REG(CMN_SSM_PLLPRE_TMR, phy_reg);
|
||||
phy_reg = GET_PMA_CMN_REG(CMN_SSM_PLLLOCK_TMR);
|
||||
phy_reg &= ~PMA_CMN_REGISTERS_BLK_CMN_SSM_PLLLOCK_TMR_11_0_UMASK;
|
||||
phy_reg |= PMA_CMN_REGISTERS_BLK_CMN_SSM_PLLLOCK_TMR_11_0_INSRT(0x19);
|
||||
SET_PMA_CMN_REG(CMN_SSM_PLLLOCK_TMR, phy_reg);
|
||||
|
||||
// For each lane...
|
||||
for (uint32_t lane = 0; phy_sig_mask != 0; lane++, phy_sig_mask >>= 1) {
|
||||
// ... if we're enabling this lane ...
|
||||
if (phy_sig_mask & 1) {
|
||||
// ... disable power gating ...
|
||||
OR_PMA_TX_REG(XCVR_DIAG_FUNC_PWR_CTRL, lane, PMA_TX_LANE_REGISTERS_BLK_XCVR_DIAG_FUNC_PWR_CTRL_14_UMASK);
|
||||
|
||||
// ... and disable transmitter boost ...
|
||||
SET_PMA_TX_REG(TX_DIAG_TX_BOOST, lane, 0);
|
||||
|
||||
// ... and update the lane calibration timer ...
|
||||
phy_reg = GET_PMA_TX_REG(XCVR_PSM_LANECAL_TMR, lane);
|
||||
phy_reg &= ~PMA_TX_LANE_REGISTERS_BLK_XCVR_PSM_LANECAL_TMR_11_0_UMASK;
|
||||
phy_reg |= PMA_TX_LANE_REGISTERS_BLK_XCVR_PSM_LANECAL_TMR_11_0_INSRT(0x600);
|
||||
SET_PMA_TX_REG(XCVR_PSM_LANECAL_TMR, lane, phy_reg);
|
||||
|
||||
// ... and improve SIG DET performance ...
|
||||
SET_PMA_RX_REG(RX_DIAG_SIGDET_TUNE, lane, 0x3105);
|
||||
|
||||
// ... and improve PI stability ...
|
||||
phy_reg = GET_PMA_RX_REG(RX_DIAG_ILL_IQE_TRIM3, lane);
|
||||
phy_reg &= ~PMA_RX_LANE_REGISTERS_BLK_RX_DIAG_ILL_IQE_TRIM3_7_0_UMASK;
|
||||
phy_reg |= PMA_RX_LANE_REGISTERS_BLK_RX_DIAG_ILL_IQE_TRIM3_7_0_INSRT(0x9f);
|
||||
SET_PMA_RX_REG(RX_DIAG_ILL_IQE_TRIM3, lane, phy_reg);
|
||||
|
||||
phy_reg = GET_PMA_RX_REG(RX_DIAG_ILL_IQE_TRIM5, lane);
|
||||
phy_reg &= ~PMA_RX_LANE_REGISTERS_BLK_RX_DIAG_ILL_IQE_TRIM5_7_0_UMASK;
|
||||
phy_reg |= PMA_RX_LANE_REGISTERS_BLK_RX_DIAG_ILL_IQE_TRIM5_7_0_INSRT(0x01);
|
||||
SET_PMA_RX_REG(RX_DIAG_ILL_IQE_TRIM5, lane, phy_reg);
|
||||
|
||||
// ... and improve CDR performace.
|
||||
phy_reg = GET_PMA_RX_REG(RX_CDRLF_CNFG, lane);
|
||||
phy_reg &= ~PMA_RX_LANE_REGISTERS_BLK_RX_CDRLF_CNFG_4_0_UMASK;
|
||||
phy_reg |= PMA_RX_LANE_REGISTERS_BLK_RX_CDRLF_CNFG_4_0_INSRT(0xa);
|
||||
SET_PMA_RX_REG(RX_CDRLF_CNFG, lane, phy_reg);
|
||||
|
||||
// NOTE: Because iBoot always forces links to Gen1 speed,
|
||||
// the steps for non-Gen1 speeds have been omitted.
|
||||
}
|
||||
}
|
||||
#endif // APPLICATION_SECUREROM
|
||||
|
||||
// 7) Software sets LINKCFG.ltssm_en to start link training
|
||||
OR_APCIE_CONFIG_REG(APCIE_CONFIG_BLK_LINKCFG_OFFSET, link, APCIE_CONFIG_BLK_LINKCFG_LTSSM_EN_UMASK);
|
||||
|
||||
start = system_time();
|
||||
while ((GET_APCIE_CONFIG_REG(APCIE_CONFIG_BLK_LINKSTS_OFFSET, link) & APCIE_CONFIG_BLK_LINKSTS_LINK_STATUS_UMASK) == 0) {
|
||||
if (time_has_elapsed(start, APCIE_ENABLE_TIMEOUT)) {
|
||||
uint32_t linksts = GET_APCIE_CONFIG_REG(APCIE_CONFIG_BLK_LINKSTS_OFFSET, link);
|
||||
dprintf(DEBUG_CRITICAL, "apcie: Timeout waiting for LinkUp on link %u\n", link);
|
||||
dprintf(DEBUG_CRITICAL, "apcie: LINKSTS 0x%08x (LTSSM state %d)\n",
|
||||
linksts, APCIE_CONFIG_BLK_LINKSTS_LTSSM_STATE_XTRCT(linksts));
|
||||
goto cleanup;
|
||||
}
|
||||
spin(10);
|
||||
}
|
||||
|
||||
status->enabled = true;
|
||||
link_enable_count++;
|
||||
|
||||
dart_init(config->dart_id);
|
||||
|
||||
apcie_setup_root_port_bridge(link, config);
|
||||
|
||||
return true;
|
||||
|
||||
cleanup:
|
||||
gpio_configure(config->perst_gpio, GPIO_CFG_OUT_0);
|
||||
spin(10);
|
||||
gpio_configure(config->perst_gpio, GPIO_CFG_DFLT);
|
||||
gpio_configure(config->clkreq_gpio, GPIO_CFG_DFLT);
|
||||
|
||||
apcie_disable_link_hardware(link);
|
||||
|
||||
if (link_enable_count == 0) {
|
||||
apcie_disable_root_complex();
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
void apcie_disable_link(uint32_t link)
|
||||
{
|
||||
struct apcie_link_config *config = &apcie_link_configs[link];
|
||||
struct apcie_link_status *status = &apcie_link_statuses[link];
|
||||
utime_t start;
|
||||
|
||||
ASSERT(link < APCIE_NUM_LINKS);
|
||||
|
||||
if (!status->enabled)
|
||||
return;
|
||||
|
||||
dprintf(DEBUG_INFO, "apcie: Disabling link %d\n", link);
|
||||
|
||||
set_reg(APCIE_PORT_COUNTER_BASE_ADDR(link), APCIE_LCOUNT_BLK_LCOUNT_COMMAND_0_OFFSET, 0);
|
||||
|
||||
// Request PMETO and clear the previous status indications
|
||||
SET_APCIE_CONFIG_REG(APCIE_CONFIG_BLK_PMETO_OFFSET, link,
|
||||
APCIE_CONFIG_BLK_PMETO_FLD_UMASK
|
||||
| APCIE_CONFIG_BLK_PMETO_PME_TO_ACK_MSG_UMASK
|
||||
| APCIE_CONFIG_BLK_PMETO_TIMEOUT_UMASK);
|
||||
start = system_time();
|
||||
while (GET_APCIE_CONFIG_REG(APCIE_CONFIG_BLK_PMETO_OFFSET, link) & APCIE_CONFIG_BLK_PMETO_FLD_UMASK) {
|
||||
if (time_has_elapsed(start, 10000)) {
|
||||
dprintf(DEBUG_CRITICAL, "apcie: timeout waiting for PME_To_Ack, continuing\n");
|
||||
break;
|
||||
}
|
||||
spin(10);
|
||||
}
|
||||
|
||||
start = system_time();
|
||||
while ((GET_APCIE_CONFIG_REG(APCIE_CONFIG_BLK_LINKSTS_OFFSET, link) & APCIE_CONFIG_BLK_LINKSTS_L2_STATE_UMASK) == 0) {
|
||||
if (time_has_elapsed(start, 10000)) {
|
||||
dprintf(DEBUG_CRITICAL, "apcie: link did not go into L2, continuing\n");
|
||||
break;
|
||||
}
|
||||
spin(10);
|
||||
}
|
||||
|
||||
gpio_configure(config->perst_gpio, GPIO_CFG_OUT_0);
|
||||
// delay to allow PERST# signal to settle before letting the pulldown hold it low
|
||||
// and to allow the endpoint to handle PERST# before removing REFCLK
|
||||
spin(25);
|
||||
gpio_configure(config->perst_gpio, GPIO_CFG_DFLT);
|
||||
gpio_configure(config->clkreq_gpio, GPIO_CFG_DFLT);
|
||||
|
||||
#if DEBUG_BUILD
|
||||
dart_assert_unmapped(config->dart_id);
|
||||
#endif
|
||||
|
||||
apcie_disable_link_hardware(link);
|
||||
|
||||
status->enabled = false;
|
||||
link_enable_count--;
|
||||
|
||||
if (link_enable_count == 0) {
|
||||
apcie_disable_root_complex();
|
||||
}
|
||||
|
||||
apcie_free_port_bridge(link);
|
||||
}
|
||||
|
||||
uint32_t apcie_get_link_enable_count(void)
|
||||
{
|
||||
return link_enable_count;
|
||||
}
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
void apcie_update_devicetree(DTNode *apcie_node)
|
||||
{
|
||||
DTNode *node;
|
||||
uint32_t propSize;
|
||||
uint8_t *dt_prop = (uint8_t *)malloc(MAX_DT_PROPERTY_SIZE);
|
||||
uint8_t *next_dt_prop = dt_prop;
|
||||
char bridge[16];
|
||||
|
||||
// Apply common tunables.
|
||||
bzero(dt_prop, MAX_DT_PROPERTY_SIZE);
|
||||
next_dt_prop = dt_prop;
|
||||
next_dt_prop = platform_apply_dt_tunables(tunables_pcie_common,
|
||||
ARRAY_SIZE(tunables_pcie_common),
|
||||
next_dt_prop,
|
||||
0, // Already at the correct offset
|
||||
"apcie common");
|
||||
|
||||
next_dt_prop = platform_apply_dt_tunables(tunables_nvme_common ,
|
||||
ARRAY_SIZE(tunables_nvme_common ),
|
||||
next_dt_prop,
|
||||
0, // Already at the correct offset
|
||||
"apcie common");
|
||||
|
||||
propSize = next_dt_prop - dt_prop;
|
||||
RELEASE_ASSERT(propSize < MAX_DT_PROPERTY_SIZE);
|
||||
dt_set_prop(apcie_node, "apcie-common-tunables", dt_prop, propSize);
|
||||
|
||||
// Apply port-specific config tunables.
|
||||
for (uint32_t i = 0; i < APCIE_NUM_LINKS; i++) {
|
||||
snprintf(bridge, sizeof(bridge), "pci-bridge%d", i);
|
||||
if (dt_find_node(apcie_node, bridge, &node)) {
|
||||
// APCIe port config tunables.
|
||||
bzero(dt_prop, MAX_DT_PROPERTY_SIZE);
|
||||
next_dt_prop = dt_prop;
|
||||
next_dt_prop = platform_apply_dt_tunables(tunables_pcie_config_ports[i].tunable_chip,
|
||||
tunables_pcie_config_ports[i].num_tunable_chips,
|
||||
next_dt_prop,
|
||||
tunables_pcie_config_ports[i].dt_base,
|
||||
bridge);
|
||||
propSize = next_dt_prop - dt_prop;
|
||||
RELEASE_ASSERT(propSize < MAX_DT_PROPERTY_SIZE);
|
||||
dt_set_prop(node, "apcie-config-tunables", dt_prop, propSize);
|
||||
|
||||
// PCIe root complex config tunables.
|
||||
snprintf(bridge, sizeof(bridge), "pcie-rc%d", i);
|
||||
bzero(dt_prop, MAX_DT_PROPERTY_SIZE);
|
||||
next_dt_prop = dt_prop;
|
||||
next_dt_prop = platform_apply_dt_tunables(tunables_pcie_config_rc[i].tunable_chip,
|
||||
tunables_pcie_config_rc[i].num_tunable_chips,
|
||||
next_dt_prop,
|
||||
tunables_pcie_config_rc[i].dt_base,
|
||||
bridge);
|
||||
propSize = next_dt_prop - dt_prop;
|
||||
RELEASE_ASSERT(propSize < MAX_DT_PROPERTY_SIZE);
|
||||
dt_set_prop(node, "pcie-rc-tunables", dt_prop, propSize);
|
||||
} else {
|
||||
dprintf(DEBUG_INFO,"PCIe bridge node %s not found -- skipping tunable update\n", bridge);
|
||||
}
|
||||
}
|
||||
|
||||
// Apply SPDS PHY tunables.
|
||||
bzero(dt_prop, MAX_DT_PROPERTY_SIZE);
|
||||
next_dt_prop = dt_prop;
|
||||
next_dt_prop = platform_apply_dt_tunables(tunables_pcie_phy,
|
||||
ARRAY_SIZE(tunables_pcie_phy),
|
||||
next_dt_prop,
|
||||
APCIE_PHY_BASE_ADDR,
|
||||
"PCIe PHY");
|
||||
|
||||
propSize = next_dt_prop - dt_prop;
|
||||
RELEASE_ASSERT(propSize < MAX_DT_PROPERTY_SIZE);
|
||||
|
||||
dt_set_prop(apcie_node, "phy-params", dt_prop, propSize);
|
||||
free(dt_prop);
|
||||
dt_prop = next_dt_prop = NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
struct apcie_link_config platform_apcie_link_configs[APCIE_NUM_LINKS] = {
|
||||
[0] = {
|
||||
.perst_gpio = GPIO_PCIE0_PERST,
|
||||
.clkreq_gpio = GPIO_PCIE0_CLKREQ,
|
||||
.dart_id = PCIE_PORT0_DART_ID,
|
||||
},
|
||||
[1] = {
|
||||
.perst_gpio = GPIO_PCIE1_PERST,
|
||||
.clkreq_gpio = GPIO_PCIE1_CLKREQ,
|
||||
.dart_id = PCIE_PORT1_DART_ID,
|
||||
},
|
||||
[2] = {
|
||||
.perst_gpio = GPIO_PCIE2_PERST,
|
||||
.clkreq_gpio = GPIO_PCIE2_CLKREQ,
|
||||
.dart_id = PCIE_PORT2_DART_ID,
|
||||
},
|
||||
[3] = {
|
||||
.perst_gpio = GPIO_PCIE3_PERST,
|
||||
.clkreq_gpio = GPIO_PCIE3_CLKREQ,
|
||||
.dart_id = PCIE_PORT3_DART_ID,
|
||||
},
|
||||
};
|
||||
|
||||
void platform_register_pci_busses(void)
|
||||
{
|
||||
apcie_init();
|
||||
}
|
||||
|
||||
uint64_t platform_map_host_to_pci_addr(uintptr_t addr)
|
||||
{
|
||||
// Right now we're only supporting 32-bit PCI addresses
|
||||
// for aPCIe, so just lop off the top 32 bits
|
||||
return addr & 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
uintptr_t platform_map_pci_to_host_addr(uint64_t addr)
|
||||
{
|
||||
// Right now we're only supporting 32-bit PCI addresses
|
||||
// for aPCIe
|
||||
ASSERT((addr & ~0xFFFFFFFFULL) == 0);
|
||||
return PCI_32BIT_BASE + (addr & (PCI_32BIT_LEN - 1));
|
||||
}
|
||||
@@ -0,0 +1,13 @@
|
||||
# Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Computer, Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Computer, Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/apcie.o \
|
||||
@@ -0,0 +1,54 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <platform/memmap.h>
|
||||
|
||||
.text
|
||||
.balign 4
|
||||
.globl _platform_start
|
||||
_platform_start:
|
||||
////////////////////////////////////////////////
|
||||
// Must preserve X0 and X1
|
||||
////////////////////////////////////////////////
|
||||
|
||||
#if !APPLICATION_SECUREROM
|
||||
// Enable the L2 cache load/store prefetcher.
|
||||
mrs x2, s3_0_c15_c5_0 // HID5
|
||||
and x2, x2, #~(3<<44) // Enable L2C load (bit 44)/store (bit 45) prefetch
|
||||
msr s3_0_c15_c5_0, x2 // HID5
|
||||
isb
|
||||
#endif
|
||||
|
||||
#if WITH_L2_AS_RAM
|
||||
#if APPLICATION_SECUREROM
|
||||
// Enable L2 as RAM
|
||||
mrs x2, s3_3_c15_c7_0 // L2_CRAMCONFIG
|
||||
orr x2, x2, #2 // L2_CRAMCONFIG.EnableSize (2 MiB SRAM)
|
||||
msr s3_3_c15_c7_0, x2 // L2_CRAMCONFIG
|
||||
1:
|
||||
// Poll for RAM ready
|
||||
mrs x2, s3_3_c15_c7_0 // L2_CRAMCONFIG
|
||||
and x2, x2, #(1<<63) // L2_CRAMCONFIG.Ready
|
||||
cbz x2, 1b // Not ready
|
||||
#endif
|
||||
#if PRODUCT_IBOOT || PRODUCT_IBEC
|
||||
// Disable L2 as RAM
|
||||
mrs x2, s3_3_c15_c7_0 // L2_CRAMCONFIG
|
||||
and x2, x2, #~0x3F // L2_CRAMCONFIG.EnableSize (disable SRAM)
|
||||
msr s3_3_c15_c7_0, x2 // L2_CRAMCONFIG
|
||||
1:
|
||||
// Poll for RAM not ready
|
||||
mrs x2, s3_3_c15_c7_0 // L2_CRAMCONFIG
|
||||
and x2, x2, #(1<<63) // L2_CRAMCONFIG.Ready
|
||||
cbnz x2, 1b // Still ready
|
||||
#endif
|
||||
#endif
|
||||
ret
|
||||
|
||||
@@ -0,0 +1,520 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
|
||||
#define MINIMUM_FUSE_REVISION 0x0
|
||||
|
||||
#define CHIPID_VOLTAGE_FIXED 0
|
||||
#define CHIPID_MODE_NONE 0
|
||||
|
||||
struct chipid_voltage_config {
|
||||
uint32_t safe_voltage;
|
||||
uint32_t mode;
|
||||
};
|
||||
|
||||
static struct chipid_voltage_config chipid_cpu_voltages[] = {
|
||||
[CHIPID_CPU_VOLTAGE_BYPASS] = { 610, CHIPID_MODE_NONE},
|
||||
[CHIPID_CPU_VOLTAGE_SECUREROM] = { 610, CHIPID_MODE_NONE},
|
||||
[CHIPID_CPU_VOLTAGE_396] = { 610, CHIPID_MODE_NONE},
|
||||
};
|
||||
|
||||
static struct chipid_voltage_config chipid_cpu_sram_voltages[] = {
|
||||
[CHIPID_CPU_VOLTAGE_BYPASS] = { 800, CHIPID_MODE_NONE},
|
||||
[CHIPID_CPU_VOLTAGE_SECUREROM] = { 800, CHIPID_MODE_NONE},
|
||||
[CHIPID_CPU_VOLTAGE_396] = { 800, CHIPID_MODE_NONE},
|
||||
};
|
||||
|
||||
static struct chipid_voltage_config chipid_soc_voltages[] = {
|
||||
[CHIPID_SOC_VOLTAGE_BYPASS] = {725, CHIPID_MODE_NONE},
|
||||
[CHIPID_SOC_VOLTAGE_SECUREROM] = {725, CHIPID_MODE_NONE},
|
||||
[CHIPID_SOC_VOLTAGE_VMIN] = {725, CHIPID_MODE_NONE},
|
||||
[CHIPID_SOC_VOLTAGE_VNOM] = {825, CHIPID_MODE_NONE},
|
||||
};
|
||||
|
||||
static struct chipid_voltage_config chipid_gpu_voltages[] = {
|
||||
[CHIPID_GPU_VOLTAGE_OFF] = { 0, CHIPID_MODE_NONE},
|
||||
};
|
||||
|
||||
static struct chipid_voltage_config chipid_gpu_sram_voltages[] = {
|
||||
[CHIPID_GPU_VOLTAGE_OFF] = { 0, CHIPID_MODE_NONE},
|
||||
};
|
||||
|
||||
static struct chipid_voltage_config chipid_sram_voltages[] = {
|
||||
[CHIPID_VOLTAGE_FIXED] = {850, CHIPID_MODE_NONE},
|
||||
};
|
||||
|
||||
struct chipid_voltadj_entry {
|
||||
uint64_t voltage_index:8;
|
||||
uint64_t chipid:32;
|
||||
uint64_t chip_rev_min:8;
|
||||
uint64_t fuse_rev_min:8;
|
||||
struct chipid_vol_adj voltages;
|
||||
};
|
||||
|
||||
#define CHIPID_ALL 0x0
|
||||
|
||||
// .voltages = {volAdj0, volAdj1, volAdj2, volAdj3, dvfmMaxAdj, dvmrAdj0, dvmrAdj1, dvmrAdj2}
|
||||
|
||||
static const struct chipid_voltadj_entry chipid_voltadj_entry[] = {
|
||||
{CHIPID_CPU_VOLTAGE_BYPASS, CHIPID_ALL, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 0, 0, 0, 0}},
|
||||
{CHIPID_SOC_VOLTAGE_SECUREROM, CHIPID_ALL, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 0, 0, 0, 0}},
|
||||
{CHIPID_CPU_VOLTAGE_396, 0x8010, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 0, 0, 0, 0}},
|
||||
};
|
||||
|
||||
const struct chipid_vol_adj *chipid_get_vol_adj(enum chipid_voltage_index voltage_index)
|
||||
{
|
||||
uint32_t chipid = chipid_get_chip_id();
|
||||
uint32_t chip_rev = chipid_get_chip_revision();
|
||||
uint32_t fuse_rev = chipid_get_fuse_revision();
|
||||
|
||||
for (size_t i = 0; i < sizeof(chipid_voltadj_entry)/sizeof(chipid_voltadj_entry[0]); i++) {
|
||||
if (voltage_index != chipid_voltadj_entry[i].voltage_index) {
|
||||
continue;
|
||||
}
|
||||
if ((chipid != chipid_voltadj_entry[i].chipid) && (chipid_voltadj_entry[i].chipid != CHIPID_ALL)) {
|
||||
continue;
|
||||
}
|
||||
if ((chip_rev < chipid_voltadj_entry[i].chip_rev_min)) {
|
||||
continue;
|
||||
}
|
||||
if ((fuse_rev < chipid_voltadj_entry[i].fuse_rev_min)) {
|
||||
continue;
|
||||
}
|
||||
return &chipid_voltadj_entry[i].voltages;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static uint32_t chipid_get_base_voltage(void)
|
||||
{
|
||||
uint32_t voltage = 0;
|
||||
|
||||
// TODO
|
||||
|
||||
return voltage;
|
||||
}
|
||||
|
||||
static uint32_t chipid_get_cpu_binfuse_for_mode(uint32_t mode)
|
||||
{
|
||||
uint32_t binfuse = 0;
|
||||
|
||||
// TODO
|
||||
|
||||
return binfuse;
|
||||
}
|
||||
|
||||
static uint32_t chipid_get_cpu_sram_binfuse_for_mode(uint32_t mode)
|
||||
{
|
||||
uint32_t binfuse = 0;
|
||||
|
||||
// TODO
|
||||
|
||||
return binfuse;
|
||||
}
|
||||
|
||||
static uint32_t chipid_get_soc_binfuse_for_mode(uint32_t mode)
|
||||
{
|
||||
uint32_t binfuse = 0;
|
||||
|
||||
// TODO
|
||||
|
||||
return binfuse;
|
||||
}
|
||||
|
||||
static uint32_t chipid_get_gpu_binfuse_for_mode(uint32_t mode)
|
||||
{
|
||||
uint32_t binfuse = 0;
|
||||
|
||||
// TODO
|
||||
|
||||
return binfuse;
|
||||
}
|
||||
|
||||
static uint32_t chipid_get_gpu_sram_binfuse_for_mode(uint32_t mode)
|
||||
{
|
||||
uint32_t binfuse = 0;
|
||||
|
||||
// TODO
|
||||
|
||||
return binfuse;
|
||||
}
|
||||
|
||||
static uint32_t chipid_get_sram_binfuse_for_mode(uint32_t mode)
|
||||
{
|
||||
uint32_t binfuse = 0;
|
||||
|
||||
// TODO
|
||||
|
||||
return binfuse;
|
||||
}
|
||||
|
||||
static uint32_t chipid_get_cpu_bin_voltage(uint32_t volt_index)
|
||||
{
|
||||
uint32_t mode, binfuse;
|
||||
|
||||
mode = chipid_cpu_voltages[volt_index].mode;
|
||||
|
||||
// Return safe voltage if no binned voltage
|
||||
if (mode == CHIPID_MODE_NONE)
|
||||
return chipid_cpu_voltages[volt_index].safe_voltage;
|
||||
|
||||
binfuse = chipid_get_cpu_binfuse_for_mode(mode);
|
||||
|
||||
return (chipid_get_base_voltage() + binfuse * 5);
|
||||
}
|
||||
|
||||
static uint32_t chipid_get_cpu_sram_bin_voltage(uint32_t volt_index)
|
||||
{
|
||||
uint32_t mode, binfuse;
|
||||
|
||||
mode = chipid_cpu_sram_voltages[volt_index].mode;
|
||||
|
||||
// Return safe voltage if no binned voltage
|
||||
if (mode == CHIPID_MODE_NONE)
|
||||
return chipid_cpu_sram_voltages[volt_index].safe_voltage;
|
||||
|
||||
binfuse = chipid_get_cpu_sram_binfuse_for_mode(mode);
|
||||
|
||||
return (chipid_get_base_voltage() + binfuse * 5);
|
||||
}
|
||||
|
||||
static uint32_t chipid_get_soc_bin_voltage(uint32_t volt_index)
|
||||
{
|
||||
uint32_t mode, binfuse;
|
||||
|
||||
mode = chipid_soc_voltages[volt_index].mode;
|
||||
|
||||
// Return safe voltage if no binned voltage
|
||||
if (mode == CHIPID_MODE_NONE)
|
||||
return chipid_soc_voltages[volt_index].safe_voltage;
|
||||
|
||||
binfuse = chipid_get_soc_binfuse_for_mode(mode);
|
||||
|
||||
return (chipid_get_base_voltage() + binfuse * 5);
|
||||
}
|
||||
|
||||
static uint32_t chipid_get_gpu_bin_voltage(uint32_t volt_index)
|
||||
{
|
||||
uint32_t mode, binfuse;
|
||||
|
||||
mode = chipid_gpu_voltages[volt_index].mode;
|
||||
|
||||
// Return safe voltage if no binned voltage
|
||||
if (mode == CHIPID_MODE_NONE)
|
||||
return chipid_gpu_voltages[volt_index].safe_voltage;
|
||||
|
||||
binfuse = chipid_get_gpu_binfuse_for_mode(mode);
|
||||
|
||||
return (chipid_get_base_voltage() + binfuse * 5);
|
||||
}
|
||||
|
||||
static uint32_t chipid_get_gpu_sram_bin_voltage(uint32_t volt_index)
|
||||
{
|
||||
uint32_t mode, binfuse;
|
||||
|
||||
mode = chipid_gpu_sram_voltages[volt_index].mode;
|
||||
|
||||
// Return safe voltage if no binned voltage
|
||||
if (mode == CHIPID_MODE_NONE)
|
||||
return chipid_gpu_sram_voltages[volt_index].safe_voltage;
|
||||
|
||||
binfuse = chipid_get_gpu_sram_binfuse_for_mode(mode);
|
||||
|
||||
return (chipid_get_base_voltage() + binfuse * 5);
|
||||
}
|
||||
|
||||
static uint32_t chipid_get_sram_bin_voltage(uint32_t volt_index)
|
||||
{
|
||||
uint32_t mode, binfuse;
|
||||
|
||||
mode = chipid_sram_voltages[volt_index].mode;
|
||||
|
||||
// Return safe voltage if no binned voltage
|
||||
if (mode == CHIPID_MODE_NONE)
|
||||
return chipid_sram_voltages[volt_index].safe_voltage;
|
||||
|
||||
binfuse = chipid_get_sram_binfuse_for_mode(mode);
|
||||
|
||||
return (chipid_get_base_voltage() + binfuse * 5);
|
||||
}
|
||||
|
||||
bool chipid_get_current_production_mode(void)
|
||||
{
|
||||
return MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_XTRCT(rCFG_FUSE0) != 0;
|
||||
}
|
||||
|
||||
bool chipid_get_raw_production_mode(void)
|
||||
{
|
||||
return MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_XTRCT(rCFG_FUSE0_RAW) != 0;
|
||||
}
|
||||
|
||||
void chipid_clear_production_mode(void)
|
||||
{
|
||||
rCFG_FUSE0 &= ~MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_UMASK;
|
||||
}
|
||||
|
||||
bool chipid_get_secure_mode(void)
|
||||
{
|
||||
// demotion only applies to the SEP, so iBoot always reads
|
||||
// the raw value for secure mode (<rdar://problem/15182573>)
|
||||
return MINIPMGR_FUSE_CFG_FUSE0_SECURE_MODE_XTRCT(rCFG_FUSE0_RAW);
|
||||
}
|
||||
|
||||
uint32_t chipid_get_security_domain(void)
|
||||
{
|
||||
return MINIPMGR_FUSE_CFG_FUSE0_SECURITY_DOMAIN_XTRCT(rCFG_FUSE0);
|
||||
}
|
||||
|
||||
uint32_t chipid_get_board_id(void)
|
||||
{
|
||||
return MINIPMGR_FUSE_CFG_FUSE0_BID_XTRCT(rCFG_FUSE0);
|
||||
}
|
||||
|
||||
uint32_t chipid_get_minimum_epoch(void)
|
||||
{
|
||||
return MINIPMGR_FUSE_CFG_FUSE0_MINIMUM_EPOCH_XTRCT(rCFG_FUSE0);
|
||||
}
|
||||
|
||||
uint32_t chipid_get_chip_id(void)
|
||||
{
|
||||
#if SUB_PLATFORM_T8010
|
||||
return 0x8010;
|
||||
#else
|
||||
#error "Unknown platform"
|
||||
#endif
|
||||
}
|
||||
|
||||
uint32_t chipid_get_chip_revision(void)
|
||||
{
|
||||
uint32_t fuse_val = rCFG_FUSE4;
|
||||
|
||||
return (MINIPMGR_FUSE_CFG_FUSE4_CHIP_REV_MAJOR_XTRCT(fuse_val) << 4) |
|
||||
(MINIPMGR_FUSE_CFG_FUSE4_CHIP_REV_MINOR_XTRCT(fuse_val));
|
||||
}
|
||||
|
||||
uint32_t chipid_get_osc_frequency(void)
|
||||
{
|
||||
return OSC_FREQ;
|
||||
}
|
||||
|
||||
uint64_t chipid_get_ecid_id(void)
|
||||
{
|
||||
return ((uint64_t)rECIDHI << 32) | rECIDLO;
|
||||
}
|
||||
|
||||
uint64_t chipid_get_die_id(void)
|
||||
{
|
||||
return ((uint64_t)rECIDHI << 32) | rECIDLO;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_cpu_voltage(uint32_t index)
|
||||
{
|
||||
uint32_t cpu_voltage;
|
||||
|
||||
if (index >= sizeof(chipid_cpu_voltages)/sizeof(chipid_cpu_voltages[0]))
|
||||
panic("Invalid CPU voltage index %d\n", index);
|
||||
|
||||
if (chipid_get_fuse_revision() < MINIMUM_FUSE_REVISION)
|
||||
cpu_voltage = chipid_cpu_voltages[index].safe_voltage;
|
||||
else
|
||||
cpu_voltage = chipid_get_cpu_bin_voltage(index);
|
||||
|
||||
return cpu_voltage;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_cpu_sram_voltage(uint32_t index)
|
||||
{
|
||||
uint32_t cpu_sram_voltage;
|
||||
|
||||
if (index >= sizeof(chipid_cpu_sram_voltages)/sizeof(chipid_cpu_sram_voltages[0]))
|
||||
panic("Invalid CPU SRAM voltage index %d\n", index);
|
||||
|
||||
if (chipid_get_fuse_revision() < MINIMUM_FUSE_REVISION)
|
||||
cpu_sram_voltage = chipid_cpu_sram_voltages[index].safe_voltage;
|
||||
else
|
||||
cpu_sram_voltage = chipid_get_cpu_sram_bin_voltage(index);
|
||||
|
||||
return cpu_sram_voltage;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_soc_voltage(uint32_t index)
|
||||
{
|
||||
uint32_t soc_voltage;
|
||||
|
||||
if (index >= sizeof(chipid_soc_voltages)/sizeof(chipid_soc_voltages[0]))
|
||||
panic("Invalid SOC voltage index %d\n", index);
|
||||
|
||||
if (chipid_get_fuse_revision() < MINIMUM_FUSE_REVISION)
|
||||
soc_voltage = chipid_soc_voltages[index].safe_voltage;
|
||||
else
|
||||
soc_voltage = chipid_get_soc_bin_voltage(index);
|
||||
|
||||
return soc_voltage;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_gpu_voltage(uint32_t index)
|
||||
{
|
||||
uint32_t gpu_voltage;
|
||||
|
||||
if (index >= sizeof(chipid_gpu_voltages)/sizeof(chipid_gpu_voltages[0]))
|
||||
panic("Invalid GPU voltage index %d\n", index);
|
||||
|
||||
if (chipid_get_fuse_revision() < MINIMUM_FUSE_REVISION)
|
||||
gpu_voltage = chipid_gpu_voltages[index].safe_voltage;
|
||||
else
|
||||
gpu_voltage = chipid_get_gpu_bin_voltage(index);
|
||||
|
||||
return gpu_voltage;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_gpu_sram_voltage(uint32_t index)
|
||||
{
|
||||
uint32_t gpu_sram_voltage;
|
||||
|
||||
if (index >= sizeof(chipid_gpu_sram_voltages)/sizeof(chipid_gpu_sram_voltages[0]))
|
||||
panic("Invalid GPU SRAM voltage index %d\n", index);
|
||||
|
||||
if (chipid_get_fuse_revision() < MINIMUM_FUSE_REVISION)
|
||||
gpu_sram_voltage = chipid_gpu_sram_voltages[index].safe_voltage;
|
||||
else
|
||||
gpu_sram_voltage = chipid_get_gpu_sram_bin_voltage(index);
|
||||
|
||||
return gpu_sram_voltage;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_sram_voltage(uint32_t index)
|
||||
{
|
||||
uint32_t sram_voltage;
|
||||
|
||||
index = CHIPID_VOLTAGE_FIXED;
|
||||
|
||||
if (index >= sizeof(chipid_sram_voltages)/sizeof(chipid_sram_voltages[0]))
|
||||
panic("Invalid SRAM voltage index %d\n", index);
|
||||
|
||||
if (chipid_get_fuse_revision() < MINIMUM_FUSE_REVISION)
|
||||
sram_voltage = chipid_sram_voltages[index].safe_voltage;
|
||||
else
|
||||
sram_voltage = chipid_get_sram_bin_voltage(index);
|
||||
|
||||
return sram_voltage;
|
||||
}
|
||||
|
||||
bool chipid_get_fuse_lock(void)
|
||||
{
|
||||
return MINIPMGR_FUSE_CFG_FUSE1_AP_LOCK_XTRCT(rCFG_FUSE1) != 0;
|
||||
}
|
||||
|
||||
void chipid_set_fuse_lock(bool locked)
|
||||
{
|
||||
if (locked) {
|
||||
rCFG_FUSE1 |= MINIPMGR_FUSE_CFG_FUSE1_AP_LOCK_INSRT(1);
|
||||
asm("dsb sy");
|
||||
if (!chipid_get_fuse_lock()) {
|
||||
panic("Failed to lock fuses\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool chipid_get_fuse_seal(void)
|
||||
{
|
||||
return MINIPMGR_FUSE_CFG_FUSE1_SEAL_FUSES_XTRCT(rCFG_FUSE1) != 0;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_lpo_trim(void)
|
||||
{
|
||||
// <rdar://problem/18460311> Workaround for Maui LPO issue
|
||||
// return MINIPMGR_FUSE_CFG_FUSE2_LPO_TRIM_XTRCT(rCFG_FUSE2);
|
||||
return 0x20;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_pcie_refpll_fcal_vco_digctrl(void)
|
||||
{
|
||||
return MINIPMGR_FUSE_CFG_FUSE4_PCIE_REFPLL_FCAL_VCO_DIGCTRL_XTRCT(rCFG_FUSE4);
|
||||
}
|
||||
|
||||
uint32_t chipid_get_soc_temp_sensor_trim(uint32_t sensor_index)
|
||||
{
|
||||
uint32_t sensor_trim;
|
||||
|
||||
switch (sensor_index) {
|
||||
case 0:
|
||||
sensor_trim = rCFG_FUSE2;
|
||||
sensor_trim &= MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_TRIMG_UMASK | MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_TRIMO_UMASK;
|
||||
sensor_trim >>= MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_TRIMG_SHIFT;
|
||||
break;
|
||||
case 1:
|
||||
sensor_trim = rCFG_FUSE2;
|
||||
sensor_trim &= MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN1_TRIMG_UMASK | MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN1_TRIMO_UMASK;
|
||||
sensor_trim >>= MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN1_TRIMG_SHIFT;
|
||||
break;
|
||||
case 2:
|
||||
sensor_trim = rCFG_FUSE3;
|
||||
sensor_trim &= MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN2_TRIMG_UMASK | MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN2_TRIMO_UMASK;
|
||||
sensor_trim >>= MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN2_TRIMG_SHIFT;
|
||||
break;
|
||||
default:
|
||||
panic("invalid thermal sensor %u", sensor_index);
|
||||
}
|
||||
return sensor_trim;
|
||||
}
|
||||
|
||||
uint32_t chipid_get_fuse_revision(void)
|
||||
{
|
||||
return MINIPMGR_FUSE_CFG_FUSE4_REV_XTRCT(rCFG_FUSE4);
|
||||
}
|
||||
|
||||
uint32_t chipid_get_total_rails_leakage()
|
||||
{
|
||||
// FIXME
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
|
||||
#define FPGA_HAS_INT3 (FPGA_HAS_MEDIA | FPGA_HAS_MSR | FPGA_HAS_JPEG | FPGA_HAS_VXD | FPGA_HAS_DISP)
|
||||
|
||||
uint32_t chipid_get_fpga_block_instantiation(void)
|
||||
{
|
||||
// Hardware blocks instantiated.
|
||||
uint32_t blocks = (rECID_FUSE3 >> 18) & 0xF;
|
||||
uint32_t mask = FPGA_HAS_ALWAYS;
|
||||
|
||||
switch (blocks) {
|
||||
// INT2 := ACC + AF + AMC + SouthBridge + PCIE
|
||||
case 0x1:
|
||||
break;
|
||||
|
||||
// INT2GFX := INT2 + GFX
|
||||
case 0x2:
|
||||
mask |= FPGA_HAS_GFX;
|
||||
break;
|
||||
|
||||
// INT3 := INT2 + DISP + MEDIA + JPEG + MSR + VXD
|
||||
case 0x8:
|
||||
mask |= FPGA_HAS_INT3;
|
||||
break;
|
||||
|
||||
// INT3GFX := INT3 + GFX
|
||||
case 0xA:
|
||||
mask |= (FPGA_HAS_INT3 | FPGA_HAS_GFX);
|
||||
break;
|
||||
|
||||
default:
|
||||
panic("Unknown hardware block instantiation: 0x%x", blocks);
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,72 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is only a database of the performance sate for CPU and GPU, regarding the kind of chip
|
||||
* or board, it has no access to the chip.
|
||||
*/
|
||||
#include <platform.h>
|
||||
#include <platform/soc/dvfmperf.h>
|
||||
|
||||
// These array are the first iteration, the next part will include reference to board id, board rev, fuse rev.
|
||||
|
||||
static const enum chipid_voltage_index t8010_cpu[] = {
|
||||
CHIPID_CPU_VOLTAGE_BYPASS,
|
||||
CHIPID_CPU_VOLTAGE_SECUREROM,
|
||||
CHIPID_CPU_VOLTAGE_396,
|
||||
};
|
||||
|
||||
static const enum chipid_voltage_index t8010_gpu[] = {
|
||||
CHIPID_GPU_VOLTAGE_OFF,
|
||||
};
|
||||
|
||||
static const struct {
|
||||
uint32_t chip_id;
|
||||
uint32_t chip_rev;
|
||||
enum chipid_voltage_type voltage_type;
|
||||
const enum chipid_voltage_index *voltage_indexes;
|
||||
uint32_t size;
|
||||
} dvfmperfs[] = { // Entry with highest chip revision must come first
|
||||
{0x8010, CHIP_REVISION_A0, CHIPID_CPU_VOLTAGE, t8010_cpu, sizeof(t8010_cpu)/sizeof(t8010_cpu[0])},
|
||||
{0x8010, CHIP_REVISION_A0, CHIPID_GPU_VOLTAGE, t8010_gpu, sizeof(t8010_gpu)/sizeof(t8010_gpu[0])},
|
||||
};
|
||||
|
||||
enum chipid_voltage_index dvfmperf_get_voltage_index(uint32_t index, enum chipid_voltage_type voltage_type)
|
||||
{
|
||||
uint32_t chip_id = chipid_get_chip_id();
|
||||
uint32_t chip_rev = chipid_get_chip_revision();
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < sizeof(dvfmperfs)/sizeof(dvfmperfs[0]); i++) {
|
||||
if (chip_id != dvfmperfs[i].chip_id) {
|
||||
continue;
|
||||
}
|
||||
if (chip_rev < dvfmperfs[i].chip_rev) {
|
||||
continue;
|
||||
}
|
||||
if (voltage_type != dvfmperfs[i].voltage_type) {
|
||||
continue;
|
||||
}
|
||||
if (index >= dvfmperfs[i].size) {
|
||||
switch (voltage_type) {
|
||||
case CHIPID_CPU_VOLTAGE:
|
||||
return dvfmperfs[i].voltage_indexes[2]; // Default to lowest frequency
|
||||
case CHIPID_GPU_VOLTAGE:
|
||||
return dvfmperfs[i].voltage_indexes[0];
|
||||
default:
|
||||
panic("Unknwon voltage type\n");
|
||||
}
|
||||
}
|
||||
return dvfmperfs[i].voltage_indexes[index];
|
||||
}
|
||||
panic("Unknown voltage for current chip\n");
|
||||
return CHIPID_GPU_VOLTAGE_OFF; // Never reach this code
|
||||
}
|
||||
@@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is only a database of the frequencies used by CPU and GPU, it has no access
|
||||
* To the chip.
|
||||
*/
|
||||
#include <platform.h>
|
||||
#include <platform/soc/operating_point.h>
|
||||
|
||||
#define CHIP_ID_ALL 0
|
||||
#define DELIMITER CHIPID_ALL_VOLTAGE_LAST
|
||||
|
||||
static const struct operating_point_params operating_point_params[] = {
|
||||
// T8010
|
||||
{.voltage_index = DELIMITER, .chip_id = 0x8010, .voltage_type = CHIPID_GPU_VOLTAGE},
|
||||
// voltage_index P M S
|
||||
{.gpu = {CHIPID_GPU_VOLTAGE_OFF, 0, 0, 0}},
|
||||
|
||||
// T8010
|
||||
{.voltage_index = DELIMITER, .chip_id = 0x8010, .voltage_type = CHIPID_CPU_VOLTAGE},
|
||||
// bypass
|
||||
// | clkSrc
|
||||
// | | fcwInt
|
||||
// | | | fcwFrac
|
||||
// | | | | pstDivS
|
||||
// | | | | | migDivS
|
||||
// | | | | | | coreTyp
|
||||
// | | | | | | | biuDiv4HiVol
|
||||
// | | | | | | | | biuDiv4LoVol
|
||||
// | | | | | | | | | dvmrMaxWgt
|
||||
// | | | | | | | | | | iexrfCfgWrData
|
||||
// | | | | | | | | | | | iexrfCfgWrIdxa
|
||||
// | | | | | | | | | | | | iexrfCfgWrIdxb
|
||||
// | | | | | | | | | | | | | exrfCfgWrIdxmuxsel
|
||||
// | | | | | | | | | | | | | |
|
||||
{.cpu = {CHIPID_CPU_VOLTAGE_BYPASS, 1, 0, 125, 0, 7, 7, kACC_CORETYP_FUSED, 2, 2, 0xf, 0, 0, 0, 0}}, // 24 MHz
|
||||
{.cpu = {CHIPID_CPU_VOLTAGE_SECUREROM,1, 1, 125, 0, 4, 7, kACC_CORETYP_FUSED, 2, 2, 0xf, 0, 0, 0, 0}}, // 300 MHz
|
||||
{.cpu = {CHIPID_CPU_VOLTAGE_396, 0, 0, 0, 0, 0, 0, kACC_CORETYP_ECORE, 2, 2, 0xf, 0, 0, 0, 0}}, // 396 MHz !!!FIXME!!! Get correct settings
|
||||
};
|
||||
|
||||
const struct operating_point_params *operating_point_get_params(enum chipid_voltage_index voltage_index, enum chipid_voltage_type voltage_type)
|
||||
{
|
||||
uint64_t chip_id = chipid_get_chip_id();
|
||||
uint64_t chip_id_in_array = 0;
|
||||
size_t size = sizeof(operating_point_params)/sizeof(operating_point_params[0]);
|
||||
enum chipid_voltage_type voltage_type_in_array = CHIPID_CPU_VOLTAGE;
|
||||
|
||||
size_t found = size;
|
||||
for (size_t i = 0; i < size; i++) {
|
||||
if (operating_point_params[i].voltage_index == DELIMITER) {
|
||||
chip_id_in_array = operating_point_params[i].chip_id;
|
||||
voltage_type_in_array = operating_point_params[i].voltage_type;
|
||||
continue;
|
||||
}
|
||||
if ((voltage_type_in_array != voltage_type)) {
|
||||
continue;
|
||||
}
|
||||
if ((operating_point_params[i].voltage_index == voltage_index) && ((chip_id_in_array == CHIP_ID_ALL) || (chip_id_in_array == chip_id))) {
|
||||
found = i;
|
||||
}
|
||||
}
|
||||
if (found == size) {
|
||||
panic("%s Index %d not found for chipId 0x%llx\n",
|
||||
__func__, voltage_index, chip_id);
|
||||
}
|
||||
return &operating_point_params[found];
|
||||
}
|
||||
@@ -0,0 +1,18 @@
|
||||
# Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_PLATFORM_CHIPID=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/chipid.o \
|
||||
$(LOCAL_DIR)/operating_point.o \
|
||||
$(LOCAL_DIR)/dvfmperf.o
|
||||
@@ -0,0 +1,117 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/dcs/dcs.h>
|
||||
#include <drivers/dcs/dcs_regs.h>
|
||||
#include <drivers/dcs/dcs_init_lib.h>
|
||||
#include <drivers/dram.h>
|
||||
#include <drivers/miu.h>
|
||||
#include <sys.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
|
||||
int mcu_initialize_dram (bool resume)
|
||||
{
|
||||
RELEASE_ASSERT(!resume);
|
||||
|
||||
// Don't perform DRAM initializion if the memory controller is already
|
||||
// initialized (e.g., for SecureROM validation testing).
|
||||
if (DCS_REG_READ_CH(0, rDCS_MCU_AMCCTRL) == 0) {
|
||||
clock_gate(CLK_DCS0, true);
|
||||
clock_gate(CLK_DCS1, true);
|
||||
clock_gate(CLK_DCS2, true);
|
||||
clock_gate(CLK_DCS3, true);
|
||||
clock_gate(CLK_MCC, true);
|
||||
|
||||
dcs_init(DCS_BOOT_COLDBOOT);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mcu_bypass_prep (int step)
|
||||
{
|
||||
}
|
||||
|
||||
uint64_t mcu_get_memory_size (void)
|
||||
{
|
||||
return dcs_get_memory_size();
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
void dcs_enable_slow_boot (bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
// switch to slow clock
|
||||
clocks_set_performance(kPerformanceMemoryLow);
|
||||
spin(1);
|
||||
}
|
||||
else {
|
||||
#if !SUPPORT_FPGA
|
||||
// switch back to full-speed
|
||||
clocks_set_performance(kPerformanceMemoryFull);
|
||||
spin(1);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
void dcs_dram_workarounds(dcs_boottype_t boot_type)
|
||||
{
|
||||
/* Nothing yet */
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Grab (Platform Specific) Tables with Definitions of Values for DCS Init & DCS Tunables
|
||||
#include <platform/dcsconfig.h>
|
||||
|
||||
#if DCS_FIXUP_PARAMS
|
||||
// Grab (Target Specific) Definition of Required Fixups to the Values for DCS Init
|
||||
#include <target/dcsfixup.h>
|
||||
#endif
|
||||
//================================================================================
|
||||
void dcs_init_config_params(dcs_config_params_t *use_dcs_params, dcs_target_t targtype)
|
||||
{
|
||||
memcpy(use_dcs_params, &dcs_params, sizeof(dcs_config_params_t));
|
||||
|
||||
#if DCS_FIXUP_PARAMS
|
||||
// This gives the particular target a chance to make target-specific changes
|
||||
dcs_init_config_fixup_params(use_dcs_params, targtype);
|
||||
#endif
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
const dcs_tunable_t *dcs_init_tunable_table(uint32_t *table_len)
|
||||
{
|
||||
if (table_len)
|
||||
*table_len = sizeof(dcs_tunables) / sizeof(dcs_tunables[0]);
|
||||
|
||||
return dcs_tunables;
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Save off calibration results to AOP_SRAM region (later to be stitched into reconfig sequence)
|
||||
// Order of registers to be saved must match the order to be restored
|
||||
volatile uint32_t *dcs_save_calibration_results(volatile uint32_t *save_region, uint32_t freq)
|
||||
{
|
||||
/* TBD */
|
||||
return NULL;
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Stitch the saved calibration results into the reconfig sequence
|
||||
// To be called immediately after stitching mcu_aop_awake_reconfig_pre_restore
|
||||
// Order of registers to be restored matches the order in the reconfig sequence
|
||||
void dcs_restore_calibration_results(volatile uint32_t *save_region)
|
||||
{
|
||||
/* TBD */
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
@@ -0,0 +1,812 @@
|
||||
/*
|
||||
* Copyright (C) 2014-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Init Sequence Library for use in:
|
||||
* Driver for the LPDDR4 compatible DRAM Control Subsystem (DCS) block
|
||||
*/
|
||||
|
||||
/*
|
||||
Summary of Steps from the Spec (Spreadsheet)
|
||||
|
||||
+ (Aa) Steps 0,1,2,3a [need to identify parameterization]
|
||||
+ (Ab) Step 3b [PMGR: set Freq to 50MHz & delay-wait]
|
||||
+ (Ac) Steps 3c,4,5 [need to identify parameterization]
|
||||
+ (B) Step 6 [Change Clk Speed]
|
||||
+ (C) Step 7 [include delay-wait from early Step 8]
|
||||
+ (D) Step 8a [Cal: CA 800MHz Vmin]
|
||||
+ (E) Step 8b [Write Regs]
|
||||
+ (F) Step 8c [Cal: CA 800MHz Vmin] (...again? should it be CS?)
|
||||
+ (G) Step 8d [Write Regs]
|
||||
+ (H) Step 9 [Write Regs]
|
||||
+ (I) Step 10 [Cal: WrLvl, RdDq, WrDq 800MHz Vmin]
|
||||
+ (J) Step 11 [Write Regs]
|
||||
+ (K) Step 12 [Cal: CA 1200MHz Vnom]
|
||||
+ (L) Step 13 [Write Regs]
|
||||
+ (M) Step 14 [Cal: WrLvl, RdDq, WrDq 1200MHz Vmin]
|
||||
+ (N) Steps 15,16,17,18,19,20 [need to identify parameterization]
|
||||
|
||||
Between these steps there is possibly a need/desire for:
|
||||
- Frequency Changes (PMGR)
|
||||
- PMU save/restore
|
||||
- debug messages
|
||||
- register dumps (DV, SiVal)
|
||||
- anything else!
|
||||
|
||||
CONFIG Table:
|
||||
Compile-Time Known:
|
||||
Type of Execution Environment CoreOS, DV, SiVal
|
||||
Type of Target SoC, FPGA, Palladium
|
||||
ChipID 0x8000, 0x8001, etc.
|
||||
Revision A0, B0, B1, etc.
|
||||
Num DCS 4, 8, etc. (Derived...!)
|
||||
Variant Flags Work-arounds, RADAR Ref., et al.
|
||||
|
||||
(Config Info know at Compile time can be subject to #if)
|
||||
|
||||
Run-Time Known:
|
||||
Type of Init ColdBoot, AOP_DDR, AOP_AWAKE
|
||||
Debug Flags Low-Level, Milestone, et al.
|
||||
|
||||
RegValue Table
|
||||
Much like today's: various values for various registers
|
||||
Sensitive to ChipID (also Target type?)
|
||||
(Internal static alloc (Complete Table Fill-in within Init function):
|
||||
Fill in Values (per ChipID/Rev & Target-type)
|
||||
return pointer to caller
|
||||
(Allows customization by caller before use)
|
||||
|
||||
TODO:
|
||||
- Convert to using SPDS for register names, et al
|
||||
|
||||
*/
|
||||
|
||||
//================================================================================
|
||||
// API Definitions
|
||||
#include <drivers/dcs/dcs_init_lib.h>
|
||||
|
||||
extern dcs_config_t dcs_cfg;
|
||||
extern dcs_config_params_t dcs_params;
|
||||
|
||||
#if izIBOOT
|
||||
extern int debug_level_dcs;
|
||||
#endif
|
||||
|
||||
void dcs_enable_autorefresh(void)
|
||||
{
|
||||
uint32_t arefen_freq0 = 0x1011013f;
|
||||
uint32_t arefen_freq1 = 0x10010000;
|
||||
|
||||
arefen_freq1 = 0x10110000;
|
||||
|
||||
// Configure auto-refresh. Freq0 has the auto-refresh enable, so do it last.
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(3), 0x10100000);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(2), 0x10000000);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(1), arefen_freq1);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFEN_FREQ(0), arefen_freq0);
|
||||
}
|
||||
|
||||
|
||||
//================================================================================
|
||||
// Implementing the Various Steps of the DCS Init, per Specification
|
||||
// Based on AMC Init Spec (Spreadsheet)
|
||||
// - Supporting Maui: Spec (v??)
|
||||
//================================================================================
|
||||
// Step 0: AMC Prolog
|
||||
//================================================================================
|
||||
void dcs_init_Prolog(void)
|
||||
{
|
||||
// NOTE: between the Compiler and the Optimization, this should vanish for non-FPGA builds
|
||||
if (izFPGA && izColdBoot) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 1);
|
||||
delay_for_us(200);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 0);
|
||||
delay_for_us(200);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 1);
|
||||
delay_for_us(200);
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 1: AMC Initial Configuration
|
||||
//================================================================================
|
||||
void dcs_init_AMC_Initial_Config(void)
|
||||
{
|
||||
uint32_t i,n;
|
||||
|
||||
// rdar://problem/19137387: this applies to Maui A1 and B0, as well as other SoCs before Cayman
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_MODEREG, 0x1);
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_VCO, dcs_params.spllctrl_vco_1);
|
||||
|
||||
|
||||
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
for (n = 0; n < dcs_params.num_freqchngctl_regs; n++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL_FREQ(n, i), dcs_params.freq[i].freqchngctl[n]);
|
||||
|
||||
// This register write to be skipped for Maui A0/A1, but written to for B0 & later, and all other SoCs
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0))
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGTIM_FREQ(i), dcs_params.freq[i].freqchngtim);
|
||||
}
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQCALVREFCODECONTROL, dcs_params.wrdqcalvrefcodecontrol);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQCALVREFCODECONTROL, dcs_params.rddqcalvrefcodecontrol);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MODEREG, 0x120c90b8);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LAT_FREQ(0), dcs_params.freq[0].lat);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LAT_FREQ(1), dcs_params.freq[1].lat);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PHYRDWRTIM_FREQ(i), dcs_params.freq[i].phyrdwrtim);
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_CASPCH_FREQ(i), dcs_params.freq[i].caspch);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ACT_FREQ(i), dcs_params.freq[i].act);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_FREQ(i), dcs_params.freq[i].autoref);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_SELFREF_FREQ(i), dcs_params.freq[i].selfref);
|
||||
|
||||
if (i == 0) dcs_reg_write_all_chan(rDCS_MCU_MODEREG, dcs_params.modereg);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PDN_FREQ(i), dcs_params.freq[i].pdn);
|
||||
if (i == 0) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PDN1, dcs_params.pdn1);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MODEREG1, dcs_params.modereg1);
|
||||
}
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_PARAMS, dcs_params.autoref_params);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PDN, dcs_params.pdn);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_DERATE_FREQ(0), dcs_params.freq[0].derate);
|
||||
|
||||
// These register writes to be skipped for Maui A0/A1, but written to for B0 & later, and all other SoCs
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0))
|
||||
for(i = 1; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_DERATE_FREQ(i), dcs_params.freq[i].derate);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LAT_FREQ(i), dcs_params.freq[i].lat2);
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_TAT_FREQ(i), dcs_params.freq[i].tat);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_RNKCFG, dcs_params.rnkcfg);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MIFQMAXCTRL_FREQ(0), dcs_params.freq[0].mifqmaxctrl);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MIFQMAXCTRL_FREQ(3), dcs_params.freq[3].mifqmaxctrl);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PWRMNGTEN, 0);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, 0x00002000);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCTRL, 0x00000002);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LS3B_QUIES_CTRL, 0x00000015);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MCPHYUPDTPARAM, 0x15030000);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 2: AMP Initial Configuration
|
||||
//================================================================================
|
||||
void dcs_init_AMP_Initial_Config(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPEN(i), 0x00000001);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_CA, i), dcs_params.freq[i].cavref);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ0, i), dcs_params.freq[i].dqvref);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_VREF_F(AMP_DQ1, i), dcs_params.freq[i].dqvref);
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_CNTL(AMP_CA), dcs_params.casdllupdatectrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_CNTL(AMP_DQ0), dcs_params.dqsdllupdatectrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_CNTL(AMP_DQ1), dcs_params.dqsdllupdatectrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step2);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step2);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step2 & 0x7, 0x0);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step2 & 0x7, 0x0);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ0), dcs_params.wrdqdqssdllctrl_step2);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ1), dcs_params.wrdqdqssdllctrl_step2);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ0), dcs_params.wrdqdqssdllctrl_step2 & 0x7, 0x0);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(AMP_DQ1), dcs_params.wrdqdqssdllctrl_step2 & 0x7, 0x0);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, dcs_params.cawrlvlsdllcode);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, dcs_params.cawrlvlsdllcode & 0x300, 0x000);
|
||||
|
||||
if (!izFPGA)
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLLOCKTIM(i), dcs_params.dlllocktim);
|
||||
|
||||
if(dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSPDENALWYSON(AMP_DQ0), 0x00000001);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSPDENALWYSON(AMP_DQ1), 0x00000001);
|
||||
}
|
||||
|
||||
// These register writes to be skipped for Maui A0/A1
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
for(i = 1; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMPCA_DFICALTIMING_F(i), dcs_params.freq[i].cadficaltiming);
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ0, i), dcs_params.freq[i].dqdficaltiming);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_DFICALTIMING_F(AMP_DQ1, i), dcs_params.freq[i].dqdficaltiming);
|
||||
}
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALTIMING_F(0), dcs_params.rdwrdqcaltiming_f0);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALSEGLEN_F(0), dcs_params.rdwrdqcalseglen_f0);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALTIMING_F(1), dcs_params.rdwrdqcaltiming_f1);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALSEGLEN_F(1), dcs_params.rdwrdqcalseglen_f1);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDWRDQCALTIMING_F(3), dcs_params.rdwrdqcaltiming_f3);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDDQCALPATPRBS4I, dcs_params.rddqcalpatprbs4i);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATPRBS4I, dcs_params.wrdqcalpatprbs4i);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATPRBS7(0), 0x87654321);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATPRBS7(1), 0xcdedcba9);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATPRBS7(2), 0x456789ab);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATPRBS7(3), 0x5fa63123);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALPATINVERTMASK, 0x55550000);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQCALWINDOW_F(0), dcs_params.freq[0].rddqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQCALWINDOW_F(0), dcs_params.freq[0].wrdqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQCALWINDOW_F(1), dcs_params.freq[1].rddqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQCALWINDOW_F(1), dcs_params.freq[1].wrdqcalwindow);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MAXRDDQS_SDLL_MULFACTOR, dcs_params.maxrddqssdllmulfactor);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MAXWRDQS_SDLL_MULFACTOR, dcs_params.maxwrdqssdllmulfactor);
|
||||
|
||||
// These register writes to be skipped for Maui A0/A1
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_RDDQSMULFACTOR(AMP_DQ0), 0x20181000);
|
||||
dcs_reg_write_all_chan(rDCS_AMPDQ_RDDQSMULFACTOR(AMP_DQ1), 0x20181000);
|
||||
}
|
||||
|
||||
for(i = 0; i < DCS_FREQUENCY_SLOTS; i++) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDCAPCFG_FREQ(AMP_DQ0, i), dcs_params.freq[i].rdcapcfg);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDCAPCFG_FREQ(AMP_DQ1, i), dcs_params.freq[i].rdcapcfg);
|
||||
}
|
||||
|
||||
if (!izFPGA) {
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTCTRL(i), dcs_params.dllupdtctrl1);
|
||||
}
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTINTVL(AMP_CA), dcs_params.dllupdtintvl);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTINTVL(AMP_DQ0), 0);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLUPDTINTVL(AMP_DQ1), 0);
|
||||
|
||||
for(i = AMP_DQ0 ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DLLEN(i), 0x00000100);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DCCCONTROL, dcs_params.dcccontrol);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DCCTIMER, 0x00000190);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALDYNHALFCLKDLYCTRL, 0x00000001);
|
||||
|
||||
|
||||
// AMPH configuration
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CB_DRIVESTR, dcs_params.cbdrivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CB_IOCTL, dcs_params.cbioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CK_DRIVESTR, dcs_params.ckdrivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_CK_IOCTL, dcs_params.ckioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_DRIVESTR, dcs_params.b0drivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_IOCTL, dcs_params.b0ioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_ODT, dcs_params.b0odt);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_ODTCTRL, dcs_params.b0odtctrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_DRIVESTR, dcs_params.b1drivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_ODTCTRL, dcs_params.b1odtctrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_IOCTL, dcs_params.b1ioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_ODT, dcs_params.b1odt);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_DRIVESTR, dcs_params.dqs0drivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_IOCTL, dcs_params.dqs0ioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_ODT, dcs_params.dqs0odt);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_ZDETBIASEN, dcs_params.dqs0zdetbiasen);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS0_ODTCTRL, dcs_params.dqs0odtctrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_DRIVESTR, dcs_params.dqs1drivestr);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_IOCTL, dcs_params.dqs1ioctl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_ODT, dcs_params.dqs1odt);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_ZDETBIASEN, dcs_params.dqs1zdetbiasen);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DQS1_ODTCTRL, dcs_params.dqs1odtctrl);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_DBG_REG0, 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_ZCAL_FSM(1), dcs_params.zcalfsm1);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_ZCAL_FSM(0), dcs_params.zcalfsm0);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_SPARE(0), dcs_params.spare0);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDDQCALTVREF, dcs_params.hwrddqcaltvref);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWWRDQCALTVREF, dcs_params.hwwrdqcaltvref);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 3: Self-Refresh Exit
|
||||
//================================================================================
|
||||
void dcs_init_Self_Refresh_Exit_a(void)
|
||||
{
|
||||
// Wait 5 us after Impedence Calibration to avoid McPhyPending
|
||||
// preventing the SRFSM from exiting SR.
|
||||
dcs_spin(5, "after Imp. Cal.");
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFPARAM, dcs_params.arefparam);
|
||||
|
||||
for(int i = 0; i < DCS_FREQUENCY_SLOTS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_FREQ(i), dcs_params.freq[i].autoref2);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AUTOREF_PARAMS, dcs_params.autoref_params2);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc);
|
||||
// M8 Bug radar #20346417, two writes to ensure propogation
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LONGSR, dcs_params.longsr);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_LONGSR, dcs_params.longsr);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MCPHYUPDTPARAM, 0x15030004);
|
||||
|
||||
}
|
||||
|
||||
//========================================
|
||||
// Caller Code should:
|
||||
// - Change Frequency to 50MHz
|
||||
//========================================
|
||||
|
||||
void dcs_init_Self_Refresh_Exit_b(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCTRL, 0x00000003);
|
||||
|
||||
for(uint32_t i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPINIT(i), 0x00000001);
|
||||
|
||||
if (!izFPGA) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_IMPCALCMD, 0x00000001);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_IMPCALCMD, 0x01, 0x00);
|
||||
}
|
||||
|
||||
if (izResume)
|
||||
dcs_enable_autorefresh();
|
||||
|
||||
dcs_spin(2200, "After Enable Auto-Refresh");
|
||||
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, dcs_params.freqchngctl_step3);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_FREQCHNGCTL, 0x10000, 0x00000);
|
||||
dcs_spin(2, "After SoC Update");
|
||||
}
|
||||
|
||||
// Resume-Boot and Cold-Boot use different Exit commands for Self-Refresh
|
||||
// Issue self-refresh exit cmd for resume boot with MPC
|
||||
int n = (izColdBoot)? 0x00000000:0x00004000;
|
||||
// Issue self-refresh exit cmd for resume boot with MPC
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MRINITCMD_0, n);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_MRINITCMD_0, n | 0x1);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_MRINITCMD_0, 0x01, 0x00);
|
||||
|
||||
dcs_spin(2, NULL);
|
||||
|
||||
dcs_reg_write(rGLBTIMER_CHEN, (1 << dcs_cfg.num_dcs) - 1);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 4: DRAM Reset, ZQ Calibration & Configuration (cold boot only)
|
||||
//================================================================================
|
||||
void dcs_init_ZQ_Cal_Cfg(void)
|
||||
{
|
||||
// ZQ calibration START MPC cmd
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0, 0x4f);
|
||||
// wait 1us for tZQCAL
|
||||
dcs_spin(1, "tZQCAL");
|
||||
|
||||
// ZQ calibration LATCH MPC cmd
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0, 0x51);
|
||||
// wait 10ns for tZQLAT
|
||||
dcs_spin(1, "tZQLAT");
|
||||
|
||||
if (izColdBoot) {
|
||||
// MR2 register (read/write latency)
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x2, 0x0);
|
||||
// MR1 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x1, 0x8e);
|
||||
// MR3 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x3, dcs_params.mr3cmd);
|
||||
// MR22 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x16, 0x0);
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xb, 0x0);
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xd, dcs_params.mr13cmd);
|
||||
// MR12 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xc, 0x59);
|
||||
// MR14 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xe, 0x59);
|
||||
// MR23 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x17, 0x80);
|
||||
|
||||
uint32_t patinvertmask = (DCS_REG_READ_CH(0, rDCS_AMP_HWRDDQCALPATPRBS4I) >> 16) & 0xffff;
|
||||
uint32_t prbs = DCS_REG_READ_CH(0, rDCS_AMP_HWWRDQCALPATPRBS4I);
|
||||
|
||||
// MR15 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xf, patinvertmask & 0xff);
|
||||
// MR20 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x14, (patinvertmask >> 8) & 0xff);
|
||||
// MR32 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x20, prbs & 0xff);
|
||||
// MR40 register
|
||||
dcs_mrcmd(MR_MPC, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x28, (prbs >> 8) & 0xff);
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 5a: AddrConfig Configuration
|
||||
//================================================================================
|
||||
void dcs_init_AddrCfg_Cfg(void)
|
||||
{
|
||||
|
||||
dcs_reg_write(rAMCC_ADDRCFG_ADDR, dcs_params.addrcfg);
|
||||
#if NUM_AMCCS == 2
|
||||
dcs_reg_write(rAMCC1_ADDRCFG_ADDR, dcs_params.addrcfg);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
//========================================
|
||||
// Caller Code should:
|
||||
// - Use MR Cmds to Query the Device
|
||||
//========================================
|
||||
|
||||
//================================================================================
|
||||
// Step 5b: Total Mem Size Config
|
||||
//================================================================================
|
||||
void dcs_init_TotalSize_Cfg(uint32_t total_size_Mbytes)
|
||||
{
|
||||
|
||||
dbgprintf(DCS_DBG_ASSESS_CONFIG, "Memory_size: %llu bytes\n",
|
||||
(((uint64_t)total_size_Mbytes) * MEG * NUM_AMCCS));
|
||||
// (Units of 128 MBs in the register)
|
||||
dcs_reg_write(rAMCC_DRAMACCCTRL_ADDR, ((total_size_Mbytes / NUM_AMCCS) / DCS_NUM_MEG_IN_DRAM_BLK) - 1);
|
||||
dcs_reg_write(rAMCC_MCCCHNLDEC_ADDR, dcs_params.chnldec);
|
||||
|
||||
#if NUM_AMCCS == 2
|
||||
dcs_reg_write(rAMCC1_DRAMACCCTRL_ADDR, ((total_size_Mbytes / NUM_AMCCS) / DCS_NUM_MEG_IN_DRAM_BLK) - 1);
|
||||
dcs_reg_write(rAMCC1_MCCCHNLDEC_ADDR, dcs_params.chnldec);
|
||||
#endif
|
||||
dbgprintf(DCS_DBG_ASSESS_CONFIG, "rAMCC_DRAMACCCTRL: 0x%08x\n", rAMCC_DRAMACCCTRL);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 6: Switch from boot-clock speed to normal operation speed
|
||||
//================================================================================
|
||||
void dcs_init_Reenable_AMC_Scheduler(void)
|
||||
{
|
||||
// Wait 5 us before freq change to make sure all refreshes have been flushed
|
||||
dcs_spin(5, "After Refresh");
|
||||
|
||||
// Enable (again) the AMC Scheduler
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCTRL, 0x00000003);
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 7: Setup registers for CA calibration for bucket 1
|
||||
//================================================================================
|
||||
void dcs_init_CA_Cal_Setup_Freq1(void)
|
||||
{
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xd, dcs_params.mr13cmd_step7);
|
||||
|
||||
if (izColdBoot) {
|
||||
if (izFPGA) {
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xb, 0x00);
|
||||
} else {
|
||||
// MR2 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x2, 0x52);
|
||||
// MR1 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x1, 0xae);
|
||||
// MR3 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x3, dcs_params.mr3cmd_step7);
|
||||
// MR22 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x16, dcs_params.mr22cmd);
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xb, dcs_params.mr11cmd);
|
||||
// MR12 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xc, 0x11);
|
||||
// MR14 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xe, 0x11);
|
||||
}
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x00000200);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x0200, 0x0000);
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 8: AMP Dynamic CA Vref Timing Calibration at Vmin 800MHz
|
||||
//================================================================================
|
||||
void dcs_init_CA_Cal_Freq1(void)
|
||||
{
|
||||
// Nothing to be done at this step for cold boot
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 9: Setup registers for DQ calibration for bucket 1
|
||||
//================================================================================
|
||||
void dcs_init_DQ_Cal_Setup_Freq1_a(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (izColdBoot) {
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0xd, dcs_params.mr13cmd_step9);
|
||||
}
|
||||
|
||||
dcs_spin(1, NULL);
|
||||
|
||||
if(izResume) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PWRMNGTEN, 0x00000002);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, 0x01008888);
|
||||
|
||||
for(i = AMP_DQ0 ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_WRDQDQSSDLLCTRL(i), 0xFF00000C);
|
||||
for(i = AMP_CA ; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_SDLL_UPDATE_DEFER_EN(i), 0x00000000);
|
||||
for(i = AMP_DQ0; i < DCS_AMP_NUM_PHYS; i++)
|
||||
dcs_reg_write_all_chan(rDCS_AMP_MDLLOVRRD(i), 0x00000000);
|
||||
}
|
||||
}
|
||||
|
||||
// Caller code should change frequency to bucket 1
|
||||
void dcs_init_DQ_Cal_Setup_Freq1_b(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, dcs_params.freqchngctl_step9);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_FREQCHNGCTL, 0x10000, 0x00000);
|
||||
|
||||
// Wait 2us for the soc update to finish
|
||||
dcs_spin(2, NULL);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 10: PHY write DQ calibration
|
||||
//================================================================================
|
||||
void dcs_init_wrdq_skew(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSDQ_SKEWCTL(AMP_DQ0), 0x06000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQSDQ_SKEWCTL(AMP_DQ1), 0x06000000);
|
||||
}
|
||||
|
||||
void dcs_init_post_wrlvl(void)
|
||||
{
|
||||
if(dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ0), 0x00000010);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ1), 0x00000010);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 11: Setup registers for CA calibration for bucket 0
|
||||
//================================================================================
|
||||
void dcs_init_CA_Cal_Setup_Freq0(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
|
||||
if(dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ0), 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_DQFLTCTRL(AMP_DQ1), 0x00000000);
|
||||
}
|
||||
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, dcs_params.mr13cmd_step11);
|
||||
if (!izFPGA) {
|
||||
// MR2 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x02, dcs_params.mr2cmd_step11);
|
||||
// MR1 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x01, dcs_params.mr1cmd_step11);
|
||||
// MR3 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x03, dcs_params.mr3cmd_step11);
|
||||
}
|
||||
|
||||
// MR22 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x16, dcs_params.mr22cmd_step11);
|
||||
// MR11 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0b, (izFPGA) ? 0x00 : dcs_params.mr11cmd_step11);
|
||||
// MR12 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0c, dcs_params.mr12cmd_step11);
|
||||
// MR14 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0e, dcs_params.mr14cmd_step11);
|
||||
|
||||
if((dcs_params.supported_freqs & DCS_FREQ(1)) == 0) {
|
||||
dcs_reg_write_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x00000200);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_CAWRLVLSDLLCODE, 0x200, 0x000);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 12: AMP Dynamic CA Timing Calibration
|
||||
//================================================================================
|
||||
|
||||
//================================================================================
|
||||
// Step 13: Setup registers for DQ calibration for bucket 0
|
||||
//================================================================================
|
||||
void dcs_init_DQ_Cal_Setup_Freq0_a(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, dcs_params.mr13cmd_step13);
|
||||
|
||||
// Wait 1 us
|
||||
dcs_spin(1, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
void dcs_init_DQ_Cal_Setup_Freq0_b(void)
|
||||
{
|
||||
if (izColdBoot) {
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, 0x00010000);
|
||||
dcs_reg_poll_all_chan(rDCS_MCU_FREQCHNGCTL, 0x10000, 0x00000);
|
||||
|
||||
// Wait 2us for the soc update to finish
|
||||
dcs_spin(2, NULL);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 14: AMP Dynamic DQ Calibration
|
||||
//================================================================================
|
||||
|
||||
//================================================================================
|
||||
// Step 15: Setup Registers for Boot
|
||||
//================================================================================
|
||||
void dcs_init_Reg_for_Boot(void)
|
||||
{
|
||||
|
||||
#ifndef DCS_RUN_AT_50MHZ
|
||||
if (izColdBoot) {
|
||||
// MR13 register
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, dcs_params.mr13cmd_step15);
|
||||
}
|
||||
#endif
|
||||
if(izFPGA && !(dcs_params.supported_freqs & DCS_FREQ(1)))
|
||||
dcs_mrcmd(MR_WRITE, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x0d, 0x50);
|
||||
|
||||
// Wait 1 us
|
||||
dcs_spin(1, NULL);
|
||||
|
||||
if (izColdBoot) {
|
||||
dcs_reg_write_all_chan(rDCS_MCU_FREQCHNGCTL, dcs_params.freqchngctl_step15);
|
||||
|
||||
#if !DCS_DO_CALIBRATION
|
||||
// skip these for all silicon targets, where calibration is performed, also skip for any Maui A1 target
|
||||
if((dcs_cfg.chipID != 0x8000) || (dcs_cfg.chipID == 0x8000 && dcs_cfg.chipRev >= CHIP_REVISION_B0)) {
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQSDLL_DLYSEL(AMP_DQ0), 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDDQSDLL_DLYSEL(AMP_DQ1), 0x00000000);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step15);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step15);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ0), dcs_params.rdsdllctrl_step15 & 0x7, 0x0);
|
||||
dcs_reg_poll_all_chan(rDCS_AMP_RDSDLLCTRL(AMP_DQ1), dcs_params.rdsdllctrl_step15 & 0x7, 0x0);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
if(!izFPGA)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDWRDQCALFULLSCANEN, 0x00000000);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_HWRDWRDQCALFULLSCANEN, 0x00000003);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 16: Enable Other Features
|
||||
//================================================================================
|
||||
void dcs_init_MoreFeatures(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AREFPARAM, dcs_params.arefparam);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc2);
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_QBREN, dcs_params.qbren_step16);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PSQWQCTL0, 0x00000100);
|
||||
|
||||
if (izColdBoot)
|
||||
dcs_enable_autorefresh();
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_DYN_ISEL_ASRTIME, dcs_params.b0dyniselasrtime);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B0_DYN_ISEL, dcs_params.b0dynisel);
|
||||
dcs_reg_write_all_chan(rDCS_AMPH_B1_DYN_ISEL, dcs_params.b1dynisel);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 17: Enable Fast Critical Word Forwarding Feature
|
||||
//================================================================================
|
||||
void dcs_init_Fast_Critical_Word_Forwarding(void)
|
||||
{
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_QBRPARAM, dcs_params.qbrparam);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_QBREN, dcs_params.qbren);
|
||||
dcs_reg_write(rAMCC_MCCGEN_ADDR, dcs_params.mccgen);
|
||||
|
||||
|
||||
#if NUM_AMCCS == 2
|
||||
dcs_reg_write(rAMCC1_MCCGEN_ADDR, dcs_params.mccgen);
|
||||
|
||||
#endif // #if NUM_AMCCS == 2
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 18: Enable Power- and Clock-Gating Features; Config MCC and Global Timers
|
||||
//================================================================================
|
||||
void dcs_init_Gating_Global_Timers(void)
|
||||
{
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPCLK(AMP_CA), dcs_params.caampclk);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPCLK(AMP_DQ0), dcs_params.dqampclk);
|
||||
dcs_reg_write_all_chan(rDCS_AMP_AMPCLK(AMP_DQ1), dcs_params.dqampclk);
|
||||
dcs_reg_write_all_chan(rDCS_SPLLCTRL_MDLLPWRDNCFG(0), 0x00000001);
|
||||
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PWRMNGTEN, dcs_params.pwrmngten);
|
||||
dcs_reg_write(rGLBTIMER_PMGRWAKEUPCFG, 0x000001ff);
|
||||
|
||||
|
||||
if(!izFPGA) {
|
||||
|
||||
dcs_reg_write_all_chan(rDCS_MCU_PSQWQCTL1, 0x01e60120);
|
||||
}
|
||||
|
||||
|
||||
// Global Timer Setup
|
||||
dcs_reg_write(rGLBTIMER_PREFREQ2ALLBANKDLY(0), 0x00f000f0);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQ2ALLBANKDLY(1), 0x00f000f0);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQCHNG2FREQCHNGDLY(0), 0x02400240);
|
||||
dcs_reg_write(rGLBTIMER_PREFREQCHNG2FREQCHNGDLY(1), 0x02400240);
|
||||
dcs_reg_write(rGLBTIMER_MDLLTIMER, 0x000bb8); // 3000
|
||||
dcs_reg_write(rGLBTIMER_DCCTIMER, 0x000bb8);
|
||||
dcs_reg_write(rGLBTIMER_MDLLVOLTRAMPTIMER, 0x00004b); // 75
|
||||
dcs_reg_write(rGLBTIMER_CTRLUPDMASKTIMER, 0x00000f); // 15
|
||||
dcs_reg_write(rGLBTIMER_IDTTIMER, 0x007530); // 30000
|
||||
dcs_reg_write(rGLBTIMER_RDCALTIMER, 0x2dc6c0); // 3000000
|
||||
dcs_reg_write(rGLBTIMER_WRCALTIMER, 0x2dc6c0); // 3000000
|
||||
dcs_reg_write(rGLBTIMER_ZQCTIMER, 0x3d0900); // 4000000
|
||||
dcs_reg_write(rGLBTIMER_PERCAL_FREQCHNGTIMER, 0x000001); // 300000
|
||||
dcs_reg_write(rGLBTIMER_IMPCALTIMER, 0x002ee0); // 12000
|
||||
dcs_reg_write(rGLBTIMER_PERVREFCALCFG, 0x0000000b);
|
||||
dcs_reg_write(rGLBTIMER_FREQCHNGCFG, 0x000000ff);
|
||||
|
||||
// Dynamic Clk & Power Gating
|
||||
dcs_reg_write_all_chan(rDCS_MCU_AMCCLKPWRGATE, 0x050a0000);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
// Step 19: ODTS read & set interval for periodic MR4 on-die Temp sensor reading
|
||||
//================================================================================
|
||||
void dcs_init_ODTS(void)
|
||||
{
|
||||
uint8_t temp[16*8]; // Far more Channels/Ranks than we are likely ever to have/need
|
||||
// INSTEAD OF: uint8_t temp[dcs_cfg.num_dcs * dcs_cfg.num_rank];
|
||||
|
||||
// MR4 read to bring memory out of self-refresh
|
||||
dcs_mrcmd(MR_READ, dcs_cfg.num_dcs, dcs_cfg.num_rank, 0x4, (uintptr_t)temp);
|
||||
// M8 Bug radar #20346417, two writes to ensure propogation
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc3);
|
||||
dcs_reg_write_all_chan(rDCS_MCU_ODTSZQC, dcs_params.odtszqc3);
|
||||
|
||||
}
|
||||
|
||||
//================================================================================
|
||||
@@ -0,0 +1,17 @@
|
||||
# Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_DCS=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/dcs.o \
|
||||
$(LOCAL_DIR)/dcs_init_lib_t8010.o
|
||||
@@ -0,0 +1,93 @@
|
||||
/*
|
||||
* Copyright (C) 2011-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <platform/int.h>
|
||||
#include <platform/error_handler.h>
|
||||
#include <platform/soc/hwisr.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <platform/soc/miu.h>
|
||||
|
||||
// All errors (the remaining bits are perf counters)
|
||||
#define AMCC_IRERRDBG_INTEN_ALLERRORS ( \
|
||||
AMCC_IRERRDBG_INTSTS_MCC_TP_PAR_ERR_UMASK \
|
||||
| AMCC_IRERRDBG_INTSTS_MCC_DAT_ONE_BIT_ERR_UMASK \
|
||||
| AMCC_IRERRDBG_INTSTS_MCC_DAT_MULTI_BITS_ERR_UMASK \
|
||||
| AMCC_IRERRDBG_INTSTS_MCC_AF_ERR_UMASK \
|
||||
| AMCC_IRERRDBG_INTSTS_MCC_TP_MULTI_PAR_ERR_UMASK \
|
||||
| AMCC_IRERRDBG_INTSTS_MCS_LS3_B_ALLOC_PAR_ERR_UMASK \
|
||||
| AMCC_IRERRDBG_INTSTS_MCS_LS3_B_RESP_PAR_ERR_UMASK \
|
||||
| AMCC_IRERRDBG_INTSTS_MCS_LS3_B_TOKEN_PAR_ERR_UMASK \
|
||||
| AMCC_IRERRDBG_INTSTS_MCS_LS3_B_DATA_PULL_PAR_ERR_UMASK \
|
||||
)
|
||||
|
||||
#define AMCC_IRERRDBG_INTSTS_ALLERRORS AMCC_IRERRDBG_INTEN_ALLERRORS
|
||||
|
||||
#define AMCC_IRERRDBG_MCC_AF_ERR_LOG2_AGENT_IODAP (0x88)
|
||||
|
||||
#define CP_COM_NORM_MSK_CLR_ALL (~0)
|
||||
#define CP_COM_NORM_MSK_ILLEGAL_COH_INTS ( \
|
||||
CP_COM_INT_NORM_MASK_SET_CCU0_ILLEGAL_PIO_ACCESS_INT_MSK_SET_UMASK \
|
||||
| CP_COM_INT_NORM_MASK_SET_CCU1_ILLEGAL_PIO_ACCESS_INT_MSK_SET_UMASK \
|
||||
)
|
||||
|
||||
#if NUM_AMCCS > 1
|
||||
#error "amc_int_handler() must be recoded for NUM_AMCCS > 1"
|
||||
#endif
|
||||
|
||||
static void amc_int_handler(void *arg __unused)
|
||||
{
|
||||
uint32_t intsts = rAMCC_IRERRDBG_INTSTS(0);
|
||||
|
||||
if ((intsts & (AMCC_IRERRDBG_INTEN_ALLERRORS & ~AMCC_IRERRDBG_INTSTS_MCC_AF_ERR_UMASK)) == 0) {
|
||||
// Whitelist errors caused by the IODAP agent (Astris) since
|
||||
// these are most likely caused by user input errors.
|
||||
uint32_t agent_id = AMCC_IRERRDBG_MCC_AF_ERR_LOG2_MCC_AF_ERR_AID_LOG_XTRCT(rAMCC_IRERRDBG_MCC_AF_ERR_LOG2(0));
|
||||
if (agent_id == AMCC_IRERRDBG_MCC_AF_ERR_LOG2_AGENT_IODAP) {
|
||||
dprintf(DEBUG_INFO, "AMC error from IODAP (ignored): 0x%x\n", intsts);
|
||||
|
||||
// Clear the interrupt and continue on.
|
||||
rAMCC_IRERRDBG_INTSTS(0) = intsts;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
panic("Received unexpected AMC error. AMCC_IRERRDBG_INTSTS = 0x%x\n", intsts);
|
||||
}
|
||||
|
||||
static void cp_int_handler(void *arg __unused) {
|
||||
panic("Received unexpected Coherency Point error. CP_COM_INT_NORM_REQUEST = 0x%x\n", rCP_COM_INT_NORM_REQUEST);
|
||||
}
|
||||
|
||||
static void enable_cp_checks()
|
||||
{
|
||||
install_int_handler(INT_COHERENCE_PNT_ERR, cp_int_handler, NULL);
|
||||
rCP_COM_INT_NORM_MASK_CLR = CP_COM_NORM_MSK_CLR_ALL;
|
||||
unmask_int(INT_COHERENCE_PNT_ERR);
|
||||
}
|
||||
|
||||
static void enable_amc_checks()
|
||||
{
|
||||
install_int_handler(INT_MEM_CONTROLLER0, amc_int_handler, NULL);
|
||||
rAMCC_IRERRDBG_INTEN(0) = AMCC_IRERRDBG_INTEN_ALLERRORS;
|
||||
if (rAMCC_IRERRDBG_INTSTS(0) & AMCC_IRERRDBG_INTSTS_ALLERRORS) {
|
||||
// AMC Interrupts, unlike the CP ones, don't seem to stick. If an error already exists
|
||||
// this early in bootup, we won't get an interrupt upon unmask.
|
||||
amc_int_handler(NULL);
|
||||
}
|
||||
rAMCC_IRERRDBG_INTSTS(0) = AMCC_IRERRDBG_INTSTS_ALLERRORS;
|
||||
unmask_int(INT_MEM_CONTROLLER0);
|
||||
}
|
||||
|
||||
void platform_enable_error_handler() {
|
||||
enable_amc_checks();
|
||||
enable_cp_checks();
|
||||
}
|
||||
|
||||
@@ -0,0 +1,16 @@
|
||||
# Copyright (C) 2011-2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_PLATFORM_ERROR_HANDLER=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/error_handler.o
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef PLATFORM_APCIE_H
|
||||
#define PLATFORM_APCIE_H
|
||||
|
||||
#define APCIE_LANE_CFG_X1_X1_X1_X1 (0)
|
||||
#define APCIE_LANE_CFG_X2_X1_X1 (1)
|
||||
#define APCIE_LANE_CFG_X1_X1_X2 (2)
|
||||
#define APCIE_LANE_CFG_X2_X2 (3)
|
||||
|
||||
#define APCIE_LANE_CONFIG_NVME0_X1 APCIE_LANE_CFG_X1_X1_X1_X1
|
||||
#define APCIE_LANE_CONFIG_NVME0_X2 APCIE_LANE_CFG_X2_X1_X1
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef _APCIE_REGS_H
|
||||
#define _APCIE_REGS_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <soc/t8010/a0/apcie_config.h>
|
||||
#include <soc/t8010/a0/apcie_lcount.h>
|
||||
#include <soc/t8010/a0/x2_pcie_rc.h>
|
||||
|
||||
#define APCIE_COUNTER_PORT_STRIDE (APCIE_LCOUNT_BLK_TIME_L0_1_OFFSET - APCIE_LCOUNT_BLK_TIME_L0_0_OFFSET)
|
||||
#define APCIE_NUM_COUNTERS (8)
|
||||
|
||||
#define APCIE_PORT_COUNTER_BASE_ADDR(port) (APCIE_COUNTER_BASE_ADDR + (port) * APCIE_COUNTER_PORT_STRIDE)
|
||||
#define APCIE_PORT_BASE_ADDR(port) (APCIE_CONFIG_BASE_ADDR + APCIE_CONFIG_PORT_STRIDE * (port))
|
||||
#define PCIE_PORT_BASE_ADDR(port) (PCI_CONFIG_BASE + ((port) << PCI_DEVICE_SHIFT))
|
||||
|
||||
#define rAPCIE_COUNTER_VALUE(port, n) (*(volatile uint32_t *)(APCIE_PORT_COUNTER_BASE_ADDR(port) + (n) * 4))
|
||||
#define rAPCIE_COUNTER_COMMAND(port) (*(volatile uint32_t *)(APCIE_PORT_COUNTER_BASE_ADDR(port) + APCIE_LCOUNT_BLK_LCOUNT_COMMAND_0_OFFSET))
|
||||
|
||||
#define APCIE_COUNTER_ENABLE APCIE_LCOUNT_BLK_LCOUNT_COMMAND_0_ENABLE_UMASK
|
||||
#define APCIE_COUNTER_CLEAR APCIE_LCOUNT_BLK_LCOUNT_COMMAND_0_CLEAR_UMASK
|
||||
#define APCIE_COUNTER_CAPTURE APCIE_LCOUNT_BLK_LCOUNT_COMMAND_0_CAPTURE_UMASK
|
||||
|
||||
#define PCIE_RC_CAP_LINK_CONTROL2_OFFSET(link) (PCIE_PORT_BASE_ADDR(link) + X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_OFFSET)
|
||||
#define PCIE_RC_CAP_LINK_CONTROL2_PCIE_TARGET_LINK_SPEED_UMASK X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_UMASK
|
||||
|
||||
#define PCIE_RC_PORT_LOGIC_GEN2_CTRL_OFFSET(link) (PCIE_PORT_BASE_ADDR(link) + X2_PCIE_RC_X2_PCIE_DSP_PF0_PORT_LOGIC_GEN2_CTRL_OFF_OFFSET)
|
||||
#define PCIE_RC_PORT_LOGIC_GEN2_CTRL_NUM_OF_LANES_SHIFT X2_PCIE_RC_X2_PCIE_DSP_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_SHIFT
|
||||
#define PCIE_RC_PORT_LOGIC_GEN2_CTRL_NUM_OF_LANES_UMASK X2_PCIE_RC_X2_PCIE_DSP_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_UMASK
|
||||
|
||||
#define PCIE_RC_PORT_LOGIC_PORT_LINK_CTRL_OFFSET(link) (PCIE_PORT_BASE_ADDR(link) + X2_PCIE_RC_X2_PCIE_DSP_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_OFFSET)
|
||||
#define PCIE_RC_PORT_LOGIC_PORT_LINK_CTRL_LINK_CAPABLE_SHIFT X2_PCIE_RC_X2_PCIE_DSP_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_SHIFT
|
||||
#define PCIE_RC_PORT_LOGIC_PORT_LINK_CTRL_LINK_CAPABLE_UMASK X2_PCIE_RC_X2_PCIE_DSP_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_UMASK
|
||||
|
||||
#define PCIE_RC_PORT_LOGIC_L1SUB_CAPABILITY_REG_OFFSET(link) (PCIE_PORT_BASE_ADDR(link) + X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_OFFSET)
|
||||
#define PCIE_RC_PORT_LOGIC_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_UMASK X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_UMASK
|
||||
#define PCIE_RC_PORT_LOGIC_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_UMASK X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_UMASK
|
||||
|
||||
#define rAPCIE_PMA_LANE_TX_XCVR_DIAG_FUNC_PWR_CTRL(lane) (*(volatile uint32_t *)(APCIE_PHY_PMA_TX_LANE_BASE_ADDR + (PMA_TX_LANE_REGISTERS_BLK_XCVR_DIAG_FUNC_PWR_CTRL_OFFSET + ((lane) * APCIE_PHY_PMA_TX_LANE_STRIDE))))
|
||||
#define rAPCIE_PMA_LANE_TX_XCVR_DIAG_DCYA(lane) (*(volatile uint32_t *)(APCIE_PHY_PMA_TX_LANE_BASE_ADDR + (PMA_TX_LANE_REGISTERS_BLK_XCVR_DIAG_DCYA_OFFSET + ((lane) * APCIE_PHY_PMA_TX_LANE_STRIDE))))
|
||||
#define rAPCIE_PMA_LANE_TX_DIAG_TX_BOOST(lane) (*(volatile uint32_t *)(APCIE_PHY_PMA_TX_LANE_BASE_ADDR + (PMA_TX_LANE_REGISTERS_BLK_TX_DIAG_TX_BOOST_OFFSET + ((lane) * APCIE_PHY_PMA_TX_LANE_STRIDE))))
|
||||
|
||||
#define rAPCIE_PMA_LANE_RX_REE_GEN_CTRL_EN(lane) (*(volatile uint32_t *)(APCIE_PHY_PMA_RX_LANE_BASE_ADDR + (PMA_RX_LANE_REGISTERS_BLK_RX_REE_GEN_CTRL_EN_OFFSET + ((lane) * APCIE_PHY_PMA_RX_LANE_STRIDE))))
|
||||
#define rAPCIE_PMA_LANE_RX_REE_FREE0_CFGD(lane) (*(volatile uint32_t *)(APCIE_PHY_PMA_RX_LANE_BASE_ADDR + (PMA_RX_LANE_REGISTERS_BLK_RX_REE_FREE0_CFGD_OFFSET + ((lane) * APCIE_PHY_PMA_RX_LANE_STRIDE))))
|
||||
|
||||
#endif /* _APCIE_REGS_H */
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __DCSCONFIG_H
|
||||
#define __DCSCONFIG_H
|
||||
|
||||
// Needful defnitions for the initializers below
|
||||
#include <drivers/dcs/dcs.h>
|
||||
#include <drivers/dcs/dcs_regs.h>
|
||||
#include <drivers/dcs/dcs_init_lib.h>
|
||||
#include <drivers/dcs/dcs_calibration.h>
|
||||
|
||||
#include SUB_PLATFORM_HEADER(dcsconfig)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,272 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __DCSCONFIG_T8010_H
|
||||
#define __DCSCONFIG_T8010_H
|
||||
|
||||
dcs_config_params_t dcs_params = {
|
||||
.supported_freqs = DCS_FREQ(0) | DCS_FREQ(1) | DCS_FREQ(3),
|
||||
.num_freqchngctl_regs = 5,
|
||||
.spllctrl_vco_1 = 0x00000015,
|
||||
.wrdqcalvrefcodecontrol = 0x19191111,
|
||||
.rddqcalvrefcodecontrol = 0x19199191,
|
||||
.pdn1 = 0x0,
|
||||
.modereg = 0x1a0c80f4,
|
||||
.modereg1 = 0x0000000c,
|
||||
.autoref_params = 0x0015005d,
|
||||
.pdn = 0x722762c6,
|
||||
.rnkcfg = 0x00006061,
|
||||
.casdllupdatectrl = 0x03030305,
|
||||
.dqsdllupdatectrl = 0x00030005,
|
||||
.rdsdllctrl_step2 = 0x00ff0002,
|
||||
.wrdqdqssdllctrl_step2 = 0xff000002,
|
||||
.cawrlvlsdllcode = 0x00ff01ff,
|
||||
.dlllocktim = 0x00c801f4,
|
||||
.rdwrdqcaltiming_f0 = 0x01060508,
|
||||
.rdwrdqcalseglen_f0 = 0x0d0b1313,
|
||||
.rdwrdqcaltiming_f1 = 0x01060305,
|
||||
.rdwrdqcalseglen_f1 = 0x09070d0d,
|
||||
.rdwrdqcaltiming_f3 = 0x01060308,
|
||||
.rddqcalpatprbs4i = 0x55553c5a,
|
||||
.wrdqcalpatprbs4i = 0x00003c5a,
|
||||
.maxrddqssdllmulfactor = 0x00a00d14,
|
||||
.maxwrdqssdllmulfactor = 0xa0a00d0d,
|
||||
.dllupdtctrl1 = 0x80000080,
|
||||
.dllupdtintvl = 0x10200020,
|
||||
.dcccontrol = 0x10050b27,
|
||||
.cbdrivestr = 0x77838317,
|
||||
.cbioctl = 0x0002000b,
|
||||
.ckdrivestr = 0x77838317,
|
||||
.ckioctl = 0x0000000f,
|
||||
.b0drivestr = 0x77838317,
|
||||
.b0ioctl = 0x7160000f,
|
||||
.b0odt = 0x01c00333,
|
||||
.b0odtctrl = 0x00000007,
|
||||
.b1drivestr = 0x77838317,
|
||||
.b1odtctrl = 0x00000007,
|
||||
.b1ioctl = 0x7160000f,
|
||||
.b1odt = 0x01c00333,
|
||||
.dqs0drivestr = 0x77838317,
|
||||
.dqs0ioctl = 0x7160000f,
|
||||
.dqs0odt = 0x01c00333,
|
||||
.dqs0zdetbiasen = 0x0007082a,
|
||||
.dqs0odtctrl = 0x00000007,
|
||||
.dqs1drivestr = 0x77838317,
|
||||
.dqs1ioctl = 0x7160000f,
|
||||
.dqs1odt = 0x01c00333,
|
||||
.dqs1zdetbiasen = 0x0007082a,
|
||||
.dqs1odtctrl = 0x00000007,
|
||||
.zcalfsm1 = 0x00887f7f,
|
||||
.zcalfsm0 = 0x000f031b,
|
||||
.spare0 = 0x00000016,
|
||||
.hwrddqcaltvref = 0x08080808,
|
||||
.hwwrdqcaltvref = 0x323286c8,
|
||||
.arefparam = 0x08012019,
|
||||
.autoref_params2 = 0x0017005d,
|
||||
.odtszqc = 0x00001000,
|
||||
.longsr = 0x01012008,
|
||||
.freqchngctl_step3 = 0x00010000,
|
||||
.mr3cmd = 0xf3,
|
||||
.mr13cmd = 0x18,
|
||||
.addrcfg = 0x00030201,
|
||||
.chnldec = 0x00050220,
|
||||
// steps 7-14 are skipped for FPGA since only freq used is 50 MHz
|
||||
// <rdar://problem/19339246> Cayman: Implement stesp 7-14 of the memory init sequence (only used on silicon)
|
||||
// .mr3cmd_step11 = 0xb2,
|
||||
.mr13cmd_step15 = 0x50,
|
||||
.freqchngctl_step15 = 0x00009999,
|
||||
.rdsdllctrl_step15 = 0x00140004,
|
||||
.odtszqc2 = 0xc0001000,
|
||||
.qbren_step16 = 0x0000000f,
|
||||
.b0dyniselasrtime = 0x00001c25,
|
||||
.b0dynisel = 0x00000003,
|
||||
.b1dynisel = 0x00000003,
|
||||
.qbrparam = 0x00001070,
|
||||
.qbren = 0x0000000f,
|
||||
.mccgen = 0x00100124,
|
||||
.caampclk = 0x8a000000,
|
||||
.dqampclk = 0x80000000,
|
||||
.pwrmngten = 0x00000033,
|
||||
.odtszqc3 = 0xc0003320,
|
||||
|
||||
.freq = {
|
||||
{ // 1600MHz
|
||||
.clk_period = CLK_PERIOD_1600,
|
||||
.freqchngctl = {0x18cd104d, 0x110c110e, 0xa303440b, 0xde012d02, 0x00000416},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.lat = 0x00113387,
|
||||
.phyrdwrtim = 0x00060d0c,
|
||||
.caspch = 0x63e2080f,
|
||||
.act = 0x2008110f,
|
||||
.autoref = 0x489000a0,
|
||||
.selfref = 0xa0096012,
|
||||
.pdn = 0x00000076,
|
||||
.derate = 0x4d05a910,
|
||||
.lat2 = 0x00123387,
|
||||
.tat = 0x01412222,
|
||||
.mifqmaxctrl = 0x00000100,
|
||||
.cavref = 0x00000003,
|
||||
.dqvref = 0x00c00000,
|
||||
.dqdficaltiming = 0x04060604,
|
||||
.rddqcalwindow = 0x00f801d1,
|
||||
.wrdqcalwindow = 0x012f0360,
|
||||
.rdcapcfg = 0x00000810,
|
||||
.autoref2 = 0x48900092,
|
||||
},
|
||||
{ // 1066MHz
|
||||
.freqchngctl = {0x18cd104d, 0x110c110e, 0xd303220b, 0xbe011b02, 0x00000216},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.lat = 0x001022c5,
|
||||
.phyrdwrtim = 0x00040c09,
|
||||
.caspch = 0x4297060a,
|
||||
.act = 0x16060c0a,
|
||||
.autoref = 0x3060006b,
|
||||
.selfref = 0x6b064012,
|
||||
.pdn = 0x00000054,
|
||||
.derate = 0x34b3760b,
|
||||
.lat2 = 0x001122c5,
|
||||
.tat = 0x01312222,
|
||||
.cavref = 0x00000003,
|
||||
.dqvref = 0x00c00000,
|
||||
.cadficaltiming = 0x04060604,
|
||||
.dqdficaltiming = 0x04060604,
|
||||
.rddqcalwindow = 0x00f801d1,
|
||||
.wrdqcalwindow = 0x012f0360,
|
||||
.rdcapcfg = 0x2000070c,
|
||||
.autoref2 = 0x30600061,
|
||||
},
|
||||
{ // 200MHz
|
||||
.freqchngctl = {0x18cd104d, 0x590c590e, 0xf303000b, 0x8e010002, 0x00000016},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.phyrdwrtim = 0x00010b01,
|
||||
.caspch = 0x40c50402,
|
||||
.act = 0x04020302,
|
||||
.autoref = 0x09120014,
|
||||
.selfref = 0x28013012,
|
||||
.pdn = 0x00000033,
|
||||
.derate = 0x0c212142,
|
||||
.lat2 = 0x001110c2,
|
||||
.tat = 0x01212222,
|
||||
.cavref = 0x00000003,
|
||||
.dqvref = 0x00000000,
|
||||
.cadficaltiming = 0x04060604,
|
||||
.dqdficaltiming = 0x04060604,
|
||||
.rdcapcfg = 0x40000406,
|
||||
.autoref2 = 0x09120013,
|
||||
},
|
||||
{ // 50MHz
|
||||
.freqchngctl = {0x18cd104d, 0x590c590e, 0xf303000b, 0x8e010002, 0x00000016},
|
||||
.freqchngtim = 0x000c1108,
|
||||
.phyrdwrtim = 0x00010901,
|
||||
.caspch = 0x40c20402,
|
||||
.act = 0x02020404,
|
||||
.autoref = 0x03050005,
|
||||
.selfref = 0x28006012,
|
||||
.pdn = 0x00000033,
|
||||
.derate = 0x10412082,
|
||||
.lat2 = 0x001110c2,
|
||||
.tat = 0x01212222,
|
||||
.mifqmaxctrl = 0x00000001,
|
||||
.cavref = 0x00000003,
|
||||
.dqvref = 0x00000000,
|
||||
.cadficaltiming = 0x02060602,
|
||||
.dqdficaltiming = 0x02060602,
|
||||
.rdcapcfg = 0x60000406,
|
||||
.autoref2 = 0x03050005,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
#define BIT32_MASKFULL (0xFFFFFFFF)
|
||||
#define BIT32_MASK(_n) (BIT32_MASKFULL >> (32 - (_n)))
|
||||
#define BIT32_MASK_VAL(_h,_l,_d) (((_d) & BIT32_MASK((_h) - (_l) + 1)) << (_l))
|
||||
#define BIT32_MASK_HI_LO(_h,_l) BIT32_MASK_VAL(_h,_l,BIT32_MASKFULL)
|
||||
#define DCS_MASK_VAL(_h,_l,_d) BIT32_MASK_HI_LO(_h,_l) , BIT32_MASK_VAL(_h,_l,_d)
|
||||
|
||||
// DCS Tunables for t8010
|
||||
// Tunables Spec versions:
|
||||
// MCU: https://seg-docs.ecs.apple.com/projects/cayman//release/UserManual/tunables/MCU.html dated 2015/02/09
|
||||
// Notes:
|
||||
// All channels are tuned in exactly the same way
|
||||
// Registers with all fields' tunable values matching the reset value omitted
|
||||
const dcs_tunable_t dcs_tunables[] = {
|
||||
|
||||
{ rDCS_MCU_CLKGATE, DCS_MASK_VAL(19, 16, 0x1) },
|
||||
{ rDCS_MCU_CLKGATE, DCS_MASK_VAL(15, 12, 0x3) },
|
||||
{ rDCS_MCU_CLKGATE, DCS_MASK_VAL( 8, 7, 0x2) },
|
||||
{ rDCS_MCU_CLKGATE, DCS_MASK_VAL( 6, 4, 0x1) },
|
||||
|
||||
{ rDCS_MCU_AMCCLKPWRGATE, DCS_MASK_VAL(12, 12, 0x1) },
|
||||
{ rDCS_MCU_AMCCLKPWRGATE, DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(31, 24, 0xff) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(20, 20, 0x0) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(16, 16, 0x1) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL(12, 12, 0x0) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
{ rDCS_MCU_PSQRQCTL0, DCS_MASK_VAL( 4, 4, 0x1) },
|
||||
|
||||
{ rDCS_MCU_PSQRQTIMER0, DCS_MASK_VAL(27, 16, 0x014) },
|
||||
{ rDCS_MCU_PSQRQTIMER0, DCS_MASK_VAL(11, 0, 0x040) },
|
||||
|
||||
{ rDCS_MCU_PSQRQTIMER1, DCS_MASK_VAL(27, 16, 0x00f) },
|
||||
{ rDCS_MCU_PSQRQTIMER1, DCS_MASK_VAL(11, 0, 0x040) },
|
||||
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL(28, 24, 0x04) },
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL(20, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL(12, 8, 0x04) },
|
||||
{ rDCS_MCU_PSQRQBRST, DCS_MASK_VAL( 4, 0, 0x10) },
|
||||
|
||||
{ rDCS_MCU_PSQRQSCHCRD, DCS_MASK_VAL(23, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQRQSCHCRD, DCS_MASK_VAL(15, 8, 0x14) },
|
||||
{ rDCS_MCU_PSQRQSCHCRD, DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_PSQWQ_CTL(0), DCS_MASK_VAL(16, 16, 0x1) },
|
||||
{ rDCS_MCU_PSQWQ_CTL(0), DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
|
||||
// part of init sequence, so have to apply tunables even if same as reset values
|
||||
{ rDCS_MCU_PSQWQ_CTL(1), DCS_MASK_VAL(31, 16, 0x01e6) },
|
||||
{ rDCS_MCU_PSQWQ_CTL(1), DCS_MASK_VAL(15, 0, 0x02da) },
|
||||
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL(28, 24, 0x04) },
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL(20, 16, 0x08) },
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL(12, 8, 0x04) },
|
||||
{ rDCS_MCU_PSQWQBRST, DCS_MASK_VAL( 4, 0, 0x10) },
|
||||
|
||||
{ rDCS_MCU_PSQWQSCHCRD, DCS_MASK_VAL(23, 16, 0x10) },
|
||||
{ rDCS_MCU_PSQWQSCHCRD, DCS_MASK_VAL(15, 8, 0x14) },
|
||||
{ rDCS_MCU_PSQWQSCHCRD, DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_QOSLLT, DCS_MASK_VAL( 8, 8, 0x1) },
|
||||
{ rDCS_MCU_QOSLLT, DCS_MASK_VAL( 4, 0, 0x1f) },
|
||||
|
||||
{ rDCS_MCU_SBQOSUPGCTL, DCS_MASK_VAL(31, 31, 0x1) },
|
||||
{ rDCS_MCU_SBQOSUPGCTL, DCS_MASK_VAL(15, 8, 0x6f) },
|
||||
{ rDCS_MCU_SBQOSUPGCTL, DCS_MASK_VAL( 7, 0, 0x6e) },
|
||||
|
||||
// DRAM Cfg
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(0), DCS_MASK_VAL(31, 16, 0x0300) },
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(0), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(1), DCS_MASK_VAL(31, 16, 0x0200) },
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(1), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(2), DCS_MASK_VAL(31, 16, 0x0180) },
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(2), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(3), DCS_MASK_VAL(31, 16, 0x0017) },
|
||||
{ rDCS_MCU_PWRMNGTPARAM_FREQ(3), DCS_MASK_VAL( 7, 0, 0x00) },
|
||||
|
||||
// Alternate End Marker
|
||||
// { 0, 0, 0 }
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_ERROR_HANDLER_H
|
||||
#define __PLATFORM_ERROR_HANDLER_H
|
||||
|
||||
void platform_enable_error_handler();
|
||||
|
||||
#endif // __PLATFORM_ERROR_HANDLER_H
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_GPIODEF_H
|
||||
#define __PLATFORM_GPIODEF_H
|
||||
|
||||
#include <platform.h>
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#if WITH_TARGET_CONFIG
|
||||
# include <target/gpiodef.h>
|
||||
#endif
|
||||
|
||||
#include SUB_PLATFORM_HEADER(gpiodef)
|
||||
|
||||
#endif /* ! __PLATFORM_GPIODEF_H */
|
||||
@@ -0,0 +1,74 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_GPIODEF_t8010_H
|
||||
#define __PLATFORM_GPIODEF_t8010_H
|
||||
|
||||
#if !SUB_PLATFORM_T8010
|
||||
#error "Only include for t8010 platform"
|
||||
#endif
|
||||
|
||||
/* t8010 specific gpio -> pin mappings - Cayman I/O Spreadsheet v2.05 */
|
||||
|
||||
/* Boot configuration pins */
|
||||
#define GPIO_BOOT_CONFIG0 GPIO(167)
|
||||
#define GPIO_BOOT_CONFIG1 GPIO(204)
|
||||
#define GPIO_BOOT_CONFIG2 GPIO(207)
|
||||
|
||||
/* Boot configuration pin encodings */
|
||||
#define BOOT_CONFIG_SPI0 (0)
|
||||
#define BOOT_CONFIG_SPI0_TEST (1)
|
||||
#define BOOT_CONFIG_NVME0_X2 (2)
|
||||
#define BOOT_CONFIG_NVME0_X2_TEST (3)
|
||||
#define BOOT_CONFIG_NVME0_X1 (4)
|
||||
#define BOOT_CONFIG_NVME0_X1_TEST (5)
|
||||
#define BOOT_CONFIG_SLOW_SPI0_TEST (6)
|
||||
#define BOOT_CONFIG_FAST_SPI0_TEST (7)
|
||||
|
||||
#define GPIO_REQUEST_DFU1 GPIO(179) // Formerly HOLD_KEY
|
||||
#define GPIO_REQUEST_DFU2 GPIO(180) // Formerly MENU_KEY
|
||||
#define GPIO_FORCE_DFU GPIO(205) // FORCE_DFU
|
||||
#define GPIO_DFU_STATUS GPIO(206) // DFU_STATUS
|
||||
|
||||
#define SPI_NOR0 (0)
|
||||
|
||||
#define GPIO_SPI0_SCLK GPIO(184)
|
||||
#define GPIO_SPI0_MOSI GPIO(185)
|
||||
#define GPIO_SPI0_MISO GPIO(186)
|
||||
#define GPIO_SPI0_SSIN GPIO(187)
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define GPIO_SPI0_CS GPIO(GPIO_PAD_SPI, 0)
|
||||
#else
|
||||
#define GPIO_SPI0_CS GPIO(187) // Alias of GPIO_SPI0_SSIN
|
||||
#endif
|
||||
|
||||
#define GPIO_IIC0_SCL GPIO(197)
|
||||
#define GPIO_IIC0_SDA GPIO(196)
|
||||
#define GPIO_IIC1_SCL GPIO(40)
|
||||
#define GPIO_IIC1_SDA GPIO(39)
|
||||
#define GPIO_IIC2_SCL GPIO(133)
|
||||
#define GPIO_IIC2_SDA GPIO(132)
|
||||
#define GPIO_IIC3_SCL GPIO(42)
|
||||
#define GPIO_IIC3_SDA GPIO(41)
|
||||
|
||||
#define GPIO_PCIE0_PERST GPIO(12)
|
||||
#define GPIO_PCIE1_PERST GPIO(13)
|
||||
#define GPIO_PCIE2_PERST GPIO(14)
|
||||
#define GPIO_PCIE3_PERST GPIO(15)
|
||||
#define GPIO_PCIE0_CLKREQ GPIO(16)
|
||||
#define GPIO_PCIE1_CLKREQ GPIO(17)
|
||||
#define GPIO_PCIE2_CLKREQ GPIO(18)
|
||||
#define GPIO_PCIE3_CLKREQ GPIO(19)
|
||||
|
||||
#define GPIO_NAND_SYS_CLK GPIO(10)
|
||||
|
||||
#endif /* ! __PLATFORM_GPIODEF_t8010_H */
|
||||
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_IMAGE_DEVICES_H
|
||||
#define __PLATFORM_IMAGE_DEVICES_H
|
||||
|
||||
static const struct image_device platform_image_devices[] = {
|
||||
#if defined(WITH_HW_ASP)
|
||||
{ "asp_fw", 0x00000 },
|
||||
#elif defined(WITH_ANC_FIRMWARE)
|
||||
{ "anc_firmware", 0x00000 },
|
||||
#endif
|
||||
#if defined(WITH_NVME)
|
||||
{ "nvme_firmware0", 0x0000 },
|
||||
#endif
|
||||
#if !defined(WITH_HW_ASP) && !defined(WITH_ANC_FIRMWARE) && !defined(WITH_NVME)
|
||||
{ "nor0", 0x00000 },
|
||||
#endif
|
||||
};
|
||||
|
||||
#if WITH_SYSCFG
|
||||
static const struct image_device platform_syscfg_devices[] = {
|
||||
#if defined(WITH_NAND_BOOT)
|
||||
{ "nand_syscfg", 0x00000 },
|
||||
#endif
|
||||
#if defined(WITH_NVME)
|
||||
{ "nvme_syscfg0", 0x0000 },
|
||||
#endif
|
||||
#if !defined(WITH_NAND_BOOT) && !defined(WITH_NVME)
|
||||
{ "nor0", 0x00000 },
|
||||
#endif
|
||||
};
|
||||
#endif /* WITH_SYSCFG */
|
||||
|
||||
#endif /* ! __PLATFORM_IMAGE_DEVICES_H */
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_MEMCONFIG_H
|
||||
#define __PLATFORM_MEMCONFIG_H
|
||||
|
||||
/* T8010 SoC Mem Pin Configuration */
|
||||
|
||||
static const gpio_t memory_interface_gpios[] = {
|
||||
/* Not needed */
|
||||
};
|
||||
#endif /* ! __PLATFORM_MEMCONFIG_H */
|
||||
@@ -0,0 +1,258 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_MEMMAP_H
|
||||
#define __PLATFORM_MEMMAP_H
|
||||
|
||||
// <rdar://problem/18127631>Remove memory map hack in s8000's memmap.h
|
||||
//#include <platform/memmap_defaults.h>
|
||||
#define DEFAULT_LOAD_ADDRESS (INSECURE_MEMORY_BASE)
|
||||
#define DEFAULT_LOAD_SIZE (0x08000000ULL) // 128 MB instead of 64 MB in memmap_defaults.h
|
||||
#define DEFAULT_KERNEL_ADDRESS (DEFAULT_LOAD_ADDRESS + DEFAULT_LOAD_SIZE)
|
||||
#define DEFAULT_KERNEL_SIZE (0x03F00000ULL)
|
||||
#define DEFAULT_DEVICETREE_ADDRESS (DEFAULT_KERNEL_ADDRESS + DEFAULT_KERNEL_SIZE)
|
||||
#define DEFAULT_DEVICETREE_SIZE (0x00100000ULL)
|
||||
#define DEFAULT_RAMDISK_ADDRESS (DEFAULT_DEVICETREE_ADDRESS + DEFAULT_DEVICETREE_SIZE)
|
||||
#define DEFAULT_RAMDISK_SIZE (0x04000000ULL)
|
||||
#define DEFAULT_FREE_ADDRESS (DEFAULT_RAMDISK_ADDRESS + DEFAULT_RAMDISK_SIZE)
|
||||
|
||||
/* T8010 specific memory map */
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
// 0x800000000 + dram_size -------------------------------
|
||||
// | NVMe (12MiB) |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | Consistent Debug (16KiB) |
|
||||
// |-----------------------------|
|
||||
// | Sleep Token Buffer (16KiB) |
|
||||
// |-----------------------------|
|
||||
// | DRAM Config Sequence (16KiB)|
|
||||
// |-----------------------------|
|
||||
// | Panic (512KiB) |
|
||||
// |-----------------------------|
|
||||
// | Display |
|
||||
// | (Framebuffer + scratch) |
|
||||
// | |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | |
|
||||
// | iBoot (Heap) |
|
||||
// | (Variable size depending |
|
||||
// (Cayman) | on DISPLAY_SIZE) |
|
||||
// 0x870180000 --> |-----------------------------|
|
||||
// | iBoot (Trampoline) |
|
||||
// (Cayman) | (BOOT_TRAMPOLINE_SIZE) |
|
||||
// 0x87017C000 --> |-----------------------------|
|
||||
// | iBoot (Stacks) |
|
||||
// (Cayman) | (STACKS_SIZE) |
|
||||
// 0x870178000 --> |-----------------------------|
|
||||
// | iBoot (Page Tables) |
|
||||
// (Cayman) | (PAGE_TABLES_SIZE) |
|
||||
// 0x870100000 --> |-----------------------------|
|
||||
// | iBoot (Text + Data) |
|
||||
// (Cayman) | (TEXT_FOOTPRINT) |
|
||||
// 0x870000000 --> |-----------------------------| <-- 0x800000000 + dram_size - 256MB
|
||||
// | |
|
||||
// | Unused |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | |
|
||||
// | (Ramdisk) |
|
||||
// | (Kernel + DeviceTree) |
|
||||
// | Secure memory |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | |
|
||||
// | Load region / |
|
||||
// | Insecure Memory |
|
||||
// | (overlaps with TZ0) | |-----------------------------|
|
||||
// | | | TZ0 (varies) |
|
||||
// 0x800000000 --> ------------------------------- -------------------------------
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define SDRAM_BASE (0x800000000ULL)
|
||||
#define SDRAM_BANK_LEN (SDRAM_LEN)
|
||||
#define SDRAM_BANK_COUNT (1)
|
||||
#define SDRAM_END (SDRAM_BASE + SDRAM_LEN)
|
||||
|
||||
#define VROM_BASE (0x100000000ULL)
|
||||
#define VROM_BANK_LEN (0x002000000ULL)
|
||||
#define VROM_RSVD (0x00080000ULL) // 512 KiB reserved for SecureROM testing
|
||||
#define SRAM_BASE (0x180000000ULL)
|
||||
#define SRAM_LEN (0x000200000ULL) // 2 MiB
|
||||
#define SRAM_BANK_LEN (SRAM_LEN) // SRAM should be in a 32 MB decode region
|
||||
#define SRAM_BANK_COUNT (1)
|
||||
#define SRAM_END (SRAM_BASE + SRAM_LEN)
|
||||
|
||||
#define IO_BASE (0x200000000ULL)
|
||||
#define IO_SIZE (0x020000000ULL)
|
||||
|
||||
#define PCI_REG_BASE (0x600000000ULL)
|
||||
#define PCI_REG_LEN (0x00C000000ULL)
|
||||
#define PCI_CONFIG_BASE (0x610000000ULL)
|
||||
#define PCI_CONFIG_LEN (0x10000000ULL)
|
||||
#define PCI_32BIT_BASE (0x7C0000000ULL)
|
||||
#define PCI_32BIT_LEN (0x002000000ULL) // 32 MiB fits nicely into a 32 MiB L2 MMU block
|
||||
|
||||
#define SECUREROM_LOAD_ADDRESS (VROM_BASE)
|
||||
|
||||
/* reserved for ASP/NVMe */
|
||||
// NOTE ASP_SIZE is now defined by the platform or target makefile.
|
||||
#define ASP_BASE (SDRAM_END - ASP_SIZE)
|
||||
|
||||
#define CONSISTENT_DEBUG_SIZE (0x00004000ULL)
|
||||
#define CONSISTENT_DEBUG_BASE (ASP_BASE - CONSISTENT_DEBUG_SIZE)
|
||||
|
||||
/* reserved area for sleep token info */
|
||||
#define SLEEP_TOKEN_BUFFER_SIZE (0x00004000ULL)
|
||||
#define SLEEP_TOKEN_BUFFER_BASE (CONSISTENT_DEBUG_BASE - SLEEP_TOKEN_BUFFER_SIZE)
|
||||
|
||||
/* reserved area for config sequence region */
|
||||
#define DRAM_CONFIG_SEQ_SIZE (0x00004000ULL)
|
||||
#define DRAM_CONFIG_SEQ_BASE (SLEEP_TOKEN_BUFFER_BASE - DRAM_CONFIG_SEQ_SIZE)
|
||||
|
||||
/* reserved area for panic info */
|
||||
#define PANIC_SIZE (0x00080000ULL)
|
||||
#define PANIC_BASE (DRAM_CONFIG_SEQ_BASE - PANIC_SIZE)
|
||||
|
||||
/* reserved area for display */
|
||||
// DISPLAY_SIZE comes from platform's rules.mk
|
||||
#define DISPLAY_BASE (PANIC_BASE - DISPLAY_SIZE)
|
||||
|
||||
// Reserved for TZ0/SEP
|
||||
// TZ0_SIZE is defined by the platform or target makefile
|
||||
#define TZ0_BASE (SDRAM_BASE)
|
||||
|
||||
/* where to stick heap and insecure memory */
|
||||
#if APPLICATION_SECUREROM
|
||||
|
||||
// SecureROM SRAM memory map
|
||||
//
|
||||
// ROM Testing 0x000000 - 0x07FFFF ( 512 KiB)
|
||||
// Data 0x080000 - 0x09FFFF ( 128 KiB)
|
||||
// Page Tables 0x0A0000 - 0x0A7FFF ( 32 KiB)
|
||||
// Stacks 0x0A8000 - 0x0ABFFF ( 16 KiB)
|
||||
// Boot Trampoline 0x0AC000 - 0x0AFFFF ( 16 KiB)
|
||||
// DFU Region 0x0B0000 - 0x1AFFFF (1024 KiB)
|
||||
// Heap 0x1B0000 - 0x1FFFFF ( 320 KiB)
|
||||
|
||||
// DATA_BASE comes from platform/t8010/rules.mk
|
||||
#define DATA_SIZE (0x00020000ULL)
|
||||
|
||||
#define PAGE_TABLES_BASE (DATA_BASE + DATA_SIZE)
|
||||
#define PAGE_TABLES_SIZE (0x00008000ULL)
|
||||
|
||||
#define STACKS_BASE (PAGE_TABLES_BASE + PAGE_TABLES_SIZE)
|
||||
#define STACKS_SIZE (0x00004000ULL)
|
||||
|
||||
#define BOOT_TRAMPOLINE_BASE (STACKS_BASE + STACKS_SIZE)
|
||||
#define BOOT_TRAMPOLINE_SIZE (0x00004000ULL)
|
||||
|
||||
#define INSECURE_MEMORY_BASE (BOOT_TRAMPOLINE_BASE + BOOT_TRAMPOLINE_SIZE)
|
||||
#define INSECURE_MEMORY_SIZE (0x00100000ULL)
|
||||
|
||||
#define HEAP_BASE (INSECURE_MEMORY_BASE + INSECURE_MEMORY_SIZE)
|
||||
#define HEAP_END (SRAM_END)
|
||||
#define HEAP_SIZE (HEAP_END - HEAP_BASE)
|
||||
#define HEAP_GUARD (HEAP_END)
|
||||
|
||||
#endif /* APPLICATION_SECUREROM */
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
|
||||
#if WITH_DFU_MODE
|
||||
|
||||
// iBSS/LLB SRAM memory map
|
||||
//
|
||||
// ROM Testing 0x000000 - 0x07FFFF ( 512 KiB)
|
||||
// Page Tables 0x080000 - 0x097FFF ( 96 KiB)
|
||||
// Stacks 0x098000 - 0x09BFFF ( 16 KiB)
|
||||
// <unused> 0x09C000 - 0x0AFFFF ( 96 KiB)
|
||||
// Code/Data 0x0B0000 - 0x1AFFFF (1024 KiB)
|
||||
// Boot Trampoline 0x1B0000 - 0x1B3FFF ( 16 KiB)
|
||||
// Heap 0x1B4000 - 0x1FFFFF ( 304 KiB)
|
||||
|
||||
#define PAGE_TABLES_BASE (SRAM_BASE + VROM_RSVD)
|
||||
#define PAGE_TABLES_SIZE (0x0018000ULL)
|
||||
|
||||
#define STACKS_BASE (PAGE_TABLES_BASE + PAGE_TABLES_SIZE)
|
||||
#define STACKS_SIZE (EXCEPTION_STACK_SIZE + BOOTSTRAP_STACK_SIZE + INTERRUPT_STACK_SIZE)
|
||||
|
||||
#define CODE_DATA_END (TEXT_BASE + TEXT_FOOTPRINT)
|
||||
|
||||
#define BOOT_TRAMPOLINE_BASE (CODE_DATA_END)
|
||||
#define BOOT_TRAMPOLINE_SIZE (PAGE_SIZE)
|
||||
|
||||
#define HEAP_BASE (BOOT_TRAMPOLINE_BASE + BOOT_TRAMPOLINE_SIZE)
|
||||
#define HEAP_END (SRAM_END)
|
||||
#define HEAP_SIZE (HEAP_END - HEAP_BASE)
|
||||
#define HEAP_GUARD (HEAP_END)
|
||||
|
||||
// Reserved area for iBoot
|
||||
#define IBOOT_BASE (SDRAM_END - SDRAM_LOAD_OFFSET)
|
||||
#define IBOOT_SIZE (0x01400000ULL)
|
||||
|
||||
#define INSECURE_MEMORY_BASE (IBOOT_BASE)
|
||||
#define INSECURE_MEMORY_SIZE (IBOOT_SIZE)
|
||||
|
||||
#else /* !WITH_DFU_MODE */
|
||||
|
||||
// iBoot/iBEC SDRAM memory map
|
||||
|
||||
// SDRAM memory map will usually look like the following for T8010:
|
||||
//
|
||||
// iBoot Text 0x870000000 - 0x8700FFFFF ( 1 MiB)
|
||||
// Page Tables 0x870100000 - 0x870177FFF (480 KiB)
|
||||
// Stacks 0x870178000 - 0x87017BFFF ( 16 KiB)
|
||||
// Boot trampoline 0x87017C000 - 0x87017FFFF ( 16 KiB)
|
||||
// Heap 0x870180000 - (DISPLAY_BASE - 1 page)
|
||||
// Guard (DISPLAY_BASE - 1 page) - DISPLAY_BASE
|
||||
|
||||
/* reserved area for iBoot */
|
||||
#define IBOOT_BASE (TEXT_BASE)
|
||||
#define IBOOT_SIZE (HEAP_END - IBOOT_BASE)
|
||||
|
||||
#define CODE_DATA_END (IBOOT_BASE + IBOOT_SIZE)
|
||||
|
||||
#if (IBOOT_BASE != (SDRAM_END - SDRAM_LOAD_OFFSET))
|
||||
#error "Memory map configuration error"
|
||||
#endif
|
||||
|
||||
#define PAGE_TABLES_BASE (IBOOT_BASE + TEXT_FOOTPRINT)
|
||||
#define PAGE_TABLES_SIZE (0x00078000ULL)
|
||||
#define STACKS_BASE (PAGE_TABLES_BASE + PAGE_TABLES_SIZE)
|
||||
#define STACKS_SIZE (EXCEPTION_STACK_SIZE + BOOTSTRAP_STACK_SIZE + INTERRUPT_STACK_SIZE)
|
||||
#define BOOT_TRAMPOLINE_BASE (STACKS_BASE + STACKS_SIZE)
|
||||
#define BOOT_TRAMPOLINE_SIZE (PAGE_SIZE)
|
||||
|
||||
#define HEAP_BASE (BOOT_TRAMPOLINE_BASE + BOOT_TRAMPOLINE_SIZE)
|
||||
#define HEAP_SIZE (DISPLAY_BASE - HEAP_BASE - PAGE_SIZE)
|
||||
#define HEAP_END (HEAP_BASE + HEAP_SIZE)
|
||||
#define HEAP_GUARD (HEAP_END)
|
||||
#if (HEAP_GUARD != (DISPLAY_BASE - PAGE_SIZE))
|
||||
#error "Memory map configuration error"
|
||||
#endif
|
||||
|
||||
#define INSECURE_MEMORY_BASE (SDRAM_BASE)
|
||||
#define INSECURE_MEMORY_SIZE (DEFAULT_LOAD_SIZE)
|
||||
|
||||
#define SECURE_MEMORY_BASE (INSECURE_MEMORY_BASE + INSECURE_MEMORY_SIZE)
|
||||
#define SECURE_MEMORY_SIZE (DEFAULT_FREE_ADDRESS - SECURE_MEMORY_BASE)
|
||||
|
||||
/* unused area */
|
||||
#define UNUSED_MEMORY_BASE (SECURE_MEMORY_BASE + SECURE_MEMORY_SIZE)
|
||||
#define UNUSED_MEMORY_SIZE (IBOOT_BASE - UNUSED_MEMORY_BASE)
|
||||
|
||||
#endif /* !WITH_DFU_MODE */
|
||||
|
||||
#endif /* APPLICATION_IBOOT */
|
||||
|
||||
#endif /* ! __PLATFORM_MEMMAP_H */
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_PCIMAP_H
|
||||
#define __PLATFORM_PCIMAP_H
|
||||
|
||||
/* T8010 specific bus/device/function and PCI base address map */
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define PCIE_PORT0_MEMORY_BASE (PCIE_MEMORY_BASE_ADDR)
|
||||
#define PCIE_PORT0_MEMORY_LEN (0x00100000ULL)
|
||||
|
||||
#define NVME0_PCI_BDF (PCI_BDF(1, 0, 0))
|
||||
#define NVME0_BASE_ADDR (PCIE_PORT0_MEMORY_BASE)
|
||||
#define NVME0_SIZE (0x00002000)
|
||||
#define NVME0_DART_ID (PCIE_PORT0_DART_ID)
|
||||
|
||||
|
||||
#endif /* ! __PLATFORM_PCIMAP_H */
|
||||
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#include SUB_PLATFORM_HEADER(pinconfig)
|
||||
|
||||
@@ -0,0 +1,398 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: cayman io list. ver 3.13
|
||||
I/O Spreadsheet tracker: <rdar://problem/20286828> H9: Update SecureROM pin configuration to I/O spreadsheet v3.13
|
||||
Conversion command: csvtopinconfig.py --rom --header --soc h9p --pupd-column 'Default pull-up/pull-down' --netname-column D1x_Net --copyright 2015 --radar '<rdar://problem/20286828> H9: Update SecureROM pin configuration to I/O spreadsheet v3.13' <filename>
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_PINCONFIG_H
|
||||
#define __PLATFORM_PINCONFIG_H
|
||||
|
||||
static const uint32_t gpio_default_cfg_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 0 : I2S0_MCK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 1 : I2S0_BCLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 2 : I2S0_LRCK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 3 : I2S0_DIN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 4 : I2S0_DOUT ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 5 : I2S2_MCK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 6 : I2S2_BCLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 7 : I2S2_LRCK ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 8 : I2S2_DIN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 9 : I2S2_DOUT ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 10 : NAND_SYS_CLK -> AP_TO_NAND_SYS_CLK_R
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 11 : S3E_RESETN -> AP_TO_NAND_RESET_L
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 12 : PCIE_PERST0_N -> PCIE_AP_TO_NAND_RESET_L
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 13 : PCIE_PERST1_N ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 14 : PCIE_PERST2_N ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 15 : PCIE_PERST3_N ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 16 : PCIE_CLKREQ0_N -> PCIE_NAND_BI_AP_CLKREQ_L
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 17 : PCIE_CLKREQ1_N ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 18 : PCIE_CLKREQ2_N ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 19 : PCIE_CLKREQ3_N ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 20 : GPIO[0] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 21 : GPIO[1] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 22 : GPIO[2] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 23 : GPIO[3] ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 24 : GPIO[4] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 25 : GPIO[5] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 26 : GPIO[6] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 27 : GPIO[7] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 28 : GPIO[8] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 29 : GPIO[9] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 30 : GPIO[10] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 31 : GPIO[11] ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 32 : CLK32K_OUT ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 33 : DWI_DO ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 34 : DWI_CLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 35 : PMU_MOSI ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 36 : PMU_MISO ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 37 : PMU_SCLK ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 38 : GPIO[12] ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 39 : I2C1_SDA ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 40 : I2C1_SCL ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 41 : I2C3_SDA ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 42 : I2C3_SCL ->
|
||||
CFG_DISABLED, // 43 : SENSOR2_RST ->
|
||||
CFG_DISABLED, // 44 : SENSOR3_RST ->
|
||||
CFG_DISABLED, // 45 : SENSOR4_RST ->
|
||||
CFG_DISABLED, // 46 : SENSOR_INT ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 47 : ISP_I2C3_SDA ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 48 : ISP_I2C3_SCL ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 49 : ISP_I2C2_SDA ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 50 : ISP_I2C2_SCL ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 51 : ISP_I2C1_SDA ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 52 : ISP_I2C1_SCL ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 53 : ISP_I2C0_SDA ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 54 : ISP_I2C0_SCL ->
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 64 : SENSOR0_ISTRB ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 65 : SENSOR0_RST ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 66 : SENSOR0_CLK ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 67 : SENSOR0_XSHUTDOWN ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 68 : SENSOR1_ISTRB ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 69 : SENSOR1_RST ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 70 : SENSOR1_CLK ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 71 : SENSOR1_XSHUTDOWN ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 72 : SENSOR2_CLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 73 : I2S1_MCK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 74 : I2S1_BCLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 75 : I2S1_LRCK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 76 : I2S1_DIN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 77 : I2S1_DOUT ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 78 : SPI2_SCLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 79 : SPI2_MOSI ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 80 : SPI2_MISO ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 81 : SPI2_SSIN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 82 : SPI3_SCLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 83 : SPI3_MOSI ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 84 : SPI3_MISO ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 85 : SPI3_SSIN ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 86 : GPIO[31] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 87 : GPIO[32] ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 88 : GPIO[33] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 89 : GPIO[34] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 90 : GPIO[35] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 91 : GPIO[36] ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 96 : UART1_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 97 : UART1_RXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 98 : UART1_RTSN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 99 : UART1_CTSN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 100 : UART4_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 101 : UART4_RXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 102 : UART4_RTSN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 103 : UART4_CTSN ->
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 128 : SPI1_SCLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 129 : SPI1_MOSI ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 130 : SPI1_MISO ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 131 : SPI1_SSIN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 132 : I2C2_SDA ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 133 : I2C2_SCL ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 134 : UART3_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 135 : UART3_RXD ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 136 : UART3_RTSN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 137 : UART3_CTSN ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 138 : GPIO[29] -> BOARD_ID4
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 139 : GPIO[30] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 140 : GPIO[13] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 141 : GPIO[14] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 142 : GPIO[15] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 143 : DROOP ->
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 144 : SOCHOT ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 145 : TMR32_PWM0 ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 146 : TMR32_PWM1 ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 147 : TMR32_PWM2 ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 148 : UART2_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 149 : UART2_RXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 150 : UART2_RTSN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 151 : UART2_CTSN ->
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 152 : UART7_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 153 : UART7_RXD ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 154 : DP_WAKEUP ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 160 : GPIO[37] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 161 : GPIO[38] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 162 : GPIO[39] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 163 : GPIO[40] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 164 : GPIO[41] ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 165 : GPIO[16] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 166 : GPIO[17] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 167 : GPIO[18] -> BOOT_CONFIG0
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 168 : GPIO[19] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 169 : GPIO[20] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 170 : GPIO[21] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 171 : GPIO[22] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 172 : GPIO[23] ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 173 : UART5_RTXD ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 174 : TST_CLKOUT ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 175 : EDP_HPD ->
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED, // 176 : DISP_TOUCH_BSYNC0 ->
|
||||
CFG_DISABLED, // 177 : DISP_TOUCH_BSYNC1 ->
|
||||
CFG_DISABLED, // 178 : DISP_TOUCH_EB ->
|
||||
CFG_IN, // 179 : REQUEST_DFU1 -> PMU_TO_AP_BUF_BUTTON1
|
||||
CFG_IN, // 180 : REQUEST_DFU2 -> PMU_TO_AP_BUF_BUTTON2
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 181 : SWD_TMS2 ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 182 : SWD_TMS3 ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 183 : GPU_TRIGGER ->
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 184 : SPI0_SCLK -> BOARD_ID0
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 185 : SPI0_MOSI -> BOARD_ID1
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 186 : SPI0_MISO -> BOARD_ID2
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 187 : SPI0_SSIN -> BOARD_ID3
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 192 : UART0_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 193 : UART0_RXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 194 : UART6_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 195 : UART6_RXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 196 : I2C0_SDA ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 197 : I2C0_SCL ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 198 : I2S3_MCK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 199 : I2S3_BCLK ->
|
||||
|
||||
/* Port 25 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 200 : I2S3_LRCK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 201 : I2S3_DOUT ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 202 : I2S3_DIN ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 203 : GPIO[24] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 204 : GPIO[25] -> BOOT_CONFIG1
|
||||
CFG_IN | PULL_DOWN | DRIVE_S4 | SLOW_SLEW, // 205 : GPIO[26] -> FORCE_DFU
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW, // 206 : GPIO[27] -> DFU_STATUS
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 207 : GPIO[28] -> BOOT_CONFIG2
|
||||
};
|
||||
|
||||
static const uint32_t gpio_default_cfg_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 0 : AOP_SPI_SCLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 1 : AOP_SPI_MOSI ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 2 : AOP_SPI_MISO ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 3 : AOP_UART0_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 4 : AOP_UART0_RXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 5 : AOP_UART1_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 6 : AOP_UART1_RXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 7 : AOP_UART2_TXD ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 8 : AOP_UART2_RXD ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 9 : AOP_I2C0_SDA ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 10 : AOP_I2C0_SCL ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 11 : AOP_FUNC[0] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 12 : AOP_FUNC[1] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 13 : AOP_FUNC[2] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 14 : AOP_FUNC[3] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 15 : AOP_FUNC[4] ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 16 : AOP_FUNC[5] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 17 : AOP_FUNC[6] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 18 : AOP_FUNC[7] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 19 : AOP_FUNC[8] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 20 : AOP_FUNC[9] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 21 : AOP_FUNC[10] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 22 : AOP_FUNC[11] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 23 : AOP_FUNC[12] ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 24 : AOP_FUNC[13] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 25 : AOP_FUNC[14] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 26 : AOP_FUNC[15] ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 27 : AOP_SWD_TCK_OUT ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 28 : AOP_SWD_TMS0 ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 29 : AOP_SWD_TMS1 ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 32 : AOP_I2S_DOUT ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 33 : AOP_I2S_BCLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 34 : AOP_I2S_LRCK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 35 : AOP_I2S_DIN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 36 : AOP_I2S_MCK ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 37 : DOCK_CONNECT ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 38 : DOCK_ATTENTION ->
|
||||
CFG_DISABLED, // 39 : AOP_PDM_CLK0 ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED, // 40 : AOP_PDM_DATA0 ->
|
||||
CFG_DISABLED, // 41 : AOP_PDM_DATA1 ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // 64 : XI0 ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 65 : XO0 ->
|
||||
CFG_DISABLED, // 66 : ANALOGMUX_OUT ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 67 : CFSB ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 68 : HOLD_RESET ->
|
||||
CFG_DISABLED, // 69 : TESTMODE ->
|
||||
CFG_DISABLED, // 70 : PACKAGED_N ->
|
||||
CFG_DISABLED, // 71 : CFSB_AOP ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // 72 : COLD_RESETN ->
|
||||
CFG_DISABLED, // 73 : JTAG_TRSTN ->
|
||||
CFG_DISABLED, // 74 : JTAG_SEL ->
|
||||
CFG_DISABLED, // 75 : JTAG_TMS ->
|
||||
CFG_DISABLED, // 76 : JTAG_TDI ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 77 : JTAG_TDO ->
|
||||
CFG_DISABLED, // 78 : JTAG_TCK ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 79 : AOP_DDR_REQ ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 80 : AOP_DDR_RESETN ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 81 : AWAKE_REQ ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 82 : AWAKE_RESETN ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 83 : WDOG ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 84 : RT_CLK32768 ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
};
|
||||
|
||||
|
||||
#endif /* __PLATFORM_PINCONFIG_H */
|
||||
@@ -0,0 +1,135 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __AOP_CONFIG_SEQUENCES_H__
|
||||
#define __AOP_CONFIG_SEQUENCES_H__
|
||||
|
||||
// These structures are valid reconfig commands. They are stitched together in
|
||||
// the platform init.c. For example look at the platform_s2r_aop_to_aop_ddr_post_sequence_insert()
|
||||
// to figure out how the reconfig sequences are stitched together for the transition
|
||||
// from s2r_aop to aop_ddr postamble
|
||||
|
||||
uint32_t s2r_aop_to_aop_ddr_post[] = {
|
||||
/* Comment: !!!FIXME!!! */
|
||||
0x00000000, /*Cfg End */
|
||||
0x00000000 /* END COMMAND */
|
||||
};
|
||||
|
||||
uint32_t s2r_aop_to_aop_ddr_post_2[] = {
|
||||
/* Comment: !!!FIXME!!! */
|
||||
0x00000000, /*Cfg End */
|
||||
0x00000000 /* END COMMAND */
|
||||
};
|
||||
|
||||
uint32_t s2r_aop_to_aop_ddr_post_3[] = {
|
||||
/* Comment: !!!FIXME!!! */
|
||||
0x00000000, /*Cfg End */
|
||||
0x00000000 /* END COMMAND */
|
||||
};
|
||||
|
||||
/* Comment: // ****************************************************************************************** */
|
||||
/* Comment: // ** AOP_DDR->S2R_AOP PREAMBLE */
|
||||
/* Comment: // ****************************************************************************************** */
|
||||
uint32_t aop_ddr_to_s2r_aop_pre[] = {
|
||||
/* Comment: !!!FIXME!!! */
|
||||
0x00000000, /*Cfg End */
|
||||
0x00000000 /* END COMMAND */
|
||||
};
|
||||
|
||||
/* Comment: // ****************************************************************************************** */
|
||||
/* Comment: // ** AWAKE->AOP_DDR PREAMBLE */
|
||||
/* Comment: // ****************************************************************************************** */
|
||||
uint32_t awake_to_aop_ddr_pre[] = {
|
||||
/* Comment: !!!FIXME!!! */
|
||||
0x00000000, /*Cfg End */
|
||||
0x00000000 /* END COMMAND */
|
||||
};
|
||||
|
||||
/* Comment: // ****************************************************************************************** */
|
||||
/* Comment: // ** AWAKE->AOP_DDR POSTAMBLE */
|
||||
/* Comment: // ** */
|
||||
/* Comment: // ** Note: */
|
||||
/* Comment: // ** According to the PMGR spec section 11.14.4 (Software Teardown for Awake Exit), either */
|
||||
/* Comment: // ** SW or the config engine may turn off SIO/PCIE. For DV simulations, we chose to power */
|
||||
/* Comment: // ** power down ALL of the unneeded blocks in the config engine rather than from the AP. This */
|
||||
/* Comment: // ** provided functionally equivalent behavior and allowed the AWAKE->AOP_DDR and */
|
||||
/* Comment: // ** S2R_AOP->AOP_DDR to appear symmetric. SiVal/SW may move parts of this sequence */
|
||||
/* Comment: // ** to AP software if desired. */
|
||||
/* Comment: // ** */
|
||||
/* Comment: // ****************************************************************************************** */
|
||||
uint32_t awake_to_aop_ddr_post[] = {
|
||||
/* Comment: !!!FIXME!!! */
|
||||
0x00000000, /*Cfg End */
|
||||
0x00000000 /* END COMMAND */
|
||||
};
|
||||
|
||||
/* Comment: // ****************************************************************************************** */
|
||||
/* Comment: // ** AOP_DDR->AWAKE PREAMBLE */
|
||||
/* Comment: // ****************************************************************************************** */
|
||||
uint32_t aop_ddr_to_awake_pre[] = {
|
||||
/* Comment: !!!FIXME!!! */
|
||||
0x00000000, /*Cfg End */
|
||||
0x00000000 /* END COMMAND */
|
||||
};
|
||||
|
||||
/* Comment: // ****************************************************************************************** */
|
||||
/* Comment: // ** AOP_DDR->AWAKE POSTAMBLE */
|
||||
/* Comment: // ** */
|
||||
/* Comment: // ** Note: */
|
||||
/* Comment: // ** According to the PMGR spec section 11.14.3 (Software Init for AOP_DDR to AWAKE), the */
|
||||
/* Comment: // ** config engine restores the state of the chip in this step. The specific use cases where */
|
||||
/* Comment: // ** the config engine is the owner of state restoration are not yet defined. */
|
||||
/* Comment: // ** */
|
||||
/* Comment: // ** The sequence below contains the minimum set of commands to re-boot the AP and restore */
|
||||
/* Comment: // ** DRAM operation at bucket 1. AP may bring DRAM up to bucket 0. */
|
||||
/* Comment: // ** */
|
||||
/* Comment: // ** It is assumed that SW will add extensively to this sequence for state restoration based */
|
||||
/* Comment: // ** on future use cases. */
|
||||
/* Comment: // ** */
|
||||
/* Comment: // ****************************************************************************************** */
|
||||
uint32_t aop_ddr_to_awake_post[] = {
|
||||
/* Comment: !!!FIXME!!! */
|
||||
0x00000000, /*Cfg End */
|
||||
0x00000000 /* END COMMAND */
|
||||
};
|
||||
|
||||
uint32_t aop_ddr_to_awake_post_2[] = {
|
||||
/* Comment: !!!FIXME!!! */
|
||||
0x00000000, /*Cfg End */
|
||||
0x00000000 /* END COMMAND */
|
||||
};
|
||||
|
||||
uint32_t mcu_aop_ddr_reconfig[] = {
|
||||
/* Comment: !!!FIXME!!! */
|
||||
0x00000000, /*Cfg End */
|
||||
0x00000000 /* END COMMAND */
|
||||
};
|
||||
|
||||
uint32_t mcu_aop_awake_reconfig_pre_restore[] = {
|
||||
/* Comment: !!!FIXME!!! */
|
||||
0x00000000, /*Cfg End */
|
||||
0x00000000 /* END COMMAND */
|
||||
};
|
||||
|
||||
// Calibrated values will be added to this sequence, thus needs to be aligned.
|
||||
// The order of registers in this sequence impacts dcs_save_calibration_results and dcs_restore_calibration_results
|
||||
uint32_t mcu_aop_awake_reconfig_restore[]__aligned(32) = {
|
||||
/* Comment: !!!FIXME!!! */
|
||||
0x00000000, /*Cfg End */
|
||||
0x00000000 /* END COMMAND */
|
||||
};
|
||||
|
||||
uint32_t mcu_aop_awake_reconfig_post_restore[] = {
|
||||
/* Comment: !!!FIXME!!! */
|
||||
0x00000000, /*Cfg End */
|
||||
0x00000000 /* END COMMAND */
|
||||
};
|
||||
|
||||
#endif // __AOP_CONFIG_SEQUENCES_H__
|
||||
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_SOC_CCC_H
|
||||
#define __PLATFORM_SOC_CCC_H
|
||||
|
||||
#include <platform.h>
|
||||
#include SUB_PLATFORM_SPDS_HEADER(acc)
|
||||
|
||||
// CPU0 Regsiters
|
||||
#define rCCC_CPU0_IMPL_IORVBAR (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + ACC_CPU0_IMPL_IO_RVBAR_OFFSET))
|
||||
#define rCCC_CPU0_IMPL_MMU_ERR_STS (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + ACC_CPU0_IMPL_MMU_ERR_STS_OFFSET))
|
||||
#define rCCC_CPU0_IMPL_MIGSTS_EL1 (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + ACC_CPU0_IMPL_MIGSTS_EL1_OFFSET))
|
||||
|
||||
// CPU0 Hurricane Regsiters
|
||||
#define rCCC_CPU0_IMPL_FED_ERR_STS (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + ACC_CPU0_IMPL_FED_ERR_STS_OFFSET))
|
||||
#define rCCC_CPU0_IMPL_LSU_ERR_STS (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + ACC_CPU0_IMPL_LSU_ERR_STS_OFFSET))
|
||||
|
||||
// CPU0 Zephyr Regsiters
|
||||
#define rCCC_CPU0_IMPL_E_FED_ERR_STS (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + ACC_CPU0_IMPL_E_FED_ERR_STS_OFFSET))
|
||||
#define rCCC_CPU0_IMPL_E_LSU_ERR_STS (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + ACC_CPU0_IMPL_E_LSU_ERR_STS_OFFSET))
|
||||
|
||||
// CPU1 Registers
|
||||
#define rCCC_CPU1_IMPL_IORVBAR (*(volatile u_int64_t *)(CCC_CPU1_SYS_BASE_ADDR + ACC_CPU0_IMPL_IO_RVBAR_OFFSET))
|
||||
|
||||
// Registers shared between all CPUs
|
||||
#define rCCC_CCC_IMPL_L2C_ERR_STS (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + ACC_IMPL_L2C_ERR_STS_OFFSET))
|
||||
#define rCCC_CCC_IMPL_L2C_ERR_ADR (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + ACC_IMPL_L2C_ERR_ADR_OFFSET))
|
||||
#define rCCC_CCC_IMPL_L2C_ERR_INF (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + ACC_IMPL_L2C_ERR_INF_OFFSET))
|
||||
|
||||
#endif /* __PLATFORM_SOC_CCC_H */
|
||||
@@ -0,0 +1,110 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_CHIPID_H
|
||||
#define __PLATFORM_SOC_CHIPID_H
|
||||
|
||||
#include <platform/chipid.h>
|
||||
#include <platform/soc/pmgr.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <soc/t8010/a0/minipmgr.h>
|
||||
|
||||
#define rCFG_FUSE0 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE0_OFFSET))
|
||||
#define rCFG_FUSE1 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE1_OFFSET))
|
||||
#define rCFG_FUSE2 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE2_OFFSET))
|
||||
#define rCFG_FUSE3 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE3_OFFSET))
|
||||
#define rCFG_FUSE4 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE4_OFFSET))
|
||||
#define rCFG_FUSE5 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE5_OFFSET))
|
||||
#define rCFG_FUSE9 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE9_OFFSET))
|
||||
|
||||
#define rECIDLO (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_ECID_FUSE0_OFFSET))
|
||||
#define rECIDHI (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_ECID_FUSE1_OFFSET))
|
||||
|
||||
#define rSEP_SECURITY (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_SEP_SECURITY_OFFSET))
|
||||
|
||||
#define rCFG_FUSE0_RAW (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE0_RAW_OFFSET))
|
||||
|
||||
enum chipid_voltage_index {
|
||||
CHIPID_CPU_VOLTAGE_BYPASS,
|
||||
CHIPID_CPU_VOLTAGE_SECUREROM,
|
||||
CHIPID_CPU_VOLTAGE_396,
|
||||
|
||||
CHIPID_GPU_VOLTAGE_OFF,
|
||||
|
||||
CHIPID_ALL_VOLTAGE_LAST,
|
||||
};
|
||||
|
||||
enum chipid_voltage_type {
|
||||
CHIPID_CPU_VOLTAGE,
|
||||
CHIPID_GPU_VOLTAGE,
|
||||
};
|
||||
|
||||
struct chipid_vol_adj {
|
||||
uint64_t volAdj0:20;
|
||||
uint64_t volAdj1:20;
|
||||
uint64_t volAdj2:20;
|
||||
uint64_t volAdj3:20;
|
||||
uint64_t dvfmMaxAdj:20;
|
||||
uint64_t dvmrAdj0:20;
|
||||
uint64_t dvmrAdj1:20;
|
||||
uint64_t dvmrAdj2:20;
|
||||
};
|
||||
|
||||
#define CHIPID_SOC_VOLTAGE_BYPASS (0)
|
||||
#define CHIPID_SOC_VOLTAGE_SECUREROM (1)
|
||||
#define CHIPID_SOC_VOLTAGE_VMIN (2)
|
||||
#define CHIPID_SOC_VOLTAGE_VNOM (3)
|
||||
|
||||
extern const struct chipid_vol_adj *chipid_get_vol_adj(enum chipid_voltage_index voltage_index);
|
||||
|
||||
uint32_t chipid_get_cpu_voltage(uint32_t index);
|
||||
|
||||
uint32_t chipid_get_cpu_sram_voltage(uint32_t index);
|
||||
|
||||
uint32_t chipid_get_soc_voltage(uint32_t index);
|
||||
|
||||
uint32_t chipid_get_gpu_voltage(uint32_t index);
|
||||
|
||||
uint32_t chipid_get_gpu_sram_voltage(uint32_t index);
|
||||
|
||||
uint32_t chipid_get_sram_voltage(uint32_t index);
|
||||
|
||||
int32_t chipid_get_cpu_temp_offset(uint32_t cpu_number);
|
||||
|
||||
uint32_t chipid_get_soc_temp_sensor_trim(uint32_t sensor_index);
|
||||
|
||||
uint32_t chipid_get_fuse_revision(void);
|
||||
|
||||
uint32_t chipid_get_total_rails_leakage();
|
||||
|
||||
uint32_t chipid_get_lpo_trim(void);
|
||||
|
||||
uint32_t chipid_get_pcie_refpll_fcal_vco_digctrl(void);
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
|
||||
#define FPGA_HAS_ALWAYS (1 << 31)
|
||||
#define FPGA_HAS_MEDIA (1 << 0)
|
||||
#define FPGA_HAS_MSR (1 << 1)
|
||||
#define FPGA_HAS_JPEG (1 << 2)
|
||||
#define FPGA_HAS_AVE (1 << 3)
|
||||
#define FPGA_HAS_VXD (1 << 4)
|
||||
#define FPGA_HAS_ISP (1 << 5)
|
||||
#define FPGA_HAS_RTBUSMUX (1 << 6)
|
||||
#define FPGA_HAS_DISP (1 << 7)
|
||||
#define FPGA_HAS_GFX (1 << 8)
|
||||
|
||||
#define rECID_FUSE3 (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_ECID_FUSE3_OFFSET))
|
||||
|
||||
uint32_t chipid_get_fpga_block_instantiation(void);
|
||||
|
||||
#endif // SUPPORT_FPGA
|
||||
|
||||
#endif /* __PLATFORM_SOC_CHIPID_H */
|
||||
@@ -0,0 +1,121 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_H
|
||||
#define __APPLE_DISPLAY_H
|
||||
|
||||
// Platform-specific displaypipe tunables
|
||||
|
||||
// XXX - disp_dpcafclkgate is listed as TBD
|
||||
// D620 is most likely something new based on the values. Update once we know more.
|
||||
|
||||
static struct adfe_v2_tuneable adfe_tuneables[] =
|
||||
{
|
||||
#if DISPLAY_IPHONE_TUNABLES
|
||||
#if DISPLAY_D620_TUNABLES
|
||||
{
|
||||
.name = "D620",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x60) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x709),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x7f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0xffff) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x6ff),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x6f7),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x5f6),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x5ee),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0xe1) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQARRG_OPPORTUNISMENAB | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0) | \
|
||||
ADPAFDYNCLKGATEEN),
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
#endif //DISPLAY_D620_TUNABLES
|
||||
|
||||
#if DISPLAY_D520_TUNABLES
|
||||
{
|
||||
.name = "D520",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x60) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x3db),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x7f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x7a7) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x3d1),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x3c9),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x2ff),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x2f7),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x6b) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQARRG_OPPORTUNISMENAB | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0) | \
|
||||
ADPAFDYNCLKGATEEN),
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
#endif //DISPLAY_D520_TUNABLES
|
||||
#endif //DISPLAY_IPHONE_TUNABLES
|
||||
|
||||
//Tunables for targets using the the timing based on landscape ipads
|
||||
#if DISPLAY_LANDSCAPE_IPAD_TUNABLES || DISPLAY_APPLE_TV_TUNABLES || DISPLAY_FPGA_TUNABLES
|
||||
{
|
||||
.name = "default",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x60) | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x547),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x7f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x3a2c) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x545),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x53d),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x3a1),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x399),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x4b) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQARRG_OPPORTUNISMENAB | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0) | \
|
||||
ADPAFDYNCLKGATEEN),
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
#if DISPLAY_IPHONE_TUNABLES
|
||||
#error DISPLAY_IPHONE_TUNABLES set for IPAD
|
||||
#endif
|
||||
|
||||
#endif //DISPLAY_LANDSCAPE_IPAD_TUNABLES || DISPLAY_APPLE_TV_TUNABLES || DISPLAY_FPGA_TUNABLES
|
||||
};
|
||||
|
||||
#endif /* ! __APPLE_DISPLAY_H */
|
||||
@@ -0,0 +1,118 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_TIMINGS_H
|
||||
#define __APPLE_DISPLAY_TIMINGS_H
|
||||
|
||||
//Supported timings by this platform
|
||||
static struct display_timing timing_list[] =
|
||||
{
|
||||
#if DEBUG_BUILD || SUB_TARGET_T8010SIM
|
||||
{
|
||||
.display_name = "D520",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 100000000,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 750,
|
||||
.h_pulse_width = 32,
|
||||
.h_back_porch = 4,
|
||||
.h_front_porch = 102,
|
||||
.v_active = 1334,
|
||||
.v_pulse_width = 3,
|
||||
.v_back_porch = 4,
|
||||
.v_front_porch = 536,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_PINOT,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD
|
||||
{
|
||||
.display_name = "D620",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 200000000,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 1080,
|
||||
.h_pulse_width = 32,
|
||||
.h_back_porch = 4,
|
||||
.h_front_porch = 116,
|
||||
.v_active = 1920,
|
||||
.v_pulse_width = 3,
|
||||
.v_back_porch = 5,
|
||||
.v_front_porch = 778,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_PINOT,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || SUB_TARGET_T8010FPGA
|
||||
{
|
||||
.display_name = "fpga-wsvga",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 5000000,
|
||||
.dot_pitch = 243,
|
||||
.h_active = 1024,
|
||||
.h_pulse_width = 50,
|
||||
.h_back_porch = 50,
|
||||
.h_front_porch = 51,
|
||||
.v_active = 600,
|
||||
.v_pulse_width = 50,
|
||||
.v_back_porch = 218,
|
||||
.v_front_porch = 6,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 18,
|
||||
.display_type = DISPLAY_TYPE_DUMB,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || WITH_HW_DISPLAY_DISPLAYPORT
|
||||
{
|
||||
.display_name = "720p",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 74250000,
|
||||
.dot_pitch = 243,
|
||||
.h_active = 1280,
|
||||
.h_pulse_width = 40,
|
||||
.h_back_porch = 110,
|
||||
.h_front_porch = 220,
|
||||
.v_active = 720,
|
||||
.v_pulse_width = 5,
|
||||
.v_back_porch = 5,
|
||||
.v_front_porch = 20,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_DP,
|
||||
.display_config.dp.mode = 0x0,
|
||||
.display_config.dp.type = 0x1,
|
||||
.display_config.dp.min_link_rate = 0x6,
|
||||
.display_config.dp.max_link_rate = 0x6,
|
||||
.display_config.dp.lanes = 0x2,
|
||||
.display_config.dp.ssc = 0x0,
|
||||
.display_config.dp.alpm = 0x0,
|
||||
.display_config.dp.vrr_enable = 0x0,
|
||||
.display_config.dp.vrr_on = 0x0,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
#endif /* ! __APPLE_DISPLAY_TIMINGS_H */
|
||||
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_DVFMPERF_H
|
||||
#define __PLATFORM_SOC_DVFMPERF_H
|
||||
#include <platform/soc/chipid.h>
|
||||
|
||||
enum chipid_voltage_index dvfmperf_get_voltage_index(uint32_t index, enum chipid_voltage_type voltage_type);
|
||||
|
||||
#endif /* __PLATFORM_SOC_DVFMPERF_H */
|
||||
@@ -0,0 +1,167 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWCLOCKS_H
|
||||
#define __PLATFORM_SOC_HWCLOCKS_H
|
||||
|
||||
#include <platform/clocks.h>
|
||||
#include <soc/t8010/a0/pmgr.h>
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define OSC_FREQ (5000000UL)
|
||||
#define LPPLL_FREQ (OSC_FREQ)
|
||||
#else
|
||||
#define OSC_FREQ (24000000UL)
|
||||
#define LPPLL_FREQ (192000000UL)
|
||||
#endif
|
||||
|
||||
#if SUB_PLATFORM_T8010
|
||||
/*
|
||||
* T8010 clock gate devices.
|
||||
*/
|
||||
enum {
|
||||
// Mini-PMGR
|
||||
CLK_AOP = HWCLOCK_BASE,
|
||||
CLK_DEBUG,
|
||||
CLK_AOP_GPIO,
|
||||
CLK_AOP_UART0,
|
||||
CLK_AOP_UART1,
|
||||
CLK_AOP_UART2,
|
||||
CLK_AOP_I2CM,
|
||||
CLK_AOP_MCA0,
|
||||
CLK_AOP_PDM_REF,
|
||||
CLK_AOP_CPU,
|
||||
CLK_AOP_FILTER,
|
||||
CLK_AOP_BUSIF,
|
||||
CLK_AOP_LPD0,
|
||||
CLK_AOP_LPD1,
|
||||
CLK_AOP_HPDS,
|
||||
CLK_AOP_HPDSC,
|
||||
CLK_AOP_HPDD,
|
||||
|
||||
// PMGR
|
||||
CLK_SBR,
|
||||
CLK_AIC,
|
||||
CLK_DWI,
|
||||
CLK_GPIO,
|
||||
CLK_PMS,
|
||||
CLK_HSIC0PHY,
|
||||
CLK_ISPSENS0,
|
||||
CLK_ISPSENS1,
|
||||
CLK_ISPSENS2,
|
||||
CLK_PCIE_REF,
|
||||
CLK_SOCUVD,
|
||||
CLK_SIO_BUSIF,
|
||||
CLK_SIO_P,
|
||||
CLK_SIO,
|
||||
CLK_MCA0,
|
||||
CLK_MCA1,
|
||||
CLK_MCA2,
|
||||
CLK_MCA3,
|
||||
CLK_MCA4,
|
||||
CLK_PWM0,
|
||||
CLK_I2C0,
|
||||
CLK_I2C1,
|
||||
CLK_I2C2,
|
||||
CLK_I2C3,
|
||||
CLK_SPI0,
|
||||
CLK_SPI1,
|
||||
CLK_SPI2,
|
||||
CLK_SPI3,
|
||||
CLK_UART0,
|
||||
CLK_UART1,
|
||||
CLK_UART2,
|
||||
CLK_UART3,
|
||||
CLK_UART4,
|
||||
CLK_UART5,
|
||||
CLK_UART6,
|
||||
CLK_UART7,
|
||||
CLK_UART8,
|
||||
CLK_AES0,
|
||||
CLK_HFD0,
|
||||
CLK_MCC,
|
||||
CLK_DCS0,
|
||||
CLK_DCS1,
|
||||
CLK_DCS2,
|
||||
CLK_DCS3,
|
||||
CLK_USB,
|
||||
CLK_USBCTLREG,
|
||||
CLK_USB2HOST0,
|
||||
CLK_USB2HOST0_OHCI,
|
||||
CLK_USB2HOST1,
|
||||
CLK_USB_OTG,
|
||||
CLK_SMX,
|
||||
CLK_SF,
|
||||
CLK_RTMUX,
|
||||
CLK_DISP0_FE,
|
||||
CLK_DISP0_BE,
|
||||
CLK_MIPI_DSI,
|
||||
CLK_MIPI = CLK_MIPI_DSI,
|
||||
CLK_DP,
|
||||
CLK_EDPLINK = CLK_DP,
|
||||
CLK_DPLINK = CLK_DP,
|
||||
CLK_ISP_SYS,
|
||||
CLK_MEDIA,
|
||||
CLK_JPG,
|
||||
CLK_MSR,
|
||||
CLK_PMP,
|
||||
CLK_PMS_SRAM,
|
||||
CLK_VDEC0,
|
||||
CLK_VENC,
|
||||
CLK_PCIE,
|
||||
CLK_PCIE_AUX,
|
||||
CLK_GFX,
|
||||
|
||||
// Unmanaged
|
||||
CLK_CPU0,
|
||||
CLK_CPU1,
|
||||
CLK_CPM,
|
||||
CLK_SEP,
|
||||
CLK_ISP_RSTS0,
|
||||
CLK_ISP_RSTS1,
|
||||
CLK_ISP_VIS,
|
||||
CLK_ISP_BE,
|
||||
CLK_ISP_PEARL,
|
||||
CLK_DPRX,
|
||||
CLK_VENC_PIPE4,
|
||||
CLK_VENC_PIPE5,
|
||||
CLK_VENC_ME0,
|
||||
CLK_VENC_ME1,
|
||||
|
||||
CLK_LAST,
|
||||
};
|
||||
|
||||
#define PMGR_FIRST_DEVICE CLK_AOP
|
||||
#define PMGR_LAST_DEVICE CLK_GFX
|
||||
|
||||
#else
|
||||
#error "Unknown Platform"
|
||||
#endif
|
||||
|
||||
#define PMGR_DEVICE_INDEX(_clk) ((_clk) - HWCLOCK_BASE)
|
||||
#define PMGR_DEVICE_COUNT (CLK_LAST - HWCLOCK_BASE)
|
||||
|
||||
#define PMGR_VALID_DEVICE(_clk) ((_clk) >= PMGR_FIRST_DEVICE && (_clk) <= PMGR_LAST_DEVICE)
|
||||
|
||||
// Legacy clocks, no associated device or PS register
|
||||
enum {
|
||||
CLK_FCLK = CLK_LAST,
|
||||
CLK_ACLK,
|
||||
CLK_HCLK,
|
||||
CLK_PCLK,
|
||||
CLK_VCLK0,
|
||||
CLK_VCLK1,
|
||||
CLK_MCLK,
|
||||
CLK_NCLK,
|
||||
CLK_USBPHYCLK,
|
||||
CLK_NCOREF,
|
||||
};
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWCLOCKS_H */
|
||||
@@ -0,0 +1,347 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWISR_H
|
||||
#define __PLATFORM_SOC_HWISR_H
|
||||
|
||||
#if SUB_PLATFORM_T8010
|
||||
|
||||
#define INT_SW0 0 // Software 0 Interrupt
|
||||
#define INT_SW1 1 // Software 1 Interrupt
|
||||
#define INT_SW2 2 // Software 2 Interrupt
|
||||
#define INT_SW3 3 // Software 3 Interrupt
|
||||
#define INT_WDT 4 // Watchdog Timer Interrupt
|
||||
#define INT_DWI1 5 // DWI Interrupt
|
||||
#define INT_DWI2 6 // DWI Interrupt
|
||||
#define INT_PMGR_PERF_CNTRS 7 // PMGR Performace Counters Interrupt
|
||||
#define INT_THERM_TEMP0 8 // Thermal Temp 0 Interrupt
|
||||
#define INT_THERM_ALARM0 9 // Thermal Alarm 0 Interrupt
|
||||
#define INT_THERM_TEMP1 10 // Thermal Temp 1 Interrupt
|
||||
#define INT_THERM_ALARM1 11 // Thermal Alarm 1 Interrupt
|
||||
#define INT_THERM_TEMP2 12 // Thermal Temp 2 Interrupt
|
||||
#define INT_THERM_ALARM2 13 // Thermal Alarm 2 Interrupt
|
||||
|
||||
// Reserved 14 - 15
|
||||
|
||||
#define INT_CPM_THERM_TEMP 16 // CPM Thermal temp Interrupt
|
||||
#define INT_CPM_THERM_ALARM 17 // CPM Thermal alarm Interrupt
|
||||
#define INT_CPU0_THERM_TEMP 18 // CPU0 Thermal temp Interrupt
|
||||
#define INT_CPU0_THERM_ALARM 19 // CPU0 Thermal alarm Interrupt
|
||||
#define INT_CPU1_THERM_TEMP 20 // CPU1 Thermal temp Interrupt
|
||||
#define INT_CPU1_THERM_ALARM 21 // CPU1 Thermal alarm Interrupt
|
||||
|
||||
// Reserved 21 - 25
|
||||
|
||||
#define INT_THERM_FS_ACT0 26 // Thermal Failsafe Active 0 Interrupt
|
||||
#define INT_THERM_FS_ACT1 27 // Thermal Failsafe Active 1 Interrupt
|
||||
#define INT_THERM_FS_EXT0 28 // Thermal Failsafe Exit 0 Interrupt
|
||||
#define INT_THERM_FS_EXT1 29 // Thermal Failsafe Exit 1 Interrupt
|
||||
#define INT_SOC_THERM_FS_ACT0 30 // SoC Thermal Failsafe Active 0 Interrupt
|
||||
#define INT_SOC_THERM_FS_ACT1 31 // SoC Thermal Failsafe Active 1 Interrupt
|
||||
#define INT_PMGR_EVENT 32 // PMGR Event Interrupt
|
||||
#define INT_CTM_TRIGGER0 33 // CTM Trigger 0 Interrupt
|
||||
#define INT_CTM_TRIGGER1 34 // CTM Trigger 1 Interrupt
|
||||
#define INT_CTM_TRIGGER2 35 // CTM Trigger 2 Interrupt
|
||||
#define INT_CTM_TRIGGER3 36 // CTM Trigger 3 Interrupt
|
||||
#define INT_COHERENCE_PNT_ERR 37 // Coherence Point Error Interrupt
|
||||
#define INT_COHERENCE_PNT_PERF_CNTRS 38 // Coherence Point Performance Counter Interrupt
|
||||
|
||||
// Reserved 39-41
|
||||
|
||||
#define INT_GPIO_CLASS0 42 // GPIO Class 0 Interrupt
|
||||
#define INT_GPIO_CLASS1 43 // GPIO Class 1 Interrupt
|
||||
#define INT_GPIO_CLASS2 44 // GPIO Class 2 Interrupt
|
||||
#define INT_GPIO_CLASS3 45 // GPIO Class 3 Interrupt
|
||||
#define INT_GPIO_CLASS4 46 // GPIO Class 4 Interrupt
|
||||
#define INT_GPIO_CLASS5 47 // GPIO Class 5 Interrupt
|
||||
#define INT_GPIO_CLASS6 48 // GPIO Class 6 Interrupt
|
||||
|
||||
// Reserved 49
|
||||
|
||||
#define INT_MINIMPGR_PERF_CTR 50 // MINIPMGR Performance Counter Interrupt
|
||||
#define INT_GFX_PERF_CTR 51 // GFX Performance Counter Interrupt
|
||||
#define INT_MEM_CONTROLLER0 52 // Memory Controller MCC0 Interrupt
|
||||
#define INT_MEM_CONTROLLER1 53 // Memory Controller MCC1 Interrupt
|
||||
|
||||
// Reserved 54-55
|
||||
|
||||
#define INT_MEM_CTLR_DCS0_AMCX0 56 // Memory Controller DCS0 AMCX 0 Interrupt
|
||||
#define INT_MEM_CTLR_DCS0_AMCX1 57 // Memory Controller DCS0 AMCX 1 Interrupt
|
||||
#define INT_MEM_CTLR_DCS0_AMP_CAL_ERR 58 // Memory Controller DCS0 AMP Cal Error 1 Interrupt
|
||||
#define INT_MEM_CTLR_DCS1_AMCX0 59 // Memory Controller DCS1 AMCX 0 Interrupt
|
||||
#define INT_MEM_CTLR_DCS1_AMCX1 60 // Memory Controller DCS1 AMCX 1 Interrupt
|
||||
#define INT_MEM_CTLR_DCS1_AMP_CAL_ERR 61 // Memory Controller DCS1 AMP Cal Error 1 Interrupt
|
||||
#define INT_MEM_CTLR_DCS2_AMCX0 62 // Memory Controller DCS2 AMCX 0 Interrupt
|
||||
#define INT_MEM_CTLR_DCS2_AMCX1 63 // Memory Controller DCS2 AMCX 1 Interrupt
|
||||
#define INT_MEM_CTLR_DCS2_AMP_CAL_ERR 64 // Memory Controller DCS2 AMP Cal Error 1 Interrupt
|
||||
#define INT_MEM_CTLR_DCS3_AMCX0 65 // Memory Controller DCS3 AMCX 0 Interrupt
|
||||
#define INT_MEM_CTLR_DCS3_AMCX1 66 // Memory Controller DCS3 AMCX 1 Interrupt
|
||||
#define INT_MEM_CTLR_DCS3_AMP_CAL_ERR 67 // Memory Controller DCS3 AMP Cal Error 1 Interrupt
|
||||
|
||||
// Reserved 68-80
|
||||
|
||||
#define INT_CPU0_COMM_TX 81 // CPU 0 COMM TX Interrupt
|
||||
#define INT_CPU0_COMM_RX 82 // CPU 0 COMM RX Interrupt
|
||||
#define INT_CPU0_PMU_IRQ 83 // CPU 0 PMU IRQ Interrupt
|
||||
#define INT_CPU1_COMM_TX 84 // CPU 1 COMM TX Interrupt
|
||||
#define INT_CPU1_COMM_RX 85 // CPU 1 COMM RX Interrupt
|
||||
#define INT_CPU1_PMU_IRQ 86 // CPU 1 PMU IRQ Interrupt
|
||||
|
||||
// Reserved 87 - 92
|
||||
|
||||
#define INT_CCC_UNIFIED_TRIGGER 93 // CCC Unified Trigger Interrupt
|
||||
|
||||
// Reserved 94
|
||||
|
||||
#define INT_GFX_THROTTLING_TRIGGER 95 // GFX Throttling Trigger Interrupt
|
||||
|
||||
// Reserved 96 - 103
|
||||
|
||||
#define INT_ISP_KF_INBOX_EMPTY 104 // ISP KF Inbox Empty Interrupt
|
||||
#define INT_ISP_KF_INBOX_NOTEMPTY 105 // ISP KF Inbox Not Empty Interrupt
|
||||
#define INT_ISP_KF_OUTBOX_EMPTY 106 // ISP KF Outbox Empty Interrupt
|
||||
#define INT_ISP_KF_OUTBOX_NOTEMPTY 107 // ISP KF Outbox Not Empty Interrupt
|
||||
#define INT_ISP0 108 // ISP 0 Interrupt
|
||||
#define INT_ISP1 109 // ISP 1 Interrupt
|
||||
#define INT_ISP2 110 // ISP 2 Interrupt
|
||||
#define INT_ISP3 111 // ISP 3 Interrupt
|
||||
#define INT_ISP_DART 112 // ISP DART Interrupt
|
||||
|
||||
// Reserved 113
|
||||
|
||||
#define INT_SEP_KF_INBOX_EMPTY 114 // SEP KF Inbox Empty Interrupt
|
||||
#define INT_SEP_KF_INBOX_NOTEMPTY 115 // SEP KF Inbox Not Empty Interrupt
|
||||
#define INT_SEP_KF_OUTBOX_EMPTY 116 // SEP KF Outbox Empty Interrupt
|
||||
#define INT_SEP_KF_OUTBOX_NOTEMPTY 117 // SEP KF Outbox Not Empty Interrupt
|
||||
#define INT_SEP_AUTH_ERROR 118 // SEP Authentication Error Interrupt
|
||||
#define INT_SEP_CRIT_PATH_MONITOR 119 // SEP Critical Path Monitor Interrupt
|
||||
|
||||
// Reserved 120 - 122
|
||||
|
||||
#define INT_DOCK_CHANNELS 123 // Dock Channels Interrupt
|
||||
#define INT_SCM_SPI 124 // SCM SPI Interrupt
|
||||
#define INT_AOP_UART0 125 // AOP UART0 Interrupt
|
||||
#define INT_AOP_UART1 126 // AOP UART1 Interrupt
|
||||
#define INT_AOP_I2CM 127 // AOP I2CM Interrupt
|
||||
#define INT_AOP_GPIO_IRQ0 128 // AOP GPIO IRQ0 Interrupt
|
||||
#define INT_AOP_GPIO_IRQ1 129 // AOP GPIO IRQ1 Interrupt
|
||||
#define INT_AOP_GPIO_IRQ2 130 // AOP GPIO IRQ2 Interrupt
|
||||
#define INT_AOP_GPIO_IRQ3 131 // AOP GPIO IRQ3 Interrupt
|
||||
#define INT_AOP_GPIO_IRQ4 132 // AOP GPIO IRQ4 Interrupt
|
||||
#define INT_AOP_GPIO_IRQ5 133 // AOP GPIO IRQ5 Interrupt
|
||||
#define INT_AOP_GPIO_IRQ6 134 // AOP GPIO IRQ6 Interrupt
|
||||
#define INT_WAKEUP_AP 135 // AOP Wakeup AP Interrupt
|
||||
#define INT_CPU_WAKEUP_AP 136 // AOP CPU Wakeup AP Interrupt
|
||||
#define INT_SCM_RX_BUFFER_FULL0 137 // AOP SCM Buffer Full 0 Interrupt
|
||||
#define INT_SCM_RX_BUFFER_FULL1 138 // AOP SCM Buffer Full 1 Interrupt
|
||||
#define INT_SCM_MAX_COUNT0 139 // AOP SCM Max Count 0 Interrupt
|
||||
#define INT_SCM_MAX_COUNT1 140 // AOP SCM Max Count 1 Interrupt
|
||||
#define INT_SCM_SLAVE_ERROR 141 // AOP SCM Slave Error Interrupt
|
||||
#define INT_AOP_UART2 142 // AOP UART2 Interrupt
|
||||
#define INT_AOP_MCA0 143 // AOP MCA0 Interrupt
|
||||
#define INT_AOP_HPD_DETECT 144 // AOP HPD Detect Interrupt
|
||||
#define INT_AOP_KF_INBOX_EMPTY 145 // AOP KF Inbox Empty Interrupt
|
||||
#define INT_AOP_KF_INBOX_NOTEMPTY 146 // AOP KF Inbox Not Empty Interrupt
|
||||
#define INT_AOP_KF_OUTBOX_EMPTY 147 // AOP KF Outbox Empty Interrupt
|
||||
#define INT_AOP_KF_OUTBOX_NOTEMPTY 148 // AOP KF Outbox Not Empty Interrupt
|
||||
#define INT_AOP_AP_WATCHDOG 149 // AOP MCA0 Interrupt
|
||||
#define INT_AOP_AP_WAKEUP_TIME 150 // AOP MCA0 Interrupt
|
||||
#define INT_AOP_CDBGPWRUPREQ 151 // AOP CDBGPWRUPREQ Interrupt
|
||||
#define INT_AOP_HPD_ERROR 152 // AOP HPD Error Interrupt
|
||||
|
||||
// Reserved 153
|
||||
|
||||
#define INT_DISP0 154 // Display 0 Interrupt
|
||||
#define INT_DISP0_PIO_DMA 155 // Display 0 PIO DMA Interrupt
|
||||
#define INT_DISP0_DART 156 // Display 0 DART Interrupt
|
||||
#define INT_DISP0_SMMU 157 // Display 0 SMMU Interrupt
|
||||
#define INT_DISP0_BACK_END_BLU 158 // Display 0 Back End Back Light Update Interrupt
|
||||
#define INT_DISP0_BACK_END_VBI 159 // Display 0 Back End VBI Interrupt
|
||||
#define INT_DISP0_BACK_END_VFTG 160 // Display 0 Back End VFTG Idle Interrupt
|
||||
#define INT_DISP0_BACK_END_VBL 161 // Display 0 Back End VBL counter Interrupt
|
||||
#define INT_DISPLAY_PORT_TX0 162 // Display Port TX 0 Interrupt
|
||||
#define INT_MIPIDSI0 163 // MIPI DSI 0 Interrupt
|
||||
#define INT_EDP0 INT_DISPLAY_PORT
|
||||
#define INT_DPORT0 INT_DISPLAY_PORT
|
||||
#define INT_DISP0_BACK_END_VBI2 164 // Display 0 Back End - VBI2 Interrupt
|
||||
#define INT_DISP0_SUBFRAME_TIMESTAMP 165 // Display 0 Sub Frame Line Count TimeStamp Interrupt
|
||||
#define INT_DISP0_BACK_END_PARAM_FIFO 166 // Display 0 Back End - Param FIFO completion Interrupt
|
||||
#define INT_PMP_KF_INBOX_EMPTY 167 // PMP KF Inbox Empty Interrupt
|
||||
#define INT_PMP_KF_INBOX_NOTEMPTY 168 // PMP KF Inbox Not Empty Interrupt
|
||||
#define INT_PMP_KF_OUTBOX_EMPTY 169 // PMP KF Outbox Empty Interrupt
|
||||
#define INT_PMP_KF_OUTBOX_NOTEMPTY 170 // PMP KF Outbox Not Empty Interrupt
|
||||
|
||||
// Reserved 171
|
||||
|
||||
#define INT_VDEC0 172 // Video Decoder 0 Interrupt
|
||||
|
||||
// Reserved 173
|
||||
|
||||
#define INT_AVE_KF_INBOX_EMPTY 174 // AVE KF Inbox Empty Interrupt
|
||||
#define INT_AVE_KF_INBOX_NOTEMPTY 175 // AVE KF Inbox Not Empty Interrupt
|
||||
#define INT_AVE_KF_OUTBOX_EMPTY 176 // AVE KF Outbox Empty Interrupt
|
||||
#define INT_AVE_KF_OUTBOX_NOTEMPTY 177 // AVE KF Outbox Not Empty Interrupt
|
||||
#define INT_AVE_SMMU 178 // AVE SMMU Interrupt
|
||||
#define INT_AVE_DART 179 // AVE DART Interrupt
|
||||
#define INT_AVE 180 // AVE Interrupt
|
||||
#define INT_SVE_SYNC 181 // SVE Driver Synchronization Interrupt
|
||||
|
||||
// Reserved 182 - 184
|
||||
|
||||
#define INT_GFX 185 // GFX Interrupt
|
||||
#define INT_GFX_SLEEP 186 // GFX Sleep Interrupt
|
||||
#define INT_GFX_WAKE 187 // GFX Wake Interrupt
|
||||
#define INT_GFX_CHG 188 // GFX Change Interrupt
|
||||
#define INT_GHX_KF_INBOX_EMPTY 189 // GHX KF Inbox Empty Interrupt
|
||||
#define INT_GHX_KF_INBOX_NOTEMPTY 190 // GHX KF Inbox Not Empty Interrupt
|
||||
#define INT_GHX_KF_OUTBOX_EMPTY 191 // GHX KF Outbox Empty Interrupt
|
||||
#define INT_GHX_KF_OUTBOX_NOTEMPTY 192 // GHX KF Outbox Not Empty Interrupt
|
||||
#define INT_GHX_FIRMWARE 193 // GHX Firmware Only Interrupt
|
||||
|
||||
// Reserved 194
|
||||
|
||||
#define INT_GPU_TIMER 195 // GPU Timer Interrupt
|
||||
#define INT_JPEG0 196 // JPEG0 Interrupt
|
||||
#define INT_JPEG0_DART 197 // JPEG0 DART Interrupt
|
||||
#define INT_JPEG0_DART_PERF 198 // JPEG0 DART Performance Interrupt
|
||||
#define INT_JPEG1 199 // JPEG1 Interrupt
|
||||
#define INT_JPEG1_DART 200 // JPEG1 DART Interrupt
|
||||
#define INT_JPEG1_DART_PERF 201 // JPEG1 DART Performance Interrupt
|
||||
|
||||
// Reserved 202 - 203
|
||||
|
||||
#define INT_MSR 204 // MSR Interrupt
|
||||
#define INT_MSR_PIO_DMA 205 // MSR PIO DMA Interrupt
|
||||
#define INT_MSR_SMMU 206 // MSR SMMU Interrupt
|
||||
#define INT_MSR_DART 207 // MSR DART Interrupt
|
||||
#define INT_MSR_DART_PERF 208 // MSR DART Performance Interrupt
|
||||
|
||||
// Reserved 209
|
||||
|
||||
#define INT_SIO_KF_INBOX_EMPTY 210 // SIO KF Inbox Empty Interrupt
|
||||
#define INT_SIO_KF_INBOX_NOTEMPTY 211 // SIO KF Inbox Not Empty Interrupt
|
||||
#define INT_SIO_KF_OUTBOX_EMPTY 212 // SIO KF Outbox Empty Interrupt
|
||||
#define INT_SIO_KF_OUTBOX_NOTEMPTY 213 // SIO KF Outbox Not Empty Interrupt
|
||||
#define INT_SPI0 214 // SPI 0 Interrupt
|
||||
#define INT_SPI1 215 // SPI 1 Interrupt
|
||||
#define INT_SPI2 216 // SPI 2 Interrupt
|
||||
#define INT_SPI3 217 // SPI 3 Interrupt
|
||||
#define INT_UART0 218 // UART 0 Interrupt
|
||||
#define INT_UART1 219 // UART 1 Interrupt
|
||||
#define INT_UART2 220 // UART 2 Interrupt
|
||||
#define INT_UART3 221 // UART 3 Interrupt
|
||||
#define INT_UART4 222 // UART 4 Interrupt
|
||||
#define INT_UART5 223 // UART 5 Interrupt
|
||||
#define INT_UART6 224 // UART 6 Interrupt
|
||||
#define INT_UART7 225 // UART 7 Interrupt
|
||||
#define INT_UART8 226 // UART 8 Interrupt
|
||||
#define INT_MCA0 227 // Multi-Channel Audio 0 Interrupt
|
||||
#define INT_MCA1 228 // Multi-Channel Audio 1 Interrupt
|
||||
#define INT_MCA2 229 // Multi-Channel Audio 2 Interrupt
|
||||
#define INT_MCA3 230 // Multi-Channel Audio 3 Interrupt
|
||||
#define INT_MCA4 231 // Multi-Channel Audio 4 Interrupt
|
||||
#define INT_IIC0 232 // I2C 0 Interrupt
|
||||
#define INT_IIC1 233 // I2C 1 Interrupt
|
||||
#define INT_IIC2 234 // I2C 2 Interrupt
|
||||
#define INT_IIC3 235 // I2C 3 Interrupt
|
||||
#define INT_PWM 236 // PWM Interrupt
|
||||
#define INT_AES0 237 // AES 0 Interrupt
|
||||
#define INT_HFD 238 // HFD Interrupt
|
||||
|
||||
// Reserved 239 - 240
|
||||
|
||||
#define INT_USB_OTG 241 // USB OTG Interrupt
|
||||
#define INT_USB2HOST0_EHCI 242 // USB EHCI 0 Interrupt
|
||||
#define INT_USB2HOST0_OHCI 243 // USB OHCI 0 Interrupt
|
||||
#define INT_USB2HOST1_EHCI 244 // USB EHCI 1 Interrupt
|
||||
|
||||
// Reserved 245
|
||||
|
||||
#define INT_USBOTG_RESUME 246 // USB OTG Resume Interrupt
|
||||
#define INT_USB_20_BATT_CHRG_DET 247 // USB 2.0 Battery Charge Detect Interrupt
|
||||
#define INT_USB2HOST0_PHY_RESUME 248 // USB Host 0 Resume Interrupt
|
||||
#define INT_USB2HOST1_PHY_RESUME 249 // USB Host 1 Resume Interrupt
|
||||
|
||||
// Reserved 250
|
||||
|
||||
#define INT_OTG_IN_EP0 251 // OTG IN Endpoint 0 Interrupt
|
||||
#define INT_OTG_IN_EP1 252 // OTG IN Endpoint 1 Interrupt
|
||||
#define INT_OTG_IN_EP2 253 // OTG IN Endpoint 2 Interrupt
|
||||
#define INT_OTG_IN_EP3 254 // OTG IN Endpoint 3 Interrupt
|
||||
#define INT_OTG_IN_EP4 255 // OTG IN Endpoint 4 Interrupt
|
||||
#define INT_OTG_IN_EP5 256 // OTG IN Endpoint 5 Interrupt
|
||||
#define INT_OTG_IN_EP6 257 // OTG IN Endpoint 6 Interrupt
|
||||
#define INT_OTG_IN_EP7 258 // OTG IN Endpoint 7 Interrupt
|
||||
#define INT_OTG_IN_EP8 259 // OTG IN Endpoint 8 Interrupt
|
||||
#define INT_OTG_OUT_EP0 260 // OTG OUT Endpoint 0 Interrupt
|
||||
#define INT_OTG_OUT_EP1 261 // OTG OUT Endpoint 1 Interrupt
|
||||
#define INT_OTG_OUT_EP2 262 // OTG OUT Endpoint 2 Interrupt
|
||||
#define INT_OTG_OUT_EP3 263 // OTG OUT Endpoint 3 Interrupt
|
||||
#define INT_OTG_OUT_EP4 264 // OTG OUT Endpoint 4 Interrupt
|
||||
#define INT_OTG_OUT_EP5 265 // OTG OUT Endpoint 5 Interrupt
|
||||
#define INT_OTG_OUT_EP6 266 // OTG OUT Endpoint 6 Interrupt
|
||||
#define INT_OTG_OUT_EP7 267 // OTG OUT Endpoint 7 Interrupt
|
||||
#define INT_OTG_OUT_EP8 268 // OTG OUT Endpoint 8 Interrupt
|
||||
|
||||
// Reserved 269
|
||||
|
||||
#define PCIE_LINK0 270 // PCIE Link 0 Interrupt
|
||||
#define PCIE_LINK0_DART 271 // PCIE Link 0 DART Interrupt
|
||||
#define PCIE_LINK0_MMU 272 // PCIE Link 0 MMU Interrupt
|
||||
#define PCIE_LINK1 273 // PCIE Link 1 Interrupt
|
||||
#define PCIE_LINK1_DART 274 // PCIE Link 1 DART Interrupt
|
||||
#define PCIE_LINK1_MMU 275 // PCIE Link 1 MMU Interrupt
|
||||
#define PCIE_LINK2 276 // PCIE Link 1 Interrupt
|
||||
#define PCIE_LINK2_DART 277 // PCIE Link 1 DART Interrupt
|
||||
#define PCIE_LINK2_MMU 278 // PCIE Link 1 MMU Interrupt
|
||||
#define PCIE_LINK3 279 // PCIE Link 1 Interrupt
|
||||
#define PCIE_LINK3_DART 280 // PCIE Link 1 DART Interrupt
|
||||
#define PCIE_LINK3_MMU 281 // PCIE Link 1 MMU Interrupt
|
||||
|
||||
// Reserved 282 - 287
|
||||
|
||||
#define PCIE_MSI0 288 // PCIE MSI 0 Interrupt
|
||||
#define PCIE_MSI1 289 // PCIE MSI 1 Interrupt
|
||||
#define PCIE_MSI2 290 // PCIE MSI 2 Interrupt
|
||||
#define PCIE_MSI3 291 // PCIE MSI 3 Interrupt
|
||||
#define PCIE_MSI4 292 // PCIE MSI 4 Interrupt
|
||||
#define PCIE_MSI5 293 // PCIE MSI 5 Interrupt
|
||||
#define PCIE_MSI6 294 // PCIE MSI 6 Interrupt
|
||||
#define PCIE_MSI7 295 // PCIE MSI 7 Interrupt
|
||||
#define PCIE_MSI8 296 // PCIE MSI 8 Interrupt
|
||||
#define PCIE_MSI9 297 // PCIE MSI 9 Interrupt
|
||||
#define PCIE_MSI10 298 // PCIE MSI 10 Interrupt
|
||||
#define PCIE_MSI11 299 // PCIE MSI 11 Interrupt
|
||||
#define PCIE_MSI12 300 // PCIE MSI 12 Interrupt
|
||||
#define PCIE_MSI13 301 // PCIE MSI 13 Interrupt
|
||||
#define PCIE_MSI14 302 // PCIE MSI 14 Interrupt
|
||||
#define PCIE_MSI15 303 // PCIE MSI 15 Interrupt
|
||||
#define PCIE_MSI16 304 // PCIE MSI 16 Interrupt
|
||||
#define PCIE_MSI17 305 // PCIE MSI 17 Interrupt
|
||||
#define PCIE_MSI18 306 // PCIE MSI 18 Interrupt
|
||||
#define PCIE_MSI19 307 // PCIE MSI 19 Interrupt
|
||||
#define PCIE_MSI20 308 // PCIE MSI 20 Interrupt
|
||||
#define PCIE_MSI21 309 // PCIE MSI 21 Interrupt
|
||||
#define PCIE_MSI22 310 // PCIE MSI 22 Interrupt
|
||||
#define PCIE_MSI23 311 // PCIE MSI 23 Interrupt
|
||||
#define PCIE_MSI24 312 // PCIE MSI 24 Interrupt
|
||||
#define PCIE_MSI25 313 // PCIE MSI 25 Interrupt
|
||||
#define PCIE_MSI26 314 // PCIE MSI 26 Interrupt
|
||||
#define PCIE_MSI27 315 // PCIE MSI 27 Interrupt
|
||||
#define PCIE_MSI28 316 // PCIE MSI 28 Interrupt
|
||||
#define PCIE_MSI29 317 // PCIE MSI 29 Interrupt
|
||||
#define PCIE_MSI30 318 // PCIE MSI 30 Interrupt
|
||||
#define PCIE_MSI31 319 // PCIE MSI 31 Interrupt
|
||||
|
||||
#else
|
||||
#error Unsupported Platform
|
||||
#endif
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWISR_H */
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWREGBASE_H
|
||||
#define __PLATFORM_SOC_HWREGBASE_H
|
||||
|
||||
#include <platform.h>
|
||||
#include <platform/memmap.h>
|
||||
|
||||
// Common definitions for T801x SoCs go here. Put everything into the
|
||||
// SoC-specific header until there is another chip in the family.
|
||||
|
||||
#include SUB_PLATFORM_SOC_HEADER(hwregbase)
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWREGBASE_H */
|
||||
@@ -0,0 +1,237 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWREGBASE_T8010_H
|
||||
#define __PLATFORM_SOC_HWREGBASE_T8010_H
|
||||
|
||||
#include <platform/memmap.h>
|
||||
|
||||
#if !SUB_PLATFORM_T8010
|
||||
#error "Include only for T8010"
|
||||
#endif
|
||||
|
||||
#define DCS_REG_VERSION (4)
|
||||
|
||||
/* T8010 Reg Base Definitions */
|
||||
|
||||
#define AMCC_BASE_ADDR(_n) (IO_BASE + ((_n) * 0x000200000)) // AMCC Config
|
||||
#define NUM_AMCCS (1)
|
||||
|
||||
#define DCS_BASE_ADDR (IO_BASE + 0x000200000) // DCS
|
||||
|
||||
#define DCS_SPACING (0x40000)
|
||||
#define SPLLCTRL_SPACING (0x00000C000)
|
||||
#define AMP_CA_SPACING (0x000020000)
|
||||
#define AMP_DQ_SPACING (0x000008000)
|
||||
#define AMP_SPACING (DCS_SPACING)
|
||||
#define AMP_BASE_ADDR (DCS_BASE_ADDR + AMP_CA_SPACING)
|
||||
#define AMPH_BASE_ADDR (AMP_BASE_ADDR + 3 * AMP_DQ_SPACING)
|
||||
|
||||
#define SWTCH_FAB_BASE_ADDR (IO_BASE + 0x000800000) // Switch Fabric Config
|
||||
|
||||
#define CP_COM_BASE_ADDR (IO_BASE + 0x000D00000) // CP Common Registers
|
||||
#define CP_COM_INT_BASE_ADDR (CP_COM_BASE_ADDR + 0x10000) // CP Common Interrupt Config Registers
|
||||
|
||||
#define CP_0_DT_DBG_CA0_ADDR (IO_BASE + 0x000D40000) // Dup Tag Debug backdoor Ram Access For CP0/CA0
|
||||
#define CP_1_DT_DBG_CA0_ADDR (IO_BASE + 0x000E40000) // Dup Tag Debug backdoor Ram Access For CP1/CA0
|
||||
|
||||
#define ACC_BASE_ADDR (IO_BASE + 0x002000000) // Apple Compute Complex
|
||||
#define CCC_CPU0_SYS_BASE_ADDR (IO_BASE + 0x002000000) // Hurricane/Zephyr CPU0 Implementation Specific Registers
|
||||
#define CCC_CPU1_SYS_BASE_ADDR (IO_BASE + 0x002100000) // Hurricane/Zephyr CPU1 Implementation Specific Registers
|
||||
|
||||
#define SOC_BUSMUX_BASE_ADDR (IO_BASE + 0x004000000) // AF SoC BusMux Config
|
||||
|
||||
#define DISP0_FAB_BASE_ADDR (IO_BASE + 0x006100000) // DisplayPipe0 AF and AXI Config
|
||||
#define DISP0_BASE_ADDR (IO_BASE + 0x006200000) // DisplayPipe0
|
||||
#define DISP0_ADP_BASE_ADDR (IO_BASE + 0x006200000) // DisplayPipe0 Configuration
|
||||
#define DISP0_SMMU_BASE_ADDR (IO_BASE + 0x006300000) // DisplayPipe0 SMMU Configuration
|
||||
#define DISP0_DART_BASE_ADDR (IO_BASE + 0x006304000) // DisplayPipe0 DART Configuration
|
||||
#define DISP0_ADBE_BASE_ADDR (IO_BASE + 0x006400000) // DisplayPipe0 Backend Config
|
||||
#define DISP0_AAP_BASE_ADDR (IO_BASE + 0x006440000) // DisplayPipe0 Ambient-Adaptive Pixel Config
|
||||
#define DISP0_DPB_BASE_ADDR (IO_BASE + 0x006480000) // DisplayPipe0 Dynamic Pixel Backlight Config
|
||||
#define DISP0_WPC_BASE_ADDR (IO_BASE + 0x0064C0000) // DisplayPipe0 White Point Correction Config
|
||||
#define DISP0_PRC_BASE_ADDR (IO_BASE + 0x006500000) // DisplayPipe0 Panel Regamma Correction Config
|
||||
#define DISP0_DITHER_BASE_ADDR (IO_BASE + 0x006540000) // DisplayPipe0 Dither Config
|
||||
#define DISP0_CDRR_BASE_ADDR (IO_BASE + 0x0065C0000) // DisplayPipe0 Content Dependent Refresh Rate Statistics Config
|
||||
#define DISP0_ADP_PARAM_FIFO_BASE_ADDR (IO_BASE + 0x006600000) // DisplayPipe0 Backend Parameter Buffer Config
|
||||
#define DITHER_BASE_ADDR DISP0_DITHER_BASE_ADDR
|
||||
#define DITHER_VERSION (3)
|
||||
|
||||
#define DISP0_DPTX_BASE_ADDR (IO_BASE + 0x006780000) // DisplayPipe0 DisplayPort TX Config
|
||||
#define DISP0_MIPI_DSI_BASE_ADDR (IO_BASE + 0x006800000) // DisplayPipe0 MIPI DSI Config
|
||||
|
||||
#define ASIO_MISC_0_BASE_ADDR (IO_BASE + 0x00A000000) // ASIO Shim0 Misc Registers
|
||||
#define ASIO_AUD_MUX_BASE_ADDR (IO_BASE + 0x00A003000) // ASIO Audio I2S Switch Config
|
||||
#define ASIO_SPI_BASE_ADDR (IO_BASE + 0x00A080000) // ASIO SPI Device
|
||||
#define ASIO_SPI_TX_CFG_BASE_ADDR (IO_BASE + 0x00A081000) // ASIO SPI TX DMA Channel
|
||||
#define ASIO_SPI_RX_CFG_BASE_ADDR (IO_BASE + 0x00A081800) // ASIO SPI RX DMA Channel
|
||||
#define ASIO_SPI_TX_FIFO_BASE_ADDR (IO_BASE + 0x00A082000) // ASIO SPI TX DMA Shim FIFO
|
||||
#define ASIO_SPI_RX_FIFO_BASE_ADDR (IO_BASE + 0x00A083000) // ASIO SPI RX DMA Shim FIFO
|
||||
#define ASIO_MCA_BASE_ADDR (IO_BASE + 0x00A0A0000) // ASIO MCA Device
|
||||
#define ASIO_MCA_TX_CFG_BASE_ADDR (IO_BASE + 0x00A0A1000) // ASIO MCA TX DMA Channel
|
||||
#define ASIO_MCA_RX_CFG_BASE_ADDR (IO_BASE + 0x00A0A1800) // ASIO MCA RX DMA Channel
|
||||
#define ASIO_MCA_TX_FIFO_BASE_ADDR (IO_BASE + 0x00A0A2000) // ASIO MCA TX DMA Shim FIFO
|
||||
#define ASIO_MCA_RX_FIFO_BASE_ADDR (IO_BASE + 0x00A0A3000) // ASIO MCA RX DMA Shim FIFO
|
||||
#define ASIO_PDM_BASE_ADDR (IO_BASE + 0x00A0B4000) // ASIO PDM Device
|
||||
#define ASIO_PDM_DEMOD_BASE_ADDR (IO_BASE + 0x00A0B4000)
|
||||
#define ASIO_PDM_TX_CFG_BASE_ADDR (IO_BASE + 0x00A0B5000)
|
||||
#define ASIO_PDM_RX_CFG_BASE_ADDR (IO_BASE + 0x00A0B5800)
|
||||
#define ASIO_PDM_TX_FIFO_BASE_ADDR (IO_BASE + 0x00A0BC000)
|
||||
#define ASIO_PDM_RX_FIFO_BASE_ADDR (IO_BASE + 0x00A0B7000)
|
||||
#define ASIO_UART_BASE_ADDR (IO_BASE + 0x00A0C0000) // ASIO UART Device
|
||||
#define ASIO_UART_TX_CFG_BASE_ADDR (IO_BASE + 0x00A0C1000) // ASIO UART TX DMA Channel
|
||||
#define ASIO_UART_RX_CFG_BASE_ADDR (IO_BASE + 0x00A0C1800) // ASIO UART RX DMA Channel
|
||||
#define ASIO_UART_TX_FIFO_BASE_ADDR (IO_BASE + 0x00A0C2000) // ASIO UART TX DMA Shim FIFO
|
||||
#define ASIO_UART_RX_FIFO_BASE_ADDR (IO_BASE + 0x00A0C3000) // ASIO UART RX DMA Shim FIFO
|
||||
#define ASIO_MISC_1_BASE_ADDR (IO_BASE + 0x00A100000) // ASIO Shim1 Misc Registers
|
||||
#define ASIO_AES_BASE_ADDR (IO_BASE + 0x00A108000) // ASIO AES Config and DMA Registers
|
||||
#define ASIO_SMB_0_BASE_ADDR (IO_BASE + 0x00A110000) // ASIO I2C 0 Device
|
||||
#define ASIO_SMB_1_BASE_ADDR (IO_BASE + 0x00A111000) // ASIO I2C 1 Device
|
||||
#define ASIO_SMB_2_BASE_ADDR (IO_BASE + 0x00A112000) // ASIO I2C 2 Device
|
||||
#define ASIO_SMB_3_BASE_ADDR (IO_BASE + 0x00A113000) // ASIO I2C 3 Device
|
||||
#define ASIO_PWM_BASE_ADDR (IO_BASE + 0x00A118000) // ASIO PWM
|
||||
#define ASIO_PL301_BASE_ADDR (IO_BASE + 0x00A140000) // ASIO PL301
|
||||
#define ASIO_PL301_AES_BASE_ADDR (IO_BASE + 0x00A141000) // ASIO PL301 AES
|
||||
#define ASIO_DNSZ_AXI_0_BASE_ADDR (IO_BASE + 0x00A142000) // ASIO Downsizer 0 Configuration Registers
|
||||
#define ASIO_DNSZ_AXI_1_BASE_ADDR (IO_BASE + 0x00A143000) // ASIO Downsizer 1 Configuration Registers
|
||||
#define ASIO_AKF_BASE_ADDR (IO_BASE + 0x00AE00000) // ASIO KF Wrapper
|
||||
#define ASIO_AKF_DEBUG_BASE_ADDR (IO_BASE + 0x00AE20000) // ASIO KF Debug Wrapper
|
||||
|
||||
#define AUSB_CTL_REG_BASE_ADDR (IO_BASE + 0x00C000000) // USBCTL Config
|
||||
#define AUSB_CTL_USB20PHY_REG_OFFSET (0x30) // USB20PHY Register offset within AUSBCTL registers
|
||||
#define AUSB_OTG_BASE_ADDR (IO_BASE + 0x00C100000) // USB OTG
|
||||
#define AUSB_USB2HOST0_EHCI_BASE_ADDR (IO_BASE + 0x00C200000) // EHCI0
|
||||
#define AUSB_USB2HOST0_OHCI_BASE_ADDR (IO_BASE + 0x00C300000) // OHCI0
|
||||
#define AUSB_PL301_BASE_ADDR (IO_BASE + 0x00C800000) // AUSB PL301 4-AHB Master to 1-AXI Slave
|
||||
#define AUSB_PL301_WIDGET_BASE_ADDR (IO_BASE + 0x00C900000) // AUSB PL301 Widget
|
||||
#define AUSB_INTR2AXI_BASE_ADDR (IO_BASE + 0x00CA00000) // AUSB Interrupt to AXI Widget
|
||||
#define AUSB_AFIFO_WIDGET_BASE_ADDR (IO_BASE + 0x00CB00000) // AUSB Async FIFO
|
||||
|
||||
#define ASEP_AKF_BASE_ADDR (IO_BASE + 0x00DA00000) // ASEP AKF control Registers
|
||||
|
||||
#define PMGR_BASE_ADDR (IO_BASE + 0x00E000000) // PMGR
|
||||
#define PMS_CRS_BASE_ADDR (IO_BASE + 0x00E400000) // PMS control registers
|
||||
|
||||
#define AIC_BASE_ADDR (IO_BASE + 0x00E100000) // AIC
|
||||
#define AIC_WIRE_VIRT_BASE_ADDR (IO_BASE + 0x00E110000) // AIC Wrapper
|
||||
|
||||
#define DWI_BASE_ADDR (IO_BASE + 0x00E200000) // DWI
|
||||
|
||||
#define AFC_AIU_SB_BASE_ADDR (IO_BASE + 0x00F000000) // AFC_AIU_SB
|
||||
|
||||
#define GPIO_BASE_ADDR (IO_BASE + 0x00F100000) // GPIO
|
||||
#define GLBTIMER_BASE_ADDR (IO_BASE + 0x00F140000) // Global Timer
|
||||
|
||||
#define LIO_MEM_PL301_BASE_ADDR (IO_BASE + 0x00F160000) // PL310 for pd_lio memory
|
||||
#define LIO_PIO_PL310_BASE_ADDR (IO_BASE + 0x00F180000) // PL310 for pd_lio PIO
|
||||
#define LIO_DNSZ_AXI_BASE_ADDR (IO_BASE + 0x00F1A0000) // PL310 for pd_lio downsizer
|
||||
|
||||
#define SB_GLUE_REG_BASE (IO_BASE + 0x00f1c0000) // Local registers for south bridge
|
||||
|
||||
#define ERR_REFLECTION_BASE_ADDR (IO_BASE + 0x00FFFC000)
|
||||
|
||||
#define AOP_BASE_ADDR (IO_BASE + 0x010000000)
|
||||
#define AOP_MINIPMGR_BASE_ADDR (IO_BASE + 0x010200000)
|
||||
#define DBG_WRP_BASE_ADDR (IO_BASE + 0x010300000) // Debug Sub-system Config
|
||||
#define AOP_GPIO_BASE_ADDR (IO_BASE + 0x0100f0000)
|
||||
#define AOP_SRAM_BASE_ADDR (IO_BASE + 0x010E00000)
|
||||
#define AOP_RECONFIG_REGION_BASE_ADDR (IO_BASE + 0x010E9B000)
|
||||
#define AOP_RECONFIG_REGION_SIZE (IO_BASE + 0x010EA0000 - AOP_RECONFIG_REGION_BASE_ADDR)
|
||||
#define MEMORY_CALIB_SAVE_BASE_ADDR AOP_SRAM_BASE_ADDR // Temporarily save cold boot memcal results in AOP_SRAM
|
||||
|
||||
#define APCIE_VERSION (2)
|
||||
#define APCIE_COMMON_BASE_ADDR (PCI_REG_BASE + 0x00000000)
|
||||
#define APCIE_COUNTER_BASE_ADDR (PCI_REG_BASE + 0x00004000)
|
||||
#define APCIE_PHY_BASE_ADDR (PCI_REG_BASE + 0x00008000)
|
||||
#define APCIE_CONFIG_BASE_ADDR (PCI_REG_BASE + 0x01000000)
|
||||
#define APCIE_CONFIG_PORT_STRIDE (0x01000000)
|
||||
#define APCIE_PHY_PMA_COMMON_BASE_ADDR (PCI_REG_BASE + 0x0a000000)
|
||||
#define APCIE_PHY_PMA_TX_LANE_BASE_ADDR (PCI_REG_BASE + 0x0a010000)
|
||||
#define APCIE_PHY_PMA_TX_LANE_STRIDE (0x800)
|
||||
#define APCIE_PHY_PMA_RX_LANE_BASE_ADDR (PCI_REG_BASE + 0x0a020000)
|
||||
#define APCIE_PHY_PMA_RX_LANE_STRIDE (0x800)
|
||||
|
||||
/* iBoot Specific Defs */
|
||||
|
||||
#define AKF_VERSION (2)
|
||||
|
||||
#define UART0_BASE_ADDR (ASIO_UART_BASE_ADDR)
|
||||
#define UART1_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x04000)
|
||||
#define UART2_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x08000)
|
||||
#define UART3_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x0C000)
|
||||
#define UART4_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x10000)
|
||||
#define UART5_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x14000)
|
||||
#define UART6_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x18000)
|
||||
#define UARTS_COUNT (7)
|
||||
#define UART_VERSION (1)
|
||||
|
||||
#define SPI0_BASE_ADDR (ASIO_SPI_BASE_ADDR)
|
||||
#define SPI1_BASE_ADDR (ASIO_SPI_BASE_ADDR + 0x04000)
|
||||
#define SPI2_BASE_ADDR (ASIO_SPI_BASE_ADDR + 0x08000)
|
||||
#define SPI_VERSION (1)
|
||||
#define SPIS_COUNT (3)
|
||||
|
||||
#define IIC_BASE_ADDR (ASIO_SMB_0_BASE_ADDR)
|
||||
#define IIC_SPACING (0x00001000)
|
||||
#define IICS_COUNT (4)
|
||||
|
||||
#define USBPHY_VERSION (4)
|
||||
|
||||
#define DSIM_BASE_ADDR (DISP0_MIPI_DSI_BASE_ADDR)
|
||||
#define DSIM_LANE_COUNT (4)
|
||||
#define DSIM_VERSION (2)
|
||||
|
||||
#define EDP_BASE_ADDR (DISP0_DPTX_BASE_ADDR)
|
||||
#define DP_BASE_ADDR (DISP0_DPTX_BASE_ADDR)
|
||||
#define LPDP_PHY_BASE_ADDR (DISP0_DPTX_BASE_ADDR + 0x080000)
|
||||
#define DISPLAYPORT_VERSION (3)
|
||||
|
||||
#define ADBE_DISPLAYPIPE_BASE_ADDR (DISP0_BASE_ADDR)
|
||||
#define DISP_VERSION (5)
|
||||
#define ADP_VERSION (2)
|
||||
|
||||
#define GPIOC_COUNT (2)
|
||||
#define GPIO_VERSION (6)
|
||||
#define GPIO_0_GROUP_COUNT (26)
|
||||
#define GPIO_1_BASE_ADDR (AOP_GPIO_BASE_ADDR)
|
||||
#define GPIO_1_GROUP_COUNT (11)
|
||||
#define GPIO_AP (GPIOC_0)
|
||||
#define GPIO_AOP (GPIOC_1)
|
||||
#define GPIO_GROUP_COUNT (GPIO_0_GROUP_COUNT)
|
||||
#define GPIO_PAD_SPI (GPIO_GROUP_COUNT)
|
||||
|
||||
#define AIC_VERSION (3)
|
||||
#define AIC_INT_COUNT (320)
|
||||
|
||||
#define PMGR_WDG_VERSION (1)
|
||||
|
||||
#define USBOTG_BASE_ADDR (AUSB_OTG_BASE_ADDR)
|
||||
|
||||
#define APCIE_NUM_LINKS (4)
|
||||
|
||||
#define DART0_BASE_ADDR (PCI_REG_BASE + 0x1008000)
|
||||
#define DART0_ADDR_MASK (0x3FFFFFFF)
|
||||
#define DART1_BASE_ADDR (PCI_REG_BASE + 0x2008000)
|
||||
#define DART1_ADDR_MASK (0x3FFFFFFF)
|
||||
#define DART2_BASE_ADDR (PCI_REG_BASE + 0x3008000)
|
||||
#define DART2_ADDR_MASK (0x3FFFFFFF)
|
||||
#define DART3_BASE_ADDR (PCI_REG_BASE + 0x4008000)
|
||||
#define DART3_ADDR_MASK (0x3FFFFFFF)
|
||||
|
||||
#define PCIE_PORT0_DART_ID (0)
|
||||
#define PCIE_PORT1_DART_ID (1)
|
||||
#define PCIE_PORT2_DART_ID (2)
|
||||
#define PCIE_PORT3_DART_ID (3)
|
||||
#define NUM_DARTS (4)
|
||||
|
||||
#define AES_AP_BASE_ADDR (ASIO_AES_BASE_ADDR)
|
||||
#define AES_AP_VERSION (0)
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWREGBASE_T8010_H */
|
||||
@@ -0,0 +1,80 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_MIU_H
|
||||
#define __PLATFORM_SOC_MIU_H
|
||||
|
||||
#include <lib/devicetree.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include SUB_PLATFORM_SPDS_HEADER(afc_aiu_sb)
|
||||
#include SUB_PLATFORM_SPDS_HEADER(amcc)
|
||||
#include SUB_PLATFORM_SPDS_HEADER(cp_com)
|
||||
#include SUB_PLATFORM_SPDS_HEADER(minipmgr)
|
||||
#include SUB_PLATFORM_SPDS_HEADER(misc1)
|
||||
#include SUB_PLATFORM_SPDS_HEADER(pms_csr)
|
||||
#include SUB_PLATFORM_SPDS_HEADER(sb_glue)
|
||||
#include SUB_PLATFORM_SPDS_HEADER(socbusmux)
|
||||
#include SUB_PLATFORM_SPDS_HEADER(switchfabric)
|
||||
|
||||
// https://seg-docs.ecs.apple.com/projects/cayman//release/UserManual/regs/MINIPMGR.html?baseaddr=0x210200000#MINIPMGR_SECURITY
|
||||
#define rSECUREROMCTRL_ROMADDRREMAP (*(volatile u_int32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_MCC_ROMADDRREMAP_OFFSET))
|
||||
#define SECUREROMCTRL_ROMADDRREMAP_SRAM (1 << 0)
|
||||
#define SECUREROMCTRL_ROMADDRREMAP_SDRAM (1 << 1)
|
||||
|
||||
// https://seg-docs.ecs.apple.com/projects/cayman//release/UserManual/regs/amcc.html?baseaddr=0x200000000
|
||||
#define MCCLOCKREGION_TZ0BASEADDR(_n) (AMCC_BASE_ADDR(_n) + AMCC_MCC_LOCK_REGION_TZ0_BASE_ADDR_OFFSET)
|
||||
#define MCCLOCKREGION_TZ0ENDADDR(_n) (AMCC_BASE_ADDR(_n) + AMCC_MCC_LOCK_REGION_TZ0_END_ADDR_OFFSET)
|
||||
#define MCCLOCKREGION_TZ0LOCK(_n) (AMCC_BASE_ADDR(_n) + AMCC_MCC_LOCK_REGION_TZ0_LOCK_OFFSET)
|
||||
|
||||
#define rMCCLOCKREGION_TZ0BASEADDR(_n) (*(volatile u_int32_t *)(MCCLOCKREGION_TZ0BASEADDR(_n)))
|
||||
#define rMCCLOCKREGION_TZ0ENDADDR(_n) (*(volatile u_int32_t *)(MCCLOCKREGION_TZ0ENDADDR(_n)))
|
||||
#define rMCCLOCKREGION_TZ0LOCK(_n) (*(volatile u_int32_t *)(MCCLOCKREGION_TZ0LOCK(_n)))
|
||||
|
||||
#define rAMCC_IRERRDBG_INTEN(_n) (*(volatile uint32_t *)(AMCC_BASE_ADDR(_n) + AMCC_IRERRDBG_INTEN_OFFSET))
|
||||
#define rAMCC_IRERRDBG_INTSTS(_n) (*(volatile uint32_t *)(AMCC_BASE_ADDR(_n) + AMCC_IRERRDBG_INTSTS_OFFSET))
|
||||
#define rAMCC_IRERRDBG_MCC_AF_ERR_LOG2(_n) (*(volatile uint32_t *)(AMCC_BASE_ADDR(_n) + AMCC_IRERRDBG_MCC_AF_ERR_LOG2_OFFSET))
|
||||
|
||||
// https://seg-docs.ecs.apple.com/projects/cayman//release/UserManual/regs/SWITCHFABRIC.html?baseaddr=0x200800000
|
||||
#define rSWITCH_FAB_CPG_CNTL (*(volatile u_int32_t *)(SWTCH_FAB_BASE_ADDR + SWITCHFABRIC_BLK_REGS_CPG_CNTL_OFFSET))
|
||||
|
||||
// https://seg-docs.ecs.apple.com/projects/cayman//release/UserManual/regs/CP_COM.html?baseaddr=0x200d00000
|
||||
#define rCP_COM_DYN_CLK_GATING_CTRL (*(volatile u_int32_t *)(CP_COM_BASE_ADDR + CP_COM_CFG_DYN_CLK_GATE_CTRL_OFFSET))
|
||||
#define rCP_COM_INT_NORM_REQUEST (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CP_COM_INT_NORM_REQUEST_OFFSET))
|
||||
#define rCP_COM_INT_NORM_MASK_SET (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CP_COM_INT_NORM_MASK_SET_OFFSET))
|
||||
#define rCP_COM_INT_NORM_MASK_CLR (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CP_COM_INT_NORM_MASK_CLR_OFFSET))
|
||||
|
||||
// https://seg-docs.ecs.apple.com/projects/cayman//release/UserManual/regs/SOCBUSMUX.html?baseaddr=0x204000000
|
||||
#define rSOCBUSMUX_CPG_CNTL (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + SOCBUSMUX_BLK_REGS_CPG_CNTL_OFFSET))
|
||||
|
||||
// https://seg-docs.ecs.apple.com/projects/cayman//release/UserManual/regs/Misc1.html?baseaddr=0x20a100000
|
||||
#define rASIO_CLK_CTRL (*(volatile u_int32_t *)(ASIO_MISC_1_BASE_ADDR + MISC1_BLK_CLOCK_CONTROL_OFFSET))
|
||||
|
||||
// https://seg-docs.ecs.apple.com/projects/cayman//release/UserManual/regs/pmsCSR.html?baseaddr=0x20e400000
|
||||
#define rPMS_SRAM_CPG_CTRL (*(volatile u_int32_t *)(PMS_CRS_BASE_ADDR + PMS_CSR_PMSCSR_PMP_PMS_SRAM_CPG_CTRL_OFFSET))
|
||||
#define rPMP_CPG_CTRL (*(volatile u_int32_t *)(PMS_CRS_BASE_ADDR + PMS_CSR_PMSCSR_PMP_PMP_CPG_CTRL_OFFSET))
|
||||
#define rPMS_CPG_CTRL (*(volatile u_int32_t *)(PMS_CRS_BASE_ADDR + PMS_CSR_PMSCSR_PMP_PMS_CPG_CTRL_OFFSET))
|
||||
|
||||
// https://seg-docs.ecs.apple.com/projects/cayman//release/UserManual/regs/afc_aiu_sb.html?baseaddr=0x20f000000
|
||||
#define rAIU_SB_CPG_CNTL (*(volatile u_int32_t *)(AFC_AIU_SB_BASE_ADDR + AFC_AIU_SB_SELF_OFFSET))
|
||||
|
||||
// https://seg-docs.ecs.apple.com/projects/cayman//release/UserManual/regs/DYNAMIC_CLK_GATING.html?baseaddr=0x20f1c0000
|
||||
#define rDYN_CLK_GATING (*(volatile u_int32_t *)(SB_GLUE_REG_BASE + SB_GLUE_BLK_DYNAMIC_CLK_GATING_OFFSET))
|
||||
#define rDYN_CLK_GATING2 (*(volatile u_int32_t *)(SB_GLUE_REG_BASE + SB_GLUE_BLK_DYNAMIC_CLK_GATING2_OFFSET))
|
||||
|
||||
enum remap_select {
|
||||
REMAP_SRAM = 0,
|
||||
REMAP_SDRAM
|
||||
};
|
||||
|
||||
extern void miu_select_remap(enum remap_select sel);
|
||||
extern void miu_bypass_prep(void);
|
||||
extern void miu_update_device_tree(DTNode *pmgr_node);
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_MIU_H */
|
||||
@@ -0,0 +1,52 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_OPERATING_POINT_H
|
||||
#define __PLATFORM_SOC_OPERATING_POINT_H
|
||||
|
||||
#include <platform/soc/chipid.h>
|
||||
struct operating_point_params {
|
||||
union {
|
||||
struct {
|
||||
uint64_t voltage_index:9;
|
||||
uint64_t bypass:1;
|
||||
uint64_t clkSrc:1;
|
||||
uint64_t fcwInt:8;
|
||||
uint64_t fcwFrac:3;
|
||||
uint64_t pstDivS:4;
|
||||
uint64_t migDivS:4;
|
||||
uint64_t coreTyp:2;
|
||||
uint64_t biuDiv4HiVol:3;
|
||||
uint64_t biuDiv4LoVol:3;
|
||||
uint64_t dvmrMaxWgt:7;
|
||||
uint64_t iexrfCfgWrData:2;
|
||||
uint64_t iexrfCfgWrIdxa:2;
|
||||
uint64_t iexrfCfgWrIdxb:2;
|
||||
uint64_t exrfCfgWrIdxmuxsel:2;
|
||||
} cpu;
|
||||
struct {
|
||||
uint64_t voltage_index:9;
|
||||
uint64_t preDivP:6;
|
||||
uint64_t fbkDivM:9;
|
||||
uint64_t pstDivS:4;
|
||||
} gpu;
|
||||
struct {
|
||||
uint64_t voltage_index:9; // must contains CHIPID_MAX
|
||||
uint64_t chip_id:16;
|
||||
uint64_t voltage_type:3;
|
||||
uint64_t reserved:34;
|
||||
};
|
||||
};
|
||||
};
|
||||
extern const struct operating_point_params *operating_point_get_params(enum chipid_voltage_index voltage_index, enum chipid_voltage_type voltage_type);
|
||||
|
||||
|
||||
|
||||
#endif /* __PLATFORM_SOC_CHIPID_H */
|
||||
@@ -0,0 +1,581 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_PMGR_H
|
||||
#define __PLATFORM_SOC_PMGR_H
|
||||
|
||||
#include <lib/devicetree.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <soc/t8010/a0/acc.h>
|
||||
#include <soc/t8010/a0/minipmgr.h>
|
||||
#include <soc/t8010/a0/pmgr.h>
|
||||
|
||||
////////////////////////////////////////////////////////////
|
||||
//
|
||||
// PMGR specific
|
||||
//
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
enum coreTyp {
|
||||
kACC_CORETYP_ECORE,
|
||||
kACC_CORETYP_PCORE,
|
||||
kACC_CORETYP_FUSED
|
||||
};
|
||||
|
||||
#define PMGR_PLL_COUNT (7)
|
||||
|
||||
#define PMGR_PLL_REG_STRIDE (PMGR_PLL1_OFFSET - PMGR_PLL0_OFFSET)
|
||||
|
||||
#define rPMGR_PLL_CTL(_p) (*(volatile uint32_t *)(PMGR_BASE_ADDR + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
|
||||
#define PMGR_PLL_ENABLE (1 << PMGR_PLL0_CTL_ENABLE_SHIFT)
|
||||
#define PMGR_PLL_LOAD (1 << PMGR_PLL0_CTL_LOAD_SHIFT)
|
||||
#define PMGR_PLL_BYPASS (1 << PMGR_PLL0_CTL_BYPASS_SHIFT)
|
||||
#define PMGR_PLL_PENDING (1 << PMGR_PLL0_CTL_PLL_PENDING_SHIFT)
|
||||
#define PMGR_PLL_M_SHIFT PMGR_PLL0_CTL_FB_DIVN_SHIFT
|
||||
#define PMGR_PLL_M_MASK PMGR_PLL0_CTL_FB_DIVN_SMASK
|
||||
#define PMGR_PLL_P_SHIFT PMGR_PLL0_CTL_PRE_DIVN_SHIFT
|
||||
#define PMGR_PLL_P_MASK PMGR_PLL0_CTL_PRE_DIVN_SMASK
|
||||
#define PMGR_PLL_S_SHIFT PMGR_PLL0_CTL_OP_DIVN_SHIFT
|
||||
#define PMGR_PLL_S_MASK PMGR_PLL0_CTL_OP_DIVN_SMASK
|
||||
#define PMGR_PLL_PCIE_S_MASK PMGR_PLL_PCIE_CTL_OP_DIVN_SMASK
|
||||
#define PMGR_PLL_M(_m) (((_m) & PMGR_PLL_M_MASK) << PMGR_PLL_M_SHIFT)
|
||||
#define PMGR_PLL_P(_p) (((_p) & PMGR_PLL_P_MASK) << PMGR_PLL_P_SHIFT)
|
||||
#define PMGR_PLL_S(_s) (((_s) & PMGR_PLL_S_MASK) << PMGR_PLL_S_SHIFT)
|
||||
#define PMGR_PLL_PCIE_S(_s) (((_s) & PMGR_PLL_PCIE_S_MASK) << PMGR_PLL_S_SHIFT)
|
||||
#define PMGR_PLL_FREQ(_m, _p, _s) ((((_m) * OSC_FREQ) / (_p))/((_s) + 1))
|
||||
|
||||
#define rPMGR_PLL_CFG(_p) (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0004 + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
|
||||
#define PMGR_PLL_OFF_MODE(_n) PMGR_PLL0_CFG_OFF_MODE_INSRT(_n)
|
||||
#define PMGR_PLL_OFF_MODE_RESET (0)
|
||||
#define PMGR_PLL_OFF_MODE_CLOCK_GATED (1)
|
||||
#define PMGR_PLL_OFF_MODE_POWER_DOWN (2)
|
||||
#define PMGR_PLL_LOCK_MODE(_n) PMGR_PLL0_CFG_LOCK_MODE_INSRT(_n)
|
||||
#define PMGR_PLL_LOCK_MODE_COUNTER (0)
|
||||
#define PMGR_PLL_LOCK_MODE_LOCK (1)
|
||||
#define PMGR_PLL_AUTO_DISABLE (1 << PMGR_PLL0_CFG_AUTO_DISABLE_SHIFT)
|
||||
#define PMGR_PLL_RELOCK_MODE_SHIFT PMGR_PLL0_CFG_RELOCK_MODE_SHIFT
|
||||
#define PMGR_PLL_RELOCK_MODE_MASK PMGR_PLL0_CFG_RELOCK_MODE_SMASK
|
||||
#define PMGR_PLL_RELOCK_MODE_STOP (0)
|
||||
#define PMGR_PLL_RELOCK_MODE_BYPASS (1)
|
||||
#define PMGR_PLL_FRAC_LOCK_TIME(_n) PMGR_PLL0_CFG_FRAC_LOCK_TIME_INSRT(_n)
|
||||
#define PMGR_PLL_LOCK_TIME(_n) PMGR_PLL0_CFG_LOCK_TIME_INSRT(_n)
|
||||
|
||||
#define rPMGR_PLL_ANA_PARAMS1(_p) (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x000c + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
|
||||
#define rPMGR_PLL_ANA_PARAMS2(_p) (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0010 + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
|
||||
#define rPMGR_PLL_ANA_PARAMS3(_p) (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0014 + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
|
||||
|
||||
#define rPMGR_PLL_DEBUG1(_p) (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0014 + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
|
||||
#define PMGR_PLL_DEBUG1_RESERVE_IN_SHIFT (20)
|
||||
#define PMGR_PLL_DEBUG1_RESERVE_IN_MASK (0x3f)
|
||||
|
||||
#define rPMGR_PLL_PCIE_DELAY_CTL0(_p) (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0028 + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
|
||||
|
||||
#define rPMGR_CLK_CFG(_x) (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_CLKCFG_##_x##_CLK_CFG_OFFSET))
|
||||
|
||||
#define PMGR_CLK_CFG_ENABLE (1 << 31)
|
||||
#define PMGR_CLK_CFG_PENDING (1 << 30)
|
||||
#define PMGR_CLK_CFG_PENDING_SHIFT (30)
|
||||
#define PMGR_CLK_CFG_SRC_SEL_MASK (0xF)
|
||||
#define PMGR_CLK_CFG_SRC_SEL_SHIFT (24)
|
||||
#define PMGR_CLK_CFG_DIVISOR_MASK (0x3F)
|
||||
|
||||
#define PMGR_SPARE_COUNT (7)
|
||||
|
||||
#define rPMGR_CLK_DIVIDER_ACG_CFG (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_CLKCFG_CLK_DIVIDER_ACG_CFG_OFFSET))
|
||||
|
||||
#define PMGR_NCO_REG_STRIDE (PMGR_NCO_1_CLK_CFG_OFFSET - PMGR_NCO_0_CLK_CFG_OFFSET)
|
||||
|
||||
#define rPMGR_NCO_CLK_CFG(_n) (*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * PMGR_NCO_REG_STRIDE + PMGR_NCO_0_CLK_CFG_OFFSET))
|
||||
#define rPMGR_NCO_DIV_INT(_n) (*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * PMGR_NCO_REG_STRIDE + PMGR_NCO_0_DIV_INT_OFFSET))
|
||||
#define rPMGR_NCO_DIV_FRAC_N1(_n) (*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * PMGR_NCO_REG_STRIDE + PMGR_NCO_0_DIV_FRAC_N1_OFFSET))
|
||||
#define rPMGR_NCO_DIV_FRAC_N2(_n) (*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * PMGR_NCO_REG_STRIDE + PMGR_NCO_0_DIV_FRAC_N2_OFFSET))
|
||||
#define rPMGR_NCO_DIV_FRAC_PRIME(_n) (*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * PMGR_NCO_REG_STRIDE + PMGR_NCO_0_DIV_FRAC_PRIME_OFFSET))
|
||||
|
||||
#define PMGR_NCO_CLK_CFG_ENABLE (1 << PMGR_NCO_0_CLK_CFG_ENABLE_SHIFT)
|
||||
#define PMGR_NCO_CLK_CFG_PENDING (1 << PMGR_NCO_0_CLK_CFG_PENDING_SHIFT)
|
||||
|
||||
#define PMGR_NUM_NCO (5)
|
||||
|
||||
#define kSOC_PERF_STATE_BYPASS (0)
|
||||
#define kSOC_PERF_STATE_SECUREROM (kSOC_PERF_STATE_BYPASS + 1)
|
||||
#define kSOC_PERF_STATE_IBOOT (kSOC_PERF_STATE_BYPASS + 2)
|
||||
#define kSOC_PERF_STATE_VMIN (kSOC_PERF_STATE_IBOOT + 0)
|
||||
#define kSOC_PERF_STATE_VNOM (kSOC_PERF_STATE_IBOOT + 1)
|
||||
|
||||
#define kSOC_PERF_STATE_VMAX (kSOC_PERF_STATE_VNOM)
|
||||
|
||||
#define kSOC_PERF_STATE_IBOOT_CNT (kSOC_PERF_STATE_VMAX + 1)
|
||||
#define kSOC_PERF_STATE_MAX_CNT (14)
|
||||
|
||||
#define rPMGR_SOC_PERF_STATE_CTL (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SOC_PERF_STATE_CTL_OFFSET))
|
||||
#define PMGR_SOC_PERF_STATE_CTL_PENDING_MASK (1 << PMGR_SOC_PERF_STATE_CTL_PENDING_SHIFT)
|
||||
|
||||
#define PMGR_SOC_PERF_STATE_STRIDE (PMGR_SOC_PERF_STATE_ENTRY_1A_OFFSET - PMGR_SOC_PERF_STATE_ENTRY_0A_OFFSET)
|
||||
|
||||
#define rPMGR_SOC_PERF_STATE_ENTRY_A(_n) (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SOC_PERF_STATE_ENTRY_0A_OFFSET + (_n) * PMGR_SOC_PERF_STATE_STRIDE))
|
||||
#define rPMGR_SOC_PERF_STATE_ENTRY_B(_n) (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SOC_PERF_STATE_ENTRY_0B_OFFSET + (_n) * PMGR_SOC_PERF_STATE_STRIDE))
|
||||
#define rPMGR_SOC_PERF_STATE_ENTRY_C(_n) (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SOC_PERF_STATE_ENTRY_0C_OFFSET + (_n) * PMGR_SOC_PERF_STATE_STRIDE))
|
||||
#define rPMGR_SOC_PERF_STATE_ENTRY_D(_n) (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SOC_PERF_STATE_ENTRY_0D_OFFSET + (_n) * PMGR_SOC_PERF_STATE_STRIDE))
|
||||
|
||||
#define PMGR_SOC_PERF_STATE_ENTRY_MCU_REF_MASK (PMGR_SOC_PERF_STATE_ENTRY_0A_MCU_REF_SRC_SEL_UMASK | PMGR_SOC_PERF_STATE_ENTRY_0A_MCU_REF_CFG_SEL_UMASK)
|
||||
#define PMGR_SOC_PERF_STATE_ENTRY_MCU_REF(_cfg, _src) (PMGR_SOC_PERF_STATE_ENTRY_0A_MCU_REF_SRC_SEL_INSRT(_src) | PMGR_SOC_PERF_STATE_ENTRY_0A_MCU_REF_CFG_SEL_INSRT(_cfg))
|
||||
#define PMGR_SOC_PERF_STATE_ENTRY_VID0(_src) (PMGR_SOC_PERF_STATE_ENTRY_0B_VID0_SRC_SEL_INSRT(_src))
|
||||
#define PMGR_SOC_PERF_STATE_ENTRY_VOLTAGE(_v) (PMGR_SOC_PERF_STATE_ENTRY_0C_VOLTAGE_INSRT(_v))
|
||||
|
||||
#define PMGR_SOC_PERF_STATE_ENTRY_COUNT (16)
|
||||
// First two entries used by AOP Config Engine
|
||||
#define PMGR_SOC_PERF_STATE_FIRST_ENTRY (PMGR_SOC_PERF_STATE_ENTRY_COUNT - kSOC_PERF_STATE_MAX_CNT)
|
||||
#define PMGR_SOC_PERF_STATE_TO_ENTRY(_s) (PMGR_SOC_PERF_STATE_ENTRY_COUNT - (_s) - 1)
|
||||
|
||||
#define kPMGR_GFX_STATE_MAX (16)
|
||||
#define rPMGR_GFX_PERF_STATE_ENTRY_A(_n) (*(volatile uint32_t *)(PMGR_BASE_ADDR + (_n) * 0x10 + PMGR_GFX_PERF_STATE_ENTRY0A_OFFSET))
|
||||
#define rPMGR_GFX_PERF_STATE_ENTRY_B(_n) (*(volatile uint32_t *)(PMGR_BASE_ADDR + (_n) * 0x10 + PMGR_GFX_PERF_STATE_ENTRY0B_OFFSET))
|
||||
#define rPMGR_GFX_PERF_STATE_ENTRY_C(_n) (*(volatile uint32_t *)(PMGR_BASE_ADDR + (_n) * 0x10 + PMGR_GFX_PERF_STATE_ENTRY0C_OFFSET))
|
||||
#define rPMGR_GFX_PERF_STATE_CTL (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_GFX_PERF_STATE_CTL_OFFSET))
|
||||
#define PMGR_GFX_PERF_STATE_CTL_ENABLE (1 << PMGR_GFX_PERF_STATE_CTL_ENABLE_SHIFT)
|
||||
#define rPMGR_GFX_PERF_STATE_SOCHOT (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_GFX_PERF_STATE_SOCHOT_OFFSET))
|
||||
|
||||
#define rPMGR_PS(_x) (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_PS_##_x##_PS_OFFSET))
|
||||
|
||||
#define PMGR_PS_RESET (1 << 31)
|
||||
#define PMGR_PS_AUTO_PM_EN (1 << 28)
|
||||
#define PMGR_PS_FORCE_NOACCESS (1 << 10)
|
||||
#define PMGR_PS_ACTUAL_PS_SHIFT (4)
|
||||
#define PMGR_PS_ACTUAL_PS_MASK (0xF)
|
||||
#define PMGR_PS_MANUAL_PS_MASK (0xF)
|
||||
#define PMGR_PS_RUN_MAX (0xF)
|
||||
#define PMGR_PS_CLOCK_OFF (0x4)
|
||||
#define PMGR_PS_POWER_OFF (0x0)
|
||||
|
||||
#define rPMGR_VOLMAN_CTL (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_CTL_OFFSET))
|
||||
#define rPMGR_VOLMAN_BUCK_MAP (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_BUCK_MAP_OFFSET))
|
||||
#define rPMGR_VOLMAN_SOC_VOLTAGE (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_SOC_VOLTAGE_OFFSET))
|
||||
#define rPMGR_VOLMAN_GFX_SRAM_VOLTAGE (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_GFX_SRAM_VOLTAGE_OFFSET))
|
||||
#define rPMGR_VOLMAN_CPU_SRAM_VOLTAGE (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_CPU_SRAM_VOLTAGE_OFFSET))
|
||||
#define rPMGR_VOLMAN_GFX_VOLTAGE (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_GFX_VOLTAGE_OFFSET))
|
||||
#define rPMGR_VOLMAN_CPU_VOLTAGE (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_CPU_VOLTAGE_OFFSET))
|
||||
#define rPMGR_VOLMAN_SOC_DELAY (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_SOC_DELAY_OFFSET))
|
||||
#define rPMGR_VOLMAN_GFX_SRAM_DELAY (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_GFX_SRAM_DELAY_OFFSET))
|
||||
#define rPMGR_VOLMAN_CPU_SRAM_DELAY (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_CPU_SRAM_DELAY_OFFSET))
|
||||
#define rPMGR_VOLMAN_GFX_DELAY (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_GFX_DELAY_OFFSET))
|
||||
#define rPMGR_VOLMAN_CPU_DELAY (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_CPU_DELAY_OFFSET))
|
||||
|
||||
#define PMGR_VOLMAN_DISABLE_CPU_VOL_CHANGE (1 << PMGR_VOLMAN_CTL_DISABLE_CPU_VOL_CHANGE_SHIFT)
|
||||
#define PMGR_VOLMAN_DISABLE_GFX_VOL_CHANGE (1 << PMGR_VOLMAN_CTL_DISABLE_GFX_VOL_CHANGE_SHIFT)
|
||||
#define PMGR_VOLMAN_DISABLE_CPU_SRAM_VOL_CHANGE (1 << PMGR_VOLMAN_CTL_DISABLE_CPU_SRAM_VOL_CHANGE_SHIFT)
|
||||
#define PMGR_VOLMAN_DISABLE_GFX_SRAM_VOL_CHANGE (1 << PMGR_VOLMAN_CTL_DISABLE_GFX_SRAM_VOL_CHANGE_SHIFT)
|
||||
#define PMGR_VOLMAN_DISABLE_SOC_VOL_CHANGE (1 << PMGR_VOLMAN_CTL_DISABLE_SOC_VOL_CHANGE_SHIFT)
|
||||
|
||||
#define PMGR_VOLMAN_VOLTAGE_PENDING (1 << 31)
|
||||
|
||||
#define rPMGR_EMA_FIXED_SOC0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_EMA_FIXED_SOC0_OFFSET)
|
||||
#define rPMGR_EMA_FIXED_SOC1 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_EMA_FIXED_SOC1_OFFSET)
|
||||
#define rPMGR_EMA_GPU_SRAM_GFX (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_EMA_FIXED_GPU_SRAM_GFX_OFFSET)
|
||||
#define rPMGR_EMA_FIXED_GFX (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_EMA_FIXED_FIXED_GFX_OFFSET)
|
||||
#define rPMGR_EMA_FIXED_SEP0 (*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_EMA_FIXED_FIXED_SEP0_OFFSET)
|
||||
|
||||
#define rPMGR_SCRATCH(_n) (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SCRATCH_0_OFFSET + ((_n)*4)))
|
||||
#define rPMGR_SCRATCH0 rPMGR_SCRATCH(0) /* Flags */
|
||||
#define rPMGR_SCRATCH1 rPMGR_SCRATCH(1)
|
||||
#define rPMGR_SCRATCH2 rPMGR_SCRATCH(2)
|
||||
#define rPMGR_SCRATCH3 rPMGR_SCRATCH(3)
|
||||
#define rPMGR_SCRATCH4 rPMGR_SCRATCH(4)
|
||||
#define rPMGR_SCRATCH5 rPMGR_SCRATCH(5)
|
||||
#define rPMGR_SCRATCH6 rPMGR_SCRATCH(6)
|
||||
#define rPMGR_SCRATCH7 rPMGR_SCRATCH(7)
|
||||
#define rPMGR_SCRATCH8 rPMGR_SCRATCH(8)
|
||||
// Use the symbolic functional name assignments below for these scratch registers
|
||||
//#define rPMGR_SCRATCH9 rPMGR_SCRATCH(9) /* Memory info */
|
||||
//#define rPMGR_SCRATCH10 rPMGR_SCRATCH(10) /* Boot Nonce 0 */
|
||||
//#define rPMGR_SCRATCH11 rPMGR_SCRATCH(11) /* Boot Nonce 1 */
|
||||
//#define rPMGR_SCRATCH12 rPMGR_SCRATCH(12) /* Boot Manifest Hash 0 */
|
||||
//#define rPMGR_SCRATCH13 rPMGR_SCRATCH(13) /* Boot Manifest Hash 1 */
|
||||
//#define rPMGR_SCRATCH14 rPMGR_SCRATCH(14) /* Boot Manifest Hash 2 */
|
||||
//#define rPMGR_SCRATCH15 rPMGR_SCRATCH(15) /* Boot Manifest Hash 3 */
|
||||
//#define rPMGR_SCRATCH16 rPMGR_SCRATCH(16) /* Boot Manifest Hash 4 */
|
||||
//#define rPMGR_SCRATCH17 rPMGR_SCRATCH(17) /* Boot Manifest Hash 5 */
|
||||
//#define rPMGR_SCRATCH18 rPMGR_SCRATCH(18) /* Boot Manifest Hash 6 */
|
||||
//#define rPMGR_SCRATCH19 rPMGR_SCRATCH(19) /* Boot Manifest Hash 7 */
|
||||
//#define rPMGR_SCRATCH20 rPMGR_SCRATCH(20) /* Boot Manifest Hash 8 */
|
||||
//#define rPMGR_SCRATCH21 rPMGR_SCRATCH(21) /* Boot Manifest Hash 9 */
|
||||
//#define rPMGR_SCRATCH22 rPMGR_SCRATCH(22) /* Boot Manifest Hash 10 */
|
||||
//#define rPMGR_SCRATCH23 rPMGR_SCRATCH(23) /* Boot Manifest Hash 11 */
|
||||
|
||||
#define rPMGR_SCRATCH_MEM_INFO rPMGR_SCRATCH(9)
|
||||
#define rPMGR_SCRATCH_BOOT_NONCE_0 rPMGR_SCRATCH(10)
|
||||
#define rPMGR_SCRATCH_BOOT_NONCE_1 rPMGR_SCRATCH(11)
|
||||
#define rPMGR_SCRATCH_BOOT_MANIFEST_HASH_FIRST rPMGR_SCRATCH(12)
|
||||
#define rPMGR_SCRATCH_BOOT_MANIFEST_HASH_LAST rPMGR_SCRATCH(23)
|
||||
#define PMGR_SCRATCH_BOOT_MANIFEST_REGISTERS (384 / 32)
|
||||
|
||||
#define rMINIPMGR_SCRATCH(_n) (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_SCRATCH_OFFSET + ((_n)*4)))
|
||||
#define rMINIPMGR_SCRATCH0 rMINIPMGR_SCRATCH(0)
|
||||
#define rMINIPMGR_SCRATCH1 rMINIPMGR_SCRATCH(1) /* Consistent debug root pointer */
|
||||
#define rMINIPMGR_SCRATCH2 rMINIPMGR_SCRATCH(2)
|
||||
#define rMINIPMGR_SCRATCH3 rMINIPMGR_SCRATCH(3)
|
||||
#define rMINIPMGR_SCRATCH4 rMINIPMGR_SCRATCH(4)
|
||||
#define rMINIPMGR_SCRATCH5 rMINIPMGR_SCRATCH(5)
|
||||
#define rMINIPMGR_SCRATCH6 rMINIPMGR_SCRATCH(6)
|
||||
#define rMINIPMGR_SCRATCH7 rMINIPMGR_SCRATCH(7)
|
||||
#define rMINIPMGR_SCRATCH8 rMINIPMGR_SCRATCH(8)
|
||||
#define rMINIPMGR_SCRATCH9 rMINIPMGR_SCRATCH(9)
|
||||
#define rMINIPMGR_SCRATCH10 rMINIPMGR_SCRATCH(10)
|
||||
#define rMINIPMGR_SCRATCH11 rMINIPMGR_SCRATCH(11)
|
||||
|
||||
#define rPMGR_THERMAL0_CTL0_SET (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_CTL0_SET_OFFSET))
|
||||
#define rPMGR_THERMAL0_CTL0_CLR (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_CTL0_CLR_OFFSET))
|
||||
#define rPMGR_THERMAL0_CTL1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_CTL1_OFFSET))
|
||||
#define rPMGR_THERMAL0_CTL2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_CTL2_OFFSET))
|
||||
#define rPMGR_THERMAL0_STATUS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_STATUS_OFFSET))
|
||||
#define rPMGR_THERMAL0_PARAM (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_PARAM_OFFSET))
|
||||
#define rPMGR_THERMAL0_RDBK0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_RDBK0_OFFSET))
|
||||
#define rPMGR_THERMAL0_RDBK1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_RDBK1_OFFSET))
|
||||
#define rPMGR_THERMAL0_SUM (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_SUM_OFFSET))
|
||||
#define rPMGR_THERMAL0_SUM_CNT (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_SUM_CNT_OFFSET))
|
||||
#define rPMGR_THERMAL0_PIECE0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_PIECE0_OFFSET))
|
||||
#define rPMGR_THERMAL0_PIECE1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_PIECE1_OFFSET))
|
||||
#define rPMGR_THERMAL0_PIECE2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_PIECE2_OFFSET))
|
||||
#define rPMGR_THERMAL0_ALARM0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_ALARM0_OFFSET))
|
||||
#define rPMGR_THERMAL0_ALARM1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_ALARM1_OFFSET))
|
||||
#define rPMGR_THERMAL0_ALARM2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_ALARM2_OFFSET))
|
||||
#define rPMGR_THERMAL0_ALARM3 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_ALARM3_OFFSET))
|
||||
#define rPMGR_THERMAL0_FAILSAFE_TRIP_TEMP_0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_FAILSAFE_TRIP_TEMP_0_OFFSET))
|
||||
#define rPMGR_THERMAL0_FAILSAFE_TRIP_TEMP_1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_FAILSAFE_TRIP_TEMP_1_OFFSET))
|
||||
#define rPMGR_THERMAL1_CTL0_SET (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_CTL0_SET_OFFSET))
|
||||
#define rPMGR_THERMAL1_CTL0_CLR (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_CTL0_CLR_OFFSET))
|
||||
#define rPMGR_THERMAL1_CTL1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_CTL1_OFFSET))
|
||||
#define rPMGR_THERMAL1_CTL2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_CTL2_OFFSET))
|
||||
#define rPMGR_THERMAL1_STATUS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_STATUS_OFFSET))
|
||||
#define rPMGR_THERMAL1_PARAM (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_PARAM_OFFSET))
|
||||
#define rPMGR_THERMAL1_RDBK0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_RDBK0_OFFSET))
|
||||
#define rPMGR_THERMAL1_RDBK1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_RDBK1_OFFSET))
|
||||
#define rPMGR_THERMAL1_SUM (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_SUM_OFFSET))
|
||||
#define rPMGR_THERMAL1_SUM_CNT (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_SUM_CNT_OFFSET))
|
||||
#define rPMGR_THERMAL1_PIECE0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_PIECE0_OFFSET))
|
||||
#define rPMGR_THERMAL1_PIECE1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_PIECE1_OFFSET))
|
||||
#define rPMGR_THERMAL1_PIECE2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_PIECE2_OFFSET))
|
||||
#define rPMGR_THERMAL1_ALARM0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_ALARM0_OFFSET))
|
||||
#define rPMGR_THERMAL1_ALARM1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_ALARM1_OFFSET))
|
||||
#define rPMGR_THERMAL1_ALARM2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_ALARM2_OFFSET))
|
||||
#define rPMGR_THERMAL1_ALARM3 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_ALARM3_OFFSET))
|
||||
#define rPMGR_THERMAL1_FAILSAFE_TRIP_TEMP_0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_FAILSAFE_TRIP_TEMP_0_OFFSET))
|
||||
#define rPMGR_THERMAL1_FAILSAFE_TRIP_TEMP_1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_FAILSAFE_TRIP_TEMP_1_OFFSET))
|
||||
#define rPMGR_THERMAL2_CTL0_SET (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_CTL0_SET_OFFSET))
|
||||
#define rPMGR_THERMAL2_CTL0_CLR (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_CTL0_CLR_OFFSET))
|
||||
#define rPMGR_THERMAL2_CTL1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_CTL1_OFFSET))
|
||||
#define rPMGR_THERMAL2_CTL2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_CTL2_OFFSET))
|
||||
#define rPMGR_THERMAL2_STATUS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_STATUS_OFFSET))
|
||||
#define rPMGR_THERMAL2_PARAM (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_PARAM_OFFSET))
|
||||
#define rPMGR_THERMAL2_RDBK0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_RDBK0_OFFSET))
|
||||
#define rPMGR_THERMAL2_RDBK1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_RDBK1_OFFSET))
|
||||
#define rPMGR_THERMAL2_SUM (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_SUM_OFFSET))
|
||||
#define rPMGR_THERMAL2_SUM_CNT (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_SUM_CNT_OFFSET))
|
||||
#define rPMGR_THERMAL2_PIECE0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_PIECE0_OFFSET))
|
||||
#define rPMGR_THERMAL2_PIECE1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_PIECE1_OFFSET))
|
||||
#define rPMGR_THERMAL2_PIECE2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_PIECE2_OFFSET))
|
||||
#define rPMGR_THERMAL2_ALARM0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_ALARM0_OFFSET))
|
||||
#define rPMGR_THERMAL2_ALARM1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_ALARM1_OFFSET))
|
||||
#define rPMGR_THERMAL2_ALARM2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_ALARM2_OFFSET))
|
||||
#define rPMGR_THERMAL2_ALARM3 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_ALARM3_OFFSET))
|
||||
#define rPMGR_THERMAL2_FAILSAFE_TRIP_TEMP_0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_FAILSAFE_TRIP_TEMP_0_OFFSET))
|
||||
#define rPMGR_THERMAL2_FAILSAFE_TRIP_TEMP_1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_FAILSAFE_TRIP_TEMP_1_OFFSET))
|
||||
|
||||
#define PMGR_THERMAL0_PIECE0(_c, _o, _s) (PMGR_THERMAL_0_PIECE0_START_CODE_INSRT(_c) | PMGR_THERMAL_0_PIECE0_OFFSET_INSRT(_o) | PMGR_THERMAL_0_PIECE0_SLOPE_INSRT(_s))
|
||||
#define PMGR_THERMAL0_PIECE1(_c, _o, _s) (PMGR_THERMAL_0_PIECE1_START_CODE_INSRT(_c) | PMGR_THERMAL_0_PIECE1_OFFSET_INSRT(_o) | PMGR_THERMAL_0_PIECE1_SLOPE_INSRT(_s))
|
||||
#define PMGR_THERMAL0_PIECE2(_c, _o, _s) (PMGR_THERMAL_0_PIECE2_START_CODE_INSRT(_c) | PMGR_THERMAL_0_PIECE2_OFFSET_INSRT(_o) | PMGR_THERMAL_0_PIECE2_SLOPE_INSRT(_s))
|
||||
#define PMGR_THERMAL1_PIECE0(_c, _o, _s) (PMGR_THERMAL_1_PIECE0_START_CODE_INSRT(_c) | PMGR_THERMAL_1_PIECE0_OFFSET_INSRT(_o) | PMGR_THERMAL_1_PIECE0_SLOPE_INSRT(_s))
|
||||
#define PMGR_THERMAL1_PIECE1(_c, _o, _s) (PMGR_THERMAL_1_PIECE1_START_CODE_INSRT(_c) | PMGR_THERMAL_1_PIECE1_OFFSET_INSRT(_o) | PMGR_THERMAL_1_PIECE1_SLOPE_INSRT(_s))
|
||||
#define PMGR_THERMAL1_PIECE2(_c, _o, _s) (PMGR_THERMAL_1_PIECE2_START_CODE_INSRT(_c) | PMGR_THERMAL_1_PIECE2_OFFSET_INSRT(_o) | PMGR_THERMAL_1_PIECE2_SLOPE_INSRT(_s))
|
||||
#define PMGR_THERMAL2_PIECE0(_c, _o, _s) (PMGR_THERMAL_2_PIECE0_START_CODE_INSRT(_c) | PMGR_THERMAL_2_PIECE0_OFFSET_INSRT(_o) | PMGR_THERMAL_2_PIECE0_SLOPE_INSRT(_s))
|
||||
#define PMGR_THERMAL2_PIECE1(_c, _o, _s) (PMGR_THERMAL_2_PIECE1_START_CODE_INSRT(_c) | PMGR_THERMAL_2_PIECE1_OFFSET_INSRT(_o) | PMGR_THERMAL_2_PIECE1_SLOPE_INSRT(_s))
|
||||
#define PMGR_THERMAL2_PIECE2(_c, _o, _s) (PMGR_THERMAL_2_PIECE2_START_CODE_INSRT(_c) | PMGR_THERMAL_2_PIECE2_OFFSET_INSRT(_o) | PMGR_THERMAL_2_PIECE2_SLOPE_INSRT(_s))
|
||||
|
||||
#define rPMGR_SOC_TVM_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_CTL_OFFSET))
|
||||
#define rPMGR_SOC_TVM_THRESH0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH0_OFFSET))
|
||||
#define rPMGR_SOC_TVM_THRESH1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH1_OFFSET))
|
||||
#define rPMGR_SOC_TVM_THRESH2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH2_OFFSET))
|
||||
#define rPMGR_SOC_TVM_TEMP0_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_TEMP0_CFG_OFFSET))
|
||||
#define rPMGR_SOC_TVM_TEMP1_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_TEMP1_CFG_OFFSET))
|
||||
#define rPMGR_SOC_TVM_DEBUG0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG0_OFFSET))
|
||||
#define rPMGR_SOC_TVM_DEBUG1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG1_OFFSET))
|
||||
#define rPMGR_SOC_TVM_DEBUG2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG2_OFFSET))
|
||||
|
||||
#define rPMGR_GFX_TVM_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_CTL_OFFSET))
|
||||
#define rPMGR_GFX_TVM_THRESH0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH0_OFFSET))
|
||||
#define rPMGR_GFX_TVM_THRESH1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH1_OFFSET))
|
||||
#define rPMGR_GFX_TVM_THRESH2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH2_OFFSET))
|
||||
#define rPMGR_GFX_TVM_TEMP0_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_TEMP0_CFG_OFFSET))
|
||||
#define rPMGR_GFX_TVM_TEMP1_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_TEMP1_CFG_OFFSET))
|
||||
#define rPMGR_GFX_TVM_DEBUG0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG0_OFFSET))
|
||||
#define rPMGR_GFX_TVM_DEBUG1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG1_OFFSET))
|
||||
#define rPMGR_GFX_TVM_DEBUG2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG2_OFFSET))
|
||||
|
||||
#define PMGR_TVM_THRESH(_t) ((_t) & 0x1FF)
|
||||
#define PMGR_TVM_TEMP_CFG_MAX_OFFSET(_mo) (((_mo) & 0x1FF) << 16)
|
||||
#define PMGR_TVM_TEMP_CFG_MIN_OFFSET(_mo) (((_mo) & 0x1FF) << 0)
|
||||
|
||||
#define rPMGR_MISC_CFG_ACG (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_MISC_CFG_ACG_OFFSET))
|
||||
|
||||
#define rPMGR_MISC_SPARE0 (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_MISC_SPARE_SPARE0_OFFSET))
|
||||
|
||||
#define rPMGR_DEBUG_PMGR_DEBUG20 (*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_DEBUG_20_OFFSET))
|
||||
#define rPMGR_PCIE_REFCLK_GOOD rPMGR_DEBUG_PMGR_DEBUG20
|
||||
#define PMGR_PCIE_REFCLK_GOOD_UMASK (PMGR_DEBUG_20_CLKGEN_PMGR_PCIE_REF_CLK_GOOD_UMASK)
|
||||
|
||||
#define rPMGR_CHIP_WDOG_TMR (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_CHIP_WATCHDOG_TIMER_OFFSET))
|
||||
#define rPMGR_CHIP_WDOG_RST_CNT (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_CHIP_WATCHDOG_RESET_COUNT_OFFSET))
|
||||
#define rPMGR_CHIP_WDOG_INTR_CNT (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_CHIP_WATCHDOG_INTERRUPT_COUNT_OFFSET))
|
||||
#define rPMGR_CHIP_WDOG_CTL (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_CHIP_WATCHDOG_CONTROL_OFFSET))
|
||||
#define rPMGR_SYS_WDOG_TMR (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_SYS_WATCHDOG_TIMER_OFFSET))
|
||||
#define rPMGR_SYS_WDOG_RST_CNT (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_SYS_WATCHDOG_RESET_COUNT_OFFSET))
|
||||
#define rPMGR_SYS_WDOG_CTL (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_SYS_WATCHDOG_CONTROL_OFFSET))
|
||||
|
||||
#define rMINIPMGR_LPPLL_CTL (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_LPPLL_CTL_OFFSET))
|
||||
#define MINIPMGR_LPPLL_CTL_ENABLE (1 << MINIPMGR_LPPLL_CTL_ENABLE_SHIFT)
|
||||
#define MINIPMGR_LPPLL_CTL_PENDING (1 << MINIPMGR_LPPLL_CTL_PENDING_SHIFT)
|
||||
#define rMINIPMGR_LPPLL_CFG (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_LPPLL_CFG_OFFSET))
|
||||
|
||||
#define rMINIPMGR_CLK_CFG(_x) (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_CLKCFG_##_x##_CLK_CFG_OFFSET))
|
||||
#define rMINIPMGR_CLK_DIVIDER_ACG_CFG (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_CLKCFG_CLK_DIVIDER_ACG_CFG_OFFSET))
|
||||
|
||||
#define rMINIPMGR_PS(_x) (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_PS_##_x##_PS_OFFSET))
|
||||
|
||||
#define rMINIPMGR_MISC_CFG_ACG (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_MISC_CFG_ACG_OFFSET))
|
||||
#define rMINIPMGR_MISC_CFG_CPU (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_MISC_CFG_CPU_CFG_OFFSET))
|
||||
|
||||
#if SUB_PLATFORM_T8010
|
||||
enum {
|
||||
PMGR_CLK_OSC = 0, // 0x00
|
||||
PMGR_CLK_PLL0, // 0x01
|
||||
PMGR_CLK_PLL1, // 0x02
|
||||
PMGR_CLK_PLL2, // 0x03
|
||||
PMGR_CLK_PLL3, // 0x04
|
||||
PMGR_CLK_PLL4, // 0x05
|
||||
PMGR_CLK_PLL5, // 0x06
|
||||
PMGR_CLK_PLL_PCIE, // 0x07
|
||||
PMGR_CLK_CPU, // 0x08
|
||||
PMGR_CLK_GFX_FENDER, // 0x09
|
||||
PMGR_CLK_FIRST = PMGR_CLK_GFX_FENDER,
|
||||
PMGR_CLK_MCU_REF, // 0x0A
|
||||
PMGR_CLK_PMP, // 0x0B
|
||||
PMGR_CLK_TEMP_MIPI_DSI, // 0x0C
|
||||
PMGR_CLK_NCO_REF0, // 0x0D
|
||||
PMGR_CLK_NCO_REF1, // 0x0E
|
||||
PMGR_CLK_NCO_ALG0, // 0x0F
|
||||
PMGR_CLK_NCO_ALG1, // 0x10
|
||||
PMGR_CLK_HSICPHY_REF_12M, // 0x11
|
||||
PMGR_CLK_USB480_0, // 0x12
|
||||
PMGR_CLK_USB_OHCI_48M, // 0x13
|
||||
PMGR_CLK_USB, // 0x14
|
||||
PMGR_CLK_USB_FREE_60M, // 0x15
|
||||
PMGR_CLK_SIO_C, // 0x16
|
||||
PMGR_CLK_SIO_P, // 0x17
|
||||
PMGR_CLK_SIO_AES, // 0x18
|
||||
PMGR_CLK_HFD, // 0x19
|
||||
PMGR_CLK_ISP_C, // 0x1A
|
||||
PMGR_CLK_ISP_AHFD, // 0x1B
|
||||
PMGR_CLK_ISP_PEARL, // 0x1C
|
||||
PMGR_CLK_ISP, // 0x1D
|
||||
PMGR_CLK_ISP_SENSOR0_REF, // 0x1E
|
||||
PMGR_CLK_ISP_SENSOR1_REF, // 0x1F
|
||||
PMGR_CLK_ISP_SENSOR2_REF, // 0x20
|
||||
PMGR_CLK_VDEC, // 0x21
|
||||
PMGR_CLK_VENC, // 0x22
|
||||
PMGR_CLK_VID0, // 0x23
|
||||
PMGR_CLK_DISP0, // 0x24
|
||||
PMGR_CLK_AJPEG_IP, // 0x25
|
||||
PMGR_CLK_AJPEG_WRAP, // 0x26
|
||||
PMGR_CLK_MSR, // 0x27
|
||||
PMGR_CLK_FAST_AF, // 0x28
|
||||
PMGR_CLK_SLOW_AF, // 0x29
|
||||
PMGR_CLK_SBR, // 0x2A
|
||||
PMGR_CLK_MCA0_M, // 0x2B
|
||||
PMGR_CLK_MCA1_M, // 0x2C
|
||||
PMGR_CLK_MCA2_M, // 0x2D
|
||||
PMGR_CLK_MCA3_M, // 0x2E
|
||||
PMGR_CLK_MCA4_M, // 0x2F
|
||||
PMGR_CLK_SEP, // 0x30
|
||||
PMGR_CLK_GPIO, // 0x31
|
||||
PMGR_CLK_SPI0_N, // 0x32
|
||||
PMGR_CLK_SPI1_N, // 0x33
|
||||
PMGR_CLK_SPI2_N, // 0x34
|
||||
PMGR_CLK_SPI3_N, // 0x35
|
||||
PMGR_CLK_TMPS, // 0x36
|
||||
PMGR_CLK_CPU_UVD, // 0x37
|
||||
PMGR_CLK_GFX_UVD, // 0x38
|
||||
PMGR_CLK_SOC_UVD, // 0x39
|
||||
PMGR_CLK_LPDP_RX_REF, // 0x3A
|
||||
PMGR_CLK_LAST = PMGR_CLK_LPDP_RX_REF,
|
||||
PMGR_CLK_S0, // 0x3B
|
||||
PMGR_CLK_SPARE_FIRST = PMGR_CLK_S0,
|
||||
PMGR_CLK_S1, // 0x3C
|
||||
PMGR_CLK_S2, // 0x3D
|
||||
PMGR_CLK_S3, // 0x3E
|
||||
PMGR_CLK_ISP_REF0, // 0x3F
|
||||
PMGR_CLK_ISP_REF1, // 0x40
|
||||
PMGR_CLK_ISP_REF2, // 0x41
|
||||
PMGR_CLK_SPARE_LAST = PMGR_CLK_ISP_REF2,
|
||||
PMGR_CLK_LPO, // 0x42
|
||||
PMGR_CLK_AOP, // 0x43
|
||||
PMGR_CLK_MINI_FIRST = PMGR_CLK_AOP,
|
||||
PMGR_CLK_UART0, // 0x44
|
||||
PMGR_CLK_UART1, // 0x45
|
||||
PMGR_CLK_UART2, // 0x46
|
||||
PMGR_CLK_AOP_MCA0_M, // 0x47
|
||||
PMGR_CLK_I2CM, // 0x48
|
||||
PMGR_CLK_PDM_REF, // 0x49
|
||||
PMGR_CLK_SENSE_2X, // 0x4A
|
||||
PMGR_CLK_DETECT, // 0x4B
|
||||
PMGR_CLK_PROXY_FABRIC, // 0x4C
|
||||
PMGR_CLK_PROXY_MCU_REF, // 0x4D
|
||||
PMGR_CLK_MINI_LAST = PMGR_CLK_PROXY_MCU_REF,
|
||||
PMGR_CLK_COUNT, // 0x4E
|
||||
PMGR_CLK_NOT_SUPPORTED
|
||||
};
|
||||
|
||||
#else
|
||||
#error "Unknown platform"
|
||||
#endif
|
||||
|
||||
////////////////////////////////////////////////////////////
|
||||
//
|
||||
// CCC specific
|
||||
//
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
#define rACC_PRE_TD_TMR (*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_PRE_TD_TMR_OFFSET))
|
||||
#define rACC_PRE_FLUSH_TMR (*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_PRE_FLUSH_TMR_OFFSET))
|
||||
|
||||
#define rACC_APSC_SCR (*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_PWRCTL_APSC_SCR_OFFSET))
|
||||
#define ACC_APSC_PENDING (1 << ACC_PWRCTL_APSC_SCR_MANUAL_PENDING_SHIFT)
|
||||
#define ACC_APSC_MANUAL_CHANGE(_d) ((1 << ACC_PWRCTL_APSC_SCR_MANUAL_CHANGE_SHIFT) | ACC_PWRCTL_APSC_SCR_MANUAL_ST_INSRT((uint64_t)_d))
|
||||
|
||||
#define rACC_DVFM_CFG (*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_DVFM_CFG_OFFSET))
|
||||
|
||||
#define rACC_DVFM_SCR (*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_PWRCTL_DVFM_SCR_OFFSET)) // 64-bit
|
||||
#define ACC_DVFM_SCR_TEMPSENSORMODE (ACC_PWRCTL_DVFM_MODE_INSRT((uint64_t)1))
|
||||
|
||||
#define rACC_DVFM_CFG_SEL (*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_DVFM_CFG_SEL_OFFSET))
|
||||
|
||||
#define rACC_DVFM_CFG1 (*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_DVFM_CFG1_OFFSET))
|
||||
|
||||
#define kDVFM_STATE_BYPASS (0)
|
||||
#define kDVFM_STATE_SECUREROM (kDVFM_STATE_BYPASS + 1)
|
||||
#define kDVFM_STATE_IBOOT (kDVFM_STATE_BYPASS + 2)
|
||||
#define kDVFM_STATE_V0 (kDVFM_STATE_IBOOT + 0)
|
||||
|
||||
#define kDVFM_STATE_VMAX (kDVFM_STATE_IBOOT) // !!! FIXME !!! (kDVFM_STATE_V5)
|
||||
|
||||
#define kDVFM_STATE_VNOM (kDVFM_STATE_V0)
|
||||
#define kDVFM_STATE_VBOOST (kDVFM_STATE_VNOM + 1)
|
||||
|
||||
#define kDVFM_STATE_IBOOT_CNT (kDVFM_STATE_VMAX + 1)
|
||||
|
||||
#define kVOLTAGE_STATES1_COUNT (kDVFM_STATE_VMAX - kDVFM_STATE_V0 + 1)
|
||||
#define kVOLTAGE_STATES1_SIZE (kVOLTAGE_STATES1_COUNT*2) // Minimum size of voltage-state1 property in devicetree
|
||||
|
||||
#define kDVFM_STATE_MAX_CNT (16)
|
||||
|
||||
// TODO: Remove these when added to EmbeddedHeaders
|
||||
#define ACC_PWRCTL_DVFM_ST0_PRE_DIV_P_INSRT(f) ((((uint64_t)f) & 0x1f) << 13)
|
||||
#define ACC_PWRCTL_DVFM_ST0_FBK_DIV_M_INSRT(f) ((((uint64_t)f) & 0x1ff) << 4)
|
||||
#define ACC_PWRCTL_DVFM_ST0_PST_DIV_S_INSRT(f) ((((uint64_t)f) & 0xf) << 0)
|
||||
|
||||
#define ACC_DVFM_ST_STRIDE (ACC_DVFM_ST1_OFFSET - ACC_DVFM_ST0_OFFSET)
|
||||
|
||||
#define rACC_DVFM_ST(_n) (*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_DVFM_ST0_OFFSET + ((_n) * ACC_DVFM_ST_STRIDE)))
|
||||
#define ACC_DVFM_ST_SAFE_VOL_INSRT(_sv) (ACC_DVFM_ST0_SAFE_VOL_INSRT((uint64_t)_sv))
|
||||
#define ACC_DVFM_ST_SAFE_VOL_XTRCT(_sv) (ACC_DVFM_ST0_SAFE_VOL_XTRCT((uint64_t)_sv))
|
||||
#define ACC_DVFM_ST_VOL_ADJ3(_va) (ACC_DVFM_ST0_VOL_ADJ3_INSRT((uint64_t)_va))
|
||||
#define ACC_DVFM_ST_VOL_ADJ2(_va) (ACC_DVFM_ST0_VOL_ADJ2_INSRT((uint64_t)_va))
|
||||
#define ACC_DVFM_ST_VOL_ADJ1(_va) (ACC_DVFM_ST0_VOL_ADJ1_INSRT((uint64_t)_va))
|
||||
#define ACC_DVFM_ST_VOL_ADJ0(_va) (ACC_DVFM_ST0_VOL_ADJ0_INSRT((uint64_t)_va))
|
||||
#define ACC_DVFM_ST_CORE_TYP(_ct) (ACC_DVFM_ST0_CORE_TYP_INSRT((uint64_t)_ct))
|
||||
#define ACC_DVFM_ST_VOL_BYP(_vb) (ACC_DVFM_ST0_VOL_BYP_INSRT((uint64_t)_vb))
|
||||
#define ACC_DVFM_ST_CLK_SRC(_s) (ACC_DVFM_ST0_CLK_SRC_INSRT((uint64_t)_s))
|
||||
#define ACC_DVFM_ST_MIG_DIV_S(_s) (ACC_DVFM_ST0_MIG_DIV_S_INSRT((uint64_t)_s))
|
||||
#define ACC_DVFM_ST_FCW_FRAC_INSRT(_f) (ACC_DVFM_ST0_FCW_FRAC_INSRT((uint64_t)_f))
|
||||
#define ACC_DVFM_ST_FCW_INT_INSRT(_i) (ACC_DVFM_ST0_FCW_INT_INSRT((uint64_t)_i))
|
||||
#define ACC_DVFM_ST_PST_DIV_S_INSRT(_s) (ACC_DVFM_ST0_PST_DIV_S_INSRT((uint64_t)_s))
|
||||
#define ACC_DVFM_ST_FCW_FRAC_XTRCT(_f) (ACC_DVFM_ST0_FCW_FRAC_XTRCT((uint64_t)_f))
|
||||
#define ACC_DVFM_ST_FCW_INT_XTRCT(_i) (ACC_DVFM_ST0_FCW_INT_XTRCT((uint64_t)_i))
|
||||
#define ACC_DVFM_ST_PST_DIV_S_XTRCT(_s) (ACC_DVFM_ST0_PST_DIV_S_XTRCT((uint64_t)_s))
|
||||
|
||||
#define rACC_DVFM_ST_EXT(_n) (*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_DVFM_ST0_EXT_OFFSET + ((_n) * ACC_DVFM_ST_STRIDE)))
|
||||
#define ACC_DVFM_ST_BIU_DIV_HI_VOL(_d) (ACC_DVFM_ST0_EXT_BIU_DIV4_HI_VOL_INSRT((uint64_t)(_d)))
|
||||
#define ACC_DVFM_ST_BIU_DIV_LO_VOL(_d) (ACC_DVFM_ST0_EXT_BIU_DIV4_LO_VOL_INSRT((uint64_t)(_d)))
|
||||
#define ACC_DVFM_ST_DVMR_MAX_WGT(_w) (ACC_DVFM_ST0_EXT_DVMR_MAX_WGT_INSRT((uint64_t)(_w)))
|
||||
#define ACC_DVFM_ST_SRAM_VOL(_v) (ACC_DVFM_ST0_EXT_SRAM_VOL_INSRT((uint64_t)(_v)))
|
||||
#define ACC_DVFM_ST_DVFM_MAX_ADJ(_a) (ACC_DVFM_ST0_EXT_MAX_ADJ_INSRT((uint64_t)(_a)))
|
||||
#define ACC_DVFM_ST_DVMR_ADJ2(_a) (ACC_DVFM_ST0_EXT_DVMR_ADJ2_INSRT((uint64_t)(_a)))
|
||||
#define ACC_DVFM_ST_DVMR_ADJ1(_a) (ACC_DVFM_ST0_EXT_DVMR_ADJ1_INSRT((uint64_t)(_a)))
|
||||
#define ACC_DVFM_ST_DVMR_ADJ0(_a) (ACC_DVFM_ST0_EXT_DVMR_ADJ0_INSRT((uint64_t)(_a)))
|
||||
|
||||
#define rACC_DVFM_ST_EXT2(_n) (*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_DVFM_ST0_EXT2_OFFSET + ((_n) * ACC_DVFM_ST_STRIDE)))
|
||||
#define ACC_DVFM_ST_ADCLK_EN(_a) (ACC_DVFM_ST0_EXT2_ADCLK_EN_INSRT((uint64_t)(_a)))
|
||||
|
||||
#define rACC_PLL_SCR1 (*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_PLL_SCR1_OFFSET))
|
||||
#define rACC_PLL_CFG2 (*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_PLL_CFG2_OFFSET))
|
||||
#define rACC_DVMR_SCR (*(volatile uint64_t *)(ACC_BASE_ADDR + DVMR_SCR_OFFSET))
|
||||
|
||||
#define rMINIPMGR_SIO_AES_DISABLE (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_SIO_AES_DISABLE_OFFSET))
|
||||
#define rMINIPMGR_SECURITY_GPIO_STRAPS (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_GPIO_STRAPS_OFFSET))
|
||||
#define rMINIPMGR_SET_ONLY (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_SET_ONLY_OFFSET))
|
||||
#define MINIPMGR_SET_ONLY_MIX_N_MATCH (1 << 31)
|
||||
#define rMINIPMGR_SEAL_DATA_A_FIRST (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_SEAL_DATA_A0_OFFSET))
|
||||
#define rMINIPMGR_SEAL_DATA_A_LAST (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_SEAL_DATA_A7_OFFSET))
|
||||
#define rMINIPMGR_SEAL_CTL_A (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_SEAL_CTL_A_OFFSET))
|
||||
#define rMINIPMGR_SEAL_DATA_B_FIRST (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_SEAL_DATA_B0_OFFSET))
|
||||
#define rMINIPMGR_SEAL_DATA_B_LAST (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_SEAL_DATA_B7_OFFSET))
|
||||
#define rMINIPMGR_SEAL_CTL_B (*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_SEAL_CTL_B_OFFSET))
|
||||
|
||||
#define rACC_THRM0_CTL0_SET (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM0_CTL0_SET_OFFSET))
|
||||
#define rACC_THRM0_CTL1 (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM0_CTL1_OFFSET))
|
||||
#define rACC_THRM0_PARAM (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM0_PARAM_OFFSET))
|
||||
#define rACC_THRM0_PIECE0 (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM0_PIECE0_OFFSET))
|
||||
#define rACC_THRM0_PIECE1 (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM0_PIECE1_OFFSET))
|
||||
#define rACC_THRM0_PIECE2 (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM0_PIECE2_OFFSET))
|
||||
|
||||
#define rACC_THRM1_CTL0_SET (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM1_CTL0_SET_OFFSET))
|
||||
#define rACC_THRM1_CTL1 (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM1_CTL1_OFFSET))
|
||||
#define rACC_THRM1_PARAM (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM1_PARAM_OFFSET))
|
||||
#define rACC_THRM1_PIECE0 (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM1_PIECE0_OFFSET))
|
||||
#define rACC_THRM1_PIECE1 (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM1_PIECE1_OFFSET))
|
||||
#define rACC_THRM1_PIECE2 (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM1_PIECE2_OFFSET))
|
||||
|
||||
#define rACC_THRM2_CTL0_SET (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM2_CTL0_SET_OFFSET))
|
||||
#define rACC_THRM2_CTL1 (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM2_CTL1_OFFSET))
|
||||
#define rACC_THRM2_PARAM (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM2_PARAM_OFFSET))
|
||||
#define rACC_THRM2_PIECE0 (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM2_PIECE0_OFFSET))
|
||||
#define rACC_THRM2_PIECE1 (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM2_PIECE1_OFFSET))
|
||||
#define rACC_THRM2_PIECE2 (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM2_PIECE2_OFFSET))
|
||||
|
||||
#define rACC_DVFM_FSHOT_IDX (*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_DVFM_FSHOT_IDX_OFFSET))
|
||||
|
||||
#define ACC_THRM0_PIECE0(_c, _o, _s) (ACC_THERMAL_THRM0_PIECE0_START_CODE_INSRT(_c) | ACC_THERMAL_THRM0_PIECE0_OFFSET_INSRT(_o) | ACC_THERMAL_THRM0_PIECE0_SLOPE_INSRT(_s))
|
||||
#define ACC_THRM0_PIECE1(_c, _o, _s) (ACC_THERMAL_THRM0_PIECE1_START_CODE_INSRT(_c) | ACC_THERMAL_THRM0_PIECE1_OFFSET_INSRT(_o) | ACC_THERMAL_THRM0_PIECE1_SLOPE_INSRT(_s))
|
||||
#define ACC_THRM0_PIECE2(_c, _o, _s) (ACC_THERMAL_THRM0_PIECE2_START_CODE_INSRT(_c) | ACC_THERMAL_THRM0_PIECE2_OFFSET_INSRT(_o) | ACC_THERMAL_THRM0_PIECE2_SLOPE_INSRT(_s))
|
||||
#define ACC_THRM1_PIECE0(_c, _o, _s) (ACC_THERMAL_THRM1_PIECE0_START_CODE_INSRT(_c) | ACC_THERMAL_THRM1_PIECE0_OFFSET_INSRT(_o) | ACC_THERMAL_THRM1_PIECE0_SLOPE_INSRT(_s))
|
||||
#define ACC_THRM1_PIECE1(_c, _o, _s) (ACC_THERMAL_THRM1_PIECE1_START_CODE_INSRT(_c) | ACC_THERMAL_THRM1_PIECE1_OFFSET_INSRT(_o) | ACC_THERMAL_THRM1_PIECE1_SLOPE_INSRT(_s))
|
||||
#define ACC_THRM1_PIECE2(_c, _o, _s) (ACC_THERMAL_THRM1_PIECE2_START_CODE_INSRT(_c) | ACC_THERMAL_THRM1_PIECE2_OFFSET_INSRT(_o) | ACC_THERMAL_THRM1_PIECE2_SLOPE_INSRT(_s))
|
||||
#define ACC_THRM2_PIECE0(_c, _o, _s) (ACC_THERMAL_THRM2_PIECE0_START_CODE_INSRT(_c) | ACC_THERMAL_THRM2_PIECE0_OFFSET_INSRT(_o) | ACC_THERMAL_THRM2_PIECE0_SLOPE_INSRT(_s))
|
||||
#define ACC_THRM2_PIECE1(_c, _o, _s) (ACC_THERMAL_THRM2_PIECE1_START_CODE_INSRT(_c) | ACC_THERMAL_THRM2_PIECE1_OFFSET_INSRT(_o) | ACC_THERMAL_THRM2_PIECE1_SLOPE_INSRT(_s))
|
||||
#define ACC_THRM2_PIECE2(_c, _o, _s) (ACC_THERMAL_THRM2_PIECE2_START_CODE_INSRT(_c) | ACC_THERMAL_THRM2_PIECE2_OFFSET_INSRT(_o) | ACC_THERMAL_THRM2_PIECE2_SLOPE_INSRT(_s))
|
||||
|
||||
////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Externs
|
||||
//
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
extern void pmgr_update_device_tree(DTNode *pmgr_node);
|
||||
extern void pmgr_gfx_update_device_tree(DTNode *gfx_node);
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_PMGR_H */
|
||||
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_RECONFIG_H
|
||||
#define __PLATFORM_RECONFIG_H
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <platform/memmap.h>
|
||||
|
||||
#define rAOP_GLOBAL(_p) (*(volatile uint32_t *)(AOP_BASE_ADDR + (_p)))
|
||||
#define rRECONFIG_RAM_BASE(base, count) *(volatile uint32_t *)((base) + ((count) * 4))
|
||||
#define rRECONFIG_RAM_BASE_BYTE(base, count, count_bytes) *(volatile uint32_t *)((base) + ((count) * 4) + (count_bytes))
|
||||
|
||||
#define ALIGNMENT_MASK_1KB ~(0x3FF)
|
||||
#define RECONFIG_NUMBER_OF_REGS(regs) ((((regs) - 1) & 0xF) << 2)
|
||||
#define AOP_CFG_TABLE (AOP_RECONFIG_REGION_BASE_ADDR)
|
||||
#define WRITE_OFFSETS(addr, values) (((addr) >> 2) & 0xFF) << (((values) % 4) * 8)
|
||||
#define MAX_WRITE_REGS 16
|
||||
|
||||
// SRAM sequences
|
||||
#define AOP_DDR_S2R_AOP_PRE_BASE_ADDR (AOP_RECONFIG_REGION_BASE_ADDR + 0x100)
|
||||
#define AOP_DDR_S2R_AOP_PRE_MAX_SIZE 0x200
|
||||
|
||||
#define AOP_DDR_S2R_AOP_POST_BASE_ADDR (AOP_DDR_S2R_AOP_PRE_BASE_ADDR + AOP_DDR_S2R_AOP_PRE_MAX_SIZE)
|
||||
#define AOP_DDR_S2R_AOP_POST_MAX_SIZE 0x100
|
||||
|
||||
#define S2R_AOP_AOP_DDR_PRE_BASE_ADDR (AOP_DDR_S2R_AOP_POST_BASE_ADDR + AOP_DDR_S2R_AOP_POST_MAX_SIZE)
|
||||
#define S2R_AOP_AOP_DDR_PRE_MAX_SIZE 0x100
|
||||
|
||||
#define S2R_AOP_AOP_DDR_POST_BASE_ADDR (S2R_AOP_AOP_DDR_PRE_BASE_ADDR + S2R_AOP_AOP_DDR_PRE_MAX_SIZE)
|
||||
#define S2R_AOP_AOP_DDR_POST_MAX_SIZE 0x3000
|
||||
|
||||
#define AOP_RECONFIG_REGION_USED (AOP_RECONFIG_REGION_BASE_ADDR - S2R_AOP_AOP_DDR_PRE_BASE_ADDR + S2R_AOP_AOP_DDR_POST_MAX_SIZE)
|
||||
|
||||
#if AOP_RECONFIG_REGION_USED > AOP_RECONFIG_REGION_SIZE
|
||||
#error "Reconfig engine programs overflow their SRAM allocation
|
||||
#endif
|
||||
|
||||
// DRAM sequences
|
||||
#define AWAKE_AOP_DDR_PRE_BASE_ADDR (DRAM_CONFIG_SEQ_BASE)
|
||||
#define AWAKE_AOP_DDR_PRE_MAX_SIZE 0x200
|
||||
|
||||
#define AWAKE_AOP_DDR_POST_BASE_ADDR (AWAKE_AOP_DDR_PRE_BASE_ADDR + AWAKE_AOP_DDR_PRE_MAX_SIZE)
|
||||
#define AWAKE_AOP_DDR_POST_MAX_SIZE 0x600
|
||||
|
||||
#define AOP_DDR_AWAKE_PRE_BASE_ADDR (AWAKE_AOP_DDR_POST_BASE_ADDR + AWAKE_AOP_DDR_POST_MAX_SIZE)
|
||||
#define AOP_DDR_AWAKE_PRE_MAX_SIZE 0x800
|
||||
|
||||
#define AOP_DDR_AWAKE_POST_BASE_ADDR (AOP_DDR_AWAKE_PRE_BASE_ADDR + AOP_DDR_AWAKE_PRE_MAX_SIZE)
|
||||
#define AOP_DDR_AWAKE_POST_MAX_SIZE 0x2400
|
||||
|
||||
#define DRAM_CONFIG_SEQ_USED (AOP_DDR_AWAKE_POST_BASE_ADDR + AOP_DDR_AWAKE_POST_MAX_SIZE - DRAM_CONFIG_SEQ_BASE)
|
||||
|
||||
#if DRAM_CONFIG_SEQ_USED > DRAM_CONFIG_SEQ_SIZE
|
||||
#error "Reconfig engine programs overflow their DRAM allocation
|
||||
#endif
|
||||
|
||||
#endif /* __PLATFORM_RECONFIG_H */
|
||||
@@ -0,0 +1,221 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_T8010_A0_TUNABLE_APCIE_COMMON_H
|
||||
#define SPDS_T8010_A0_TUNABLE_APCIE_COMMON_H
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_FABRIC_TLIMITS_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x7f7f7f7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_FABRIC_TLIMITS_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_LLT_RATE_LIMITER_CTRL_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_LLT_RATE_LIMITER_CTRL_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_COMMON_PRIORITY_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x700)
|
||||
#define PCIE_APCIE_COMMON_BLK_COMMON_PRIORITY_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NANDSYSCLK_TIMING_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xffffff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NANDSYSCLK_TIMING_DEFAULT_TUNABLE_VALUE_T8010_A0 (0xc0800)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NAND_LTR_THRESH_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x1fff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NAND_LTR_THRESH_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x92c)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_REFCLKBUF_TIMING_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_REFCLKBUF_TIMING_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x9)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_NVME_TUNABLE_UMASK_T8010_A0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_NVME_TUNABLE_VALUE_T8010_A0 (0x10)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x31100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x1000000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_FPGA_TUNABLE_UMASK_T8010_A0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_0_FPGA_TUNABLE_VALUE_T8010_A0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_0_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_0_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NVME_CTRL_0_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x11)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NVME_CTRL_0_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NVME_CTRL_0_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0x1)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_NVME_CTRL_0_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_PRIORITY_0_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x7)
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_PRIORITY_0_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_0_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_0_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x333003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_0_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x111000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_0_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_0_DEFAULT_TUNABLE_VALUE_T8010_A0 (0xf)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_0_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_0_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_NVME_TUNABLE_UMASK_T8010_A0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_NVME_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x31100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x1000000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_FPGA_TUNABLE_UMASK_T8010_A0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_1_FPGA_TUNABLE_VALUE_T8010_A0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_1_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_1_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_1_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_1_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_1_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x333003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_1_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x111000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_1_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_1_DEFAULT_TUNABLE_VALUE_T8010_A0 (0xf)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_1_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_1_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_NVME_TUNABLE_UMASK_T8010_A0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_NVME_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x31100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x1000000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_FPGA_TUNABLE_UMASK_T8010_A0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_2_FPGA_TUNABLE_VALUE_T8010_A0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_2_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_2_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_2_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_2_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_2_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x333003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_2_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x111000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_2_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_2_DEFAULT_TUNABLE_VALUE_T8010_A0 (0xf)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_2_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_2_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_NVME_TUNABLE_UMASK_T8010_A0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_NVME_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x31100010)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x1000000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0x10)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_FPGA_TUNABLE_UMASK_T8010_A0 (0x100000)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_CTRL_3_FPGA_TUNABLE_VALUE_T8010_A0 (0x100000)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_3_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x707)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_PRIORITY_3_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_3_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x73f3f)
|
||||
#define PCIE_APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_3_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x43f00)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_3_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x333003f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_3_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x111000f)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_3_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xff)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_3_DEFAULT_TUNABLE_VALUE_T8010_A0 (0xf)
|
||||
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_3_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x7f)
|
||||
#define PCIE_APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_3_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x3e)
|
||||
|
||||
#define PCIE_APCIE_COMMON_DEFAULT_TUNABLES_T8010_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_COMMON_BLK_FABRIC_TLIMITS */ 0x8, sizeof(uint32_t), 0x7f7f7f7f, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_LLT_RATE_LIMITER_CTRL */ 0xc, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_COMMON_PRIORITY */ 0x10, sizeof(uint32_t), 0x700, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NANDSYSCLK_TIMING */ 0x18, sizeof(uint32_t), 0xffffff, 0xc0800 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NAND_LTR_THRESH */ 0x1c, sizeof(uint32_t), 0x1fff, 0x92c }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_REFCLKBUF_TIMING */ 0x2c, sizeof(uint32_t), 0xff, 0x9 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_0 */ 0x100, sizeof(uint32_t), 0x31100010, 0x1000000 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_0 */ 0x108, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_0 */ 0x10c, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NVME_CTRL_0 */ 0x110, sizeof(uint32_t), 0x11, 0x1 }, \
|
||||
{ /* APCIE_COMMON_BLK_NVME_PRIORITY_0 */ 0x114, sizeof(uint32_t), 0x7, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_NVME_RATE_LIMITER_CTRL_0 */ 0x118, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_0 */ 0x120, sizeof(uint32_t), 0x333003f, 0x111000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_0 */ 0x130, sizeof(uint32_t), 0xff, 0xf }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_0 */ 0x138, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_1 */ 0x180, sizeof(uint32_t), 0x31100010, 0x1000000 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_1 */ 0x188, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_1 */ 0x18c, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_1 */ 0x1a0, sizeof(uint32_t), 0x333003f, 0x111000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_1 */ 0x1b0, sizeof(uint32_t), 0xff, 0xf }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_1 */ 0x1b8, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_2 */ 0x200, sizeof(uint32_t), 0x31100010, 0x1000000 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_2 */ 0x208, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_2 */ 0x20c, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_2 */ 0x220, sizeof(uint32_t), 0x333003f, 0x111000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_2 */ 0x230, sizeof(uint32_t), 0xff, 0xf }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_2 */ 0x238, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_3 */ 0x280, sizeof(uint32_t), 0x31100010, 0x1000000 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_PRIORITY_3 */ 0x288, sizeof(uint32_t), 0x707, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_PORT_RATE_LIMITER_CTRL_3 */ 0x28c, sizeof(uint32_t), 0x73f3f, 0x43f00 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_SQUELCH_CTRL_3 */ 0x2a0, sizeof(uint32_t), 0x333003f, 0x111000f }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_ACG_IDLE_CTRL_3 */ 0x2b0, sizeof(uint32_t), 0xff, 0xf }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PIPE_OVERRIDE_VAL_3 */ 0x2b8, sizeof(uint32_t), 0x7f, 0x3e }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_COMMON_FPGA_TUNABLES_T8010_A0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_0 */ 0x100, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_1 */ 0x180, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_2 */ 0x200, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_3 */ 0x280, sizeof(uint32_t), 0x100000, 0x100000 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_COMMON_NVME_TUNABLES_T8010_A0 \
|
||||
/* Key = nvme_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_0 */ 0x100, sizeof(uint32_t), 0x10, 0x10 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_1 */ 0x180, sizeof(uint32_t), 0x10, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_2 */ 0x200, sizeof(uint32_t), 0x10, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_3 */ 0x280, sizeof(uint32_t), 0x10, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_COMMON_SECURE_ROM_TUNABLES_T8010_A0 \
|
||||
/* Key = secure_rom_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_0 */ 0x100, sizeof(uint32_t), 0x10, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_NVME_CTRL_0 */ 0x110, sizeof(uint32_t), 0x1, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_1 */ 0x180, sizeof(uint32_t), 0x10, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_2 */ 0x200, sizeof(uint32_t), 0x10, 0x0 }, \
|
||||
{ /* APCIE_COMMON_BLK_APCIE_PORT_CTRL_3 */ 0x280, sizeof(uint32_t), 0x10, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_T8010_A0_TUNABLE_APCIE_COMMON_H */
|
||||
@@ -0,0 +1,201 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_T8010_A0_TUNABLE_APCIE_CONFIG_H
|
||||
#define SPDS_T8010_A0_TUNABLE_APCIE_CONFIG_H
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xff)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0xff)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xd)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_INBCTRL_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0x2)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_INBCTRL_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x1)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_OUTBCTRL_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0x1)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_OUTBCTRL_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x3)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_DEFAULT_TUNABLES_T8010_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0xd, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT0_APCIE_CONFIG_SECURE_ROM_TUNABLES_T8010_A0 \
|
||||
/* Key = secure_rom_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x2, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xff)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0xff)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xd)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_INBCTRL_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0x2)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_INBCTRL_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x1)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_OUTBCTRL_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0x1)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_OUTBCTRL_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x3)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_DEFAULT_TUNABLES_T8010_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0xd, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT1_APCIE_CONFIG_SECURE_ROM_TUNABLES_T8010_A0 \
|
||||
/* Key = secure_rom_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x2, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xff)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0xff)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xd)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_INBCTRL_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0x2)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_INBCTRL_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x1)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_OUTBCTRL_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0x1)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_OUTBCTRL_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x3)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_DEFAULT_TUNABLES_T8010_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0xd, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT2_APCIE_CONFIG_SECURE_ROM_TUNABLES_T8010_A0 \
|
||||
/* Key = secure_rom_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x2, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xff)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0xff)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_PMETOACK_TMOTLIM_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x28)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xd)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_INBCTRL_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x5)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_INBCTRL_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0x2)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_INBCTRL_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x1)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_OUTBCTRL_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_OUTBCTRL_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0x1)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_OUTBCTRL_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x1)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x7f7f)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_MCACHE_HINT_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x3)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_L1_SUBCTRL_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x2)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_UMASK_T8010_A0 (0x8073ffff)
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_BLK_AF_TMOT_CTRL_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x403d09)
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_DEFAULT_TUNABLES_T8010_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0xd, 0x5 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ /* APCIE_CONFIG_BLK_MCACHE_HINT */ 0x138, sizeof(uint32_t), 0x7f7f, 0x0 }, \
|
||||
{ /* APCIE_CONFIG_BLK_L1_SUBCTRL */ 0x13c, sizeof(uint32_t), 0x3, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_AF_TMOT_CTRL */ 0x140, sizeof(uint32_t), 0x8073ffff, 0x403d09 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_APCIE_PORT3_APCIE_CONFIG_SECURE_ROM_TUNABLES_T8010_A0 \
|
||||
/* Key = secure_rom_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* APCIE_CONFIG_BLK_PMETOACK_TMOTLIM */ 0x90, sizeof(uint32_t), 0xff, 0x28 }, \
|
||||
{ /* APCIE_CONFIG_BLK_INBCTRL */ 0x130, sizeof(uint32_t), 0x2, 0x2 }, \
|
||||
{ /* APCIE_CONFIG_BLK_OUTBCTRL */ 0x134, sizeof(uint32_t), 0x1, 0x1 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_T8010_A0_TUNABLE_APCIE_CONFIG_H */
|
||||
@@ -0,0 +1,141 @@
|
||||
/*
|
||||
* Automatically generated by socgen. DO NOT EDIT!
|
||||
*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_T8010_A0_TUNABLE_X2_PCIE_RC_H
|
||||
#define SPDS_T8010_A0_TUNABLE_X2_PCIE_RC_H
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_T8010_A0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_DEFAULT_TUNABLES_T8010_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_FPGA_TUNABLES_T8010_A0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC0_SECURE_ROM_TUNABLES_T8010_A0 \
|
||||
/* Key = secure_rom_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_T8010_A0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_DEFAULT_TUNABLES_T8010_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_FPGA_TUNABLES_T8010_A0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC1_SECURE_ROM_TUNABLES_T8010_A0 \
|
||||
/* Key = secure_rom_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_T8010_A0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_DEFAULT_TUNABLES_T8010_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_FPGA_TUNABLES_T8010_A0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC2_SECURE_ROM_TUNABLES_T8010_A0 \
|
||||
/* Key = secure_rom_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xf)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_UMASK_T8010_A0 (0x1f)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_FPGA_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_UMASK_T8010_A0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_DEFAULT_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_SECURE_ROM_TUNABLE_UMASK_T8010_A0 (0xf8ff00)
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_SECURE_ROM_TUNABLE_VALUE_T8010_A0 (0x0)
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_DEFAULT_TUNABLES_T8010_A0 \
|
||||
/* Key = default_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG */ 0x98, sizeof(uint32_t), 0xf, 0x0 }, \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_FPGA_TUNABLES_T8010_A0 \
|
||||
/* Key = fpga_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0x1f, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#define PCIE_PCIE_CONFIG_PCIE_RC3_SECURE_ROM_TUNABLES_T8010_A0 \
|
||||
/* Key = secure_rom_tunable_key */ \
|
||||
/* Register Macro Identifier Register Offset Register Size Tunable Mask Tunable Value */ \
|
||||
{ /* X2_PCIE_RC_X2_PCIE_DSP_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG */ 0x164, sizeof(uint32_t), 0xf8ff00, 0x0 }, \
|
||||
{ -1, -1, -1, -1 }
|
||||
|
||||
#endif /* SPDS_T8010_A0_TUNABLE_X2_PCIE_RC_H */
|
||||
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_T8010_TUNABLE_APCIE_COMMON_H
|
||||
#define SPDS_T8010_TUNABLE_APCIE_COMMON_H
|
||||
|
||||
#include <platform/soc/t8010/a0/tunable/apcie_common.h>
|
||||
|
||||
#endif /* SPDS_T8010_TUNABLE_APCIE_COMMON_H */
|
||||
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_T8010_TUNABLE_APCIE_CONFIG_H
|
||||
#define SPDS_T8010_TUNABLE_APCIE_CONFIG_H
|
||||
|
||||
#include <platform/soc/t8010/a0/tunable/apcie_config.h>
|
||||
|
||||
#endif /* SPDS_T8010_TUNABLE_APCIE_CONFIG_H */
|
||||
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (c) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple inc.
|
||||
*/
|
||||
|
||||
#ifndef SPDS_T8010_TUNABLE_X2_PCIE_RC_H
|
||||
#define SPDS_T8010_TUNABLE_X2_PCIE_RC_H
|
||||
|
||||
#include <platform/soc/t8010/a0/tunable/x2_pcie_rc.h>
|
||||
|
||||
#endif /* SPDS_T8010_TUNABLE_X2_PCIE_RC_H */
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_TRAMPOLINE_H
|
||||
#define __PLATFORM_TRAMPOLINE_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
/* ROM related registers in AOP MINIPMGR space */
|
||||
|
||||
#define SECURITY_REG (AOP_MINIPMGR_BASE_ADDR + 0xD0010)
|
||||
#define ROM_READ_DISABLE (1 << 0)
|
||||
|
||||
#define REMAP_REG (AOP_MINIPMGR_BASE_ADDR + 0xD0014)
|
||||
|
||||
#endif /* ! __PLATFORM_TRAMPOLINE_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_UARTCONFIG_H
|
||||
#define __PLATFORM_UARTCONFIG_H
|
||||
|
||||
/* define one debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (0)
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define UART_OVERSAMPLE_OVERRIDE (11)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_USBCONFIG_H
|
||||
#define __PLATFORM_USBCONFIG_H
|
||||
|
||||
#if SUB_PLATFORM_T8010
|
||||
/*
|
||||
* per Cayman Tunables Specification, SPDS version 0.0.1
|
||||
*/
|
||||
|
||||
#define USBPHY_OTGTUNE0 (0x37377BC3)
|
||||
#define USBPHY_OTGTUNE1 (0x00020C04)
|
||||
|
||||
#else
|
||||
#error "Unknown SUB_PLATFORM"
|
||||
#endif
|
||||
|
||||
#define USBOTG_AHB_DMA_BURST (DWCUSB_GAHBCFG_HBST_INCR16)
|
||||
|
||||
#endif /* ! __PLATFORM_USBCONFIG_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,210 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <arch.h>
|
||||
#include <debug.h>
|
||||
#include <drivers/miu.h>
|
||||
#include <platform.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <platform/miu.h>
|
||||
#include <platform/soc/miu.h>
|
||||
#include <platform/soc/pmgr.h>
|
||||
#include <platform/clocks.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
|
||||
static void miu_configure_bridge(const uint32_t *bridge_settings);
|
||||
|
||||
#define STATIC_BRIDGE_SHIFT (28)
|
||||
#define STATIC_BRIDGE_MASK ((1 << STATIC_BRIDGE_SHIFT) - 1)
|
||||
|
||||
// !!!FIXME!!! <rdar://problem/19602477> H9: Implement static MIU bridge setting
|
||||
#define SB_WIDGETS (0 << STATIC_BRIDGE_SHIFT)
|
||||
#define SOCBUSMUX_WIDGETS (1 << STATIC_BRIDGE_SHIFT)
|
||||
#define SWITCH_FAB_WIDGETS (2 << STATIC_BRIDGE_SHIFT)
|
||||
#define CP_WIDGETS (3 << STATIC_BRIDGE_SHIFT)
|
||||
|
||||
static const uint64_t bridge_registers[] = {
|
||||
#if 0 // <rdar://problem/19602477> H9: Implement static MIU bridge setting
|
||||
SB_BASE_ADDR,
|
||||
SOC_BUSMUX_BASE_ADDR,
|
||||
SWTCH_FAB_BASE_ADDR,
|
||||
CP_COM_BASE_ADDR,
|
||||
#endif
|
||||
0
|
||||
};
|
||||
|
||||
|
||||
#if (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
|
||||
|
||||
static const uint32_t bridge_settings_static[] = {
|
||||
0,0
|
||||
};
|
||||
|
||||
#endif // (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
#if SUPPORT_FPGA
|
||||
|
||||
struct bridge_list_t {
|
||||
char *bridge_settings;
|
||||
uint32_t fpga_enable_mask;
|
||||
};
|
||||
|
||||
#define BRIDGE(b, m) { "bridge-settings-" #b, (m) }
|
||||
|
||||
// ALERT: The ordering effects the device tree entries under pmgr node's reg dictionary.
|
||||
// It also affects the bridge id used in the pmgr device-clock nodes. The
|
||||
// bridge id must match the id on the device tree bridge-settings-<n> properties.
|
||||
// NOTE: The second parameter on the BRIDGE macro is used to dynamically determine
|
||||
// which bridge settings properties should exist based upon the hardware
|
||||
// blocks actually present on the device.
|
||||
|
||||
static const struct bridge_list_t bridge_list[] = {
|
||||
BRIDGE(0, FPGA_HAS_MEDIA), // Media Bus Mux
|
||||
BRIDGE(1, FPGA_HAS_MSR), // MSR_AXI2AF
|
||||
BRIDGE(2, FPGA_HAS_JPEG), // AJPEG_AXI2AF
|
||||
BRIDGE(3, FPGA_HAS_AVE), // AVE_AXI2AF
|
||||
BRIDGE(4, FPGA_HAS_VXD), // VDEC0_AXI2AF
|
||||
BRIDGE(5, FPGA_HAS_ISP), // ISP_DMA_AXI2AF + ISAP_KF_AXI2AF
|
||||
BRIDGE(6, FPGA_HAS_RTBUSMUX), // RTBusMux
|
||||
BRIDGE(7, FPGA_HAS_DISP), // Disp0
|
||||
BRIDGE(8, FPGA_HAS_GFX), // GFX
|
||||
BRIDGE(9, FPGA_HAS_GFX), // GFX_AFUSER
|
||||
BRIDGE(10, FPGA_HAS_ALWAYS), // USB
|
||||
BRIDGE(11, FPGA_HAS_ALWAYS), // PCIe
|
||||
};
|
||||
|
||||
#endif // SUPPORT_FPGA
|
||||
#endif // WITH_DEVICETREE
|
||||
|
||||
extern void ausb_setup_widgets();
|
||||
|
||||
int miu_initialize_internal_ram(void)
|
||||
{
|
||||
#if APPLICATION_SECUREROM
|
||||
// Ensure that rPMGR_SCRATCH0-3 get cleared
|
||||
rPMGR_SCRATCH0 = 0;
|
||||
rPMGR_SCRATCH1 = 0;
|
||||
rPMGR_SCRATCH2 = 0;
|
||||
rPMGR_SCRATCH3 = 0;
|
||||
#endif /* APPLICATION_SECUREROM */
|
||||
|
||||
// Save the Security Epoch in the top byte of PMGR_SCRATCH0
|
||||
rPMGR_SCRATCH0 &= ~0xFF000000;
|
||||
rPMGR_SCRATCH0 |= (platform_get_security_epoch()) << 24;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int miu_init(void)
|
||||
{
|
||||
#if APPLICATION_IBOOT && !PRODUCT_IBEC
|
||||
// Verify that the Security Epoch in PMGR_SCRATCH0 matches
|
||||
if ((rPMGR_SCRATCH0 >> 24) != platform_get_security_epoch()) {
|
||||
panic("miu_init: Epoch Mismatch\n");
|
||||
}
|
||||
#endif
|
||||
#if (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
|
||||
miu_configure_bridge(bridge_settings_static);
|
||||
#endif
|
||||
ausb_setup_widgets();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void miu_suspend(void)
|
||||
{
|
||||
/* nothing required for suspend */
|
||||
}
|
||||
|
||||
int miu_initialize_dram(bool resume)
|
||||
{
|
||||
RELEASE_ASSERT(!resume);
|
||||
|
||||
#if APPLICATION_IBOOT && WITH_HW_DCS
|
||||
mcu_initialize_dram(resume);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
void miu_select_remap(enum remap_select sel)
|
||||
{
|
||||
switch (sel) {
|
||||
case REMAP_SRAM:
|
||||
rSECUREROMCTRL_ROMADDRREMAP = (rSECUREROMCTRL_ROMADDRREMAP & ~MINIPMGR_SECURITY_MCC_ROMADDRREMAP_ROMADDRRREMAP_UMASK) | SECUREROMCTRL_ROMADDRREMAP_SRAM;
|
||||
break;
|
||||
|
||||
case REMAP_SDRAM:
|
||||
rSECUREROMCTRL_ROMADDRREMAP = (rSECUREROMCTRL_ROMADDRREMAP & ~MINIPMGR_SECURITY_MCC_ROMADDRREMAP_ROMADDRRREMAP_UMASK) | SECUREROMCTRL_ROMADDRREMAP_SDRAM;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void miu_bypass_prep(void)
|
||||
{
|
||||
}
|
||||
|
||||
static void miu_configure_bridge(const uint32_t *bridge_settings)
|
||||
{
|
||||
volatile uint32_t *reg;
|
||||
uint32_t cnt = 0, bridge, offset, data;
|
||||
|
||||
while ((bridge_settings[cnt] != 0) || (bridge_settings[cnt + 1] != 0)) {
|
||||
while ((bridge_settings[cnt] != 0) || (bridge_settings[cnt + 1] != 0)) {
|
||||
bridge = bridge_settings[cnt] >> STATIC_BRIDGE_SHIFT;
|
||||
offset = bridge_settings[cnt] & STATIC_BRIDGE_MASK;
|
||||
data = bridge_settings[cnt + 1];
|
||||
reg = (volatile uint32_t *)(bridge_registers[bridge] + offset);
|
||||
*reg = data;
|
||||
cnt += 2;
|
||||
}
|
||||
cnt += 2;
|
||||
}
|
||||
}
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
#define DEBUG_BRIDGE DEBUG_SPEW // Debug level for bridge messages
|
||||
|
||||
void miu_update_device_tree(DTNode *pmgr_node)
|
||||
{
|
||||
#if SUPPORT_FPGA
|
||||
DTNode *node;
|
||||
char *propName;
|
||||
void *propData;
|
||||
uint32_t propSize;
|
||||
uint32_t fpga_blocks = chipid_get_fpga_block_instantiation();
|
||||
uint32_t i;
|
||||
|
||||
dprintf(DEBUG_INFO, "chipid_get_fpga_block_instantiation() = 0x%08X\n",
|
||||
fpga_blocks);
|
||||
|
||||
if (FindNode(0, "arm-io/pmgr", &node)) {
|
||||
|
||||
// For each bridge...
|
||||
for (i = 0; i < ARRAY_SIZE(bridge_list); i++) {
|
||||
|
||||
// Filter out if not supported by FPGA
|
||||
if (!(fpga_blocks & bridge_list[i].fpga_enable_mask)) {
|
||||
|
||||
propName = bridge_list[i].bridge_settings;
|
||||
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
dprintf(DEBUG_CRITICAL, "Eliding %s\n", propName);
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif // SUPPORT_FPGA
|
||||
}
|
||||
|
||||
#endif // WITH_DEVICETREE
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_MIU=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/miu.o
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,17 @@
|
||||
# Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_CLOCKS=1 \
|
||||
WITH_HW_PLATFORM_POWER=1 \
|
||||
WITH_HW_POWER_GATING=0
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/pmgr.o
|
||||
@@ -0,0 +1,136 @@
|
||||
# Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
# modules implied by this platform
|
||||
MODULES += \
|
||||
platform/defaults \
|
||||
platform/generic \
|
||||
arch/$(ARCH)
|
||||
|
||||
# Devmap chip ID, CPU, and memory default configs based on sub-platform identifier
|
||||
ifeq ($(SUB_PLATFORM),t8010)
|
||||
ARM_CPU := apple-hurricane-zephyr
|
||||
DEVMAP_CHIP_ID := 8010
|
||||
DISPLAY_SIZE_DEFAULT := 34*1024*1024
|
||||
MAX_DFU_SIZE := 512*1024
|
||||
SDRAM_LEN_DEFAULT := 2*1024*1024*1024
|
||||
SDRAM_LOAD_OFFSET := 256*1024*1024
|
||||
SDRAM_TEXT_BASE := 0x870000000
|
||||
SDRAM_TEXT_FOOTPRINT := 1024*1024
|
||||
SRAM_TEXT_BASE := 0x1800B0000
|
||||
SRAM_TEXT_FOOTPRINT := 1024*1024
|
||||
SROM_DATA_BASE := 0x180080000
|
||||
SPDS_CHIP_REV := a0
|
||||
else
|
||||
$(error "Unrecognized SUB_PLATFORM \"$(SUB_PLATFORM)\"")
|
||||
endif
|
||||
|
||||
# SROM is always defined here
|
||||
ifeq ($(TEXT_BANK),srom)
|
||||
TEXT_BASE := 0x100000000
|
||||
endif
|
||||
|
||||
# Overriding SRAM_LEN is not allowed.
|
||||
ifeq ($(TEXT_BANK),sram)
|
||||
# SRAM TEXT_BASE is fixed by SecureROM.
|
||||
TEXT_BASE := $(SRAM_TEXT_BASE)
|
||||
|
||||
# iBSS/LLB memory configuration
|
||||
ifeq ($(TEXT_FOOTPRINT),)
|
||||
TEXT_FOOTPRINT := $(SRAM_TEXT_FOOTPRINT)
|
||||
endif
|
||||
endif
|
||||
|
||||
# Platform target can override SDRAM config by specifying this in target config file (apps/iBoot/$target-config.mk)
|
||||
ifeq ($(SDRAM_LEN),)
|
||||
SDRAM_LEN := $(SDRAM_LEN_DEFAULT)
|
||||
|
||||
# iBoot/iBEC memory configuration
|
||||
ifeq ($(TEXT_BANK),sdram)
|
||||
# SDRAM TEXT_BASE is now set such that you don't have to do lots of math to
|
||||
# calulate the correct value if you change any of the other region sizes:
|
||||
# TEXT_BASE = SDRAM_BASE + SDRAM_LEN - 256MB
|
||||
TEXT_BASE := $(SDRAM_TEXT_BASE)
|
||||
# Platform target can override SRAM config by specifying this in target config file (apps/iBoot/$target-config.mk)
|
||||
ifeq ($(TEXT_FOOTPRINT),)
|
||||
TEXT_FOOTPRINT := $(SDRAM_TEXT_FOOTPRINT)
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
# Platform target can override any of these sizes by specifying in target config file (apps/iBoot/$target-config.mk)
|
||||
ifeq ($(TZ0_SIZE),)
|
||||
TZ0_SIZE := 12*1024*1024
|
||||
endif
|
||||
ifeq ($(DISPLAY_SIZE),)
|
||||
DISPLAY_SIZE := $(DISPLAY_SIZE_DEFAULT)
|
||||
endif
|
||||
|
||||
ifeq ($(TEXT_FOOTPRINT),)
|
||||
$(error TEXT_FOOTPRINT has not been set)
|
||||
endif
|
||||
|
||||
# platform target can override ASP size by specifying this in target config file (apps/iBoot/$target-config.mk)
|
||||
ifeq ($(ASP_SIZE),)
|
||||
ASP_SIZE := 12*1024*1024
|
||||
endif
|
||||
|
||||
OPTIONS += \
|
||||
AIC_CPU_ID=0 \
|
||||
ANC_PPNNPL_DS_DRIVE_STRENGTH=6 \
|
||||
ANC_PPNNPL_INPUT_SELECT_SCHMITT=1 \
|
||||
ANC_LINK_CMD_ADDR_PULSE_TIMING_CA_HOLD_TIME=2 \
|
||||
ANC_LINK_CMD_ADDR_PULSE_TIMING_CA_SETUP_TIME=3 \
|
||||
ANC_LINK_SDR_REN_HOLD_TIME=2 \
|
||||
ANC_LINK_SDR_REN_SETUP_TIME=3 \
|
||||
ANC_LINK_SDR_WEN_HOLD_TIME=2 \
|
||||
ANC_LINK_SDR_WEN_SETUP_TIME=3 \
|
||||
ANC_LINK_SDR_DATA_CAPTURE_DELAY=1 \
|
||||
ANC_LINK_SDR_CLE_ALE_SETUP_TIME=0 \
|
||||
ANC_BOOT_CONTROLLERS=2 \
|
||||
ANC_TOGGLE_SUPPORTED=1 \
|
||||
DISPLAY_SIZE="($(DISPLAY_SIZE)ULL)" \
|
||||
PLATFORM_ENTROPY_RATIO=200 \
|
||||
PLATFORM_IRQ_COUNT=288 \
|
||||
PLATFORM_START_FUNCTION=_platform_start \
|
||||
SDRAM_LEN="$(SDRAM_LEN)ULL" \
|
||||
TZ0_SIZE="$(TZ0_SIZE)ULL" \
|
||||
ASP_SIZE="$(ASP_SIZE)" \
|
||||
SDRAM_LOAD_OFFSET="$(SDRAM_LOAD_OFFSET)ULL" \
|
||||
PLATFORM_SPDS_CHIP_REV=$(SUB_PLATFORM)/$(SPDS_CHIP_REV) \
|
||||
TEXT_BASE="$(TEXT_BASE)" \
|
||||
TEXT_FOOTPRINT="$(TEXT_FOOTPRINT)" \
|
||||
WITH_DPA=1 \
|
||||
WITH_SIDP=1
|
||||
|
||||
GLOBAL_LDFLAGS += \
|
||||
-seg1addr $(TEXT_BASE)
|
||||
|
||||
ifeq ($(APPLICATION),SecureROM)
|
||||
DATA_BASE := $(SROM_DATA_BASE)
|
||||
GLOBAL_LDFLAGS += \
|
||||
-segaddr __DATA $(DATA_BASE)
|
||||
OPTIONS += \
|
||||
WITH_ROM_TRAMPOLINE=1 \
|
||||
DATA_BASE="$(DATA_BASE)"
|
||||
|
||||
ifeq ($(CONFIGS),fpga)
|
||||
OPTIONS += \
|
||||
SUPPORT_FPGA=1
|
||||
endif
|
||||
endif
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/asm.o \
|
||||
$(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/trampoline.o
|
||||
@@ -0,0 +1,215 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple, Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple, Inc.
|
||||
*/
|
||||
|
||||
#include <platform/memmap.h>
|
||||
#include <platform/trampoline.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <arch/arm64/proc_reg.h>
|
||||
|
||||
// Clears from X0 to X1 (not including X1).
|
||||
// Assumes that X0 and X1 are both 64-byte aligned as this
|
||||
// will normally be used to clear a whole page.
|
||||
.macro CLEAR_X0_TO_X1
|
||||
1:
|
||||
stp xzr, xzr, [x0], #16
|
||||
stp xzr, xzr, [x0], #16
|
||||
stp xzr, xzr, [x0], #16
|
||||
stp xzr, xzr, [x0], #16
|
||||
cmp x0, x1
|
||||
b.lo 1b
|
||||
.endmacro
|
||||
|
||||
// Clears from X0 to X1 (not including X1) using cacheline clear
|
||||
// operations.
|
||||
// Assumes that X0 and X1 are both cacheline aligned as this
|
||||
// will normally be used to clear a whole page.
|
||||
.macro CLEAR_X0_TO_X1_CACHE_ON
|
||||
1:
|
||||
dc zva, x0 // zero cacheline
|
||||
add x0, x0, #L1_CACHELINE_SIZE
|
||||
cmp x0, x1
|
||||
b.lo 1b
|
||||
.endmacro
|
||||
|
||||
.text
|
||||
.balign 16
|
||||
.globl _boot_handoff_trampoline, _boot_handoff_trampoline_end
|
||||
_boot_handoff_trampoline:
|
||||
|
||||
// Disable external aborts, interrupts
|
||||
msr DAIFSet, #(0xf)
|
||||
|
||||
// Save jump address in x29, and next stage boot info into x28.
|
||||
mov x29, x0
|
||||
mov x28, x1
|
||||
|
||||
// Start by clearing the heap.
|
||||
ldr x0, L_heap_base
|
||||
ldr x1, L_heap_end
|
||||
CLEAR_X0_TO_X1_CACHE_ON
|
||||
|
||||
// Clear the stacks area.
|
||||
ldr x0, L_stacks_base
|
||||
ldr x1, L_stacks_end
|
||||
CLEAR_X0_TO_X1_CACHE_ON
|
||||
|
||||
// Retire all data accesses prior to this
|
||||
// <rdar://problem/19862668> H9: L2 as RAM request RO and DO alias result in prb hang
|
||||
dsb sy
|
||||
// Retire all instructions executed prior to this (may include ROM).
|
||||
isb sy
|
||||
|
||||
// Disable caches, mmu, stack alignment fault
|
||||
mov x3, #0
|
||||
msr SCTLR_EL1, x3
|
||||
dsb sy
|
||||
isb sy
|
||||
|
||||
// Flush the TLBs
|
||||
tlbi vmalle1
|
||||
dsb sy
|
||||
isb sy
|
||||
|
||||
// Now running EL1 with MMU off. All accesses are device.
|
||||
|
||||
// Clear the page tables.
|
||||
ldr x0, L_page_tables_base
|
||||
ldr x1, L_page_tables_end
|
||||
CLEAR_X0_TO_X1
|
||||
|
||||
// Clear the text area (or data area in ROM)
|
||||
// This can only be done if the trampoline was copied to a safe location
|
||||
ldr x0, L_text_base
|
||||
ldr x1, L_text_end
|
||||
CLEAR_X0_TO_X1
|
||||
|
||||
// Clear all the pointers to interesting memory areas
|
||||
// that were included in the trampoline
|
||||
adr x0, L_pointers_base
|
||||
adr x1, L_pointers_end
|
||||
CLEAR_X0_TO_X1
|
||||
|
||||
#if WITH_ROM_TRAMPOLINE
|
||||
// Disable R/W access to ROM region
|
||||
ldr x1, L_rom_trampoline_reg
|
||||
ldr w2, L_rom_trampoline_val
|
||||
ldr w3, [x1]
|
||||
orr w3, w3, w2
|
||||
str w3, [x1]
|
||||
dsb sy
|
||||
ldr w3, [x1]
|
||||
tst w3, w2 // Verify ROM access is disabled
|
||||
b.eq _trampoline_spin // Oops, not disabled
|
||||
|
||||
// ROM doesn't pass any info to next stage (LLB)
|
||||
mov x28, #0
|
||||
|
||||
// Clear remap if enabled to boot this ROM
|
||||
ldr x1, L_rom_remap_reg
|
||||
str wzr, [x1]
|
||||
#endif // WITH_ROM_TRAMPOLINE
|
||||
|
||||
// Reset CPU state
|
||||
mov x1, #0
|
||||
mov x2, #0
|
||||
mov x3, #0
|
||||
mov x4, #0
|
||||
mov x5, #0
|
||||
mov x6, #0
|
||||
mov x7, #0
|
||||
mov x8, #0
|
||||
mov x9, #0
|
||||
mov x10, #0
|
||||
mov x11, #0
|
||||
mov x12, #0
|
||||
mov x13, #0
|
||||
mov x14, #0
|
||||
mov x15, #0
|
||||
mov x16, #0
|
||||
mov x17, #0
|
||||
mov x18, #0
|
||||
mov x19, #0
|
||||
mov x20, #0
|
||||
mov x21, #0
|
||||
mov x22, #0
|
||||
mov x23, #0
|
||||
mov x24, #0
|
||||
mov x25, #0
|
||||
mov x26, #0
|
||||
mov x27, #0
|
||||
mov x30, x29 // lr = next boot stage PC
|
||||
mov x0, x28 // x0 = next boot stage info
|
||||
mov x28, #0
|
||||
mov x29, #0
|
||||
msr TTBR0_EL1, x1
|
||||
msr VBAR_EL1, x1
|
||||
msr ELR_EL1, x1
|
||||
msr SPSR_EL1, x1
|
||||
msr SPSel, #0
|
||||
mov sp, x1 // SP_EL0
|
||||
msr SPSel, #1
|
||||
mov sp, x1 // SP_EL1
|
||||
|
||||
// Invalidate I-cache
|
||||
ic iallu
|
||||
dsb sy
|
||||
isb sy
|
||||
|
||||
ret
|
||||
|
||||
#if WITH_ROM_TRAMPOLINE
|
||||
// Not really able to panic at this point, so let's just spin.
|
||||
_trampoline_spin:
|
||||
wfe
|
||||
b _trampoline_spin
|
||||
|
||||
.balign 8
|
||||
L_rom_remap_reg:
|
||||
.8byte REMAP_REG
|
||||
L_rom_trampoline_reg:
|
||||
.8byte SECURITY_REG
|
||||
L_rom_trampoline_val:
|
||||
.4byte ROM_READ_DISABLE
|
||||
#endif // WITH_ROM_TRAMPOLINE
|
||||
|
||||
.balign 64
|
||||
L_pointers_base:
|
||||
#if WITH_ROM_TRAMPOLINE
|
||||
// in ROM we don't erase TEXT, but we can erase DATA
|
||||
L_text_base:
|
||||
.8byte DATA_BASE
|
||||
L_text_end:
|
||||
.8byte DATA_BASE + DATA_SIZE
|
||||
#else
|
||||
// In non-ROM we erase TEXT_FOOTPRINT, which includes both TEXT and DATA
|
||||
L_text_base:
|
||||
.8byte TEXT_BASE
|
||||
L_text_end:
|
||||
.8byte TEXT_BASE + TEXT_FOOTPRINT
|
||||
#endif // WITH_ROM_TRAMPOLINE
|
||||
L_heap_base:
|
||||
.8byte HEAP_BASE
|
||||
L_heap_end:
|
||||
.8byte HEAP_BASE + HEAP_SIZE
|
||||
L_stacks_base:
|
||||
.8byte STACKS_BASE
|
||||
L_stacks_end:
|
||||
.8byte STACKS_BASE + STACKS_SIZE
|
||||
L_page_tables_base:
|
||||
.8byte PAGE_TABLES_BASE
|
||||
L_page_tables_end:
|
||||
.8byte PAGE_TABLES_BASE + PAGE_TABLES_SIZE
|
||||
.balign 64
|
||||
L_pointers_end:
|
||||
|
||||
_boot_handoff_trampoline_end:
|
||||
|
||||
.balign 16
|
||||
Reference in new issue
Block a user