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@@ -0,0 +1,27 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ADBE_SETTINGS_H
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#define __TARGET_ADBE_SETTINGS_H
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static struct adbe_v1_tuneable adbe_tuneables[] = {
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{
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.name = "default",
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.adbe0_vblank_pos_vbi_pulse = 0x0000,
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.adbe0_vblank_clk_gate_wakeup = 0x0000,
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.adbe0_vblank_clk_gate_idle = 0x0001,
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.adbe0_vblank_blk_idle_dpb = 0x0000,
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.adbe0_vblank_blk_idle_aap = 0x0000,
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.adbe0_tunable_mode_ctrl = (DBEMODECNTL_DYN_CLK_GATE_ENABLE | DBEMODECNTL_AFC_TEARDOWN_ENABLE | DBEMODECNTL_PMGR_CLK_GATE_ENABL| DBEMODECNTL_BLK_CLK_GATE_ENABLE),
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.adbe0_aap_support = 1,
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},
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};
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#endif
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ASPNANDCONFIG_H
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#define __TARGET_ASPNANDCONFIG_H
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//MLC devices
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#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
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#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_DIES_IN_PARALLEL 4
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#define ASPNAND_READ_DIES_IN_PARALLEL 4
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#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
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//TLC devices
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#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
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// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
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#define ASPNAND_INDIRECTION_MEMORY (2*1024*1024)
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#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
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#endif
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@@ -0,0 +1,28 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* iRef,x specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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/* define target-specific gpios in a generic fashion here. */
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#define GPIO_RINGER_AB GPIO( 2, 0)
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#define GPIO_WDOG GPIO( 0, 1) // WDOG
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/* D2094 watchdog tickle, 'KEEPACT' */
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#define GPIO_WDOG_TICKLE GPIO(2, 5)
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,88 @@
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD2045_LDO9_VSEL, 0x5A}, // LDO9 (PP2V8_CAM) to 2.85V <rdar://problem/12660594>
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{ PMU_IIC_BUS, kD2045_ACTIVE3, 0xAE }, // Current OTP enables LDO{1,2,3,4,5,7}, disable LDO4.
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{ PMU_IIC_BUS, kD2045_ACTIVE6, 0x37 }, // enable BUCK3_SW1, BUCK3_SW2, BUCK3_SW3, BUCK4_SW1, BUCK4_SW2
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{ PMU_IIC_BUS, kD2045_ACTIVE3, 0xBE }, // enable LDO4 along with LDO{1,2,3,5,7}
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{ PMU_IIC_BUS, kD2045_HIBERNATE1, 0x18 },
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{ PMU_IIC_BUS, kD2045_HIBERNATE3, 0x18 },
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{ PMU_IIC_BUS, kD2045_HIBERNATE6, 0x24 },
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup_a0[] =
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{
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{ PMU_IIC_BUS, kD2045_LDO9_VSEL, 0x42}, // LDO9 (PP2V8_CAM) to 2.85V <rdar://problem/12660594>
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{ PMU_IIC_BUS, kD2045_ACTIVE3, 0xAE }, // Current OTP enables LDO{1,2,3,4,5,7}, disable LDO4.
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{ PMU_IIC_BUS, kD2045_ACTIVE6, 0x37 }, // enable BUCK3_SW1, BUCK3_SW2, BUCK3_SW3, BUCK4_SW1, BUCK4_SW2
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{ PMU_IIC_BUS, kD2045_ACTIVE3, 0xBE }, // enable LDO4 along with LDO{1,2,3,5,7}
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// <rdar://problem/12264399> N51: Workaround needed for hibernate on PROTO2 Amber OTP
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{ PMU_IIC_BUS, 0x7000, 0x1d }, // Enable test mode
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{ PMU_IIC_BUS, kD2045_BUTTON4_CONF, 0x94 }, // Set BUTTON4 config to be pulled up to VBUCK3 instead of VBUCK3_SW
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{ PMU_IIC_BUS, 0x7000, 0x00 }, // Disable test mode
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{ PMU_IIC_BUS, kD2045_HIBERNATE1, 0x18 },
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{ PMU_IIC_BUS, kD2045_HIBERNATE3, 0x18 },
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{ PMU_IIC_BUS, kD2045_HIBERNATE6, 0x24 },
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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};
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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{ PMU_IIC_BUS, kD2045_GPIO_DEB2, 0x12 },
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{ PMU_IIC_BUS, kD2045_GPIO_DEB5, 0x12 },
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{ PMU_IIC_BUS, kD2045_GPIO_DEB6, 0x12 },
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{ PMU_IIC_BUS, kD2045_BUCK_DWI_CTRL0, 0x03 }, // enable DWI for BUCK0, BUCK1
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{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2, 0x11 }, // enable HIB_32kHz (for WIFI/BT) and DWI
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{ PMU_IIC_BUS, kD2045_ACT_TO_HIB_DLY, 0x03 }, // set ACT_TO_HIB_DLY to 3 (6ms)
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};
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static const struct core_rails_struct soc_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2045_BUCK2_VSEL }
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};
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static const struct core_rails_struct cpu_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2045_BUCK0_VSEL }
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};
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static const struct core_rails_struct ram_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2045_BUCK5_VSEL }
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};
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#endif /* POWERCONFIG_PMU_SETUP */
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#define NO_BATTERY_VOLTAGE 2700
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#define MIN_BOOT_BATTERY_VOLTAGE 3600
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#define TARGET_BOOT_BATTERY_VOLTAGE 3700
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#define TARGET_BOOT_BATTERY_CAPACITY 50
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#define PRECHARGE_BACKLIGHT_LEVEL 824
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#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
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#define ACC_PWR_LDO (6)
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#endif
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@@ -0,0 +1,23 @@
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/*
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* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_UARTCONFIG_H
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#define __TARGET_UARTCONFIG_H
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/* define one debug serial ports */
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#define DEBUG_SERIAL_PORT (0)
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#define HDQGAUGE_SERIAL_PORT (5)
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#if SUPPORT_FPGA
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#define UART_OVERSAMPLE_OVERRIDE (11)
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#endif
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#endif
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@@ -0,0 +1,112 @@
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/*
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* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
|
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* Apple Inc.
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*/
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#include <debug.h>
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#include <drivers/flash_nor.h>
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#include <drivers/iic.h>
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#include <drivers/power.h>
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#include <lib/devicetree.h>
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#include <lib/env.h>
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#include <lib/mib.h>
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#include <lib/syscfg.h>
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#include <platform.h>
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#include <platform/gpio.h>
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#include <platform/gpiodef.h>
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#include <sys.h>
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#include <sys/boot.h>
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#include <sys/menu.h>
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#include <target.h>
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MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
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MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
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uint32_t display_config;
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void target_early_init(void)
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{
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}
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void target_late_init(void)
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{
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}
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void target_init(void)
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{
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#if WITH_HW_FLASH_NOR
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flash_nor_init(SPI_NOR0);
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#endif
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}
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void target_quiesce_hardware(void)
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{
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}
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void target_poweroff(void)
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{
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}
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int target_bootprep(enum boot_target target)
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{
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return 0;
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}
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bool target_should_recover(void)
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{
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return platform_get_request_dfu2() && power_has_usb();
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}
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bool target_should_poweron(bool *cold_button_boot)
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{
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#if WITH_HW_POWER
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if (power_get_boot_flag() == kPowerBootFlagColdButton) *cold_button_boot = true;
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#else
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*cold_button_boot = false;
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#endif // WITH_HW_POWER
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return !*cold_button_boot || platform_get_request_dfu1();
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}
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bool target_should_poweroff(bool at_boot)
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{
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return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
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}
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#if APPLICATION_IBOOT
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void target_watchdog_tickle(void)
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{
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uint32_t value = gpio_read(GPIO_WDOG_TICKLE);
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gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
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}
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#endif // APPLICATION_IBOOT
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void * target_get_display_configuration(void)
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{
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display_config = 0x00000da2;
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return ((void *)(&display_config));
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}
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#if WITH_ENV
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void target_setup_default_environment(void)
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{
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env_set("boot-device", "asp_nand", 0);
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env_set("display-color-space","RGB888", 0);
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env_set("display-timing", "n51", 0);
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}
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#endif // WITH_ENV
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#if WITH_DEVICETREE
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int target_update_device_tree(void)
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{
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return 0;
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}
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#endif // WITH_DEVICETREE
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@@ -0,0 +1,308 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
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||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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*/
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#include <drivers/apple/gpio.h>
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#include <platform/soc/hwregbase.h>
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#include <stdint.h>
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/* N51/N53 (iPhone6,x) Pin Configuration */
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/*
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* N51 pinlist v0.13
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* <rdar://problem/11763484> N51 HW ERS | System | Pinlist
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*/
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#define CFG_DISABLED_SS_X4 (CFG_DISABLED | SLOW_SLEW | DRIVE_X4 )
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#define CFG_DISABLED_SS_X4_PD (CFG_DISABLED | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
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#define CFG_DISABLED_SS_X1_PD (CFG_DISABLED | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
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#define CFG_DISABLED_SS_X4_PU (CFG_DISABLED | SLOW_SLEW | DRIVE_X4 | PULL_UP )
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#define CFG_DISABLED_SS_X1_PU (CFG_DISABLED | SLOW_SLEW | DRIVE_X1 | PULL_UP )
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#define CFG_IN_SS_X1 (CFG_IN | SLOW_SLEW | DRIVE_X1 )
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#define CFG_IN_SS_X2 (CFG_IN | SLOW_SLEW | DRIVE_X2 )
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#define CFG_IN_SS_X4 (CFG_IN | SLOW_SLEW | DRIVE_X4 )
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#define CFG_IN_SS_X4_PD (CFG_IN | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
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#define CFG_IN_SS_X1_PD (CFG_IN | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
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#define CFG_IN_SS_X4_PU (CFG_IN | SLOW_SLEW | DRIVE_X4 | PULL_UP )
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#define CFG_IN_SS_X1_PU (CFG_IN | SLOW_SLEW | DRIVE_X1 | PULL_UP )
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#define CFG_OUT_0_SS_X4 (CFG_OUT_0 | SLOW_SLEW | DRIVE_X4 )
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#define CFG_OUT_0_SS_X4_PD (CFG_OUT_0 | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
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#define CFG_OUT_0_SS_X1_PD (CFG_OUT_0 | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
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||||
#define CFG_OUT_0_SS_X4_PU (CFG_OUT_0 | SLOW_SLEW | DRIVE_X4 | PULL_UP )
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||||
#define CFG_OUT_0_SS_X1_PU (CFG_OUT_0 | SLOW_SLEW | DRIVE_X1 | PULL_UP )
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||||
#define CFG_OUT_1_SS_X4 (CFG_OUT_1 | SLOW_SLEW | DRIVE_X4 )
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||||
#define CFG_OUT_1_SS_X4_PD (CFG_OUT_1 | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
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||||
#define CFG_OUT_1_SS_X1_PD (CFG_OUT_1 | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
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||||
#define CFG_OUT_1_SS_X4_PU (CFG_OUT_1 | SLOW_SLEW | DRIVE_X4 | PULL_UP )
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||||
#define CFG_OUT_1_SS_X1_PU (CFG_OUT_1 | SLOW_SLEW | DRIVE_X1 | PULL_UP )
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#define CFG_FUNC0_SS_X1 (CFG_FUNC0 | SLOW_SLEW | DRIVE_X1 )
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#define CFG_FUNC0_SS_X2 (CFG_FUNC0 | SLOW_SLEW | DRIVE_X2 )
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#define CFG_FUNC0_SS_X4 (CFG_FUNC0 | SLOW_SLEW | DRIVE_X4 )
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#define CFG_FUNC0_SS_X4_PD (CFG_FUNC0 | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
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||||
#define CFG_FUNC0_SS_X2_PD (CFG_FUNC0 | SLOW_SLEW | DRIVE_X2 | PULL_DOWN)
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||||
#define CFG_FUNC0_SS_X1_PD (CFG_FUNC0 | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
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#define CFG_FUNC0_SS_X4_PU (CFG_FUNC0 | SLOW_SLEW | DRIVE_X4 | PULL_UP )
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#define CFG_FUNC0_SS_X1_PU (CFG_FUNC0 | SLOW_SLEW | DRIVE_X1 | PULL_UP )
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static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
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||||
/* Port 0 */
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||||
CFG_DISABLED_SS_X4_PD, // TST_CLKOUT -> AP_TO_PMU_TEST_CLKOUT
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||||
CFG_DISABLED_SS_X4_PD, // WDOG -> AP_TO_PMU_RESET_IN
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||||
CFG_IN_SS_X1, // GPIO0 -> BUTTON_TO_AP_MENU_KEY_BUFF_L
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||||
CFG_IN_SS_X1, // GPIO1 -> BUTTON_TO_AP_HOLD_KEY_BUFF_L
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||||
CFG_IN_SS_X1_PU, // GPIO2 -> BUTTON_TO_AP_VOL_UP_L
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||||
CFG_IN_SS_X1_PU, // GPIO3 -> BUTTON_TO_AP_VOL_DOWN_L
|
||||
CFG_IN_SS_X1_PU, // GPIO4 -> PMU_NIRQ [PMU_TO_AP_IRQ_L in N51]
|
||||
CFG_OUT_0_SS_X4_PD, // GPIO5 -> AP_TO_SPKAMP_BEE_GEES
|
||||
|
||||
/* Port 1 */
|
||||
CFG_OUT_0_SS_X4_PD, // GPIO6 -> AP_TO_SPKAMP_RESET_L
|
||||
CFG_OUT_0_SS_X4_PD, // GPIO7 -> AP_TO_BT_WAKE
|
||||
CFG_IN_SS_X4, // GPIO8 -> AP_TO_BB_RST_L
|
||||
CFG_DISABLED_SS_X4, // GPIO9 -> AP_TO_BB_JTAG_TDI
|
||||
CFG_DISABLED_SS_X4_PD, // GPIO10 -> AP_TO_BB_JTAG_TDO
|
||||
CFG_DISABLED_SS_X4_PD, // GPIO11 -> AP_TO_HEADSET_HS3_CTRL
|
||||
CFG_DISABLED_SS_X4_PD, // GPIO12 -> AP_TO_HEADSET_HS4_CTRL
|
||||
CFG_DISABLED, // GPIO13 -> NULL
|
||||
|
||||
/* Port 2 */
|
||||
CFG_IN_SS_X1, // GPIO14 -> BUTTON_TO_AP_RINGER_A
|
||||
CFG_OUT_0_SS_X4, // GPIO15 -> AP_TO_BB_WAKE_MODEM
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO16 -> N/C -> BOARD_ID[3]
|
||||
CFG_IN_SS_X1, // GPIO17 -> AP_TO_OSCAR_DBGEN
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO18 -> BOARD_INFO -> BOOT_CONFIG[0]
|
||||
CFG_DISABLED, // GPIO19 -> NULL
|
||||
CFG_DISABLED, // GPIO20 -> NULL
|
||||
CFG_DISABLED, // GPIO21 -> NULL
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_FUNC0_SS_X4_PU, // UART1_TXD -> AP_TO_BT_UART1_TXD
|
||||
CFG_FUNC0_SS_X1_PU, // UART1_RXD -> BT_TO_AP_UART1_RXD
|
||||
CFG_FUNC0_SS_X4_PU, // UART1_RTSN -> AP_TO_BT_UART1_RTS_L
|
||||
CFG_FUNC0_SS_X1_PU, // UART1_CTSN -> BT_TO_AP_UART1_CTS_L
|
||||
CFG_FUNC0_SS_X4_PU, // UART2_TXD -> AP_TO_OSCAR_UART2_TXD
|
||||
CFG_FUNC0_SS_X1_PU, // UART2_RXD -> OSCAR_TO_AP_UART2_RXD
|
||||
CFG_OUT_1_SS_X4_PU, // UART2_RTSN -> AP_TO_OSCAR_RESET_L
|
||||
CFG_IN_SS_X1_PD, // UART2_CTSN -> OSCAR_TO_PMU_HOST_WAKE
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0_SS_X4, // UART3_TXD -> AP_TO_WLAN_UART3_TXD
|
||||
CFG_FUNC0_SS_X1, // UART3_RXD -> WLAN_TO_AP_UART3_RXD
|
||||
CFG_DISABLED_SS_X1_PD, // UART3_RTSN -> BB_TO_AP_PP_SYNC
|
||||
CFG_OUT_0_SS_X4_PD, // UART3_CTSN -> AP_TO_RCAM_VDDCORE_EN
|
||||
CFG_FUNC0_SS_X2, // UART5_RXD -> AP_BI_BATTERY_SWI
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 8 */
|
||||
CFG_OUT_0_SS_X4, // UART4_TXD -> AP_TO_BB_UART4_TXD
|
||||
CFG_FUNC0_SS_X1, // UART4_RXD -> BB_TO_AP_UART4_RXD
|
||||
CFG_OUT_0_SS_X4, // UART4_RTSN -> AP_TO_BB_UART4_RTS_L
|
||||
CFG_FUNC0_SS_X1, // UART4_CTSN -> BB_TO_AP_UART4_CTS_L
|
||||
CFG_FUNC0_SS_X4_PD, // SPI1_SCLK -> AP_TO_TOUCH_SPI1_CLK
|
||||
CFG_FUNC0_SS_X4_PD, // SPI1_MOSI -> AP_TO_TOUCH_SPI1_MOSI
|
||||
CFG_FUNC0_SS_X1_PD, // SPI1_MISO -> TOUCH_TO_AP_SPI1_MISO
|
||||
CFG_FUNC0_SS_X4_PU, // SPI1_SSIN -> AP_TO_TOUCH_SPI1_CS_L
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED_SS_X1_PU, // SPI0_SCLK -> N/C -> SPI0_SCLK/BOARD_ID[0]
|
||||
CFG_DISABLED_SS_X1_PU, // SPI0_MOSI -> N/C -> SPI0_MOSI/BOARD_ID[1]
|
||||
CFG_DISABLED_SS_X1_PU, // SPI0_MISO -> N/C -> SPI0_MISO/BOARD_ID[2]
|
||||
CFG_DISABLED_SS_X1_PD, // SPI0_SSIN -> LCM_TO_AP_PIFA
|
||||
CFG_FUNC0_SS_X2, // SPI2_SCLK -> AP_TO_NAVAJO_SPI2_CLK
|
||||
CFG_FUNC0_SS_X2, // SPI2_MOSI -> AP_TO_NAVAJO_SPI2_MOSI
|
||||
CFG_FUNC0_SS_X2_PD, // SPI2_MISO -> NAVAJO_TO_AP_SPI2_MISO
|
||||
CFG_FUNC0_SS_X2, // SPI2_SSIN -> NAVAJO_TO_PMU_INT_H
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0_SS_X4, // I2C0_SDA -> AP_BI_I2C0_SDA
|
||||
CFG_FUNC0_SS_X4, // I2C0_SCL -> AP_TO_I2C0_SDA
|
||||
CFG_FUNC0_SS_X4, // I2C1_SDA -> AP_BI_I2C1_SDA
|
||||
CFG_FUNC0_SS_X4, // I2C1_SCL -> AP_TO_ISC1_SCL
|
||||
CFG_FUNC0_SS_X4, // ISP0_SDA -> AP_BI_RCAM_I2C_SDA
|
||||
CFG_FUNC0_SS_X4, // ISP0_SCL -> AP_TO_RCAM_I2C_SCL
|
||||
CFG_FUNC0_SS_X4, // ISP1_SDA -> AP_TO_FCAM_I2C_SCL
|
||||
CFG_FUNC0_SS_X4, // ISP1_SCL -> AP_TO_FCAM_I2C_SCL
|
||||
|
||||
/* Port 11 */
|
||||
CFG_OUT_0_SS_X4_PD, // SENSOR0_RST -> AP_TO_RCAM_SHUTDOWN
|
||||
CFG_DISABLED_SS_X4_PD, // SENSOR0_CLK -> 45_AP_TO_RCAM_CLK_R
|
||||
CFG_IN_SS_X1_PU, // SENSOR0_XSHUTDOWN -> FCAM_TO_AP_ALS_INT_L
|
||||
CFG_DISABLED_SS_X1_PD, // SENSOR0_ISTRB -> BB_TO_AP_IPC_GPIO
|
||||
CFG_OUT_0_SS_X4_PD, // SENSOR1_RST -> AP_TO_FCAM_SHUTDOWN
|
||||
CFG_DISABLED_SS_X4_PD, // SENSOR1_CLK -> 45_AP_TO_FCAM_CLK_R
|
||||
CFG_DISABLED_SS_X1_PD, // SENSOR1_XSHUTDOWN -> N/C
|
||||
CFG_OUT_0_SS_X4_PD, // SENSOR1_ISTRB -> AP_TO_LEDDRV_EN
|
||||
|
||||
/* Port 12 */
|
||||
CFG_FUNC0_SS_X4_PD, // SPI3_MOSI -> AP_TO_CODEC_SPI3_MOSI
|
||||
CFG_FUNC0_SS_X1_PD, // SPI3_MISO -> CODEC_TO_AP_SPI3_MISO
|
||||
CFG_FUNC0_SS_X4_PD, // SPI3_SCLK -> AP_TO_CODEC_SPI3_CLK
|
||||
CFG_FUNC0_SS_X4_PD, // SPI3_SSIN -> AP_TO_CODEC_SPI3_CS_L
|
||||
CFG_DISABLED_SS_X1_PD, // I2C2_SDA -> N/C
|
||||
CFG_DISABLED_SS_X1_PD, // I2C2_SCL -> N/C
|
||||
CFG_DISABLED_SS_X4_PD, // GPIO22 -> AP_TO_PMU_KEEPACT
|
||||
CFG_DISABLED_SS_X1_PD, // GPIO23 -> LCM_TO_AP_HIFA_BSYNC
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED_SS_X1_PD, // GPIO24 -> BB_TO_AP_RESET_DET_L
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO25 -> BOARD_INFO -> BOOT_CONFIG[1]
|
||||
CFG_DISABLED_SS_X1_PD, // GPIO26 -> FORCE_DFU
|
||||
CFG_DISABLED_SS_X1_PD, // GPIO27 -> DFU_STATUS
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO28 -> N/C -> BOOT_CONFIG[2]
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO29 -> N/C -> BOOT_CONFIG[3]
|
||||
CFG_DISABLED, // GPIO30 -> NULL
|
||||
CFG_IN_SS_X4, // GPIO31 -> AP_TO_RADIO_ON_L
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED_SS_X4, // GPIO32 -> AP_TO_BB_JTAG_TCK
|
||||
CFG_DISABLED_SS_X4, // GPIO33 -> AP_TO_BB_JTAG_TMS
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO34 -> BOARD_INFO -> BOARD_REV3
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO35 -> BOARD_INFO -> BOARD_REV2
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO36 -> BOARD_INFO -> BOARD_REV1
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO37 -> BOARD_INFO -> BOARD_REV0
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO38 -> AP_TO_NAVAJO_DAISY_CHAIN
|
||||
CFG_DISABLED_SS_X1_PD, // DISPLAY_SYNC -> N/C
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED_SS_X1_PU, // SOCHOT0 -> BB_TO_AP_SOCHOT0
|
||||
CFG_FUNC0_SS_X4, // SOCHOT1 -> AP_TO_PMU_SOCHOT1
|
||||
CFG_FUNC0_SS_X4_PU, // UART0_TXD -> AP_TO_TRISTAR_DEBUG_UART0_TXD
|
||||
CFG_FUNC0_SS_X1_PU, // UART0_RXD -> TRISTAR_TO_AP_DEBUG_UART0_RXD
|
||||
CFG_DISABLED_SS_X1_PD, // DWI_DI -> N/C
|
||||
CFG_FUNC0_SS_X4_PD, // DWI_D0 -> 45_AP_TO_PMU_DWI_DO
|
||||
CFG_FUNC0_SS_X4_PD, // DWI_CLK -> 45_AP_TO_PMU_DWI_CLK
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0_SS_X4_PD, // I2S0_LRCK -> AP_TO_CODEC_ASP_I2S0_LRCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S0_BCLK -> 45_AP_TO_CODEC_ASP_I2S0_BCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S0_DOUT -> AP_TO_CODEC_ASP_I2S0_DOUT
|
||||
CFG_FUNC0_SS_X1_PD, // I2S0_DIN -> CODEC_TO_AP_ASP_I2S0_DIN
|
||||
CFG_DISABLED_SS_X4, // I2S1_MCK -> AP_TO_BB_JTAG_TRST_L
|
||||
CFG_FUNC0_SS_X4_PD, // I2S1_LRCK -> AP_TO_BB_I2S1_LRCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S1_BCLK -> 45_AP_TO_BB_I2S1_BCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S1_DOUT -> AP_TO_BB_I2S1_DOUT
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0_SS_X1_PD, // I2S1_DIN -> BB_TO_AP_I2S1_DIN
|
||||
CFG_FUNC0_SS_X4_PD, // I2S2_LRCK -> AP_TO_CODEC_XSP_I2S2_LRCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S2_BCLK -> 45_AP_TO_CODEC_XSP_I2S2_BCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S2_DOUT -> AP_TO_CODEC_XSP_I2S2_DOUT
|
||||
CFG_FUNC0_SS_X1_PD, // I2S2_DIN -> CODEC_TO_AP_XSP_I2S2_DIN
|
||||
CFG_IN_SS_X1_PU, // I2S3_MCK -> ALS_TO_AP_INT_L
|
||||
CFG_FUNC0_SS_X4_PD, // I2S3_LRCK -> AP_TO_BT_I2S3_LRCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S3_BCLK -> 45_AP_TO_BT_I2S3_BCLK
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0_SS_X4_PD, // I2S3_DOUT -> AP_TO_BT_I2S3_DOUT
|
||||
CFG_FUNC0_SS_X1_PD, // I2S3_DIN -> BT_TO_AP_I2S3_DIN
|
||||
CFG_IN_SS_X1_PD, // I2S4_MCK -> TRISTAR_TO_AP_INT
|
||||
CFG_FUNC0_SS_X4_PD, // I2S4_LRCK -> AP_TO_CODEC_VSP_I2S4_LRCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S4_BCLK -> 45_AP_TO_CODEC_VSP_I2S4_BCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S4_DOUT -> AP_TO_CODEC_VSP_I2S4_DOUT
|
||||
CFG_FUNC0_SS_X1_PD, // I2S4_DIN -> CODEC_TO_AP_VSP_I2S4_DIN
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0_SS_X4_PD, // TMR32_PWM0 -> OSCAR_BI_AP_TIME_SYNC_HOST_INT
|
||||
CFG_DISABLED_SS_X4_PD, // TMR32_PWM1 -> AP_TO_PMU_VIBE_PWM_EN
|
||||
CFG_FUNC0_SS_X4, // TMR32_PWM2 -> 45_AP_TO_TOUCH_CLK32K_RESET_L
|
||||
CFG_OUT_0_SS_X4, // SIO_7816UART0_SDA -> AP_TO_BB_HSIC1_RDY
|
||||
CFG_DISABLED_SS_X1_PD, // SIO_7816UART0_SCL -> BB_TO_AP_HSIC1_RDY
|
||||
CFG_DISABLED_SS_X1_PD, // SIO_7816UART0_RST -> BB_TO_AP_HSIC1_REMOTE_WAKE
|
||||
CFG_OUT_0_SS_X4, // SIO_7816UART1_SDA -> AP_TO_WLAN_HSIC2_RDY
|
||||
CFG_IN_SS_X1_PD, // SIO_7816UART1_SCL -> WLAN_TO_AP_HSIC2_RDY
|
||||
|
||||
/* Port 21 */
|
||||
CFG_IN_SS_X1_PD, // SIO_7816UART0_RST -> WLAN_TO_AP_HSIC2_REMOTE_WAKE
|
||||
CFG_FUNC0_SS_X4_PU, // UART6_TXD -> AP_TO_TRISTAR_ACC_UART6_TXD
|
||||
CFG_FUNC0_SS_X1_PU, // UART6_RXD -> TRISTAR_TO_AP_ACC_UART6_RXD
|
||||
CFG_DISABLED_SS_X4_PD, // I2C3_SDA -> AP_BI_OSCAR_SWDIO_1V8
|
||||
CFG_DISABLED_SS_X4_PD, // I2C3_SCL -> AP_TO_OSCAR_SWDCLK_1V8
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED_SS_X1_PD, // EPD_HPD -> N/C
|
||||
CFG_FUNC0_SS_X4_PD, // I2S0_MCK -> 45_AP_TO_CODEC_I2S_MCLK_R
|
||||
CFG_FUNC0_SS_X4_PD, // I2S2_MCK -> 45_AP_TO_SPKAMP_I2S2_MCLK_R
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
return gpio_default_cfg;
|
||||
}
|
||||
@@ -0,0 +1,40 @@
|
||||
# Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2045=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_MED \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=0 \
|
||||
TARGET_VID0_CLK_CFG=0x86100000 \
|
||||
DISPLAY_IPHONE_TUNABLES=1 \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
TARGET_DSIM_CONFIG=0x00400000 \
|
||||
TARGET_DSIM_DPHYCTL=0x30 \
|
||||
TARGET_DSIM_UP_CODE=0x1 \
|
||||
TARGET_DSIM_DOWN_CODE=0x1 \
|
||||
TARGET_DSIM_SUPPRESS=0x1 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_GPU=1 \
|
||||
WITH_CPU_APSC=1
|
||||
|
||||
# this board may have no PMU installed, so AMP should not panic because of that
|
||||
OPTIONS += \
|
||||
AMP_NO_PMU_PANIC=1
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_ADBE_SETTINGS_H
|
||||
#define __TARGET_ADBE_SETTINGS_H
|
||||
|
||||
static struct adbe_v1_tuneable adbe_tuneables[] = {
|
||||
{
|
||||
.name = "default",
|
||||
.adbe0_vblank_pos_vbi_pulse = 0x0000,
|
||||
.adbe0_vblank_clk_gate_wakeup = 0x0000,
|
||||
.adbe0_vblank_clk_gate_idle = 0x0001,
|
||||
.adbe0_vblank_blk_idle_dpb = 0x0000,
|
||||
.adbe0_vblank_blk_idle_aap = 0x0000,
|
||||
.adbe0_tunable_mode_ctrl = (DBEMODECNTL_DYN_CLK_GATE_ENABLE | DBEMODECNTL_AFC_TEARDOWN_ENABLE | DBEMODECNTL_PMGR_CLK_GATE_ENABL| DBEMODECNTL_BLK_CLK_GATE_ENABLE),
|
||||
.adbe0_aap_support = 1,
|
||||
},
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,106 @@
|
||||
/*
|
||||
* Copyright (C) 2011-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
static const struct amc_param amc_params = {
|
||||
.flags = (FLAG_AMC_PARAM_BUSTAT23 | FLAG_AMC_PARAM_SLOW_BOOT | FLAG_AMC_PARAM_ZQCL),
|
||||
|
||||
.tREFi = 0x5d,
|
||||
.longsrcnt = 0x2008,
|
||||
.srextrarefcnt = 0x00020000,
|
||||
.rdlat = 6,
|
||||
.wrlat = 3,
|
||||
.phyrdlat = 10,
|
||||
.phywrlat = 2,
|
||||
.pdn = 0x22000403,
|
||||
.read = 0x00000203,
|
||||
.bustat = 0x00222209,
|
||||
.bustat2 = 0x00222209,
|
||||
.derate = 0x2483135b,
|
||||
.mcphyupdate = 0x05030000,
|
||||
.autoref_params = 0x00000021,
|
||||
.pwrmngtparam_small = 0x00011000,
|
||||
.pwrmngtparam_guided = 0x01801000,
|
||||
.chnldec = 0x00050000,
|
||||
.aref_freq0 = 0x00000110,
|
||||
.schen_default = 0x00000110,
|
||||
.mr1 = 0x44,
|
||||
.mr2 = 0x1a,
|
||||
.mr3 = 0x01,
|
||||
.pwrmngten_default = 0x00100100,
|
||||
.mcphyupdate1 = 0x00000001,
|
||||
.odts = 0x190,
|
||||
.readleveling = 0x00000300,
|
||||
.offset_shift_hynix = 0,
|
||||
.offset_shift_elpida = 1,
|
||||
|
||||
.freq = {
|
||||
{ // 800MHz
|
||||
.cas = 0x00000308,
|
||||
.pch = 0x00030612,
|
||||
.act = 0x12040908,
|
||||
.autoref = 0x19350000,
|
||||
.selfref = 0x00039060,
|
||||
.modereg = 0x20250782,
|
||||
.mifcassch = 0x00000110,
|
||||
.arefparam = 0x0c022131,
|
||||
},
|
||||
{ // 400MHz
|
||||
.cas = 0x00000005,
|
||||
.pch = 0x00000009,
|
||||
.act = 0x09020505,
|
||||
.autoref = 0x0d1b0000,
|
||||
.selfref = 0x0001d000,
|
||||
.modereg = 0x00130000,
|
||||
.mifcassch = 0x00000000,
|
||||
.arefparam = 0x00000101,
|
||||
},
|
||||
{ // 200MHz
|
||||
.cas = 0x00000003,
|
||||
.pch = 0x00000005,
|
||||
.act = 0x08020303,
|
||||
.autoref = 0x070e0000,
|
||||
.selfref = 0x0000f000,
|
||||
.modereg = 0x000a0000,
|
||||
.mifcassch = 0x00000000,
|
||||
.arefparam = 0x00000101,
|
||||
},
|
||||
{ // 50MHz
|
||||
.cas = 0x00000003,
|
||||
.pch = 0x00000003,
|
||||
.act = 0x08020303,
|
||||
.autoref = 0x02040000,
|
||||
.selfref = 0x00004000,
|
||||
.modereg = 0x00030000,
|
||||
.mifcassch = 0x00000000,
|
||||
.arefparam = 0x00000101,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static const struct amc_tunable amc_tunables[] = {
|
||||
{ &rAMC_MCSARBCFG, 0x00000001 },
|
||||
{ &rAMC_OPIDLETMR, 0x00200000 },
|
||||
{ &rAMC_OPTMRADJPARAM, 0x20400064 },
|
||||
{ &rAMC_MIFACTSCH, 0x00000001 },
|
||||
{ &rAMC_MIFCASSCH_FREQ(0), 0x10000010 },
|
||||
{ &rAMC_PSQRQCTL0, 0xff010110 },
|
||||
{ &rAMC_PSQRQCTL1, 0x00001728 },
|
||||
{ &rAMC_PSQRQTIMER0, 0x00000040 },
|
||||
{ &rAMC_PSQRQTIMER1, 0x00000014 },
|
||||
{ &rAMC_PSQRQTIMER2, 0x00000040 },
|
||||
{ &rAMC_PSQRQBRST, 0x04100410 },
|
||||
{ &rAMC_PSQRQSCHCRD, 0x00101400 },
|
||||
{ &rAMC_PSQWQCTL0, 0x00010100 },
|
||||
{ &rAMC_PSQWQBRST, 0x04100410 },
|
||||
{ &rAMC_PSQWQSCHCRD, 0x00101400 },
|
||||
{ &rAMC_MCUQOS, 0x00001919 },
|
||||
{ &rAMC_MCUQOSLLT, 0x0000011f },
|
||||
};
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_ASPNANDCONFIG_H
|
||||
#define __TARGET_ASPNANDCONFIG_H
|
||||
|
||||
//MLC devices
|
||||
#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_ERASE_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_READ_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
|
||||
//TLC devices
|
||||
#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
|
||||
// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
|
||||
#define ASPNAND_INDIRECTION_MEMORY (2*1024*1024)
|
||||
#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_GPIODEF_H
|
||||
#define __TARGET_GPIODEF_H
|
||||
|
||||
/* iPad4,x specific gpio -> pin mappings */
|
||||
|
||||
#include <platform/gpio.h>
|
||||
|
||||
/* define target-specific gpios in a generic fashion here. */
|
||||
#define GPIO_LCD_PWR_EN GPIO( 2, 7)
|
||||
|
||||
#define GPIO_RINGER_AB GPIO(13, 6)
|
||||
|
||||
/* Board Revision */
|
||||
#define GPIO_BOARD_REV0 GPIO(14, 6)
|
||||
#define GPIO_BOARD_REV1 GPIO(14, 5)
|
||||
#define GPIO_BOARD_REV2 GPIO(14, 4)
|
||||
#define GPIO_BOARD_REV3 GPIO(14, 3)
|
||||
|
||||
/* which IICs to initialize */
|
||||
#define IICS_MASK (0x5)
|
||||
|
||||
#define TRISTAR_IIC_BUS (0)
|
||||
|
||||
/* D2089 watchdog tickle, 'KEEPACT' */
|
||||
#define GPIO_WDOG_TICKLE GPIO(12, 6)
|
||||
|
||||
#endif /* ! __TARGET_GPIODEF_H */
|
||||
@@ -0,0 +1,90 @@
|
||||
#ifndef __TARGET_POWERCONFIG_H
|
||||
#define __TARGET_POWERCONFIG_H
|
||||
|
||||
/* configuration per target */
|
||||
|
||||
#define PMU_IIC_BUS 0
|
||||
|
||||
/* this configuration is very PMU specific and must be included exactly once in power.c */
|
||||
#ifdef POWERCONFIG_PMU_SETUP
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
|
||||
{
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kD2045_ACTIVE3, 0xAE }, // Current OTP enables LDO{1,2,3,4,5,7}, disable LDO4.
|
||||
{ PMU_IIC_BUS, kD2045_ACTIVE6, 0x37 }, // enable BUCK3_SW1, BUCK3_SW2, BUCK3_SW3, BUCK4_SW1, BUCK4_SW2
|
||||
{ PMU_IIC_BUS, kD2045_ACTIVE3, 0xBE }, // enable LDO4 along with LDO{1,2,3,5,7}
|
||||
|
||||
{ PMU_IIC_BUS, kD2045_HIBERNATE1, 0x18 },
|
||||
{ PMU_IIC_BUS, kD2045_HIBERNATE3, 0x18 },
|
||||
{ PMU_IIC_BUS, kD2045_HIBERNATE6, 0x24 },
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_warm_init[] =
|
||||
{
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_cold_init[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kD2045_GPIO1, 0xBB }, // AUD_ARRAY_HOST_WAKE In, R Edge, No PU, Wake, PD
|
||||
{ PMU_IIC_BUS, kD2045_GPIO2, 0xBB }, // WLAN2_HOST_WAKE IN, R Edge, No PU, Wake, PD
|
||||
{ PMU_IIC_BUS, kD2045_GPIO3, 0x0B }, // WLAN2_REG_ON Out 1, Buck 3, push-pull
|
||||
{ PMU_IIC_BUS, kD2045_GPIO4, 0xB9 }, // TRI_INT In, R Edge, No PU, no wake, PD
|
||||
{ PMU_IIC_BUS, kD2045_GPIO5, 0x09 }, // BT1_REG_ON
|
||||
{ PMU_IIC_BUS, kD2045_GPIO6, 0xBB }, // BT1_HOST_WAKE In, R Edge, No PU, wake, PD
|
||||
{ PMU_IIC_BUS, kD2045_GPIO7, 0xBB }, // WLAN1_HOST_WAKE In, R Edge, No PU, wake, PD
|
||||
{ PMU_IIC_BUS, kD2045_GPIO8, 0xBB }, // ENET_PHY_HOST_WAKE In, R Edge, No PU, wake, PD
|
||||
{ PMU_IIC_BUS, kD2045_GPIO9, 0x09 }, // BT2_REG_ON Out 0, Push-Pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD2045_GPIO10, 0xBB }, // BT2_HOST_WAKE In, R Edge, No PU, wake, PD
|
||||
{ PMU_IIC_BUS, kD2045_GPIO11, 0x0B }, // WLAN1_REG_ON Out 1, Push-Pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD2045_GPIO12, 0xBB }, // ENET_PME_1V8 In, R Edge, No PU, wake, PD
|
||||
{ PMU_IIC_BUS, kD2045_GPIO13, 0xBB }, // MCU_HOST_WAKE In, R Edge, No PU, wake, PD
|
||||
{ PMU_IIC_BUS, kD2045_GPIO14, 0x0B }, // PS_ON (16V) Out 1, VBUCK3, open drain
|
||||
{ PMU_IIC_BUS, kD2045_GPIO15, 0x7A }, // PMU_WAKE_ON_VCC
|
||||
{ PMU_IIC_BUS, kD2045_GPIO16, 0xBB }, // ACCEL_HOST_WAKE1 In, R Edge, No PU, wake, PD
|
||||
{ PMU_IIC_BUS, kD2045_OUT_32K, 0x49 }, // OUT_32K (WLAN_CLK32K) Out 32K, Push-Pull, VBUCK3
|
||||
|
||||
{ PMU_IIC_BUS, kD2045_BUCK_DWI_CTRL0, 0x03 }, // enable DWI for BUCK0, BUCK1
|
||||
|
||||
{ PMU_IIC_BUS, kD2045_BUTTON1_CONF, 0x84 }, // PMU_BUTTTON1
|
||||
{ PMU_IIC_BUS, kD2045_BUTTON2_CONF, 0x84 }, // PMU_BUTTTON2
|
||||
{ PMU_IIC_BUS, kD2045_BUTTON3_CONF, 0xD4 }, // PMU_BUTTTON3
|
||||
{ PMU_IIC_BUS, kD2045_BUTTON4_CONF, 0x94 }, // PMU_BUTTTON4
|
||||
|
||||
// Special function
|
||||
{ PMU_IIC_BUS, kDIALOG_BUTTON_DBL, 0x00 }, //
|
||||
{ PMU_IIC_BUS, kD2045_BUTTON_WAKE, 0x00 }, // AUD_ARRAY_HOST_WAKE
|
||||
{ PMU_IIC_BUS, kD2045_RESET_IN1_CONF,0x02}, // PMU_RESET_IN1_WDOG
|
||||
{ PMU_IIC_BUS, kD2045_RESET_IN2_CONF,0x00}, // PMU_RESET_IN2_TRISTAR
|
||||
{ PMU_IIC_BUS, kD2045_RESET_IN3_CONF,0x14}, // SOCHOT1_L
|
||||
|
||||
};
|
||||
|
||||
static const struct core_rails_struct soc_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2045_BUCK2_VSEL }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct cpu_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2045_BUCK0_VSEL }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct ram_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2045_BUCK5_VSEL }
|
||||
};
|
||||
|
||||
#endif /* POWERCONFIG_PMU_SETUP */
|
||||
|
||||
#define TARGET_POWER_NO_BATTERY 1
|
||||
#define ALWAYS_BOOT_BATTERY_VOLTAGE (3000)
|
||||
#define PRECHARGE_BACKLIGHT_LEVEL 103
|
||||
#define TARGET_MAX_USB_INPUT_CURRENT 2400
|
||||
|
||||
#define ACC_PWR_LDO (6)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define one debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (0)
|
||||
|
||||
#define HDQGAUGE_SERIAL_PORT (5)
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define UART_OVERSAMPLE_OVERRIDE (11)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_USBCONFIG_H
|
||||
#define __TARGET_USBCONFIG_H
|
||||
|
||||
#ifdef USBPHY_OTGTUNE0
|
||||
|
||||
#undef USBPHY_OTGTUNE0
|
||||
#define USBPHY_OTGTUNE0 (0x3644D3F3)
|
||||
|
||||
#endif /* USBPHY_OTGTUNE0 */
|
||||
|
||||
#endif /* __TARGET_USBCONFIG_H */
|
||||
@@ -0,0 +1,232 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/flash_nor.h>
|
||||
#include <drivers/iic.h>
|
||||
#include <drivers/power.h>
|
||||
#include <lib/devicetree.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <lib/syscfg.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <sys.h>
|
||||
#include <sys/boot.h>
|
||||
#include <sys/menu.h>
|
||||
#include <sys/task.h>
|
||||
#include <target.h>
|
||||
|
||||
static bool gpio_board_rev_valid;
|
||||
static u_int32_t gpio_board_rev;
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
|
||||
static u_int32_t b184_get_board_rev(void)
|
||||
{
|
||||
|
||||
if (!gpio_board_rev_valid) {
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV3, GPIO_PUP);
|
||||
|
||||
spin(100); // Wait 100us
|
||||
|
||||
gpio_board_rev =
|
||||
(gpio_read(GPIO_BOARD_REV3) << 3) |
|
||||
(gpio_read(GPIO_BOARD_REV2) << 2) |
|
||||
(gpio_read(GPIO_BOARD_REV1) << 1) |
|
||||
(gpio_read(GPIO_BOARD_REV0) << 0);
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_DFLT);
|
||||
|
||||
gpio_board_rev_valid = true;
|
||||
}
|
||||
|
||||
return gpio_board_rev;
|
||||
}
|
||||
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return platform_get_request_dfu2() && power_has_usb();
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
#if WITH_HW_POWER
|
||||
if (power_get_boot_flag() == kPowerBootFlagColdButton) *cold_button_boot = true;
|
||||
#else
|
||||
*cold_button_boot = false;
|
||||
#endif // WITH_HW_POWER
|
||||
|
||||
return !*cold_button_boot || platform_get_request_dfu1();
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
u_int32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
env_set("boot-device", "asp_nand", 0);
|
||||
}
|
||||
|
||||
#endif // WITH_ENV
|
||||
|
||||
bool target_has_tristar2(void)
|
||||
{
|
||||
return true; // TODO: Does it have tristar2?
|
||||
}
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
#if WITH_HW_DISPLAY_EDP
|
||||
DTNode *clcd_node = NULL, *backlight_node = NULL, *lcd_node = NULL;
|
||||
#endif
|
||||
DTNode *node;
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
// Store secondary mac addresses into products node
|
||||
if (FindNode(0, "product", &node)) {
|
||||
propName = "mac-address-wifi1";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (env_get("wifi1addr")) {
|
||||
env_get_ethaddr("wifi1addr", propData);
|
||||
} else {
|
||||
int retlen = 0;
|
||||
if (!target_get_property(TARGET_PROPERTY_WIFI1_MACADDR, propData, 6, &retlen)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
propName = "mac-address-ethernet1";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (env_get("eth1addr")) {
|
||||
env_get_ethaddr("eth1addr", propData);
|
||||
} else {
|
||||
int retlen = 0;
|
||||
if (!target_get_property(TARGET_PROPERTY_ETH1_MACADDR, propData, 6, &retlen)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
propName = "mac-address-bluetooth1";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (env_get("bt1addr")) {
|
||||
env_get_ethaddr("bt1addr", propData);
|
||||
} else {
|
||||
int retlen = 0;
|
||||
if (!target_get_property(TARGET_PROPERTY_BT1_MACADDR, propData, 6, &retlen)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Store second wlan mac address into wlan1 node
|
||||
if (FindNode(0, "arm-io/usb-complex/usb-ehci1/wlan1", &node)) {
|
||||
propName = "local-mac-address";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (env_get("wifi1addr")) {
|
||||
env_get_ethaddr("wifi1addr", propData);
|
||||
} else {
|
||||
int retlen = 0;
|
||||
if (!target_get_property(TARGET_PROPERTY_WIFI1_MACADDR, propData, 6, &retlen)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Add bluetooth, ethernet second mac address when node is available
|
||||
// <rdar://problem/14324725> B184 /12A43 : bluetooth not responding
|
||||
|
||||
// TriStar 1 on older systems
|
||||
if (!target_has_tristar2()) {
|
||||
if (FindNode(0, "arm-io/i2c2/tristar", &node)) {
|
||||
propName = "compatible";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
strlcpy(propData, "tristar,cbtl1608", kPropNameLength);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Update charger calibration data
|
||||
if (FindNode(0, "charger", &node)) {
|
||||
propName = "usb-input-limit-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('CBAT', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif // WITH_DEVICETREE
|
||||
@@ -0,0 +1,271 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* THIS STRUCT IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: version 1.16
|
||||
I/O Spreadsheet tracker: 12739020&15521285
|
||||
*/
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_FUNC0, // 0 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_FUNC0 | FAST_SLEW, // 1 : WDOG -> SOC_WDOG
|
||||
CFG_IN, // 2 : GPIO[0] -> PMU_BUTTON1
|
||||
CFG_IN, // 3 : GPIO[1] -> PMU_BUTTON2
|
||||
CFG_IN, // 4 : GPIO[2] -> PMU_BUTTON3
|
||||
CFG_IN, // 5 : GPIO[3] -> PMU_BUTTON4
|
||||
CFG_IN, // 6 : GPIO[4] -> ACCEL_HOST_WAKE1
|
||||
CFG_IN, // 7 : GPIO[5] -> PS_ON_SOC
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN, // 8 : GPIO[6] -> AUD_ARRAY_HOST_WAKE
|
||||
CFG_IN, // 9 : GPIO[7] -> BT2_BTWAKE
|
||||
CFG_IN, // 10 : GPIO[8] -> ENET_PHY_HOST_WAKE
|
||||
CFG_IN, // 11 : GPIO[9] -> MCU_HOST_WAKE
|
||||
CFG_OUT_0 | PULL_DOWN | SLOW_SLEW, // 12 : GPIO[10] -> SOC_TO_ENET_PME_MODE_SEL
|
||||
CFG_IN, // 13 : GPIO[11] -> SOC_TO_MCU_RESET_L
|
||||
CFG_IN, // 14 : GPIO[12] -> SOC_TO_MCU_BOOTLOAD
|
||||
CFG_IN | PULL_UP, // 15 : GPIO[13] -> PMU_IRQ_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_IN, // 16 : GPIO[14] -> SOC_WLAN_ASTP_SEL
|
||||
CFG_IN, // 17 : GPIO[15] -> ENET_HSIC_DEVICE_READY
|
||||
CFG_IN | PULL_DOWN, // 18 : GPIO[16] -> BOARDID_3
|
||||
CFG_IN, // 19 : GPIO[17] -> TRI_INT
|
||||
CFG_IN | PULL_DOWN, // 20 : GPIO[18] -> BOOTCONFIG_0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 21 : GPIO[19] -> PMU_KEEPACT
|
||||
CFG_DISABLED, // 22 : GPIO[20] -> NC_SPDIF_LOCK_L
|
||||
CFG_DISABLED, // 23 : GPIO[21] -> NC_SPDIF_INT_L
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 32 : UART1_TXD -> SOC_UART1_TO_MCU_TXD
|
||||
CFG_FUNC0, // 33 : UART1_RXD -> MCU_TO_SOC_UART1_RXD
|
||||
CFG_OUT_0, // 34 : UART1_RTSN -> MCU_SWCLK
|
||||
CFG_IN | SLOW_SLEW, // 35 : UART1_CTSN -> MCU_SWDIO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : UART2_TXD -> SOC_UART2_TO_BT_TXD
|
||||
CFG_FUNC0, // 37 : UART2_RXD -> BT_TO_SOC_UART2_RXD
|
||||
CFG_FUNC0, // 38 : UART2_RTSN -> SOC_UART2_TO_BT_RTSB
|
||||
CFG_FUNC0, // 39 : UART2_CTSN -> BT_TO_SOC_UART2_CTSB
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : UART3_TXD -> WLAN1_TO_SOC_UART3_RXD
|
||||
CFG_FUNC0, // 41 : UART3_RXD -> SOC_UART3_TO_WLAN1_TXD
|
||||
CFG_DISABLED, // 42 : UART3_RTSN -> NC_UART3_RTSN
|
||||
CFG_DISABLED, // 43 : UART3_CTSN -> NC_UART3_CTSN
|
||||
CFG_DISABLED, // 44 : UART5_RTXD -> UART5_RTXD
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 64 : UART4_TXD -> SOC_UART4_TO_WLAN2_TXD
|
||||
CFG_FUNC0, // 65 : UART4_RXD -> WLAN2_TO_SOC_UART4_RXD
|
||||
CFG_DISABLED, // 66 : UART4_RTSN -> NC_UART4_RTSN
|
||||
CFG_DISABLED, // 67 : UART4_CTSN -> NC_UART4_CTSN
|
||||
CFG_DISABLED, // 68 : SPI1_SCLK -> NC_SPI1_SCLK
|
||||
CFG_DISABLED, // 69 : SPI1_MOSI -> NC_SPI1_MOSI
|
||||
CFG_DISABLED, // 70 : SPI1_MISO -> NC_SPI1_MISO
|
||||
CFG_DISABLED, // 71 : SPI1_SSIN -> NC_SPI1_SSIN
|
||||
|
||||
/* Port 9 */
|
||||
CFG_IN | PULL_DOWN, // 72 : SPI0_SCLK -> BOARDID_0
|
||||
CFG_IN | PULL_DOWN, // 73 : SPI0_MOSI -> BOARDID_1
|
||||
CFG_IN | PULL_DOWN, // 74 : SPI0_MISO -> BOARDID_2
|
||||
CFG_DISABLED, // 75 : SPI0_SSIN -> NC_SPI0_SSIN
|
||||
CFG_DISABLED, // 76 : SPI2_SCLK -> NC_SPI2_SCLK
|
||||
CFG_DISABLED, // 77 : SPI2_MOSI -> NC_SPI2_MOSI
|
||||
CFG_DISABLED, // 78 : SPI2_MISO -> NC_SPI2_MISO
|
||||
CFG_DISABLED, // 79 : SPI2_SSIN -> NC_SPI2_SSIN
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 80 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 81 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 82 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 83 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 84 : ISP0_SDA -> (NC)
|
||||
CFG_DISABLED, // 85 : ISP0_SCL -> (NC)
|
||||
CFG_DISABLED, // 86 : ISP1_SDA -> (NC)
|
||||
CFG_DISABLED, // 87 : ISP1_SCL -> (NC)
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // 88 : SENSOR0_RST ->
|
||||
CFG_DISABLED, // 89 : SENSOR0_CLK ->
|
||||
CFG_DISABLED, // 90 : SENSOR0_XSHUTDOWN ->
|
||||
CFG_DISABLED, // 91 : SENSOR0_ISTRB ->
|
||||
CFG_DISABLED, // 92 : SENSOR1_RST ->
|
||||
CFG_DISABLED, // 93 : SENSOR1_CLK ->
|
||||
CFG_DISABLED, // 94 : SENSOR1_XSHUTDOWN ->
|
||||
CFG_DISABLED, // 95 : SENSOR1_ISTRB ->
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : SPI3_MOSI -> NC_SPI3_MOSI
|
||||
CFG_DISABLED, // 97 : SPI3_MISO -> NC_SPI3_MISO
|
||||
CFG_DISABLED, // 98 : SPI3_SCLK -> NC_SPI3_SCLK
|
||||
CFG_DISABLED, // 99 : SPI3_SSIN -> NC_SPI3_SSIN
|
||||
CFG_DISABLED, // 100 : I2C2_SDA -> I2C2_SPDIF_SDA_1V8
|
||||
CFG_DISABLED, // 101 : I2C2_SCL -> I2C2_SPDIF_SCL_1V8
|
||||
CFG_DISABLED, // 102 : GPIO[22] -> NC_SPDIF_RESET_L
|
||||
CFG_OUT_0 | PULL_UP | SLOW_SLEW, // 103 : GPIO[23] -> ENET_RESET_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_IN, // 104 : GPIO[24] -> ENET_PME_1V8
|
||||
CFG_IN | PULL_DOWN, // 105 : GPIO[25] -> BOOTCONFIG_1
|
||||
CFG_IN, // 106 : GPIO[26] -> FORCE_DFU
|
||||
CFG_OUT_0 | SLOW_SLEW, // 107 : GPIO[27] -> DFU_STATUS
|
||||
CFG_IN | PULL_DOWN, // 108 : GPIO[28] -> BOOTCONFIG_2
|
||||
CFG_IN | PULL_DOWN, // 109 : GPIO[29] -> BOOTCONFIG_3
|
||||
CFG_IN, // 110 : GPIO[30] -> BT1_BTWAKE
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> SOC_ANALOG_SEL
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : GPIO[32] -> SOC_SPDIF_SEL
|
||||
CFG_DISABLED, // 113 : GPIO[33] -> SOC_ANALOG_PWR_EN
|
||||
CFG_IN | PULL_DOWN, // 114 : GPIO[34] -> BOARDREV_3
|
||||
CFG_IN | PULL_DOWN, // 115 : GPIO[35] -> BOARDREV_2
|
||||
CFG_IN | PULL_DOWN, // 116 : GPIO[36] -> BOARDREV_1
|
||||
CFG_IN | PULL_DOWN, // 117 : GPIO[37] -> BOARDREV_0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 118 : GPIO[38] -> SOC_BT_SEL
|
||||
CFG_DISABLED, // 119 : DISP_VSYNC -> SOC_DISP_VSYNC
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0, // 121 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_FUNC0 | FAST_SLEW, // 122 : UART0_TXD -> UART0_TXD
|
||||
CFG_FUNC0, // 123 : UART0_RXD -> UART0_RXD
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 125 : DWI_DO -> DWI_AP_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 126 : DWI_CLK -> DWI_AP_CLK
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0, // 128 : I2S0_LRCK -> MCA_FSYNC_1V8
|
||||
CFG_FUNC0, // 129 : I2S0_BCLK -> MCA_BCLK_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 130 : I2S0_DOUT -> MCA0_DOUT
|
||||
CFG_FUNC0, // 131 : I2S0_DIN -> MIC_DATA_1V8
|
||||
CFG_DISABLED, // 132 : I2S1_MCK -> I2S0_MCK
|
||||
CFG_FUNC0, // 133 : I2S1_LRCK -> MCA_FSYNC_1V8
|
||||
CFG_FUNC0, // 134 : I2S1_BCLK -> MCA_BCLK_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 135 : I2S1_DOUT -> MCA1_DOUT
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // 136 : I2S1_DIN -> MCA1_DIN
|
||||
CFG_FUNC0, // 137 : I2S2_LRCK -> MCA_FSYNC_1V8
|
||||
CFG_FUNC0, // 138 : I2S2_BCLK -> MCA_BCLK_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 139 : I2S2_DOUT -> MCA2_DOUT
|
||||
CFG_FUNC0, // 140 : I2S2_DIN -> MCU_MISO_1V8
|
||||
CFG_DISABLED, // 141 : I2S3_MCK -> NC_I2S2_MCK
|
||||
CFG_FUNC0, // 142 : I2S3_LRCK -> MCA_FSYNC_1V8
|
||||
CFG_FUNC0, // 143 : I2S3_BCLK -> MCA_BCLK_1V8
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 144 : I2S3_DOUT -> MCA3_DOUT
|
||||
CFG_FUNC0, // 145 : I2S3_DIN -> MCA3_DIN
|
||||
CFG_DISABLED, // 146 : I2S4_MCK -> NC_I2S4_MCK
|
||||
CFG_DISABLED, // 147 : I2S4_LRCK -> NC_I2S4_LRCLK
|
||||
CFG_DISABLED, // 148 : I2S4_BCLK -> NC_I2S4_BCLK
|
||||
CFG_DISABLED, // 149 : I2S4_DOUT -> NC_I2S4_DOUT
|
||||
CFG_DISABLED, // 150 : I2S4_DIN -> NC_I2S4_DIN
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // 160 : TMR32_PWM0 -> NC_TMR32_PWM0
|
||||
CFG_DISABLED, // 161 : TMR32_PWM1 -> NC_TMR32_PWM1
|
||||
CFG_DISABLED, // 162 : TMR32_PWM2 -> NC_TMR32_PWM2
|
||||
CFG_OUT_0 | FAST_SLEW, // 163 : SIO_7816UART0_SDA -> WLAN2_HOST_READY
|
||||
CFG_IN, // 164 : SIO_7816UART0_SCL -> WLAN2_DEVICE_READY
|
||||
CFG_IN, // 165 : SIO_7816UART0_RST -> WLAN2_HSIC_RESUME
|
||||
CFG_OUT_0, // 166 : SIO_7816UART1_SDA -> WLAN1_HOST_READY
|
||||
CFG_IN, // 167 : SIO_7816UART1_SCL -> WLAN1_DEVICE_READY
|
||||
|
||||
/* Port 21 */
|
||||
CFG_IN, // 168 : SIO_7816UART1_RST -> WLAN1_HSIC_RESUME
|
||||
CFG_FUNC0 | FAST_SLEW, // 169 : UART6_TXD -> UART6_TXD
|
||||
CFG_FUNC0, // 170 : UART6_RXD -> UART6_RXD
|
||||
CFG_DISABLED, // 171 : I2C3_SDA -> I2C_ARRAY_SCL_1V8
|
||||
CFG_DISABLED, // 172 : I2C3_SCL -> I2C_ARRAY_SDA_1V8
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED, // 192 : EDP_HPD -> (NC)
|
||||
CFG_DISABLED, // 193 : I2S0_MCK -> I2S0_MCK
|
||||
CFG_DISABLED, // 194 : I2S2_MCK -> NC_I2S2_MCK
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
return gpio_default_cfg;
|
||||
}
|
||||
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <target.h>
|
||||
#include <target/powerconfig.h>
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
bool
|
||||
target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
|
||||
{
|
||||
int length = 0;
|
||||
bool result = false;
|
||||
|
||||
if ((result = target_get_property_base(prop, data, maxdata, retlen)) == false) {
|
||||
switch(prop) {
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (retlen != NULL) *retlen = length;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,45 @@
|
||||
# Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2045=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_MED \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=0 \
|
||||
TARGET_HAS_BASEBAND=$(TARGET_HAS_BASEBAND) \
|
||||
TARGET_SPARE0_CLK_CFG=0x83000006 \
|
||||
TARGET_VID0_CLK_CFG=0x81000000 \
|
||||
TARGET_DDR_798M=1 \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
WITH_TARGET_AMC_PARAMS=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_GPU=1 \
|
||||
WITH_CPU_APSC=1 \
|
||||
BT_DTPATH=\"arm-io/uart1/bluetooth\" \
|
||||
WIFI_DTPATH=\"arm-io/usb-complex/usb-ehci0/wlan0\" \
|
||||
WITH_TARGET_USB_CONFIG=1 \
|
||||
ETHERNET_DTPATH=\"arm-io/usb-complex/usb-ehci0/lan0\"
|
||||
|
||||
# TODO: Wifi and BT config are almost certainly wrong here.
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
|
||||
ifneq ($(PRODUCT),LLB)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/properties.o
|
||||
endif
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_ASPNANDCONFIG_H
|
||||
#define __TARGET_ASPNANDCONFIG_H
|
||||
|
||||
//MLC devices
|
||||
#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_ERASE_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_READ_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
|
||||
//TLC devices
|
||||
#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
|
||||
// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
|
||||
#define ASPNAND_INDIRECTION_MEMORY (4*1024*1024)
|
||||
#define ASPNAND_LEGACY_INDIRECTION_MEMORY ASPNAND_INDIRECTION_MEMORY
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_GPIODEF_H
|
||||
#define __TARGET_GPIODEF_H
|
||||
|
||||
/* B238 specific gpio -> pin mappings */
|
||||
|
||||
#include <platform/gpio.h>
|
||||
|
||||
/* define target-specific gpios in a generic fashion here. */
|
||||
|
||||
#define GPIO_BOARD_REV0 GPIO( 9, 2) // 74 : GPIO[34]
|
||||
#define GPIO_BOARD_REV1 GPIO( 9, 1) // 73 : GPIO[35]
|
||||
#define GPIO_BOARD_REV2 GPIO( 9, 0) // 72 : GPIO[36]
|
||||
#define GPIO_BOARD_REV3 GPIO( 8, 7) // 71 : GPIO[37]
|
||||
|
||||
/* D2186 watchdog tickle, 'KEEPACT' */
|
||||
#define GPIO_WDOG_TICKLE GPIO(13, 3) // 107 : GPIO[19] -> AP_TO_PMU_KEEPACT
|
||||
|
||||
/* which IICs to initialize */
|
||||
// for t7000/fiji IICS_COUNT is 4.
|
||||
// if IICS_MASK is not defined it is set to 0xF
|
||||
// iic0 - ADI PMU
|
||||
// iic1 - Accel
|
||||
// iic2 - Mic Codec
|
||||
// iic3 - Nitrogen
|
||||
#define IICS_MASK (0xF)
|
||||
|
||||
#endif /* ! __TARGET_GPIODEF_H */
|
||||
@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_POWERCONFIG_H
|
||||
#define __TARGET_POWERCONFIG_H
|
||||
|
||||
/* configuration per target */
|
||||
|
||||
#define PMU_IIC_BUS 0
|
||||
|
||||
|
||||
/* this configuration is very PMU specific and must be included exactly once in power.c */
|
||||
#ifdef POWERCONFIG_PMU_SETUP
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
|
||||
{
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
|
||||
{
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_warm_init[] =
|
||||
{
|
||||
};
|
||||
|
||||
// XXX: review setup for each GPIO and add back decoded description of each config
|
||||
// rdar://problem/19654165 B238: IO Spreadsheet Tracker
|
||||
|
||||
static const struct pmu_setup_struct pmu_cold_init[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kD2186_BUCK_DWI_CTRL0, 0x07 }, // <rdar://problem/20401454> B238: Multiple panics when entering single user mode - need to enable DWI comm between PMU and bucks
|
||||
{ PMU_IIC_BUS, kD2186_GPIO9_CONF1, 0x93 }, // <rdar://problem/21039044> B238: GPIO17 wake on rising edge
|
||||
};
|
||||
|
||||
|
||||
static const struct core_rails_struct cpu_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2186_BUCK0_VSEL }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct ram_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2186_BUCK5_VSEL }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct soc_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2186_BUCK2_VSEL }
|
||||
};
|
||||
|
||||
#endif /* POWERCONFIG_PMU_SETUP */
|
||||
|
||||
#define TARGET_POWER_NO_BATTERY 1
|
||||
//#define TARGET_POWER_USB_MASK STATUS_FLAG_MAKE(0, kD1815_STATUS_A_VBUS_EXT)
|
||||
#define ALWAYS_BOOT_BATTERY_VOLTAGE (3000)
|
||||
#define PRECHARGE_BACKLIGHT_LEVEL 103
|
||||
|
||||
#define ACC_PWR_LDO (6)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (C) 2009 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define one debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (0)
|
||||
|
||||
#define UART_FLOWCONTROL_MASK (0x08)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,182 @@
|
||||
/*
|
||||
* Copyright (C) 2009-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
//#include <drivers/flash_nor.h>
|
||||
//#include <drivers/iic.h>
|
||||
#include <drivers/power.h>
|
||||
//#include <drivers/mcu.h>
|
||||
//#include <lib/devicetree.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <lib/syscfg.h>
|
||||
#include <platform.h>
|
||||
//#include <platform/gpio.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <sys.h>
|
||||
#include <sys/boot.h>
|
||||
#include <sys/menu.h>
|
||||
#include <sys/task.h>
|
||||
#include <target.h>
|
||||
//#include <target/powerconfig.h>
|
||||
|
||||
// Do not delay iBoot by more than this amount from power on (microseconds).
|
||||
// Give up waiting for a boot logo and carry on at this point.
|
||||
#define kDPDeviceStartTimeout (8 * 1000 * 1000)
|
||||
|
||||
static u_int32_t b238_get_board_rev(void);
|
||||
extern utime_t gPowerOnTime;
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 1);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
#if PRODUCT_LLB || PRODUCT_IBSS
|
||||
// dprintf(DEBUG_INFO, "%s: chip rev: %d, fuse: %d\n", __func__,
|
||||
// chipid_get_chip_revision(), chipid_get_fuse_revision());
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
dprintf(DEBUG_INFO, "%s ...\n", __func__);
|
||||
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
int target_debug_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
switch (target) {
|
||||
case BOOT_DARWIN:
|
||||
case BOOT_DIAGS:
|
||||
break;
|
||||
case BOOT_DARWIN_RESTORE:
|
||||
break;
|
||||
default:
|
||||
// do nothing
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
// trigger recovery mode whenever USB is attached, unless
|
||||
// environment variable says otherwise.
|
||||
|
||||
return power_has_usb() && !env_get_bool("auto-boot-usb", true);
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
// always powers on
|
||||
return true;
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
// never power off
|
||||
return false;
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
// u_int32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
// gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
env_set("boot-device", "asp_nand", 0);
|
||||
env_set("idle-off", "false", 0); // do not idle off; there is no battery and this will just reboot (8035422)
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
#if 0
|
||||
DTNode *node;
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
// Update the pmu node with the actual vcore values
|
||||
if (FindNode(0, "arm-io/i2c0/pmu", &node)) {
|
||||
propName = "swi-vcores";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
platform_get_soc_voltages(propSize / sizeof(u_int32_t), propData);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
static u_int32_t b238_get_board_rev(void)
|
||||
{
|
||||
u_int32_t gpio_board_rev=0;
|
||||
|
||||
#if 0
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV3, GPIO_PDN);
|
||||
|
||||
spin(100); // Wait 100us
|
||||
|
||||
gpio_board_rev =
|
||||
(gpio_read(GPIO_BOARD_REV3) << 3) |
|
||||
(gpio_read(GPIO_BOARD_REV2) << 2) |
|
||||
(gpio_read(GPIO_BOARD_REV1) << 1) |
|
||||
(gpio_read(GPIO_BOARD_REV0) << 0);
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_DFLT);
|
||||
#endif
|
||||
return (gpio_board_rev &0xF);
|
||||
}
|
||||
@@ -0,0 +1,580 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: rev 1v1
|
||||
I/O Spreadsheet tracker: <rdar://problem/19579177>
|
||||
Conversion command: ./tools/csvtopinconfig.py --soc fiji --copyright 2015 --config-column Dir --radar '<rdar://problem/19579177>' <filename>
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
|
||||
static const uint32_t pinconfig_ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 0 : ULPI_DIR -> LAN_PME_MODE_1V8
|
||||
CFG_DISABLED | SLOW_SLEW, // 1 : ULPI_STP ->
|
||||
CFG_OUT_0 | SLOW_SLEW, // 2 : ULPI_NXT -> LAN_RESET_1V8_L
|
||||
CFG_DISABLED | SLOW_SLEW, // 3 : ULPI_DATA[7] ->
|
||||
CFG_IN | SLOW_SLEW, // 4 : ULPI_DATA[6] -> LAN_PHY_IRQ_1V8
|
||||
CFG_IN | SLOW_SLEW, // 5 : ULPI_DATA[5] -> LAN_PME_1V8
|
||||
CFG_IN | SLOW_SLEW, // 6 : ULPI_DATA[4] -> LAN_HSIC_DEV_RDY
|
||||
CFG_DISABLED | SLOW_SLEW, // 7 : ULPI_CLK ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 8 : ULPI_DATA[3] -> SOC2WLB_DEVICE_WAKE_R
|
||||
CFG_OUT_0 | SLOW_SLEW, // 9 : ULPI_DATA[2] -> SOC2WLB_THROTTLE_R
|
||||
CFG_IN | SLOW_SLEW, // 10 : ULPI_DATA[1] -> WLB2PMU_HOST_WAKE_R
|
||||
CFG_OUT_0 | SLOW_SLEW, // 11 : ULPI_DATA[0] -> SOC2BTB_BTWAKE_R
|
||||
CFG_DISABLED | SLOW_SLEW, // 12 : SPI1_SCLK ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 13 : SPI1_MOSI ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 14 : SPI1_MISO ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 15 : SPI1_SSIN ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_IN | SLOW_SLEW, // 32 : GPIO[11] -> AP_BUTTON1_L
|
||||
CFG_IN | SLOW_SLEW, // 33 : GPIO[12] -> AP_BUTTON2_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : I2S3_MCK -> AP_TDM3_MCLK
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 35 : I2S3_LRCK -> AP_TDM3_FSYNC
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 36 : I2S3_BCLK -> AP_TDM3_BCLK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 37 : I2S3_DOUT -> AP_TDM3_DOUT
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT, // 38 : I2S3_DIN -> AP_TDM3_DIN
|
||||
CFG_DISABLED | SLOW_SLEW, // 39 : CLK32K_OUT ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 40 : PCIE_CLKREQ0_N -> PCIE0_WLA2SOC_CLKREQ_R_L
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 41 : PCIE_CLKREQ1_N -> PCIE1_WLB2SOC_CLKREQ_R_L
|
||||
CFG_DISABLED | SLOW_SLEW, // 42 : NAND_SYS_CLK ->
|
||||
CFG_OUT_0 | SLOW_SLEW, // 43 : GPIO[0] -> SOC2WLA_DEVICE_WAKE_R
|
||||
CFG_OUT_0 | SLOW_SLEW | INPUT_SCHMITT, // 44 : GPIO[1] -> SOC2WLA_THROTTLE_R
|
||||
CFG_DISABLED | SLOW_SLEW, // 45 : GPIO[2] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 46 : GPIO[3] ->
|
||||
CFG_OUT_1 | SLOW_SLEW, // 47 : GPIO[4] -> CODEC_RESET_L
|
||||
|
||||
/* Port 6 */
|
||||
CFG_OUT_1 | SLOW_SLEW, // 48 : GPIO[5] -> DEV_TUX_AUX_EN
|
||||
CFG_OUT_1 | SLOW_SLEW, // 49 : GPIO[6] -> DEV_TUX_SYNC_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 50 : GPIO[7] -> DEV_TUX_EN
|
||||
CFG_DISABLED | SLOW_SLEW, // 51 : GPIO[14] ->
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 52 : GPIO[16] -> AP_BOARD_ID_3
|
||||
CFG_DISABLED | SLOW_SLEW, // 53 : GPIO[17] ->
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT, // 54 : GPIO[18] -> AP_BOARD_CFG_0
|
||||
CFG_DISABLED | SLOW_SLEW | INPUT_SCHMITT, // 55 : GPIO[20] ->
|
||||
|
||||
/* Port 7 */
|
||||
CFG_OUT_1 | SLOW_SLEW, // 56 : GPIO[21] -> AP_TS_RST_L
|
||||
CFG_DISABLED | SLOW_SLEW | INPUT_SCHMITT, // 57 : UART5_RTXD ->
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW, // 58 : UART8_TXD -> AP_UART8_SOC2MCU
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 59 : UART8_RXD -> AP_UART8_MCU2SOC
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 60 : SPI0_SCLK -> AP_BOARD_ID_0
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 61 : SPI0_MOSI -> AP_BOARD_ID_1
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 62 : SPI0_MISO -> AP_BOARD_ID_2
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 63 : SPI0_SSIN ->
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0 | FAST_SLEW | INPUT_SCHMITT, // 64 : I2C2_SDA -> I2C2_SDA
|
||||
CFG_FUNC0 | FAST_SLEW | INPUT_SCHMITT, // 65 : I2C2_SCL -> I2C2_SCL
|
||||
CFG_IN | SLOW_SLEW | INPUT_SCHMITT, // 66 : GPIO[22] -> AP_TRIG_MYSELF
|
||||
CFG_OUT_1 | SLOW_SLEW | INPUT_SCHMITT, // 67 : GPIO[23] -> NITRO_MCA_BUF_EN_L
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 68 : GPIO[25] -> AP_BOARD_CFG_1
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 69 : GPIO[28] -> AP_BOARD_CFG_2
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 70 : GPIO[29] -> AP_BOARD_ID_4
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 71 : GPIO[34] -> AP_BOARD_REV_3
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 72 : GPIO[35] -> AP_BOARD_REV_2
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 73 : GPIO[36] -> AP_BOARD_REV_1
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 74 : GPIO[37] -> AP_BOARD_REV_0
|
||||
CFG_IN | SLOW_SLEW | INPUT_SCHMITT, // 75 : GPIO[39] -> PCIE0_SOC2WLA_RESET_R_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 76 : GPIO[42] -> AP_LED_SEL
|
||||
CFG_IN | SLOW_SLEW | INPUT_SCHMITT, // 77 : GPIO[43] -> PCIE1_SOC2WLB_RESET_R_L
|
||||
CFG_DISABLED | SLOW_SLEW, // 78 : DISP_VSYNC ->
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW, // 79 : UART0_TXD -> AP_UART0_SOC2USR
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 80 : UART0_RXD -> AP_UART0_USR2SOC
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT, // 81 : TMR32_PWM0 -> WLA2SOC_TIME_SYNC_R
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT, // 82 : TMR32_PWM1 -> WLB2SOC_TIME_SYNC_R
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 83 : TMR32_PWM2 -> AP_LED_PWM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 84 : UART6_TXD -> PLL_S0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 85 : UART6_RXD -> PLL_S1
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 86 : I2C3_SDA -> I2C3_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 87 : I2C3_SCL -> I2C3_SCL
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 12 */
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 96 : I2C0_SDA -> I2C0_SDA
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 97 : I2C0_SCL -> I2C0_SCL
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 98 : GPIO[38] ->
|
||||
CFG_FUNC0 | PULL_UP | FAST_SLEW, // 99 : UART2_TXD -> AP_UART2_SOC2BTB
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 100 : UART2_RXD -> AP_UART2_BTB2SOC
|
||||
CFG_FUNC0 | SLOW_SLEW, // 101 : UART2_RTSN -> AP_UART2_SOC2BTB_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 102 : UART2_CTSN -> AP_UART2_BTB2SOC_CTS_L
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | FAST_SLEW, // 103 : DWI_DO -> AP_DWI_DAT
|
||||
|
||||
/* Port 13 */
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | FAST_SLEW, // 104 : DWI_CLK -> AP_DWI_CLK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 105 : WDOG -> AP_WDOG
|
||||
CFG_IN | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 106 : GPIO[13] -> PMU_IRQ_L
|
||||
CFG_OUT_0 | FAST_SLEW, // 107 : GPIO[19] -> SOC2PMU_KEEPACT
|
||||
CFG_IN | SLOW_SLEW | INPUT_SCHMITT, // 108 : GPIO[26] -> FORCE_DFU
|
||||
CFG_OUT_0 | SLOW_SLEW, // 109 : GPIO[27] -> DFU_STATUS
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 110 : SOCHOT0 -> AP_SOCHOT0_L
|
||||
CFG_FUNC0 | PULL_UP | FAST_SLEW | INPUT_SCHMITT, // 111 : SOCHOT1 -> SOC2PMU_SOCHOT1_L
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 113 : TST_CLKOUT ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 114 : GPIO[8] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 115 : GPIO[9] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 116 : GPIO[10] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 117 : GPIO[15] ->
|
||||
CFG_FUNC0 | PULL_UP | FAST_SLEW, // 118 : UART4_TXD -> AP_UART4_SOC2WLB
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 119 : UART4_RXD -> AP_UART4_WLB2SOC
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 120 : UART4_RTSN -> AP_UART4_SOC2WLB_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 121 : UART4_CTSN -> AP_UART4_WLB2SOC_CTS_L
|
||||
CFG_DISABLED | SLOW_SLEW, // 122 : SPI3_MOSI ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 123 : SPI3_MISO ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 124 : SPI3_SCLK ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 125 : SPI3_SSIN ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 126 : GPIO[24] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 127 : GPIO[30] ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED | SLOW_SLEW, // 128 : GPIO[31] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 129 : GPIO[32] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 130 : GPIO[33] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 131 : GPIO[40] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 132 : GPIO[41] ->
|
||||
CFG_FUNC0 | SLOW_SLEW, // 133 : I2S4_MCK -> AP_I2S4_MCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 134 : I2S4_LRCK -> AP_I2S4_LRCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 135 : I2S4_BCLK -> AP_I2S4_BCLK
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 136 : I2S4_DOUT -> AP_I2S4_DOUT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 137 : I2S4_DIN -> AP_I2S4_DIN
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 138 : I2C1_SDA -> I2C1_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 139 : I2C1_SCL -> I2C1_SCL
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 160 : I2S0_LRCK -> AP_TDM0_FSYNC
|
||||
CFG_FUNC0 | SLOW_SLEW, // 161 : I2S0_BCLK -> AP_TDM0_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 162 : I2S0_DOUT -> AP_TDM0_DOUT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 163 : I2S0_DIN -> AP_TDM0_DIN
|
||||
CFG_FUNC0 | SLOW_SLEW, // 164 : I2S1_MCK -> AP_TDM1_MCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 165 : I2S1_LRCK -> AP_TDM1_FSYNC
|
||||
CFG_FUNC0 | SLOW_SLEW, // 166 : I2S1_BCLK -> AP_TDM1_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 167 : I2S1_DOUT -> AP_TDM1_DOUT
|
||||
|
||||
/* Port 21 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 168 : I2S1_DIN -> AP_TDM1_DIN
|
||||
CFG_FUNC0 | SLOW_SLEW, // 169 : I2S2_LRCK -> AP_TDM2_FSYNC
|
||||
CFG_FUNC0 | SLOW_SLEW, // 170 : I2S2_BCLK -> AP_TDM2_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 171 : I2S2_DOUT -> AP_TDM2_DOUT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 172 : I2S2_DIN -> AP_TDM2_DIN
|
||||
CFG_FUNC0 | PULL_UP | FAST_SLEW, // 173 : UART1_TXD -> AP_UART1_SOC2BTA
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : UART1_RXD -> AP_UART1_BTA2SOC
|
||||
CFG_FUNC0 | SLOW_SLEW, // 175 : UART1_RTSN -> AP_UART1_SOC2BTA_RTS_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 176 : UART1_CTSN -> AP_UART1_BTA2SOC_CTS_L
|
||||
CFG_DISABLED | SLOW_SLEW, // 177 : EDP_HPD ->
|
||||
CFG_FUNC0 | PULL_UP | FAST_SLEW, // 178 : UART3_TXD -> AP_UART3_SOC2WLA
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 179 : UART3_RXD -> AP_UART3_WLA2SOC
|
||||
CFG_FUNC0 | SLOW_SLEW, // 180 : UART3_RTSN -> AP_UART3_SOC2WLA_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 181 : UART3_CTSN -> AP_UART3_WLA2SOC_CTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : SPI2_SCLK -> MCU_SPI2_SCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 183 : SPI2_MOSI -> MCU_SPI2_MOSI
|
||||
|
||||
/* Port 23 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 184 : SPI2_MISO -> MCU_SPI2_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 185 : SPI2_SSIN -> MCU_SPI2_CS_L
|
||||
CFG_DISABLED | SLOW_SLEW, // 186 : ISP0_SDA ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 187 : ISP0_SCL ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 188 : ISP1_SDA ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 189 : ISP1_SCL ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 190 : SENSOR0_RST ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 191 : SENSOR0_CLK ->
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED | SLOW_SLEW, // 192 : SENSOR0_XSHUTDOWN ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 193 : SENSOR0_ISTRB ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 194 : ISP_UART0_TXD ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 195 : ISP_UART0_RXD ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 196 : SENSOR1_RST ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 197 : SENSOR1_CLK ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 198 : SENSOR1_XSHUTDOWN ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 199 : SENSOR1_ISTRB ->
|
||||
|
||||
/* Port 25 */
|
||||
CFG_OUT_0 | FAST_SLEW, // 200 : UART7_TXD -> SOC2BTA_BTWAKE_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 201 : UART7_RXD -> WLA2PMU_HOST_WAKE_R
|
||||
CFG_FUNC0 | FAST_SLEW, // 202 : I2S0_MCK -> AP_TDM0_MCLK
|
||||
CFG_FUNC0 | FAST_SLEW, // 203 : I2S2_MCK -> AP_TDM2_MCLK
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 0 : ULPI_DIR -> LAN_PME_MODE_1V8
|
||||
CFG_DISABLED | SLOW_SLEW, // 1 : ULPI_STP ->
|
||||
CFG_OUT_0 | SLOW_SLEW, // 2 : ULPI_NXT -> LAN_RESET_1V8_L
|
||||
CFG_DISABLED | SLOW_SLEW, // 3 : ULPI_DATA[7] ->
|
||||
CFG_IN | SLOW_SLEW, // 4 : ULPI_DATA[6] -> LAN_PHY_IRQ_1V8
|
||||
CFG_IN | SLOW_SLEW, // 5 : ULPI_DATA[5] -> LAN_PME_1V8
|
||||
CFG_IN | SLOW_SLEW, // 6 : ULPI_DATA[4] -> LAN_HSIC_DEV_RDY
|
||||
CFG_DISABLED | SLOW_SLEW, // 7 : ULPI_CLK ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 8 : ULPI_DATA[3] -> SOC2WLB_DEVICE_WAKE_R
|
||||
CFG_OUT_0 | SLOW_SLEW, // 9 : ULPI_DATA[2] -> SOC2WLB_THROTTLE_R
|
||||
CFG_IN | SLOW_SLEW, // 10 : ULPI_DATA[1] -> WLB2PMU_HOST_WAKE_R
|
||||
CFG_OUT_0 | SLOW_SLEW, // 11 : ULPI_DATA[0] -> SOC2BTB_BTWAKE_R
|
||||
CFG_DISABLED | SLOW_SLEW, // 12 : SPI1_SCLK ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 13 : SPI1_MOSI ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 14 : SPI1_MISO ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 15 : SPI1_SSIN ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_IN | SLOW_SLEW, // 32 : GPIO[11] -> AP_BUTTON1_L
|
||||
CFG_IN | SLOW_SLEW, // 33 : GPIO[12] -> AP_BUTTON2_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : I2S3_MCK -> AP_TDM3_MCLK
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 35 : I2S3_LRCK -> AP_TDM3_FSYNC
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 36 : I2S3_BCLK -> AP_TDM3_BCLK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 37 : I2S3_DOUT -> AP_TDM3_DOUT
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT, // 38 : I2S3_DIN -> AP_TDM3_DIN
|
||||
CFG_DISABLED | SLOW_SLEW, // 39 : CLK32K_OUT ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 40 : PCIE_CLKREQ0_N -> PCIE0_WLA2SOC_CLKREQ_R_L
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 41 : PCIE_CLKREQ1_N -> PCIE1_WLB2SOC_CLKREQ_R_L
|
||||
CFG_DISABLED | SLOW_SLEW, // 42 : NAND_SYS_CLK ->
|
||||
CFG_OUT_0 | SLOW_SLEW, // 43 : GPIO[0] -> SOC2WLA_DEVICE_WAKE_R
|
||||
CFG_OUT_0 | SLOW_SLEW | INPUT_SCHMITT, // 44 : GPIO[1] -> SOC2WLA_THROTTLE_R
|
||||
CFG_DISABLED | SLOW_SLEW, // 45 : GPIO[2] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 46 : GPIO[3] ->
|
||||
CFG_OUT_1 | SLOW_SLEW, // 47 : GPIO[4] -> CODEC_RESET_L
|
||||
|
||||
/* Port 6 */
|
||||
CFG_OUT_1 | SLOW_SLEW, // 48 : GPIO[5] -> DEV_TUX_AUX_EN
|
||||
CFG_OUT_1 | SLOW_SLEW, // 49 : GPIO[6] -> DEV_TUX_SYNC_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 50 : GPIO[7] -> DEV_TUX_EN
|
||||
CFG_DISABLED | SLOW_SLEW, // 51 : GPIO[14] ->
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 52 : GPIO[16] -> AP_BOARD_ID_3
|
||||
CFG_DISABLED | SLOW_SLEW, // 53 : GPIO[17] ->
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT, // 54 : GPIO[18] -> AP_BOARD_CFG_0
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 55 : GPIO[20] ->
|
||||
|
||||
/* Port 7 */
|
||||
CFG_OUT_1 | DRIVE_X4 | SLOW_SLEW, // 56 : GPIO[21] -> AP_TS_RST_L
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 57 : UART5_RTXD ->
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 58 : UART8_TXD -> AP_UART8_SOC2MCU
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 59 : UART8_RXD -> AP_UART8_MCU2SOC
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 60 : SPI0_SCLK -> AP_BOARD_ID_0
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 61 : SPI0_MOSI -> AP_BOARD_ID_1
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 62 : SPI0_MISO -> AP_BOARD_ID_2
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 63 : SPI0_SSIN ->
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0 | DRIVE_X4 | FAST_SLEW | INPUT_SCHMITT, // 64 : I2C2_SDA -> I2C2_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | FAST_SLEW | INPUT_SCHMITT, // 65 : I2C2_SCL -> I2C2_SCL
|
||||
CFG_IN | SLOW_SLEW | INPUT_SCHMITT, // 66 : GPIO[22] -> AP_TRIG_MYSELF
|
||||
CFG_OUT_1 | SLOW_SLEW | INPUT_SCHMITT, // 67 : GPIO[23] -> NITRO_MCA_BUF_EN_L
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 68 : GPIO[25] -> AP_BOARD_CFG_1
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 69 : GPIO[28] -> AP_BOARD_CFG_2
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 70 : GPIO[29] -> AP_BOARD_ID_4
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 71 : GPIO[34] -> AP_BOARD_REV_3
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 72 : GPIO[35] -> AP_BOARD_REV_2
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 73 : GPIO[36] -> AP_BOARD_REV_1
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 74 : GPIO[37] -> AP_BOARD_REV_0
|
||||
CFG_IN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 75 : GPIO[39] -> PCIE0_SOC2WLA_RESET_R_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 76 : GPIO[42] -> AP_LED_SEL
|
||||
CFG_IN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 77 : GPIO[43] -> PCIE1_SOC2WLB_RESET_R_L
|
||||
CFG_DISABLED | SLOW_SLEW, // 78 : DISP_VSYNC ->
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 79 : UART0_TXD -> AP_UART0_SOC2USR
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 80 : UART0_RXD -> AP_UART0_USR2SOC
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT, // 81 : TMR32_PWM0 -> WLA2SOC_TIME_SYNC_R
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT, // 82 : TMR32_PWM1 -> WLB2SOC_TIME_SYNC_R
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 83 : TMR32_PWM2 -> AP_LED_PWM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 84 : UART6_TXD -> PLL_S0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 85 : UART6_RXD -> PLL_S1
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 86 : I2C3_SDA -> I2C3_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 87 : I2C3_SCL -> I2C3_SCL
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 12 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 96 : I2C0_SDA -> I2C0_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 97 : I2C0_SCL -> I2C0_SCL
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 98 : GPIO[38] ->
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | FAST_SLEW, // 99 : UART2_TXD -> AP_UART2_SOC2BTB
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 100 : UART2_RXD -> AP_UART2_BTB2SOC
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 101 : UART2_RTSN -> AP_UART2_SOC2BTB_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 102 : UART2_CTSN -> AP_UART2_BTB2SOC_CTS_L
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | FAST_SLEW, // 103 : DWI_DO -> AP_DWI_DAT
|
||||
|
||||
/* Port 13 */
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | FAST_SLEW, // 104 : DWI_CLK -> AP_DWI_CLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 105 : WDOG -> AP_WDOG
|
||||
CFG_IN | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 106 : GPIO[13] -> PMU_IRQ_L
|
||||
CFG_OUT_0 | FAST_SLEW, // 107 : GPIO[19] -> SOC2PMU_KEEPACT
|
||||
CFG_IN | SLOW_SLEW | INPUT_SCHMITT, // 108 : GPIO[26] -> FORCE_DFU
|
||||
CFG_OUT_0 | SLOW_SLEW, // 109 : GPIO[27] -> DFU_STATUS
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 110 : SOCHOT0 -> AP_SOCHOT0_L
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | FAST_SLEW | INPUT_SCHMITT, // 111 : SOCHOT1 -> SOC2PMU_SOCHOT1_L
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 113 : TST_CLKOUT ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 114 : GPIO[8] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 115 : GPIO[9] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 116 : GPIO[10] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 117 : GPIO[15] ->
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | FAST_SLEW, // 118 : UART4_TXD -> AP_UART4_SOC2WLB
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 119 : UART4_RXD -> AP_UART4_WLB2SOC
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 120 : UART4_RTSN -> AP_UART4_SOC2WLB_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 121 : UART4_CTSN -> AP_UART4_WLB2SOC_CTS_L
|
||||
CFG_DISABLED | SLOW_SLEW, // 122 : SPI3_MOSI ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 123 : SPI3_MISO ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 124 : SPI3_SCLK ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 125 : SPI3_SSIN ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 126 : GPIO[24] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 127 : GPIO[30] ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED | SLOW_SLEW, // 128 : GPIO[31] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 129 : GPIO[32] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 130 : GPIO[33] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 131 : GPIO[40] ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 132 : GPIO[41] ->
|
||||
CFG_FUNC0 | SLOW_SLEW, // 133 : I2S4_MCK -> AP_I2S4_MCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 134 : I2S4_LRCK -> AP_I2S4_LRCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 135 : I2S4_BCLK -> AP_I2S4_BCLK
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 136 : I2S4_DOUT -> AP_I2S4_DOUT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 137 : I2S4_DIN -> AP_I2S4_DIN
|
||||
CFG_FUNC0 | DRIVE_X4 | FAST_SLEW, // 138 : I2C1_SDA -> I2C1_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | FAST_SLEW, // 139 : I2C1_SCL -> I2C1_SCL
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 160 : I2S0_LRCK -> AP_TDM0_FSYNC
|
||||
CFG_FUNC0 | SLOW_SLEW, // 161 : I2S0_BCLK -> AP_TDM0_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 162 : I2S0_DOUT -> AP_TDM0_DOUT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 163 : I2S0_DIN -> AP_TDM0_DIN
|
||||
CFG_FUNC0 | SLOW_SLEW, // 164 : I2S1_MCK -> AP_TDM1_MCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 165 : I2S1_LRCK -> AP_TDM1_FSYNC
|
||||
CFG_FUNC0 | SLOW_SLEW, // 166 : I2S1_BCLK -> AP_TDM1_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 167 : I2S1_DOUT -> AP_TDM1_DOUT
|
||||
|
||||
/* Port 21 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 168 : I2S1_DIN -> AP_TDM1_DIN
|
||||
CFG_FUNC0 | SLOW_SLEW, // 169 : I2S2_LRCK -> AP_TDM2_FSYNC
|
||||
CFG_FUNC0 | SLOW_SLEW, // 170 : I2S2_BCLK -> AP_TDM2_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 171 : I2S2_DOUT -> AP_TDM2_DOUT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 172 : I2S2_DIN -> AP_TDM2_DIN
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | FAST_SLEW, // 173 : UART1_TXD -> AP_UART1_SOC2BTA
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : UART1_RXD -> AP_UART1_BTA2SOC
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 175 : UART1_RTSN -> AP_UART1_SOC2BTA_RTS_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 176 : UART1_CTSN -> AP_UART1_BTA2SOC_CTS_L
|
||||
CFG_DISABLED | SLOW_SLEW, // 177 : EDP_HPD ->
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | FAST_SLEW, // 178 : UART3_TXD -> AP_UART3_SOC2WLA
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 179 : UART3_RXD -> AP_UART3_WLA2SOC
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 180 : UART3_RTSN -> AP_UART3_SOC2WLA_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 181 : UART3_CTSN -> AP_UART3_WLA2SOC_CTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : SPI2_SCLK -> MCU_SPI2_SCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 183 : SPI2_MOSI -> MCU_SPI2_MOSI
|
||||
|
||||
/* Port 23 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 184 : SPI2_MISO -> MCU_SPI2_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 185 : SPI2_SSIN -> MCU_SPI2_CS_L
|
||||
CFG_DISABLED | SLOW_SLEW, // 186 : ISP0_SDA ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 187 : ISP0_SCL ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 188 : ISP1_SDA ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 189 : ISP1_SCL ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 190 : SENSOR0_RST ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 191 : SENSOR0_CLK ->
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED | SLOW_SLEW, // 192 : SENSOR0_XSHUTDOWN ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 193 : SENSOR0_ISTRB ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 194 : ISP_UART0_TXD ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 195 : ISP_UART0_RXD ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 196 : SENSOR1_RST ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 197 : SENSOR1_CLK ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 198 : SENSOR1_XSHUTDOWN ->
|
||||
CFG_DISABLED | SLOW_SLEW, // 199 : SENSOR1_ISTRB ->
|
||||
|
||||
/* Port 25 */
|
||||
CFG_OUT_0 | DRIVE_X4 | FAST_SLEW, // 200 : UART7_TXD -> SOC2BTA_BTWAKE_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 201 : UART7_RXD -> WLA2PMU_HOST_WAKE_R
|
||||
CFG_FUNC0 | FAST_SLEW, // 202 : I2S0_MCK -> AP_TDM0_MCLK
|
||||
CFG_FUNC0 | FAST_SLEW, // 203 : I2S2_MCK -> AP_TDM2_MCLK
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
};
|
||||
|
||||
struct pinconfig_map {
|
||||
uint32_t board_id;
|
||||
uint32_t board_id_mask;
|
||||
const uint32_t *pinconfigs[GPIOC_COUNT];
|
||||
};
|
||||
|
||||
static const struct pinconfig_map cfg_map[] = {
|
||||
{ 0, 1, { pinconfig_ap_0 } },
|
||||
{ 1, 1, { pinconfig_dev_0 } },
|
||||
};
|
||||
|
||||
const uint32_t * target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
static const struct pinconfig_map *selected_map = NULL;
|
||||
|
||||
if (selected_map == NULL) {
|
||||
uint32_t board_id = platform_get_board_id();
|
||||
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
|
||||
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
|
||||
selected_map = &cfg_map[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (selected_map == NULL)
|
||||
panic("no default pinconfig for board id %u", board_id);
|
||||
}
|
||||
|
||||
ASSERT(gpioc < GPIOC_COUNT);
|
||||
return selected_map->pinconfigs[gpioc];
|
||||
}
|
||||
@@ -0,0 +1,36 @@
|
||||
# Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2186=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_V2 \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=CHIPID_SOC_VOLTAGE_VMIN \
|
||||
TARGET_VID0_CLK_CFG=0x86100000 \
|
||||
TARGET_PHY_STOP_WAIT_TIME=0x28 \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_SOC=2 \
|
||||
BUCK_GPU=1 \
|
||||
WIFI_DTPATH=\"arm-io/uart3/wlan\" \
|
||||
BT_DTPATH=\"arm-io/uart1/bluetooth\" \
|
||||
TARGET_HS_2_LP_DATA_TIME=24 \
|
||||
TARGET_LP_2_HS_DATA_TIME=63 \
|
||||
TARGET_HS_2_LP_CLOCK_TIME=36 \
|
||||
TARGET_LP_2_HS_CLOCK_TIME=79
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o $(LOCAL_DIR)/pinconfig.o
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_ADBE_SETTINGS_H
|
||||
#define __TARGET_ADBE_SETTINGS_H
|
||||
|
||||
static struct adbe_v2_tuneable adbe_tuneables[] = {
|
||||
{
|
||||
.name = "default",
|
||||
.adbe0_vblank_pos_vbi_pulse = 0x0000,
|
||||
.adbe0_vblank_clk_gate_wakeup = 0x0000,
|
||||
.adbe0_vblank_clk_gate_idle = 0x0001,
|
||||
.adbe0_vblank_busy_finish = 2,
|
||||
.adbe0_tunable_mode_ctrl = (DBEMODECNTL_PMGR_CLK_GATE_ENABLE | DBEMODECNTL_DYN_CLK_GATE_ENABLE | DBEMODECNTL_BLK_CLK_GATE_ENABLE),
|
||||
.adbe0_aap_support = 1,
|
||||
.adbe0_aap_format_control_reg1 = (AAP_FORMAT_CONTROL_REG1_AUTOPOS | AAP_FORMAT_CONTROL_REG1_RSVD(8) | AAP_FORMAT_CONTROL_REG1_VS_POL),
|
||||
},
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The amc_param struct is defined in drivers/apple/amc/amc.h, and this
|
||||
* file should only by included from amc.c.
|
||||
*/
|
||||
|
||||
static const struct amc_param amc_params = {
|
||||
.lat = 0x00040200,
|
||||
.phyrdwrtim = 0x00010802,
|
||||
.tREFi = 0x11,
|
||||
.pdn = 0x22000203,
|
||||
.derate = 0x04110111,
|
||||
.read = 0x00000101,
|
||||
.bustat = 0x00222209,
|
||||
.bustat2 = 0x00222209,
|
||||
.pwrmngten_default = 0x00100100,
|
||||
.schen_default = 0x00001110,
|
||||
.mcphyupdate = 0x15030000,
|
||||
.mcphyupdate1 = 0x00000001,
|
||||
.arefparam = 0x0ca2b532,
|
||||
.longsr = 0x05022008,
|
||||
.mr1 = 0x84,
|
||||
.mr2 = 0x06,
|
||||
.mr3 = 0x03,
|
||||
.addrcfg = 0x00020201,
|
||||
.mccchnldec = 0x00050020,
|
||||
.mcuchnhash = 0x0ffffd54,
|
||||
.mcuchnhash2 = 0x0aaaaaa8,
|
||||
.mcschnldec = 0x00020200,
|
||||
.qbrparam = 0x00050200,
|
||||
.odts = 0x00000320,
|
||||
.addrmapmode = 0x00000501,
|
||||
|
||||
.freq = {
|
||||
{ // 800MHz
|
||||
.cas = 0x00000203,
|
||||
.pch = 0x00020303,
|
||||
.act = 0x08020303,
|
||||
.autoref = 0x01020000,
|
||||
.selfref = 0x00002030,
|
||||
.modereg = 0x20010732,
|
||||
},
|
||||
{ // 400MHz
|
||||
.cas = 0x00000003,
|
||||
.pch = 0x00000003,
|
||||
.act = 0x08020303,
|
||||
.autoref = 0x01020000,
|
||||
.selfref = 0x00002000,
|
||||
.modereg = 0x00010000,
|
||||
},
|
||||
{ // 200MHz
|
||||
.cas = 0x00000003,
|
||||
.pch = 0x00000003,
|
||||
.act = 0x08020303,
|
||||
.autoref = 0x01020000,
|
||||
.selfref = 0x00002000,
|
||||
.modereg = 0x00010000,
|
||||
},
|
||||
{ // 50MHz
|
||||
.cas = 0x00000003,
|
||||
.pch = 0x00000003,
|
||||
.act = 0x08020303,
|
||||
.autoref = 0x01020000,
|
||||
.selfref = 0x00002000,
|
||||
.modereg = 0x00010000,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static const struct amc_tunable amc_tunables[] = {
|
||||
{ &rAMC_MCSARBCFG, 0x00000001 },
|
||||
{ &rAMC_OPIDLETMR, 0x00200000 },
|
||||
{ &rAMC_OPTMRADJPARAM, 0x20400064 },
|
||||
{ &rAMC_MIFACTSCH, 0x00000001 },
|
||||
{ &rAMC_MIFCASSCH_FREQ(0), 0x10000010 },
|
||||
{ &rAMC_PSQRQCTL0, 0xff010110 },
|
||||
{ &rAMC_PSQRQCTL1, 0x00001700 },
|
||||
{ &rAMC_PSQRQTIMER0, 0x00000040 },
|
||||
{ &rAMC_PSQRQTIMER1, 0x00000014 },
|
||||
{ &rAMC_PSQRQTIMER2, 0x00000040 },
|
||||
{ &rAMC_PSQRQBRST, 0x04100410 },
|
||||
{ &rAMC_PSQRQSCHCRD, 0x00101400 },
|
||||
{ &rAMC_PSQWQCTL0, 0x00010100 },
|
||||
{ &rAMC_PSQWQCTL1, 0x00000336 },
|
||||
{ &rAMC_PSQWQBRST, 0x04080410 },
|
||||
{ &rAMC_PSQWQSCHCRD, 0x00101400 },
|
||||
{ &rAMC_MCUQOSLLT, 0x0000011f },
|
||||
{ &rAMC_PWRMNGTPARAM, 0x03521000 },
|
||||
};
|
||||
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The amc_phy_params struct is defined in drivers/apple/amp_v3/amp_v3.h, and this
|
||||
* file should only by included from amp_v3.c.
|
||||
*/
|
||||
|
||||
static const struct amp_params amc_phy_params = {
|
||||
.freq = {
|
||||
{
|
||||
.caoutdllscl = 0x00000008,
|
||||
.dqsindllscl = 0x00000008,
|
||||
.rdcapcfg = 0x01010304,
|
||||
},
|
||||
{
|
||||
.caoutdllscl = 0x00000010,
|
||||
.dqsindllscl = 0x00000010,
|
||||
.rdcapcfg = 0x21010309,
|
||||
},
|
||||
{
|
||||
.caoutdllscl = 0x00000020,
|
||||
.dqsindllscl = 0x00000020,
|
||||
.rdcapcfg = 0x41010306,
|
||||
},
|
||||
{
|
||||
.caoutdllscl = 0x0000003f,
|
||||
.dqsindllscl = 0x0000003f,
|
||||
.rdcapcfg = 0x61010304,
|
||||
},
|
||||
},
|
||||
};
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_ASPNANDCONFIG_H
|
||||
#define __TARGET_ASPNANDCONFIG_H
|
||||
|
||||
//MLC devices
|
||||
#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_ERASE_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_READ_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
|
||||
//TLC devices
|
||||
#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
|
||||
// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
|
||||
#define ASPNAND_INDIRECTION_MEMORY (2*1024*1024)
|
||||
#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_GPIODEF_H
|
||||
#define __TARGET_GPIODEF_H
|
||||
|
||||
/* CapriRef specific gpio -> pin mappings */
|
||||
|
||||
#include <platform/gpio.h>
|
||||
|
||||
/* define target-specific gpios in a generic fashion here. */
|
||||
|
||||
/* Board Revision */
|
||||
#define GPIO_BOARD_REV0 GPIO( 20, 1) // 161 : ULPI_NXT
|
||||
#define GPIO_BOARD_REV1 GPIO( 19, 7) // 159 : ULPI_DIR
|
||||
#define GPIO_BOARD_REV2 GPIO( 21, 0) // 168 : ULPI_DATA[2]
|
||||
#define GPIO_BOARD_REV3 GPIO( 20, 3) // 163 : ULPI_DATA[6]
|
||||
|
||||
/* D2207 watchdog tickle, 'KEEPACT' */
|
||||
#define GPIO_WDOG_TICKLE GPIO( 10, 7) // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
#endif /* ! __TARGET_GPIODEF_H */
|
||||
@@ -0,0 +1,97 @@
|
||||
#ifndef __TARGET_POWERCONFIG_H
|
||||
#define __TARGET_POWERCONFIG_H
|
||||
|
||||
/* configuration per target */
|
||||
|
||||
#define PMU_IIC_BUS 0
|
||||
|
||||
/* this configuration is very PMU specific and must be included exactly once in power.c */
|
||||
#ifdef POWERCONFIG_PMU_SETUP
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
|
||||
{
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kD2207_HIBERNATE3, 0x90 }, // enable LDO7+LDO4 in hibernate
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_warm_init[] =
|
||||
{
|
||||
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_cold_init[] =
|
||||
{
|
||||
/* <rdar://problem/14847504> J82 IO Spreadsheet */
|
||||
#if TARGET_HAS_BASEBAND
|
||||
{ PMU_IIC_BUS, kD2207_GPIO5, 0x09}, // PMU_GPIO_PMU2BBPMU_RST_L Out 0, Push-Pull, VBUCK3
|
||||
#else
|
||||
{ PMU_IIC_BUS, kD2207_GPIO5, 0xB9}, // PMU_GPIO_PMU2BBPMU_RST_L In, R Edge, PD
|
||||
#endif
|
||||
{ PMU_IIC_BUS, kD2207_GPIO6, 0xDA}, // UART5_BATT_TRXD In, F Edge, Wake, PD
|
||||
{ PMU_IIC_BUS, kD2207_GPIO7, 0xBA}, // PMU_GPIO_BT_HOST_WAKE In, R Edge, Wake, PD
|
||||
{ PMU_IIC_BUS, kD2207_GPIO8, 0xBA}, // PMU_GPIO_WLAN_HOST_WAKE In, R Edge, Wake, PD
|
||||
#if TARGET_HAS_BASEBAND
|
||||
{ PMU_IIC_BUS, kD2207_GPIO9, 0xBA}, // PMU_GPIO_BB2PMU_HOST_WAKE In, R Edge, Wake, PU, VBUCK3
|
||||
#else
|
||||
{ PMU_IIC_BUS, kD2207_GPIO9, 0xB9}, // PMU_GPIO_BB2PMU_HOST_WAKE In, R Edge, PD
|
||||
#endif
|
||||
{ PMU_IIC_BUS, kD2207_GPIO10, 0xCA}, // PMU_GPIO_CODEC_HS_INT_L In, F Edge, Wake, PU, VBUCK3
|
||||
{ PMU_IIC_BUS, kD2207_GPIO11, 0xFA}, // PMU_GPIO_MB_HALL1_IRQ In, Any Edge, Wake, No PU
|
||||
{ PMU_IIC_BUS, kD2207_GPIO12, 0x7B}, // GPIO_TS2SOC2PMU_INT In, Hi level, Wake, PD
|
||||
{ PMU_IIC_BUS, kD2207_GPIO14, 0xB8}, // PMU_GPIO_WLAN2PMU_PCIE_WAKE_L In, R Edge, PU
|
||||
{ PMU_IIC_BUS, kD2207_GPIO16, 0x7B}, // PMU_GPIO_OSCAR2PMU_HOST_WAKE In, Hi level, Wake, PD
|
||||
|
||||
{ PMU_IIC_BUS, kD2207_BUCK_DWI_CTRL0, 0x07 }, // enable DWI for BUCK0, BUCK1, BUCK2
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_backlight_enable[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_ISET, 0xD4 }, // 50% value from OS
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_ISET2, 0x00 },
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, // enable all LED strings
|
||||
(kDIALOG_WLED_CONTROL_WLED_ENABLE1 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE2 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE3 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE4 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE5 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE6) },
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_OPTIONS, // enable LED Power
|
||||
(kDIALOG_WLED_CONTROL2_WLED_RAMP_EN |
|
||||
kDIALOG_WLED_CONTROL2_WLED_DITH_EN) }
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_backlight_disable[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, 0x0 } // disable LED power
|
||||
};
|
||||
|
||||
static const struct core_rails_struct soc_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2207_BUCK2_VSEL }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct cpu_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2207_BUCK0_VSEL }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct ram_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2207_BUCK5_VSEL }
|
||||
};
|
||||
|
||||
#endif /* POWERCONFIG_PMU_SETUP */
|
||||
|
||||
#define NO_BATTERY_VOLTAGE 2700
|
||||
#define MIN_BOOT_BATTERY_VOLTAGE 3600
|
||||
#define TARGET_BOOT_BATTERY_VOLTAGE 3700
|
||||
#define TARGET_BOOT_BATTERY_CAPACITY 50
|
||||
#define PRECHARGE_BACKLIGHT_LEVEL 824
|
||||
#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
|
||||
|
||||
#define ACC_PWR_LDO (6)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define one debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (0)
|
||||
|
||||
#define HDQGAUGE_SERIAL_PORT (5)
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define UART_OVERSAMPLE_OVERRIDE (11)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,90 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/power.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <target.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return platform_get_request_dfu2() && power_has_usb();
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
*cold_button_boot = false;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
uint32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
#if WITH_ENV
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
// boot-device is set in platform's init.c
|
||||
env_set("wifiaddr", "7E:77:77:77:77:77", 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif // WITH_DEVICETREE
|
||||
@@ -0,0 +1,258 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* FIXME: just pulled these direction from ipad5b, may need to update */
|
||||
|
||||
/* THIS STRUCT IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: rev 0.2
|
||||
I/O Spreadsheet tracker: <rdar://problem/14847504> J82 IO Spreadsheet
|
||||
*/
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2OSLO_EN
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2OSLO_DWLD_REQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 15 : UART3_RXD -> UART_BT2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 33 : UART3_CTSN -> UART_BT2SOC_RTS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_GRAPE_MISO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_OUT_1, // 51 : SPI3_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_DISABLED, // 53 : TMR32_PWM1 -> GPIO_SOC2GRAPE_HV_BOOST_EN
|
||||
CFG_DISABLED, // 54 : TMR32_PWM2 -> JTAG_BB_TCK
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_DISABLED, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_DISABLED, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_DISABLED, // 63 : UART7_TXD -> GPIO_TT2SOC_SMI_L
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // 64 : UART7_RXD -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_DISABLED, // 70 : SPI0_SSIN -> JTAG_BB_TMS
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2OSLO_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_OSLO2SOC_TX
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2OSLO_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_OSLO2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // 80 : GPIO[0] -> GPIO_SOC2TT_MUX_SEL
|
||||
CFG_DISABLED, // 81 : GPIO[1] -> GPIO_SOC2TT_PWR_SW_EN
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN | PULL_UP, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_DISABLED, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_SW_EN
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // 88 : GPIO[8] -> GPIO_GANGES2SOC_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_ALS2SOC_DEVBRD_IRQ_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2SPKRAMP_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_DISABLED, // 94 : GPIO[14] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_DISABLED, // 99 : GPIO[19] -> GPIO_SOC2TT_POR_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED | PULL_DOWN, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> NC_BOARD_ID4
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_BTN_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_IN | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_IN | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2OSCAR_TX
|
||||
CFG_FUNC0, // 123 : UART8_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BB_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BB2SOC_TX
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BB2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_DISABLED, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_DISABLED, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_DISABLED, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 156 : SPI1_MISO -> SPI_CODEC_MISO
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_32K
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // 160 : ULPI_STP -> GPIO_SOC2DEVBRD_S3E_WAKE
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_DISABLED, // 167 : ULPI_DATA[3] -> GPIO_SOC2DEVBRD_S3E_RESET2_L
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_DISABLED, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_DISABLED, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED, // 175 : PCIE_CLKREQ2_N -> PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> CLK_SOC2DEVBRD_PCIE_24MHZ
|
||||
CFG_DISABLED, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> NC_PERST3
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_DISABLED, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
return gpio_default_cfg;
|
||||
}
|
||||
@@ -0,0 +1,32 @@
|
||||
# Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2207=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_V2 \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=CHIPID_SOC_VOLTAGE_VMIN \
|
||||
TARGET_VID0_CLK_CFG=0x86100000 \
|
||||
TARGET_DDR_798M=1 \
|
||||
DISPLAY_LANDSCAPE_IPAD_TUNABLES=1 \
|
||||
AMC_NUM_CHANNELS=4 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_GPU=2 \
|
||||
BUCK_RAM=1
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_ADBE_SETTINGS_H
|
||||
#define __TARGET_ADBE_SETTINGS_H
|
||||
|
||||
static struct adbe_v1_tuneable adbe_tuneables[] = {
|
||||
{
|
||||
.name = "default",
|
||||
.adbe0_vblank_pos_vbi_pulse = 0x0000,
|
||||
.adbe0_vblank_clk_gate_wakeup = 0x0000,
|
||||
.adbe0_vblank_clk_gate_idle = 0x0001,
|
||||
.adbe0_vblank_blk_idle_dpb = 0x0000,
|
||||
.adbe0_vblank_blk_idle_aap = 0x0000,
|
||||
.adbe0_tunable_mode_ctrl = (DBEMODECNTL_DYN_CLK_GATE_ENABLE | DBEMODECNTL_AFC_TEARDOWN_ENABLE | DBEMODECNTL_PMGR_CLK_GATE_ENABL| DBEMODECNTL_BLK_CLK_GATE_ENABLE),
|
||||
.adbe0_aap_support = 1,
|
||||
},
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,155 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The amc_param struct is defined in drivers/apple/amc/amc.h, and this
|
||||
* file should only by included from amc.c.
|
||||
*/
|
||||
|
||||
#define AMC_PARAMS_AP_DEV (1)
|
||||
|
||||
static const struct amc_param amc_params_dev = {
|
||||
.flags = (FLAG_AMC_PARAM_BUSTAT23),
|
||||
|
||||
.tREFi = 0x11,
|
||||
.longsrcnt = 0x2008,
|
||||
.srextrarefcnt = 0x00020000,
|
||||
.rdlat = 4,
|
||||
.wrlat = 2,
|
||||
.phyrdlat = 10,
|
||||
.phywrlat = 1,
|
||||
.pdn = 0x22000203,
|
||||
.read = 0x00000101,
|
||||
.bustat = 0x0022221b,
|
||||
.bustat2 = 0x0022221b,
|
||||
.derate = 0x04110111,
|
||||
.mcphyupdate = 0x05030000,
|
||||
.autoref_params = 0x00000021,
|
||||
.pwrmngtparam_small = 0x00011000,
|
||||
.pwrmngtparam_guided = 0x01801000,
|
||||
.chnldec = 0x00050000,
|
||||
.arefparam = 0x0c00a000,
|
||||
.aref_freq0 = 0x00000110,
|
||||
.schen_default = 0x00000110,
|
||||
.mr1 = 0x44,
|
||||
.mr2 = 0x1a,
|
||||
.pwrmngten_default = 0x00100000,
|
||||
|
||||
.freq = {
|
||||
{ // 522MHz
|
||||
.cas = 0x00000203,
|
||||
.pch = 0x00020303,
|
||||
.act = 0x08020303,
|
||||
.autoref = 0x01020000,
|
||||
.selfref = 0x00002030,
|
||||
.modereg = 0x00010772,
|
||||
.mifcassch = 0x001f0110,
|
||||
},
|
||||
{ // 400MHz
|
||||
.cas = 0x00000003,
|
||||
.pch = 0x00000003,
|
||||
.act = 0x08020303,
|
||||
.autoref = 0x01020000,
|
||||
.selfref = 0x00002000,
|
||||
.modereg = 0x00010000,
|
||||
.mifcassch = 0x00000000,
|
||||
},
|
||||
{ // 200MHz
|
||||
.cas = 0x00000003,
|
||||
.pch = 0x00000003,
|
||||
.act = 0x08020303,
|
||||
.autoref = 0x01020000,
|
||||
.selfref = 0x00002000,
|
||||
.modereg = 0x00010000,
|
||||
.mifcassch = 0x00000000,
|
||||
},
|
||||
{ // 50 & 24MHz
|
||||
.cas = 0x00000003,
|
||||
.pch = 0x00000003,
|
||||
.act = 0x08020303,
|
||||
.autoref = 0x01020000,
|
||||
.selfref = 0x00002000,
|
||||
.modereg = 0x00010000,
|
||||
.mifcassch = 0x00000000,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static const struct amc_param amc_params_ap = {
|
||||
.flags = (FLAG_AMC_PARAM_BUSTAT23 | FLAG_AMC_PARAM_SLOW_BOOT),
|
||||
|
||||
.tREFi = 0x5d,
|
||||
.longsrcnt = 0x2008,
|
||||
.srextrarefcnt = 0x00020000,
|
||||
.rdlat = 6,
|
||||
.wrlat = 3,
|
||||
.phyrdlat = 10,
|
||||
.phywrlat = 2,
|
||||
.pdn = 0x22000403,
|
||||
.read = 0x00000203,
|
||||
.bustat = 0x0022221b,
|
||||
.bustat2 = 0x0022221b,
|
||||
.derate = 0x2483135b,
|
||||
.mcphyupdate = 0x05030000,
|
||||
.autoref_params = 0x00000021,
|
||||
.pwrmngtparam_small = 0x00011000,
|
||||
.pwrmngtparam_guided = 0x01801000,
|
||||
.chnldec = 0x00050000,
|
||||
.arefparam = 0x0c00a000,
|
||||
.aref_freq0 = 0x00000110,
|
||||
.schen_default = 0x00000110,
|
||||
.mr1 = 0x44,
|
||||
.mr2 = 0x1a,
|
||||
.pwrmngten_default = 0x00100000,
|
||||
|
||||
.freq = {
|
||||
{ // 522MHz
|
||||
.cas = 0x00000308,
|
||||
.pch = 0x00030612,
|
||||
.act = 0x14040908,
|
||||
.autoref = 0x19350000,
|
||||
.selfref = 0x00039060,
|
||||
.modereg = 0x40250772,
|
||||
.mifcassch = 0x001f0110,
|
||||
},
|
||||
{ // 400MHz
|
||||
.cas = 0x00000005,
|
||||
.pch = 0x00000009,
|
||||
.act = 0x0a020505,
|
||||
.autoref = 0x0d1b0000,
|
||||
.selfref = 0x0001d000,
|
||||
.modereg = 0x00130000,
|
||||
.mifcassch = 0x00000000,
|
||||
},
|
||||
{ // 200MHz
|
||||
.cas = 0x00000003,
|
||||
.pch = 0x00000005,
|
||||
.act = 0x08020303,
|
||||
.autoref = 0x070e0000,
|
||||
.selfref = 0x0000f000,
|
||||
.modereg = 0x000a0000,
|
||||
.mifcassch = 0x00000000,
|
||||
},
|
||||
{ // 50
|
||||
.cas = 0x00000003,
|
||||
.pch = 0x00000003,
|
||||
.act = 0x08020303,
|
||||
.autoref = 0x02040000,
|
||||
.selfref = 0x00004000,
|
||||
.modereg = 0x00030000,
|
||||
.mifcassch = 0x00000000,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static const struct amc_tunable amc_tunables[] = {
|
||||
{ 0, 0 }
|
||||
};
|
||||
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The amc_param struct is defined in drivers/apple/amp/amp.h, and this
|
||||
* file should only by included from that amp.c.
|
||||
*/
|
||||
|
||||
static struct amp_params amc_phy_params = {
|
||||
.freq = {
|
||||
{
|
||||
.caoutdllscl = 0x00000008,
|
||||
.dqsindllscl = 0x00000008,
|
||||
.rdcapcfg = 0x0002040a
|
||||
},
|
||||
{
|
||||
.caoutdllscl = 0x00000010,
|
||||
.dqsindllscl = 0x00000010,
|
||||
.rdcapcfg = 0x20020308
|
||||
},
|
||||
{
|
||||
.caoutdllscl = 0x00000020,
|
||||
.dqsindllscl = 0x00000020,
|
||||
.rdcapcfg = 0x40020308
|
||||
},
|
||||
{
|
||||
.caoutdllscl = 0x0000003f,
|
||||
.dqsindllscl = 0x0000003f,
|
||||
.rdcapcfg = 0x60020308
|
||||
}
|
||||
}
|
||||
};
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_ASPNANDCONFIG_H
|
||||
#define __TARGET_ASPNANDCONFIG_H
|
||||
|
||||
//MLC devices
|
||||
#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_ERASE_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_READ_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
|
||||
//TLC devices
|
||||
#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
|
||||
// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
|
||||
#define ASPNAND_INDIRECTION_MEMORY (2*1024*1024)
|
||||
#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_GPIODEF_H
|
||||
#define __TARGET_GPIODEF_H
|
||||
|
||||
/* Cyclonic specific gpio -> pin mappings */
|
||||
|
||||
#include <platform/gpio.h>
|
||||
|
||||
/* define target-specific gpios in a generic fashion here. */
|
||||
|
||||
#endif /* ! __TARGET_GPIODEF_H */
|
||||
@@ -0,0 +1,153 @@
|
||||
|
||||
// Copyright (C) 2008-2010 Apple, Inc. All rights reserved.
|
||||
//
|
||||
// This document is the property of Apple, Inc.
|
||||
// It is considered confidential and proprietary.
|
||||
//
|
||||
// This document may not be reproduced or transmitted in any form,
|
||||
// in whole or in part, without the express written permission of
|
||||
// Apple, Inc.
|
||||
//
|
||||
// NOTE: This is a generated file and should not be hand-edited!
|
||||
//
|
||||
|
||||
// =============================================================================
|
||||
// Nand Geometry Table
|
||||
|
||||
static NandGeometry _nandGeometryTable[] =
|
||||
{
|
||||
{
|
||||
/* chipId */ { 0x98, 0xE7, 0x94, 0x32 },
|
||||
/* blocksPerCS */ 4100,
|
||||
/* pagesPerBlock */ 128,
|
||||
/* dataBytesPerPage */ 8192,
|
||||
/* spareBytesPerPage */ 448,
|
||||
/* eccPer512Bytes */ 16,
|
||||
/* initialBBType */ INIT_BBT_TOSHIBA_MLC,
|
||||
/* diesPerCS */ 1
|
||||
}
|
||||
};
|
||||
|
||||
// =============================================================================
|
||||
// Nand Timing Table
|
||||
|
||||
static NandTiming _nandTimingTable[] =
|
||||
{
|
||||
{
|
||||
/* configId */
|
||||
{
|
||||
/* connectedBusCnt */ 2,
|
||||
/* packageCnt */ 1,
|
||||
/* packageIds[] */
|
||||
{
|
||||
{
|
||||
/* chipId */ { 0x98, 0xE7, 0x94, 0x32 },
|
||||
/* ceCnt */ 2
|
||||
}
|
||||
}
|
||||
},
|
||||
/* writeCycleNanosecs */ 25,
|
||||
/* writeSetupNanosecs */ 12,
|
||||
/* writeHoldNanosecs */ 10,
|
||||
/* readCycleNanosecs */ 25,
|
||||
/* readSetupNanosecs */ 12,
|
||||
/* readHoldNanosecs */ 10,
|
||||
/* readDelayNanosecs */ 20,
|
||||
/* readValidNanosecs */ 25
|
||||
}
|
||||
};
|
||||
|
||||
#if (defined (AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
|
||||
// =============================================================================
|
||||
// NandChipId Description
|
||||
const NandChipIdDescription _nandChipIdDescriptionTable[] =
|
||||
{
|
||||
{
|
||||
/* chipId */ { 0x98, 0xE7, 0x94, 0x32 },
|
||||
/* die */ "32nm",
|
||||
/* vendor_name */ "Toshiba"
|
||||
}
|
||||
};
|
||||
|
||||
// =============================================================================
|
||||
// Nand Description Table
|
||||
|
||||
static const NandDescription _nandDescriptionTable[] =
|
||||
{
|
||||
{
|
||||
/* packageId */
|
||||
{
|
||||
/* chipId */ { 0x98, 0xE7, 0x94, 0x32 },
|
||||
/* ceCnt */ 2
|
||||
},
|
||||
/* appleName */ "335S0700",
|
||||
/* vendor_part_num */ "TH58NVG6D2FLA49",
|
||||
/* package_type */ "DDP",
|
||||
/* package_size */ "1.00mm LGA"
|
||||
}
|
||||
};
|
||||
const UInt32 _nandDescriptionTableSize = sizeof(_nandDescriptionTable) / sizeof(NandDescription);
|
||||
|
||||
#endif // (defined(AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
|
||||
|
||||
// =============================================================================
|
||||
// Nand Board Support Table
|
||||
|
||||
static NandBoardSupport _nandBoardSupportTable[] =
|
||||
{
|
||||
{
|
||||
/* configId */
|
||||
{
|
||||
/* connectedBusCnt */ 2,
|
||||
/* packageCnt */ 1,
|
||||
/* packageIds[] */
|
||||
{
|
||||
{
|
||||
/* deviceId */ { 0x98, 0xE7, 0x94, 0x32 },
|
||||
/* ceCnt */ 2
|
||||
}
|
||||
}
|
||||
},
|
||||
/* vsType */ FIL_VS_TOSHIBA_2P_EXT
|
||||
}
|
||||
};
|
||||
|
||||
// =============================================================================
|
||||
// Nand Board Timing Table
|
||||
|
||||
static NandBoardInfo _nandBoardInfo =
|
||||
{
|
||||
/* controlDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
|
||||
/* dataDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
|
||||
/* chipEnableDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
|
||||
|
||||
/* socToNandRiseNanosecs */ 10,
|
||||
/* socToNandFallNanosecs */ 10,
|
||||
/* nandToSocRiseNanosecs */ 10,
|
||||
/* nandToSocFallNanosecs */ 10,
|
||||
|
||||
/* landing map */
|
||||
{
|
||||
0x00000303
|
||||
},
|
||||
|
||||
/* useToggleMode */ 0,
|
||||
/* useDiffDQSMode */ 0,
|
||||
/* useDiffREMode */ 0,
|
||||
/* useVref */ 0
|
||||
};
|
||||
|
||||
static NandFormat _nandFormatPpn =
|
||||
{
|
||||
/* metaPerLogicalPage */ 16,
|
||||
/* validMetaPerLogicalPage */ 16,
|
||||
/* logicalPageSize */ 0
|
||||
};
|
||||
|
||||
static NandFormat _nandFormatRaw =
|
||||
{
|
||||
/* metaPerLogicalPage */ 12,
|
||||
/* validMetaPerLogicalPage */ 10,
|
||||
/* logicalPageSize */ 0
|
||||
};
|
||||
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __TARGET_POWERCONFIG_H
|
||||
#define __TARGET_POWERCONFIG_H
|
||||
|
||||
// Minimal definitions to make lib/power.c happy
|
||||
#define TARGET_POWER_NO_BATTERY 1
|
||||
#define PRECHARGE_BACKLIGHT_LEVEL 824
|
||||
#define ALWAYS_BOOT_BATTERY_VOLTAGE (5000)
|
||||
|
||||
// This fake SoC block takes the place of the external PMU in Fastsim
|
||||
#define SWIFTER_PMU_BASE 0x20F050000
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define two debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (0)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,223 @@
|
||||
/*
|
||||
* Copyright (C) 2011-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/flash_nor.h>
|
||||
#include <lib/devicetree.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <sys.h>
|
||||
#include <sys/menu.h>
|
||||
#include <sys/task.h>
|
||||
#include <target.h>
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
uint32_t display_config;
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
*cold_button_boot = true;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if !PRODUCT_LLB
|
||||
bool target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
void * target_get_display_configuration(void)
|
||||
{
|
||||
|
||||
display_config = 0x00000da2;
|
||||
return ((void *)(&display_config));
|
||||
}
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
env_set("boot-args", "debug=0x14e serial=3 amfi=0x83 cs_enforcement_disable=1 fips_mode=0 -disable_aslr", ENV_PERSISTENT);
|
||||
env_set("boot-device", "asp_nand", 0);
|
||||
env_set("display-color-space","RGB888", 0);
|
||||
env_set("display-timing", "n51", 0);
|
||||
env_set("idle-off", "false", 0);
|
||||
env_set("kaslr-slide", "0x10000000", 0);
|
||||
env_set("wifiaddr", "12:22:33:44:55:66", 0);
|
||||
env_set("ethaddr", "12:22:33:44:55:77", 0);
|
||||
env_set("btaddr", "00:00:00:00:00:00", 0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
#define ROOT_DTPATH ""
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
DTNode *node;
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
// Overwrite the serial-number with data from the simplertc fastsim model
|
||||
if (FindNode(0, ROOT_DTPATH, &node)) {
|
||||
propName = "serial-number";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (propSize != 0x20) {
|
||||
dprintf(DEBUG_CRITICAL, "serial-number property size 0x%x (expected 0x20)\n", propSize);
|
||||
return -1;
|
||||
}
|
||||
uint64_t *serial = (uint64_t *)propData;
|
||||
serial[0] = *(volatile uint64_t *)0x20f050040;
|
||||
serial[1] = *(volatile uint64_t *)0x20f050048;
|
||||
serial[2] = *(volatile uint64_t *)0x20f050050;
|
||||
serial[3] = *(volatile uint64_t *)0x20f050058;
|
||||
}
|
||||
}
|
||||
|
||||
// Overwrite the region-info with data from the simplertc fastsim model
|
||||
if (FindNode(0, ROOT_DTPATH, &node)) {
|
||||
propName = "region-info";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (propSize != 0x20) {
|
||||
dprintf(DEBUG_CRITICAL, "region-info property size 0x%x (expected 0x20)\n", propSize);
|
||||
return -1;
|
||||
}
|
||||
uint64_t *region = (uint64_t *)propData;
|
||||
region[0] = *(volatile uint64_t *)0x20f050060;
|
||||
region[1] = *(volatile uint64_t *)0x20f050068;
|
||||
region[2] = *(volatile uint64_t *)0x20f050070;
|
||||
region[3] = *(volatile uint64_t *)0x20f050078;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if !WITH_HW_POWER
|
||||
|
||||
bool power_needs_precharge(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
void power_cancel_buttonwait(void)
|
||||
{
|
||||
}
|
||||
|
||||
bool power_do_chargetrap(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
bool power_is_suspended(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
void power_will_resume(void)
|
||||
{
|
||||
}
|
||||
|
||||
bool power_has_usb(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
int power_read_dock_id(unsigned *id)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
bool power_get_diags_dock(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
u_int32_t power_get_boot_battery_level(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int power_get_nvram(u_int8_t key, u_int8_t *data)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int power_set_nvram(u_int8_t key, u_int8_t data)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int power_set_soc_voltage(unsigned mv, int override)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
bool force_usb_power = false;
|
||||
|
||||
void power_set_usb_state(bool configured, bool suspended)
|
||||
{
|
||||
}
|
||||
|
||||
int power_backlight_enable(u_int32_t backlight_level)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* ! WITH_HW_POWER */
|
||||
@@ -0,0 +1,272 @@
|
||||
/*
|
||||
* Copyright (C) 2011-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* Pin configuration for FPGA */
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
/* Port 0 */
|
||||
CFG_DISABLED, // TST_CLKOUT ->
|
||||
CFG_DISABLED, // WDOG ->
|
||||
CFG_IN, // GPIO0 -> MENU_KEY (REQUEST_DFU2)
|
||||
CFG_IN, // GPIO1 -> HOLD_KEY (REQUEST_DFU1)
|
||||
CFG_DISABLED, // GPIO2 ->
|
||||
CFG_DISABLED, // GPIO3 ->
|
||||
CFG_DISABLED, // GPIO4 ->
|
||||
CFG_DISABLED, // GPIO5 ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED, // GPIO6 ->
|
||||
CFG_DISABLED, // GPIO7 ->
|
||||
CFG_DISABLED, // GPIO8 ->
|
||||
CFG_DISABLED, // GPIO9 ->
|
||||
CFG_DISABLED, // GPIO10 ->
|
||||
CFG_DISABLED, // GPIO11 ->
|
||||
CFG_DISABLED, // GPIO12 ->
|
||||
CFG_DISABLED, // GPIO13 ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // GPIO14 ->
|
||||
CFG_DISABLED, // GPIO15 ->
|
||||
CFG_DISABLED, // GPIO16 -> BOARD_ID[3]
|
||||
CFG_DISABLED, // GPIO17 ->
|
||||
CFG_DISABLED, // GPIO18 -> BOOT_CONFIG[0]
|
||||
CFG_DISABLED, // GPIO19 ->
|
||||
CFG_DISABLED, // GPIO20 ->
|
||||
CFG_DISABLED, // GPIO21 ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED, // UART1_TXD ->
|
||||
CFG_DISABLED, // UART1_RXD ->
|
||||
CFG_DISABLED, // UART1_RTSN ->
|
||||
CFG_DISABLED, // UART1_CTSN ->
|
||||
CFG_DISABLED, // UART2_TXD ->
|
||||
CFG_DISABLED, // UART2_RXD ->
|
||||
CFG_DISABLED, // UART2_RTSN ->
|
||||
CFG_DISABLED, // UART2_CTSN ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED, // UART3_TXD ->
|
||||
CFG_DISABLED, // UART3_RXD ->
|
||||
CFG_DISABLED, // UART3_RTSN ->
|
||||
CFG_DISABLED, // UART3_CTSN ->
|
||||
CFG_DISABLED, // UART5_RXD ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // UART4_TXD ->
|
||||
CFG_DISABLED, // UART4_RXD ->
|
||||
CFG_DISABLED, // UART4_RTSN ->
|
||||
CFG_DISABLED, // UART4_CTSN ->
|
||||
CFG_DISABLED, // SPI1_SCLK ->
|
||||
CFG_DISABLED, // SPI1_MOSI ->
|
||||
CFG_DISABLED, // SPI1_MISO ->
|
||||
CFG_DISABLED, // SPI1_SSIN ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0, // SPI0_SCLK -> SPI0_SCLK/BOARD_ID[0]
|
||||
CFG_FUNC0, // SPI0_MOSI -> SPI0_MOSI/BOARD_ID[1]
|
||||
CFG_FUNC0, // SPI0_MISO -> SPI0_MISO/BOARD_ID[2]
|
||||
CFG_OUT_1, // SPI0_SSIN ->
|
||||
CFG_DISABLED, // SPI2_SCLK ->
|
||||
CFG_DISABLED, // SPI2_MOSI ->
|
||||
CFG_DISABLED, // SPI2_MISO ->
|
||||
CFG_DISABLED, // SPI2_SSIN ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // I2C0_SDA ->
|
||||
CFG_DISABLED, // I2C0_SCL ->
|
||||
CFG_DISABLED, // I2C1_SDA ->
|
||||
CFG_DISABLED, // I2C1_SCL ->
|
||||
CFG_DISABLED, // ISP0_SDA ->
|
||||
CFG_DISABLED, // ISP0_SCL ->
|
||||
CFG_DISABLED, // ISP1_SDA ->
|
||||
CFG_DISABLED, // ISP1_SCL ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // SENSOR0_RST ->
|
||||
CFG_DISABLED, // SENSOR0_CLK ->
|
||||
CFG_DISABLED, // SENSOR0_XSHUTDOWN ->
|
||||
CFG_DISABLED, // SENSOR0_ISTRB ->
|
||||
CFG_DISABLED, // SENSOR1_RST ->
|
||||
CFG_DISABLED, // SENSOR1_CLK ->
|
||||
CFG_DISABLED, // SENSOR1_XSHUTDOWN ->
|
||||
CFG_DISABLED, // SENSOR1_ISTRB ->
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // SPI3_MOSI ->
|
||||
CFG_DISABLED, // SPI3_MISO ->
|
||||
CFG_DISABLED, // SPI3_SCLK ->
|
||||
CFG_DISABLED, // SPI3_SSIN ->
|
||||
CFG_DISABLED, // I2C2_SDA ->
|
||||
CFG_DISABLED, // I2C2_SCL ->
|
||||
CFG_DISABLED, // GPIO22 ->
|
||||
CFG_DISABLED, // GPIO23 ->
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // GPIO24 ->
|
||||
CFG_DISABLED, // GPIO25 -> BOOT_CONFIG[1]
|
||||
CFG_IN, // GPIO26 -> FORCE_DFU
|
||||
CFG_DISABLED, // GPIO27 -> DFU_STATUS
|
||||
CFG_DISABLED, // GPIO28 -> BOOT_CONFIG[2]
|
||||
CFG_DISABLED, // GPIO29 -> BOOT_CONFIG[3]
|
||||
CFG_DISABLED, // GPIO30 ->
|
||||
CFG_DISABLED, // GPIO31 ->
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // GPIO32 ->
|
||||
CFG_DISABLED, // GPIO33 ->
|
||||
CFG_DISABLED, // GPIO34 ->
|
||||
CFG_DISABLED, // GPIO35 ->
|
||||
CFG_DISABLED, // GPIO36 ->
|
||||
CFG_DISABLED, // GPIO37 ->
|
||||
CFG_DISABLED, // GPIO38 ->
|
||||
CFG_DISABLED, // GPIO39 ->
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // SOCHOT0 ->
|
||||
CFG_DISABLED, // SOCHOT1 ->
|
||||
CFG_FUNC0, // UART0_TXD ->
|
||||
CFG_FUNC0, // UART0_RXD ->
|
||||
CFG_DISABLED, // DWI_DI ->
|
||||
CFG_DISABLED, // DWI_D0 ->
|
||||
CFG_DISABLED, // DWI_CLK ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED, // I2S0_LRCK ->
|
||||
CFG_DISABLED, // I2S0_BCLK ->
|
||||
CFG_DISABLED, // I2S0_DOUT ->
|
||||
CFG_DISABLED, // I2S0_DIN ->
|
||||
CFG_DISABLED, // I2S1_MCK ->
|
||||
CFG_DISABLED, // I2S1_LRCK ->
|
||||
CFG_DISABLED, // I2S1_BCLK ->
|
||||
CFG_DISABLED, // I2S1_DOUT ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // I2S1_DIN ->
|
||||
CFG_DISABLED, // I2S2_LRCK ->
|
||||
CFG_DISABLED, // I2S2_BCLK ->
|
||||
CFG_DISABLED, // I2S2_DOUT ->
|
||||
CFG_DISABLED, // I2S2_DIN ->
|
||||
CFG_DISABLED, // I2S3_MCK ->
|
||||
CFG_DISABLED, // I2S3_LRCK ->
|
||||
CFG_DISABLED, // I2S3_BCLK ->
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED, // I2S3_DOUT ->
|
||||
CFG_DISABLED, // I2S3_DIN ->
|
||||
CFG_DISABLED, // I2S4_LRCK ->
|
||||
CFG_DISABLED, // I2S4_BCLK ->
|
||||
CFG_DISABLED, // I2S4_DOUT ->
|
||||
CFG_DISABLED, // I2S4_DIN ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // TMR32_PWM0 ->
|
||||
CFG_DISABLED, // TMR32_PWM1 ->
|
||||
CFG_DISABLED, // TMR32_PWM2 ->
|
||||
CFG_DISABLED, // SIO_7816UART0_SDA ->
|
||||
CFG_DISABLED, // SIO_7816UART0_SCL ->
|
||||
CFG_DISABLED, // SIO_7816UART0_RST ->
|
||||
CFG_DISABLED, // SIO_7816UART1_SDA ->
|
||||
CFG_DISABLED, // SIO_7816UART1_SCL ->
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // SIO_7816UART0_RST ->
|
||||
CFG_DISABLED, // UART6_TXD ->
|
||||
CFG_DISABLED, // UART6_RXD ->
|
||||
CFG_DISABLED, // I2C3_SDA ->
|
||||
CFG_DISABLED, // I2C3_SCL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED, // EPD_HPD ->
|
||||
CFG_DISABLED, // I2S0_MCK ->
|
||||
CFG_DISABLED, // I2S2_MCK ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
return gpio_default_cfg;
|
||||
}
|
||||
@@ -0,0 +1,31 @@
|
||||
# Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_MED \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=0 \
|
||||
TARGET_VID0_CLK_CFG=0x86100000 \
|
||||
DISPLAY_IPHONE_TUNABLES=1 \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
AMP_CALIBRATION_SKIP=1 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_GPU=1 \
|
||||
WITH_TARGET_AMC_PARAMS=1 \
|
||||
WITH_TARGET_AMP_PARAMS=1 \
|
||||
WIFI_DTPATH=\"arm-io/wlan\"
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_ADBE_SETTINGS_H
|
||||
#define __TARGET_ADBE_SETTINGS_H
|
||||
|
||||
static struct adbe_v2_tuneable adbe_tuneables[] =
|
||||
{
|
||||
{
|
||||
.name = "default",
|
||||
.adbe0_vblank_pos_vbi_pulse = 0x000e,
|
||||
.adbe0_vblank_clk_gate_wakeup = 0x000e,
|
||||
.adbe0_vblank_clk_gate_idle = 0x0000,
|
||||
.adbe0_vblank_busy_finish = 2,
|
||||
.adbe0_tunable_mode_ctrl = (DBEMODECNTL_DPB_BUSY_MASK | \
|
||||
DBEMODECNTL_DYN_CLK_GATE_ENABLE | \
|
||||
DBEMODECNTL_BLK_CLK_GATE_ENABLE),
|
||||
.adbe0_aap_support = 1,
|
||||
.adbe0_aap_format_control_reg1 = (AAP_FORMAT_CONTROL_REG1_AUTOPOS | AAP_FORMAT_CONTROL_REG1_RSVD(8) | AAP_FORMAT_CONTROL_REG1_VS_POL),
|
||||
},
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_ASPNANDCONFIG_H
|
||||
#define __TARGET_ASPNANDCONFIG_H
|
||||
|
||||
//MLC devices
|
||||
#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_ERASE_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_READ_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
|
||||
//TLC devices
|
||||
#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
|
||||
// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
|
||||
#define ASPNAND_INDIRECTION_MEMORY (2*1024*1024)
|
||||
#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_GPIODEF_H
|
||||
#define __TARGET_GPIODEF_H
|
||||
|
||||
/* iphone7,x specific gpio -> pin mappings */
|
||||
|
||||
#include <platform/gpio.h>
|
||||
|
||||
/* define target-specific gpios in a generic fashion here. */
|
||||
|
||||
/* Board Revision */
|
||||
#define GPIO_BOARD_REV0 GPIO( 9, 2) // 74 : GPIO[34]
|
||||
#define GPIO_BOARD_REV1 GPIO( 9, 1) // 73 : GPIO[35]
|
||||
#define GPIO_BOARD_REV2 GPIO( 9, 0) // 72 : GPIO[36]
|
||||
#define GPIO_BOARD_REV3 GPIO( 8, 7) // 71 : GPIO[37]
|
||||
|
||||
/* Display reset */
|
||||
#define GPIO_LCD_RST GPIO(0, 1) // 1 : ULPI_STP -> AP_TO_LCM_RESET_L
|
||||
#define GPIO_LCD_RST_POLARITY (0) // active low
|
||||
|
||||
/* D2186 watchdog tickle, 'KEEPACT' */
|
||||
#define GPIO_WDOG_TICKLE GPIO(13, 3) // 107 : GPIO[19] -> AP_TO_PMU_KEEPACT
|
||||
|
||||
/* which IICs to initialize */
|
||||
#define IICS_MASK (1)
|
||||
|
||||
#define TRISTAR_IIC_BUS (0)
|
||||
#define DISPLAY_PMU_IIC_BUS (0)
|
||||
|
||||
#define POWER_GPIO_HVR_RESET_L (5)
|
||||
|
||||
#endif /* ! __TARGET_GPIODEF_H */
|
||||
@@ -0,0 +1,115 @@
|
||||
#ifndef __TARGET_POWERCONFIG_H
|
||||
#define __TARGET_POWERCONFIG_H
|
||||
|
||||
/* configuration per target */
|
||||
|
||||
#define PMU_IIC_BUS 0
|
||||
|
||||
/* this configuration is very PMU specific and must be included exactly once in power.c */
|
||||
#ifdef POWERCONFIG_PMU_SETUP
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
|
||||
{
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kD2186_ACTIVE3, 0xAE }, // Current OTP enables LDO{1,2,3,4,5,7}, disable LDO4.
|
||||
{ PMU_IIC_BUS, kD2186_ACTIVE6, 0x37 }, // enable BUCK3_SW1, BUCK3_SW2, BUCK3_SW3, BUCK4_SW1, BUCK4_SW2
|
||||
{ PMU_IIC_BUS, kD2186_ACTIVE3, 0xBE }, // enable LDO4 along with LDO{1,2,3,5,7}
|
||||
|
||||
{ PMU_IIC_BUS, kD2186_BUCK1_VSEL, 0x80 }, // rdar://14689066 TODO: remove when not necessary
|
||||
|
||||
{ PMU_IIC_BUS, kD2186_OUT_32K, 0x49 }, // enable OUT32 clock
|
||||
|
||||
{ PMU_IIC_BUS, kD2186_BUCK6_VSEL, 0x26 }, // <rdar://problem/15038492> N56/T133 Adi PMU: Change default voltage on BUCK6 to 2.0375 V
|
||||
|
||||
{ PMU_IIC_BUS, kD2186_LDO9_VSEL, 0x44 }, // <rdar://problem/15047684> N56/T133/N61 Front Camera AVDD Voltage setting from PMU
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_warm_init[] =
|
||||
{
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_cold_init[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kD2186_GPIO1_CONF1, 0x88 }, // CHG_TO_PMU_INT_L In, L Low, No Wake, PU
|
||||
{ PMU_IIC_BUS, kD2186_GPIO1_CONF2, 0x72 }, // CHG_TO_PMU_INT_L POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO2_CONF1, 0x8a }, // BB_TO_PMU_HOST_WAKE_L In, L Low, Wake, PU
|
||||
{ PMU_IIC_BUS, kD2186_GPIO2_CONF2, 0x72 }, // BB_TO_PMU_HOST_WAKE_L POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO3_CONF1, 0x01 }, // PMU_TO_BB_RST_R_L Out 0, Low , Push-Pull
|
||||
{ PMU_IIC_BUS, kD2186_GPIO3_CONF2, 0x12 }, // PMU_TO_BB_RST_R_L VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO4_CONF1, 0x82 }, // TRISTAR_TO_AP_INT In, L High, Wake, PU
|
||||
{ PMU_IIC_BUS, kD2186_GPIO4_CONF2, 0x72 }, // TRISTAR_TO_AP_INT POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO5_CONF1, 0x83 }, // STOCKHOLM_TO_PMU_HOST_WAKE_L In, L High, Wake, PD
|
||||
{ PMU_IIC_BUS, kD2186_GPIO5_CONF2, 0x72 }, // STOCKHOLM_TO_PMU_HOST_WAKE_L POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO6_CONF1, 0x01 }, // PMU_TO_OSCAR_RESET_CLK_32K_L Out 0, Push-Pull
|
||||
{ PMU_IIC_BUS, kD2186_GPIO6_CONF2, 0x12 }, // PMU_TO_OSCAR_RESET_CLK_32K_L VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO7_CONF1, 0x83 }, // WLAN_TO_PMU_HOST_WAKE In, L High, Wake, PD
|
||||
{ PMU_IIC_BUS, kD2186_GPIO7_CONF2, 0x72 }, // WLAN_TO_PMU_HOST_WAKE POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO8_CONF1, 0xA2 }, // CODEC_TO_PMU_MIKEY_INT_L In, Any Edge, Wake, PU
|
||||
{ PMU_IIC_BUS, kD2186_GPIO8_CONF2, 0x12 }, // CODEC_TO_PMU_MIKEY_INT_L VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO9_CONF1, 0x01 }, // PMU_TO_BT_REG_ON_R Out 0, Push-Pull
|
||||
{ PMU_IIC_BUS, kD2186_GPIO9_CONF2, 0x12 }, // PMU_TO_BT_REG_ON_R VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO10_CONF1, 0x92 }, // BT_TO_PMU_HOST_WAKE In, R Edge, Wake, Push-Pull
|
||||
{ PMU_IIC_BUS, kD2186_GPIO10_CONF2, 0x72 }, // BT_TO_PMU_HOST_WAKE Disabled
|
||||
// { PMU_IIC_BUS, kD2186_GPIO11_CONF1, 0x01 }, // PMU_TO_WLAN_REG_ON_R Out 0, Push-Pull
|
||||
{ PMU_IIC_BUS, kD2186_GPIO11_CONF1, 0x03 }, // PMU_TO_WLAN_REG_ON_R Out 1, Push-Pull (FIXME! rdar://14957372)
|
||||
{ PMU_IIC_BUS, kD2186_GPIO11_CONF2, 0x12 }, // PMU_TO_WLAN_REG_ON_R VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO12_CONF1, 0x08}, // AP_TO_I2C0_SCL Out, nReset, PU
|
||||
{ PMU_IIC_BUS, kD2186_GPIO12_CONF2, 0x72 }, // AP_TO_I2C0_SCL POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO13_CONF1, 0x83 }, // OSCAR_TO_PMU_HOST_WAKE In, In, L High, Wake, PD
|
||||
{ PMU_IIC_BUS, kD2186_GPIO13_CONF2, 0x72 }, // OSCAR_TO_PMU_HOST_WAKE POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO14_CONF1, 0x91 }, // NC
|
||||
{ PMU_IIC_BUS, kD2186_GPIO14_CONF2, 0x72 }, // POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO15_CONF1, 0x01 }, // PMU_TO_BB_VBUS_DET Out 0, Low, Push-Pull
|
||||
{ PMU_IIC_BUS, kD2186_GPIO15_CONF2, 0x02 }, // PMU_TO_BB_VBUS_DET VCC_MAIN
|
||||
{ PMU_IIC_BUS, kD2186_GPIO16_CONF1, 0x91 }, // NC
|
||||
{ PMU_IIC_BUS, kD2186_GPIO16_CONF2, 0x72 }, // POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO17_CONF1, 0x9A }, // WLAN_TO_PMU_PCIE_WAKE_L In, F Edge, Wake, PU
|
||||
{ PMU_IIC_BUS, kD2186_GPIO17_CONF2, 0x12 }, // WLAN_TO_PMU_PCIE_WAKE_L VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO18_CONF1, 0x01 }, // PMU_TO_ACC_SW_ON Out 0, Low, Push-Pull
|
||||
{ PMU_IIC_BUS, kD2186_GPIO18_CONF2, 0x12 }, // PMU_TO_ACC_SW_ON VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO19_CONF1, 0x93 }, // NC_HALL1_TO_PMU_WAKE In, R Edge, Wake, PD
|
||||
{ PMU_IIC_BUS, kD2186_GPIO19_CONF2, 0x12 }, // NC_HALL1_TO_PMU_WAKE VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO20_CONF1, 0x93 }, // NC_HALL2_TO_PMU_WAKE In, R Edge, Wake, PD
|
||||
{ PMU_IIC_BUS, kD2186_GPIO20_CONF2, 0x12 }, // NC_HALL2_TO_PMU_WAKE VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO21_CONF1, 0x91 }, // NC
|
||||
{ PMU_IIC_BUS, kD2186_GPIO21_CONF2, 0x72 }, // POR
|
||||
|
||||
// TODO: configure debounce for WAS kD2045_GPIO_DEB2,kD2045_GPIO_DEB5,kD2045_GPIO_DEB6?
|
||||
|
||||
{ PMU_IIC_BUS, kD2186_BUCK_DWI_CTRL0, 0x07 }, // enable DWI for BUCK0, BUCK1, BUCK2
|
||||
{ PMU_IIC_BUS, kD2186_SYS_CTRL2, 0x11 }, // enable HIB_32kHz (for WIFI/BT) and DWI
|
||||
|
||||
// TODO: verify
|
||||
{ PMU_IIC_BUS, kD2186_ACT_TO_HIB_DLY, 0x03 }, // set ACT_TO_HIB_DLY to 3 (6ms)
|
||||
};
|
||||
|
||||
static const struct core_rails_struct soc_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2186_BUCK2_VSEL }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct cpu_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2186_BUCK0_VSEL }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct ram_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2186_BUCK5_VSEL }
|
||||
};
|
||||
|
||||
#endif /* POWERCONFIG_PMU_SETUP */
|
||||
|
||||
#define NO_BATTERY_VOLTAGE 2700
|
||||
#define MIN_BOOT_BATTERY_VOLTAGE 3600
|
||||
#define TARGET_BOOT_BATTERY_VOLTAGE 3700
|
||||
#define TARGET_BOOT_BATTERY_CAPACITY 50
|
||||
#define PRECHARGE_BACKLIGHT_LEVEL 824
|
||||
#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
|
||||
|
||||
#define ACC_PWR_LDO (6)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define one debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (0)
|
||||
|
||||
#define HDQGAUGE_SERIAL_PORT (5)
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define UART_OVERSAMPLE_OVERRIDE (11)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,298 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/power.h>
|
||||
#if (APPLICATION_IBOOT && PRODUCT_IBOOT)
|
||||
#include <drivers/displayport/displayport.h>
|
||||
#include <drivers/displayport.h>
|
||||
#endif
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <lib/paint.h>
|
||||
#include <lib/syscfg.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <target.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
|
||||
#define E86_AP_BOARD_ID (0xE) // AP board ID
|
||||
#define E86_DEV_BOARD_ID (0xF) // DEV board ID
|
||||
|
||||
#define E86_BOARD_REV (0xF) //(0xF)
|
||||
|
||||
// Combined Board Id/Board Revision
|
||||
typedef enum {
|
||||
BOARD_TYPE_UNKNOWN = 0,
|
||||
BOARD_TYPE_E86_PROTO1 = 1
|
||||
} board_type;
|
||||
|
||||
static uint32_t gpio_board_rev;
|
||||
static bool gpio_board_rev_valid;
|
||||
|
||||
static uint32_t e86_get_board_rev(void);
|
||||
static board_type e86_get_board_type(void);
|
||||
|
||||
#if WITH_HW_DISPLAY_DISPLAYPORT
|
||||
static dp_t dp_link_config = {
|
||||
.mode = 1,
|
||||
.type = 0,
|
||||
.min_link_rate = 0xa,
|
||||
.max_link_rate = 0xa,
|
||||
.lanes = 4,
|
||||
.ssc = 0,
|
||||
.alpm = 0,
|
||||
.vrr_enable = 0,
|
||||
.vrr_on = 0,
|
||||
.fast_link_training = false,
|
||||
};
|
||||
#endif
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 1);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
|
||||
static uint32_t e86_get_board_rev (void)
|
||||
{
|
||||
if (!gpio_board_rev_valid) {
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV3, GPIO_PDN);
|
||||
|
||||
spin(100); // Wait 100us
|
||||
|
||||
gpio_board_rev =
|
||||
(gpio_read(GPIO_BOARD_REV3) << 3) |
|
||||
(gpio_read(GPIO_BOARD_REV2) << 2) |
|
||||
(gpio_read(GPIO_BOARD_REV1) << 1) |
|
||||
(gpio_read(GPIO_BOARD_REV0) << 0);
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_DFLT);
|
||||
|
||||
gpio_board_rev_valid = true;
|
||||
}
|
||||
|
||||
return gpio_board_rev;
|
||||
}
|
||||
|
||||
static board_type e86_get_board_type (void)
|
||||
{
|
||||
static board_type board_type = BOARD_TYPE_UNKNOWN;
|
||||
|
||||
if (board_type != BOARD_TYPE_UNKNOWN) {
|
||||
dprintf(DEBUG_INFO, "%s: board type: %d\n", __func__, board_type);
|
||||
return board_type;
|
||||
}
|
||||
|
||||
uint32_t board_id = platform_get_board_id();
|
||||
uint32_t board_rev = e86_get_board_rev();
|
||||
|
||||
dprintf(DEBUG_INFO, "%s: board id: %d, rev: %d\n",
|
||||
__func__, board_id, board_rev);
|
||||
|
||||
if (target_config_ap()) {
|
||||
if (E86_AP_BOARD_ID == board_id) {
|
||||
if (E86_BOARD_REV == board_rev) {
|
||||
return (BOARD_TYPE_E86_PROTO1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
panic("Unknown/unsupported board id/rev combination: 0x%x/0x%x",
|
||||
board_id, board_rev);
|
||||
|
||||
return (BOARD_TYPE_UNKNOWN);
|
||||
}
|
||||
|
||||
static void e86_reset_hoover (bool reset)
|
||||
{
|
||||
power_set_gpio(POWER_GPIO_HVR_RESET_L, 1, !reset);
|
||||
}
|
||||
|
||||
static void target_fixup_pmu(void)
|
||||
{
|
||||
#if WITH_HW_POWER
|
||||
int pmu_set_data(int dev, uint16_t reg, uint8_t byte, bool do_confirm);
|
||||
int pmu_get_data(int dev, uint16_t reg, uint8_t *byte);
|
||||
|
||||
int rc;
|
||||
uint8_t val;
|
||||
bool fix_ana_trim = false;
|
||||
|
||||
rc = pmu_get_data(0, 0x1, &val); // read PMU.OTP version
|
||||
|
||||
if (rc < 0) {
|
||||
dprintf(DEBUG_CRITICAL, "PMU: cannot read OTP Version (%d)\n", rc);
|
||||
} else {
|
||||
dprintf(DEBUG_INFO, "%s: PMU OTP ver: %x\n", __func__, val);
|
||||
|
||||
if (val < 0x0d) {
|
||||
rc = pmu_get_data(0, 0x01d7, &val); // read kD2186_BUCK6_ANA_TRIM4
|
||||
|
||||
if (rc < 0) {
|
||||
dprintf(DEBUG_INFO, "PMU: cannot read "
|
||||
"kD2186_BUCK6_ANA_TRIM4 (%d)\n", rc);
|
||||
} else {
|
||||
fix_ana_trim = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
dprintf(DEBUG_INFO, "%s: fix_ana_trim: %d\n", __func__, fix_ana_trim);
|
||||
|
||||
rc = pmu_set_data(0, 0x7000, 0x1d, 0); // test mode
|
||||
|
||||
if (rc < 0) {
|
||||
dprintf(DEBUG_INFO, "PMU: cannot enter test mode (%d)\n", rc);
|
||||
} else {
|
||||
// <rdar://problem/16775541> Remove N56 EVT iBoot Overwrites for PMU
|
||||
// to set high gain mode for kD2186_BUCK6_ANA_TRIM4 0x02 has to be
|
||||
// OR'd in to preserve exiting bits
|
||||
if (fix_ana_trim) {
|
||||
// merge in high gain mode
|
||||
rc = pmu_set_data(0, 0x01d7, ( val | 0x02 ), 1);
|
||||
|
||||
if (rc < 0) {
|
||||
dprintf(DEBUG_INFO, "cannot change "
|
||||
"kD2186_BUCK6_ANA_TRIM4 (%d)\n", rc);
|
||||
}
|
||||
}
|
||||
|
||||
// <rdar://problem/16871166> N61/12A265: All wakes appended with
|
||||
// "button4"
|
||||
rc = pmu_set_data(0, 0x0443, 0x35, 1);
|
||||
|
||||
if (rc < 0) {
|
||||
dprintf(DEBUG_INFO, "cannot change button4 (%d)\n", rc);
|
||||
}
|
||||
|
||||
rc = pmu_set_data(0, 0x7000, 0x00, 0);
|
||||
|
||||
if (rc < 0) {
|
||||
panic("PMU: cannot exit test mode (%d)", rc);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_early_init (void)
|
||||
{
|
||||
#if PRODUCT_LLB || PRODUCT_IBSS
|
||||
dprintf(DEBUG_INFO, "%s: chip rev: %d, fuse: %d\n", __func__,
|
||||
chipid_get_chip_revision(), chipid_get_fuse_revision());
|
||||
|
||||
target_fixup_pmu();
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_late_init (void)
|
||||
{
|
||||
clock_gate(CLK_UART7, 0);
|
||||
|
||||
#if WITH_HW_DISPLAY_DISPLAYPORT
|
||||
displayport_init(&dp_link_config);
|
||||
e86_reset_hoover(false);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_init (void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_quiesce_hardware (void)
|
||||
{
|
||||
dprintf(DEBUG_INFO, "%s ...\n", __func__);
|
||||
}
|
||||
|
||||
void target_poweroff (void)
|
||||
{
|
||||
dprintf(DEBUG_INFO, "%s ...\n", __func__);
|
||||
}
|
||||
|
||||
int target_bootprep (enum boot_target target)
|
||||
{
|
||||
dprintf(DEBUG_INFO, "%s ...\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover (void)
|
||||
{
|
||||
return platform_get_request_dfu2() && power_has_usb();
|
||||
}
|
||||
|
||||
bool target_should_poweron (bool *cold_button_boot)
|
||||
{
|
||||
#if WITH_HW_POWER
|
||||
if (power_get_boot_flag() == kPowerBootFlagColdButton) {
|
||||
*cold_button_boot = true;
|
||||
}
|
||||
#else
|
||||
*cold_button_boot = false;
|
||||
#endif // WITH_HW_POWER
|
||||
|
||||
return (!*cold_button_boot || platform_get_request_dfu1());
|
||||
}
|
||||
|
||||
bool target_should_poweroff (bool at_boot)
|
||||
{
|
||||
return (platform_get_request_dfu1() && (!at_boot || !power_has_usb()));
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle (void)
|
||||
{
|
||||
uint32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
dprintf(DEBUG_INFO, "%s ...\n", __func__);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
void * target_get_display_configuration(void)
|
||||
{
|
||||
#if WITH_HW_DISPLAY_DISPLAYPORT
|
||||
return ((void *)(&dp_link_config));
|
||||
#else
|
||||
return (NULL);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if WITH_ENV
|
||||
void target_setup_default_environment (void)
|
||||
{
|
||||
dprintf(DEBUG_INFO, "%s ...\n", __func__);
|
||||
|
||||
// boot-device is set in platform's init.c
|
||||
env_set("wifiaddr", "7E:77:77:77:77:77", 0);
|
||||
env_set("display-timing", "720p-e86", 0);
|
||||
env_set("adbe-tunables", "default", 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
int target_update_device_tree (void)
|
||||
{
|
||||
|
||||
dprintf(DEBUG_INFO, "%s ...\n", __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif // WITH_DEVICETREE
|
||||
@@ -0,0 +1,316 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: rev 1v0
|
||||
I/O Spreadsheet tracker: <rdar://problem/16391334> E86: IO Spreadsheet Tracker
|
||||
Conversion command: csvtopinconfig.py --soc fiji --copyright 2014 --radar '<rdar://problem/16391334> E86: IO Spreadsheet Tracker' <filename>
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
|
||||
static const uint32_t pinconfig_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED, // 0 : ULPI_DIR ->
|
||||
CFG_DISABLED, // 1 : ULPI_STP ->
|
||||
CFG_DISABLED, // 2 : ULPI_NXT ->
|
||||
CFG_DISABLED, // 3 : ULPI_DATA[7] ->
|
||||
CFG_DISABLED, // 4 : ULPI_DATA[6] ->
|
||||
CFG_DISABLED, // 5 : ULPI_DATA[5] ->
|
||||
CFG_DISABLED, // 6 : ULPI_DATA[4] ->
|
||||
CFG_DISABLED, // 7 : ULPI_CLK ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED, // 8 : ULPI_DATA[3] ->
|
||||
CFG_DISABLED, // 9 : ULPI_DATA[2] ->
|
||||
CFG_DISABLED, // 10 : ULPI_DATA[1] ->
|
||||
CFG_DISABLED, // 11 : ULPI_DATA[0] ->
|
||||
CFG_DISABLED, // 12 : SPI1_SCLK ->
|
||||
CFG_DISABLED, // 13 : SPI1_MOSI ->
|
||||
CFG_DISABLED, // 14 : SPI1_MISO ->
|
||||
CFG_DISABLED, // 15 : SPI1_SSIN ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_IN | PULL_UP, // 32 : GPIO[11] -> SYS_BTN_MENU_L
|
||||
CFG_IN | PULL_UP, // 33 : GPIO[12] -> SYS_BTN_HOLD_L
|
||||
CFG_DISABLED, // 34 : I2S3_MCK ->
|
||||
CFG_DISABLED, // 35 : I2S3_LRCK ->
|
||||
CFG_DISABLED, // 36 : I2S3_BCLK ->
|
||||
CFG_DISABLED, // 37 : I2S3_DOUT ->
|
||||
CFG_DISABLED, // 38 : I2S3_DIN ->
|
||||
CFG_DISABLED, // 39 : CLK32K_OUT ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 40 : PCIE_CLKREQ0_N -> GMAC_CLKREQ_L
|
||||
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 41 : PCIE_CLKREQ1_N -> WLAN_PCIE_CLKREQ_L
|
||||
CFG_DISABLED, // 42 : NAND_SYS_CLK ->
|
||||
CFG_DISABLED, // 43 : GPIO[0] ->
|
||||
CFG_DISABLED, // 44 : GPIO[1] ->
|
||||
CFG_IN | PULL_UP, // 45 : GPIO[2] -> SYS_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 46 : GPIO[3] -> SYS_BTN_VOL_DN_L
|
||||
CFG_DISABLED, // 47 : GPIO[4] ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED, // 48 : GPIO[5] ->
|
||||
CFG_DISABLED, // 49 : GPIO[6] ->
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 50 : GPIO[7] -> WLAN_BT_DEV_WAKE
|
||||
CFG_DISABLED, // 51 : GPIO[14] ->
|
||||
CFG_DISABLED, // 52 : GPIO[16] -> DUT_BOARD_ID3
|
||||
CFG_DISABLED, // 53 : GPIO[17] ->
|
||||
CFG_DISABLED, // 54 : GPIO[18] -> DUT_BOOT_CFG0
|
||||
CFG_DISABLED, // 55 : GPIO[20] ->
|
||||
|
||||
/* Port 7 */
|
||||
CFG_IN | PULL_DOWN, // 56 : GPIO[21] -> HOOVER_IRQ
|
||||
CFG_DISABLED, // 57 : UART5_RTXD ->
|
||||
CFG_DISABLED, // 58 : UART8_TXD ->
|
||||
CFG_DISABLED, // 59 : UART8_RXD ->
|
||||
CFG_DISABLED, // 60 : SPI0_SCLK -> DUT_BOARD_ID0
|
||||
CFG_DISABLED, // 61 : SPI0_MOSI -> DUT_BOARD_ID1
|
||||
CFG_DISABLED, // 62 : SPI0_MISO -> DUT_BOARD_ID2
|
||||
CFG_DISABLED, // 63 : SPI0_SSIN ->
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 64 : I2C2_SDA -> GMAC_SMB_DATA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 65 : I2C2_SCL -> GMAC_SMB_CLK
|
||||
CFG_DISABLED, // 66 : GPIO[22] ->
|
||||
CFG_DISABLED, // 67 : GPIO[23] ->
|
||||
CFG_DISABLED, // 68 : GPIO[25] -> DUT_BOOT_CFG1
|
||||
CFG_DISABLED, // 69 : GPIO[28] -> DUT_BOOT_CFG2
|
||||
CFG_DISABLED, // 70 : GPIO[29] -> DUT_BOARD_ID4
|
||||
CFG_DISABLED, // 71 : GPIO[34] -> DUT_BOARD_REV3
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // 72 : GPIO[35] -> DUT_BOARD_REV2
|
||||
CFG_DISABLED, // 73 : GPIO[36] -> DUT_BOARD_REV1
|
||||
CFG_DISABLED, // 74 : GPIO[37] -> DUT_BOARD_REV0
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 75 : GPIO[39]/ PCIE_PERST0_N -> GMAC_PERST_L
|
||||
CFG_DISABLED, // 76 : GPIO[42] ->
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 77 : GPIO[43]/PCIE_PERST1_N -> WLAN_PCIE_RST_L
|
||||
CFG_DISABLED, // 78 : DISP_VSYNC ->
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 79 : UART0_TXD -> TRISTAR_UART1_TX
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 80 : UART0_RXD -> TRISTAR_UART1_RX
|
||||
CFG_DISABLED, // 81 : TMR32_PWM0 ->
|
||||
CFG_DISABLED, // 82 : TMR32_PWM1 ->
|
||||
CFG_DISABLED, // 83 : TMR32_PWM2 ->
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW, // 84 : UART6_TXD -> TRISTAR_UART0_TX
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 85 : UART6_RXD -> TRISTAR_UART0_RX
|
||||
CFG_DISABLED, // 86 : I2C3_SDA -> HUB0_NON_REM1_SDA
|
||||
CFG_DISABLED, // 87 : I2C3_SCL -> HUB0_CFG_SEL0_SCL
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 12 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 96 : I2C0_SDA -> PMU_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 97 : I2C0_SCL -> PMU_SCL
|
||||
CFG_DISABLED, // 98 : GPIO[38] ->
|
||||
CFG_DISABLED, // 99 : UART2_TXD -> << CPLD MUX >>
|
||||
CFG_DISABLED, // 100 : UART2_RXD -> << CPLD MUX >>
|
||||
CFG_DISABLED, // 101 : UART2_RTSN -> << CPLD MUX >>
|
||||
CFG_DISABLED, // 102 : UART2_CTSN -> << CPLD MUX >>
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 103 : DWI_DO -> PMU_DWI_DI
|
||||
|
||||
/* Port 13 */
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 104 : DWI_CLK -> PMU_DWI_CLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 105 : WDOG -> PMU_RESET_IN1
|
||||
CFG_IN | PULL_UP, // 106 : GPIO[13] -> PMU_IRQ_L
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 107 : GPIO[19] -> PMU_KEEPACT
|
||||
CFG_DISABLED, // 108 : GPIO[26] -> DUT_FORCE_DFU
|
||||
CFG_DISABLED, // 109 : GPIO[27] -> DUT_DFU_STATUS
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 110 : SOCHOT0 -> PMU_PRE_UVLO
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 111 : SOCHOT1 -> PMU_RESET_IN3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 113 : TST_CLKOUT -> << SMA CONN >>
|
||||
CFG_DISABLED, // 114 : GPIO[8] ->
|
||||
CFG_DISABLED, // 115 : GPIO[9] -> WLAN_JTAG_SWCLK
|
||||
CFG_DISABLED, // 116 : GPIO[10] -> WLAN_JTAG_SWDIO
|
||||
CFG_DISABLED, // 117 : GPIO[15] ->
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 118 : UART4_TXD -> WLAN_UART_RXD
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 119 : UART4_RXD -> WLAN_UART_TXD
|
||||
|
||||
/* Port 15 */
|
||||
CFG_OUT_1 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 120 : UART4_RTSN -> WLAN_UART_CTS_L
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 121 : UART4_CTSN -> WLAN_UART_RTS_L
|
||||
CFG_DISABLED, // 122 : SPI3_MOSI ->
|
||||
CFG_DISABLED, // 123 : SPI3_MISO ->
|
||||
CFG_DISABLED, // 124 : SPI3_SCLK ->
|
||||
CFG_DISABLED, // 125 : SPI3_SSIN ->
|
||||
CFG_DISABLED, // 126 : GPIO[24] ->
|
||||
CFG_DISABLED, // 127 : GPIO[30] -> << CPLD SPARE >>
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED, // 128 : GPIO[31] -> << CPLD SPARE >>
|
||||
CFG_DISABLED, // 129 : GPIO[32] -> << CPLD SPARE >>
|
||||
CFG_DISABLED, // 130 : GPIO[33] -> << CPLD SPARE >>
|
||||
CFG_IN, // 131 : GPIO[40] -> SYS_BTN_RING_L
|
||||
CFG_DISABLED, // 132 : GPIO[41] ->
|
||||
CFG_IN | PULL_DOWN, // 133 : I2S4_MCK -> TRISTAR_INT
|
||||
CFG_DISABLED, // 134 : I2S4_LRCK ->
|
||||
CFG_DISABLED, // 135 : I2S4_BCLK ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // 136 : I2S4_DOUT ->
|
||||
CFG_DISABLED, // 137 : I2S4_DIN ->
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 138 : I2C1_SDA -> HOOVER_I2C_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 139 : I2C1_SCL -> HOOVER_I2C_SCL
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 160 : I2S0_LRCK -> HOOVER_MCA_LRCK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 161 : I2S0_BCLK -> HOOVER_MCA_BCLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 162 : I2S0_DOUT -> HOOVER_MCA_D0
|
||||
CFG_DISABLED, // 163 : I2S0_DIN ->
|
||||
CFG_DISABLED, // 164 : I2S1_MCK ->
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 165 : I2S1_LRCK -> WLAN_BT_I2S_LRCK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 166 : I2S1_BCLK -> WLAN_BT_I2S_BCLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 167 : I2S1_DOUT -> WLAN_BT_I2S_DIN
|
||||
|
||||
/* Port 21 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 168 : I2S1_DIN -> WLAN_B2_I2S_DOUT
|
||||
CFG_DISABLED, // 169 : I2S2_LRCK ->
|
||||
CFG_DISABLED, // 170 : I2S2_BCLK ->
|
||||
CFG_DISABLED, // 171 : I2S2_DOUT ->
|
||||
CFG_DISABLED, // 172 : I2S2_DIN ->
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 173 : UART1_TXD -> WLAN_BT_UART_RXD
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 174 : UART1_RXD -> WLAN_BT_UART_TXD
|
||||
CFG_OUT_1 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 175 : UART1_RTSN -> WLAN_BT_UART_CTS_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 176 : UART1_CTSN -> WLAN_BT_UART_RTS_L
|
||||
CFG_FUNC0 | PULL_DOWN, // 177 : EDP_HPD -> HOOVER_HPD_OUT
|
||||
CFG_DISABLED, // 178 : UART3_TXD ->
|
||||
CFG_DISABLED, // 179 : UART3_RXD ->
|
||||
CFG_DISABLED, // 180 : UART3_RTSN ->
|
||||
CFG_DISABLED, // 181 : UART3_CTSN ->
|
||||
CFG_DISABLED, // 182 : SPI2_SCLK ->
|
||||
CFG_DISABLED, // 183 : SPI2_MOSI ->
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED, // 184 : SPI2_MISO ->
|
||||
CFG_DISABLED, // 185 : SPI2_SSIN ->
|
||||
CFG_DISABLED, // 186 : ISP0_SDA ->
|
||||
CFG_DISABLED, // 187 : ISP0_SCL ->
|
||||
CFG_DISABLED, // 188 : ISP1_SDA ->
|
||||
CFG_DISABLED, // 189 : ISP1_SCL ->
|
||||
CFG_DISABLED, // 190 : SENSOR0_RST ->
|
||||
CFG_DISABLED, // 191 : SENSOR0_CLK ->
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED, // 192 : SENSOR0_XSHUTDOWN ->
|
||||
CFG_DISABLED, // 193 : SENSOR0_ISTRB ->
|
||||
CFG_DISABLED, // 194 : ISP_UART0_TXD ->
|
||||
CFG_DISABLED, // 195 : ISP_UART0_RXD ->
|
||||
CFG_DISABLED, // 196 : SENSOR1_RST ->
|
||||
CFG_DISABLED, // 197 : SENSOR1_CLK ->
|
||||
CFG_DISABLED, // 198 : SENSOR1_XSHUTDOWN ->
|
||||
CFG_DISABLED, // 199 : SENSOR1_ISTRB ->
|
||||
|
||||
/* Port 25 */
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 200 : UART7_TXD -> WLAN_GPIO_1_WLAN_DEV_WAKE
|
||||
CFG_DISABLED, // 201 : UART7_RXD ->
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 202 : I2S0_MCK -> HOOVER_MCA_MCK
|
||||
CFG_DISABLED, // 203 : I2S2_MCK ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
};
|
||||
|
||||
struct pinconfig_map {
|
||||
uint32_t board_id;
|
||||
uint32_t board_id_mask;
|
||||
const uint32_t *pinconfigs[GPIOC_COUNT];
|
||||
};
|
||||
|
||||
static const struct pinconfig_map cfg_map[] = {
|
||||
{ 0, 0, { pinconfig_0 } },
|
||||
};
|
||||
|
||||
const uint32_t * target_get_default_gpio_cfg(int gpioc)
|
||||
{
|
||||
static const struct pinconfig_map *selected_map = NULL;
|
||||
|
||||
if (selected_map == NULL) {
|
||||
uint32_t board_id = platform_get_board_id();
|
||||
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
|
||||
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
|
||||
selected_map = &cfg_map[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (selected_map == NULL)
|
||||
panic("no default pinconfig for board id %u", board_id);
|
||||
}
|
||||
|
||||
ASSERT(gpioc < GPIOC_COUNT);
|
||||
return selected_map->pinconfigs[gpioc];
|
||||
}
|
||||
@@ -0,0 +1,44 @@
|
||||
# Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2186=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_V2 \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=CHIPID_SOC_VOLTAGE_VMIN \
|
||||
TARGET_VID0_CLK_CFG=0x86100000 \
|
||||
TARGET_CORE_PHY_TMR_LPCLK_CFG=0x00330087 \
|
||||
TARGET_CORE_PHY_TMR_CFG=0x256f0000 \
|
||||
TARGET_PHY_STOP_WAIT_TIME=0x28 \
|
||||
WITH_HW_HOOVER=1 \
|
||||
DISPLAY_APPLE_TV_TUNABLES=1 \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_SOC=2 \
|
||||
BUCK_GPU=1 \
|
||||
DP_DTPATH=\"arm-io/displayport\" \
|
||||
DPPHY_DTPATH=\"arm-io/lpdp-phy\" \
|
||||
WIFI_DTPATH=\"arm-io/uart4/wlan\" \
|
||||
BT_DTPATH=\"arm-io/uart1/bluetooth\"
|
||||
|
||||
ifeq ($(PRODUCT),iBoot)
|
||||
OPTIONS += \
|
||||
WITH_HW_DISPLAY_DISPLAYPORT=1
|
||||
endif
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_GPIODEF_H
|
||||
#define __TARGET_GPIODEF_H
|
||||
|
||||
/* E88 specific gpio -> pin mappings */
|
||||
|
||||
#include <platform/gpio.h>
|
||||
|
||||
/* define target-specific gpios in a generic fashion here. */
|
||||
#define GPIO_RINGER_AB GPIO( 0, 4)
|
||||
|
||||
/* Board Revision */
|
||||
#define GPIO_BOARD_REV0 GPIO( 4, 5) // EHCI_PORT_PWR0
|
||||
#define GPIO_BOARD_REV1 GPIO( 4, 6) // EHCI_PORT_PWR1
|
||||
#define GPIO_BOARD_REV2 GPIO( 4, 7) // EHCI_PORT_PWR2
|
||||
#define GPIO_BOARD_REV3 GPIO( 2, 1) // GPIO17
|
||||
|
||||
/* which IICs to initialize */
|
||||
#define IICS_MASK (5)
|
||||
|
||||
#define TRISTAR_IIC_BUS (0)
|
||||
|
||||
/* D1881 watchdog tickle, 'KEEPACT' */
|
||||
#define GPIO_WDOG_TICKLE GPIO(2, 3)
|
||||
|
||||
#endif /* ! __TARGET_GPIODEF_H */
|
||||
@@ -0,0 +1,92 @@
|
||||
|
||||
// Copyright (C) 2008-2010 Apple, Inc. All rights reserved.
|
||||
//
|
||||
// This document is the property of Apple, Inc.
|
||||
// It is considered confidential and proprietary.
|
||||
//
|
||||
// This document may not be reproduced or transmitted in any form,
|
||||
// in whole or in part, without the express written permission of
|
||||
// Apple, Inc.
|
||||
//
|
||||
// NOTE: This is a generated file and should not be hand-edited!
|
||||
//
|
||||
|
||||
// =============================================================================
|
||||
// Nand Geometry Table
|
||||
|
||||
static NandGeometry _nandGeometryTable[] =
|
||||
{
|
||||
};
|
||||
|
||||
// =============================================================================
|
||||
// Nand Timing Table
|
||||
|
||||
static NandTiming _nandTimingTable[] =
|
||||
{
|
||||
};
|
||||
|
||||
#if (defined (AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
|
||||
// =============================================================================
|
||||
// NandChipId Description
|
||||
const NandChipIdDescription _nandChipIdDescriptionTable[] =
|
||||
{
|
||||
};
|
||||
|
||||
// =============================================================================
|
||||
// Nand Description Table
|
||||
|
||||
static const NandDescription _nandDescriptionTable[] =
|
||||
{
|
||||
};
|
||||
const UInt32 _nandDescriptionTableSize = sizeof(_nandDescriptionTable) / sizeof(NandDescription);
|
||||
|
||||
#endif // (defined(AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
|
||||
|
||||
// =============================================================================
|
||||
// Nand Board Support Table
|
||||
|
||||
static NandBoardSupport _nandBoardSupportTable[] =
|
||||
{
|
||||
};
|
||||
|
||||
// =============================================================================
|
||||
// Nand Board Timing Table
|
||||
|
||||
static NandBoardInfo _nandBoardInfo =
|
||||
{
|
||||
/* controlDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
|
||||
/* dataDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
|
||||
/* chipEnableDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
|
||||
|
||||
/* socToNandRiseNanosecs */ 10,
|
||||
/* socToNandFallNanosecs */ 10,
|
||||
/* nandToSocRiseNanosecs */ 10,
|
||||
/* nandToSocFallNanosecs */ 10,
|
||||
|
||||
/* landing map */
|
||||
{
|
||||
0x00000101
|
||||
},
|
||||
|
||||
/* useToggleMode */ TRUE32,
|
||||
/* useDiffDQSMode */ FALSE32,
|
||||
/* useDiffREMode */ FALSE32,
|
||||
/* useVref */ TRUE32,
|
||||
/* useSingleHostChannel */ FALSE32,
|
||||
/* allowSingleChipEnable */ TRUE32
|
||||
};
|
||||
|
||||
static NandFormat _nandFormatPpn =
|
||||
{
|
||||
/* metaPerLogicalPage */ 16,
|
||||
/* validMetaPerLogicalPage */ 16,
|
||||
/* logicalPageSize */ 4096
|
||||
};
|
||||
|
||||
static NandFormat _nandFormatRaw =
|
||||
{
|
||||
/* metaPerLogicalPage */ 12,
|
||||
/* validMetaPerLogicalPage */ 10,
|
||||
/* logicalPageSize */ 0
|
||||
};
|
||||
|
||||
@@ -0,0 +1,130 @@
|
||||
/*
|
||||
* Copyright (C) 2010-2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_POWERCONFIG_H
|
||||
#define __TARGET_POWERCONFIG_H
|
||||
#include <stdbool.h>
|
||||
|
||||
/* configuration per target */
|
||||
|
||||
#define PMU_IIC_BUS 0
|
||||
|
||||
/* this configuration is very PMU specific and must be included exactly once in power.c */
|
||||
#ifdef POWERCONFIG_PMU_SETUP
|
||||
|
||||
/* Matched to D1881B1-OTP-CD-v5 */
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kD1881_LDO1, 0x0D }, // PP3V0_USB 3.15V <rdar://problem/9200307>
|
||||
{ PMU_IIC_BUS, kD1881_LDO2, 0x0A }, // PP1V7_VA_VCP 1.70V
|
||||
{ PMU_IIC_BUS, kD1881_LDO3, 0x0A }, // PP3V0_IMU 3.00V
|
||||
{ PMU_IIC_BUS, kD1881_LDO4, 0x16 }, // PP3V0_OPTICAL 2.90V
|
||||
{ PMU_IIC_BUS, kD1881_LDO5, 0x0A }, // PP3V0_NAND 3.00V
|
||||
{ PMU_IIC_BUS, kD1881_LDO6, 0x10 }, // PP3V3_ACC 3.30V
|
||||
{ PMU_IIC_BUS, kD1881_LDO7, 0x0F }, // PP3V3_VIDEO 3.00V
|
||||
{ PMU_IIC_BUS, kD1881_LDO8, 0x14 }, // PP3V0_USBMUX 3.00V
|
||||
{ PMU_IIC_BUS, kD1881_LDO9, 0x01 }, // PP1V5_CAM_AVDD 1.30V
|
||||
{ PMU_IIC_BUS, kD1881_LDO10, 0x01 }, // PP2V8_CAM_AVDD 2.55V
|
||||
{ PMU_IIC_BUS, kD1881_LDO11, 0x02 }, // 1.80V
|
||||
{ PMU_IIC_BUS, kD1881_LDO12, 0x10 }, // PP1V1 1.00V
|
||||
{ PMU_IIC_BUS, kDIALOG_LDO_CONTROL, 0x00 }, // no bypass
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kD1881_ACTIVE1, 0xBD }, // Everything except VBUCK1, LDO2
|
||||
{ PMU_IIC_BUS, kD1881_ACTIVE2, 0xBB }, // LDO4, LDO5, LDO7, LDO8, LDO9, LDO11 enabled
|
||||
{ PMU_IIC_BUS, kD1881_ACTIVE3, 0x2F }, // LDO12
|
||||
{ PMU_IIC_BUS, kD1881_ACTIVE4, 0xE0 }, // CPU1V8 & CPU1V2 on, WDIG off
|
||||
{ PMU_IIC_BUS, kD1881_LCM_CONTROL1, 0x02 }, // PP5V1_GRAPE_VDDH 5.10V
|
||||
{ PMU_IIC_BUS, kD1881_LCM_CONTROL2, 0x0E }, // PP5V7_LCD_AVDDH 5.70V
|
||||
{ PMU_IIC_BUS, kD1881_LCM_CONTROL3, 0x00 }, // BB_VBUS_DET 5.00V
|
||||
{ PMU_IIC_BUS, kD1881_LCM_BST_CONTROL, 0x1A }, // PP6V3_LCM_VBOOST 6.30V
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_warm_init[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kDIALOG_ADC_CONTROL, kDIALOG_ADC_CONTROL_DEFAULTS },
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_cold_init[] =
|
||||
{
|
||||
/* Note: the following differences from OTP are intentional:
|
||||
- GPIO 5: Enable CLK32k
|
||||
- GPIO 8: Enable Codec (Mikey) Wake
|
||||
- GPIO 7: Enable WiFi Wake
|
||||
- GPIO 10: Enable Wake amd Pull-Up
|
||||
*/
|
||||
{ PMU_IIC_BUS, kD1881_SYS_GPIO_1, 0xB9 }, // CLK32K_GRAPE In, R Edge, No Wake, No PU
|
||||
// Clock is enabled by AppleARMFunction default
|
||||
{ PMU_IIC_BUS, kD1881_SYS_GPIO_2, 0x09 }, // BB_WAKE_AP -- NC
|
||||
{ PMU_IIC_BUS, kD1881_SYS_GPIO_3, 0x09 }, // BB_PMU_FET_ON -- NC
|
||||
{ PMU_IIC_BUS, kD1881_SYS_GPIO_4, 0xBA }, // TRISTAR_INT In, R Edge, Wake, No PU
|
||||
{ PMU_IIC_BUS, kD1881_SYS_GPIO_5, 0x49 }, // CLK32K_WIFI Out 0, Push-Pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD1881_SYS_GPIO_6, 0x09 }, // BATTERY_SWI -- NC
|
||||
{ PMU_IIC_BUS, kD1881_SYS_GPIO_7, 0xBB }, // WLAN_HOST_WAKE In, R Edge, Wake, PD, No PU
|
||||
{ PMU_IIC_BUS, kD1881_SYS_GPIO_8, 0xEA }, // CODEC_HOST_WAKE_L In, Any Edge, Wake, PU, VBUCK3
|
||||
{ PMU_IIC_BUS, kD1881_SYS_GPIO_9, 0x09 }, // BT_REG_ON Out 1, Push-Pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD1881_SYS_GPIO_10, 0xBA }, // BT_HOST_WAKE In, R Edge, Wake, PU
|
||||
{ PMU_IIC_BUS, kD1881_SYS_GPIO_11, 0x09 }, // WIFI_REG_ON Out 0, Push-Pull, VBUCK3
|
||||
|
||||
{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB1, 0x12 },
|
||||
{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB2, 0x02 },
|
||||
{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB3, 0x12 },
|
||||
{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB4, 0x00 },
|
||||
{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB5, 0x12 },
|
||||
{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB6, 0x02 },
|
||||
|
||||
{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2, 0x10 }, // enable HIB_32kHz (for WIFI/BT); DWI disabled
|
||||
|
||||
// <rdar://problem/12192156> turn off buck4 negative current limit
|
||||
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x01 }, // set bank1
|
||||
{ PMU_IIC_BUS, kD1881_TEST_MODE, 0x01 }, // enter test mode
|
||||
{ PMU_IIC_BUS, 0xCB, 0x23 }, // turn off negative current limit
|
||||
{ PMU_IIC_BUS, kD1881_TEST_MODE, 0x00 }, // exit test mode
|
||||
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x00 }, // set bank0
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_backlight_enable[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_ISET, 0xC8 }, // 50% value from OS
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_ISET2, 0x01 },
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, // enable LED Power
|
||||
(kDIALOG_WLED_CONTROL_WLED_ENABLE2 | kDIALOG_WLED_CONTROL_WLED_ENABLE1 | kDIALOG_WLED_CONTROL_WLED_RAMP_EN) }
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_backlight_disable[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, 0x0 } // disable LED power
|
||||
};
|
||||
|
||||
static const struct core_rails_struct soc_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kDIALOG_BUCK0 }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct cpu_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kDIALOG_BUCK2 }
|
||||
};
|
||||
|
||||
#endif /* POWERCONFIG_PMU_SETUP */
|
||||
|
||||
#define NO_BATTERY_VOLTAGE 2700
|
||||
#define MIN_BOOT_BATTERY_VOLTAGE 3600
|
||||
#define TARGET_BOOT_BATTERY_VOLTAGE 3700
|
||||
#define TARGET_BOOT_BATTERY_CAPACITY 50
|
||||
#define PRECHARGE_BACKLIGHT_LEVEL 824
|
||||
#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
|
||||
|
||||
#define ACC_PWR_LDO (6)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define two debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (1)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_USBCONFIG_H
|
||||
#define __TARGET_USBCONFIG_H
|
||||
|
||||
#ifdef USBPHY_UOTGTUNE1
|
||||
|
||||
#undef USBPHY_UOTGTUNE1
|
||||
#define USBPHY_UOTGTUNE1 (0x749)
|
||||
|
||||
#endif /* USBPHY_UOTGTUNE1 */
|
||||
|
||||
#ifdef USBPHY_UOTGTUNE2
|
||||
|
||||
#undef USBPHY_UOTGTUNE2
|
||||
#define USBPHY_UOTGTUNE2 (0x2FF3)
|
||||
|
||||
#endif /* USBPHY_UOTGTUNE2 */
|
||||
|
||||
|
||||
#endif /* __TARGET_USBCONFIG_H */
|
||||
@@ -0,0 +1,239 @@
|
||||
/*
|
||||
* Copyright (C) 2011-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/flash_nor.h>
|
||||
#include <drivers/iic.h>
|
||||
#include <drivers/power.h>
|
||||
#include <lib/devicetree.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <lib/syscfg.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <sys.h>
|
||||
#include <sys/boot.h>
|
||||
#include <sys/menu.h>
|
||||
#include <sys/task.h>
|
||||
#include <target.h>
|
||||
#include <target/powerconfig.h>
|
||||
|
||||
static u_int32_t e88_get_board_rev(void);
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
switch (target) {
|
||||
case BOOT_DARWIN:
|
||||
case BOOT_DARWIN_RESTORE:
|
||||
case BOOT_DIAGS:
|
||||
break;
|
||||
|
||||
default:
|
||||
; // do nothing
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return platform_get_request_dfu2() && power_has_usb();
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
#if WITH_HW_POWER
|
||||
if (power_get_boot_flag() == kPowerBootFlagColdButton) *cold_button_boot = true;
|
||||
#else
|
||||
*cold_button_boot = false;
|
||||
#endif
|
||||
|
||||
return !*cold_button_boot || platform_get_request_dfu1();
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
u_int32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
env_set("boot-device", "nand0", 0);
|
||||
env_set("boot-partition", "0", 0);
|
||||
env_set("boot-path", "/System/Library/Caches/com.apple.kernelcaches/kernelcache", 0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static bool gpio_board_rev_valid;
|
||||
static u_int32_t gpio_board_rev;
|
||||
|
||||
static u_int32_t e88_get_board_rev(void)
|
||||
{
|
||||
if (!gpio_board_rev_valid) {
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV3, GPIO_PDN);
|
||||
|
||||
spin(100); // Wait 100us
|
||||
|
||||
uint32_t brd_rev3_inverted = (gpio_read(GPIO_BOARD_REV3) ? 0UL : 1UL);
|
||||
gpio_board_rev =
|
||||
(brd_rev3_inverted << 3) |
|
||||
(gpio_read(GPIO_BOARD_REV2) << 2) |
|
||||
(gpio_read(GPIO_BOARD_REV1) << 1) |
|
||||
(gpio_read(GPIO_BOARD_REV0) << 0);
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_DFLT);
|
||||
|
||||
gpio_board_rev_valid = true;
|
||||
}
|
||||
|
||||
return gpio_board_rev;
|
||||
}
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
DTNode *node;
|
||||
uint32_t propSize, propCnt;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
// Update the DWI node with the actual voltages
|
||||
if (FindNode(0, "arm-io/dwi", &node)) {
|
||||
propName = "voltages-buck2";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propCnt = propSize / sizeof(u_int32_t);
|
||||
platform_get_cpu_voltages(propCnt, propData);
|
||||
platform_convert_voltages(2, propCnt, propData);
|
||||
}
|
||||
propName = "voltages-buck0";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propCnt = propSize / sizeof(u_int32_t);
|
||||
platform_get_soc_voltages(propCnt, propData);
|
||||
platform_convert_voltages(0, propCnt, propData);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// Update the gyro calibration data
|
||||
if (FindNode(0, "arm-io/i2c2/gyro", &node)) {
|
||||
propName = "low-temp-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LTGO', propData, propSize);
|
||||
}
|
||||
propName = "high-temp-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('HTGO', propData, propSize);
|
||||
}
|
||||
propName = "gyro-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GSCl', propData, propSize);
|
||||
}
|
||||
propName = "gyro-temp-table";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GYTT', propData, propSize);
|
||||
}
|
||||
propName = "gyro-interrupt-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GICl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update accelerometer calibration data
|
||||
if (FindNode(0, "arm-io/i2c2/accelerometer", &node)) {
|
||||
propName = "low-temp-accel-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LTAO', propData, propSize);
|
||||
}
|
||||
propName = "accel-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ASCl', propData, propSize);
|
||||
}
|
||||
propName = "accel-interrupt-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('AICl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Updte the speaker calibration data
|
||||
if (FindNode(0, "arm-io/i2c0/audio-speaker", &node)) {
|
||||
propName = "speaker-rdc";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('SRdc', propData, propSize);
|
||||
}
|
||||
propName = "speaker-config";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
uint8_t vpbr;
|
||||
if (syscfgCopyDataForTag('VPBR', &vpbr, sizeof(vpbr)) == 1) {
|
||||
((uint8_t *)propData)[12] = (((uint8_t *)propData)[12] & ~0x1f) | (vpbr & 0x1f);
|
||||
}
|
||||
uint8_t vbst;
|
||||
if (syscfgCopyDataForTag('VBST', &vbst, sizeof(vbst)) == 1) {
|
||||
((uint8_t *)propData)[16] = vbst;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,580 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: rev 0v4
|
||||
I/O Spreadsheet tracker: <rdar://problem/19464609> E88: IO Spreadsheet Tracker
|
||||
Conversion command: csvtopinconfig.py --soc h4a --radar '<rdar://problem/19464609> E88: IO Spreadsheet Tracker' --copyright 2014 <filename>
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
|
||||
static const uint32_t pinconfig_ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN | PULL_UP, // 0 : GPIO[0] -> MENU_KEY_L
|
||||
CFG_IN | PULL_UP, // 1 : GPIO[1] -> HOLD_KEY_L
|
||||
CFG_IN | PULL_UP, // 2 : GPIO[2] -> VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 3 : GPIO[3] -> VOL_DWN_L
|
||||
CFG_OUT_1, // 4 : GPIO[4] -> ACC_UHPM_EN
|
||||
CFG_DISABLED | PULL_DOWN, // 5 : GPIO[5] -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 6 : GPIO[6] -> NC
|
||||
CFG_OUT_0 | PULL_DOWN, // 7 : GPIO[7] -> BT_WAKE
|
||||
|
||||
/* Port 1 */
|
||||
CFG_OUT_0, // 8 : GPIO[8] -> WLAN_HSIC_AP_RDY
|
||||
CFG_IN | PULL_DOWN, // 9 : GPIO[9] -> WLAN_HSIC_DEV_RDY
|
||||
CFG_DISABLED, // 10 : GPIO[10] -> NC
|
||||
CFG_DISABLED, // 11 : GPIO[11] -> NC
|
||||
CFG_OUT_0, // 12 : GPIO[12] -> EN_8VBOOST
|
||||
CFG_IN | PULL_UP, // 13 : GPIO[13] -> PMU_IRQ_L
|
||||
CFG_OUT_0, // 14 : GPIO[14] -> WLAN_HSIC_RESUME
|
||||
CFG_OUT_1, // 15 : GPIO[15] -> SNAP_MCU_RESET_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_IN, // 16 : GPIO[16] -> BRD_ID3
|
||||
CFG_IN, // 17 : GPIO[17] -> BRD_REV3
|
||||
CFG_IN | PULL_DOWN, // 18 : GPIO[18] -> BOOT_CFG0
|
||||
CFG_OUT_0, // 19 : GPIO[19] -> KEEPACTIVE
|
||||
CFG_IN, // 20 : GPIO[20] -> TRISTAR_INT
|
||||
CFG_IN | PULL_UP, // 21 : GPIO[21] -> SNAP_INT_L
|
||||
CFG_OUT_0 | PULL_DOWN, // 22 : GPIO[22] -> SNAP_ID0
|
||||
CFG_IN | PULL_DOWN, // 23 : GPIO[23] -> SNAP_ID1
|
||||
|
||||
/* Port 3 */
|
||||
CFG_OUT_0 | PULL_DOWN, // 24 : GPIO[24] -> PS_5VBOOST_L
|
||||
CFG_IN | PULL_DOWN, // 25 : GPIO[25] -> BOOT_CFG1
|
||||
CFG_IN | PULL_DOWN, // 26 : GPIO[26] -> FORCE_DFU
|
||||
CFG_OUT_0, // 27 : GPIO[27] -> DUT_DFU_STATUS
|
||||
CFG_IN, // 28 : GPIO[28] -> BOOT_CFG2
|
||||
CFG_IN, // 29 : GPIO[29] -> BOOT_CFG3
|
||||
CFG_OUT_0 | PULL_DOWN, // 30 : GPIO[30] -> CODEC_RESET_L
|
||||
CFG_IN, // 31 : GPIO[31] -> VBUS_FAULT_L
|
||||
|
||||
/* Port 4 */
|
||||
CFG_OUT_0, // 32 : GPIO[32] -> USB_SW_EN
|
||||
CFG_IN | PULL_DOWN, // 33 : GPIO[33] -> GYRO_INT1
|
||||
CFG_IN, // 34 : GPIO[34] -> ACC_UHPM_POK
|
||||
CFG_OUT_1, // 35 : GPIO[35] -> EN_5VBOOST
|
||||
CFG_IN, // 36 : GPIO[36] -> ACCEL_INT2_L
|
||||
CFG_IN, // 37 : EHCI_PORT_PWR[0] -> BRD_REV[0]
|
||||
CFG_IN, // 38 : EHCI_PORT_PWR[1] -> BRD_REV[1]
|
||||
CFG_IN, // 39 : EHCI_PORT_PWR[2] -> BRD_REV[2]
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0, // 40 : UART1_TXD -> AP_DBG_UART_TXD
|
||||
CFG_FUNC0, // 41 : UART1_RXD -> AP_DBG_UART_RXD
|
||||
CFG_DISABLED | PULL_DOWN, // 42 : UART1_RTSN -> NC
|
||||
CFG_IN, // 43 : UART1_CTSN -> SNAP_DET_L
|
||||
CFG_FUNC0, // 44 : UART2_TXD -> ACC_UART_TXD
|
||||
CFG_FUNC0, // 45 : UART2_RXD -> ACC_UART_RXD
|
||||
CFG_DISABLED | PULL_DOWN, // 46 : UART2_RTSN -> NC
|
||||
CFG_OUT_1, // 47 : UART2_CTSN -> USB_HUB_RST_L
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0, // 48 : UART3_TXD -> BT_UART_RXD
|
||||
CFG_FUNC0, // 49 : UART3_RXD -> BT_UART_TXD
|
||||
CFG_FUNC0, // 50 : UART3_RTSN -> BT_UART_CTS_L
|
||||
CFG_FUNC0, // 51 : UART3_CTSN -> BT_UART_RTS_L
|
||||
CFG_FUNC0, // 52 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0, // 53 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0, // 54 : I2C1_SDA -> SNAP_I2C_SDA
|
||||
CFG_FUNC0, // 55 : I2C1_SCL -> SNAP_I2C_SCL
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0, // 56 : ISP0_SDA -> I2C_CAM_REAR_SDA_1V8
|
||||
CFG_FUNC0, // 57 : ISP0_SCL -> I2C_CAM_REAR_SCL_1V8
|
||||
CFG_DISABLED | PULL_DOWN, // 58 : ISP1_SDA -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 59 : ISP1_SCL -> NC
|
||||
CFG_FUNC0 | PULL_DOWN, // 60 : MIPI_VSYNC -> SNAP_MIPI_VSYNC
|
||||
CFG_FUNC0 | PULL_DOWN, // 61 : TMR32_PWM0 -> GYRO_INT2
|
||||
CFG_FUNC0 | PULL_DOWN, // 62 : TMR32_PWM1 -> ACCEL_INT1_L
|
||||
CFG_FUNC0, // 63 : TMR32_PWM2 -> WLAN_TIMESYNC
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // 64 : SWI_DATA -> NC
|
||||
CFG_FUNC0, // 65 : DWI_DI -> DWI_AP_DI
|
||||
CFG_FUNC0, // 66 : DWI_DO -> DWI_AP_DO
|
||||
CFG_FUNC0, // 67 : DWI_CLK -> DWI_AP_CLK
|
||||
CFG_OUT_0, // 68 : SENSOR0_RST -> CAM_REAR_SHUTDOWN_L
|
||||
CFG_FUNC0, // 69 : SENSOR0_CLK -> CAM_REAR_CLK
|
||||
CFG_DISABLED | PULL_DOWN, // 70 : SENSOR1_RST -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 71 : SENSOR1_CLK -> NC
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED | PULL_DOWN, // 72 : ISP0_PRE_FLASH -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 73 : ISP0_FLASH -> NC
|
||||
CFG_DISABLED, // 74 : ISP1_PRE_FLASH -> NC
|
||||
CFG_DISABLED, // 75 : ISP1_FLASH -> NC
|
||||
CFG_FUNC0, // 76 : I2S0_MCK -> CODEC_MCLK
|
||||
CFG_FUNC0, // 77 : I2S0_LRCK -> CODEC_LRCLK
|
||||
CFG_FUNC0, // 78 : I2S0_BCLK -> CODEC_BCLK
|
||||
CFG_DISABLED | PULL_DOWN, // 79 : I2S0_DOUT -> NC
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0, // 80 : I2S0_DIN -> CODEC_TO_DUT_DIN
|
||||
CFG_DISABLED, // 81 : I2S1_MCK -> NC
|
||||
CFG_FUNC0, // 82 : I2S1_LRCK -> BT_PCM_SYNC
|
||||
CFG_FUNC0, // 83 : I2S1_BCLK -> BT_PCM_CLK
|
||||
CFG_FUNC0, // 84 : I2S1_DOUT -> BT_PCM_IN
|
||||
CFG_FUNC0, // 85 : I2S1_DIN -> BT_PCM_OUT
|
||||
CFG_DISABLED, // 86 : I2S2_MCK -> NC
|
||||
CFG_FUNC0, // 87 : I2S2_LRCK -> SPKR_AMP_MCA_FSYNC
|
||||
|
||||
/* Port 11 */
|
||||
CFG_FUNC0, // 88 : I2S2_BCLK -> SPKR_AMP_MCA_BCLK
|
||||
CFG_FUNC0 | PULL_DOWN, // 89 : I2S2_DOUT -> SPKR_AMP_MCA_SDATA
|
||||
CFG_DISABLED, // 90 : I2S2_DIN -> NC
|
||||
CFG_FUNC0, // 91 : I2S3_MCK -> SNAP_I2S_MCLK_H4A
|
||||
CFG_FUNC0, // 92 : I2S3_LRCK -> SNAP_I2S_LRCK
|
||||
CFG_FUNC0, // 93 : I2S3_BCLK -> SNAP_I2S_BCLK
|
||||
CFG_FUNC0, // 94 : I2S3_DOUT -> DUT_DOUT_TO_SNAP_I2S
|
||||
CFG_FUNC0, // 95 : I2S3_DIN -> SNAP_TO_DUT_I2S_DIN
|
||||
|
||||
/* Port 12 */
|
||||
CFG_IN, // 96 : SPI0_SCLK -> BRD_ID0
|
||||
CFG_IN, // 97 : SPI0_MOSI -> BRD_ID1
|
||||
CFG_IN, // 98 : SPI0_MISO -> BRD_ID2
|
||||
CFG_DISABLED, // 99 : SPI0_SSIN -> NC
|
||||
CFG_FUNC0, // 100 : SPI1_SCLK -> SNAP_SPI_CLK
|
||||
CFG_FUNC0, // 101 : SPI1_MOSI -> SNAP_SPI_MOSI
|
||||
CFG_FUNC0, // 102 : SPI1_MISO -> SNAP_SPI_MISO
|
||||
CFG_FUNC0, // 103 : SPI1_SSIN -> SNAP_MCU_SPI_CS_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // 104 : SPI2_SCLK -> NC
|
||||
CFG_DISABLED, // 105 : SPI2_MOSI -> NC
|
||||
CFG_DISABLED, // 106 : SPI2_MISO -> NC
|
||||
CFG_DISABLED, // 107 : SPI2_SSIN -> NC
|
||||
CFG_DISABLED, // 108 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 109 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 110 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 111 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 113 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 114 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 115 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 116 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 117 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 118 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 119 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // 120 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 121 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 122 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 123 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0, // 128 : UART4_TXD -> WLAN_DBG_UART_RXD
|
||||
CFG_FUNC0, // 129 : UART4_RXD -> WLAN_DBG_UART_TXD
|
||||
CFG_DISABLED | PULL_DOWN, // 130 : UART4_RTSN -> NC
|
||||
CFG_IN, // 131 : UART4_CTSN -> PMU_AMUX_AY_CTRL
|
||||
CFG_DISABLED | PULL_DOWN, // 132 : SDIO0_DATA[3] -> SDIO0_DATA[3]
|
||||
CFG_DISABLED | PULL_DOWN, // 133 : SDIO0_DATA[2] -> SDIO0_DATA[2]
|
||||
CFG_DISABLED | PULL_DOWN, // 134 : SDIO0_DATA[1] -> SDIO0_DATA[1]
|
||||
CFG_DISABLED | PULL_DOWN, // 135 : SDIO0_DATA[0] -> SDIO0_DATA[0]
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED | PULL_DOWN, // 136 : SDIO0_CMD -> SDIO0_CMD
|
||||
CFG_DISABLED | PULL_DOWN, // 137 : SDIO0_CLK -> SDIO0_CLK
|
||||
CFG_DISABLED | PULL_DOWN, // 138 : FMI0_CEN[3] -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 139 : FMI0_CEN[2] -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 140 : FMI0_CEN[1] -> NC
|
||||
CFG_FUNC0 | DRIVE_X2, // 141 : FMI0_CEN[0] -> F0CE0_L
|
||||
CFG_FUNC0 | DRIVE_X2, // 142 : FMI0_CLE -> F0CLE
|
||||
CFG_FUNC0 | DRIVE_X2, // 143 : FMI0_ALE -> F0ALE
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0 | DRIVE_X2, // 144 : FMI0_REN -> F0RE_L
|
||||
CFG_FUNC0 | DRIVE_X2, // 145 : FMI0_WEN -> F0WE_L
|
||||
CFG_FUNC0 | DRIVE_X2, // 146 : FMI0_IO[7] -> F0AD<7>
|
||||
CFG_FUNC0 | DRIVE_X2, // 147 : FMI0_IO[6] -> F0AD<6>
|
||||
CFG_FUNC0 | DRIVE_X2, // 148 : FMI0_IO[5] -> F0AD<5>
|
||||
CFG_FUNC0 | DRIVE_X2, // 149 : FMI0_IO[4] -> F0AD<4>
|
||||
CFG_DISABLED, // 150 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 151 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // 152 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 153 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 154 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 155 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 156 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 157 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 158 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 159 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 20 */
|
||||
CFG_FUNC0 | DRIVE_X2, // 160 : FMI0_DQS -> F0DQS
|
||||
CFG_FUNC0 | DRIVE_X2, // 161 : FMI0_IO[3] -> F0AD<3>
|
||||
CFG_FUNC0 | DRIVE_X2, // 162 : FMI0_IO[2] -> F0AD<2>
|
||||
CFG_FUNC0 | DRIVE_X2, // 163 : FMI0_IO[1] -> F0AD<1>
|
||||
CFG_FUNC0 | DRIVE_X2, // 164 : FMI0_IO[0] -> F0AD<0>
|
||||
CFG_DISABLED | PULL_DOWN, // 165 : FMI1_CEN[3] ->
|
||||
CFG_DISABLED | PULL_DOWN, // 166 : FMI1_CEN[2] ->
|
||||
CFG_DISABLED | PULL_DOWN, // 167 : FMI1_CEN[1] ->
|
||||
|
||||
/* Port 21 */
|
||||
CFG_FUNC0 | DRIVE_X2, // 168 : FMI1_CEN[0] -> F1CE0_L
|
||||
CFG_FUNC0 | DRIVE_X2, // 169 : FMI1_CLE -> F1CLE
|
||||
CFG_FUNC0 | DRIVE_X2, // 170 : FMI1_ALE -> F1ALE
|
||||
CFG_FUNC0 | DRIVE_X2, // 171 : FMI1_REN -> F1RE_L
|
||||
CFG_FUNC0 | DRIVE_X2, // 172 : FMI1_WEN -> F1WE_L
|
||||
CFG_FUNC0 | DRIVE_X2, // 173 : FMI1_IO[7] -> F1AD<7>
|
||||
CFG_FUNC0 | DRIVE_X2, // 174 : FMI1_IO[6] -> F1AD<6>
|
||||
CFG_FUNC0 | DRIVE_X2, // 175 : FMI1_IO[5] -> F1AD<5>
|
||||
|
||||
/* Port 22 */
|
||||
CFG_FUNC0 | DRIVE_X2, // 176 : FMI1_IO[4] -> F1AD<4>
|
||||
CFG_FUNC0 | DRIVE_X2, // 177 : FMI1_DQS -> F1DQS
|
||||
CFG_FUNC0 | DRIVE_X2, // 178 : FMI1_IO[3] -> F1AD<3>
|
||||
CFG_FUNC0 | DRIVE_X2, // 179 : FMI1_IO[2] -> F1AD<2>
|
||||
CFG_FUNC0 | DRIVE_X2, // 180 : FMI1_IO[1] -> F1AD<1>
|
||||
CFG_FUNC0 | DRIVE_X2, // 181 : FMI1_IO[0] -> F1AD<0>
|
||||
CFG_DISABLED, // 182 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 183 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED, // 184 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 185 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 186 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 187 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 188 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 189 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 190 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 191 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 24 */
|
||||
CFG_FUNC0, // 192 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0, // 193 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0, // 194 : UART0_TXD -> DUT_TXD
|
||||
CFG_FUNC0 | PULL_DOWN, // 195 : UART0_RXD -> DUT_RXD
|
||||
CFG_DISABLED | PULL_DOWN, // 196 : UART5_RTXD -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 197 : DP_HPD -> GND
|
||||
CFG_FUNC0 | PULL_DOWN, // 198 : TST_CLKOUT -> TST_CLKOUT
|
||||
CFG_DISABLED | PULL_DOWN, // 199 : TST_STPCLK -> GND
|
||||
|
||||
/* Port 25 */
|
||||
CFG_FUNC0, // 200 : WDOG -> H4A_WDOG
|
||||
CFG_DISABLED, // 201 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 202 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 203 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 204 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 205 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 206 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 207 : UNSPECIFIED -> UNSPECIFIED
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN | PULL_UP, // 0 : GPIO[0] -> MENU_KEY_L
|
||||
CFG_IN | PULL_UP, // 1 : GPIO[1] -> HOLD_KEY_L
|
||||
CFG_IN | PULL_UP, // 2 : GPIO[2] -> VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 3 : GPIO[3] -> VOL_DWN_L
|
||||
CFG_OUT_1, // 4 : GPIO[4] -> ACC_UHPM_EN
|
||||
CFG_DISABLED | PULL_DOWN, // 5 : GPIO[5] -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 6 : GPIO[6] -> NC
|
||||
CFG_OUT_0 | PULL_DOWN, // 7 : GPIO[7] -> BT_WAKE
|
||||
|
||||
/* Port 1 */
|
||||
CFG_OUT_0, // 8 : GPIO[8] -> WLAN_HSIC_AP_RDY
|
||||
CFG_IN | PULL_DOWN, // 9 : GPIO[9] -> WLAN_HSIC_DEV_RDY
|
||||
CFG_DISABLED, // 10 : GPIO[10] -> NC
|
||||
CFG_DISABLED, // 11 : GPIO[11] -> NC
|
||||
CFG_OUT_0, // 12 : GPIO[12] -> EN_8VBOOST
|
||||
CFG_IN | PULL_UP, // 13 : GPIO[13] -> PMU_IRQ_L
|
||||
CFG_OUT_0, // 14 : GPIO[14] -> WLAN_HSIC_RESUME
|
||||
CFG_OUT_1, // 15 : GPIO[15] -> SNAP_MCU_RESET_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_IN, // 16 : GPIO[16] -> BRD_ID3
|
||||
CFG_IN, // 17 : GPIO[17] -> BRD_REV3
|
||||
CFG_IN | PULL_DOWN, // 18 : GPIO[18] -> BOOT_CFG0
|
||||
CFG_OUT_0, // 19 : GPIO[19] -> KEEPACTIVE
|
||||
CFG_IN, // 20 : GPIO[20] -> TRISTAR_INT
|
||||
CFG_IN | PULL_UP, // 21 : GPIO[21] -> SNAP_INT_L
|
||||
CFG_OUT_0 | PULL_DOWN, // 22 : GPIO[22] -> SNAP_ID0
|
||||
CFG_IN | PULL_DOWN, // 23 : GPIO[23] -> SNAP_ID1
|
||||
|
||||
/* Port 3 */
|
||||
CFG_OUT_0 | PULL_DOWN, // 24 : GPIO[24] -> PS_5VBOOST_L
|
||||
CFG_IN | PULL_DOWN, // 25 : GPIO[25] -> BOOT_CFG1
|
||||
CFG_IN | PULL_DOWN, // 26 : GPIO[26] -> FORCE_DFU
|
||||
CFG_OUT_0, // 27 : GPIO[27] -> DUT_DFU_STATUS
|
||||
CFG_IN, // 28 : GPIO[28] -> BOOT_CFG2
|
||||
CFG_IN, // 29 : GPIO[29] -> BOOT_CFG3
|
||||
CFG_OUT_0 | PULL_DOWN, // 30 : GPIO[30] -> CODEC_RESET_L
|
||||
CFG_IN, // 31 : GPIO[31] -> VBUS_FAULT_L
|
||||
|
||||
/* Port 4 */
|
||||
CFG_OUT_0, // 32 : GPIO[32] -> USB_SW_EN
|
||||
CFG_IN | PULL_DOWN, // 33 : GPIO[33] -> GYRO_INT1
|
||||
CFG_IN, // 34 : GPIO[34] -> ACC_UHPM_POK
|
||||
CFG_OUT_1, // 35 : GPIO[35] -> EN_5VBOOST
|
||||
CFG_IN, // 36 : GPIO[36] -> ACCEL_INT2_L
|
||||
CFG_IN, // 37 : EHCI_PORT_PWR[0] -> BRD_REV[0]
|
||||
CFG_IN, // 38 : EHCI_PORT_PWR[1] -> BRD_REV[1]
|
||||
CFG_IN, // 39 : EHCI_PORT_PWR[2] -> BRD_REV[2]
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0, // 40 : UART1_TXD -> AP_DBG_UART_TXD
|
||||
CFG_FUNC0, // 41 : UART1_RXD -> AP_DBG_UART_RXD
|
||||
CFG_DISABLED | PULL_DOWN, // 42 : UART1_RTSN -> NC
|
||||
CFG_IN, // 43 : UART1_CTSN -> SNAP_DET_L
|
||||
CFG_FUNC0, // 44 : UART2_TXD -> ACC_UART_TXD
|
||||
CFG_FUNC0, // 45 : UART2_RXD -> ACC_UART_RXD
|
||||
CFG_DISABLED | PULL_DOWN, // 46 : UART2_RTSN -> NC
|
||||
CFG_OUT_1, // 47 : UART2_CTSN -> USB_HUB_RST_L
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0, // 48 : UART3_TXD -> BT_UART_RXD
|
||||
CFG_FUNC0, // 49 : UART3_RXD -> BT_UART_TXD
|
||||
CFG_FUNC0, // 50 : UART3_RTSN -> BT_UART_CTS_L
|
||||
CFG_FUNC0, // 51 : UART3_CTSN -> BT_UART_RTS_L
|
||||
CFG_FUNC0, // 52 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0, // 53 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0, // 54 : I2C1_SDA -> SNAP_I2C_SDA
|
||||
CFG_FUNC0, // 55 : I2C1_SCL -> SNAP_I2C_SCL
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0, // 56 : ISP0_SDA -> I2C_CAM_REAR_SDA_1V8
|
||||
CFG_FUNC0, // 57 : ISP0_SCL -> I2C_CAM_REAR_SCL_1V8
|
||||
CFG_DISABLED | PULL_DOWN, // 58 : ISP1_SDA -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 59 : ISP1_SCL -> NC
|
||||
CFG_FUNC0 | PULL_DOWN, // 60 : MIPI_VSYNC -> SNAP_MIPI_VSYNC
|
||||
CFG_FUNC0 | PULL_DOWN, // 61 : TMR32_PWM0 -> GYRO_INT2
|
||||
CFG_FUNC0 | PULL_DOWN, // 62 : TMR32_PWM1 -> ACCEL_INT1_L
|
||||
CFG_FUNC0, // 63 : TMR32_PWM2 -> WLAN_TIMESYNC
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // 64 : SWI_DATA -> NC
|
||||
CFG_FUNC0, // 65 : DWI_DI -> DWI_AP_DI
|
||||
CFG_FUNC0, // 66 : DWI_DO -> DWI_AP_DO
|
||||
CFG_FUNC0, // 67 : DWI_CLK -> DWI_AP_CLK
|
||||
CFG_OUT_0, // 68 : SENSOR0_RST -> CAM_REAR_SHUTDOWN_L
|
||||
CFG_FUNC0, // 69 : SENSOR0_CLK -> CAM_REAR_CLK
|
||||
CFG_DISABLED | PULL_DOWN, // 70 : SENSOR1_RST -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 71 : SENSOR1_CLK -> NC
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED | PULL_DOWN, // 72 : ISP0_PRE_FLASH -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 73 : ISP0_FLASH -> NC
|
||||
CFG_DISABLED, // 74 : ISP1_PRE_FLASH -> NC
|
||||
CFG_DISABLED, // 75 : ISP1_FLASH -> NC
|
||||
CFG_FUNC0, // 76 : I2S0_MCK -> CODEC_MCLK
|
||||
CFG_FUNC0, // 77 : I2S0_LRCK -> CODEC_LRCLK
|
||||
CFG_FUNC0, // 78 : I2S0_BCLK -> CODEC_BCLK
|
||||
CFG_DISABLED | PULL_DOWN, // 79 : I2S0_DOUT -> NC
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0, // 80 : I2S0_DIN -> CODEC_TO_DUT_DIN
|
||||
CFG_DISABLED, // 81 : I2S1_MCK -> NC
|
||||
CFG_FUNC0, // 82 : I2S1_LRCK -> BT_PCM_SYNC
|
||||
CFG_FUNC0, // 83 : I2S1_BCLK -> BT_PCM_CLK
|
||||
CFG_FUNC0, // 84 : I2S1_DOUT -> BT_PCM_IN
|
||||
CFG_FUNC0, // 85 : I2S1_DIN -> BT_PCM_OUT
|
||||
CFG_DISABLED, // 86 : I2S2_MCK -> NC
|
||||
CFG_FUNC0, // 87 : I2S2_LRCK -> SPKR_AMP_MCA_FSYNC
|
||||
|
||||
/* Port 11 */
|
||||
CFG_FUNC0, // 88 : I2S2_BCLK -> SPKR_AMP_MCA_BCLK
|
||||
CFG_FUNC0 | PULL_DOWN, // 89 : I2S2_DOUT -> SPKR_AMP_MCA_SDATA
|
||||
CFG_DISABLED, // 90 : I2S2_DIN -> NC
|
||||
CFG_FUNC0, // 91 : I2S3_MCK -> SNAP_I2S_MCLK_H4A
|
||||
CFG_FUNC0, // 92 : I2S3_LRCK -> SNAP_I2S_LRCK
|
||||
CFG_FUNC0, // 93 : I2S3_BCLK -> SNAP_I2S_BCLK
|
||||
CFG_FUNC0, // 94 : I2S3_DOUT -> DUT_DOUT_TO_SNAP_I2S
|
||||
CFG_FUNC0, // 95 : I2S3_DIN -> SNAP_TO_DUT_I2S_DIN
|
||||
|
||||
/* Port 12 */
|
||||
CFG_IN, // 96 : SPI0_SCLK -> BRD_ID0
|
||||
CFG_IN, // 97 : SPI0_MOSI -> BRD_ID1
|
||||
CFG_IN, // 98 : SPI0_MISO -> BRD_ID2
|
||||
CFG_DISABLED, // 99 : SPI0_SSIN -> NC
|
||||
CFG_FUNC0, // 100 : SPI1_SCLK -> SNAP_SPI_CLK
|
||||
CFG_FUNC0, // 101 : SPI1_MOSI -> SNAP_SPI_MOSI
|
||||
CFG_FUNC0, // 102 : SPI1_MISO -> SNAP_SPI_MISO
|
||||
CFG_FUNC0, // 103 : SPI1_SSIN -> SNAP_MCU_SPI_CS_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // 104 : SPI2_SCLK -> NC
|
||||
CFG_DISABLED, // 105 : SPI2_MOSI -> NC
|
||||
CFG_DISABLED, // 106 : SPI2_MISO -> NC
|
||||
CFG_DISABLED, // 107 : SPI2_SSIN -> NC
|
||||
CFG_DISABLED, // 108 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 109 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 110 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 111 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 113 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 114 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 115 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 116 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 117 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 118 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 119 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // 120 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 121 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 122 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 123 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0, // 128 : UART4_TXD -> WLAN_DBG_UART_RXD
|
||||
CFG_FUNC0, // 129 : UART4_RXD -> WLAN_DBG_UART_TXD
|
||||
CFG_DISABLED | PULL_DOWN, // 130 : UART4_RTSN -> NC
|
||||
CFG_IN, // 131 : UART4_CTSN -> PMU_AMUX_AY_CTRL
|
||||
CFG_DISABLED | PULL_DOWN, // 132 : SDIO0_DATA[3] -> SDIO0_DATA[3]
|
||||
CFG_DISABLED | PULL_DOWN, // 133 : SDIO0_DATA[2] -> SDIO0_DATA[2]
|
||||
CFG_DISABLED | PULL_DOWN, // 134 : SDIO0_DATA[1] -> SDIO0_DATA[1]
|
||||
CFG_DISABLED | PULL_DOWN, // 135 : SDIO0_DATA[0] -> SDIO0_DATA[0]
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED | PULL_DOWN, // 136 : SDIO0_CMD -> SDIO0_CMD
|
||||
CFG_DISABLED | PULL_DOWN, // 137 : SDIO0_CLK -> SDIO0_CLK
|
||||
CFG_DISABLED | PULL_DOWN, // 138 : FMI0_CEN[3] -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 139 : FMI0_CEN[2] -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 140 : FMI0_CEN[1] -> NC
|
||||
CFG_FUNC0, // 141 : FMI0_CEN[0] -> F0CE0_L
|
||||
CFG_FUNC0, // 142 : FMI0_CLE -> F0CLE
|
||||
CFG_FUNC0, // 143 : FMI0_ALE -> F0ALE
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : FMI0_REN -> F0RE_L
|
||||
CFG_FUNC0, // 145 : FMI0_WEN -> F0WE_L
|
||||
CFG_FUNC0, // 146 : FMI0_IO[7] -> F0AD<7>
|
||||
CFG_FUNC0, // 147 : FMI0_IO[6] -> F0AD<6>
|
||||
CFG_FUNC0, // 148 : FMI0_IO[5] -> F0AD<5>
|
||||
CFG_FUNC0, // 149 : FMI0_IO[4] -> F0AD<4>
|
||||
CFG_DISABLED, // 150 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 151 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // 152 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 153 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 154 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 155 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 156 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 157 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 158 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 159 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 20 */
|
||||
CFG_FUNC0, // 160 : FMI0_DQS -> F0DQS
|
||||
CFG_FUNC0, // 161 : FMI0_IO[3] -> F0AD<3>
|
||||
CFG_FUNC0, // 162 : FMI0_IO[2] -> F0AD<2>
|
||||
CFG_FUNC0, // 163 : FMI0_IO[1] -> F0AD<1>
|
||||
CFG_FUNC0, // 164 : FMI0_IO[0] -> F0AD<0>
|
||||
CFG_DISABLED | PULL_DOWN, // 165 : FMI1_CEN[3] ->
|
||||
CFG_DISABLED | PULL_DOWN, // 166 : FMI1_CEN[2] ->
|
||||
CFG_DISABLED | PULL_DOWN, // 167 : FMI1_CEN[1] ->
|
||||
|
||||
/* Port 21 */
|
||||
CFG_FUNC0, // 168 : FMI1_CEN[0] -> F1CE0_L
|
||||
CFG_FUNC0, // 169 : FMI1_CLE -> F1CLE
|
||||
CFG_FUNC0, // 170 : FMI1_ALE -> F1ALE
|
||||
CFG_FUNC0, // 171 : FMI1_REN -> F1RE_L
|
||||
CFG_FUNC0, // 172 : FMI1_WEN -> F1WE_L
|
||||
CFG_FUNC0, // 173 : FMI1_IO[7] -> F1AD<7>
|
||||
CFG_FUNC0, // 174 : FMI1_IO[6] -> F1AD<6>
|
||||
CFG_FUNC0, // 175 : FMI1_IO[5] -> F1AD<5>
|
||||
|
||||
/* Port 22 */
|
||||
CFG_FUNC0, // 176 : FMI1_IO[4] -> F1AD<4>
|
||||
CFG_FUNC0, // 177 : FMI1_DQS -> F1DQS
|
||||
CFG_FUNC0, // 178 : FMI1_IO[3] -> F1AD<3>
|
||||
CFG_FUNC0, // 179 : FMI1_IO[2] -> F1AD<2>
|
||||
CFG_FUNC0, // 180 : FMI1_IO[1] -> F1AD<1>
|
||||
CFG_FUNC0, // 181 : FMI1_IO[0] -> F1AD<0>
|
||||
CFG_DISABLED, // 182 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 183 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED, // 184 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 185 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 186 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 187 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 188 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 189 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 190 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 191 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 24 */
|
||||
CFG_FUNC0, // 192 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0, // 193 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0, // 194 : UART0_TXD -> DUT_TXD
|
||||
CFG_FUNC0 | PULL_DOWN, // 195 : UART0_RXD -> DUT_RXD
|
||||
CFG_DISABLED | PULL_DOWN, // 196 : UART5_RTXD -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 197 : DP_HPD -> GND
|
||||
CFG_FUNC0 | PULL_DOWN, // 198 : TST_CLKOUT -> TST_CLKOUT
|
||||
CFG_DISABLED | PULL_DOWN, // 199 : TST_STPCLK -> GND
|
||||
|
||||
/* Port 25 */
|
||||
CFG_FUNC0, // 200 : WDOG -> H4A_WDOG
|
||||
CFG_DISABLED, // 201 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 202 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 203 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 204 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 205 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 206 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 207 : UNSPECIFIED -> UNSPECIFIED
|
||||
};
|
||||
|
||||
struct pinconfig_map {
|
||||
uint32_t board_id;
|
||||
uint32_t board_id_mask;
|
||||
const uint32_t *pinconfigs[GPIOC_COUNT];
|
||||
};
|
||||
|
||||
static const struct pinconfig_map cfg_map[] = {
|
||||
{ 0, 1, { pinconfig_ap_0 } },
|
||||
{ 1, 1, { pinconfig_dev_0 } },
|
||||
};
|
||||
|
||||
const uint32_t * target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
static const struct pinconfig_map *selected_map = NULL;
|
||||
|
||||
if (selected_map == NULL) {
|
||||
uint32_t board_id = platform_get_board_id();
|
||||
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
|
||||
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
|
||||
selected_map = &cfg_map[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (selected_map == NULL)
|
||||
panic("no default pinconfig for board id %u", board_id);
|
||||
}
|
||||
|
||||
ASSERT(gpioc < GPIOC_COUNT);
|
||||
return selected_map->pinconfigs[gpioc];
|
||||
}
|
||||
@@ -0,0 +1,43 @@
|
||||
# Copyright (C) 2010-2012 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D1881=1 \
|
||||
TARGET_HIGH_SOC_VOLTAGE=CHIPID_SOC_VOLTAGE_MED \
|
||||
TARGET_HIGH_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_MED \
|
||||
TARGET_CPU_SOURCE=2 \
|
||||
TARGET_MIPI_DSI_SOURCE=1 \
|
||||
TARGET_MANAGED2H_SOURCE=0 \
|
||||
TARGET_MANAGED2L_SOURCE=0 \
|
||||
TARGET_MANAGED2H_DIV=1 \
|
||||
TARGET_MANAGED2L_DIV=2 \
|
||||
TARGET_PCLK1_SOURCE=1 \
|
||||
TARGET_PCLK1_DIV=4 \
|
||||
TARGET_GFX_SOURCE=2 \
|
||||
TARGET_GFX_SLC_SOURCE=3 \
|
||||
TARGET_IOP_SOURCE=3 \
|
||||
TARGET_LPERFS_SOURCE=3 \
|
||||
TARGET_HPERFNRT_SOURCE=0 \
|
||||
TARGET_USE_HSIC=1 \
|
||||
TARGET_DSIM_CONFIG=0x00400000 \
|
||||
TARGET_DSIM_DPHYCTL=0x30 \
|
||||
TARGET_DSIM_SUPPRESS=0x1 \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
AMC_CHANNEL_WIDTH=4 \
|
||||
WIFI_DTPATH=\"arm-io/usb-complex/usb-ehci/wlan\" \
|
||||
WITH_TARGET_USB_CONFIG=1
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_ADBE_SETTINGS_H
|
||||
#define __TARGET_ADBE_SETTINGS_H
|
||||
|
||||
static struct adbe_v2_tuneable adbe_tuneables[] = {
|
||||
{
|
||||
.name = "ipad6d",
|
||||
.adbe0_vblank_pos_vbi_pulse = 0x0132,
|
||||
.adbe0_vblank_clk_gate_wakeup = 0x07,
|
||||
.adbe0_vblank_clk_gate_idle = 0x0000,
|
||||
.adbe0_vblank_busy_finish = 2,
|
||||
.adbe0_tunable_mode_ctrl = (DBEMODECNTL_PMGR_CLK_GATE_ENABLE |
|
||||
DBEMODECNTL_DYN_CLK_GATE_ENABLE |
|
||||
DBEMODECNTL_BLK_CLK_GATE_ENABLE),
|
||||
.adbe0_aap_support = 1,
|
||||
.adbe0_aap_format_control_reg1 = (AAP_FORMAT_CONTROL_REG1_AUTOPOS |
|
||||
AAP_FORMAT_CONTROL_REG1_FCMODE(2) |
|
||||
AAP_FORMAT_CONTROL_REG1_RSVD(0) |
|
||||
AAP_FORMAT_CONTROL_REG1_VS_POL),
|
||||
},
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef TARGET_BOARDID_H
|
||||
#define TARGET_BOARDID_H
|
||||
|
||||
// Board ids
|
||||
#define TARGET_BOARD_ID_J98aAP (0x10)
|
||||
#define TARGET_BOARD_ID_J98aDEV (0x11)
|
||||
|
||||
#define TARGET_BOARD_ID_J99aAP (0x12)
|
||||
#define TARGET_BOARD_ID_J99aDEV (0x13)
|
||||
|
||||
// Board revs
|
||||
#define J99a_DEV0_BOARD_REV (0x0)
|
||||
#define J99a_DEV1_BOARD_REV (0x1)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
// <rdar://problem/19636728> Revert applicable Elba targets to 4 GB when kernel supports 4 GB
|
||||
// will require removing chnldec from the table below, as well as
|
||||
// setting DCS_NUM_CHANNELS to 8. In addition, the SDRAM_LEN and TEXT_BASE will have to be increased
|
||||
static inline
|
||||
void dcs_init_config_fixup_params(dcs_config_params_t *dcs_params, dcs_target_t targtype)
|
||||
{
|
||||
dcs_params->chnldec = 0x00050110;
|
||||
|
||||
#if DCS_DRAM_800MHZ
|
||||
dcs_params->freq[0].clk_period = CLK_PERIOD_800;
|
||||
dcs_params->freq[0].freqchngctl[3] = 0xae015202;
|
||||
dcs_params->freq[1].freqchngctl[3] = 0xae011202;
|
||||
dcs_params->freq[0].lat = 0x001031c6;
|
||||
dcs_params->freq[0].phyrdwrtim = 0x00050c05;
|
||||
dcs_params->freq[0].caspch = 0x43d10408;
|
||||
dcs_params->freq[0].act = 0x10040908;
|
||||
dcs_params->freq[0].autoref = 0x24480078;
|
||||
dcs_params->freq[0].selfref = 0x5004b012;
|
||||
dcs_params->modereg = 0x0e0c6084;
|
||||
dcs_params->pdn = 0x72273263;
|
||||
dcs_params->freq[0].derate = 0x28835488;
|
||||
dcs_params->freq[0].lat2 = 0x001121c6;
|
||||
dcs_params->freq[0].tat = 0x01312222;
|
||||
dcs_params->rdwrdqcaltiming_f0 = 0x01040401;
|
||||
dcs_params->rdwrdqcaltiming_f3 = 0x01040408;
|
||||
dcs_params->rdwrdqcaltimingctrl2 = 0x010f0a01;
|
||||
dcs_params->maxrddqssdllmulfactor = 0x00a00b0b;
|
||||
dcs_params->maxwrdqssdllmulfactor = 0xa0a00808;
|
||||
dcs_params->freq[0].rdcapcfg = 0x0100070a;
|
||||
dcs_params->freq[0].autoref2 = 0x24480049;
|
||||
dcs_params->mr2cmd_step11 = 0x52;
|
||||
dcs_params->mr1cmd_step11 = 0xae;
|
||||
dcs_params->rdsdllctrl_step15 = 0x00280004;
|
||||
dcs_params->qbrparam = 0x00000000;
|
||||
#endif
|
||||
};
|
||||
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_GPIODEF_H
|
||||
#define __TARGET_GPIODEF_H
|
||||
|
||||
/* ipad6,x specific gpio -> pin mappings */
|
||||
|
||||
#include <platform/gpio.h>
|
||||
|
||||
// XXX: Update all of this
|
||||
|
||||
/* define target-specific gpios in a generic fashion here. */
|
||||
|
||||
/* Board Revision */
|
||||
#define GPIO_BOARD_REV0 GPIO(14, 4) // 116 : GPIO[44]
|
||||
#define GPIO_BOARD_REV1 GPIO(14, 5) // 117 : GPIO[45]
|
||||
#define GPIO_BOARD_REV2 GPIO(14, 6) // 118 : GPIO[46]
|
||||
#define GPIO_BOARD_REV3 GPIO(15, 1) // 121 : GPIO[49]
|
||||
|
||||
/* Miscellaneous Pins */
|
||||
#define GPIO_DISPLAY_HPD GPIO(24, 2) // 194: EPD_HPD0 -> LPDP_TCON_TO_SOC_HPD
|
||||
|
||||
#define GPIO_S3E_BOOT_FROM_HOST GPIO_ID(76) // 76 : GPIO[2] -> GPIO_SOC_TO_NAND_FW_STRAP (formerly AP_TO_NAND_FW_STRAP)
|
||||
|
||||
/* which IICs to initialize */
|
||||
#define IICS_MASK (7)
|
||||
|
||||
/* Switch to this when i2c3 is enabled */
|
||||
//#define IICS_MASK (0xF)
|
||||
|
||||
#define TRISTAR_IIC_BUS (0)
|
||||
#define BACKLIGHT_IIC_BUS (0)
|
||||
#define DISPLAY_PMU_IIC_BUS (0)
|
||||
|
||||
#define GPIO_PMU_LCD_PWR_EN (17) // PMU GPIO 18 - GPIO_PMU_TO_LCD_PWREN
|
||||
#define GPIO_PMU_NAND_LOW_POWER_MODE (15) // PMU GPIO 16 - GPIO_PMU_TO_NAND_LOW_BATT_L
|
||||
|
||||
#endif /* ! __TARGET_GPIODEF_H */
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef LPDP_SETTINGS_H
|
||||
#define LPDP_SETTINGS_H
|
||||
|
||||
static struct lpdp_port_calibration lpdp_port_calibration_table[1][1] = {
|
||||
{ {LPDP_PHY_LANE_VREG_ADJ_450_mV, 0}, },
|
||||
};
|
||||
|
||||
#define LPDP_PORT_CALIBRATION_TABLE_FIXED (true)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,140 @@
|
||||
#ifndef __TARGET_POWERCONFIG_H
|
||||
#define __TARGET_POWERCONFIG_H
|
||||
|
||||
// Configuration per target
|
||||
|
||||
#define PMU_IIC_BUS 0
|
||||
|
||||
// This configuration is very PMU specific and must be included exactly
|
||||
// once in power.c
|
||||
#ifdef POWERCONFIG_PMU_SETUP
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
|
||||
{
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kD2257_EN_CMD0, (1<<7)|(1<<3)|(1<<2)|(1<<1)|(1<<0) },
|
||||
{ PMU_IIC_BUS, kD2257_EN_CMD1, (1<<0) }, // buck8
|
||||
{ PMU_IIC_BUS, kD2257_EN_CMD2, 1 }, // enable WLED SPI access
|
||||
{ PMU_IIC_BUS, kD2257_SPI_CTRL, 1 } // enable SPI access
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_warm_init[] =
|
||||
{
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_cold_init[] =
|
||||
{
|
||||
// TODO :This is a Bringup Hack, remove
|
||||
{ PMU_IIC_BUS, kD2257_BUCK0_VSEL, 0xc0}, // CPU rail
|
||||
{ PMU_IIC_BUS, kD2257_BUCK1_VSEL, 0xc0}, // GPU rail
|
||||
{ PMU_IIC_BUS, kD2257_PWRONOFF_BUCK1_EN, 0xf}, // GPU power rail (see <rdar://problem/19733370>)
|
||||
{ PMU_IIC_BUS, kD2257_PWRONOFF_BUCK8_EN, 0xf}, // GPU RAM power rail (see <rdar://problem/19733370>)
|
||||
// TODO :This is a Bringup Hack, remove
|
||||
|
||||
{ PMU_IIC_BUS, kD2257_PWRONOFF_LDO4_EN, 0x1}, // Enable PP3V0_ALS
|
||||
{ PMU_IIC_BUS, kD2257_PWRONOFF_LDO7_EN, 0x1}, // Enable PP3V3_USB3
|
||||
|
||||
{ PMU_IIC_BUS, kD2257_LDO2_BYPASS, 0x1}, // bypass when Active rdar://19773152
|
||||
|
||||
// Drive GPIO_PMU_TO_1V1_EXT_SW_ON (PMU GPIO 20) to enable PP1V1_S1_EXT_SW
|
||||
// which inturn is SNSI_PP1V1_S1_DDR_VDDQ_x.
|
||||
//
|
||||
// Should be ON by default via OTP.
|
||||
|
||||
// Drive GPIO_PMU_TO_1V8_EXT_SW2_ON (PMU GPIO 21) to enable PP1V8_S2_EXT_SW2
|
||||
// which inturn is PP1V8_S2_IO_EXPANDER.
|
||||
//
|
||||
// Should be ON by default via OTP.
|
||||
|
||||
{ PMU_IIC_BUS, 0x7000, 0x1D }, // Enable Test Mode
|
||||
{ PMU_IIC_BUS, kD2257_EN_CMD3, 0}, // Enable SPI access for BUCKx (x=3)
|
||||
{ PMU_IIC_BUS, 0x7000, 0x0 }, // Disable Test Mode
|
||||
|
||||
#if SUB_TARGET_J98a
|
||||
{ PMU_IIC_BUS, kD2257_GPIO5_CONF1, 0x14},
|
||||
{ PMU_IIC_BUS, kD2257_GPIO5_CONF2, 0x0F},
|
||||
{ PMU_IIC_BUS, kD2257_GPIO9_CONF1, 0x14},
|
||||
{ PMU_IIC_BUS, kD2257_GPIO9_CONF2, 0x0F}
|
||||
#endif
|
||||
|
||||
// ElbaRefUI uses PMU_GPIO19 as GPIO_BEACON_EN_R (J99a uses UART7_RXD as GPIO_SOC_TO_BEACON_EN)
|
||||
{ PMU_IIC_BUS, kD2257_GPIO19_CONF1, (2<<6)|(0<<3)|(0<<1)|(1<<0) }, // 0x80 Output(Push-Pull), Level, no PU/PD, High
|
||||
{ PMU_IIC_BUS, kD2257_GPIO19_CONF2, (1<<3)|(0<<0) }, // 0x08 VBUCK3, no DEB
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_backlight_enable[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_ISET, 0xff }, // 50% value from OS
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_ISET2, 0x7f },
|
||||
{ PMU_IIC_BUS, kD2257_WLED_CTRL1, // enable all LED strings
|
||||
(kDIALOG_WLED_CONTROL_WLED_ENABLE1 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE2 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE3 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE4 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE5 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE6) },
|
||||
{ PMU_IIC_BUS, kD2257_WLED_CTRL2, // enable all LED strings
|
||||
(kDIALOG_WLED_CONTROL_WLED_ENABLE1 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE2 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE3 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE4 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE5 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE6) },
|
||||
{ PMU_IIC_BUS, kD2257_PWRONOFF_WLEDA_EN, 0x1f }, // enable LED Power
|
||||
{ PMU_IIC_BUS, kD2257_PWRONOFF_WLEDB_EN, 0x1f }, // enable LED Power
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_backlight_disable[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kD2257_PWRONOFF_WLEDA_EN, 0x0 }, // disable LED Power
|
||||
{ PMU_IIC_BUS, kD2257_PWRONOFF_WLEDB_EN, 0x0 }, // disable LED Power
|
||||
};
|
||||
|
||||
static const struct core_rails_struct soc_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2257_BUCK2_VSEL }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct cpu_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2257_BUCK0_VSEL }
|
||||
};
|
||||
|
||||
// It's VDD FIXED! used for RAM inside the SOC
|
||||
static const struct core_rails_struct ram_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2257_BUCK5_VSEL }
|
||||
};
|
||||
|
||||
// This is indexed with POWER_RAIL_*, I really just need to use the
|
||||
// index in LDO[]
|
||||
target_rails_t target_rails = {
|
||||
{ 0x10, 450, 1250, 3125 }, // POWER_RAIL_CPU, BUCK0
|
||||
{ 0x15, 600, 1400, 3125 }, // POWER_RAIL_VDD_FIXED BUCK5
|
||||
{ 0x12, 600, 1400, 3125 }, // POWER_RAIL_SOC, BUCK2
|
||||
|
||||
{ 0x17, 600, 1400, 3125 }, // POWER_RAIL_CPU_RAM, BUCK7
|
||||
{ 0x11, 450, 1250, 3125 }, // POWER_RAIL_GPU, BUCK1
|
||||
{ 0x18, 600, 1400, 3125 }, // POWER_RAIL_GPU_RAM, BUCK8
|
||||
};
|
||||
|
||||
#endif // POWERCONFIG_PMU_SETUP
|
||||
|
||||
#define NO_BATTERY_VOLTAGE 2700
|
||||
#define MIN_BOOT_BATTERY_VOLTAGE 3600
|
||||
#define TARGET_BOOT_BATTERY_VOLTAGE 3700
|
||||
#define TARGET_BOOT_BATTERY_CAPACITY 50
|
||||
#define PRECHARGE_BACKLIGHT_LEVEL 824
|
||||
#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
|
||||
#define TARGET_MAX_USB_INPUT_CURRENT 2400
|
||||
|
||||
#define TARGET_PRECHARGE_ALWAYS_DISPLAY_IDLE 1
|
||||
|
||||
#define ACC_PWR_LDO (6)
|
||||
|
||||
#define GASGAUGE_BATTERYID_BLOCK 1
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define one debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (0)
|
||||
|
||||
#define HDQGAUGE_SERIAL_PORT (5)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,279 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <drivers/flash_nor.h>
|
||||
#include <drivers/power.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <target.h>
|
||||
#if WITH_HW_DISPLAY_PMU
|
||||
#include <drivers/display_pmu.h>
|
||||
#endif
|
||||
#if (ELBAUIREF && APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC))
|
||||
#include <drivers/displayport/displayport.h>
|
||||
#include <drivers/displayport.h>
|
||||
dp_t dp;
|
||||
#endif
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, -90);
|
||||
|
||||
void
|
||||
target_early_init (void)
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
target_late_init (void)
|
||||
{
|
||||
power_set_gpio(GPIO_PMU_NAND_LOW_POWER_MODE, 1, 1);
|
||||
}
|
||||
|
||||
void
|
||||
target_init (void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
target_quiesce_hardware (void)
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
target_poweroff (void)
|
||||
{
|
||||
}
|
||||
|
||||
int
|
||||
target_bootprep (enum boot_target target)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool
|
||||
target_should_recover (void)
|
||||
{
|
||||
return (platform_get_request_dfu2() && power_has_usb());
|
||||
}
|
||||
|
||||
bool
|
||||
target_should_poweron (bool *cold_button_boot)
|
||||
{
|
||||
#if WITH_HW_POWER
|
||||
if (power_get_boot_flag() == kPowerBootFlagColdButton) {
|
||||
*cold_button_boot = true;
|
||||
}
|
||||
#else
|
||||
*cold_button_boot = false;
|
||||
#endif // WITH_HW_POWER
|
||||
|
||||
return (!*cold_button_boot || platform_get_request_dfu1());
|
||||
}
|
||||
|
||||
bool
|
||||
target_should_poweroff (bool at_boot)
|
||||
{
|
||||
return (platform_get_request_dfu1() && (!at_boot || !power_has_usb()));
|
||||
}
|
||||
|
||||
void * target_get_display_configuration(void)
|
||||
{
|
||||
#if (ELBAUIREF && APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC))
|
||||
dp.mode = kDPControllerMode_Slave;
|
||||
dp.type = kDPControllerType_EDP;
|
||||
dp.min_link_rate = kLinkRate324Gbps;
|
||||
dp.max_link_rate = kLinkRate324Gbps;
|
||||
dp.lanes = 0x4;
|
||||
dp.ssc = 0x0;
|
||||
dp.alpm = 0x1;
|
||||
dp.vrr_enable = 0x1;
|
||||
dp.vrr_on = 0x1;
|
||||
dp.rx_n1= 25;
|
||||
dp.rx_n2= 2;
|
||||
dp.rx_n3= 16030;
|
||||
dp.rx_n5= 0x2;
|
||||
dp.fast_link_training = true;
|
||||
return ((void *)(&dp));
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void
|
||||
target_setup_default_environment (void)
|
||||
{
|
||||
env_set("boot-args", " debug=0x14e serial=3 amfi=3 amfi_get_out_of_my_way=1 cs_enforcement_disable=1 fips_mode=0", 0);
|
||||
// boot-device is set in platform's init.c
|
||||
env_set("boot-partition", "0", 0);
|
||||
env_set("boot-path", "/System/Library/Caches/com.apple.kernelcaches/kernelcache", 0);
|
||||
|
||||
env_set("display-color-space","RGB888", 0);
|
||||
|
||||
env_set("display-timing", "ipad6d", 0);
|
||||
env_set("adbe-tunables", "ipad6d", 0);
|
||||
env_set("adfe-tunables", "ipad6d", 0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
int
|
||||
target_update_device_tree (void)
|
||||
{
|
||||
DTNode *node;
|
||||
|
||||
#if WITH_HW_DISPLAY_EDP
|
||||
DTNode *clcd_node = NULL, *backlight_node = NULL, *lcd_node = NULL;
|
||||
DTNode *lpdp_node = NULL;
|
||||
#endif
|
||||
|
||||
#if WITH_HW_DISPLAY_EDP
|
||||
if (FindNode(0, DP_DTPATH, &node)) {
|
||||
extern int edp_update_device_tree(DTNode *edp_node, DTNode *lcd_node, DTNode *clcd_node, DTNode *backlight_node);
|
||||
FindNode(0, "arm-io/disp0", &clcd_node);
|
||||
FindNode(0, DP_DTPATH "/lcd", &lcd_node);
|
||||
FindNode(0, "backlight", &backlight_node);
|
||||
edp_update_device_tree(node, lcd_node, clcd_node, backlight_node);
|
||||
|
||||
extern int lpdp_phy_update_device_tree(DTNode *lpdp_node);
|
||||
FindNode(0, DPPHY_DTPATH, &lpdp_node);
|
||||
lpdp_phy_update_device_tree(lpdp_node);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif // WITH_DEVICETREE
|
||||
|
||||
#if WITH_PAINT
|
||||
|
||||
// The default background is expected to to be black and the artwork is expected
|
||||
// to be white. This arrangement will be inverted depending upon the cover glass
|
||||
// color of the device.
|
||||
|
||||
// Sample DClr_override values for testing devices without DClr syscfg entries
|
||||
// (enclosure/cover glass):
|
||||
// gray/black: setenv DClr_override 000200009B9899003C3B3B0000000000
|
||||
// silver/white: setenv DClr_override 00020000D8D9D700E3E4E10000000000
|
||||
|
||||
static color_policy_invert_t target_cover_glass_color_table[] = {
|
||||
{ RGB( 59, 59, 60), false }, // Black - black background, white logo
|
||||
{ RGB(225, 228, 227), true }, // White - white background, black logo
|
||||
};
|
||||
|
||||
color_policy_t *
|
||||
target_color_map_init (enum colorspace cs, color_policy_t *color_policy)
|
||||
{
|
||||
// Must have a color policy structure passed in.
|
||||
if (color_policy == NULL)
|
||||
goto fail;
|
||||
|
||||
// We only support the RGB888 colorspace.
|
||||
if (cs != CS_RGB888)
|
||||
goto fail;
|
||||
|
||||
color_policy->policy_type = COLOR_MAP_POLICY_INVERT;
|
||||
color_policy->color_table = (void *)target_cover_glass_color_table;
|
||||
color_policy->color_count = ARRAY_SIZE(target_cover_glass_color_table);
|
||||
color_policy->map_color = NULL; // Use standard remapper
|
||||
|
||||
return color_policy;
|
||||
|
||||
fail:
|
||||
return NULL;
|
||||
}
|
||||
#endif // WITH_PAINT
|
||||
|
||||
#if !WITH_HW_POWER
|
||||
|
||||
bool power_needs_precharge(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
void power_cancel_buttonwait(void)
|
||||
{
|
||||
}
|
||||
|
||||
bool power_do_chargetrap(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
bool power_is_suspended(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
void power_will_resume(void)
|
||||
{
|
||||
}
|
||||
|
||||
bool power_has_usb(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
int power_read_dock_id(unsigned *id)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
bool power_get_diags_dock(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
uint32_t power_get_boot_battery_level(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int power_get_nvram(uint8_t key, uint8_t *data)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int power_set_nvram(uint8_t key, uint8_t data)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int power_set_soc_voltage(unsigned mv, int override)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
bool force_usb_power = false;
|
||||
|
||||
void power_set_usb_state(bool configured, bool suspended)
|
||||
{
|
||||
}
|
||||
|
||||
int power_backlight_enable(uint32_t backlight_level)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* ! WITH_HW_POWER */
|
||||
@@ -0,0 +1,706 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: rev 0.1
|
||||
I/O Spreadsheet tracker: rdar://problem/18695359
|
||||
Conversion command: csvtopinconfig.py --soc elba --config-column 'J99A Config' --radar rdar://problem/18695359 --copyright 2015 <filename>
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
|
||||
static const uint32_t pinconfig_ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 0 : SPI1_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 1 : SPI1_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 2 : SPI1_MISO -> SPI_CODEC_MISO
|
||||
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 3 : SPI1_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 4 : ISP_I2C1_SDA -> ISP_FRONT_CAM_SDA
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 5 : ISP_I2C1_SCL -> ISP_FRONT_CAM_SCL
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 6 : ISP_I2C0_SDA -> ISP_REAR_CAM_SDA
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 7 : ISP_I2C0_SCL -> ISP_REAR_CAM_SCL
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 8 : SENSOR0_ISTRB -> NC_GPIO_SOC_TO_AUDIO_FH_KEEPALIVE
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 9 : SENSOR0_RST -> GPIO_SOC_TO_REAR_CAM_SHTDWN_L
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 10 : SENSOR0_CLK -> CLK_SOC_TO_REAR_CAM_12MHZ_R
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 11 : SENSOR0_XSHUTDOWN -> NC_SENSOR0_XSHUTDOWN
|
||||
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 12 : SENSOR1_ISTRB -> GPIO_BTN_VOL_UP_L
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 13 : SENSOR1_RST -> GPIO_SOC_TO_FRONT_CAM_SHTDWN_L
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 14 : SENSOR1_CLK -> CLK_SOC_TO_FRONT_CAM_12MHZ_R
|
||||
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 15 : SENSOR1_XSHUTDOWN -> GPIO_BTN_VOL_DOWN_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 16 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 17 : GPIO[17] -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 18 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 19 : I2S1_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 20 : I2S1_BCLK -> I2S_SOC2CODEC_ASP_BCLK_R
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 21 : I2S1_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 22 : I2S1_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 23 : I2S1_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
|
||||
/* Port 3 */
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 24 : NAND_SYS_CLK -> NAND_SYS_CLK_24MHZ
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_S3 | SLOW_SLEW, // 25 : S3E0_RESETN -> GPIO_SOC_TO_NAND_RESET_L
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 26 : S3E1_RESETN -> NC_PCIE_S3E1_RESET
|
||||
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 27 : UART1_TXD -> UART_SOC2BB_TX
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 28 : UART1_RXD -> UART_BB2SOC_TX
|
||||
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 29 : UART1_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 30 : UART1_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 31 : GPIO[43] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
|
||||
/* Port 4 */
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 32 : I2S0_BCLK -> I2S_SOC2CODEC_XSP_BCLK_R
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 33 : I2S0_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 34 : I2S0_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 35 : I2S0_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 36 : I2S0_MCK -> I2S_AOP_MCLK_R
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 8 */
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 64 : I2S4_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 65 : I2S4_BCLK -> I2S_SOC_TO_BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 66 : I2S4_LRCK -> I2S_SOC_TO_BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 67 : I2S4_DIN -> I2S_BT_TO_SOC_DOUT
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 68 : I2S4_DOUT -> I2S_SOC_TO_BT_DOUT
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 69 : I2S2_MCK -> I2S_SOC_TO_SPKRAMP_FH_MCLK_R
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 70 : I2S2_BCLK -> I2S_SOC_TO_SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 71 : I2S2_LRCK -> I2S_SOC_TO_SPKRAMP_FH_LRCK
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 72 : I2S2_DIN -> I2S_SPKRAMP_FH_TO_SOC_DOUT
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 73 : I2S2_DOUT -> I2S_SOC_TO_SPKRAMP_FH_DOUT
|
||||
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 74 : GPIO[0] -> GPIO_CODEC_TO_SOC_IRQ_L
|
||||
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 75 : GPIO[1] -> GPIO_SOC_TO_BB_RADIO_ON_L
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 76 : GPIO[2] -> GPIO_SOC_TO_NAND_FW_STRAP
|
||||
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW, // 77 : GPIO[3] -> GPIO_BB_TO_SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 78 : GPIO[4] -> GPIO_TOUCH_TO_SOC_IRQ_L
|
||||
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 79 : GPIO[5] -> GPIO_FH_ALS_TO_SOC_IRQ_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 80 : GPIO[6] -> NC_DISPLAY_ID0
|
||||
CFG_DISABLED, // 81 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 82 : GPIO[8] -> GPIO_BB_TO_SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 83 : GPIO[9] -> GPIO_CN_ALS_TO_SOC_IRQ_L
|
||||
CFG_FUNC1 | DRIVE_S3 | SLOW_SLEW, // 84 : GPIO[10] -> GPIO_SOC_TO_KONA_DISPLAY_SYNC
|
||||
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 85 : GPIO[11] -> GPIO_SPKAMP_FH_RIGHT_TO_SOC_IRQ_L
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 86 : GPIO[12] -> NC_DISPLAY_ID0
|
||||
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 87 : GPIO[13] -> GPIO_PMU_TO_SOC_IRQ_L
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 88 : GPIO[14] -> NC_DISPLAY_ID0
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 89 : GPIO[15] -> GPIO_SOC_TO_1V8_TOUCH_EXT_SW_ON
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 90 : UART3_TXD -> UART_SOC_TO_BT_TX
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 91 : UART3_RXD -> UART_BT_TO_SOC_TX
|
||||
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 92 : UART3_RTSN -> UART_SOC_TO_BT_RTS_L
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 93 : UART3_CTSN -> UART_BT_TO_SOC_RTS_L
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 94 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 95 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 96 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 97 : SPI0_SSIN -> GPIO_USBPD_TO_SOC_IRQ
|
||||
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 98 : PCIE_PERST0_N -> PCIE_SOC_TO_NAND_RESET_L
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 99 : PCIE_PERST1_N -> NC_PCIE_PERST1
|
||||
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 100 : PCIE_PERST2_N -> PCIE_SOC_TO_WLAN_RESET_L
|
||||
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 101 : PCIE_PERST3_N -> GPIO_SOC_TO_BB_WAKE_MODEM
|
||||
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 102 : PCIE_PERST4_N -> PCIE_SOC_TO_USB3_RESET_L
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 103 : PCIE_PERST5_N -> NC_PCIE_PERST5
|
||||
|
||||
/* Port 13 */
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 104 : PCIE_CLKREQ0_N -> PCIE_NAND_TO_SOC_CLKREQ_L
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 105 : PCIE_CLKREQ1_N -> NC_PCIE_CLKREQ1
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 106 : PCIE_CLKREQ2_N -> PCIE_WLAN_TO_SOC_CLKREQ_L
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 107 : PCIE_CLKREQ3_N -> PCIE_BB_TO_SOC_CLKREQ_L
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 108 : PCIE_CLKREQ4_N -> PCIE_USB3_TO_SOC_CLKREQ_L
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 109 : PCIE_CLKREQ5_N -> NC_PCIE_CLKREQ5
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 110 : UART2_TXD -> UART_SOC_TO_WLAN_TX
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 111 : UART2_RXD -> UART_WLAN_TO_SOC_TX
|
||||
|
||||
/* Port 14 */
|
||||
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 112 : UART2_RTSN -> UART_SOC_TO_WLAN_RTS_L
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 113 : UART2_CTSN -> UART_WLAN_TO_SOC_RTS_L
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 114 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 115 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 116 : GPIO[44] -> GPIO_BRD_REV0
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 117 : GPIO[45] -> GPIO_BRD_REV1
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 118 : GPIO[46] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 119 : GPIO[47] -> GPIO_BRD_REV2
|
||||
|
||||
/* Port 15 */
|
||||
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 120 : GPIO[48] -> GPIO_TS_TO_SOC_TO_PMU_IRQ
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 121 : GPIO[49] -> GPIO_BRD_REV3
|
||||
CFG_IN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 122 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 123 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 124 : SKEY_L -> NC_SKEY_ID
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 128 : SWD_TMS2 -> SWD_NAND_SWDIO
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 129 : SWD_TMS3 -> SWD_KONA_SWDIO
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 130 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 131 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 132 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW, // 133 : UART4_TXD -> UART_SOC_TO_ROTTERDAM_TX
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 134 : UART4_RXD -> UART_ROTTERDAM_TO_SOC_TX
|
||||
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW, // 135 : UART4_RTSN -> UART_SOC_TO_ROTTERDAM_RTS_L
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 136 : UART4_CTSN -> UART_ROTTERDAM_TO_SOC_RTS_L
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 137 : UART7_TXD -> NC_GPIO_SOC_TO_3V3_TOUCH_EXT_SW_ON
|
||||
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 138 : UART7_RXD -> 1v25_CAM_LDO_EN
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 139 : CLK32K_OUT -> NC_CLK32K_OUT_24MHZ
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 140 : DP_WAKEUP0 -> SWD_ORION_SWCLK
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 141 : DP_WAKEUP1 -> SWD_ORION_SWDIO
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 160 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 161 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 162 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 163 : SPI2_SSIN -> GPIO_MESA_TO_SOC_IRQ
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 164 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 165 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 166 : SPI3_SCLK -> SPI_TOUCH_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 167 : SPI3_MOSI -> SPI_TOUCH_MOSI
|
||||
|
||||
/* Port 21 */
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_S3 | SLOW_SLEW, // 168 : SPI3_MISO -> SPI_TOUCH_MISO
|
||||
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 169 : SPI3_SSIN -> SPI_TOUCH_CS_L
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 170 : UART0_TXD -> UART_SOC_TO_DEBUG_TX
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 171 : UART0_RXD -> UART_DEBUG_TO_SOC_TX
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 172 : UART6_TXD -> UART_SOC_TO_ACC_TX
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 173 : UART6_RXD -> UART_ACC_TO_SOC_TX
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 174 : TMR32_PWM0 -> GPIO_SOC_TO_WLAN_DEVICE_WAKE
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 175 : TMR32_PWM1 -> GPIO_SOC_TO_BT_TO_TOUCH_TS_SYNC
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 176 : TMR32_PWM2 -> NC_TMR32_PWM2
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 177 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 178 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 179 : GPIO[19] -> GPIO_SPKAMP_CN_RIGHT_TO_SOC_IRQ_L
|
||||
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 180 : GPIO[20] -> GPIO_SOC_TO_USB3_XBAR_EN_PULSE_L
|
||||
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 181 : GPIO[21] -> GPIO_SOC_TO_USB3_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 182 : GPIO[22] -> GPIO_SPKAMP_CN_LEFT_TO_SOC_IRQ_L
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 183 : GPIO[23] -> GPIO_USB3_TO_SOC_SMI_L
|
||||
|
||||
/* Port 23 */
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 184 : GPIO[24] -> GPIO_SOC_TO_AUDIO_KEEPALIVE_FH
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 185 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 186 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 187 : PSPI_MOSI -> SPI_SOC_TO_PMU_DATA
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 188 : DWI_DO -> DWI_SOC_TO_BEACON_DO
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 189 : PMGR_MISO -> SPI_PMU_TO_SOC_DATA
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 190 : PMGR_SCLK0 -> SPI_SOC_TO_PMU_SCLK
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 191 : PMGR_SSCLK1 -> DWI_SOC_TO_BEACON_CLK
|
||||
|
||||
/* Port 24 */
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 192 : DROOP -> SOCHOT0_PMU_TO_SOC_L
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 193 : SOCHOT1 -> SOCHOT1_SOC_TO_PMU_L
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 194 : EDP_HPD0 -> LPDP_TCON_TO_SOC_HPD
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 195 : EDP_HPD1 -> NC_EDP_HPD1
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 196 : I2S3_MCK -> I2S_SOC_TO_SPKRAMP_CN_MCLK_R
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 197 : I2S3_BCLK -> I2S_SOC_TO_SPKRAMP_CN_BCLK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 198 : I2S3_LRCK -> I2S_SOC_TO_SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 199 : I2S3_DOUT -> I2S_SOC_TO_SPKRAMP_CN_DOUT
|
||||
|
||||
/* Port 25 */
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 200 : I2S3_DIN -> I2S_SPKRAMP_CN_TO_SOC_DOUT
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 201 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 202 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 203 : GPIO[29] -> GPIO_BRD_ID4
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 204 : GPIO[30] -> NC_EDP_HPD1
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 205 : GPIO[31] -> NC_EDP_HPD1
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 206 : GPIO[32] -> NC_EDP_HPD1
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 207 : GPIO[33] -> NC_EDP_HPD1
|
||||
|
||||
/* Port 26 */
|
||||
CFG_DISABLED, // 208 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 209 : GPIO[35] -> GPIO_SOC_TO_2V85_CAM_LDO_EN
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 210 : GPIO[36] -> GPIO_SOC_TO_TOUCH_RESET_L
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 211 : GPIO[37] -> NC_EDP_HPD1
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 212 : GPIO[38] -> NC_EDP_HPD1
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 213 : GPIO[39] -> NC_EDP_HPD1
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 214 : GPIO[40] -> GPIO_SOC_TO_AUDIO_KEEPALIVE_CN
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 215 : GPIO[41] -> NC_EDP_HPD1
|
||||
|
||||
/* Port 27 */
|
||||
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 216 : GPIO[42] -> GPIO_ORION_TO_SOC_TO_PMU_IRQ
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 217 : TST_CLKOUT -> TP_TST_CLKOUT
|
||||
CFG_IN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 218 : GPU_TRIGGER1 -> GPIO_PMU_TO_SOC_UV_WARN_L
|
||||
CFG_IN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 219 : GPU_TRIGGER2 -> GPIO_PMU_TO_SOC_UV_PEAKI_L
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_ap_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 0 : AOP_SPI_SCLK -> SPI_SENSORS_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 1 : AOP_SPI_MOSI -> SPI_SENSORS_MOSI_R
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 2 : AOP_SPI_MISO -> SPI_SENSORS_MISO
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 3 : AOP_UART1_TXD -> GPIO_AOP_TO_WLAN_CONTEXT_A
|
||||
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 4 : AOP_UART1_RXD -> GPIO_AOP_TO_WLAN_CONTEXT_B
|
||||
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 5 : AOP_UART0_TXD -> UART_AOP_TO_BB_TX
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 6 : AOP_UART0_RXD -> UART_BB_TO_AOP_TX
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 7 : AOP_UART2_TXD -> NC_UART_AOP_TO_TOUCH_TX
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 8 : AOP_UART2_RXD -> NC_GPIO_TOUCH_TO_AOP_DATA_REQUEST
|
||||
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 9 : AOP_I2CM_SDA -> GPIO_ACCEL_TO_AOP_IRQ1
|
||||
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 10 : AOP_I2CM_SCL -> SPI_ACCEL_CS_L
|
||||
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 11 : AOP_FUNC[0] -> SPI_COMPASS_CS_L
|
||||
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 12 : AOP_FUNC[1] -> GPIO_COMPASS_TO_AOP_IRQ
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 13 : AOP_FUNC[2] -> NC_GPIO_PHOSPHORUS_TO_AOP_IRQ
|
||||
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 14 : AOP_FUNC[3] -> GPIO_CARBON_TO_AOP_IRQ1
|
||||
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 15 : AOP_FUNC[4] -> SPI_CARBON_CS_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 16 : AOP_FUNC[5] -> GPIO_CARBON_TO_AOP_IRQ2
|
||||
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 17 : AOP_FUNC[6] -> SPI_PHOSPHORUS_CS_L
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 18 : AOP_FUNC[7] -> NC_GPIO_SOC_TO_TCON_DISPLAY_SYNC
|
||||
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 19 : AOP_FUNC[8] -> GPIO_ACCEL_TO_AOP_IRQ2
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 20 : AOP_FUNC[9] -> NC_GPIO_AOP_TO_LPOSC_EN
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 21 : AOP_SWD_TCK_OUT -> SWD_PERIPHERAL_SWCLK
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 22 : AOP_SWD_TMS0 -> SWD_USBPD_SWDIO
|
||||
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 23 : AOP_SWD_TMS1 -> NC_SWD_BB_SWDIO
|
||||
|
||||
/* Port 3 */
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 24 : AOP_I2S_MCK -> I2S_AOP_MCLK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 25 : AOP_I2S_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 26 : AOP_I2S_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 27 : AOP_I2S_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 0 : SPI1_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 1 : SPI1_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 2 : SPI1_MISO -> SPI_CODEC_MISO
|
||||
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 3 : SPI1_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 4 : ISP_I2C1_SDA -> ISP_FRONT_CAM_SDA
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 5 : ISP_I2C1_SCL -> ISP_FRONT_CAM_SCL
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 6 : ISP_I2C0_SDA -> ISP_REAR_CAM_SDA
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 7 : ISP_I2C0_SCL -> ISP_REAR_CAM_SCL
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 8 : SENSOR0_ISTRB -> NC_GPIO_SOC_TO_AUDIO_FH_KEEPALIVE
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 9 : SENSOR0_RST -> GPIO_SOC_TO_REAR_CAM_SHTDWN_L
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 10 : SENSOR0_CLK -> CLK_SOC_TO_REAR_CAM_12MHZ_R
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 11 : SENSOR0_XSHUTDOWN -> NC_SENSOR0_XSHUTDOWN
|
||||
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 12 : SENSOR1_ISTRB -> GPIO_BTN_VOL_UP_L
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 13 : SENSOR1_RST -> GPIO_SOC_TO_FRONT_CAM_SHTDWN_L
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 14 : SENSOR1_CLK -> CLK_SOC_TO_FRONT_CAM_12MHZ_R
|
||||
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 15 : SENSOR1_XSHUTDOWN -> GPIO_BTN_VOL_DOWN_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 16 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 17 : GPIO[17] -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 18 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 19 : I2S1_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 20 : I2S1_BCLK -> I2S_SOC2CODEC_ASP_BCLK_R
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 21 : I2S1_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 22 : I2S1_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 23 : I2S1_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
|
||||
/* Port 3 */
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 24 : NAND_SYS_CLK -> NAND_SYS_CLK_24MHZ
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_S7 | SLOW_SLEW, // 25 : S3E0_RESETN -> GPIO_SOC_TO_NAND_RESET_L
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 26 : S3E1_RESETN -> NC_PCIE_S3E1_RESET
|
||||
CFG_IN | DRIVE_S7 | SLOW_SLEW, // 27 : UART1_TXD -> UART_SOC2BB_TX
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 28 : UART1_RXD -> UART_BB2SOC_TX
|
||||
CFG_IN | DRIVE_S7 | SLOW_SLEW, // 29 : UART1_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 30 : UART1_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 31 : GPIO[43] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
|
||||
/* Port 4 */
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 32 : I2S0_BCLK -> I2S_SOC2CODEC_XSP_BCLK_R
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 33 : I2S0_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 34 : I2S0_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 35 : I2S0_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 36 : I2S0_MCK -> I2S_AOP_MCLK_R
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 8 */
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 64 : I2S4_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 65 : I2S4_BCLK -> I2S_SOC_TO_BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 66 : I2S4_LRCK -> I2S_SOC_TO_BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 67 : I2S4_DIN -> I2S_BT_TO_SOC_DOUT
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 68 : I2S4_DOUT -> I2S_SOC_TO_BT_DOUT
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 69 : I2S2_MCK -> I2S_SOC_TO_SPKRAMP_FH_MCLK_R
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 70 : I2S2_BCLK -> I2S_SOC_TO_SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 71 : I2S2_LRCK -> I2S_SOC_TO_SPKRAMP_FH_LRCK
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 72 : I2S2_DIN -> I2S_SPKRAMP_FH_TO_SOC_DOUT
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 73 : I2S2_DOUT -> I2S_SOC_TO_SPKRAMP_FH_DOUT
|
||||
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 74 : GPIO[0] -> GPIO_CODEC_TO_SOC_IRQ_L
|
||||
CFG_IN | DRIVE_S4 | SLOW_SLEW, // 75 : GPIO[1] -> GPIO_SOC_TO_BB_RADIO_ON_L
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 76 : GPIO[2] -> GPIO_SOC_TO_NAND_FW_STRAP
|
||||
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW, // 77 : GPIO[3] -> GPIO_BB_TO_SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 78 : GPIO[4] -> GPIO_TOUCH_TO_SOC_IRQ_L
|
||||
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 79 : GPIO[5] -> GPIO_FH_ALS_TO_SOC_IRQ_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 80 : GPIO[6] -> NC_DISPLAY_ID0
|
||||
CFG_DISABLED, // 81 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 82 : GPIO[8] -> GPIO_BB_TO_SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 83 : GPIO[9] -> GPIO_CN_ALS_TO_SOC_IRQ_L
|
||||
CFG_FUNC1 | DRIVE_S7 | SLOW_SLEW, // 84 : GPIO[10] -> GPIO_SOC_TO_KONA_DISPLAY_SYNC
|
||||
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 85 : GPIO[11] -> GPIO_SPKAMP_FH_RIGHT_TO_SOC_IRQ_L
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 86 : GPIO[12] -> NC_DISPLAY_ID0
|
||||
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 87 : GPIO[13] -> GPIO_PMU_TO_SOC_IRQ_L
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 88 : GPIO[14] -> NC_DISPLAY_ID0
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 89 : GPIO[15] -> GPIO_SOC_TO_1V8_TOUCH_EXT_SW_ON
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 90 : UART3_TXD -> UART_SOC_TO_BT_TX
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 91 : UART3_RXD -> UART_BT_TO_SOC_TX
|
||||
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 92 : UART3_RTSN -> UART_SOC_TO_BT_RTS_L
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 93 : UART3_CTSN -> UART_BT_TO_SOC_RTS_L
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 94 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 95 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 96 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 97 : SPI0_SSIN -> GPIO_USBPD_TO_SOC_IRQ
|
||||
CFG_IN | DRIVE_S7 | SLOW_SLEW, // 98 : PCIE_PERST0_N -> PCIE_SOC_TO_NAND_RESET_L
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 99 : PCIE_PERST1_N -> NC_PCIE_PERST1
|
||||
CFG_IN | DRIVE_S4 | SLOW_SLEW, // 100 : PCIE_PERST2_N -> PCIE_SOC_TO_WLAN_RESET_L
|
||||
CFG_IN | DRIVE_S7 | SLOW_SLEW, // 101 : PCIE_PERST3_N -> GPIO_SOC_TO_BB_WAKE_MODEM
|
||||
CFG_IN | DRIVE_S7 | SLOW_SLEW, // 102 : PCIE_PERST4_N -> PCIE_SOC_TO_USB3_RESET_L
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 103 : PCIE_PERST5_N -> NC_PCIE_PERST5
|
||||
|
||||
/* Port 13 */
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 104 : PCIE_CLKREQ0_N -> PCIE_NAND_TO_SOC_CLKREQ_L
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 105 : PCIE_CLKREQ1_N -> NC_PCIE_CLKREQ1
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 106 : PCIE_CLKREQ2_N -> PCIE_WLAN_TO_SOC_CLKREQ_L
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 107 : PCIE_CLKREQ3_N -> PCIE_BB_TO_SOC_CLKREQ_L
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 108 : PCIE_CLKREQ4_N -> PCIE_USB3_TO_SOC_CLKREQ_L
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 109 : PCIE_CLKREQ5_N -> NC_PCIE_CLKREQ5
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 110 : UART2_TXD -> UART_SOC_TO_WLAN_TX
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 111 : UART2_RXD -> UART_WLAN_TO_SOC_TX
|
||||
|
||||
/* Port 14 */
|
||||
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 112 : UART2_RTSN -> UART_SOC_TO_WLAN_RTS_L
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 113 : UART2_CTSN -> UART_WLAN_TO_SOC_RTS_L
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 114 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 115 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 116 : GPIO[44] -> GPIO_BRD_REV0
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 117 : GPIO[45] -> GPIO_BRD_REV1
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 118 : GPIO[46] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 119 : GPIO[47] -> GPIO_BRD_REV2
|
||||
|
||||
/* Port 15 */
|
||||
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 120 : GPIO[48] -> GPIO_TS_TO_SOC_TO_PMU_IRQ
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 121 : GPIO[49] -> GPIO_BRD_REV3
|
||||
CFG_IN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 122 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 123 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 124 : SKEY_L -> NC_SKEY_ID
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 128 : SWD_TMS2 -> SWD_NAND_SWDIO
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 129 : SWD_TMS3 -> SWD_KONA_SWDIO
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 130 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 131 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 132 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW, // 133 : UART4_TXD -> UART_SOC_TO_ROTTERDAM_TX
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 134 : UART4_RXD -> UART_ROTTERDAM_TO_SOC_TX
|
||||
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW, // 135 : UART4_RTSN -> UART_SOC_TO_ROTTERDAM_RTS_L
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 136 : UART4_CTSN -> UART_ROTTERDAM_TO_SOC_RTS_L
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 137 : UART7_TXD -> NC_GPIO_SOC_TO_3V3_TOUCH_EXT_SW_ON
|
||||
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 138 : UART7_RXD -> 1v25_CAM_LDO_EN
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 139 : CLK32K_OUT -> NC_CLK32K_OUT_24MHZ
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 140 : DP_WAKEUP0 -> SWD_ORION_SWCLK
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 141 : DP_WAKEUP1 -> SWD_ORION_SWDIO
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 160 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 161 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 162 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 163 : SPI2_SSIN -> GPIO_MESA_TO_SOC_IRQ
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 164 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 165 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 166 : SPI3_SCLK -> SPI_TOUCH_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 167 : SPI3_MOSI -> SPI_TOUCH_MOSI
|
||||
|
||||
/* Port 21 */
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_S7 | SLOW_SLEW, // 168 : SPI3_MISO -> SPI_TOUCH_MISO
|
||||
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 169 : SPI3_SSIN -> SPI_TOUCH_CS_L
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 170 : UART0_TXD -> UART_SOC_TO_DEBUG_TX
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 171 : UART0_RXD -> UART_DEBUG_TO_SOC_TX
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 172 : UART6_TXD -> UART_SOC_TO_ACC_TX
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 173 : UART6_RXD -> UART_ACC_TO_SOC_TX
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 174 : TMR32_PWM0 -> GPIO_SOC_TO_WLAN_DEVICE_WAKE
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 175 : TMR32_PWM1 -> GPIO_SOC_TO_BT_TO_TOUCH_TS_SYNC
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 176 : TMR32_PWM2 -> NC_TMR32_PWM2
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 177 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 178 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 179 : GPIO[19] -> GPIO_SPKAMP_CN_RIGHT_TO_SOC_IRQ_L
|
||||
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 180 : GPIO[20] -> GPIO_SOC_TO_USB3_XBAR_EN_PULSE_L
|
||||
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 181 : GPIO[21] -> GPIO_SOC_TO_USB3_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 182 : GPIO[22] -> GPIO_SPKAMP_CN_LEFT_TO_SOC_IRQ_L
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 183 : GPIO[23] -> GPIO_USB3_TO_SOC_SMI_L
|
||||
|
||||
/* Port 23 */
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 184 : GPIO[24] -> GPIO_SOC_TO_AUDIO_KEEPALIVE_FH
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 185 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN | DRIVE_S7 | SLOW_SLEW, // 186 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 187 : PSPI_MOSI -> SPI_SOC_TO_PMU_DATA
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 188 : DWI_DO -> DWI_SOC_TO_BEACON_DO
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 189 : PMGR_MISO -> SPI_PMU_TO_SOC_DATA
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 190 : PMGR_SCLK0 -> SPI_SOC_TO_PMU_SCLK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 191 : PMGR_SSCLK1 -> DWI_SOC_TO_BEACON_CLK
|
||||
|
||||
/* Port 24 */
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 192 : DROOP -> SOCHOT0_PMU_TO_SOC_L
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 193 : SOCHOT1 -> SOCHOT1_SOC_TO_PMU_L
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 194 : EDP_HPD0 -> LPDP_TCON_TO_SOC_HPD
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 195 : EDP_HPD1 -> NC_EDP_HPD1
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 196 : I2S3_MCK -> I2S_SOC_TO_SPKRAMP_CN_MCLK_R
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 197 : I2S3_BCLK -> I2S_SOC_TO_SPKRAMP_CN_BCLK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 198 : I2S3_LRCK -> I2S_SOC_TO_SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 199 : I2S3_DOUT -> I2S_SOC_TO_SPKRAMP_CN_DOUT
|
||||
|
||||
/* Port 25 */
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 200 : I2S3_DIN -> I2S_SPKRAMP_CN_TO_SOC_DOUT
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 201 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 202 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 203 : GPIO[29] -> GPIO_BRD_ID4
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 204 : GPIO[30] -> NC_EDP_HPD1
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 205 : GPIO[31] -> NC_EDP_HPD1
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 206 : GPIO[32] -> NC_EDP_HPD1
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 207 : GPIO[33] -> NC_EDP_HPD1
|
||||
|
||||
/* Port 26 */
|
||||
CFG_DISABLED, // 208 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 209 : GPIO[35] -> GPIO_SOC_TO_2V85_CAM_LDO_EN
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 210 : GPIO[36] -> GPIO_SOC_TO_TOUCH_RESET_L
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 211 : GPIO[37] -> NC_EDP_HPD1
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 212 : GPIO[38] -> NC_EDP_HPD1
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 213 : GPIO[39] -> NC_EDP_HPD1
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 214 : GPIO[40] -> GPIO_SOC_TO_AUDIO_KEEPALIVE_CN
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 215 : GPIO[41] -> NC_EDP_HPD1
|
||||
|
||||
/* Port 27 */
|
||||
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 216 : GPIO[42] -> GPIO_ORION_TO_SOC_TO_PMU_IRQ
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 217 : TST_CLKOUT -> TP_TST_CLKOUT
|
||||
CFG_IN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 218 : GPU_TRIGGER1 -> GPIO_PMU_TO_SOC_UV_WARN_L
|
||||
CFG_IN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 219 : GPU_TRIGGER2 -> GPIO_PMU_TO_SOC_UV_PEAKI_L
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_dev_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 0 : AOP_SPI_SCLK -> SPI_SENSORS_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 1 : AOP_SPI_MOSI -> SPI_SENSORS_MOSI_R
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 2 : AOP_SPI_MISO -> SPI_SENSORS_MISO
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 3 : AOP_UART1_TXD -> GPIO_AOP_TO_WLAN_CONTEXT_A
|
||||
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 4 : AOP_UART1_RXD -> GPIO_AOP_TO_WLAN_CONTEXT_B
|
||||
CFG_IN | DRIVE_S7 | SLOW_SLEW, // 5 : AOP_UART0_TXD -> UART_AOP_TO_BB_TX
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 6 : AOP_UART0_RXD -> UART_BB_TO_AOP_TX
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 7 : AOP_UART2_TXD -> NC_UART_AOP_TO_TOUCH_TX
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 8 : AOP_UART2_RXD -> NC_GPIO_TOUCH_TO_AOP_DATA_REQUEST
|
||||
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 9 : AOP_I2CM_SDA -> GPIO_ACCEL_TO_AOP_IRQ1
|
||||
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 10 : AOP_I2CM_SCL -> SPI_ACCEL_CS_L
|
||||
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 11 : AOP_FUNC[0] -> SPI_COMPASS_CS_L
|
||||
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 12 : AOP_FUNC[1] -> GPIO_COMPASS_TO_AOP_IRQ
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 13 : AOP_FUNC[2] -> NC_GPIO_PHOSPHORUS_TO_AOP_IRQ
|
||||
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 14 : AOP_FUNC[3] -> GPIO_CARBON_TO_AOP_IRQ1
|
||||
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 15 : AOP_FUNC[4] -> SPI_CARBON_CS_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 16 : AOP_FUNC[5] -> GPIO_CARBON_TO_AOP_IRQ2
|
||||
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 17 : AOP_FUNC[6] -> SPI_PHOSPHORUS_CS_L
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 18 : AOP_FUNC[7] -> NC_GPIO_SOC_TO_TCON_DISPLAY_SYNC
|
||||
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 19 : AOP_FUNC[8] -> GPIO_ACCEL_TO_AOP_IRQ2
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 20 : AOP_FUNC[9] -> NC_GPIO_AOP_TO_LPOSC_EN
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 21 : AOP_SWD_TCK_OUT -> SWD_PERIPHERAL_SWCLK
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 22 : AOP_SWD_TMS0 -> SWD_USBPD_SWDIO
|
||||
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 23 : AOP_SWD_TMS1 -> NC_SWD_BB_SWDIO
|
||||
|
||||
/* Port 3 */
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 24 : AOP_I2S_MCK -> I2S_AOP_MCLK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 25 : AOP_I2S_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 26 : AOP_I2S_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 27 : AOP_I2S_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
};
|
||||
|
||||
struct pinconfig_map {
|
||||
uint32_t board_id;
|
||||
uint32_t board_id_mask;
|
||||
const uint32_t *pinconfigs[GPIOC_COUNT];
|
||||
};
|
||||
|
||||
static const struct pinconfig_map cfg_map[] = {
|
||||
{ 0, 1, { pinconfig_ap_0, pinconfig_ap_1 } },
|
||||
{ 1, 1, { pinconfig_dev_0, pinconfig_dev_1 } },
|
||||
};
|
||||
|
||||
const uint32_t * target_get_default_gpio_cfg(int gpioc)
|
||||
{
|
||||
static const struct pinconfig_map *selected_map = NULL;
|
||||
|
||||
if (selected_map == NULL) {
|
||||
uint32_t board_id = platform_get_board_id();
|
||||
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
|
||||
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
|
||||
selected_map = &cfg_map[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (selected_map == NULL)
|
||||
panic("no default pinconfig for board id %u", board_id);
|
||||
}
|
||||
|
||||
ASSERT(gpioc < GPIOC_COUNT);
|
||||
return selected_map->pinconfigs[gpioc];
|
||||
}
|
||||
@@ -0,0 +1,46 @@
|
||||
# Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2257=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=0 \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=0 \
|
||||
TARGET_PLL_VCO_CAP=0 \
|
||||
TARGET_VCO_RANGE=2 \
|
||||
TARGET_LPF_CTRL=8 \
|
||||
TARGET_ICP_CTR=15 \
|
||||
TARGET_PHY_STOP_WAIT_TIME=0x28 \
|
||||
DISPLAY_LANDSCAPE_IPAD_TUNABLES=1 \
|
||||
PMU_LCD_PWR_EN=1 \
|
||||
TARGET_HAS_BASEBAND=$(TARGET_HAS_BASEBAND) \
|
||||
TARGET_CORE_PHY_TMR_LPCLK_CFG=0x00330087 \
|
||||
TARGET_CORE_PHY_TMR_CFG=0x256f0000 \
|
||||
DCS_NUM_RANKS=1 \
|
||||
DCS_NUM_CHANNELS=8 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_CPU_RAM=7 \
|
||||
BUCK_SOC=2 \
|
||||
BUCK_GPU=1 \
|
||||
BUCK_GPU_RAM=8 \
|
||||
WITH_CPU_APSC=1 \
|
||||
MULTITOUCH_DTPATH=\"arm-io/spi3/multi-touch\" \
|
||||
WIFI_DTPATH=\"arm-io/uart2/wlan\" \
|
||||
DP_DTPATH=\"arm-io/displayport0\" \
|
||||
DPPHY_DTPATH=\"arm-io/lpdp-phy0\" \
|
||||
BT_DTPATH=\"arm-io/uart3/bluetooth\"
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o $(LOCAL_DIR)/pinconfig.o
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_ADBE_SETTINGS_H
|
||||
#define __TARGET_ADBE_SETTINGS_H
|
||||
|
||||
static struct adbe_v2_tuneable adbe_tuneables[] = {
|
||||
{
|
||||
.name = "default",
|
||||
.adbe0_vblank_pos_vbi_pulse = 0x0000,
|
||||
.adbe0_vblank_clk_gate_wakeup = 0x0000,
|
||||
.adbe0_vblank_clk_gate_idle = 0x0001,
|
||||
.adbe0_vblank_busy_finish = 0,
|
||||
.adbe0_tunable_mode_ctrl = 0,
|
||||
.adbe0_aap_support = 1,
|
||||
.adbe0_aap_format_control_reg1 = (AAP_FORMAT_CONTROL_REG1_AUTOPOS | AAP_FORMAT_CONTROL_REG1_RSVD(8) | AAP_FORMAT_CONTROL_REG1_VS_POL),
|
||||
},
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_ASPNANDCONFIG_H
|
||||
#define __TARGET_ASPNANDCONFIG_H
|
||||
|
||||
//MLC devices
|
||||
#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_ERASE_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_READ_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
|
||||
//TLC devices
|
||||
#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
|
||||
// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
|
||||
#define ASPNAND_INDIRECTION_MEMORY (2*1024*1024)
|
||||
#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_GPIODEF_H
|
||||
#define __TARGET_GPIODEF_H
|
||||
|
||||
/* iphone7,x specific gpio -> pin mappings */
|
||||
|
||||
#include <platform/gpio.h>
|
||||
|
||||
/* define target-specific gpios in a generic fashion here. */
|
||||
|
||||
/* Board Revision */
|
||||
#define GPIO_BOARD_REV0 GPIO( 9, 2) // 74 : GPIO[34]
|
||||
#define GPIO_BOARD_REV1 GPIO( 9, 1) // 73 : GPIO[35]
|
||||
#define GPIO_BOARD_REV2 GPIO( 9, 0) // 72 : GPIO[36]
|
||||
#define GPIO_BOARD_REV3 GPIO( 8, 7) // 71 : GPIO[37]
|
||||
|
||||
/* Miscellaneous Pins */
|
||||
|
||||
/* Display reset */
|
||||
#define GPIO_LCD_RST GPIO( 0, 1) // 1 : ULPI_STP -> AP_TO_LCM_RESET_L
|
||||
#define GPIO_LCD_RST_POLARITY (0) // active low
|
||||
|
||||
/* Ringer Switch */
|
||||
#define GPIO_RINGER_AB GPIO(16, 3) // 131 : GPIO[40] -> BUTTON_TO_AP_RINGER_A
|
||||
|
||||
/* D2186 watchdog tickle, 'KEEPACT' */
|
||||
#define GPIO_WDOG_TICKLE GPIO(13, 3) // 107 : GPIO[19] -> AP_TO_PMU_KEEPACT
|
||||
|
||||
|
||||
/* which IICs to initialize */
|
||||
#define IICS_MASK (7)
|
||||
|
||||
#define TRISTAR_IIC_BUS (0)
|
||||
|
||||
#define DISPLAY_PMU_IIC_BUS (0)
|
||||
|
||||
#endif /* ! __TARGET_GPIODEF_H */
|
||||
@@ -0,0 +1,115 @@
|
||||
#ifndef __TARGET_POWERCONFIG_H
|
||||
#define __TARGET_POWERCONFIG_H
|
||||
|
||||
/* configuration per target */
|
||||
|
||||
#define PMU_IIC_BUS 0
|
||||
|
||||
/* this configuration is very PMU specific and must be included exactly once in power.c */
|
||||
#ifdef POWERCONFIG_PMU_SETUP
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
|
||||
{
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kD2186_ACTIVE3, 0xAE }, // Current OTP enables LDO{1,2,3,4,5,7}, disable LDO4.
|
||||
{ PMU_IIC_BUS, kD2186_ACTIVE6, 0x37 }, // enable BUCK3_SW1, BUCK3_SW2, BUCK3_SW3, BUCK4_SW1, BUCK4_SW2
|
||||
{ PMU_IIC_BUS, kD2186_ACTIVE3, 0xBE }, // enable LDO4 along with LDO{1,2,3,5,7}
|
||||
|
||||
{ PMU_IIC_BUS, kD2186_BUCK1_VSEL, 0x80 }, // rdar://14689066 TODO: remove when not necessary
|
||||
|
||||
{ PMU_IIC_BUS, kD2186_OUT_32K, 0x49 }, // enable OUT32 clock
|
||||
|
||||
{ PMU_IIC_BUS, kD2186_BUCK6_VSEL, 0x26 }, // <rdar://problem/15038492> N56/T133 Adi PMU: Change default voltage on BUCK6 to 2.0375 V
|
||||
|
||||
{ PMU_IIC_BUS, kD2186_LDO9_VSEL, 0x44 }, // <rdar://problem/15047684> N56/T133/N61 Front Camera AVDD Voltage setting from PMU
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_warm_init[] =
|
||||
{
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_cold_init[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kD2186_GPIO1_CONF1, 0x88 }, // CHG_TO_PMU_INT_L In, L Low, No Wake, PU
|
||||
{ PMU_IIC_BUS, kD2186_GPIO1_CONF2, 0x72 }, // CHG_TO_PMU_INT_L POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO2_CONF1, 0x8a }, // BB_TO_PMU_HOST_WAKE_L In, L Low, Wake, PU
|
||||
{ PMU_IIC_BUS, kD2186_GPIO2_CONF2, 0x72 }, // BB_TO_PMU_HOST_WAKE_L POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO3_CONF1, 0x01 }, // PMU_TO_BB_RST_R_L Out 0, Low , Push-Pull
|
||||
{ PMU_IIC_BUS, kD2186_GPIO3_CONF2, 0x12 }, // PMU_TO_BB_RST_R_L VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO4_CONF1, 0x82 }, // TRISTAR_TO_AP_INT In, L High, Wake, PU
|
||||
{ PMU_IIC_BUS, kD2186_GPIO4_CONF2, 0x72 }, // TRISTAR_TO_AP_INT POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO5_CONF1, 0x83 }, // STOCKHOLM_TO_PMU_HOST_WAKE_L In, L High, Wake, PD
|
||||
{ PMU_IIC_BUS, kD2186_GPIO5_CONF2, 0x72 }, // STOCKHOLM_TO_PMU_HOST_WAKE_L POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO6_CONF1, 0x01 }, // PMU_TO_OSCAR_RESET_CLK_32K_L Out 0, Push-Pull
|
||||
{ PMU_IIC_BUS, kD2186_GPIO6_CONF2, 0x12 }, // PMU_TO_OSCAR_RESET_CLK_32K_L VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO7_CONF1, 0x83 }, // WLAN_TO_PMU_HOST_WAKE In, L High, Wake, PD
|
||||
{ PMU_IIC_BUS, kD2186_GPIO7_CONF2, 0x72 }, // WLAN_TO_PMU_HOST_WAKE POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO8_CONF1, 0xA2 }, // CODEC_TO_PMU_MIKEY_INT_L In, Any Edge, Wake, PU
|
||||
{ PMU_IIC_BUS, kD2186_GPIO8_CONF2, 0x12 }, // CODEC_TO_PMU_MIKEY_INT_L VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO9_CONF1, 0x01 }, // PMU_TO_BT_REG_ON_R Out 0, Push-Pull
|
||||
{ PMU_IIC_BUS, kD2186_GPIO9_CONF2, 0x12 }, // PMU_TO_BT_REG_ON_R VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO10_CONF1, 0x92 }, // BT_TO_PMU_HOST_WAKE In, R Edge, Wake, Push-Pull
|
||||
{ PMU_IIC_BUS, kD2186_GPIO10_CONF2, 0x72 }, // BT_TO_PMU_HOST_WAKE Disabled
|
||||
// { PMU_IIC_BUS, kD2186_GPIO11_CONF1, 0x01 }, // PMU_TO_WLAN_REG_ON_R Out 0, Push-Pull
|
||||
{ PMU_IIC_BUS, kD2186_GPIO11_CONF1, 0x03 }, // PMU_TO_WLAN_REG_ON_R Out 1, Push-Pull (FIXME! rdar://14957372)
|
||||
{ PMU_IIC_BUS, kD2186_GPIO11_CONF2, 0x12 }, // PMU_TO_WLAN_REG_ON_R VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO12_CONF1, 0x08}, // AP_TO_I2C0_SCL Out, nReset, PU
|
||||
{ PMU_IIC_BUS, kD2186_GPIO12_CONF2, 0x72 }, // AP_TO_I2C0_SCL POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO13_CONF1, 0x83 }, // OSCAR_TO_PMU_HOST_WAKE In, In, L High, Wake, PD
|
||||
{ PMU_IIC_BUS, kD2186_GPIO13_CONF2, 0x72 }, // OSCAR_TO_PMU_HOST_WAKE POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO14_CONF1, 0x91 }, // NC
|
||||
{ PMU_IIC_BUS, kD2186_GPIO14_CONF2, 0x72 }, // POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO15_CONF1, 0x01 }, // PMU_TO_BB_VBUS_DET Out 0, Low, Push-Pull
|
||||
{ PMU_IIC_BUS, kD2186_GPIO15_CONF2, 0x02 }, // PMU_TO_BB_VBUS_DET VCC_MAIN
|
||||
{ PMU_IIC_BUS, kD2186_GPIO16_CONF1, 0x91 }, // NC
|
||||
{ PMU_IIC_BUS, kD2186_GPIO16_CONF2, 0x72 }, // POR
|
||||
{ PMU_IIC_BUS, kD2186_GPIO17_CONF1, 0x9A }, // WLAN_TO_PMU_PCIE_WAKE_L In, F Edge, Wake, PU
|
||||
{ PMU_IIC_BUS, kD2186_GPIO17_CONF2, 0x12 }, // WLAN_TO_PMU_PCIE_WAKE_L VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO18_CONF1, 0x01 }, // PMU_TO_ACC_SW_ON Out 0, Low, Push-Pull
|
||||
{ PMU_IIC_BUS, kD2186_GPIO18_CONF2, 0x12 }, // PMU_TO_ACC_SW_ON VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO19_CONF1, 0x93 }, // NC_HALL1_TO_PMU_WAKE In, R Edge, Wake, PD
|
||||
{ PMU_IIC_BUS, kD2186_GPIO19_CONF2, 0x12 }, // NC_HALL1_TO_PMU_WAKE VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO20_CONF1, 0x93 }, // NC_HALL2_TO_PMU_WAKE In, R Edge, Wake, PD
|
||||
{ PMU_IIC_BUS, kD2186_GPIO20_CONF2, 0x12 }, // NC_HALL2_TO_PMU_WAKE VBUCK3
|
||||
{ PMU_IIC_BUS, kD2186_GPIO21_CONF1, 0x91 }, // NC
|
||||
{ PMU_IIC_BUS, kD2186_GPIO21_CONF2, 0x72 }, // POR
|
||||
|
||||
// TODO: configure debounce for WAS kD2045_GPIO_DEB2,kD2045_GPIO_DEB5,kD2045_GPIO_DEB6?
|
||||
|
||||
{ PMU_IIC_BUS, kD2186_BUCK_DWI_CTRL0, 0x07 }, // enable DWI for BUCK0, BUCK1, BUCK2
|
||||
{ PMU_IIC_BUS, kD2186_SYS_CTRL2, 0x11 }, // enable HIB_32kHz (for WIFI/BT) and DWI
|
||||
|
||||
// TODO: verify
|
||||
{ PMU_IIC_BUS, kD2186_ACT_TO_HIB_DLY, 0x03 }, // set ACT_TO_HIB_DLY to 3 (6ms)
|
||||
};
|
||||
|
||||
static const struct core_rails_struct soc_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2186_BUCK2_VSEL }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct cpu_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2186_BUCK0_VSEL }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct ram_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2186_BUCK5_VSEL }
|
||||
};
|
||||
|
||||
#endif /* POWERCONFIG_PMU_SETUP */
|
||||
|
||||
#define NO_BATTERY_VOLTAGE 2700
|
||||
#define MIN_BOOT_BATTERY_VOLTAGE 3600
|
||||
#define TARGET_BOOT_BATTERY_VOLTAGE 3700
|
||||
#define TARGET_BOOT_BATTERY_CAPACITY 50
|
||||
#define PRECHARGE_BACKLIGHT_LEVEL 824
|
||||
#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
|
||||
|
||||
#define ACC_PWR_LDO (6)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define one debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (0)
|
||||
|
||||
#define HDQGAUGE_SERIAL_PORT (5)
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define UART_OVERSAMPLE_OVERRIDE (11)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,92 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/power.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <target.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
clock_gate(CLK_UART7, 0);
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return platform_get_request_dfu2() && power_has_usb();
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
if (power_get_boot_flag() == kPowerBootFlagColdButton)
|
||||
*cold_button_boot = true;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
uint32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
#if WITH_ENV
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
// boot-device is set in platform's init.c
|
||||
env_set("wifiaddr", "7E:77:77:77:77:77", 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif // WITH_DEVICETREE
|
||||
@@ -0,0 +1,282 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* THIS STRUCT IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: rev 0v7
|
||||
I/O Spreadsheet tracker: <rdar://problem/14388548> N56 | IOSpreadsheet
|
||||
*/
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 0 : ULPI_DIR -> LCM_TO_AP_HIFA_BSYNC
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 1 : ULPI_STP -> AP_TO_LCM_RESET_L
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 2 : ULPI_NXT -> AP_TO_TOUCH_AND_MAMBA_RESET_L
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 3 : ULPI_DATA[7] -> TOUCH_TO_AP_INT_L
|
||||
CFG_DISABLED | PULL_DOWN, // 4 : ULPI_DATA[6] -> NC
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 5 : ULPI_DATA[5] -> NC
|
||||
CFG_IN | DRIVE_X4 | SLOW_SLEW, // 6 : ULPI_DATA[4] -> DISPLAY_TO_AP_ID1
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 7 : ULPI_CLK -> OSCAR_TO_PMU_HOST_WAKE
|
||||
|
||||
/* Port 1 */
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 8 : ULPI_DATA[3] -> AP_TO_LEDDRV_EN
|
||||
CFG_IN | DRIVE_X4 | SLOW_SLEW, // 9 : ULPI_DATA[2] -> DISPLAY_TO_AP_ID0
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 10 : ULPI_DATA[1] -> AP_BI_OSCAR_SWDIO_1V8
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 11 : ULPI_DATA[0] -> AP_TO_OSCAR_SWDCLK_1V8
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 12 : SPI1_SCLK -> AP_TO_CODEC_SPI_CLK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 13 : SPI1_MOSI -> AP_TO_CODEC_SPI_MOSI
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 14 : SPI1_MISO -> CODEC_TO_AP_SPI_MISO
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 15 : SPI1_SSIN -> AP_TO_CODEC_SPI_CS_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_IN | SLOW_SLEW, // 32 : GPIO[11] -> BUTTON_TO_AP_MENU_KEY_L
|
||||
CFG_IN | SLOW_SLEW, // 33 : GPIO[12] -> BUTTON_TO_AP_HOLD_KEY_L
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 34 : I2S3_MCK -> ALS_TO_AP_INT_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 35 : I2S3_LRCK -> AP_TO_BB_I2S3_LRCLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 36 : I2S3_BCLK -> 45_AP_TO_BB_I2S3_BCLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 37 : I2S3_DOUT -> AP_TO_BB_I2S3_DOUT
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 38 : I2S3_DIN -> BB_TO_AP_I2S3_DIN
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 39 : CLK32K_OUT -> 45_AP_TO_TOUCH_CLK32K_RESET_L
|
||||
|
||||
/* Port 5 */
|
||||
CFG_IN | SLOW_SLEW, // 40 : PCIE_CLKREQ0_N -> NC
|
||||
CFG_FUNC0 | PULL_UP, // 41 : PCIE_CLKREQ1_N -> WLAN_TO_AP_PCIE1_CLKREQ_L
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 42 : NAND_SYS_CLK -> NC
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 43 : GPIO[0] -> AP_TO_HEADSET_HS3_CTRL
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 44 : GPIO[1] -> AP_TO_HEADSET_HS4_CTRL
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 45 : GPIO[2] -> BUTTON_TO_AP_VOL_UP_L
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 46 : GPIO[3] -> BUTTON_TO_AP_VOL_DOWN_L
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 47 : GPIO[4] -> SPKAMP_TO_AP_INT_L
|
||||
|
||||
/* Port 6 */
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 48 : GPIO[5] -> AP_TO_SPKAMP_BEE_GEES
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 49 : GPIO[6] -> AP_TO_SPKAMP_RESET_L
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 50 : GPIO[7] -> AP_TO_BT_WAKE
|
||||
CFG_IN | SLOW_SLEW, // 51 : GPIO[14] -> HALL_TO_PMU_AP_WAKE
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 52 : GPIO[16] -> BOARD_ID3
|
||||
CFG_OUT_0 | PULL_DOWN | SLOW_SLEW, // 53 : GPIO[17] -> AP_TO_STOCKHOLM_SIM_SEL
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 54 : GPIO[18] -> BOOT_CONFIG0
|
||||
CFG_DISABLED | PULL_DOWN, // 55 : GPIO[20] -> NC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 56 : GPIO[21] -> BB_TO_AP_DEVICE_RDY
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 57 : UART5_RTXD -> AP_TO_TIGRIS_SWI
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 58 : UART8_TXD -> AP_TO_OSCAR_UART_TXD
|
||||
CFG_FUNC0 | SLOW_SLEW, // 59 : UART8_RXD -> OSCAR_TO_AP_UART_RXD
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 60 : SPI0_SCLK -> BOARD_ID0
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 61 : SPI0_MOSI -> BOARD_ID1
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 62 : SPI0_MISO -> BOARD_ID2
|
||||
CFG_OUT_1 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 63 : SPI0_SSIN -> NC
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 64 : I2C2_SDA -> AP_BI_I2C2_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 65 : I2C2_SCL -> AP_TO_I2C2_SCL
|
||||
CFG_DISABLED | SLOW_SLEW, // 66 : GPIO[22] -> BB_TO_AP_HSIC1_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 67 : GPIO[23] -> AP_TO_BB_HOST_RDY
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 68 : GPIO[25] -> BOOT_CONFIG1
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 69 : GPIO[28] -> BOOT_CONFIG2
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 70 : GPIO[29] -> BOARD_ID4
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 71 : GPIO[34] -> BOARD_REV3
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 72 : GPIO[35] -> BOARD_REV2
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 73 : GPIO[36] -> BOARD_REV1
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 74 : GPIO[37] -> BOARD_REV0
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 75 : GPIO[39] -> NC
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 76 : GPIO[42] -> AP_TO_VIBE_EN
|
||||
CFG_OUT_1 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 77 : GPIO[43] -> AP_TO_WLAN_PCIE1_RST_L
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 78 : DISP_VSYNC -> NC
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 79 : UART0_TXD -> AP_TO_TRISTAR_DEBUG_UART0_TXD
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW, // 80 : UART0_RXD -> TRISTAR_TO_AP_DEBUG_UART0_RXD
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 81 : TMR32_PWM0 -> OSCAR_BI_AP_TIME_SYNC_HOST_INT
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 82 : TMR32_PWM1 -> AP_TO_VIBE_TRIG
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 83 : TMR32_PWM2 -> HALL_TO_AP_GPIO
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 84 : UART6_TXD -> AP_TO_TRISTAR_ACC_UART6_TXD
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW, // 85 : UART6_RXD -> TRISTAR_TO_AP_ACC_UART6_RXD
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 86 : I2C3_SDA -> NC
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 87 : I2C3_SCL -> NC
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 12 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 96 : I2C0_SDA -> AP_BI_I2C0_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 97 : I2C0_SCL -> AP_TO_I2C0_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 98 : GPIO[38] -> AP_TO_BB_COREDUMP
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : UART2_TXD -> AP_TO_BB_UART2_TXD
|
||||
CFG_FUNC0 | SLOW_SLEW, // 100 : UART2_RXD -> BB_TO_AP_UART2_RXD
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : UART2_RTSN -> AP_TO_BB_UART2_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 102 : UART2_CTSN -> BB_TO_AP_UART2_CTS_L
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 103 : DWI_DO -> 45_AP_TO_PMU_AND_BL_DWI_DO
|
||||
|
||||
/* Port 13 */
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 104 : DWI_CLK -> 45_AP_TO_PMU_AND_BL_DWI_CLK_H7P
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 105 : WDOG -> AP_TO_PMU_RESET_IN
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 106 : GPIO[13] -> PMU_TO_AP_IRQ_L
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 107 : GPIO[19] -> AP_TO_PMU_KEEPACT
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 108 : GPIO[26] -> FORCE_DFU
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 109 : GPIO[27] -> NC
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW, // 110 : SOCHOT0 -> PMU_TO_AP_PRE_UVLO_L_R
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW, // 111 : SOCHOT1 -> AP_TO_PMU_SOCHOT1_L_R
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 113 : TST_CLKOUT -> AP_TO_PMU_TEST_CLKOUT
|
||||
CFG_DISABLED | SLOW_SLEW, // 114 : GPIO[8] -> AP_TO_BB_RST_L
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW, // 115 : GPIO[9] -> AP_TO_WLAN_JTAG_SWCLK
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW, // 116 : GPIO[10] -> AP_TO_WLAN_JTAG_SWDIO
|
||||
CFG_OUT_0 | SLOW_SLEW, // 117 : GPIO[15] -> AP_TO_BB_WAKE_MODEM
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 118 : UART4_TXD -> AP_TO_WLAN_UART4_TXD
|
||||
CFG_FUNC0 | SLOW_SLEW, // 119 : UART4_RXD -> WLAN_TO_AP_UART4_RXD
|
||||
|
||||
/* Port 15 */
|
||||
CFG_OUT_1 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 120 : UART4_RTSN -> AP_TO_WLAN_UART4_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 121 : UART4_CTSN -> WLAN_TO_AP_UART4_CTS_L
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 122 : SPI3_MOSI -> NC
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 123 : SPI3_MISO -> NC
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 124 : SPI3_SCLK -> NC
|
||||
CFG_IN | SLOW_SLEW, // 125 : SPI3_SSIN -> BB_TO_AP_GPS_SYNC
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 126 : GPIO[24] -> BB_TO_AP_RESET_DET_L
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 127 : GPIO[30] -> CODEC_TO_AP_INT_L
|
||||
|
||||
/* Port 16 */
|
||||
CFG_IN | DRIVE_X4 | SLOW_SLEW, // 128 : GPIO[31] -> AP_TO_RADIO_ON_L
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW, // 129 : GPIO[32] -> AP_TO_BB_JTAG_SWCLK
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW, // 130 : GPIO[33] -> AP_TO_BB_JTAG_SWDIO
|
||||
CFG_IN | SLOW_SLEW, // 131 : GPIO[40] -> BUTTON_TO_AP_RINGER_A
|
||||
CFG_DISABLED | SLOW_SLEW, // 132 : GPIO[41] -> BB_TO_AP_IPC_GPIO
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 133 : I2S4_MCK -> TRISTAR_TO_AP_INT
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 134 : I2S4_LRCK -> AP_TO_CODEC_VSP_I2S4_LRCLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 135 : I2S4_BCLK -> 45_AP_TO_CODEC_VSP_I2S4_BCLK
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 136 : I2S4_DOUT -> AP_TO_CODEC_VSP_I2S4_DOUT
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 137 : I2S4_DIN -> CODEC_TO_AP_VSP_I2S4_DIN
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 138 : I2C1_SDA -> AP_BI_I2C1_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 139 : I2C1_SCL -> AP_TO_I2C1_SCL
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 160 : I2S0_LRCK -> AP_TO_CODEC_ASP_I2S0_LRCLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 161 : I2S0_BCLK -> 45_AP_TO_CODEC_ASP_I2S0_BCLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 162 : I2S0_DOUT -> AP_TO_CODEC_ASP_I2S0_DOUT
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 163 : I2S0_DIN -> CODEC_TO_AP_ASP_I2S0_DIN
|
||||
CFG_DISABLED | PULL_DOWN, // 164 : I2S1_MCK -> NC
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 165 : I2S1_LRCK -> AP_TO_BT_I2S1_LRCLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 166 : I2S1_BCLK -> 45_AP_TO_BT_I2S1_BCLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 167 : I2S1_DOUT -> AP_TO_BT_I2S1_DOUT
|
||||
|
||||
/* Port 21 */
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 168 : I2S1_DIN -> BT_TO_AP_I2S1_DIN
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 169 : I2S2_LRCK -> AP_TO_CODEC_XSP_I2S2_LRCLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 170 : I2S2_BCLK -> 45_AP_TO_CODEC_XSP_I2S2_BCLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 171 : I2S2_DOUT -> AP_TO_CODEC_XSP_I2S2_DOUT
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 172 : I2S2_DIN -> CODEC_TO_AP_XSP_I2S2_DIN
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 173 : UART1_TXD -> AP_TO_BT_UART1_TXD
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW, // 174 : UART1_RXD -> BT_TO_AP_UART1_RXD
|
||||
CFG_OUT_1 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 175 : UART1_RTSN -> AP_TO_BT_UART1_RTS_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW, // 176 : UART1_CTSN -> BT_TO_AP_UART1_CTS_L
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 177 : EDP_HPD -> AP_TO_STOCKHOLM_EN
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 178 : UART3_TXD -> AP_TO_STOCKHOLM_UART3_TXD
|
||||
CFG_FUNC0 | SLOW_SLEW, // 179 : UART3_RXD -> STOCKHOLM_TO_AP_UART3_RXD
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 180 : UART3_RTSN -> AP_TO_STOCKHOLM_UART3_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 181 : UART3_CTSN -> STOCKHOLM_TO_AP_UART3_CTS_L
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 182 : SPI2_SCLK -> AP_TO_TOUCH_SPI_CLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 183 : SPI2_MOSI -> AP_TO_TOUCH_SPI_MOSI
|
||||
|
||||
/* Port 23 */
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 184 : SPI2_MISO -> TOUCH_TO_AP_SPI_MISO
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 185 : SPI2_SSIN -> AP_TO_TOUCH_SPI_CS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 186 : ISP0_SDA -> AP_BI_RCAM_I2C_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 187 : ISP0_SCL -> AP_TO_RCAM_I2C_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 188 : ISP1_SDA -> AP_BI_FCAM_I2C_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 189 : ISP1_SCL -> AP_TO_FCAM_I2C_SCL
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 190 : SENSOR0_RST -> AP_TO_RCAM_SHUTDOWN
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 191 : SENSOR0_CLK -> 45_AP_TO_RCAM_CLK_R
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 192 : SENSOR0_XSHUTDOWN -> AP_TO_STOCKHOLM_DWLD_REQ
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 193 : SENSOR0_ISTRB -> BUTTON_TO_AP_SKEY_L
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 194 : ISP_UART0_TXD -> NC_AP_ISP_TO_OSCAR_UART_TXD
|
||||
CFG_FUNC0 | SLOW_SLEW, // 195 : ISP_UART0_RXD -> NC_OSCAR_TO_AP_ISP_UART_RXD
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 196 : SENSOR1_RST -> AP_TO_FCAM_SHUTDOWN
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 197 : SENSOR1_CLK -> 45_AP_TO_FCAM_CLK_R
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 198 : SENSOR1_XSHUTDOWN -> CAM_EXT_LDO_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 199 : SENSOR1_ISTRB -> STOCKHOLM_TO_PMU_HOST_WAKE
|
||||
|
||||
/* Port 25 */
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 200 : UART7_TXD -> AP_TO_WLAN_DEVICE_WAKE
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 201 : UART7_RXD -> NC
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 202 : I2S0_MCK -> 45_AP_TO_CODEC_I2S0_MCLK_R
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 203 : I2S2_MCK -> 45_AP_TO_SPKAMP_I2S2_MCLK_R
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
return gpio_default_cfg;
|
||||
}
|
||||
@@ -0,0 +1,38 @@
|
||||
# Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2186=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_V2 \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=CHIPID_SOC_VOLTAGE_VMIN \
|
||||
TARGET_VID0_CLK_CFG=0x86100000 \
|
||||
TARGET_CORE_PHY_TMR_LPCLK_CFG=0x00330087 \
|
||||
TARGET_CORE_PHY_TMR_CFG=0x256f0000 \
|
||||
TARGET_PHY_STOP_WAIT_TIME=0x28 \
|
||||
DISPLAY_IPHONE_TUNABLES=1 \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_SOC=2 \
|
||||
BUCK_GPU=1 \
|
||||
TARGET_HS_2_LP_DATA_TIME=0 \
|
||||
TARGET_LP_2_HS_DATA_TIME=0 \
|
||||
TARGET_HS_2_LP_CLOCK_TIME=0 \
|
||||
TARGET_LP_2_HS_CLOCK_TIME=0
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <drivers/display.h>
|
||||
#include <lib/paint.h>
|
||||
#include <platform.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <target.h>
|
||||
|
||||
int display_get_info(struct display_info *info)
|
||||
{
|
||||
// Relatively sane defaults of 1136x640 @2x
|
||||
info->stride = 640 * 4;
|
||||
info->width = 640;
|
||||
info->height = 1136;
|
||||
|
||||
// 32bpp and @2x scale
|
||||
info->depth = 32 | 1 << 16;
|
||||
info->framebuffer = (uintptr_t)PANIC_BASE - (((info->stride * info->height + 0xFFFUL) & ~0xFFFUL) * 3);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_GPIODEF_H
|
||||
#define __TARGET_GPIODEF_H
|
||||
|
||||
/* iaccy1 specific gpio -> pin mappings */
|
||||
|
||||
#include <platform/gpio.h>
|
||||
|
||||
/* define target-specific gpios in a generic fashion here. */
|
||||
|
||||
#endif /* ! __TARGET_GPIODEF_H */
|
||||
@@ -0,0 +1,97 @@
|
||||
/*
|
||||
* Copyright (C) 2011-2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_PINCONFIG_H
|
||||
#define __TARGET_PINCONFIG_H
|
||||
|
||||
/* Default iAccy1 Hardware Pin Configuration */
|
||||
|
||||
/* Updated to match B137B165_io_pinlist_013.xls */
|
||||
|
||||
#if SUB_TARGET_B137
|
||||
#define PCON_B137_B165(x, y) (PCON_##x)
|
||||
#elif SUB_TARGET_B165
|
||||
#define PCON_B137_B165(x, y) (PCON_##y)
|
||||
#else
|
||||
#error "Unknown subtarget"
|
||||
#endif
|
||||
|
||||
static const struct gpio_default_config gpio_default_config[GPIO_GROUP_COUNT] = {
|
||||
/* P0 */ PINCONFIG(
|
||||
PCON_OUT_0, NO_PUPDN, // I2S0_MCK -> FORCE_PWM_3V3_L
|
||||
PCON_OUT_1, NO_PUPDN, // I2S0_LRCK -> 5V_EN
|
||||
PCON_IN, NO_PUPDN, // I2S0_BCK -> TRI_INT
|
||||
PCON_B137_B165(DISABLE, OUT_1), NO_PUPDN, // I2S0_DOUT -> FORCE_PWM_1V8
|
||||
PCON_OUT_1, NO_PUPDN, // I2S0_DIN -> FORCE_PWM_1V2
|
||||
PCON_FUNC2, NO_PUPDN, // UART0_RXD ->
|
||||
PCON_FUNC2, NO_PUPDN, // UART0_TXD ->
|
||||
PCON_B137_B165(DISABLE, IN), NO_PUPDN // UART0_NRTS -> DAC_SENSE_STS
|
||||
),
|
||||
/* P1 */ PINCONFIG(
|
||||
PCON_B137_B165(DISABLE, IN), NO_PUPDN, // UART0_NCTS -> DAC_HEARTBEAT
|
||||
PCON_FUNC2, NO_PUPDN, // I2C0_SCL -> I2C0_SCL
|
||||
PCON_FUNC2, NO_PUPDN, // I2C0_SDA -> I2C0_SCL
|
||||
PCON_DISABLE, NO_PUPDN, // SPI0_CEN -> SPI0_CS
|
||||
PCON_DISABLE, NO_PUPDN, // SPI0_CLK -> SPI0_CLK
|
||||
PCON_DISABLE, NO_PUPDN, // SPI0_MOSI -> SPI0_MOSI
|
||||
PCON_DISABLE, NO_PUPDN, // SPI0_MISO -> SPI0_MISO
|
||||
PCON_DISABLE, NO_PUPDN // - ->
|
||||
),
|
||||
/* P2 */ PINCONFIG(
|
||||
PCON_DISABLE, NO_PUPDN, // GPIO0 -> BOARD_REV[0]
|
||||
PCON_DISABLE, NO_PUPDN, // GPIO1 -> BOOT_CONFIG[0]
|
||||
PCON_DISABLE, NO_PUPDN, // GPIO2 -> BOOT_CONFIG[1]
|
||||
PCON_DISABLE, NO_PUPDN, // GPIO3 -> BOARD_ID[1]
|
||||
PCON_DISABLE, NO_PUPDN, // GPIO4 -> BOARD_ID[2]
|
||||
PCON_DISABLE, NO_PUPDN, // GPIO5 -> BOARD_ID[3]
|
||||
PCON_DISABLE, NO_PUPDN, // GPIO6 -> BOARD_ID[4]
|
||||
PCON_DISABLE, NO_PUPDN // GPIO7 -> BOARD_REV[1]
|
||||
),
|
||||
/* P3 */ PINCONFIG(
|
||||
PCON_DISABLE, NO_PUPDN, // CLK0_OUT -> G1_CLK0
|
||||
PCON_DISABLE, NO_PUPDN, // CLK1_OUT ->
|
||||
PCON_B137_B165(FUNC2, DISABLE), NO_PUPDN, // HDMI_HPD -> G1_HPD
|
||||
PCON_DISABLE, NO_PUPDN, // HDMI_CEC -> G1_HDMI_CEC
|
||||
PCON_DISABLE, NO_PUPDN, // FORCE_DFU -> FORCE_DFU
|
||||
PCON_DISABLE, NO_PUPDN, // DFU_STATUS -> DFU_STATUS
|
||||
PCON_FUNC2, NO_PUPDN, // I2C1_SCL -> G1_I2C1_SCL
|
||||
PCON_FUNC2, NO_PUPDN // I2C1_SDA -> G1_I2C1_SDA
|
||||
),
|
||||
/* P4 */ PINCONFIG(
|
||||
PCON_FUNC2, NO_PUPDN, // UART2_RXD -> G1_UART_RXFROMPOD
|
||||
PCON_FUNC2, NO_PUPDN, // UART2_TXD -> G1_UART_TXTOPOD
|
||||
PCON_DISABLE, NO_PUPDN, // UART2_NRTS ->
|
||||
PCON_DISABLE, NO_PUPDN, // UART2_NCTS ->
|
||||
PCON_DISABLE, NO_PUPDN, // SPI1_CEN ->
|
||||
PCON_DISABLE, NO_PUPDN, // SPI1_CLK ->
|
||||
PCON_DISABLE, NO_PUPDN, // SPI1_MOSI ->
|
||||
PCON_DISABLE, NO_PUPDN // SPI1_MISO -> BOARD_REV[2]
|
||||
),
|
||||
/* P5 */ PINCONFIG(
|
||||
PCON_FUNC2, NO_PUPDN, // UART1_RXD -> G1_UART_RXFROMACC
|
||||
PCON_FUNC2, NO_PUPDN, // UART1_TXD -> G1_UART_TXTOACC
|
||||
PCON_DISABLE, NO_PUPDN, // UART1_NRTS ->
|
||||
PCON_B137_B165(DISABLE, OUT_1), NO_PUPDN, // UART1_NCTS -> DAC_RESETN
|
||||
PCON_DISABLE, NO_PUPDN, // VGA_VDEN ->
|
||||
PCON_DISABLE, NO_PUPDN, // VGA_HSYNC ->
|
||||
PCON_DISABLE, NO_PUPDN, // VGA_VSYNC ->
|
||||
PCON_DISABLE, NO_PUPDN // - ->
|
||||
),
|
||||
};
|
||||
|
||||
/* default push-pull/open-drain configuration */
|
||||
#define DEFAULT_ODEN (0x00000007) // PoR Defaults
|
||||
|
||||
/* default drive strength */
|
||||
#define DEFAULT_DSTR0 (0x00000555) // PoR Defaults
|
||||
|
||||
#define DEFAULT_OSC_DSTR (0x00000004)
|
||||
|
||||
#endif /* ! __TARGET_PINCONFIG_H */
|
||||
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define two debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (0)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,168 @@
|
||||
/*
|
||||
* Copyright (C) 2011-2012, 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/flash_nor.h>
|
||||
#include <drivers/power.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <sys.h>
|
||||
#include <sys/boot.h>
|
||||
#include <sys/menu.h>
|
||||
#include <sys/task.h>
|
||||
#include <target.h>
|
||||
|
||||
MIB_CONSTANT(kMIBTargetAcceptGlobalTicket, kOIDTypeBoolean, true);
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
|
||||
#if !RELEASE_BUILD
|
||||
// <rdar://problem/10967375> API for B137 test harness to control G1 CLK0_OUT state
|
||||
gpio_configure(GPIO_CLK0_OUT, GPIO_CFG_FUNC0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
switch (target) {
|
||||
case BOOT_DARWIN: {
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
; // do nothing
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if !PRODUCT_LLB
|
||||
bool target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
#if DEVELOPMENT_BUILD || DEBUG_BUILD
|
||||
env_set("boot-args", "debug=0x14e serial=3 rd=md0", 0);
|
||||
env_set("debug-uarts", "3", 0);
|
||||
#else
|
||||
env_set("boot-args", "rd=md0", 0);
|
||||
#endif
|
||||
env_set("auto-boot", "false", 0);
|
||||
env_set("idle-off", "false", 0);
|
||||
}
|
||||
|
||||
#endif // WITH_ENV
|
||||
|
||||
// Dummy function to make LIBENV happy.
|
||||
int syscfgCopyDataForTag(u_int32_t tag, u_int8_t *buffer, size_t size) {
|
||||
#pragma unused ( tag, buffer, size )
|
||||
return -1;
|
||||
}
|
||||
|
||||
#if !WITH_HW_POWER
|
||||
|
||||
bool power_needs_precharge(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
void power_cancel_buttonwait(void)
|
||||
{
|
||||
}
|
||||
|
||||
bool power_do_chargetrap(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
bool power_is_suspended(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
void power_will_resume(void)
|
||||
{
|
||||
}
|
||||
|
||||
bool power_has_usb(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
int power_read_dock_id(unsigned *id)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
u_int32_t power_get_boot_battery_level(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int power_get_nvram(u_int8_t key, u_int8_t *data)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int power_set_nvram(u_int8_t key, u_int8_t data)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int power_set_soc_voltage(unsigned mv, int override)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
bool force_usb_power = false;
|
||||
|
||||
void power_set_usb_state(bool configured, bool suspended)
|
||||
{
|
||||
}
|
||||
|
||||
int power_backlight_enable(u_int32_t backlight_level)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* ! WITH_HW_POWER */
|
||||
@@ -0,0 +1,32 @@
|
||||
# Copyright (C) 2007 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
TARGET_DREX_CLK_RATIO=2 \
|
||||
TARGET_DREX_TIMING_AREF=0x0000005D \
|
||||
TARGET_DREX_TIMING_ROW=0x34488611 \
|
||||
TARGET_DREX_TIMING_DATA=0x36330306 \
|
||||
TARGET_DREX_TIMING_POWER=0x50380335 \
|
||||
TARGET_DREX_QOS_TIDEMARK=9 \
|
||||
TARGET_DREX_QOS_ACCESS=12 \
|
||||
TARGET_USB_DEVICE_SELF_POWERED=1 \
|
||||
WITH_BRIEF_BOOT_BANNER=1
|
||||
|
||||
ifeq ($(APPLICATION),iBoot)
|
||||
OPTIONS += \
|
||||
DISABLE_CLEAR_MEMORY=1
|
||||
endif
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/display_get_info.o
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The amg_param struct is defined in drivers/apple/amg/amg.h, and this
|
||||
* file should only by included from amg.c.
|
||||
*/
|
||||
|
||||
static const struct amg_params amc_phy_params = {
|
||||
.flags = FLAG_AMG_PARAM_CAL_STATIC,
|
||||
.core_config = 0x00001053,
|
||||
.read_latency = 0x0000669b,
|
||||
.gate_offset = 0x08080808,
|
||||
};
|
||||
@@ -0,0 +1,251 @@
|
||||
/*
|
||||
* Copyright (C) 2010,2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_DISPLAY_GAMMA_TABLES_H
|
||||
#define __TARGET_DISPLAY_GAMMA_TABLES_H
|
||||
|
||||
/* K9x display gamma tables */
|
||||
|
||||
static const display_gamma_table ipad2_display_gamma_tables[] =
|
||||
{
|
||||
{
|
||||
0x00960C49, 0x00FFFF7F, // LGD P5 table V0
|
||||
{
|
||||
0x62, 0xca, 0x1d, 0xd0, 0x1d, 0x00, 0x00, 0x0d,
|
||||
0x0d, 0x00, 0xc0, 0x1d, 0x77, 0xd3, 0x1d, 0x1c,
|
||||
0xc7, 0x71, 0x1c, 0x00, 0x70, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0xd0, 0x40, 0x03, 0x0d, 0x34, 0x34,
|
||||
0x0d, 0x0d, 0x00, 0x1c, 0x77, 0xdc, 0x71, 0x1c,
|
||||
0xc7, 0x71, 0xc7, 0xc1, 0x01, 0x70, 0xc0, 0x01,
|
||||
0x07, 0xc0, 0x01, 0x40, 0x00, 0x1c, 0x00, 0x1c,
|
||||
0x1c, 0xc7, 0xdd, 0x4d, 0xd3, 0x4d, 0x00, 0x00,
|
||||
0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x62, 0xca, 0x04, 0x40, 0xc7, 0x01, 0xd0, 0xd0,
|
||||
0x00, 0x00, 0x70, 0x77, 0x37, 0xdd, 0x74, 0xdc,
|
||||
0x71, 0xdc, 0x1d, 0x07, 0x00, 0x1c, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0xd0, 0xd0, 0x40, 0x03, 0x0d,
|
||||
0x4d, 0x43, 0x03, 0x1c, 0xc7, 0x1d, 0x77, 0x1c,
|
||||
0x07, 0xc7, 0xc1, 0x71, 0x00, 0x70, 0x00, 0x70,
|
||||
0x00, 0x00, 0x1c, 0xd0, 0x01, 0x00, 0x00, 0xc0,
|
||||
0x01, 0x07, 0x77, 0x77, 0x77, 0x13, 0x07, 0x00,
|
||||
0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x62, 0xca, 0x04, 0x40, 0x77, 0x00, 0x40, 0x43,
|
||||
0x03, 0x0d, 0x07, 0x07, 0xc7, 0x1d, 0x07, 0x07,
|
||||
0x70, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0,
|
||||
0x00, 0x0d, 0xd0, 0x34, 0x34, 0x0d, 0x4d, 0xd3,
|
||||
0x0d, 0x0d, 0xc0, 0x71, 0x1c, 0xc7, 0x71, 0x70,
|
||||
0x70, 0x1c, 0x1c, 0x00, 0x07, 0xc0, 0x01, 0x70,
|
||||
0x00, 0x1c, 0x00, 0x01, 0x1c, 0x00, 0x1c, 0x77,
|
||||
0xdc, 0x4d, 0x03, 0x0d, 0x00, 0x34, 0x4d, 0xd3,
|
||||
0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
}
|
||||
},
|
||||
{
|
||||
0x00950C49, 0x00FFFF7F, // LGD P6 table V0 (same as P5)
|
||||
{
|
||||
0x62, 0xca, 0x1d, 0xd0, 0x1d, 0x00, 0x00, 0x0d,
|
||||
0x0d, 0x00, 0xc0, 0x1d, 0x77, 0xd3, 0x1d, 0x1c,
|
||||
0xc7, 0x71, 0x1c, 0x00, 0x70, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0xd0, 0x40, 0x03, 0x0d, 0x34, 0x34,
|
||||
0x0d, 0x0d, 0x00, 0x1c, 0x77, 0xdc, 0x71, 0x1c,
|
||||
0xc7, 0x71, 0xc7, 0xc1, 0x01, 0x70, 0xc0, 0x01,
|
||||
0x07, 0xc0, 0x01, 0x40, 0x00, 0x1c, 0x00, 0x1c,
|
||||
0x1c, 0xc7, 0xdd, 0x4d, 0xd3, 0x4d, 0x00, 0x00,
|
||||
0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x62, 0xca, 0x04, 0x40, 0xc7, 0x01, 0xd0, 0xd0,
|
||||
0x00, 0x00, 0x70, 0x77, 0x37, 0xdd, 0x74, 0xdc,
|
||||
0x71, 0xdc, 0x1d, 0x07, 0x00, 0x1c, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0xd0, 0xd0, 0x40, 0x03, 0x0d,
|
||||
0x4d, 0x43, 0x03, 0x1c, 0xc7, 0x1d, 0x77, 0x1c,
|
||||
0x07, 0xc7, 0xc1, 0x71, 0x00, 0x70, 0x00, 0x70,
|
||||
0x00, 0x00, 0x1c, 0xd0, 0x01, 0x00, 0x00, 0xc0,
|
||||
0x01, 0x07, 0x77, 0x77, 0x77, 0x13, 0x07, 0x00,
|
||||
0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x62, 0xca, 0x04, 0x40, 0x77, 0x00, 0x40, 0x43,
|
||||
0x03, 0x0d, 0x07, 0x07, 0xc7, 0x1d, 0x07, 0x07,
|
||||
0x70, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0,
|
||||
0x00, 0x0d, 0xd0, 0x34, 0x34, 0x0d, 0x4d, 0xd3,
|
||||
0x0d, 0x0d, 0xc0, 0x71, 0x1c, 0xc7, 0x71, 0x70,
|
||||
0x70, 0x1c, 0x1c, 0x00, 0x07, 0xc0, 0x01, 0x70,
|
||||
0x00, 0x1c, 0x00, 0x01, 0x1c, 0x00, 0x1c, 0x77,
|
||||
0xdc, 0x4d, 0x03, 0x0d, 0x00, 0x34, 0x4d, 0xd3,
|
||||
0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
}
|
||||
},
|
||||
{
|
||||
0x00970C49, 0x00FFFF7F, // LGD P3 table V0
|
||||
{
|
||||
0x62, 0xca, 0x04, 0x00, 0x71, 0x00, 0x40, 0x03,
|
||||
0x0d, 0x00, 0x70, 0xdc, 0xdd, 0xdd, 0x1d, 0x07,
|
||||
0x07, 0xc7, 0x01, 0xd7, 0x00, 0x00, 0x00, 0xd0,
|
||||
0xd0, 0x40, 0x43, 0x37, 0xdd, 0x34, 0xdd, 0x74,
|
||||
0x37, 0x0d, 0x00, 0xc7, 0x1d, 0x77, 0x1c, 0x1c,
|
||||
0x1c, 0xc7, 0xc1, 0x01, 0x70, 0xc0, 0x01, 0x07,
|
||||
0xc0, 0x01, 0x47, 0x07, 0x00, 0x1c, 0xc0, 0x1d,
|
||||
0xc7, 0xdd, 0x40, 0x03, 0xd0, 0x40, 0x77, 0x77,
|
||||
0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x62, 0xca, 0x74, 0xd0, 0x04, 0x07, 0x00, 0x0d,
|
||||
0x00, 0x00, 0x70, 0x77, 0x77, 0xd3, 0xdd, 0x71,
|
||||
0x70, 0x1c, 0xc7, 0x01, 0x00, 0x00, 0x00, 0x40,
|
||||
0x03, 0x0d, 0x34, 0x74, 0xd3, 0x34, 0xdd, 0x74,
|
||||
0x77, 0xd3, 0x00, 0xc7, 0x71, 0xc7, 0x71, 0x70,
|
||||
0x70, 0x1c, 0x1c, 0x70, 0x00, 0x70, 0x00, 0x70,
|
||||
0x00, 0x70, 0x00, 0x04, 0x00, 0x00, 0x70, 0x70,
|
||||
0x1c, 0x77, 0x37, 0x34, 0xd0, 0xd0, 0xdd, 0xdd,
|
||||
0xdd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x62, 0xca, 0x74, 0x0d, 0x1d, 0x07, 0xd0, 0x40,
|
||||
0x03, 0x00, 0x00, 0x07, 0x1c, 0xc7, 0x01, 0xc0,
|
||||
0x01, 0xc0, 0x01, 0x0d, 0x34, 0x00, 0x34, 0x4d,
|
||||
0x37, 0x4d, 0xd3, 0xdd, 0xdd, 0xdd, 0x1d, 0x77,
|
||||
0x37, 0x7d, 0x70, 0x1c, 0x1c, 0xc7, 0x01, 0x07,
|
||||
0x1c, 0x1c, 0x00, 0x1c, 0xc0, 0x01, 0x1c, 0xc0,
|
||||
0x01, 0x1c, 0x1d, 0x00, 0x70, 0x70, 0xdc, 0x4d,
|
||||
0x37, 0x00, 0x00, 0x1c, 0x00, 0x1c, 0x00, 0x1c,
|
||||
0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
}
|
||||
},
|
||||
{
|
||||
0x00E40C49, 0x00FFFF7F, // Samsung 6mask table V0
|
||||
{
|
||||
0x62, 0xca, 0x74, 0xd0, 0x04, 0x07, 0x00, 0x0d,
|
||||
0xd0, 0x00, 0x1c, 0x1c, 0x1c, 0x77, 0x70, 0x00,
|
||||
0x00, 0x00, 0x00, 0x4d, 0x43, 0x43, 0x43, 0xd3,
|
||||
0x40, 0x03, 0x0d, 0x34, 0x00, 0x0d, 0x00, 0x34,
|
||||
0x00, 0x00, 0x34, 0x00, 0x34, 0x00, 0x1c, 0x70,
|
||||
0x70, 0x1c, 0x1c, 0x07, 0xc7, 0x71, 0x77, 0x77,
|
||||
0xd3, 0x74, 0xd3, 0x01, 0x00, 0x00, 0x40, 0x43,
|
||||
0x77, 0x77, 0x77, 0x07, 0xc7, 0xc1, 0x41, 0x43,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x62, 0xca, 0x04, 0x00, 0x1d, 0xb0, 0x32, 0x00,
|
||||
0x0d, 0x40, 0x1f, 0x70, 0xdc, 0x71, 0xc7, 0x01,
|
||||
0x1c, 0x00, 0x07, 0x40, 0x43, 0x03, 0x34, 0x40,
|
||||
0x03, 0x0d, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x70,
|
||||
0x70, 0x1c, 0xc7, 0x71, 0x1c, 0xc7, 0x71, 0x77,
|
||||
0x77, 0xd3, 0x4d, 0x77, 0x07, 0x00, 0x00, 0xd0,
|
||||
0x74, 0x77, 0x1c, 0x07, 0x1c, 0x00, 0xd0, 0xdd,
|
||||
0x71, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x62, 0xca, 0x74, 0x00, 0xdd, 0x01, 0x00, 0x00,
|
||||
0x34, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x34,
|
||||
0x40, 0x03, 0x74, 0x37, 0xdd, 0x74, 0x37, 0xdd,
|
||||
0x34, 0x4d, 0xd3, 0xd0, 0x40, 0x43, 0x03, 0x0d,
|
||||
0xd0, 0x40, 0x03, 0x0d, 0x34, 0x1c, 0xc0, 0x01,
|
||||
0x07, 0x1c, 0x1c, 0x1c, 0x1c, 0x77, 0x37, 0xdd,
|
||||
0x4d, 0x77, 0x07, 0x00, 0x00, 0x00, 0x40, 0xd3,
|
||||
0x34, 0x34, 0xdd, 0x34, 0x4d, 0xd3, 0x34, 0xdd,
|
||||
0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
}
|
||||
},
|
||||
{
|
||||
0x00E30C49, 0x00FFFF7F, // Samsung 5mask table V0
|
||||
{
|
||||
0x22, 0xce, 0x4d, 0x07, 0xd0, 0x74, 0x1c, 0x1c,
|
||||
0x1c, 0x1c, 0xd3, 0xdd, 0xdd, 0x34, 0xdd, 0x74,
|
||||
0x07, 0x1c, 0x1c, 0x1c, 0x00, 0x0d, 0xd0, 0x00,
|
||||
0x34, 0x0d, 0x0d, 0x34, 0xd0, 0x40, 0x03, 0x34,
|
||||
0xd0, 0x40, 0x03, 0x34, 0x34, 0x0d, 0x0d, 0x00,
|
||||
0x00, 0x07, 0x00, 0x07, 0x00, 0x07, 0xc0, 0x71,
|
||||
0x1c, 0x77, 0xc7, 0x1d, 0x00, 0xd0, 0x00, 0x4d,
|
||||
0x07, 0x07, 0x1c, 0x00, 0x00, 0x00, 0xd0, 0x1d,
|
||||
0xc7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x22, 0xce, 0x4d, 0x07, 0x40, 0x77, 0x07, 0x07,
|
||||
0xc7, 0x71, 0x37, 0xdd, 0x74, 0xd3, 0x34, 0x74,
|
||||
0xc7, 0xc1, 0x71, 0x07, 0x07, 0x0d, 0x00, 0x40,
|
||||
0x03, 0x34, 0x40, 0x03, 0xd0, 0x00, 0x0d, 0x00,
|
||||
0x0d, 0xd0, 0x00, 0x34, 0xd0, 0xd0, 0x40, 0x03,
|
||||
0x00, 0x07, 0xc0, 0x01, 0x00, 0x1c, 0x00, 0x07,
|
||||
0xc7, 0x1d, 0x77, 0xdc, 0x41, 0x43, 0x43, 0xd3,
|
||||
0x71, 0x00, 0x1c, 0x00, 0x0d, 0xd0, 0xc4, 0x01,
|
||||
0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x22, 0xce, 0x0d, 0x01, 0x40, 0x13, 0x77, 0x70,
|
||||
0xc0, 0xc1, 0x1d, 0xc7, 0x71, 0xc7, 0xdd, 0x71,
|
||||
0x00, 0x00, 0x07, 0x00, 0x4d, 0xd3, 0xd0, 0x34,
|
||||
0x4d, 0x37, 0x4d, 0xd3, 0x34, 0x34, 0x34, 0x4d,
|
||||
0x43, 0xd3, 0xd0, 0x74, 0xd3, 0x34, 0x00, 0x00,
|
||||
0x00, 0x70, 0x00, 0x00, 0x00, 0x07, 0x70, 0xdc,
|
||||
0x1d, 0x77, 0x07, 0x00, 0x00, 0x0d, 0xd0, 0x74,
|
||||
0xdc, 0xdd, 0x1d, 0x77, 0xdc, 0x71, 0x1c, 0x77,
|
||||
0xdc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
}
|
||||
},
|
||||
{
|
||||
0x00890C49, 0x00FFFF7F, // CMI T1 table V0
|
||||
{
|
||||
0x62, 0xca, 0x01, 0x74, 0x00, 0xd0, 0xdd, 0x1d,
|
||||
0x77, 0x4c, 0x43, 0x03, 0x40, 0xd3, 0xdd, 0xdd,
|
||||
0x1d, 0xc7, 0xc1, 0x1d, 0xc7, 0x71, 0x77, 0x77,
|
||||
0x77, 0xd3, 0x34, 0x0d, 0x0d, 0x0d, 0x34, 0xd0,
|
||||
0x00, 0x34, 0x00, 0x70, 0x70, 0xc7, 0x71, 0xdc,
|
||||
0x1d, 0x77, 0x77, 0x77, 0x43, 0x03, 0xd0, 0x00,
|
||||
0xd0, 0x74, 0x1c, 0x77, 0xdc, 0xc1, 0x01, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x03, 0x4d, 0xd3,
|
||||
0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x62, 0xca, 0x01, 0x74, 0x00, 0xd0, 0x74, 0xdc,
|
||||
0x71, 0xd3, 0x34, 0x00, 0xd0, 0xd0, 0xdd, 0xdd,
|
||||
0xdd, 0x1d, 0x1c, 0xc7, 0x1d, 0xc7, 0xdd, 0xdd,
|
||||
0xdd, 0x74, 0x43, 0xd3, 0x34, 0x34, 0x34, 0x40,
|
||||
0x03, 0x34, 0x00, 0xc0, 0x71, 0x1c, 0xc7, 0x71,
|
||||
0xc7, 0xdd, 0x1d, 0x37, 0x0d, 0x34, 0x40, 0x03,
|
||||
0xd0, 0x74, 0x1c, 0x77, 0x1c, 0x07, 0x00, 0x07,
|
||||
0x00, 0x00, 0x00, 0x34, 0x00, 0x40, 0xd3, 0x34,
|
||||
0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x62, 0xca, 0x01, 0x74, 0x00, 0xd0, 0x74, 0xdc,
|
||||
0x71, 0x77, 0xd3, 0xd0, 0xd0, 0x74, 0xdc, 0x1d,
|
||||
0x77, 0x70, 0x70, 0x70, 0x1c, 0x1c, 0x77, 0xdc,
|
||||
0xdd, 0x4d, 0x37, 0x4d, 0xd3, 0x34, 0x34, 0x0d,
|
||||
0x0d, 0x34, 0x00, 0x70, 0x1c, 0x07, 0xc7, 0x1d,
|
||||
0xc7, 0x1d, 0x77, 0x37, 0x34, 0xd0, 0x00, 0x0d,
|
||||
0x74, 0xc7, 0x71, 0xc7, 0x71, 0x00, 0x07, 0x00,
|
||||
0x1c, 0x00, 0x70, 0x00, 0x1c, 0x00, 0xc0, 0x01,
|
||||
0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
}
|
||||
},
|
||||
{
|
||||
0x00900C49, 0x00FFFF7F, // CMI T1x table V0
|
||||
{
|
||||
0x26, 0x11, 0x07, 0xd0, 0x1d, 0x00, 0x00, 0xdd,
|
||||
0xdd, 0xc1, 0x01, 0x07, 0x1c, 0x1c, 0xc7, 0xdd,
|
||||
0x34, 0x34, 0xd0, 0x00, 0x0d, 0x34, 0x00, 0x0d,
|
||||
0x00, 0xd0, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00,
|
||||
0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x1c,
|
||||
0x00, 0x00, 0x00, 0x70, 0xc0, 0xc1, 0xc1, 0xc1,
|
||||
0xc1, 0x71, 0x1c, 0x77, 0xdc, 0x71, 0x1c, 0x07,
|
||||
0xc7, 0x71, 0x70, 0x1c, 0x1c, 0x40, 0x1c, 0x70,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x26, 0xd1, 0x1d, 0xd0, 0x74, 0x1c, 0x00, 0x34,
|
||||
0x4d, 0xc7, 0x1d, 0xc7, 0x1d, 0x77, 0x77, 0xd3,
|
||||
0xd0, 0x00, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x07, 0x70,
|
||||
0xc0, 0x01, 0x00, 0x07, 0x70, 0x00, 0x07, 0xc0,
|
||||
0x01, 0x1c, 0xc0, 0x01, 0x07, 0x1c, 0xc7, 0x71,
|
||||
0x1c, 0x77, 0xdc, 0x1d, 0x77, 0x77, 0x77, 0xc7,
|
||||
0xdd, 0x71, 0x77, 0xdc, 0x71, 0xc7, 0x1d, 0x00,
|
||||
0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x26, 0x41, 0x77, 0x00, 0x74, 0x77, 0x00, 0x00,
|
||||
0x40, 0xd3, 0x4d, 0x77, 0x37, 0xdd, 0x34, 0x0d,
|
||||
0x40, 0x03, 0x00, 0x00, 0x00, 0x1c, 0x00, 0xc0,
|
||||
0x01, 0x70, 0x00, 0x1c, 0x70, 0xc0, 0xc1, 0x71,
|
||||
0x1c, 0xc7, 0xc1, 0xc1, 0x71, 0x1c, 0xc7, 0xc1,
|
||||
0x71, 0x1c, 0x1c, 0x77, 0x1c, 0x77, 0xdc, 0xdd,
|
||||
0x31, 0xdd, 0xdd, 0x4d, 0x37, 0x4d, 0x43, 0xd3,
|
||||
0x34, 0x4d, 0xd3, 0xd0, 0x34, 0x34, 0x34, 0x34,
|
||||
0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
}
|
||||
},
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_GPIODEF_H
|
||||
#define __TARGET_GPIODEF_H
|
||||
|
||||
/* K93 specific gpio -> pin mappings */
|
||||
|
||||
#include <platform/gpio.h>
|
||||
|
||||
/* define target-specific gpios in a generic fashion here. */
|
||||
#define GPIO_LCD_RST GPIO(17, 7)
|
||||
#define GPIO_LCD_RST_POLARITY (0)
|
||||
#define GPIO_LCD_PWR_EN GPIO(18, 1)
|
||||
|
||||
#define GPIO_RINGER_AB GPIO( 6, 2)
|
||||
|
||||
#define POWER_GPIO_BATTERY_SWI (5)
|
||||
#define POWER_GPIO_BATTERY_SWI_CONFIG_OUTPUT 0x03
|
||||
#define POWER_GPIO_BATTERY_SWI_CONFIG_INPUT 0xD8
|
||||
|
||||
/* Board Revision */
|
||||
#define GPIO_BOARD_REV0 GPIO( 5, 0)
|
||||
#define GPIO_BOARD_REV1 GPIO( 5, 1)
|
||||
#define GPIO_BOARD_REV2 GPIO( 5, 2)
|
||||
|
||||
/* which IICs to initialize */
|
||||
#define IICS_MASK (7)
|
||||
|
||||
/* D1946 watchdog tickle, 'KEEPACT' */
|
||||
#define GPIO_WDOG_TICKLE GPIO(2, 3)
|
||||
|
||||
#endif /* ! __TARGET_GPIODEF_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,414 @@
|
||||
/*
|
||||
* Copyright (C) 2009-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* Default K93/K94 SoC Pin Configuration, v1.2 */
|
||||
|
||||
#if PIN_CFG_AP
|
||||
#define HI_DRIVE_STR DRIVE_X3
|
||||
#define GPIO_DRIVE_STR DRIVE_X2
|
||||
#elif PIN_CFG_DEV
|
||||
#define HI_DRIVE_STR DRIVE_X4
|
||||
#define GPIO_DRIVE_STR DRIVE_X2
|
||||
#endif
|
||||
|
||||
#define BB_DRIVE_STR HI_DRIVE_STR
|
||||
#define BT_DRIVE_STR HI_DRIVE_STR
|
||||
#define SWI_DRIVE_STR HI_DRIVE_STR
|
||||
#define GPS_DRIVE_STR HI_DRIVE_STR
|
||||
#define FMI_DRIVE_STR HI_DRIVE_STR
|
||||
#define SPI_DRIVE_STR HI_DRIVE_STR
|
||||
#define SPI_CS_DRIVE_STR GPIO_DRIVE_STR
|
||||
#define I2C_DRIVE_STR HI_DRIVE_STR
|
||||
#define DWI_DRIVE_STR HI_DRIVE_STR
|
||||
#define I2S_DRIVE_STR HI_DRIVE_STR
|
||||
#define SDIO_DRIVE_STR HI_DRIVE_STR
|
||||
#define CAM_DRIVE_STR HI_DRIVE_STR
|
||||
#define UART_DRIVE_STR HI_DRIVE_STR
|
||||
|
||||
#if PIN_CFG_AP
|
||||
static const u_int32_t gpio_default_cfg_ap[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
#elif PIN_CFG_DEV
|
||||
static const u_int32_t gpio_default_cfg_dev[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
#endif
|
||||
/* Port 0 */
|
||||
CFG_IN, // GPIO0 -> MENU_KEY (REQUEST_DFU2)
|
||||
CFG_IN, // GPIO1 -> HOLD_KEY (REQUEST_DFU1)
|
||||
CFG_DISABLED, // GPIO2 ->
|
||||
CFG_DISABLED, // GPIO3 ->
|
||||
CFG_DISABLED, // GPIO4 ->
|
||||
CFG_DISABLED, // GPIO5 ->
|
||||
CFG_DISABLED, // GPIO6 ->
|
||||
CFG_OUT_0 | GPIO_DRIVE_STR, // GPIO7 -> PM_BT_WAKE
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED, // GPIO8 ->
|
||||
#if SUB_TARGET_K93
|
||||
CFG_DISABLED, // GPIO9 ->
|
||||
CFG_DISABLED, // GPIO10 ->
|
||||
CFG_DISABLED, // GPIO11 ->
|
||||
CFG_DISABLED, // GPIO12 ->
|
||||
#else
|
||||
#if SUB_TARGET_K94
|
||||
CFG_OUT_0 | GPIO_DRIVE_STR, // GPIO9 -> PM_RADIO_ON
|
||||
#else
|
||||
CFG_IN, // GPIO9 -> PM_RADIO_ON
|
||||
#endif
|
||||
CFG_DISABLED, // GPIO10 ->
|
||||
CFG_IN, // GPIO11 -> RST_DET_L
|
||||
CFG_IN, // GPIO12 -> SPI_IPC_SRDY
|
||||
#endif
|
||||
CFG_IN | PULL_UP, // GPIO13 -> IRQ_PMU_L
|
||||
CFG_DISABLED, // GPIO14 ->
|
||||
CFG_IN | PULL_UP, // GPIO15 -> IRQ_CODEC_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // GPIO16 -> BOARD_ID[3]
|
||||
CFG_IN | PULL_DOWN, // GPIO17 -> IRQ_GYRO_INT2
|
||||
CFG_DISABLED, // GPIO18 -> BOOT_CONFIG[0]
|
||||
CFG_OUT_0 | GPIO_DRIVE_STR, // GPIO19 -> PM_KEEPACT
|
||||
CFG_DISABLED, // GPIO20 ->
|
||||
CFG_IN | PULL_UP, // GPIO21 -> IRQ_GRAPE_HOST_INT_L
|
||||
CFG_DISABLED, // GPIO22 ->
|
||||
#if SUB_TARGET_K93
|
||||
CFG_DISABLED, // GPIO23 ->
|
||||
#else
|
||||
CFG_IN, // GPIO23 -> GPS_SYNC
|
||||
#endif
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // GPIO24 -> GSM_TXBURST_IND
|
||||
CFG_DISABLED, // GPIO25 -> BOOT_CONFIG[1]
|
||||
CFG_IN, // GPIO26 -> FORCE_DFU
|
||||
CFG_OUT_0, // GPIO27 -> DFU_STATUS
|
||||
CFG_DISABLED, // GPIO28 -> BOOT_CONFIG[2]
|
||||
CFG_DISABLED, // GPIO29 -> BOOT_CONFIG[3]
|
||||
#if SUB_TARGET_K93
|
||||
CFG_DISABLED, // GPIO30 ->
|
||||
CFG_DISABLED, // GPIO31 ->
|
||||
#else
|
||||
CFG_OUT_1 | GPIO_DRIVE_STR, // GPIO30 -> RST_GPS_L
|
||||
CFG_OUT_0 | GPIO_DRIVE_STR, // GPIO31 -> PM_GPS_STANDBY
|
||||
#endif
|
||||
|
||||
/* Port 4 */
|
||||
#if SUB_TARGET_K93
|
||||
CFG_DISABLED, // GPIO32 ->
|
||||
#else
|
||||
CFG_IN, // GPIO32 -> IRQ_PROX_INT_L
|
||||
#endif
|
||||
CFG_IN | PULL_DOWN, // GPIO33 -> IRQ_GYRO_INT1
|
||||
CFG_DISABLED, // GPIO34 -> IRQ_GPS_INT_L
|
||||
CFG_DISABLED, // GPIO35 ->
|
||||
CFG_IN | PULL_UP, // GPIO36 -> IRQ_ACCEL_INT1_L
|
||||
CFG_IN | PULL_UP, // GPIO37 -> IRQ_ALS_INT_L
|
||||
CFG_IN | PULL_UP, // GPIO38 -> IRQ_ACCEL_INT2_L
|
||||
CFG_OUT_0, // GPIO39 -> AUD_SPKRAMP_MUTE_L
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED, // EHCI_PORT_PWR[0] -> BOARD_REV0
|
||||
CFG_DISABLED, // EHCI_PORT_PWR[1] -> BOARD_REV1
|
||||
CFG_DISABLED, // EHCI_PORT_PWR[2] -> BOARD_REV2
|
||||
#if SUB_TARGET_K93
|
||||
CFG_DISABLED, // UART1_TXD ->
|
||||
CFG_DISABLED, // UART1_RXD ->
|
||||
CFG_DISABLED, // UART1_RTSN ->
|
||||
CFG_DISABLED, // UART1_CTSN ->
|
||||
CFG_DISABLED, // UART2_TXD ->
|
||||
#else
|
||||
#if SUB_TARGET_K94
|
||||
CFG_FUNC0 | BB_DRIVE_STR, // UART1_TXD -> UART_AP_1_TXD (BB USART)
|
||||
// <rdar://problem/11526274> Add pullup to BB UART RX pin to work around glitch during baseband updates (Sundance)
|
||||
CFG_FUNC0 | PULL_UP, // UART1_RXD -> UART_AP_1_RXD
|
||||
#else
|
||||
CFG_OUT_0 | BB_DRIVE_STR, // UART1_TXD -> UART_AP_1_TXD (BB USART)
|
||||
CFG_FUNC0, // UART1_RXD -> UART_AP_1_RXD
|
||||
#endif
|
||||
CFG_FUNC0 | BB_DRIVE_STR, // UART1_RTSN -> UART_AP_1_RTS_L
|
||||
CFG_FUNC0, // UART1_CTSN -> UART_AP_1_CTS_L
|
||||
CFG_FUNC0 | BB_DRIVE_STR, // UART2_TXD -> UART_AP_2_TXD (BB UMTS)
|
||||
#endif
|
||||
|
||||
/* Port 6 */
|
||||
#if SUB_TARGET_K93
|
||||
CFG_DISABLED, // UART2_RXD ->
|
||||
CFG_DISABLED, // UART2_RTSN ->
|
||||
#else
|
||||
CFG_FUNC0, // UART2_RXD -> UART_AP_2_RXD
|
||||
#if SUB_TARGET_K94
|
||||
CFG_OUT_1 | GPIO_DRIVE_STR, // UART2_RTSN -> RST_BB_L
|
||||
#else
|
||||
CFG_IN, // UART2_RTSN -> RST_BB_L
|
||||
#endif
|
||||
#endif
|
||||
CFG_IN, // UART2_CTSN -> SRL_L
|
||||
CFG_FUNC0 | BT_DRIVE_STR, // UART3_TXD -> UART_AP_3_TXD (BT)
|
||||
CFG_FUNC0, // UART3_RXD -> UART_AP_3_RXD
|
||||
CFG_OUT_1 | BT_DRIVE_STR, // UART3_RTSN -> UART_AP_3_RTS_L
|
||||
CFG_FUNC0, // UART3_CTSN -> UART_AP_3_CTS_L
|
||||
CFG_FUNC0 | SWI_DRIVE_STR, // UART5_RTXD -> BATTERY_SWI
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED, // UART6_TXD ->
|
||||
CFG_IN | PULL_UP, // UART6_RXD -> AUD_VOL_UP_L
|
||||
#if SUB_TARGET_K95
|
||||
CFG_OUT_0, // UART6_RTSN -> IPC_GPIO
|
||||
#else
|
||||
CFG_DISABLED, // UART6_RTSN ->
|
||||
#endif
|
||||
CFG_IN | PULL_UP, // UART6_CTSN -> AUD_VOL_DOWN_L
|
||||
#if SUB_TARGET_K93
|
||||
CFG_DISABLED, // UART4_TXD -> UART_AP_4_TXD (GPS)
|
||||
CFG_DISABLED, // UART4_RXD -> UART_AP_4_RXD
|
||||
CFG_DISABLED, // UART4_RTSN -> UART_AP_4_RTS_L
|
||||
CFG_DISABLED, // UART4_CTSN -> UART_AP_4_CTS_L
|
||||
#else
|
||||
CFG_FUNC0 | GPS_DRIVE_STR, // UART4_TXD -> UART_AP_4_TXD (GPS)
|
||||
CFG_FUNC0, // UART4_RXD -> UART_AP_4_RXD
|
||||
CFG_FUNC0 | GPS_DRIVE_STR, // UART4_RTSN -> UART_AP_4_RTS_L
|
||||
CFG_FUNC0, // UART4_CTSN -> UART_AP_4_CTS_L
|
||||
#endif
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN3 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN2 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN1 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN0 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CLE ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_ALE ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_REN ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_WEN ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO7 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO6 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO5 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO4 ->
|
||||
CFG_DISABLED, // FMI0_DQS ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO3 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO2 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO1 ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO0 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN3 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN2 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN1 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN0 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CLE ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_ALE ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_REN ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_WEN ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO7 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO6 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO5 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO4 ->
|
||||
CFG_DISABLED, // FMI1_DQS ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO3 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO2 ->
|
||||
|
||||
/* Port 12 */
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO1 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO0 ->
|
||||
CFG_DISABLED, // FMI2_CEN3 ->
|
||||
CFG_DISABLED, // FMI2_CEN2 ->
|
||||
CFG_DISABLED, // FMI2_CEN1 ->
|
||||
CFG_DISABLED, // FMI2_CEN0 ->
|
||||
CFG_DISABLED, // FMI2_CLE ->
|
||||
CFG_DISABLED, // FMI2_ALE ->
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // FMI2_REN ->
|
||||
CFG_DISABLED, // FMI2_WEN ->
|
||||
CFG_DISABLED, // FMI2_IO7 ->
|
||||
CFG_DISABLED, // FMI2_IO6 ->
|
||||
CFG_DISABLED, // FMI2_IO5 ->
|
||||
CFG_DISABLED, // FMI2_IO4 ->
|
||||
CFG_DISABLED, // FMI2_DQS ->
|
||||
CFG_DISABLED, // FMI2_IO3 ->
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // FMI2_IO2 ->
|
||||
CFG_DISABLED, // FMI2_IO1 ->
|
||||
CFG_DISABLED, // FMI2_IO0 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN7 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN6 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN5 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN4 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN7 ->
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN6 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN5 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN4 ->
|
||||
CFG_DISABLED, // FMI3_CEN3 ->
|
||||
CFG_DISABLED, // FMI3_CEN2 ->
|
||||
CFG_DISABLED, // FMI3_CEN1 ->
|
||||
CFG_DISABLED, // FMI3_CEN0 ->
|
||||
CFG_DISABLED, // FMI3_CLE ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED, // FMI3_ALE ->
|
||||
CFG_DISABLED, // FMI3_REN ->
|
||||
CFG_DISABLED, // FMI3_WEN ->
|
||||
CFG_DISABLED, // FMI3_IO7 ->
|
||||
CFG_DISABLED, // FMI3_IO6 ->
|
||||
CFG_DISABLED, // FMI3_IO5 ->
|
||||
CFG_DISABLED, // FMI3_IO4 ->
|
||||
CFG_DISABLED, // FMI3_DQS ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // FMI3_IO3 ->
|
||||
CFG_DISABLED, // FMI3_IO2 ->
|
||||
CFG_DISABLED, // FMI3_IO1 ->
|
||||
CFG_DISABLED, // FMI3_IO0 ->
|
||||
CFG_OUT_1 | GPIO_DRIVE_STR, // FMI2_CEN7 -> GRAPE_FW_DNLD_EN_L
|
||||
CFG_DISABLED, // FMI2_CEN6 -> RST_GRAPE_L
|
||||
CFG_DISABLED, // FMI2_CEN5 ->
|
||||
CFG_OUT_0 | GPIO_DRIVE_STR, // FMI2_CEN4 -> RST_MLC_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED, // FMI3_CEN7 ->
|
||||
CFG_OUT_0 | GPIO_DRIVE_STR, // FMI3_CEN6 -> PM_MLC_PWR_EN
|
||||
CFG_OUT_0, // FMI3_CEN5 -> SD_RESET_L
|
||||
CFG_DISABLED, // FMI3_CEN4 ->
|
||||
CFG_DISABLED, // SPI3_MOSI ->
|
||||
CFG_DISABLED, // SPI3_MISO ->
|
||||
CFG_DISABLED, // SPI3_SCLK ->
|
||||
CFG_DISABLED, // SPI3_SSIN ->
|
||||
|
||||
/* Port 19 */
|
||||
CFG_FUNC0, // ISP0_PRE_FLASH ->
|
||||
CFG_FUNC0, // ISP0_FLASH ->
|
||||
CFG_FUNC0, // ISP1_PRE_FLASH ->
|
||||
CFG_FUNC0, // ISP1_FLASH ->
|
||||
CFG_FUNC0 | SPI_DRIVE_STR, // SPI1_SCLK -> SPI_GRAPE_SCLK
|
||||
CFG_FUNC0 | SPI_DRIVE_STR, // SPI1_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // SPI1_MISO -> SPI_GRAPE_MISO
|
||||
CFG_OUT_1 | SPI_CS_DRIVE_STR, // SPI1_SSIN -> SPI_GRAPE_CS_L
|
||||
|
||||
/* Port 20 */
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C2_SDA -> I2C2_SDA_3V0
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C2_SCL -> I2C2_SCL_3V0
|
||||
CFG_DISABLED, // SPI0_SCLK -> SPI0_SCLK/BOARD_ID[0]
|
||||
CFG_DISABLED, // SPI0_MOSI -> SPI0_MOSI/BOARD_ID[1]
|
||||
CFG_DISABLED, // SPI0_MISO -> SPI0_MISO/BOARD_ID[2]
|
||||
CFG_DISABLED, // SPI0_SSIN -> SPI0_SSIN
|
||||
#if SUB_TARGET_K93
|
||||
CFG_DISABLED, // SPI2_SCLK ->
|
||||
CFG_DISABLED, // SPI2_MOSI ->
|
||||
#else
|
||||
CFG_FUNC0 | SPI_DRIVE_STR, // SPI2_SCLK -> SPI_IPC_SCLK
|
||||
CFG_FUNC0 | SPI_DRIVE_STR, // SPI2_MOSI -> SPI_IPC_MOSI
|
||||
#endif
|
||||
|
||||
/* Port 21 */
|
||||
#if SUB_TARGET_K93
|
||||
CFG_DISABLED, // SPI2_MISO ->
|
||||
CFG_DISABLED, // SPI2_SSIN ->
|
||||
#else
|
||||
CFG_FUNC0, // SPI2_MISO -> SPI_IPC_MISO
|
||||
CFG_OUT_0 | SPI_CS_DRIVE_STR, // SPI2_SSIN -> SPI_IPC_MRDY
|
||||
#endif
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // ISP0_SDA -> ISP_AP_0_SDA
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // ISP0_SCL -> ISP_AP_0_SCL
|
||||
|
||||
/* Port 22 */
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // ISP1_SDA -> ISP_AP_1_SDA
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // ISP1_SCL -> ISP_AP_1_SCL
|
||||
CFG_FUNC0 | SDIO_DRIVE_STR, // SDIO_CLK ->
|
||||
CFG_FUNC0 | PULL_UP | SDIO_DRIVE_STR, // SDIO_CMD ->
|
||||
CFG_FUNC0 | PULL_UP | SDIO_DRIVE_STR, // SDIO_DATA0 ->
|
||||
CFG_FUNC0 | PULL_UP | SDIO_DRIVE_STR, // SDIO_DATA1 ->
|
||||
CFG_FUNC0 | PULL_UP | SDIO_DRIVE_STR, // SDIO_DATA2 ->
|
||||
CFG_FUNC0 | PULL_UP | SDIO_DRIVE_STR, // SDIO_DATA3 ->
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED, // MIPI_VSYNC ->
|
||||
CFG_DISABLED, // TMR32_PWM0 ->
|
||||
CFG_DISABLED, // TMR32_PWM1 ->
|
||||
CFG_DISABLED, // TMR32_PWM2 ->
|
||||
CFG_DISABLED, // SWI_DATA ->
|
||||
CFG_FUNC0 | PULL_DOWN, // DWI_DI ->
|
||||
CFG_FUNC0 | DWI_DRIVE_STR, // DWI_DO ->
|
||||
CFG_FUNC0 | DWI_DRIVE_STR, // DWI_CLK ->
|
||||
|
||||
/* Port 24 */
|
||||
CFG_OUT_0 | GPIO_DRIVE_STR, // SENSOR0_RST -> PM_REAR_CAM_SHUTDOWN
|
||||
CFG_OUT_0 | CAM_DRIVE_STR, // SENSOR0_CLK -> CLK_CAM_RF
|
||||
CFG_OUT_1 | GPIO_DRIVE_STR, // SENSOR1_RST -> PM_FRONT_CAM_SHUTDOWN
|
||||
CFG_OUT_0 | CAM_DRIVE_STR, // SENSOR1_CLK -> CLK_CAM_FF
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_MCK -> I2S_AP_0_MCL (codec ASP)
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_LRCK -> I2S_AP_0_LRCK
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_BCLK -> I2S_AP_0_BCLK
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_DOUT -> I2S_AP_0_DOUT
|
||||
|
||||
/* Port 25 */
|
||||
CFG_FUNC0, // I2S0_DIN -> I2S_AP_0_DIN
|
||||
CFG_DISABLED, // I2S1_MCK ->
|
||||
CFG_DISABLED, // I2S1_LRCK ->
|
||||
CFG_DISABLED, // I2S1_BCLK ->
|
||||
CFG_DISABLED, // I2S1_DOUT ->
|
||||
CFG_DISABLED, // I2S1_DIN ->
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_MCK -> I2S_AP_2_MCK (codec VSP)
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_LRCK -> I2S_AP_2_LRCK
|
||||
|
||||
/* Port 26 */
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_BCLK -> I2S_AP_2_BCLK
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_DOUT -> I2S_AP_2_DOUT
|
||||
CFG_FUNC0, // I2S2_DIN -> I2S_AP_2_DIN
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S3_MCK -> I2S_AP_3_MCK (codec XSP)
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S3_LRCK -> I2S_AP_3_LRCK
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S3_BCLK -> I2S_AP_3_BCLK
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S3_DOUT -> I2S_AP_3_DOUT
|
||||
CFG_FUNC0, // I2S3_DIN -> I2S_AP_3_DIN
|
||||
|
||||
/* Port 27 */
|
||||
CFG_DISABLED, // SPDIF ->
|
||||
CFG_OUT_0 | GPIO_DRIVE_STR, // GPIO217 -> PORT_DOCK_VIDEO_AMP_EN
|
||||
CFG_DISABLED, // GPIO218 ->
|
||||
CFG_FUNC0, // DP_HPD -> DP_AP_HPD
|
||||
CFG_FUNC0 | UART_DRIVE_STR, // UART0_TXD -> UART_AP_0_TXD
|
||||
CFG_FUNC0, // UART0_RXD -> UART_AP_0_RXD
|
||||
CFG_DISABLED, // TST_CLKOUT ->
|
||||
CFG_DISABLED, // TST_STPCLK ->
|
||||
|
||||
/* Port 28 */
|
||||
CFG_FUNC0, // WDOG -> AP_WDOG
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
};
|
||||
|
||||
#undef BB_DRIVE_STR
|
||||
#undef BT_DRIVE_STR
|
||||
#undef SWI_DRIVE_STR
|
||||
#undef GPS_DRIVE_STR
|
||||
#undef FMI_DRIVE_STR
|
||||
#undef SPI_DRIVE_STR
|
||||
#undef SPI_CS_DRIVE_STR
|
||||
#undef I2C_DRIVE_STR
|
||||
#undef DWI_DRIVE_STR
|
||||
#undef I2S_DRIVE_STR
|
||||
#undef SDIO_DRIVE_STR
|
||||
#undef CAM_DRIVE_STR
|
||||
#undef UART_DRIVE_STR
|
||||
#undef HI_DRIVE_STR
|
||||
#undef GPIO_DRIVE_STR
|
||||
@@ -0,0 +1,183 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_POWERCONFIG_H
|
||||
#define __TARGET_POWERCONFIG_H
|
||||
|
||||
#include <drivers/gasgauge.h>
|
||||
|
||||
/* configuration per target */
|
||||
|
||||
#define PMU_IIC_BUS 0
|
||||
|
||||
/* this configuration is very PMU specific and must be included exactly once in power.c */
|
||||
#ifdef POWERCONFIG_PMU_SETUP
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kDIALOG_LDO_CONTROL, 0x00 }, // Force bypass off
|
||||
{ PMU_IIC_BUS, kD1946_LDO1, 0x0A }, // PP3V0_GRAPE 3.00V
|
||||
{ PMU_IIC_BUS, kD1946_LDO2, 0x0A }, // PP1V7_VA_VCP 1.70V
|
||||
{ PMU_IIC_BUS, kD1946_LDO3, 0x0A }, // PP3V0_VIDEO 3.00V
|
||||
{ PMU_IIC_BUS, kD1946_LDO4, 0x18 }, // PP3V0_OPTICAL 3.00V
|
||||
{ PMU_IIC_BUS, kD1946_LDO5, 0x0E }, // PP3V2_SD 3.20V
|
||||
{ PMU_IIC_BUS, kD1946_LDO6, 0x10 }, // PP3V3_ACC 3.30V
|
||||
{ PMU_IIC_BUS, kD1946_LDO7, 0x0F }, // PP3V0_VIDEO_BUF 3.00V
|
||||
{ PMU_IIC_BUS, kD1946_LDO8, 0x18 }, // PP3V2_S2R_USBMUX 3.20V
|
||||
{ PMU_IIC_BUS, kD1946_LDO9, 0x12 }, // PP3V0_IO 3.00V
|
||||
{ PMU_IIC_BUS, kD1946_LDO10, 0x0A }, // PP3V2_SD_CTRL 3.00V
|
||||
{ PMU_IIC_BUS, kD1946_LDO11, 0x17 }, // PP2V85_CAM 2.85V
|
||||
{ PMU_IIC_BUS, kD1946_LDO12, 0x14 }, // PP1V1 1.10V
|
||||
{ PMU_IIC_BUS, kDIALOG_LDO_CONTROL, 0x00 }, // Leave bypass off
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kD1946_ACTIVE1, 0xDD }, // Everything but BUCK1 and LDO1
|
||||
{ PMU_IIC_BUS, kD1946_ACTIVE2, 0xF9 }, // Everything but SD and ACC
|
||||
{ PMU_IIC_BUS, kD1946_ACTIVE3, 0x61 }, // BUCK5, VBOOST_LCM, PP1V1
|
||||
{ PMU_IIC_BUS, kD1946_ACTIVE4, 0xA0 }, // CPU1V8_SW and CPU1V2_SW
|
||||
{ PMU_IIC_BUS, kD1946_LCM_CONTROL1, 0x02 }, // unused 5.10V
|
||||
{ PMU_IIC_BUS, kD1946_LCM_CONTROL2, 0x0E }, // unused 5.70V
|
||||
{ PMU_IIC_BUS, kD1946_LCM_CONTROL3, 0x00 }, // BB_VBUS_DET 5.00V
|
||||
{ PMU_IIC_BUS, kD1946_LCM_BST_CONTROL, 0x14 }, // VBOOST_LCM 6.00V
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_warm_init[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2, 0x10 }, // HIB_32K on, DWI off
|
||||
|
||||
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_A, 0x00 },
|
||||
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_B, 0x00 },
|
||||
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_C, 0x00 },
|
||||
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_D, 0x00 },
|
||||
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_E, 0x00 },
|
||||
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_F, 0x00 },
|
||||
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_G, 0x00 },
|
||||
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_H, 0x00 },
|
||||
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_K, 0x00 },
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_cold_init[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kD1946_BUCK4, 0x9B }, // BUCK4 1.21V
|
||||
{ PMU_IIC_BUS, kD1946_BUCK4_HIB, 0x9B }, // BUCK4_HIB 1.21V
|
||||
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_1, 0x11 }, // CLK_32K_PMU Out 0, Push-Pull, CPU_1V8
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_2, 0x49 }, // CLK_32K_WLAN CLK32K, Pull Down, VBUCK3
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_3, 0x09 }, // RST_BT_L Out 0, Push-Pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_4, 0x09 }, // RST_WLAN_L Out 0, Push-Pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_5, 0x09 }, // RST_BB_PMU_L Out 0, Push-pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_6, 0xDA }, // BATTERY_SWI In, F Edge, Wake, Pull Up, Disable Pull-Up
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_7, 0xBB }, // PM_BT_HOST_WAKE In, R Edge, Wake, Pull Down, Disable Pull-Up
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_8, 0xBB }, // PM_WLAN_HOST_WAKE In, R Edge, Wake, Pull Down, Disable Pull-Up
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_9, 0xBB }, // PM_BB_HOST_WAKE In, R Edge, Wake, Pull Down, Disable Pull-Up
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_10, 0xEA }, // AUD_MIK_HS1_INT_L In, Change, Wake, Pull Up, VBUCK3
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_11, 0x09 }, // DOCK_BB_EN Out 0, Push-Pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_12, 0x49 }, // CLK_32K_GPS CLK32K, Push-Pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_13, 0xB9 }, // SD_CON_CD In, R Edge, No Wake, Pull Down, Disable Pull-Up
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_14, 0xC8 }, // RST_L63_L In, F Edge, No Wake, Pull Up, VBUCK3
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_15, 0xFA }, // HALL_IRQ In, E Edge, Wake, Pull Up, Disable Pull-Up
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_16, 0xB9 }, // unused In, R Edge, No Wake, Pull Down, Disable Pull-Up
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_17, 0xB9 }, // unused In, R Edge, No Wake, Pull Down, Disable Pull-Up
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_18, 0xB9 }, // unused In, R Edge, No Wake, Pull Down, Disable Pull-Up
|
||||
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB1, 0x12 }, // 10ms debounce
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB2, 0x12 }, // 10ms debounce
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB3, 0x02 }, // no debounce on GPIO6
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB4, 0x10 }, // no debounce on GPIO7
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB5, 0x02 }, // no debounce on GPIO10
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB6, 0x12 }, // 10ms debounce
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB7, 0x12 }, // 10ms debounce
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB8, 0x12 }, // 10ms debounce
|
||||
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB9, 0x12 }, // 10ms debounce
|
||||
|
||||
// <rdar://problem/8932682>
|
||||
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x02 },
|
||||
{ PMU_IIC_BUS, kD1946_TEST_MODE, 0x01 }, // Enable test mode
|
||||
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x01 },
|
||||
{ PMU_IIC_BUS, kD1946_WLED_CONTROL5, 0x00 }, // set WLED to IDAC always
|
||||
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x02 },
|
||||
{ PMU_IIC_BUS, kD1946_TEST_MODE, 0x00 }, // Disable test mode
|
||||
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x00 },
|
||||
|
||||
// <rdar://problem/8784560>
|
||||
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x01 }, // Select Bank 1
|
||||
{ PMU_IIC_BUS, kD1946_BUCK_CONTROL1, 0x0e }, // Force Buck0 into PWM Mode
|
||||
{ PMU_IIC_BUS, kD1946_BUCK_CONTROL3, 0x0e }, // Force Buck2 into PWM Mode
|
||||
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x00 }, // Select Bank 0
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_backlight_enable[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_ISET, 0xD4 }, // 50% value from OS
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_ISET2, 0x00 },
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, // enable all LED strings
|
||||
(kDIALOG_WLED_CONTROL_WLED_ENABLE1 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE2 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE3 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE4 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE5 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE6) },
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL2, // enable LED Power
|
||||
(kDIALOG_WLED_CONTROL2_WLED_RAMP_EN |
|
||||
kDIALOG_WLED_CONTROL2_WLED_DITH_EN) }
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_backlight_disable[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, 0x0 } // disable LED power
|
||||
};
|
||||
|
||||
static const struct core_rails_struct soc_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kDIALOG_BUCK2 }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct cpu_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kDIALOG_BUCK0 }
|
||||
};
|
||||
|
||||
#endif /* POWERCONFIG_PMU_SETUP */
|
||||
|
||||
#define TARGET_USE_CHARGE_TABLE 1
|
||||
static const struct power_charge_limits pmu_charge_table[16] = { // gas gauge can have up to 16 entries
|
||||
{ 4000, 1000, 1600, 3000 }, // 10 - 16C 0.44C
|
||||
{ 4100, 1000, 1600, 1375 }, // 0.2C
|
||||
{ USHRT_MAX, 1000, 1600, 750 }, // 0.11C
|
||||
{ 4000, 1500, 2100, 3000 }, // 15 - 21C 0.44C
|
||||
{ 4100, 1500, 2100, 2000 }, // 0.29C
|
||||
{ USHRT_MAX, 1500, 2100, 1375 }, // 0.2C
|
||||
{ 4000, 2000, 3500, 3000 }, // 20 - 35C 0.44C
|
||||
{ 4100, 2000, 3500, 3000 }, // 0.44C
|
||||
{ USHRT_MAX, 2000, 3500, 2000 }, // 0.29C
|
||||
{ 4000, 3400, 4500, 3000 }, // 34 - 45C 0.44C
|
||||
{ 4100, 3400, 4500, 3000 }, // 0.44C
|
||||
{ USHRT_MAX, 3400, 4500, 3000 }, // 0.44C
|
||||
};
|
||||
|
||||
// matches OTP for ICHG_TBAT_x
|
||||
#define TARGET_ICHG_TBAT_MAX { 0x00, 0x00, 0x3f, 0x3f, 0x3f }
|
||||
|
||||
#define NO_BATTERY_VOLTAGE 2700
|
||||
#define MIN_BOOT_BATTERY_VOLTAGE 3600
|
||||
#define TARGET_BOOT_BATTERY_VOLTAGE 3700
|
||||
#define TARGET_BOOT_BATTERY_CAPACITY 50
|
||||
#define PRECHARGE_BACKLIGHT_LEVEL 1287 /* 10% brightness */
|
||||
#define TARGET_PRECHARGE_ALWAYS_DISPLAY_IDLE 1
|
||||
#define TARGET_MAX_USB_INPUT_CURRENT 2100
|
||||
|
||||
#define GASGAUGE_BATTERYID_BLOCK 1
|
||||
#define GASGAUGE_CHARGETABLE_BLOCK 3
|
||||
static const unsigned int atv_voltage_limit[16] = { 3600, 3650, 3700, 3750, 3800, 3850, 3900, 3950, 4000, 4050, 4100, 4150, 4200, 4250, 4300, 4350 };
|
||||
static const unsigned int atv_current_limit[16] = { 0, 0, 625, 750, 875, 1000, 1125, 1250, 1375, 1500, 1750, 2000, 2250, 2500, 2750, 3000 };
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (C) 2009 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_RADIOCONFIG_H
|
||||
#define __TARGET_RADIOCONFIG_H
|
||||
|
||||
/* configuration per target */
|
||||
|
||||
#define RADIO_VERIFY_BASEBAND_EXISTS 1
|
||||
|
||||
static const gpio_t target_radio_quiesce_pins[] =
|
||||
{
|
||||
GPIO_UART1_TXD
|
||||
};
|
||||
|
||||
#define RADIO_ENABLE_IMEI_OVERRIDE 0
|
||||
|
||||
#endif /* ! __TARGET_RADIOCONFIG_H */
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define two debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (0)
|
||||
|
||||
/* define radio serial port */
|
||||
#define RADIO_SERIAL_PORT (1)
|
||||
#define RADIO_MAX_READ_ERRORS (10)
|
||||
|
||||
/* define HDQ serial port */
|
||||
#define HDQGAUGE_SERIAL_PORT (5)
|
||||
|
||||
#define UART_FLOWCONTROL_MASK (0x08)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,299 @@
|
||||
/*
|
||||
* Copyright (C) 2010-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/display.h>
|
||||
#include <drivers/flash_nor.h>
|
||||
#include <drivers/iic.h>
|
||||
#include <drivers/power.h>
|
||||
#include <lib/devicetree.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <lib/syscfg.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <sys.h>
|
||||
#include <sys/boot.h>
|
||||
#include <sys/menu.h>
|
||||
#include <sys/task.h>
|
||||
#include <target.h>
|
||||
#include <target/powerconfig.h>
|
||||
#include <target/display_gamma_tables.h>
|
||||
|
||||
#define K93_PROTO1_BOARD (0) // And DEV1
|
||||
#define K93_PROTO2_BOARD (1)
|
||||
#define K93_EVT_BOARD (2) // And DEV3
|
||||
#define K93_EVT2_BOARD (3)
|
||||
#define K93_DVT_BOARD (4)
|
||||
|
||||
static u_int32_t k93_get_board_rev(void);
|
||||
static uint32_t display_config;
|
||||
|
||||
MIB_CONSTANT_PTR(kMIBTargetDisplayGammaTablePtr,kOIDTypeStruct, (void *)ipad2_display_gamma_tables);
|
||||
MIB_CONSTANT(kMIBTargetDisplayGammaTableCount, kOIDTypeUInt32, ARRAY_SIZE(ipad2_display_gamma_tables));
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 1);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 90);
|
||||
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
switch (target) {
|
||||
case BOOT_DARWIN:
|
||||
case BOOT_DARWIN_RESTORE:
|
||||
case BOOT_DIAGS:
|
||||
break;
|
||||
|
||||
default:
|
||||
; // do nothing
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return platform_get_request_dfu2() && power_has_usb();
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
#if WITH_HW_POWER
|
||||
if (power_get_boot_flag() == kPowerBootFlagColdButton) *cold_button_boot = true;
|
||||
#else
|
||||
*cold_button_boot = false;
|
||||
#endif
|
||||
|
||||
return !*cold_button_boot || platform_get_request_dfu1();
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
u_int32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
void * target_get_display_configuration(void)
|
||||
{
|
||||
display_config = 0x00000644;
|
||||
return ((void *)(&display_config));
|
||||
}
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
env_set("boot-device", "nand0", 0);
|
||||
env_set("display-color-space","RGB888", 0);
|
||||
env_set("display-timing", "k48", 0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
DTNode *node, *clcd_node, *backlight_node;
|
||||
uint32_t propSize, propCnt;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
// Update the DWI node with the actual voltages
|
||||
if (FindNode(0, "arm-io/dwi", &node)) {
|
||||
propName = "voltages-buck0";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propCnt = propSize / sizeof(u_int32_t);
|
||||
platform_get_cpu_voltages(propCnt, propData);
|
||||
platform_convert_voltages(0, propCnt, propData);
|
||||
}
|
||||
propName = "voltages-buck2";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propCnt = propSize / sizeof(u_int32_t);
|
||||
platform_get_soc_voltages(propCnt, propData);
|
||||
platform_convert_voltages(2, propCnt, propData);
|
||||
}
|
||||
}
|
||||
|
||||
// Find the CLCD node
|
||||
FindNode(0, "arm-io/clcd", &clcd_node);
|
||||
|
||||
#if WITH_HW_DISPLAY_PINOT
|
||||
if (FindNode(0, "arm-io/mipi-dsim/lcd", &node)) {
|
||||
extern int pinot_update_device_tree(DTNode *pinot_node, DTNode *clcd_node, DTNode *backlight_node);
|
||||
|
||||
FindNode(0, "backlight", &backlight_node);
|
||||
pinot_update_device_tree(node, clcd_node, backlight_node);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Update the bottom prox calibration data
|
||||
if (FindNode(0, "arm-io/i2c1/prox", &node)) {
|
||||
propName = "prox-bottom-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('PBCl', propData, propSize);
|
||||
}
|
||||
propName = "prox-temp-base";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('PBTb', propData, propSize);
|
||||
}
|
||||
propName = "prox-centerpoint-base";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('PBCb', propData, propSize);
|
||||
}
|
||||
propName = "prox-calibration-blob";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('CPCl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update als node with calibration data
|
||||
if (FindNode(0, "arm-io/i2c2/als", &node)) {
|
||||
propName = "backlight-leakage-channel0";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ALC0', propData, propSize);
|
||||
}
|
||||
propName = "backlight-leakage-channel1";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ALC1', propData, propSize);
|
||||
}
|
||||
propName = "alsCalibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('AlsC', propData, propSize);
|
||||
}
|
||||
propName = "als-colorCfg";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ClrC', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the gyro calibration data
|
||||
if (FindNode(0, "arm-io/i2c2/gyro", &node)) {
|
||||
propName = "low-temp-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LTGO', propData, propSize);
|
||||
}
|
||||
propName = "high-temp-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('HTGO', propData, propSize);
|
||||
}
|
||||
propName = "gyro-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GSCl', propData, propSize);
|
||||
}
|
||||
propName = "gyro-temp-table";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GYTT', propData, propSize);
|
||||
}
|
||||
propName = "gyro-interrupt-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GICl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update accelerometer calibration data
|
||||
if (FindNode(0, "arm-io/i2c2/accelerometer", &node)) {
|
||||
propName = "low-temp-accel-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LTAO', propData, propSize);
|
||||
}
|
||||
propName = "accel-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ASCl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update camera calibration data
|
||||
if (FindNode(0, "arm-io/isp", &node)) {
|
||||
propName = "camera-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('CmCl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update USB input current limit
|
||||
if (FindNode(0, "charger", &node)) {
|
||||
propName = "usb-input-limit-max";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
*(uint32_t *)propData = TARGET_MAX_USB_INPUT_CURRENT;
|
||||
}
|
||||
}
|
||||
|
||||
// K94 EVT does not support Charleston slow-ramp
|
||||
if (k93_get_board_rev() < K93_DVT_BOARD) {
|
||||
if (FindNode(0, "arm-io/i2c0/headset-switch", &node)) {
|
||||
propName = "slow-ramp-delay";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
*(uint32_t *)propData = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static u_int32_t k93_get_board_rev(void)
|
||||
{
|
||||
u_int32_t gpio_board_rev;
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PUP);
|
||||
|
||||
spin(100); // Wait 100us
|
||||
|
||||
gpio_board_rev =
|
||||
(gpio_read(GPIO_BOARD_REV2) << 2) |
|
||||
(gpio_read(GPIO_BOARD_REV1) << 1) |
|
||||
(gpio_read(GPIO_BOARD_REV0) << 0);
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
|
||||
|
||||
return (gpio_board_rev & 0x7);
|
||||
}
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) 2009-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <target.h>
|
||||
|
||||
#define PIN_CFG_AP 1
|
||||
#include <target/pinconfig.h>
|
||||
#undef PIN_CFG_AP
|
||||
|
||||
#define PIN_CFG_DEV 1
|
||||
#include <target/pinconfig.h>
|
||||
#undef PIN_CFG_DEV
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
if (target_config_ap())
|
||||
return gpio_default_cfg_ap;
|
||||
else
|
||||
return gpio_default_cfg_dev;
|
||||
}
|
||||
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* Copyright (C) 2010-2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <target.h>
|
||||
#include <target/powerconfig.h>
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
bool
|
||||
target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
|
||||
{
|
||||
int length = 0;
|
||||
bool result = false;
|
||||
|
||||
if ((result = target_get_property_base(prop, data, maxdata, retlen)) == false) {
|
||||
switch(prop) {
|
||||
case TARGET_PROPERTY_RESTORE_BACKLIGHT_LEVEL:
|
||||
// fix the restore backlight level at the precharge level,
|
||||
// to make sure the backlight does not cause the battery to
|
||||
// drain during restore
|
||||
if (maxdata >= (ssize_t)sizeof(uint32_t)) {
|
||||
result = true;
|
||||
length = sizeof(uint32_t);
|
||||
*(uint32_t *)data = PRECHARGE_BACKLIGHT_LEVEL;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (retlen != NULL) *retlen = length;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,49 @@
|
||||
# Copyright (C) 2010-2012 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D1946=1 \
|
||||
TARGET_HIGH_SOC_VOLTAGE=CHIPID_SOC_VOLTAGE_HIGH \
|
||||
TARGET_HIGH_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_HIGH \
|
||||
TARGET_CPU_VOLTAGE_MASK=5 \
|
||||
TARGET_CPU_SOURCE=1 \
|
||||
TARGET_MIPI_DSI_SOURCE=2 \
|
||||
TARGET_MANAGED2H_SOURCE=1 \
|
||||
TARGET_MANAGED2L_SOURCE=2 \
|
||||
TARGET_MANAGED2H_DIV=2 \
|
||||
TARGET_MANAGED2L_DIV=3 \
|
||||
TARGET_PCLK1_SOURCE=2 \
|
||||
TARGET_PCLK1_DIV=6 \
|
||||
TARGET_GFX_SOURCE=2 \
|
||||
TARGET_GFX_SLC_SOURCE=2 \
|
||||
TARGET_SPI2_SOURCE=0 \
|
||||
TARGET_IOP_SOURCE=3 \
|
||||
TARGET_LPERFS_SOURCE=3 \
|
||||
TARGET_HPERFNRT_SOURCE=0 \
|
||||
TARGET_CLCD_VSPP=0 \
|
||||
TARGET_DSIM_CONFIG=0x00800000 \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
AMC_CHANNEL_WIDTH=4 \
|
||||
MULTITOUCH_DTPATH=\"arm-io/spi1/multi-touch\" \
|
||||
BASEBAND_DTPATH=\"baseband\" \
|
||||
WITH_TARGET_AMG_PARAMS=1
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
|
||||
ifneq ($(PRODUCT),LLB)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/properties.o
|
||||
endif
|
||||
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Copyright (C) 2010, 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_DISPLAY_GAMMA_TABLES_H
|
||||
#define __TARGET_DISPLAY_GAMMA_TABLES_H
|
||||
|
||||
/* K9x display gamma tables */
|
||||
|
||||
static const display_gamma_table ipad2b_display_gamma_tables[] =
|
||||
{
|
||||
{
|
||||
0x00951149, 0x00FFFF7F, // LGD table 8/19/2012
|
||||
{
|
||||
0x62, 0x0a, 0x4d, 0x40, 0x07, 0x2b, 0x03, 0x34,
|
||||
0x34, 0xc0, 0x31, 0xc0, 0xdd, 0xdd, 0x34, 0x4d,
|
||||
0xd3, 0xd0, 0x74, 0xd3, 0xd0, 0x34, 0x34, 0xdd,
|
||||
0x34, 0x4d, 0xd3, 0x74, 0xc7, 0xdd, 0xdd, 0xc4,
|
||||
0x71, 0x70, 0x1c, 0xc7, 0x01, 0xc0, 0x01, 0x70,
|
||||
0x00, 0xd0, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x0d,
|
||||
0xd0, 0xd0, 0x40, 0x13, 0xd0, 0x1d, 0xd3, 0x00,
|
||||
0xc0, 0x01, 0x37, 0x34, 0x34, 0x34, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x62, 0x0a, 0x4d, 0x40, 0x07, 0x2b, 0x03, 0x34,
|
||||
0x34, 0xc0, 0x31, 0xc0, 0xdd, 0xdd, 0x34, 0x4d,
|
||||
0xd3, 0xd0, 0x74, 0xd3, 0xd0, 0x34, 0x34, 0xdd,
|
||||
0x34, 0x4d, 0xd3, 0x74, 0xc7, 0xdd, 0xdd, 0xc4,
|
||||
0x71, 0x70, 0x1c, 0xc7, 0x01, 0xc0, 0x01, 0x70,
|
||||
0x00, 0xd0, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x0d,
|
||||
0xd0, 0xd0, 0x40, 0x13, 0xd0, 0x1d, 0xd3, 0x00,
|
||||
0xc0, 0x01, 0x37, 0x34, 0x34, 0x34, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x62, 0x0a, 0x4d, 0x40, 0x07, 0x2b, 0x03, 0x34,
|
||||
0x34, 0xc0, 0x31, 0xc0, 0xdd, 0xdd, 0x34, 0x4d,
|
||||
0xd3, 0xd0, 0x74, 0xd3, 0xd0, 0x34, 0x34, 0xdd,
|
||||
0x34, 0x4d, 0xd3, 0x74, 0xc7, 0xdd, 0xdd, 0xc4,
|
||||
0x71, 0x70, 0x1c, 0xc7, 0x01, 0xc0, 0x01, 0x70,
|
||||
0x00, 0xd0, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x0d,
|
||||
0xd0, 0xd0, 0x40, 0x13, 0xd0, 0x1d, 0xd3, 0x00,
|
||||
0xc0, 0x01, 0x37, 0x34, 0x34, 0x34, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
}
|
||||
},
|
||||
{
|
||||
0x00A41149, 0x00FFFF7F, // AUO table 8/20/2012
|
||||
{
|
||||
0x62, 0x0a, 0x0d, 0x01, 0xdd, 0x01, 0x00, 0x00,
|
||||
0x00, 0xc7, 0x0d, 0x1c, 0x07, 0x07, 0xc7, 0x71,
|
||||
0x70, 0x1c, 0x1c, 0x77, 0xdc, 0xc1, 0x71, 0x70,
|
||||
0xc7, 0x71, 0x70, 0xc0, 0x01, 0x07, 0x00, 0x00,
|
||||
0x00, 0x00, 0x1c, 0x70, 0x70, 0x70, 0x00, 0x07,
|
||||
0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d,
|
||||
0x00, 0x00, 0x74, 0xc7, 0x1d, 0x77, 0x37, 0x4d,
|
||||
0x43, 0x03, 0x70, 0xc0, 0x01, 0x00, 0x34, 0xdd,
|
||||
0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x62, 0x0a, 0x40, 0x77, 0x34, 0x1d, 0x07, 0x70,
|
||||
0x70, 0xdc, 0x00, 0x00, 0xc7, 0xdd, 0xdd, 0xdd,
|
||||
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x71,
|
||||
0xdc, 0x71, 0x07, 0xc7, 0xc1, 0x71, 0x1c, 0x00,
|
||||
0x00, 0x70, 0x00, 0x00, 0x07, 0x1c, 0x1c, 0x00,
|
||||
0x00, 0x00, 0x70, 0x0d, 0x40, 0x03, 0xd0, 0x00,
|
||||
0x0d, 0x34, 0xd0, 0x1d, 0x1c, 0x70, 0xdc, 0xdd,
|
||||
0xdd, 0xdd, 0x34, 0x40, 0x03, 0x34, 0x1d, 0x77,
|
||||
0xdc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x62, 0x0a, 0x4d, 0x40, 0x13, 0x00, 0x40, 0xd3,
|
||||
0x00, 0xc0, 0x4d, 0x73, 0x00, 0x00, 0xc0, 0x01,
|
||||
0x70, 0x00, 0x07, 0x07, 0x07, 0x1c, 0xc0, 0x01,
|
||||
0x07, 0x00, 0x70, 0x00, 0x07, 0x40, 0x03, 0x00,
|
||||
0x00, 0x00, 0x07, 0x70, 0x00, 0x00, 0x00, 0x00,
|
||||
0x07, 0x0d, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00,
|
||||
0x40, 0xd3, 0xdd, 0xdd, 0x0d, 0x0d, 0x00, 0x00,
|
||||
0xc0, 0x71, 0x77, 0x77, 0x77, 0x77, 0x1c, 0xc7,
|
||||
0xdd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
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