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@@ -0,0 +1,27 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ADBE_SETTINGS_H
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#define __TARGET_ADBE_SETTINGS_H
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static struct adbe_v1_tuneable adbe_tuneables[] = {
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{
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.name = "default",
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.adbe0_vblank_pos_vbi_pulse = 0x0000,
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.adbe0_vblank_clk_gate_wakeup = 0x0000,
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.adbe0_vblank_clk_gate_idle = 0x0001,
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.adbe0_vblank_blk_idle_dpb = 0x0000,
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.adbe0_vblank_blk_idle_aap = 0x0000,
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.adbe0_tunable_mode_ctrl = (DBEMODECNTL_DYN_CLK_GATE_ENABLE | DBEMODECNTL_AFC_TEARDOWN_ENABLE | DBEMODECNTL_PMGR_CLK_GATE_ENABL| DBEMODECNTL_BLK_CLK_GATE_ENABLE),
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.adbe0_aap_support = 1,
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},
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};
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#endif
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ASPNANDCONFIG_H
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#define __TARGET_ASPNANDCONFIG_H
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//MLC devices
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#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
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#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_DIES_IN_PARALLEL 4
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#define ASPNAND_READ_DIES_IN_PARALLEL 4
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#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
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//TLC devices
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#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
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// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
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#define ASPNAND_INDIRECTION_MEMORY (2*1024*1024)
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#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
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#endif
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@@ -0,0 +1,28 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* iRef,x specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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/* define target-specific gpios in a generic fashion here. */
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#define GPIO_RINGER_AB GPIO( 2, 0)
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#define GPIO_WDOG GPIO( 0, 1) // WDOG
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/* D2094 watchdog tickle, 'KEEPACT' */
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#define GPIO_WDOG_TICKLE GPIO(2, 5)
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,88 @@
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD2045_LDO9_VSEL, 0x5A}, // LDO9 (PP2V8_CAM) to 2.85V <rdar://problem/12660594>
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{ PMU_IIC_BUS, kD2045_ACTIVE3, 0xAE }, // Current OTP enables LDO{1,2,3,4,5,7}, disable LDO4.
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{ PMU_IIC_BUS, kD2045_ACTIVE6, 0x37 }, // enable BUCK3_SW1, BUCK3_SW2, BUCK3_SW3, BUCK4_SW1, BUCK4_SW2
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{ PMU_IIC_BUS, kD2045_ACTIVE3, 0xBE }, // enable LDO4 along with LDO{1,2,3,5,7}
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{ PMU_IIC_BUS, kD2045_HIBERNATE1, 0x18 },
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{ PMU_IIC_BUS, kD2045_HIBERNATE3, 0x18 },
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{ PMU_IIC_BUS, kD2045_HIBERNATE6, 0x24 },
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup_a0[] =
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{
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{ PMU_IIC_BUS, kD2045_LDO9_VSEL, 0x42}, // LDO9 (PP2V8_CAM) to 2.85V <rdar://problem/12660594>
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{ PMU_IIC_BUS, kD2045_ACTIVE3, 0xAE }, // Current OTP enables LDO{1,2,3,4,5,7}, disable LDO4.
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{ PMU_IIC_BUS, kD2045_ACTIVE6, 0x37 }, // enable BUCK3_SW1, BUCK3_SW2, BUCK3_SW3, BUCK4_SW1, BUCK4_SW2
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{ PMU_IIC_BUS, kD2045_ACTIVE3, 0xBE }, // enable LDO4 along with LDO{1,2,3,5,7}
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// <rdar://problem/12264399> N51: Workaround needed for hibernate on PROTO2 Amber OTP
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{ PMU_IIC_BUS, 0x7000, 0x1d }, // Enable test mode
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{ PMU_IIC_BUS, kD2045_BUTTON4_CONF, 0x94 }, // Set BUTTON4 config to be pulled up to VBUCK3 instead of VBUCK3_SW
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{ PMU_IIC_BUS, 0x7000, 0x00 }, // Disable test mode
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{ PMU_IIC_BUS, kD2045_HIBERNATE1, 0x18 },
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{ PMU_IIC_BUS, kD2045_HIBERNATE3, 0x18 },
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{ PMU_IIC_BUS, kD2045_HIBERNATE6, 0x24 },
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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};
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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{ PMU_IIC_BUS, kD2045_GPIO_DEB2, 0x12 },
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{ PMU_IIC_BUS, kD2045_GPIO_DEB5, 0x12 },
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{ PMU_IIC_BUS, kD2045_GPIO_DEB6, 0x12 },
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{ PMU_IIC_BUS, kD2045_BUCK_DWI_CTRL0, 0x03 }, // enable DWI for BUCK0, BUCK1
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{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2, 0x11 }, // enable HIB_32kHz (for WIFI/BT) and DWI
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{ PMU_IIC_BUS, kD2045_ACT_TO_HIB_DLY, 0x03 }, // set ACT_TO_HIB_DLY to 3 (6ms)
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};
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static const struct core_rails_struct soc_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2045_BUCK2_VSEL }
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};
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static const struct core_rails_struct cpu_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2045_BUCK0_VSEL }
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};
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static const struct core_rails_struct ram_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2045_BUCK5_VSEL }
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};
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#endif /* POWERCONFIG_PMU_SETUP */
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#define NO_BATTERY_VOLTAGE 2700
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#define MIN_BOOT_BATTERY_VOLTAGE 3600
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#define TARGET_BOOT_BATTERY_VOLTAGE 3700
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#define TARGET_BOOT_BATTERY_CAPACITY 50
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#define PRECHARGE_BACKLIGHT_LEVEL 824
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#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
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#define ACC_PWR_LDO (6)
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#endif
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@@ -0,0 +1,23 @@
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/*
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* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_UARTCONFIG_H
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#define __TARGET_UARTCONFIG_H
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/* define one debug serial ports */
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#define DEBUG_SERIAL_PORT (0)
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#define HDQGAUGE_SERIAL_PORT (5)
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#if SUPPORT_FPGA
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#define UART_OVERSAMPLE_OVERRIDE (11)
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#endif
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#endif
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@@ -0,0 +1,112 @@
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/*
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* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
|
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* Apple Inc.
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*/
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#include <debug.h>
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#include <drivers/flash_nor.h>
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#include <drivers/iic.h>
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#include <drivers/power.h>
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#include <lib/devicetree.h>
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#include <lib/env.h>
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#include <lib/mib.h>
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#include <lib/syscfg.h>
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#include <platform.h>
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#include <platform/gpio.h>
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#include <platform/gpiodef.h>
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#include <sys.h>
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#include <sys/boot.h>
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#include <sys/menu.h>
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#include <target.h>
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MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
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MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
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uint32_t display_config;
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void target_early_init(void)
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{
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}
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void target_late_init(void)
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{
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}
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void target_init(void)
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{
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#if WITH_HW_FLASH_NOR
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flash_nor_init(SPI_NOR0);
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#endif
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}
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void target_quiesce_hardware(void)
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{
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}
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void target_poweroff(void)
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{
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}
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int target_bootprep(enum boot_target target)
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{
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return 0;
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}
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bool target_should_recover(void)
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{
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return platform_get_request_dfu2() && power_has_usb();
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}
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bool target_should_poweron(bool *cold_button_boot)
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{
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#if WITH_HW_POWER
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if (power_get_boot_flag() == kPowerBootFlagColdButton) *cold_button_boot = true;
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#else
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*cold_button_boot = false;
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#endif // WITH_HW_POWER
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return !*cold_button_boot || platform_get_request_dfu1();
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}
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bool target_should_poweroff(bool at_boot)
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{
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return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
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}
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#if APPLICATION_IBOOT
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void target_watchdog_tickle(void)
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{
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uint32_t value = gpio_read(GPIO_WDOG_TICKLE);
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gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
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}
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#endif // APPLICATION_IBOOT
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void * target_get_display_configuration(void)
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{
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display_config = 0x00000da2;
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return ((void *)(&display_config));
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}
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#if WITH_ENV
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void target_setup_default_environment(void)
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{
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env_set("boot-device", "asp_nand", 0);
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env_set("display-color-space","RGB888", 0);
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env_set("display-timing", "n51", 0);
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}
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#endif // WITH_ENV
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#if WITH_DEVICETREE
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int target_update_device_tree(void)
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{
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return 0;
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}
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#endif // WITH_DEVICETREE
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@@ -0,0 +1,308 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
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||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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*/
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#include <drivers/apple/gpio.h>
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#include <platform/soc/hwregbase.h>
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#include <stdint.h>
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/* N51/N53 (iPhone6,x) Pin Configuration */
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/*
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* N51 pinlist v0.13
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* <rdar://problem/11763484> N51 HW ERS | System | Pinlist
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*/
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#define CFG_DISABLED_SS_X4 (CFG_DISABLED | SLOW_SLEW | DRIVE_X4 )
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#define CFG_DISABLED_SS_X4_PD (CFG_DISABLED | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
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#define CFG_DISABLED_SS_X1_PD (CFG_DISABLED | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
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#define CFG_DISABLED_SS_X4_PU (CFG_DISABLED | SLOW_SLEW | DRIVE_X4 | PULL_UP )
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#define CFG_DISABLED_SS_X1_PU (CFG_DISABLED | SLOW_SLEW | DRIVE_X1 | PULL_UP )
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#define CFG_IN_SS_X1 (CFG_IN | SLOW_SLEW | DRIVE_X1 )
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#define CFG_IN_SS_X2 (CFG_IN | SLOW_SLEW | DRIVE_X2 )
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#define CFG_IN_SS_X4 (CFG_IN | SLOW_SLEW | DRIVE_X4 )
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#define CFG_IN_SS_X4_PD (CFG_IN | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
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#define CFG_IN_SS_X1_PD (CFG_IN | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
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#define CFG_IN_SS_X4_PU (CFG_IN | SLOW_SLEW | DRIVE_X4 | PULL_UP )
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#define CFG_IN_SS_X1_PU (CFG_IN | SLOW_SLEW | DRIVE_X1 | PULL_UP )
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#define CFG_OUT_0_SS_X4 (CFG_OUT_0 | SLOW_SLEW | DRIVE_X4 )
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#define CFG_OUT_0_SS_X4_PD (CFG_OUT_0 | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
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#define CFG_OUT_0_SS_X1_PD (CFG_OUT_0 | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
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||||
#define CFG_OUT_0_SS_X4_PU (CFG_OUT_0 | SLOW_SLEW | DRIVE_X4 | PULL_UP )
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||||
#define CFG_OUT_0_SS_X1_PU (CFG_OUT_0 | SLOW_SLEW | DRIVE_X1 | PULL_UP )
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||||
#define CFG_OUT_1_SS_X4 (CFG_OUT_1 | SLOW_SLEW | DRIVE_X4 )
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||||
#define CFG_OUT_1_SS_X4_PD (CFG_OUT_1 | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
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||||
#define CFG_OUT_1_SS_X1_PD (CFG_OUT_1 | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
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||||
#define CFG_OUT_1_SS_X4_PU (CFG_OUT_1 | SLOW_SLEW | DRIVE_X4 | PULL_UP )
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||||
#define CFG_OUT_1_SS_X1_PU (CFG_OUT_1 | SLOW_SLEW | DRIVE_X1 | PULL_UP )
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#define CFG_FUNC0_SS_X1 (CFG_FUNC0 | SLOW_SLEW | DRIVE_X1 )
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#define CFG_FUNC0_SS_X2 (CFG_FUNC0 | SLOW_SLEW | DRIVE_X2 )
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#define CFG_FUNC0_SS_X4 (CFG_FUNC0 | SLOW_SLEW | DRIVE_X4 )
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#define CFG_FUNC0_SS_X4_PD (CFG_FUNC0 | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
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||||
#define CFG_FUNC0_SS_X2_PD (CFG_FUNC0 | SLOW_SLEW | DRIVE_X2 | PULL_DOWN)
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||||
#define CFG_FUNC0_SS_X1_PD (CFG_FUNC0 | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
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#define CFG_FUNC0_SS_X4_PU (CFG_FUNC0 | SLOW_SLEW | DRIVE_X4 | PULL_UP )
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#define CFG_FUNC0_SS_X1_PU (CFG_FUNC0 | SLOW_SLEW | DRIVE_X1 | PULL_UP )
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static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
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||||
/* Port 0 */
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||||
CFG_DISABLED_SS_X4_PD, // TST_CLKOUT -> AP_TO_PMU_TEST_CLKOUT
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||||
CFG_DISABLED_SS_X4_PD, // WDOG -> AP_TO_PMU_RESET_IN
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||||
CFG_IN_SS_X1, // GPIO0 -> BUTTON_TO_AP_MENU_KEY_BUFF_L
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||||
CFG_IN_SS_X1, // GPIO1 -> BUTTON_TO_AP_HOLD_KEY_BUFF_L
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||||
CFG_IN_SS_X1_PU, // GPIO2 -> BUTTON_TO_AP_VOL_UP_L
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||||
CFG_IN_SS_X1_PU, // GPIO3 -> BUTTON_TO_AP_VOL_DOWN_L
|
||||
CFG_IN_SS_X1_PU, // GPIO4 -> PMU_NIRQ [PMU_TO_AP_IRQ_L in N51]
|
||||
CFG_OUT_0_SS_X4_PD, // GPIO5 -> AP_TO_SPKAMP_BEE_GEES
|
||||
|
||||
/* Port 1 */
|
||||
CFG_OUT_0_SS_X4_PD, // GPIO6 -> AP_TO_SPKAMP_RESET_L
|
||||
CFG_OUT_0_SS_X4_PD, // GPIO7 -> AP_TO_BT_WAKE
|
||||
CFG_IN_SS_X4, // GPIO8 -> AP_TO_BB_RST_L
|
||||
CFG_DISABLED_SS_X4, // GPIO9 -> AP_TO_BB_JTAG_TDI
|
||||
CFG_DISABLED_SS_X4_PD, // GPIO10 -> AP_TO_BB_JTAG_TDO
|
||||
CFG_DISABLED_SS_X4_PD, // GPIO11 -> AP_TO_HEADSET_HS3_CTRL
|
||||
CFG_DISABLED_SS_X4_PD, // GPIO12 -> AP_TO_HEADSET_HS4_CTRL
|
||||
CFG_DISABLED, // GPIO13 -> NULL
|
||||
|
||||
/* Port 2 */
|
||||
CFG_IN_SS_X1, // GPIO14 -> BUTTON_TO_AP_RINGER_A
|
||||
CFG_OUT_0_SS_X4, // GPIO15 -> AP_TO_BB_WAKE_MODEM
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO16 -> N/C -> BOARD_ID[3]
|
||||
CFG_IN_SS_X1, // GPIO17 -> AP_TO_OSCAR_DBGEN
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO18 -> BOARD_INFO -> BOOT_CONFIG[0]
|
||||
CFG_DISABLED, // GPIO19 -> NULL
|
||||
CFG_DISABLED, // GPIO20 -> NULL
|
||||
CFG_DISABLED, // GPIO21 -> NULL
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_FUNC0_SS_X4_PU, // UART1_TXD -> AP_TO_BT_UART1_TXD
|
||||
CFG_FUNC0_SS_X1_PU, // UART1_RXD -> BT_TO_AP_UART1_RXD
|
||||
CFG_FUNC0_SS_X4_PU, // UART1_RTSN -> AP_TO_BT_UART1_RTS_L
|
||||
CFG_FUNC0_SS_X1_PU, // UART1_CTSN -> BT_TO_AP_UART1_CTS_L
|
||||
CFG_FUNC0_SS_X4_PU, // UART2_TXD -> AP_TO_OSCAR_UART2_TXD
|
||||
CFG_FUNC0_SS_X1_PU, // UART2_RXD -> OSCAR_TO_AP_UART2_RXD
|
||||
CFG_OUT_1_SS_X4_PU, // UART2_RTSN -> AP_TO_OSCAR_RESET_L
|
||||
CFG_IN_SS_X1_PD, // UART2_CTSN -> OSCAR_TO_PMU_HOST_WAKE
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0_SS_X4, // UART3_TXD -> AP_TO_WLAN_UART3_TXD
|
||||
CFG_FUNC0_SS_X1, // UART3_RXD -> WLAN_TO_AP_UART3_RXD
|
||||
CFG_DISABLED_SS_X1_PD, // UART3_RTSN -> BB_TO_AP_PP_SYNC
|
||||
CFG_OUT_0_SS_X4_PD, // UART3_CTSN -> AP_TO_RCAM_VDDCORE_EN
|
||||
CFG_FUNC0_SS_X2, // UART5_RXD -> AP_BI_BATTERY_SWI
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 8 */
|
||||
CFG_OUT_0_SS_X4, // UART4_TXD -> AP_TO_BB_UART4_TXD
|
||||
CFG_FUNC0_SS_X1, // UART4_RXD -> BB_TO_AP_UART4_RXD
|
||||
CFG_OUT_0_SS_X4, // UART4_RTSN -> AP_TO_BB_UART4_RTS_L
|
||||
CFG_FUNC0_SS_X1, // UART4_CTSN -> BB_TO_AP_UART4_CTS_L
|
||||
CFG_FUNC0_SS_X4_PD, // SPI1_SCLK -> AP_TO_TOUCH_SPI1_CLK
|
||||
CFG_FUNC0_SS_X4_PD, // SPI1_MOSI -> AP_TO_TOUCH_SPI1_MOSI
|
||||
CFG_FUNC0_SS_X1_PD, // SPI1_MISO -> TOUCH_TO_AP_SPI1_MISO
|
||||
CFG_FUNC0_SS_X4_PU, // SPI1_SSIN -> AP_TO_TOUCH_SPI1_CS_L
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED_SS_X1_PU, // SPI0_SCLK -> N/C -> SPI0_SCLK/BOARD_ID[0]
|
||||
CFG_DISABLED_SS_X1_PU, // SPI0_MOSI -> N/C -> SPI0_MOSI/BOARD_ID[1]
|
||||
CFG_DISABLED_SS_X1_PU, // SPI0_MISO -> N/C -> SPI0_MISO/BOARD_ID[2]
|
||||
CFG_DISABLED_SS_X1_PD, // SPI0_SSIN -> LCM_TO_AP_PIFA
|
||||
CFG_FUNC0_SS_X2, // SPI2_SCLK -> AP_TO_NAVAJO_SPI2_CLK
|
||||
CFG_FUNC0_SS_X2, // SPI2_MOSI -> AP_TO_NAVAJO_SPI2_MOSI
|
||||
CFG_FUNC0_SS_X2_PD, // SPI2_MISO -> NAVAJO_TO_AP_SPI2_MISO
|
||||
CFG_FUNC0_SS_X2, // SPI2_SSIN -> NAVAJO_TO_PMU_INT_H
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0_SS_X4, // I2C0_SDA -> AP_BI_I2C0_SDA
|
||||
CFG_FUNC0_SS_X4, // I2C0_SCL -> AP_TO_I2C0_SDA
|
||||
CFG_FUNC0_SS_X4, // I2C1_SDA -> AP_BI_I2C1_SDA
|
||||
CFG_FUNC0_SS_X4, // I2C1_SCL -> AP_TO_ISC1_SCL
|
||||
CFG_FUNC0_SS_X4, // ISP0_SDA -> AP_BI_RCAM_I2C_SDA
|
||||
CFG_FUNC0_SS_X4, // ISP0_SCL -> AP_TO_RCAM_I2C_SCL
|
||||
CFG_FUNC0_SS_X4, // ISP1_SDA -> AP_TO_FCAM_I2C_SCL
|
||||
CFG_FUNC0_SS_X4, // ISP1_SCL -> AP_TO_FCAM_I2C_SCL
|
||||
|
||||
/* Port 11 */
|
||||
CFG_OUT_0_SS_X4_PD, // SENSOR0_RST -> AP_TO_RCAM_SHUTDOWN
|
||||
CFG_DISABLED_SS_X4_PD, // SENSOR0_CLK -> 45_AP_TO_RCAM_CLK_R
|
||||
CFG_IN_SS_X1_PU, // SENSOR0_XSHUTDOWN -> FCAM_TO_AP_ALS_INT_L
|
||||
CFG_DISABLED_SS_X1_PD, // SENSOR0_ISTRB -> BB_TO_AP_IPC_GPIO
|
||||
CFG_OUT_0_SS_X4_PD, // SENSOR1_RST -> AP_TO_FCAM_SHUTDOWN
|
||||
CFG_DISABLED_SS_X4_PD, // SENSOR1_CLK -> 45_AP_TO_FCAM_CLK_R
|
||||
CFG_DISABLED_SS_X1_PD, // SENSOR1_XSHUTDOWN -> N/C
|
||||
CFG_OUT_0_SS_X4_PD, // SENSOR1_ISTRB -> AP_TO_LEDDRV_EN
|
||||
|
||||
/* Port 12 */
|
||||
CFG_FUNC0_SS_X4_PD, // SPI3_MOSI -> AP_TO_CODEC_SPI3_MOSI
|
||||
CFG_FUNC0_SS_X1_PD, // SPI3_MISO -> CODEC_TO_AP_SPI3_MISO
|
||||
CFG_FUNC0_SS_X4_PD, // SPI3_SCLK -> AP_TO_CODEC_SPI3_CLK
|
||||
CFG_FUNC0_SS_X4_PD, // SPI3_SSIN -> AP_TO_CODEC_SPI3_CS_L
|
||||
CFG_DISABLED_SS_X1_PD, // I2C2_SDA -> N/C
|
||||
CFG_DISABLED_SS_X1_PD, // I2C2_SCL -> N/C
|
||||
CFG_DISABLED_SS_X4_PD, // GPIO22 -> AP_TO_PMU_KEEPACT
|
||||
CFG_DISABLED_SS_X1_PD, // GPIO23 -> LCM_TO_AP_HIFA_BSYNC
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED_SS_X1_PD, // GPIO24 -> BB_TO_AP_RESET_DET_L
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO25 -> BOARD_INFO -> BOOT_CONFIG[1]
|
||||
CFG_DISABLED_SS_X1_PD, // GPIO26 -> FORCE_DFU
|
||||
CFG_DISABLED_SS_X1_PD, // GPIO27 -> DFU_STATUS
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO28 -> N/C -> BOOT_CONFIG[2]
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO29 -> N/C -> BOOT_CONFIG[3]
|
||||
CFG_DISABLED, // GPIO30 -> NULL
|
||||
CFG_IN_SS_X4, // GPIO31 -> AP_TO_RADIO_ON_L
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED_SS_X4, // GPIO32 -> AP_TO_BB_JTAG_TCK
|
||||
CFG_DISABLED_SS_X4, // GPIO33 -> AP_TO_BB_JTAG_TMS
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO34 -> BOARD_INFO -> BOARD_REV3
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO35 -> BOARD_INFO -> BOARD_REV2
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO36 -> BOARD_INFO -> BOARD_REV1
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO37 -> BOARD_INFO -> BOARD_REV0
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO38 -> AP_TO_NAVAJO_DAISY_CHAIN
|
||||
CFG_DISABLED_SS_X1_PD, // DISPLAY_SYNC -> N/C
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED_SS_X1_PU, // SOCHOT0 -> BB_TO_AP_SOCHOT0
|
||||
CFG_FUNC0_SS_X4, // SOCHOT1 -> AP_TO_PMU_SOCHOT1
|
||||
CFG_FUNC0_SS_X4_PU, // UART0_TXD -> AP_TO_TRISTAR_DEBUG_UART0_TXD
|
||||
CFG_FUNC0_SS_X1_PU, // UART0_RXD -> TRISTAR_TO_AP_DEBUG_UART0_RXD
|
||||
CFG_DISABLED_SS_X1_PD, // DWI_DI -> N/C
|
||||
CFG_FUNC0_SS_X4_PD, // DWI_D0 -> 45_AP_TO_PMU_DWI_DO
|
||||
CFG_FUNC0_SS_X4_PD, // DWI_CLK -> 45_AP_TO_PMU_DWI_CLK
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0_SS_X4_PD, // I2S0_LRCK -> AP_TO_CODEC_ASP_I2S0_LRCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S0_BCLK -> 45_AP_TO_CODEC_ASP_I2S0_BCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S0_DOUT -> AP_TO_CODEC_ASP_I2S0_DOUT
|
||||
CFG_FUNC0_SS_X1_PD, // I2S0_DIN -> CODEC_TO_AP_ASP_I2S0_DIN
|
||||
CFG_DISABLED_SS_X4, // I2S1_MCK -> AP_TO_BB_JTAG_TRST_L
|
||||
CFG_FUNC0_SS_X4_PD, // I2S1_LRCK -> AP_TO_BB_I2S1_LRCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S1_BCLK -> 45_AP_TO_BB_I2S1_BCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S1_DOUT -> AP_TO_BB_I2S1_DOUT
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0_SS_X1_PD, // I2S1_DIN -> BB_TO_AP_I2S1_DIN
|
||||
CFG_FUNC0_SS_X4_PD, // I2S2_LRCK -> AP_TO_CODEC_XSP_I2S2_LRCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S2_BCLK -> 45_AP_TO_CODEC_XSP_I2S2_BCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S2_DOUT -> AP_TO_CODEC_XSP_I2S2_DOUT
|
||||
CFG_FUNC0_SS_X1_PD, // I2S2_DIN -> CODEC_TO_AP_XSP_I2S2_DIN
|
||||
CFG_IN_SS_X1_PU, // I2S3_MCK -> ALS_TO_AP_INT_L
|
||||
CFG_FUNC0_SS_X4_PD, // I2S3_LRCK -> AP_TO_BT_I2S3_LRCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S3_BCLK -> 45_AP_TO_BT_I2S3_BCLK
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0_SS_X4_PD, // I2S3_DOUT -> AP_TO_BT_I2S3_DOUT
|
||||
CFG_FUNC0_SS_X1_PD, // I2S3_DIN -> BT_TO_AP_I2S3_DIN
|
||||
CFG_IN_SS_X1_PD, // I2S4_MCK -> TRISTAR_TO_AP_INT
|
||||
CFG_FUNC0_SS_X4_PD, // I2S4_LRCK -> AP_TO_CODEC_VSP_I2S4_LRCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S4_BCLK -> 45_AP_TO_CODEC_VSP_I2S4_BCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S4_DOUT -> AP_TO_CODEC_VSP_I2S4_DOUT
|
||||
CFG_FUNC0_SS_X1_PD, // I2S4_DIN -> CODEC_TO_AP_VSP_I2S4_DIN
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0_SS_X4_PD, // TMR32_PWM0 -> OSCAR_BI_AP_TIME_SYNC_HOST_INT
|
||||
CFG_DISABLED_SS_X4_PD, // TMR32_PWM1 -> AP_TO_PMU_VIBE_PWM_EN
|
||||
CFG_FUNC0_SS_X4, // TMR32_PWM2 -> 45_AP_TO_TOUCH_CLK32K_RESET_L
|
||||
CFG_OUT_0_SS_X4, // SIO_7816UART0_SDA -> AP_TO_BB_HSIC1_RDY
|
||||
CFG_DISABLED_SS_X1_PD, // SIO_7816UART0_SCL -> BB_TO_AP_HSIC1_RDY
|
||||
CFG_DISABLED_SS_X1_PD, // SIO_7816UART0_RST -> BB_TO_AP_HSIC1_REMOTE_WAKE
|
||||
CFG_OUT_0_SS_X4, // SIO_7816UART1_SDA -> AP_TO_WLAN_HSIC2_RDY
|
||||
CFG_IN_SS_X1_PD, // SIO_7816UART1_SCL -> WLAN_TO_AP_HSIC2_RDY
|
||||
|
||||
/* Port 21 */
|
||||
CFG_IN_SS_X1_PD, // SIO_7816UART0_RST -> WLAN_TO_AP_HSIC2_REMOTE_WAKE
|
||||
CFG_FUNC0_SS_X4_PU, // UART6_TXD -> AP_TO_TRISTAR_ACC_UART6_TXD
|
||||
CFG_FUNC0_SS_X1_PU, // UART6_RXD -> TRISTAR_TO_AP_ACC_UART6_RXD
|
||||
CFG_DISABLED_SS_X4_PD, // I2C3_SDA -> AP_BI_OSCAR_SWDIO_1V8
|
||||
CFG_DISABLED_SS_X4_PD, // I2C3_SCL -> AP_TO_OSCAR_SWDCLK_1V8
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED_SS_X1_PD, // EPD_HPD -> N/C
|
||||
CFG_FUNC0_SS_X4_PD, // I2S0_MCK -> 45_AP_TO_CODEC_I2S_MCLK_R
|
||||
CFG_FUNC0_SS_X4_PD, // I2S2_MCK -> 45_AP_TO_SPKAMP_I2S2_MCLK_R
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
return gpio_default_cfg;
|
||||
}
|
||||
@@ -0,0 +1,40 @@
|
||||
# Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2045=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_MED \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=0 \
|
||||
TARGET_VID0_CLK_CFG=0x86100000 \
|
||||
DISPLAY_IPHONE_TUNABLES=1 \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
TARGET_DSIM_CONFIG=0x00400000 \
|
||||
TARGET_DSIM_DPHYCTL=0x30 \
|
||||
TARGET_DSIM_UP_CODE=0x1 \
|
||||
TARGET_DSIM_DOWN_CODE=0x1 \
|
||||
TARGET_DSIM_SUPPRESS=0x1 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_GPU=1 \
|
||||
WITH_CPU_APSC=1
|
||||
|
||||
# this board may have no PMU installed, so AMP should not panic because of that
|
||||
OPTIONS += \
|
||||
AMP_NO_PMU_PANIC=1
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
Reference in new issue
Block a user