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@@ -0,0 +1,27 @@
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/*
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* Copyright (C) 2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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||||
*
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||||
* This document may not be reproduced or transmitted in any form,
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||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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*/
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#ifndef __TARGET_ADBE_SETTINGS_H
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#define __TARGET_ADBE_SETTINGS_H
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static struct adbe_v1_tuneable adbe_tuneables[] = {
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{
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.name = "default",
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.adbe0_vblank_pos_vbi_pulse = 0x0000,
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.adbe0_vblank_clk_gate_wakeup = 0x0000,
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.adbe0_vblank_clk_gate_idle = 0x0001,
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.adbe0_vblank_blk_idle_dpb = 0x0000,
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.adbe0_vblank_blk_idle_aap = 0x0000,
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.adbe0_tunable_mode_ctrl = (DBEMODECNTL_DYN_CLK_GATE_ENABLE | DBEMODECNTL_AFC_TEARDOWN_ENABLE | DBEMODECNTL_PMGR_CLK_GATE_ENABL| DBEMODECNTL_BLK_CLK_GATE_ENABLE),
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.adbe0_aap_support = 1,
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},
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};
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#endif
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@@ -0,0 +1,106 @@
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/*
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* Copyright (C) 2011-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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||||
* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
|
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* Apple Inc.
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*/
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static const struct amc_param amc_params = {
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.flags = (FLAG_AMC_PARAM_BUSTAT23 | FLAG_AMC_PARAM_SLOW_BOOT | FLAG_AMC_PARAM_ZQCL),
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.tREFi = 0x5d,
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.longsrcnt = 0x2008,
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.srextrarefcnt = 0x00020000,
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.rdlat = 6,
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.wrlat = 3,
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.phyrdlat = 10,
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.phywrlat = 2,
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.pdn = 0x22000403,
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.read = 0x00000203,
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.bustat = 0x00222209,
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.bustat2 = 0x00222209,
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.derate = 0x2483135b,
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.mcphyupdate = 0x05030000,
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.autoref_params = 0x00000021,
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.pwrmngtparam_small = 0x00011000,
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.pwrmngtparam_guided = 0x01801000,
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.chnldec = 0x00050000,
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.aref_freq0 = 0x00000110,
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.schen_default = 0x00000110,
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.mr1 = 0x44,
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.mr2 = 0x1a,
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.mr3 = 0x01,
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.pwrmngten_default = 0x00100100,
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.mcphyupdate1 = 0x00000001,
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.odts = 0x190,
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.readleveling = 0x00000300,
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.offset_shift_hynix = 0,
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.offset_shift_elpida = 1,
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.freq = {
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{ // 800MHz
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.cas = 0x00000308,
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.pch = 0x00030612,
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.act = 0x12040908,
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.autoref = 0x19350000,
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.selfref = 0x00039060,
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.modereg = 0x20250782,
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.mifcassch = 0x00000110,
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.arefparam = 0x0c022131,
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},
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{ // 400MHz
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.cas = 0x00000005,
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.pch = 0x00000009,
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.act = 0x09020505,
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.autoref = 0x0d1b0000,
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.selfref = 0x0001d000,
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.modereg = 0x00130000,
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.mifcassch = 0x00000000,
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.arefparam = 0x00000101,
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},
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{ // 200MHz
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.cas = 0x00000003,
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.pch = 0x00000005,
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.act = 0x08020303,
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.autoref = 0x070e0000,
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.selfref = 0x0000f000,
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.modereg = 0x000a0000,
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.mifcassch = 0x00000000,
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.arefparam = 0x00000101,
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},
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{ // 50MHz
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.cas = 0x00000003,
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.pch = 0x00000003,
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.act = 0x08020303,
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.autoref = 0x02040000,
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.selfref = 0x00004000,
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.modereg = 0x00030000,
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.mifcassch = 0x00000000,
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.arefparam = 0x00000101,
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}
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}
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};
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static const struct amc_tunable amc_tunables[] = {
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{ &rAMC_MCSARBCFG, 0x00000001 },
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{ &rAMC_OPIDLETMR, 0x00200000 },
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{ &rAMC_OPTMRADJPARAM, 0x20400064 },
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{ &rAMC_MIFACTSCH, 0x00000001 },
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{ &rAMC_MIFCASSCH_FREQ(0), 0x10000010 },
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{ &rAMC_PSQRQCTL0, 0xff010110 },
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{ &rAMC_PSQRQCTL1, 0x00001728 },
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{ &rAMC_PSQRQTIMER0, 0x00000040 },
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{ &rAMC_PSQRQTIMER1, 0x00000014 },
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{ &rAMC_PSQRQTIMER2, 0x00000040 },
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{ &rAMC_PSQRQBRST, 0x04100410 },
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{ &rAMC_PSQRQSCHCRD, 0x00101400 },
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{ &rAMC_PSQWQCTL0, 0x00010100 },
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{ &rAMC_PSQWQBRST, 0x04100410 },
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{ &rAMC_PSQWQSCHCRD, 0x00101400 },
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{ &rAMC_MCUQOS, 0x00001919 },
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{ &rAMC_MCUQOSLLT, 0x0000011f },
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};
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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||||
* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ASPNANDCONFIG_H
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#define __TARGET_ASPNANDCONFIG_H
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//MLC devices
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#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_DIES_IN_PARALLEL 2
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#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
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//TLC devices
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#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
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// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
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#define ASPNAND_INDIRECTION_MEMORY (2*1024*1024)
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#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
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#endif
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@@ -0,0 +1,37 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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||||
* It is considered confidential and proprietary.
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||||
*
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||||
* This document may not be reproduced or transmitted in any form,
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||||
* in whole or in part, without the express written permission of
|
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* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* iPad4,x specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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#define GPIO_LCD_PWR_EN GPIO( 2, 7)
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#define GPIO_RINGER_AB GPIO(13, 6)
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/* Board Revision */
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#define GPIO_BOARD_REV0 GPIO(14, 6)
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#define GPIO_BOARD_REV1 GPIO(14, 5)
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#define GPIO_BOARD_REV2 GPIO(14, 4)
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#define GPIO_BOARD_REV3 GPIO(14, 3)
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/* which IICs to initialize */
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#define IICS_MASK (0x5)
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#define TRISTAR_IIC_BUS (0)
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/* D2089 watchdog tickle, 'KEEPACT' */
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#define GPIO_WDOG_TICKLE GPIO(12, 6)
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,90 @@
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD2045_ACTIVE3, 0xAE }, // Current OTP enables LDO{1,2,3,4,5,7}, disable LDO4.
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{ PMU_IIC_BUS, kD2045_ACTIVE6, 0x37 }, // enable BUCK3_SW1, BUCK3_SW2, BUCK3_SW3, BUCK4_SW1, BUCK4_SW2
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{ PMU_IIC_BUS, kD2045_ACTIVE3, 0xBE }, // enable LDO4 along with LDO{1,2,3,5,7}
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{ PMU_IIC_BUS, kD2045_HIBERNATE1, 0x18 },
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{ PMU_IIC_BUS, kD2045_HIBERNATE3, 0x18 },
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{ PMU_IIC_BUS, kD2045_HIBERNATE6, 0x24 },
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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};
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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{ PMU_IIC_BUS, kD2045_GPIO1, 0xBB }, // AUD_ARRAY_HOST_WAKE In, R Edge, No PU, Wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO2, 0xBB }, // WLAN2_HOST_WAKE IN, R Edge, No PU, Wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO3, 0x0B }, // WLAN2_REG_ON Out 1, Buck 3, push-pull
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{ PMU_IIC_BUS, kD2045_GPIO4, 0xB9 }, // TRI_INT In, R Edge, No PU, no wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO5, 0x09 }, // BT1_REG_ON
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{ PMU_IIC_BUS, kD2045_GPIO6, 0xBB }, // BT1_HOST_WAKE In, R Edge, No PU, wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO7, 0xBB }, // WLAN1_HOST_WAKE In, R Edge, No PU, wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO8, 0xBB }, // ENET_PHY_HOST_WAKE In, R Edge, No PU, wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO9, 0x09 }, // BT2_REG_ON Out 0, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD2045_GPIO10, 0xBB }, // BT2_HOST_WAKE In, R Edge, No PU, wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO11, 0x0B }, // WLAN1_REG_ON Out 1, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD2045_GPIO12, 0xBB }, // ENET_PME_1V8 In, R Edge, No PU, wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO13, 0xBB }, // MCU_HOST_WAKE In, R Edge, No PU, wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO14, 0x0B }, // PS_ON (16V) Out 1, VBUCK3, open drain
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{ PMU_IIC_BUS, kD2045_GPIO15, 0x7A }, // PMU_WAKE_ON_VCC
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{ PMU_IIC_BUS, kD2045_GPIO16, 0xBB }, // ACCEL_HOST_WAKE1 In, R Edge, No PU, wake, PD
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{ PMU_IIC_BUS, kD2045_OUT_32K, 0x49 }, // OUT_32K (WLAN_CLK32K) Out 32K, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD2045_BUCK_DWI_CTRL0, 0x03 }, // enable DWI for BUCK0, BUCK1
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{ PMU_IIC_BUS, kD2045_BUTTON1_CONF, 0x84 }, // PMU_BUTTTON1
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{ PMU_IIC_BUS, kD2045_BUTTON2_CONF, 0x84 }, // PMU_BUTTTON2
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{ PMU_IIC_BUS, kD2045_BUTTON3_CONF, 0xD4 }, // PMU_BUTTTON3
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{ PMU_IIC_BUS, kD2045_BUTTON4_CONF, 0x94 }, // PMU_BUTTTON4
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// Special function
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{ PMU_IIC_BUS, kDIALOG_BUTTON_DBL, 0x00 }, //
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{ PMU_IIC_BUS, kD2045_BUTTON_WAKE, 0x00 }, // AUD_ARRAY_HOST_WAKE
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{ PMU_IIC_BUS, kD2045_RESET_IN1_CONF,0x02}, // PMU_RESET_IN1_WDOG
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{ PMU_IIC_BUS, kD2045_RESET_IN2_CONF,0x00}, // PMU_RESET_IN2_TRISTAR
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{ PMU_IIC_BUS, kD2045_RESET_IN3_CONF,0x14}, // SOCHOT1_L
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};
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static const struct core_rails_struct soc_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2045_BUCK2_VSEL }
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||||
};
|
||||
|
||||
static const struct core_rails_struct cpu_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2045_BUCK0_VSEL }
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};
|
||||
|
||||
static const struct core_rails_struct ram_rails[] =
|
||||
{
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{ PMU_IIC_BUS, 0, kD2045_BUCK5_VSEL }
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};
|
||||
|
||||
#endif /* POWERCONFIG_PMU_SETUP */
|
||||
|
||||
#define TARGET_POWER_NO_BATTERY 1
|
||||
#define ALWAYS_BOOT_BATTERY_VOLTAGE (3000)
|
||||
#define PRECHARGE_BACKLIGHT_LEVEL 103
|
||||
#define TARGET_MAX_USB_INPUT_CURRENT 2400
|
||||
|
||||
#define ACC_PWR_LDO (6)
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|
||||
#endif
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define one debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (0)
|
||||
|
||||
#define HDQGAUGE_SERIAL_PORT (5)
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define UART_OVERSAMPLE_OVERRIDE (11)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_USBCONFIG_H
|
||||
#define __TARGET_USBCONFIG_H
|
||||
|
||||
#ifdef USBPHY_OTGTUNE0
|
||||
|
||||
#undef USBPHY_OTGTUNE0
|
||||
#define USBPHY_OTGTUNE0 (0x3644D3F3)
|
||||
|
||||
#endif /* USBPHY_OTGTUNE0 */
|
||||
|
||||
#endif /* __TARGET_USBCONFIG_H */
|
||||
@@ -0,0 +1,232 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/flash_nor.h>
|
||||
#include <drivers/iic.h>
|
||||
#include <drivers/power.h>
|
||||
#include <lib/devicetree.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <lib/syscfg.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <sys.h>
|
||||
#include <sys/boot.h>
|
||||
#include <sys/menu.h>
|
||||
#include <sys/task.h>
|
||||
#include <target.h>
|
||||
|
||||
static bool gpio_board_rev_valid;
|
||||
static u_int32_t gpio_board_rev;
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
|
||||
static u_int32_t b184_get_board_rev(void)
|
||||
{
|
||||
|
||||
if (!gpio_board_rev_valid) {
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV3, GPIO_PUP);
|
||||
|
||||
spin(100); // Wait 100us
|
||||
|
||||
gpio_board_rev =
|
||||
(gpio_read(GPIO_BOARD_REV3) << 3) |
|
||||
(gpio_read(GPIO_BOARD_REV2) << 2) |
|
||||
(gpio_read(GPIO_BOARD_REV1) << 1) |
|
||||
(gpio_read(GPIO_BOARD_REV0) << 0);
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_DFLT);
|
||||
|
||||
gpio_board_rev_valid = true;
|
||||
}
|
||||
|
||||
return gpio_board_rev;
|
||||
}
|
||||
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return platform_get_request_dfu2() && power_has_usb();
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
#if WITH_HW_POWER
|
||||
if (power_get_boot_flag() == kPowerBootFlagColdButton) *cold_button_boot = true;
|
||||
#else
|
||||
*cold_button_boot = false;
|
||||
#endif // WITH_HW_POWER
|
||||
|
||||
return !*cold_button_boot || platform_get_request_dfu1();
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
u_int32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
env_set("boot-device", "asp_nand", 0);
|
||||
}
|
||||
|
||||
#endif // WITH_ENV
|
||||
|
||||
bool target_has_tristar2(void)
|
||||
{
|
||||
return true; // TODO: Does it have tristar2?
|
||||
}
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
#if WITH_HW_DISPLAY_EDP
|
||||
DTNode *clcd_node = NULL, *backlight_node = NULL, *lcd_node = NULL;
|
||||
#endif
|
||||
DTNode *node;
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
// Store secondary mac addresses into products node
|
||||
if (FindNode(0, "product", &node)) {
|
||||
propName = "mac-address-wifi1";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (env_get("wifi1addr")) {
|
||||
env_get_ethaddr("wifi1addr", propData);
|
||||
} else {
|
||||
int retlen = 0;
|
||||
if (!target_get_property(TARGET_PROPERTY_WIFI1_MACADDR, propData, 6, &retlen)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
propName = "mac-address-ethernet1";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (env_get("eth1addr")) {
|
||||
env_get_ethaddr("eth1addr", propData);
|
||||
} else {
|
||||
int retlen = 0;
|
||||
if (!target_get_property(TARGET_PROPERTY_ETH1_MACADDR, propData, 6, &retlen)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
propName = "mac-address-bluetooth1";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (env_get("bt1addr")) {
|
||||
env_get_ethaddr("bt1addr", propData);
|
||||
} else {
|
||||
int retlen = 0;
|
||||
if (!target_get_property(TARGET_PROPERTY_BT1_MACADDR, propData, 6, &retlen)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Store second wlan mac address into wlan1 node
|
||||
if (FindNode(0, "arm-io/usb-complex/usb-ehci1/wlan1", &node)) {
|
||||
propName = "local-mac-address";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (env_get("wifi1addr")) {
|
||||
env_get_ethaddr("wifi1addr", propData);
|
||||
} else {
|
||||
int retlen = 0;
|
||||
if (!target_get_property(TARGET_PROPERTY_WIFI1_MACADDR, propData, 6, &retlen)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Add bluetooth, ethernet second mac address when node is available
|
||||
// <rdar://problem/14324725> B184 /12A43 : bluetooth not responding
|
||||
|
||||
// TriStar 1 on older systems
|
||||
if (!target_has_tristar2()) {
|
||||
if (FindNode(0, "arm-io/i2c2/tristar", &node)) {
|
||||
propName = "compatible";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
strlcpy(propData, "tristar,cbtl1608", kPropNameLength);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Update charger calibration data
|
||||
if (FindNode(0, "charger", &node)) {
|
||||
propName = "usb-input-limit-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('CBAT', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif // WITH_DEVICETREE
|
||||
@@ -0,0 +1,271 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* THIS STRUCT IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: version 1.16
|
||||
I/O Spreadsheet tracker: 12739020&15521285
|
||||
*/
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_FUNC0, // 0 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_FUNC0 | FAST_SLEW, // 1 : WDOG -> SOC_WDOG
|
||||
CFG_IN, // 2 : GPIO[0] -> PMU_BUTTON1
|
||||
CFG_IN, // 3 : GPIO[1] -> PMU_BUTTON2
|
||||
CFG_IN, // 4 : GPIO[2] -> PMU_BUTTON3
|
||||
CFG_IN, // 5 : GPIO[3] -> PMU_BUTTON4
|
||||
CFG_IN, // 6 : GPIO[4] -> ACCEL_HOST_WAKE1
|
||||
CFG_IN, // 7 : GPIO[5] -> PS_ON_SOC
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN, // 8 : GPIO[6] -> AUD_ARRAY_HOST_WAKE
|
||||
CFG_IN, // 9 : GPIO[7] -> BT2_BTWAKE
|
||||
CFG_IN, // 10 : GPIO[8] -> ENET_PHY_HOST_WAKE
|
||||
CFG_IN, // 11 : GPIO[9] -> MCU_HOST_WAKE
|
||||
CFG_OUT_0 | PULL_DOWN | SLOW_SLEW, // 12 : GPIO[10] -> SOC_TO_ENET_PME_MODE_SEL
|
||||
CFG_IN, // 13 : GPIO[11] -> SOC_TO_MCU_RESET_L
|
||||
CFG_IN, // 14 : GPIO[12] -> SOC_TO_MCU_BOOTLOAD
|
||||
CFG_IN | PULL_UP, // 15 : GPIO[13] -> PMU_IRQ_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_IN, // 16 : GPIO[14] -> SOC_WLAN_ASTP_SEL
|
||||
CFG_IN, // 17 : GPIO[15] -> ENET_HSIC_DEVICE_READY
|
||||
CFG_IN | PULL_DOWN, // 18 : GPIO[16] -> BOARDID_3
|
||||
CFG_IN, // 19 : GPIO[17] -> TRI_INT
|
||||
CFG_IN | PULL_DOWN, // 20 : GPIO[18] -> BOOTCONFIG_0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 21 : GPIO[19] -> PMU_KEEPACT
|
||||
CFG_DISABLED, // 22 : GPIO[20] -> NC_SPDIF_LOCK_L
|
||||
CFG_DISABLED, // 23 : GPIO[21] -> NC_SPDIF_INT_L
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 32 : UART1_TXD -> SOC_UART1_TO_MCU_TXD
|
||||
CFG_FUNC0, // 33 : UART1_RXD -> MCU_TO_SOC_UART1_RXD
|
||||
CFG_OUT_0, // 34 : UART1_RTSN -> MCU_SWCLK
|
||||
CFG_IN | SLOW_SLEW, // 35 : UART1_CTSN -> MCU_SWDIO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : UART2_TXD -> SOC_UART2_TO_BT_TXD
|
||||
CFG_FUNC0, // 37 : UART2_RXD -> BT_TO_SOC_UART2_RXD
|
||||
CFG_FUNC0, // 38 : UART2_RTSN -> SOC_UART2_TO_BT_RTSB
|
||||
CFG_FUNC0, // 39 : UART2_CTSN -> BT_TO_SOC_UART2_CTSB
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : UART3_TXD -> WLAN1_TO_SOC_UART3_RXD
|
||||
CFG_FUNC0, // 41 : UART3_RXD -> SOC_UART3_TO_WLAN1_TXD
|
||||
CFG_DISABLED, // 42 : UART3_RTSN -> NC_UART3_RTSN
|
||||
CFG_DISABLED, // 43 : UART3_CTSN -> NC_UART3_CTSN
|
||||
CFG_DISABLED, // 44 : UART5_RTXD -> UART5_RTXD
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 64 : UART4_TXD -> SOC_UART4_TO_WLAN2_TXD
|
||||
CFG_FUNC0, // 65 : UART4_RXD -> WLAN2_TO_SOC_UART4_RXD
|
||||
CFG_DISABLED, // 66 : UART4_RTSN -> NC_UART4_RTSN
|
||||
CFG_DISABLED, // 67 : UART4_CTSN -> NC_UART4_CTSN
|
||||
CFG_DISABLED, // 68 : SPI1_SCLK -> NC_SPI1_SCLK
|
||||
CFG_DISABLED, // 69 : SPI1_MOSI -> NC_SPI1_MOSI
|
||||
CFG_DISABLED, // 70 : SPI1_MISO -> NC_SPI1_MISO
|
||||
CFG_DISABLED, // 71 : SPI1_SSIN -> NC_SPI1_SSIN
|
||||
|
||||
/* Port 9 */
|
||||
CFG_IN | PULL_DOWN, // 72 : SPI0_SCLK -> BOARDID_0
|
||||
CFG_IN | PULL_DOWN, // 73 : SPI0_MOSI -> BOARDID_1
|
||||
CFG_IN | PULL_DOWN, // 74 : SPI0_MISO -> BOARDID_2
|
||||
CFG_DISABLED, // 75 : SPI0_SSIN -> NC_SPI0_SSIN
|
||||
CFG_DISABLED, // 76 : SPI2_SCLK -> NC_SPI2_SCLK
|
||||
CFG_DISABLED, // 77 : SPI2_MOSI -> NC_SPI2_MOSI
|
||||
CFG_DISABLED, // 78 : SPI2_MISO -> NC_SPI2_MISO
|
||||
CFG_DISABLED, // 79 : SPI2_SSIN -> NC_SPI2_SSIN
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 80 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 81 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 82 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 83 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 84 : ISP0_SDA -> (NC)
|
||||
CFG_DISABLED, // 85 : ISP0_SCL -> (NC)
|
||||
CFG_DISABLED, // 86 : ISP1_SDA -> (NC)
|
||||
CFG_DISABLED, // 87 : ISP1_SCL -> (NC)
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // 88 : SENSOR0_RST ->
|
||||
CFG_DISABLED, // 89 : SENSOR0_CLK ->
|
||||
CFG_DISABLED, // 90 : SENSOR0_XSHUTDOWN ->
|
||||
CFG_DISABLED, // 91 : SENSOR0_ISTRB ->
|
||||
CFG_DISABLED, // 92 : SENSOR1_RST ->
|
||||
CFG_DISABLED, // 93 : SENSOR1_CLK ->
|
||||
CFG_DISABLED, // 94 : SENSOR1_XSHUTDOWN ->
|
||||
CFG_DISABLED, // 95 : SENSOR1_ISTRB ->
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : SPI3_MOSI -> NC_SPI3_MOSI
|
||||
CFG_DISABLED, // 97 : SPI3_MISO -> NC_SPI3_MISO
|
||||
CFG_DISABLED, // 98 : SPI3_SCLK -> NC_SPI3_SCLK
|
||||
CFG_DISABLED, // 99 : SPI3_SSIN -> NC_SPI3_SSIN
|
||||
CFG_DISABLED, // 100 : I2C2_SDA -> I2C2_SPDIF_SDA_1V8
|
||||
CFG_DISABLED, // 101 : I2C2_SCL -> I2C2_SPDIF_SCL_1V8
|
||||
CFG_DISABLED, // 102 : GPIO[22] -> NC_SPDIF_RESET_L
|
||||
CFG_OUT_0 | PULL_UP | SLOW_SLEW, // 103 : GPIO[23] -> ENET_RESET_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_IN, // 104 : GPIO[24] -> ENET_PME_1V8
|
||||
CFG_IN | PULL_DOWN, // 105 : GPIO[25] -> BOOTCONFIG_1
|
||||
CFG_IN, // 106 : GPIO[26] -> FORCE_DFU
|
||||
CFG_OUT_0 | SLOW_SLEW, // 107 : GPIO[27] -> DFU_STATUS
|
||||
CFG_IN | PULL_DOWN, // 108 : GPIO[28] -> BOOTCONFIG_2
|
||||
CFG_IN | PULL_DOWN, // 109 : GPIO[29] -> BOOTCONFIG_3
|
||||
CFG_IN, // 110 : GPIO[30] -> BT1_BTWAKE
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> SOC_ANALOG_SEL
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : GPIO[32] -> SOC_SPDIF_SEL
|
||||
CFG_DISABLED, // 113 : GPIO[33] -> SOC_ANALOG_PWR_EN
|
||||
CFG_IN | PULL_DOWN, // 114 : GPIO[34] -> BOARDREV_3
|
||||
CFG_IN | PULL_DOWN, // 115 : GPIO[35] -> BOARDREV_2
|
||||
CFG_IN | PULL_DOWN, // 116 : GPIO[36] -> BOARDREV_1
|
||||
CFG_IN | PULL_DOWN, // 117 : GPIO[37] -> BOARDREV_0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 118 : GPIO[38] -> SOC_BT_SEL
|
||||
CFG_DISABLED, // 119 : DISP_VSYNC -> SOC_DISP_VSYNC
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0, // 121 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_FUNC0 | FAST_SLEW, // 122 : UART0_TXD -> UART0_TXD
|
||||
CFG_FUNC0, // 123 : UART0_RXD -> UART0_RXD
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 125 : DWI_DO -> DWI_AP_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 126 : DWI_CLK -> DWI_AP_CLK
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0, // 128 : I2S0_LRCK -> MCA_FSYNC_1V8
|
||||
CFG_FUNC0, // 129 : I2S0_BCLK -> MCA_BCLK_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 130 : I2S0_DOUT -> MCA0_DOUT
|
||||
CFG_FUNC0, // 131 : I2S0_DIN -> MIC_DATA_1V8
|
||||
CFG_DISABLED, // 132 : I2S1_MCK -> I2S0_MCK
|
||||
CFG_FUNC0, // 133 : I2S1_LRCK -> MCA_FSYNC_1V8
|
||||
CFG_FUNC0, // 134 : I2S1_BCLK -> MCA_BCLK_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 135 : I2S1_DOUT -> MCA1_DOUT
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // 136 : I2S1_DIN -> MCA1_DIN
|
||||
CFG_FUNC0, // 137 : I2S2_LRCK -> MCA_FSYNC_1V8
|
||||
CFG_FUNC0, // 138 : I2S2_BCLK -> MCA_BCLK_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 139 : I2S2_DOUT -> MCA2_DOUT
|
||||
CFG_FUNC0, // 140 : I2S2_DIN -> MCU_MISO_1V8
|
||||
CFG_DISABLED, // 141 : I2S3_MCK -> NC_I2S2_MCK
|
||||
CFG_FUNC0, // 142 : I2S3_LRCK -> MCA_FSYNC_1V8
|
||||
CFG_FUNC0, // 143 : I2S3_BCLK -> MCA_BCLK_1V8
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 144 : I2S3_DOUT -> MCA3_DOUT
|
||||
CFG_FUNC0, // 145 : I2S3_DIN -> MCA3_DIN
|
||||
CFG_DISABLED, // 146 : I2S4_MCK -> NC_I2S4_MCK
|
||||
CFG_DISABLED, // 147 : I2S4_LRCK -> NC_I2S4_LRCLK
|
||||
CFG_DISABLED, // 148 : I2S4_BCLK -> NC_I2S4_BCLK
|
||||
CFG_DISABLED, // 149 : I2S4_DOUT -> NC_I2S4_DOUT
|
||||
CFG_DISABLED, // 150 : I2S4_DIN -> NC_I2S4_DIN
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // 160 : TMR32_PWM0 -> NC_TMR32_PWM0
|
||||
CFG_DISABLED, // 161 : TMR32_PWM1 -> NC_TMR32_PWM1
|
||||
CFG_DISABLED, // 162 : TMR32_PWM2 -> NC_TMR32_PWM2
|
||||
CFG_OUT_0 | FAST_SLEW, // 163 : SIO_7816UART0_SDA -> WLAN2_HOST_READY
|
||||
CFG_IN, // 164 : SIO_7816UART0_SCL -> WLAN2_DEVICE_READY
|
||||
CFG_IN, // 165 : SIO_7816UART0_RST -> WLAN2_HSIC_RESUME
|
||||
CFG_OUT_0, // 166 : SIO_7816UART1_SDA -> WLAN1_HOST_READY
|
||||
CFG_IN, // 167 : SIO_7816UART1_SCL -> WLAN1_DEVICE_READY
|
||||
|
||||
/* Port 21 */
|
||||
CFG_IN, // 168 : SIO_7816UART1_RST -> WLAN1_HSIC_RESUME
|
||||
CFG_FUNC0 | FAST_SLEW, // 169 : UART6_TXD -> UART6_TXD
|
||||
CFG_FUNC0, // 170 : UART6_RXD -> UART6_RXD
|
||||
CFG_DISABLED, // 171 : I2C3_SDA -> I2C_ARRAY_SCL_1V8
|
||||
CFG_DISABLED, // 172 : I2C3_SCL -> I2C_ARRAY_SDA_1V8
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED, // 192 : EDP_HPD -> (NC)
|
||||
CFG_DISABLED, // 193 : I2S0_MCK -> I2S0_MCK
|
||||
CFG_DISABLED, // 194 : I2S2_MCK -> NC_I2S2_MCK
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
return gpio_default_cfg;
|
||||
}
|
||||
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <target.h>
|
||||
#include <target/powerconfig.h>
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
bool
|
||||
target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
|
||||
{
|
||||
int length = 0;
|
||||
bool result = false;
|
||||
|
||||
if ((result = target_get_property_base(prop, data, maxdata, retlen)) == false) {
|
||||
switch(prop) {
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (retlen != NULL) *retlen = length;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,45 @@
|
||||
# Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2045=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_MED \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=0 \
|
||||
TARGET_HAS_BASEBAND=$(TARGET_HAS_BASEBAND) \
|
||||
TARGET_SPARE0_CLK_CFG=0x83000006 \
|
||||
TARGET_VID0_CLK_CFG=0x81000000 \
|
||||
TARGET_DDR_798M=1 \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
WITH_TARGET_AMC_PARAMS=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_GPU=1 \
|
||||
WITH_CPU_APSC=1 \
|
||||
BT_DTPATH=\"arm-io/uart1/bluetooth\" \
|
||||
WIFI_DTPATH=\"arm-io/usb-complex/usb-ehci0/wlan0\" \
|
||||
WITH_TARGET_USB_CONFIG=1 \
|
||||
ETHERNET_DTPATH=\"arm-io/usb-complex/usb-ehci0/lan0\"
|
||||
|
||||
# TODO: Wifi and BT config are almost certainly wrong here.
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
|
||||
ifneq ($(PRODUCT),LLB)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/properties.o
|
||||
endif
|
||||
Reference in new issue
Block a user