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@@ -0,0 +1,27 @@
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/*
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* Copyright (C) 2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ADBE_SETTINGS_H
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#define __TARGET_ADBE_SETTINGS_H
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static struct adbe_v1_tuneable adbe_tuneables[] = {
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{
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.name = "default",
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.adbe0_vblank_pos_vbi_pulse = 0x0000,
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.adbe0_vblank_clk_gate_wakeup = 0x0000,
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.adbe0_vblank_clk_gate_idle = 0x0001,
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.adbe0_vblank_blk_idle_dpb = 0x0000,
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.adbe0_vblank_blk_idle_aap = 0x0000,
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.adbe0_tunable_mode_ctrl = (DBEMODECNTL_DYN_CLK_GATE_ENABLE | DBEMODECNTL_AFC_TEARDOWN_ENABLE | DBEMODECNTL_PMGR_CLK_GATE_ENABL| DBEMODECNTL_BLK_CLK_GATE_ENABLE),
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.adbe0_aap_support = 1,
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},
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};
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#endif
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@@ -0,0 +1,106 @@
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/*
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* Copyright (C) 2011-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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static const struct amc_param amc_params = {
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.flags = (FLAG_AMC_PARAM_BUSTAT23 | FLAG_AMC_PARAM_SLOW_BOOT | FLAG_AMC_PARAM_ZQCL),
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.tREFi = 0x5d,
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.longsrcnt = 0x2008,
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.srextrarefcnt = 0x00020000,
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.rdlat = 6,
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.wrlat = 3,
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.phyrdlat = 10,
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.phywrlat = 2,
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.pdn = 0x22000403,
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.read = 0x00000203,
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.bustat = 0x00222209,
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.bustat2 = 0x00222209,
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.derate = 0x2483135b,
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.mcphyupdate = 0x05030000,
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.autoref_params = 0x00000021,
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.pwrmngtparam_small = 0x00011000,
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.pwrmngtparam_guided = 0x01801000,
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.chnldec = 0x00050000,
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.aref_freq0 = 0x00000110,
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.schen_default = 0x00000110,
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.mr1 = 0x44,
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.mr2 = 0x1a,
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.mr3 = 0x01,
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.pwrmngten_default = 0x00100100,
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.mcphyupdate1 = 0x00000001,
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.odts = 0x190,
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.readleveling = 0x00000300,
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.offset_shift_hynix = 0,
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.offset_shift_elpida = 1,
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.freq = {
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{ // 800MHz
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.cas = 0x00000308,
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.pch = 0x00030612,
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.act = 0x12040908,
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.autoref = 0x19350000,
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.selfref = 0x00039060,
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.modereg = 0x20250782,
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.mifcassch = 0x00000110,
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.arefparam = 0x0c022131,
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},
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{ // 400MHz
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.cas = 0x00000005,
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.pch = 0x00000009,
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.act = 0x09020505,
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.autoref = 0x0d1b0000,
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.selfref = 0x0001d000,
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.modereg = 0x00130000,
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.mifcassch = 0x00000000,
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.arefparam = 0x00000101,
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},
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{ // 200MHz
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.cas = 0x00000003,
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.pch = 0x00000005,
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.act = 0x08020303,
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.autoref = 0x070e0000,
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.selfref = 0x0000f000,
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.modereg = 0x000a0000,
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.mifcassch = 0x00000000,
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.arefparam = 0x00000101,
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},
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{ // 50MHz
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.cas = 0x00000003,
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.pch = 0x00000003,
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.act = 0x08020303,
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.autoref = 0x02040000,
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.selfref = 0x00004000,
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.modereg = 0x00030000,
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.mifcassch = 0x00000000,
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.arefparam = 0x00000101,
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}
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}
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};
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static const struct amc_tunable amc_tunables[] = {
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{ &rAMC_MCSARBCFG, 0x00000001 },
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{ &rAMC_OPIDLETMR, 0x00200000 },
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{ &rAMC_OPTMRADJPARAM, 0x20400064 },
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{ &rAMC_MIFACTSCH, 0x00000001 },
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{ &rAMC_MIFCASSCH_FREQ(0), 0x10000010 },
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{ &rAMC_PSQRQCTL0, 0xff010110 },
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{ &rAMC_PSQRQCTL1, 0x00001728 },
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{ &rAMC_PSQRQTIMER0, 0x00000040 },
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{ &rAMC_PSQRQTIMER1, 0x00000014 },
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{ &rAMC_PSQRQTIMER2, 0x00000040 },
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{ &rAMC_PSQRQBRST, 0x04100410 },
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{ &rAMC_PSQRQSCHCRD, 0x00101400 },
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{ &rAMC_PSQWQCTL0, 0x00010100 },
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{ &rAMC_PSQWQBRST, 0x04100410 },
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{ &rAMC_PSQWQSCHCRD, 0x00101400 },
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{ &rAMC_MCUQOS, 0x00001919 },
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{ &rAMC_MCUQOSLLT, 0x0000011f },
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};
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ASPNANDCONFIG_H
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#define __TARGET_ASPNANDCONFIG_H
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//MLC devices
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#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_DIES_IN_PARALLEL 2
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#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
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//TLC devices
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#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
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// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
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#define ASPNAND_INDIRECTION_MEMORY (2*1024*1024)
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#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
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#endif
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@@ -0,0 +1,37 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* iPad4,x specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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#define GPIO_LCD_PWR_EN GPIO( 2, 7)
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#define GPIO_RINGER_AB GPIO(13, 6)
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/* Board Revision */
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#define GPIO_BOARD_REV0 GPIO(14, 6)
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#define GPIO_BOARD_REV1 GPIO(14, 5)
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#define GPIO_BOARD_REV2 GPIO(14, 4)
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#define GPIO_BOARD_REV3 GPIO(14, 3)
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/* which IICs to initialize */
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#define IICS_MASK (0x5)
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#define TRISTAR_IIC_BUS (0)
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/* D2089 watchdog tickle, 'KEEPACT' */
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#define GPIO_WDOG_TICKLE GPIO(12, 6)
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,90 @@
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD2045_ACTIVE3, 0xAE }, // Current OTP enables LDO{1,2,3,4,5,7}, disable LDO4.
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{ PMU_IIC_BUS, kD2045_ACTIVE6, 0x37 }, // enable BUCK3_SW1, BUCK3_SW2, BUCK3_SW3, BUCK4_SW1, BUCK4_SW2
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{ PMU_IIC_BUS, kD2045_ACTIVE3, 0xBE }, // enable LDO4 along with LDO{1,2,3,5,7}
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{ PMU_IIC_BUS, kD2045_HIBERNATE1, 0x18 },
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{ PMU_IIC_BUS, kD2045_HIBERNATE3, 0x18 },
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{ PMU_IIC_BUS, kD2045_HIBERNATE6, 0x24 },
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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};
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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{ PMU_IIC_BUS, kD2045_GPIO1, 0xBB }, // AUD_ARRAY_HOST_WAKE In, R Edge, No PU, Wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO2, 0xBB }, // WLAN2_HOST_WAKE IN, R Edge, No PU, Wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO3, 0x0B }, // WLAN2_REG_ON Out 1, Buck 3, push-pull
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{ PMU_IIC_BUS, kD2045_GPIO4, 0xB9 }, // TRI_INT In, R Edge, No PU, no wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO5, 0x09 }, // BT1_REG_ON
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{ PMU_IIC_BUS, kD2045_GPIO6, 0xBB }, // BT1_HOST_WAKE In, R Edge, No PU, wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO7, 0xBB }, // WLAN1_HOST_WAKE In, R Edge, No PU, wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO8, 0xBB }, // ENET_PHY_HOST_WAKE In, R Edge, No PU, wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO9, 0x09 }, // BT2_REG_ON Out 0, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD2045_GPIO10, 0xBB }, // BT2_HOST_WAKE In, R Edge, No PU, wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO11, 0x0B }, // WLAN1_REG_ON Out 1, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD2045_GPIO12, 0xBB }, // ENET_PME_1V8 In, R Edge, No PU, wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO13, 0xBB }, // MCU_HOST_WAKE In, R Edge, No PU, wake, PD
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{ PMU_IIC_BUS, kD2045_GPIO14, 0x0B }, // PS_ON (16V) Out 1, VBUCK3, open drain
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{ PMU_IIC_BUS, kD2045_GPIO15, 0x7A }, // PMU_WAKE_ON_VCC
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{ PMU_IIC_BUS, kD2045_GPIO16, 0xBB }, // ACCEL_HOST_WAKE1 In, R Edge, No PU, wake, PD
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{ PMU_IIC_BUS, kD2045_OUT_32K, 0x49 }, // OUT_32K (WLAN_CLK32K) Out 32K, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD2045_BUCK_DWI_CTRL0, 0x03 }, // enable DWI for BUCK0, BUCK1
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{ PMU_IIC_BUS, kD2045_BUTTON1_CONF, 0x84 }, // PMU_BUTTTON1
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{ PMU_IIC_BUS, kD2045_BUTTON2_CONF, 0x84 }, // PMU_BUTTTON2
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{ PMU_IIC_BUS, kD2045_BUTTON3_CONF, 0xD4 }, // PMU_BUTTTON3
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{ PMU_IIC_BUS, kD2045_BUTTON4_CONF, 0x94 }, // PMU_BUTTTON4
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// Special function
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{ PMU_IIC_BUS, kDIALOG_BUTTON_DBL, 0x00 }, //
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{ PMU_IIC_BUS, kD2045_BUTTON_WAKE, 0x00 }, // AUD_ARRAY_HOST_WAKE
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{ PMU_IIC_BUS, kD2045_RESET_IN1_CONF,0x02}, // PMU_RESET_IN1_WDOG
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{ PMU_IIC_BUS, kD2045_RESET_IN2_CONF,0x00}, // PMU_RESET_IN2_TRISTAR
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{ PMU_IIC_BUS, kD2045_RESET_IN3_CONF,0x14}, // SOCHOT1_L
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};
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static const struct core_rails_struct soc_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2045_BUCK2_VSEL }
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};
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static const struct core_rails_struct cpu_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2045_BUCK0_VSEL }
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};
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static const struct core_rails_struct ram_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2045_BUCK5_VSEL }
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};
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#endif /* POWERCONFIG_PMU_SETUP */
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#define TARGET_POWER_NO_BATTERY 1
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#define ALWAYS_BOOT_BATTERY_VOLTAGE (3000)
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#define PRECHARGE_BACKLIGHT_LEVEL 103
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#define TARGET_MAX_USB_INPUT_CURRENT 2400
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#define ACC_PWR_LDO (6)
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#endif
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@@ -0,0 +1,23 @@
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/*
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* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
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||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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||||
*/
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#ifndef __TARGET_UARTCONFIG_H
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#define __TARGET_UARTCONFIG_H
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/* define one debug serial ports */
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#define DEBUG_SERIAL_PORT (0)
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#define HDQGAUGE_SERIAL_PORT (5)
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#if SUPPORT_FPGA
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#define UART_OVERSAMPLE_OVERRIDE (11)
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#endif
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#endif
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@@ -0,0 +1,21 @@
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/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
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||||
#ifndef __TARGET_USBCONFIG_H
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#define __TARGET_USBCONFIG_H
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#ifdef USBPHY_OTGTUNE0
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#undef USBPHY_OTGTUNE0
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#define USBPHY_OTGTUNE0 (0x3644D3F3)
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#endif /* USBPHY_OTGTUNE0 */
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#endif /* __TARGET_USBCONFIG_H */
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