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@@ -0,0 +1,27 @@
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/*
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* Copyright (C) 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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||||
*
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||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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||||
*/
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#ifndef __TARGET_ADBE_SETTINGS_H
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#define __TARGET_ADBE_SETTINGS_H
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static struct adbe_v2_tuneable adbe_tuneables[] = {
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{
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.name = "default",
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.adbe0_vblank_pos_vbi_pulse = 0x0000,
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.adbe0_vblank_clk_gate_wakeup = 0x0000,
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.adbe0_vblank_clk_gate_idle = 0x0001,
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.adbe0_vblank_busy_finish = 2,
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.adbe0_tunable_mode_ctrl = (DBEMODECNTL_PMGR_CLK_GATE_ENABLE | DBEMODECNTL_DYN_CLK_GATE_ENABLE | DBEMODECNTL_BLK_CLK_GATE_ENABLE),
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.adbe0_aap_support = 1,
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.adbe0_aap_format_control_reg1 = (AAP_FORMAT_CONTROL_REG1_AUTOPOS | AAP_FORMAT_CONTROL_REG1_RSVD(8) | AAP_FORMAT_CONTROL_REG1_VS_POL),
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},
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};
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#endif
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@@ -0,0 +1,99 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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||||
*
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||||
* This document is the property of Apple Inc.
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||||
* It is considered confidential and proprietary.
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||||
*
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||||
* This document may not be reproduced or transmitted in any form,
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||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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*/
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/*
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* The amc_param struct is defined in drivers/apple/amc/amc.h, and this
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* file should only by included from amc.c.
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*/
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static const struct amc_param amc_params = {
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.lat = 0x00040200,
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.phyrdwrtim = 0x00010802,
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.tREFi = 0x11,
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.pdn = 0x22000203,
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.derate = 0x04110111,
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.read = 0x00000101,
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.bustat = 0x00222209,
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.bustat2 = 0x00222209,
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.pwrmngten_default = 0x00100100,
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.schen_default = 0x00001110,
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.mcphyupdate = 0x15030000,
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.mcphyupdate1 = 0x00000001,
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.arefparam = 0x0ca2b532,
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.longsr = 0x05022008,
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.mr1 = 0x84,
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.mr2 = 0x06,
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.mr3 = 0x03,
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.addrcfg = 0x00020201,
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.mccchnldec = 0x00050020,
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.mcuchnhash = 0x0ffffd54,
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.mcuchnhash2 = 0x0aaaaaa8,
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.mcschnldec = 0x00020200,
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.qbrparam = 0x00050200,
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.odts = 0x00000320,
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.addrmapmode = 0x00000501,
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.freq = {
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{ // 800MHz
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.cas = 0x00000203,
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.pch = 0x00020303,
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.act = 0x08020303,
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.autoref = 0x01020000,
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.selfref = 0x00002030,
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.modereg = 0x20010732,
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},
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{ // 400MHz
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.cas = 0x00000003,
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.pch = 0x00000003,
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.act = 0x08020303,
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.autoref = 0x01020000,
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.selfref = 0x00002000,
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.modereg = 0x00010000,
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},
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{ // 200MHz
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.cas = 0x00000003,
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.pch = 0x00000003,
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.act = 0x08020303,
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.autoref = 0x01020000,
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.selfref = 0x00002000,
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.modereg = 0x00010000,
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},
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{ // 50MHz
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.cas = 0x00000003,
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.pch = 0x00000003,
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.act = 0x08020303,
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.autoref = 0x01020000,
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.selfref = 0x00002000,
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.modereg = 0x00010000,
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}
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}
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};
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static const struct amc_tunable amc_tunables[] = {
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{ &rAMC_MCSARBCFG, 0x00000001 },
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{ &rAMC_OPIDLETMR, 0x00200000 },
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{ &rAMC_OPTMRADJPARAM, 0x20400064 },
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{ &rAMC_MIFACTSCH, 0x00000001 },
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{ &rAMC_MIFCASSCH_FREQ(0), 0x10000010 },
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{ &rAMC_PSQRQCTL0, 0xff010110 },
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{ &rAMC_PSQRQCTL1, 0x00001700 },
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{ &rAMC_PSQRQTIMER0, 0x00000040 },
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{ &rAMC_PSQRQTIMER1, 0x00000014 },
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{ &rAMC_PSQRQTIMER2, 0x00000040 },
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{ &rAMC_PSQRQBRST, 0x04100410 },
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{ &rAMC_PSQRQSCHCRD, 0x00101400 },
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{ &rAMC_PSQWQCTL0, 0x00010100 },
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{ &rAMC_PSQWQCTL1, 0x00000336 },
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{ &rAMC_PSQWQBRST, 0x04080410 },
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{ &rAMC_PSQWQSCHCRD, 0x00101400 },
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{ &rAMC_MCUQOSLLT, 0x0000011f },
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{ &rAMC_PWRMNGTPARAM, 0x03521000 },
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};
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@@ -0,0 +1,40 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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||||
* in whole or in part, without the express written permission of
|
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* Apple Inc.
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*/
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/*
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* The amc_phy_params struct is defined in drivers/apple/amp_v3/amp_v3.h, and this
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* file should only by included from amp_v3.c.
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*/
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static const struct amp_params amc_phy_params = {
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.freq = {
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{
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.caoutdllscl = 0x00000008,
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.dqsindllscl = 0x00000008,
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.rdcapcfg = 0x01010304,
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},
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{
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.caoutdllscl = 0x00000010,
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.dqsindllscl = 0x00000010,
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.rdcapcfg = 0x21010309,
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},
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{
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.caoutdllscl = 0x00000020,
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.dqsindllscl = 0x00000020,
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.rdcapcfg = 0x41010306,
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},
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{
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.caoutdllscl = 0x0000003f,
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.dqsindllscl = 0x0000003f,
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.rdcapcfg = 0x61010304,
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},
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},
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};
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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||||
*
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||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
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* Apple Inc.
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*/
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#ifndef __TARGET_ASPNANDCONFIG_H
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#define __TARGET_ASPNANDCONFIG_H
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//MLC devices
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#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 4
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#define ASPNAND_ERASE_DIES_IN_PARALLEL 8
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#define ASPNAND_READ_DIES_IN_PARALLEL 8
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#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
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//TLC devices
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#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
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// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
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#define ASPNAND_INDIRECTION_MEMORY (2*1024*1024)
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#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
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#endif
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@@ -0,0 +1,29 @@
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/*
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* Copyright (C) 2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* CapriRef specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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/* Board Revision */
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#define GPIO_BOARD_REV0 GPIO( 20, 1) // 161 : ULPI_NXT
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#define GPIO_BOARD_REV1 GPIO( 19, 7) // 159 : ULPI_DIR
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#define GPIO_BOARD_REV2 GPIO( 21, 0) // 168 : ULPI_DATA[2]
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#define GPIO_BOARD_REV3 GPIO( 20, 3) // 163 : ULPI_DATA[6]
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/* D2207 watchdog tickle, 'KEEPACT' */
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#define GPIO_WDOG_TICKLE GPIO( 10, 7) // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,97 @@
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD2207_HIBERNATE3, 0x90 }, // enable LDO7+LDO4 in hibernate
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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};
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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/* <rdar://problem/14847504> J82 IO Spreadsheet */
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#if TARGET_HAS_BASEBAND
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{ PMU_IIC_BUS, kD2207_GPIO5, 0x09}, // PMU_GPIO_PMU2BBPMU_RST_L Out 0, Push-Pull, VBUCK3
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#else
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{ PMU_IIC_BUS, kD2207_GPIO5, 0xB9}, // PMU_GPIO_PMU2BBPMU_RST_L In, R Edge, PD
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#endif
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{ PMU_IIC_BUS, kD2207_GPIO6, 0xDA}, // UART5_BATT_TRXD In, F Edge, Wake, PD
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{ PMU_IIC_BUS, kD2207_GPIO7, 0xBA}, // PMU_GPIO_BT_HOST_WAKE In, R Edge, Wake, PD
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{ PMU_IIC_BUS, kD2207_GPIO8, 0xBA}, // PMU_GPIO_WLAN_HOST_WAKE In, R Edge, Wake, PD
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#if TARGET_HAS_BASEBAND
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{ PMU_IIC_BUS, kD2207_GPIO9, 0xBA}, // PMU_GPIO_BB2PMU_HOST_WAKE In, R Edge, Wake, PU, VBUCK3
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#else
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{ PMU_IIC_BUS, kD2207_GPIO9, 0xB9}, // PMU_GPIO_BB2PMU_HOST_WAKE In, R Edge, PD
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#endif
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{ PMU_IIC_BUS, kD2207_GPIO10, 0xCA}, // PMU_GPIO_CODEC_HS_INT_L In, F Edge, Wake, PU, VBUCK3
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{ PMU_IIC_BUS, kD2207_GPIO11, 0xFA}, // PMU_GPIO_MB_HALL1_IRQ In, Any Edge, Wake, No PU
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{ PMU_IIC_BUS, kD2207_GPIO12, 0x7B}, // GPIO_TS2SOC2PMU_INT In, Hi level, Wake, PD
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{ PMU_IIC_BUS, kD2207_GPIO14, 0xB8}, // PMU_GPIO_WLAN2PMU_PCIE_WAKE_L In, R Edge, PU
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{ PMU_IIC_BUS, kD2207_GPIO16, 0x7B}, // PMU_GPIO_OSCAR2PMU_HOST_WAKE In, Hi level, Wake, PD
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{ PMU_IIC_BUS, kD2207_BUCK_DWI_CTRL0, 0x07 }, // enable DWI for BUCK0, BUCK1, BUCK2
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};
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static const struct pmu_setup_struct pmu_backlight_enable[] =
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{
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{ PMU_IIC_BUS, kDIALOG_WLED_ISET, 0xD4 }, // 50% value from OS
|
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{ PMU_IIC_BUS, kDIALOG_WLED_ISET2, 0x00 },
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{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, // enable all LED strings
|
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(kDIALOG_WLED_CONTROL_WLED_ENABLE1 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE2 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE3 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE4 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE5 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE6) },
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{ PMU_IIC_BUS, kDIALOG_WLED_OPTIONS, // enable LED Power
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||||
(kDIALOG_WLED_CONTROL2_WLED_RAMP_EN |
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kDIALOG_WLED_CONTROL2_WLED_DITH_EN) }
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};
|
||||
|
||||
static const struct pmu_setup_struct pmu_backlight_disable[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, 0x0 } // disable LED power
|
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};
|
||||
|
||||
static const struct core_rails_struct soc_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2207_BUCK2_VSEL }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct cpu_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2207_BUCK0_VSEL }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct ram_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2207_BUCK5_VSEL }
|
||||
};
|
||||
|
||||
#endif /* POWERCONFIG_PMU_SETUP */
|
||||
|
||||
#define NO_BATTERY_VOLTAGE 2700
|
||||
#define MIN_BOOT_BATTERY_VOLTAGE 3600
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||||
#define TARGET_BOOT_BATTERY_VOLTAGE 3700
|
||||
#define TARGET_BOOT_BATTERY_CAPACITY 50
|
||||
#define PRECHARGE_BACKLIGHT_LEVEL 824
|
||||
#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
|
||||
|
||||
#define ACC_PWR_LDO (6)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define one debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (0)
|
||||
|
||||
#define HDQGAUGE_SERIAL_PORT (5)
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define UART_OVERSAMPLE_OVERRIDE (11)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,90 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/power.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <target.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return platform_get_request_dfu2() && power_has_usb();
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
*cold_button_boot = false;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
uint32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
#if WITH_ENV
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
// boot-device is set in platform's init.c
|
||||
env_set("wifiaddr", "7E:77:77:77:77:77", 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif // WITH_DEVICETREE
|
||||
@@ -0,0 +1,258 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* FIXME: just pulled these direction from ipad5b, may need to update */
|
||||
|
||||
/* THIS STRUCT IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: rev 0.2
|
||||
I/O Spreadsheet tracker: <rdar://problem/14847504> J82 IO Spreadsheet
|
||||
*/
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2OSLO_EN
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2OSLO_DWLD_REQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 15 : UART3_RXD -> UART_BT2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 33 : UART3_CTSN -> UART_BT2SOC_RTS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_GRAPE_MISO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_OUT_1, // 51 : SPI3_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_DISABLED, // 53 : TMR32_PWM1 -> GPIO_SOC2GRAPE_HV_BOOST_EN
|
||||
CFG_DISABLED, // 54 : TMR32_PWM2 -> JTAG_BB_TCK
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_DISABLED, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_DISABLED, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_DISABLED, // 63 : UART7_TXD -> GPIO_TT2SOC_SMI_L
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // 64 : UART7_RXD -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_DISABLED, // 70 : SPI0_SSIN -> JTAG_BB_TMS
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2OSLO_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_OSLO2SOC_TX
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2OSLO_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_OSLO2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // 80 : GPIO[0] -> GPIO_SOC2TT_MUX_SEL
|
||||
CFG_DISABLED, // 81 : GPIO[1] -> GPIO_SOC2TT_PWR_SW_EN
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN | PULL_UP, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_DISABLED, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_SW_EN
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // 88 : GPIO[8] -> GPIO_GANGES2SOC_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_ALS2SOC_DEVBRD_IRQ_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2SPKRAMP_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_DISABLED, // 94 : GPIO[14] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_DISABLED, // 99 : GPIO[19] -> GPIO_SOC2TT_POR_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED | PULL_DOWN, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> NC_BOARD_ID4
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_BTN_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_IN | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_IN | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2OSCAR_TX
|
||||
CFG_FUNC0, // 123 : UART8_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BB_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BB2SOC_TX
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BB2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_DISABLED, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_DISABLED, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_DISABLED, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 156 : SPI1_MISO -> SPI_CODEC_MISO
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_32K
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // 160 : ULPI_STP -> GPIO_SOC2DEVBRD_S3E_WAKE
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_DISABLED, // 167 : ULPI_DATA[3] -> GPIO_SOC2DEVBRD_S3E_RESET2_L
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_DISABLED, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_DISABLED, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED, // 175 : PCIE_CLKREQ2_N -> PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> CLK_SOC2DEVBRD_PCIE_24MHZ
|
||||
CFG_DISABLED, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> NC_PERST3
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_DISABLED, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
return gpio_default_cfg;
|
||||
}
|
||||
@@ -0,0 +1,32 @@
|
||||
# Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2207=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_V2 \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=CHIPID_SOC_VOLTAGE_VMIN \
|
||||
TARGET_VID0_CLK_CFG=0x86100000 \
|
||||
TARGET_DDR_798M=1 \
|
||||
DISPLAY_LANDSCAPE_IPAD_TUNABLES=1 \
|
||||
AMC_NUM_CHANNELS=4 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_GPU=2 \
|
||||
BUCK_RAM=1
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
Reference in new issue
Block a user