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@@ -0,0 +1,35 @@
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/*
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* Copyright (C) 2011 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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||||
* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* E88 specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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#define GPIO_RINGER_AB GPIO( 0, 4)
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/* Board Revision */
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#define GPIO_BOARD_REV0 GPIO( 4, 5) // EHCI_PORT_PWR0
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#define GPIO_BOARD_REV1 GPIO( 4, 6) // EHCI_PORT_PWR1
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#define GPIO_BOARD_REV2 GPIO( 4, 7) // EHCI_PORT_PWR2
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#define GPIO_BOARD_REV3 GPIO( 2, 1) // GPIO17
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/* which IICs to initialize */
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#define IICS_MASK (5)
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#define TRISTAR_IIC_BUS (0)
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/* D1881 watchdog tickle, 'KEEPACT' */
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#define GPIO_WDOG_TICKLE GPIO(2, 3)
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,92 @@
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// Copyright (C) 2008-2010 Apple, Inc. All rights reserved.
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//
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// This document is the property of Apple, Inc.
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// It is considered confidential and proprietary.
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//
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// This document may not be reproduced or transmitted in any form,
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// in whole or in part, without the express written permission of
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// Apple, Inc.
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//
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// NOTE: This is a generated file and should not be hand-edited!
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//
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// =============================================================================
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// Nand Geometry Table
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static NandGeometry _nandGeometryTable[] =
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{
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};
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// =============================================================================
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// Nand Timing Table
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static NandTiming _nandTimingTable[] =
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{
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};
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#if (defined (AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
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// =============================================================================
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// NandChipId Description
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const NandChipIdDescription _nandChipIdDescriptionTable[] =
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{
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};
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// =============================================================================
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// Nand Description Table
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static const NandDescription _nandDescriptionTable[] =
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{
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};
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const UInt32 _nandDescriptionTableSize = sizeof(_nandDescriptionTable) / sizeof(NandDescription);
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#endif // (defined(AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
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// =============================================================================
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// Nand Board Support Table
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static NandBoardSupport _nandBoardSupportTable[] =
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{
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};
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// =============================================================================
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// Nand Board Timing Table
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static NandBoardInfo _nandBoardInfo =
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{
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/* controlDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* dataDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* chipEnableDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* socToNandRiseNanosecs */ 10,
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/* socToNandFallNanosecs */ 10,
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/* nandToSocRiseNanosecs */ 10,
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/* nandToSocFallNanosecs */ 10,
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/* landing map */
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{
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0x00000101
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},
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/* useToggleMode */ TRUE32,
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/* useDiffDQSMode */ FALSE32,
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/* useDiffREMode */ FALSE32,
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/* useVref */ TRUE32,
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/* useSingleHostChannel */ FALSE32,
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/* allowSingleChipEnable */ TRUE32
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};
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static NandFormat _nandFormatPpn =
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{
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/* metaPerLogicalPage */ 16,
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/* validMetaPerLogicalPage */ 16,
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/* logicalPageSize */ 4096
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};
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static NandFormat _nandFormatRaw =
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{
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/* metaPerLogicalPage */ 12,
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/* validMetaPerLogicalPage */ 10,
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/* logicalPageSize */ 0
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};
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@@ -0,0 +1,130 @@
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/*
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* Copyright (C) 2010-2011 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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#include <stdbool.h>
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/* configuration per target */
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#define PMU_IIC_BUS 0
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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/* Matched to D1881B1-OTP-CD-v5 */
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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{ PMU_IIC_BUS, kD1881_LDO1, 0x0D }, // PP3V0_USB 3.15V <rdar://problem/9200307>
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{ PMU_IIC_BUS, kD1881_LDO2, 0x0A }, // PP1V7_VA_VCP 1.70V
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{ PMU_IIC_BUS, kD1881_LDO3, 0x0A }, // PP3V0_IMU 3.00V
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{ PMU_IIC_BUS, kD1881_LDO4, 0x16 }, // PP3V0_OPTICAL 2.90V
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{ PMU_IIC_BUS, kD1881_LDO5, 0x0A }, // PP3V0_NAND 3.00V
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{ PMU_IIC_BUS, kD1881_LDO6, 0x10 }, // PP3V3_ACC 3.30V
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{ PMU_IIC_BUS, kD1881_LDO7, 0x0F }, // PP3V3_VIDEO 3.00V
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{ PMU_IIC_BUS, kD1881_LDO8, 0x14 }, // PP3V0_USBMUX 3.00V
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{ PMU_IIC_BUS, kD1881_LDO9, 0x01 }, // PP1V5_CAM_AVDD 1.30V
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{ PMU_IIC_BUS, kD1881_LDO10, 0x01 }, // PP2V8_CAM_AVDD 2.55V
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{ PMU_IIC_BUS, kD1881_LDO11, 0x02 }, // 1.80V
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{ PMU_IIC_BUS, kD1881_LDO12, 0x10 }, // PP1V1 1.00V
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{ PMU_IIC_BUS, kDIALOG_LDO_CONTROL, 0x00 }, // no bypass
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD1881_ACTIVE1, 0xBD }, // Everything except VBUCK1, LDO2
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{ PMU_IIC_BUS, kD1881_ACTIVE2, 0xBB }, // LDO4, LDO5, LDO7, LDO8, LDO9, LDO11 enabled
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{ PMU_IIC_BUS, kD1881_ACTIVE3, 0x2F }, // LDO12
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{ PMU_IIC_BUS, kD1881_ACTIVE4, 0xE0 }, // CPU1V8 & CPU1V2 on, WDIG off
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{ PMU_IIC_BUS, kD1881_LCM_CONTROL1, 0x02 }, // PP5V1_GRAPE_VDDH 5.10V
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{ PMU_IIC_BUS, kD1881_LCM_CONTROL2, 0x0E }, // PP5V7_LCD_AVDDH 5.70V
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{ PMU_IIC_BUS, kD1881_LCM_CONTROL3, 0x00 }, // BB_VBUS_DET 5.00V
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{ PMU_IIC_BUS, kD1881_LCM_BST_CONTROL, 0x1A }, // PP6V3_LCM_VBOOST 6.30V
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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{ PMU_IIC_BUS, kDIALOG_ADC_CONTROL, kDIALOG_ADC_CONTROL_DEFAULTS },
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};
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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/* Note: the following differences from OTP are intentional:
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- GPIO 5: Enable CLK32k
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- GPIO 8: Enable Codec (Mikey) Wake
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- GPIO 7: Enable WiFi Wake
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- GPIO 10: Enable Wake amd Pull-Up
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*/
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_1, 0xB9 }, // CLK32K_GRAPE In, R Edge, No Wake, No PU
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// Clock is enabled by AppleARMFunction default
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_2, 0x09 }, // BB_WAKE_AP -- NC
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_3, 0x09 }, // BB_PMU_FET_ON -- NC
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_4, 0xBA }, // TRISTAR_INT In, R Edge, Wake, No PU
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_5, 0x49 }, // CLK32K_WIFI Out 0, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_6, 0x09 }, // BATTERY_SWI -- NC
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_7, 0xBB }, // WLAN_HOST_WAKE In, R Edge, Wake, PD, No PU
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_8, 0xEA }, // CODEC_HOST_WAKE_L In, Any Edge, Wake, PU, VBUCK3
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_9, 0x09 }, // BT_REG_ON Out 1, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_10, 0xBA }, // BT_HOST_WAKE In, R Edge, Wake, PU
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_11, 0x09 }, // WIFI_REG_ON Out 0, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB1, 0x12 },
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB2, 0x02 },
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB3, 0x12 },
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB4, 0x00 },
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB5, 0x12 },
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB6, 0x02 },
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{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2, 0x10 }, // enable HIB_32kHz (for WIFI/BT); DWI disabled
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// <rdar://problem/12192156> turn off buck4 negative current limit
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{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x01 }, // set bank1
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{ PMU_IIC_BUS, kD1881_TEST_MODE, 0x01 }, // enter test mode
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{ PMU_IIC_BUS, 0xCB, 0x23 }, // turn off negative current limit
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{ PMU_IIC_BUS, kD1881_TEST_MODE, 0x00 }, // exit test mode
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{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x00 }, // set bank0
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};
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static const struct pmu_setup_struct pmu_backlight_enable[] =
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{
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{ PMU_IIC_BUS, kDIALOG_WLED_ISET, 0xC8 }, // 50% value from OS
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{ PMU_IIC_BUS, kDIALOG_WLED_ISET2, 0x01 },
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{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, // enable LED Power
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(kDIALOG_WLED_CONTROL_WLED_ENABLE2 | kDIALOG_WLED_CONTROL_WLED_ENABLE1 | kDIALOG_WLED_CONTROL_WLED_RAMP_EN) }
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};
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static const struct pmu_setup_struct pmu_backlight_disable[] =
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{
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{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, 0x0 } // disable LED power
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};
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static const struct core_rails_struct soc_rails[] =
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{
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{ PMU_IIC_BUS, 0, kDIALOG_BUCK0 }
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};
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static const struct core_rails_struct cpu_rails[] =
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{
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{ PMU_IIC_BUS, 0, kDIALOG_BUCK2 }
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};
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#endif /* POWERCONFIG_PMU_SETUP */
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#define NO_BATTERY_VOLTAGE 2700
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#define MIN_BOOT_BATTERY_VOLTAGE 3600
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#define TARGET_BOOT_BATTERY_VOLTAGE 3700
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#define TARGET_BOOT_BATTERY_CAPACITY 50
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#define PRECHARGE_BACKLIGHT_LEVEL 824
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#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
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#define ACC_PWR_LDO (6)
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#endif
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@@ -0,0 +1,17 @@
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/*
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* Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
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#ifndef __TARGET_UARTCONFIG_H
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#define __TARGET_UARTCONFIG_H
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/* define two debug serial ports */
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#define DEBUG_SERIAL_PORT (1)
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#endif
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@@ -0,0 +1,29 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
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#ifndef __TARGET_USBCONFIG_H
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#define __TARGET_USBCONFIG_H
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#ifdef USBPHY_UOTGTUNE1
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#undef USBPHY_UOTGTUNE1
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#define USBPHY_UOTGTUNE1 (0x749)
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#endif /* USBPHY_UOTGTUNE1 */
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#ifdef USBPHY_UOTGTUNE2
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#undef USBPHY_UOTGTUNE2
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#define USBPHY_UOTGTUNE2 (0x2FF3)
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#endif /* USBPHY_UOTGTUNE2 */
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#endif /* __TARGET_USBCONFIG_H */
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@@ -0,0 +1,239 @@
|
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/*
|
||||
* Copyright (C) 2011-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/flash_nor.h>
|
||||
#include <drivers/iic.h>
|
||||
#include <drivers/power.h>
|
||||
#include <lib/devicetree.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <lib/syscfg.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/gpiodef.h>
|
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#include <platform/memmap.h>
|
||||
#include <sys.h>
|
||||
#include <sys/boot.h>
|
||||
#include <sys/menu.h>
|
||||
#include <sys/task.h>
|
||||
#include <target.h>
|
||||
#include <target/powerconfig.h>
|
||||
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||||
static u_int32_t e88_get_board_rev(void);
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||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
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||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
switch (target) {
|
||||
case BOOT_DARWIN:
|
||||
case BOOT_DARWIN_RESTORE:
|
||||
case BOOT_DIAGS:
|
||||
break;
|
||||
|
||||
default:
|
||||
; // do nothing
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return platform_get_request_dfu2() && power_has_usb();
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
#if WITH_HW_POWER
|
||||
if (power_get_boot_flag() == kPowerBootFlagColdButton) *cold_button_boot = true;
|
||||
#else
|
||||
*cold_button_boot = false;
|
||||
#endif
|
||||
|
||||
return !*cold_button_boot || platform_get_request_dfu1();
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
u_int32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
env_set("boot-device", "nand0", 0);
|
||||
env_set("boot-partition", "0", 0);
|
||||
env_set("boot-path", "/System/Library/Caches/com.apple.kernelcaches/kernelcache", 0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static bool gpio_board_rev_valid;
|
||||
static u_int32_t gpio_board_rev;
|
||||
|
||||
static u_int32_t e88_get_board_rev(void)
|
||||
{
|
||||
if (!gpio_board_rev_valid) {
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV3, GPIO_PDN);
|
||||
|
||||
spin(100); // Wait 100us
|
||||
|
||||
uint32_t brd_rev3_inverted = (gpio_read(GPIO_BOARD_REV3) ? 0UL : 1UL);
|
||||
gpio_board_rev =
|
||||
(brd_rev3_inverted << 3) |
|
||||
(gpio_read(GPIO_BOARD_REV2) << 2) |
|
||||
(gpio_read(GPIO_BOARD_REV1) << 1) |
|
||||
(gpio_read(GPIO_BOARD_REV0) << 0);
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_DFLT);
|
||||
|
||||
gpio_board_rev_valid = true;
|
||||
}
|
||||
|
||||
return gpio_board_rev;
|
||||
}
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
DTNode *node;
|
||||
uint32_t propSize, propCnt;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
// Update the DWI node with the actual voltages
|
||||
if (FindNode(0, "arm-io/dwi", &node)) {
|
||||
propName = "voltages-buck2";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propCnt = propSize / sizeof(u_int32_t);
|
||||
platform_get_cpu_voltages(propCnt, propData);
|
||||
platform_convert_voltages(2, propCnt, propData);
|
||||
}
|
||||
propName = "voltages-buck0";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propCnt = propSize / sizeof(u_int32_t);
|
||||
platform_get_soc_voltages(propCnt, propData);
|
||||
platform_convert_voltages(0, propCnt, propData);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// Update the gyro calibration data
|
||||
if (FindNode(0, "arm-io/i2c2/gyro", &node)) {
|
||||
propName = "low-temp-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LTGO', propData, propSize);
|
||||
}
|
||||
propName = "high-temp-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('HTGO', propData, propSize);
|
||||
}
|
||||
propName = "gyro-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GSCl', propData, propSize);
|
||||
}
|
||||
propName = "gyro-temp-table";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GYTT', propData, propSize);
|
||||
}
|
||||
propName = "gyro-interrupt-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GICl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update accelerometer calibration data
|
||||
if (FindNode(0, "arm-io/i2c2/accelerometer", &node)) {
|
||||
propName = "low-temp-accel-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LTAO', propData, propSize);
|
||||
}
|
||||
propName = "accel-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ASCl', propData, propSize);
|
||||
}
|
||||
propName = "accel-interrupt-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('AICl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Updte the speaker calibration data
|
||||
if (FindNode(0, "arm-io/i2c0/audio-speaker", &node)) {
|
||||
propName = "speaker-rdc";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('SRdc', propData, propSize);
|
||||
}
|
||||
propName = "speaker-config";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
uint8_t vpbr;
|
||||
if (syscfgCopyDataForTag('VPBR', &vpbr, sizeof(vpbr)) == 1) {
|
||||
((uint8_t *)propData)[12] = (((uint8_t *)propData)[12] & ~0x1f) | (vpbr & 0x1f);
|
||||
}
|
||||
uint8_t vbst;
|
||||
if (syscfgCopyDataForTag('VBST', &vbst, sizeof(vbst)) == 1) {
|
||||
((uint8_t *)propData)[16] = vbst;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,580 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: rev 0v4
|
||||
I/O Spreadsheet tracker: <rdar://problem/19464609> E88: IO Spreadsheet Tracker
|
||||
Conversion command: csvtopinconfig.py --soc h4a --radar '<rdar://problem/19464609> E88: IO Spreadsheet Tracker' --copyright 2014 <filename>
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
|
||||
static const uint32_t pinconfig_ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN | PULL_UP, // 0 : GPIO[0] -> MENU_KEY_L
|
||||
CFG_IN | PULL_UP, // 1 : GPIO[1] -> HOLD_KEY_L
|
||||
CFG_IN | PULL_UP, // 2 : GPIO[2] -> VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 3 : GPIO[3] -> VOL_DWN_L
|
||||
CFG_OUT_1, // 4 : GPIO[4] -> ACC_UHPM_EN
|
||||
CFG_DISABLED | PULL_DOWN, // 5 : GPIO[5] -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 6 : GPIO[6] -> NC
|
||||
CFG_OUT_0 | PULL_DOWN, // 7 : GPIO[7] -> BT_WAKE
|
||||
|
||||
/* Port 1 */
|
||||
CFG_OUT_0, // 8 : GPIO[8] -> WLAN_HSIC_AP_RDY
|
||||
CFG_IN | PULL_DOWN, // 9 : GPIO[9] -> WLAN_HSIC_DEV_RDY
|
||||
CFG_DISABLED, // 10 : GPIO[10] -> NC
|
||||
CFG_DISABLED, // 11 : GPIO[11] -> NC
|
||||
CFG_OUT_0, // 12 : GPIO[12] -> EN_8VBOOST
|
||||
CFG_IN | PULL_UP, // 13 : GPIO[13] -> PMU_IRQ_L
|
||||
CFG_OUT_0, // 14 : GPIO[14] -> WLAN_HSIC_RESUME
|
||||
CFG_OUT_1, // 15 : GPIO[15] -> SNAP_MCU_RESET_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_IN, // 16 : GPIO[16] -> BRD_ID3
|
||||
CFG_IN, // 17 : GPIO[17] -> BRD_REV3
|
||||
CFG_IN | PULL_DOWN, // 18 : GPIO[18] -> BOOT_CFG0
|
||||
CFG_OUT_0, // 19 : GPIO[19] -> KEEPACTIVE
|
||||
CFG_IN, // 20 : GPIO[20] -> TRISTAR_INT
|
||||
CFG_IN | PULL_UP, // 21 : GPIO[21] -> SNAP_INT_L
|
||||
CFG_OUT_0 | PULL_DOWN, // 22 : GPIO[22] -> SNAP_ID0
|
||||
CFG_IN | PULL_DOWN, // 23 : GPIO[23] -> SNAP_ID1
|
||||
|
||||
/* Port 3 */
|
||||
CFG_OUT_0 | PULL_DOWN, // 24 : GPIO[24] -> PS_5VBOOST_L
|
||||
CFG_IN | PULL_DOWN, // 25 : GPIO[25] -> BOOT_CFG1
|
||||
CFG_IN | PULL_DOWN, // 26 : GPIO[26] -> FORCE_DFU
|
||||
CFG_OUT_0, // 27 : GPIO[27] -> DUT_DFU_STATUS
|
||||
CFG_IN, // 28 : GPIO[28] -> BOOT_CFG2
|
||||
CFG_IN, // 29 : GPIO[29] -> BOOT_CFG3
|
||||
CFG_OUT_0 | PULL_DOWN, // 30 : GPIO[30] -> CODEC_RESET_L
|
||||
CFG_IN, // 31 : GPIO[31] -> VBUS_FAULT_L
|
||||
|
||||
/* Port 4 */
|
||||
CFG_OUT_0, // 32 : GPIO[32] -> USB_SW_EN
|
||||
CFG_IN | PULL_DOWN, // 33 : GPIO[33] -> GYRO_INT1
|
||||
CFG_IN, // 34 : GPIO[34] -> ACC_UHPM_POK
|
||||
CFG_OUT_1, // 35 : GPIO[35] -> EN_5VBOOST
|
||||
CFG_IN, // 36 : GPIO[36] -> ACCEL_INT2_L
|
||||
CFG_IN, // 37 : EHCI_PORT_PWR[0] -> BRD_REV[0]
|
||||
CFG_IN, // 38 : EHCI_PORT_PWR[1] -> BRD_REV[1]
|
||||
CFG_IN, // 39 : EHCI_PORT_PWR[2] -> BRD_REV[2]
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0, // 40 : UART1_TXD -> AP_DBG_UART_TXD
|
||||
CFG_FUNC0, // 41 : UART1_RXD -> AP_DBG_UART_RXD
|
||||
CFG_DISABLED | PULL_DOWN, // 42 : UART1_RTSN -> NC
|
||||
CFG_IN, // 43 : UART1_CTSN -> SNAP_DET_L
|
||||
CFG_FUNC0, // 44 : UART2_TXD -> ACC_UART_TXD
|
||||
CFG_FUNC0, // 45 : UART2_RXD -> ACC_UART_RXD
|
||||
CFG_DISABLED | PULL_DOWN, // 46 : UART2_RTSN -> NC
|
||||
CFG_OUT_1, // 47 : UART2_CTSN -> USB_HUB_RST_L
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0, // 48 : UART3_TXD -> BT_UART_RXD
|
||||
CFG_FUNC0, // 49 : UART3_RXD -> BT_UART_TXD
|
||||
CFG_FUNC0, // 50 : UART3_RTSN -> BT_UART_CTS_L
|
||||
CFG_FUNC0, // 51 : UART3_CTSN -> BT_UART_RTS_L
|
||||
CFG_FUNC0, // 52 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0, // 53 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0, // 54 : I2C1_SDA -> SNAP_I2C_SDA
|
||||
CFG_FUNC0, // 55 : I2C1_SCL -> SNAP_I2C_SCL
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0, // 56 : ISP0_SDA -> I2C_CAM_REAR_SDA_1V8
|
||||
CFG_FUNC0, // 57 : ISP0_SCL -> I2C_CAM_REAR_SCL_1V8
|
||||
CFG_DISABLED | PULL_DOWN, // 58 : ISP1_SDA -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 59 : ISP1_SCL -> NC
|
||||
CFG_FUNC0 | PULL_DOWN, // 60 : MIPI_VSYNC -> SNAP_MIPI_VSYNC
|
||||
CFG_FUNC0 | PULL_DOWN, // 61 : TMR32_PWM0 -> GYRO_INT2
|
||||
CFG_FUNC0 | PULL_DOWN, // 62 : TMR32_PWM1 -> ACCEL_INT1_L
|
||||
CFG_FUNC0, // 63 : TMR32_PWM2 -> WLAN_TIMESYNC
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // 64 : SWI_DATA -> NC
|
||||
CFG_FUNC0, // 65 : DWI_DI -> DWI_AP_DI
|
||||
CFG_FUNC0, // 66 : DWI_DO -> DWI_AP_DO
|
||||
CFG_FUNC0, // 67 : DWI_CLK -> DWI_AP_CLK
|
||||
CFG_OUT_0, // 68 : SENSOR0_RST -> CAM_REAR_SHUTDOWN_L
|
||||
CFG_FUNC0, // 69 : SENSOR0_CLK -> CAM_REAR_CLK
|
||||
CFG_DISABLED | PULL_DOWN, // 70 : SENSOR1_RST -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 71 : SENSOR1_CLK -> NC
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED | PULL_DOWN, // 72 : ISP0_PRE_FLASH -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 73 : ISP0_FLASH -> NC
|
||||
CFG_DISABLED, // 74 : ISP1_PRE_FLASH -> NC
|
||||
CFG_DISABLED, // 75 : ISP1_FLASH -> NC
|
||||
CFG_FUNC0, // 76 : I2S0_MCK -> CODEC_MCLK
|
||||
CFG_FUNC0, // 77 : I2S0_LRCK -> CODEC_LRCLK
|
||||
CFG_FUNC0, // 78 : I2S0_BCLK -> CODEC_BCLK
|
||||
CFG_DISABLED | PULL_DOWN, // 79 : I2S0_DOUT -> NC
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0, // 80 : I2S0_DIN -> CODEC_TO_DUT_DIN
|
||||
CFG_DISABLED, // 81 : I2S1_MCK -> NC
|
||||
CFG_FUNC0, // 82 : I2S1_LRCK -> BT_PCM_SYNC
|
||||
CFG_FUNC0, // 83 : I2S1_BCLK -> BT_PCM_CLK
|
||||
CFG_FUNC0, // 84 : I2S1_DOUT -> BT_PCM_IN
|
||||
CFG_FUNC0, // 85 : I2S1_DIN -> BT_PCM_OUT
|
||||
CFG_DISABLED, // 86 : I2S2_MCK -> NC
|
||||
CFG_FUNC0, // 87 : I2S2_LRCK -> SPKR_AMP_MCA_FSYNC
|
||||
|
||||
/* Port 11 */
|
||||
CFG_FUNC0, // 88 : I2S2_BCLK -> SPKR_AMP_MCA_BCLK
|
||||
CFG_FUNC0 | PULL_DOWN, // 89 : I2S2_DOUT -> SPKR_AMP_MCA_SDATA
|
||||
CFG_DISABLED, // 90 : I2S2_DIN -> NC
|
||||
CFG_FUNC0, // 91 : I2S3_MCK -> SNAP_I2S_MCLK_H4A
|
||||
CFG_FUNC0, // 92 : I2S3_LRCK -> SNAP_I2S_LRCK
|
||||
CFG_FUNC0, // 93 : I2S3_BCLK -> SNAP_I2S_BCLK
|
||||
CFG_FUNC0, // 94 : I2S3_DOUT -> DUT_DOUT_TO_SNAP_I2S
|
||||
CFG_FUNC0, // 95 : I2S3_DIN -> SNAP_TO_DUT_I2S_DIN
|
||||
|
||||
/* Port 12 */
|
||||
CFG_IN, // 96 : SPI0_SCLK -> BRD_ID0
|
||||
CFG_IN, // 97 : SPI0_MOSI -> BRD_ID1
|
||||
CFG_IN, // 98 : SPI0_MISO -> BRD_ID2
|
||||
CFG_DISABLED, // 99 : SPI0_SSIN -> NC
|
||||
CFG_FUNC0, // 100 : SPI1_SCLK -> SNAP_SPI_CLK
|
||||
CFG_FUNC0, // 101 : SPI1_MOSI -> SNAP_SPI_MOSI
|
||||
CFG_FUNC0, // 102 : SPI1_MISO -> SNAP_SPI_MISO
|
||||
CFG_FUNC0, // 103 : SPI1_SSIN -> SNAP_MCU_SPI_CS_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // 104 : SPI2_SCLK -> NC
|
||||
CFG_DISABLED, // 105 : SPI2_MOSI -> NC
|
||||
CFG_DISABLED, // 106 : SPI2_MISO -> NC
|
||||
CFG_DISABLED, // 107 : SPI2_SSIN -> NC
|
||||
CFG_DISABLED, // 108 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 109 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 110 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 111 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 113 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 114 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 115 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 116 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 117 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 118 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 119 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // 120 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 121 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 122 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 123 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0, // 128 : UART4_TXD -> WLAN_DBG_UART_RXD
|
||||
CFG_FUNC0, // 129 : UART4_RXD -> WLAN_DBG_UART_TXD
|
||||
CFG_DISABLED | PULL_DOWN, // 130 : UART4_RTSN -> NC
|
||||
CFG_IN, // 131 : UART4_CTSN -> PMU_AMUX_AY_CTRL
|
||||
CFG_DISABLED | PULL_DOWN, // 132 : SDIO0_DATA[3] -> SDIO0_DATA[3]
|
||||
CFG_DISABLED | PULL_DOWN, // 133 : SDIO0_DATA[2] -> SDIO0_DATA[2]
|
||||
CFG_DISABLED | PULL_DOWN, // 134 : SDIO0_DATA[1] -> SDIO0_DATA[1]
|
||||
CFG_DISABLED | PULL_DOWN, // 135 : SDIO0_DATA[0] -> SDIO0_DATA[0]
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED | PULL_DOWN, // 136 : SDIO0_CMD -> SDIO0_CMD
|
||||
CFG_DISABLED | PULL_DOWN, // 137 : SDIO0_CLK -> SDIO0_CLK
|
||||
CFG_DISABLED | PULL_DOWN, // 138 : FMI0_CEN[3] -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 139 : FMI0_CEN[2] -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 140 : FMI0_CEN[1] -> NC
|
||||
CFG_FUNC0 | DRIVE_X2, // 141 : FMI0_CEN[0] -> F0CE0_L
|
||||
CFG_FUNC0 | DRIVE_X2, // 142 : FMI0_CLE -> F0CLE
|
||||
CFG_FUNC0 | DRIVE_X2, // 143 : FMI0_ALE -> F0ALE
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0 | DRIVE_X2, // 144 : FMI0_REN -> F0RE_L
|
||||
CFG_FUNC0 | DRIVE_X2, // 145 : FMI0_WEN -> F0WE_L
|
||||
CFG_FUNC0 | DRIVE_X2, // 146 : FMI0_IO[7] -> F0AD<7>
|
||||
CFG_FUNC0 | DRIVE_X2, // 147 : FMI0_IO[6] -> F0AD<6>
|
||||
CFG_FUNC0 | DRIVE_X2, // 148 : FMI0_IO[5] -> F0AD<5>
|
||||
CFG_FUNC0 | DRIVE_X2, // 149 : FMI0_IO[4] -> F0AD<4>
|
||||
CFG_DISABLED, // 150 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 151 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // 152 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 153 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 154 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 155 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 156 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 157 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 158 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 159 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 20 */
|
||||
CFG_FUNC0 | DRIVE_X2, // 160 : FMI0_DQS -> F0DQS
|
||||
CFG_FUNC0 | DRIVE_X2, // 161 : FMI0_IO[3] -> F0AD<3>
|
||||
CFG_FUNC0 | DRIVE_X2, // 162 : FMI0_IO[2] -> F0AD<2>
|
||||
CFG_FUNC0 | DRIVE_X2, // 163 : FMI0_IO[1] -> F0AD<1>
|
||||
CFG_FUNC0 | DRIVE_X2, // 164 : FMI0_IO[0] -> F0AD<0>
|
||||
CFG_DISABLED | PULL_DOWN, // 165 : FMI1_CEN[3] ->
|
||||
CFG_DISABLED | PULL_DOWN, // 166 : FMI1_CEN[2] ->
|
||||
CFG_DISABLED | PULL_DOWN, // 167 : FMI1_CEN[1] ->
|
||||
|
||||
/* Port 21 */
|
||||
CFG_FUNC0 | DRIVE_X2, // 168 : FMI1_CEN[0] -> F1CE0_L
|
||||
CFG_FUNC0 | DRIVE_X2, // 169 : FMI1_CLE -> F1CLE
|
||||
CFG_FUNC0 | DRIVE_X2, // 170 : FMI1_ALE -> F1ALE
|
||||
CFG_FUNC0 | DRIVE_X2, // 171 : FMI1_REN -> F1RE_L
|
||||
CFG_FUNC0 | DRIVE_X2, // 172 : FMI1_WEN -> F1WE_L
|
||||
CFG_FUNC0 | DRIVE_X2, // 173 : FMI1_IO[7] -> F1AD<7>
|
||||
CFG_FUNC0 | DRIVE_X2, // 174 : FMI1_IO[6] -> F1AD<6>
|
||||
CFG_FUNC0 | DRIVE_X2, // 175 : FMI1_IO[5] -> F1AD<5>
|
||||
|
||||
/* Port 22 */
|
||||
CFG_FUNC0 | DRIVE_X2, // 176 : FMI1_IO[4] -> F1AD<4>
|
||||
CFG_FUNC0 | DRIVE_X2, // 177 : FMI1_DQS -> F1DQS
|
||||
CFG_FUNC0 | DRIVE_X2, // 178 : FMI1_IO[3] -> F1AD<3>
|
||||
CFG_FUNC0 | DRIVE_X2, // 179 : FMI1_IO[2] -> F1AD<2>
|
||||
CFG_FUNC0 | DRIVE_X2, // 180 : FMI1_IO[1] -> F1AD<1>
|
||||
CFG_FUNC0 | DRIVE_X2, // 181 : FMI1_IO[0] -> F1AD<0>
|
||||
CFG_DISABLED, // 182 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 183 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED, // 184 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 185 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 186 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 187 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 188 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 189 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 190 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 191 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 24 */
|
||||
CFG_FUNC0, // 192 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0, // 193 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0, // 194 : UART0_TXD -> DUT_TXD
|
||||
CFG_FUNC0 | PULL_DOWN, // 195 : UART0_RXD -> DUT_RXD
|
||||
CFG_DISABLED | PULL_DOWN, // 196 : UART5_RTXD -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 197 : DP_HPD -> GND
|
||||
CFG_FUNC0 | PULL_DOWN, // 198 : TST_CLKOUT -> TST_CLKOUT
|
||||
CFG_DISABLED | PULL_DOWN, // 199 : TST_STPCLK -> GND
|
||||
|
||||
/* Port 25 */
|
||||
CFG_FUNC0, // 200 : WDOG -> H4A_WDOG
|
||||
CFG_DISABLED, // 201 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 202 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 203 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 204 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 205 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 206 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 207 : UNSPECIFIED -> UNSPECIFIED
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN | PULL_UP, // 0 : GPIO[0] -> MENU_KEY_L
|
||||
CFG_IN | PULL_UP, // 1 : GPIO[1] -> HOLD_KEY_L
|
||||
CFG_IN | PULL_UP, // 2 : GPIO[2] -> VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 3 : GPIO[3] -> VOL_DWN_L
|
||||
CFG_OUT_1, // 4 : GPIO[4] -> ACC_UHPM_EN
|
||||
CFG_DISABLED | PULL_DOWN, // 5 : GPIO[5] -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 6 : GPIO[6] -> NC
|
||||
CFG_OUT_0 | PULL_DOWN, // 7 : GPIO[7] -> BT_WAKE
|
||||
|
||||
/* Port 1 */
|
||||
CFG_OUT_0, // 8 : GPIO[8] -> WLAN_HSIC_AP_RDY
|
||||
CFG_IN | PULL_DOWN, // 9 : GPIO[9] -> WLAN_HSIC_DEV_RDY
|
||||
CFG_DISABLED, // 10 : GPIO[10] -> NC
|
||||
CFG_DISABLED, // 11 : GPIO[11] -> NC
|
||||
CFG_OUT_0, // 12 : GPIO[12] -> EN_8VBOOST
|
||||
CFG_IN | PULL_UP, // 13 : GPIO[13] -> PMU_IRQ_L
|
||||
CFG_OUT_0, // 14 : GPIO[14] -> WLAN_HSIC_RESUME
|
||||
CFG_OUT_1, // 15 : GPIO[15] -> SNAP_MCU_RESET_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_IN, // 16 : GPIO[16] -> BRD_ID3
|
||||
CFG_IN, // 17 : GPIO[17] -> BRD_REV3
|
||||
CFG_IN | PULL_DOWN, // 18 : GPIO[18] -> BOOT_CFG0
|
||||
CFG_OUT_0, // 19 : GPIO[19] -> KEEPACTIVE
|
||||
CFG_IN, // 20 : GPIO[20] -> TRISTAR_INT
|
||||
CFG_IN | PULL_UP, // 21 : GPIO[21] -> SNAP_INT_L
|
||||
CFG_OUT_0 | PULL_DOWN, // 22 : GPIO[22] -> SNAP_ID0
|
||||
CFG_IN | PULL_DOWN, // 23 : GPIO[23] -> SNAP_ID1
|
||||
|
||||
/* Port 3 */
|
||||
CFG_OUT_0 | PULL_DOWN, // 24 : GPIO[24] -> PS_5VBOOST_L
|
||||
CFG_IN | PULL_DOWN, // 25 : GPIO[25] -> BOOT_CFG1
|
||||
CFG_IN | PULL_DOWN, // 26 : GPIO[26] -> FORCE_DFU
|
||||
CFG_OUT_0, // 27 : GPIO[27] -> DUT_DFU_STATUS
|
||||
CFG_IN, // 28 : GPIO[28] -> BOOT_CFG2
|
||||
CFG_IN, // 29 : GPIO[29] -> BOOT_CFG3
|
||||
CFG_OUT_0 | PULL_DOWN, // 30 : GPIO[30] -> CODEC_RESET_L
|
||||
CFG_IN, // 31 : GPIO[31] -> VBUS_FAULT_L
|
||||
|
||||
/* Port 4 */
|
||||
CFG_OUT_0, // 32 : GPIO[32] -> USB_SW_EN
|
||||
CFG_IN | PULL_DOWN, // 33 : GPIO[33] -> GYRO_INT1
|
||||
CFG_IN, // 34 : GPIO[34] -> ACC_UHPM_POK
|
||||
CFG_OUT_1, // 35 : GPIO[35] -> EN_5VBOOST
|
||||
CFG_IN, // 36 : GPIO[36] -> ACCEL_INT2_L
|
||||
CFG_IN, // 37 : EHCI_PORT_PWR[0] -> BRD_REV[0]
|
||||
CFG_IN, // 38 : EHCI_PORT_PWR[1] -> BRD_REV[1]
|
||||
CFG_IN, // 39 : EHCI_PORT_PWR[2] -> BRD_REV[2]
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0, // 40 : UART1_TXD -> AP_DBG_UART_TXD
|
||||
CFG_FUNC0, // 41 : UART1_RXD -> AP_DBG_UART_RXD
|
||||
CFG_DISABLED | PULL_DOWN, // 42 : UART1_RTSN -> NC
|
||||
CFG_IN, // 43 : UART1_CTSN -> SNAP_DET_L
|
||||
CFG_FUNC0, // 44 : UART2_TXD -> ACC_UART_TXD
|
||||
CFG_FUNC0, // 45 : UART2_RXD -> ACC_UART_RXD
|
||||
CFG_DISABLED | PULL_DOWN, // 46 : UART2_RTSN -> NC
|
||||
CFG_OUT_1, // 47 : UART2_CTSN -> USB_HUB_RST_L
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0, // 48 : UART3_TXD -> BT_UART_RXD
|
||||
CFG_FUNC0, // 49 : UART3_RXD -> BT_UART_TXD
|
||||
CFG_FUNC0, // 50 : UART3_RTSN -> BT_UART_CTS_L
|
||||
CFG_FUNC0, // 51 : UART3_CTSN -> BT_UART_RTS_L
|
||||
CFG_FUNC0, // 52 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0, // 53 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0, // 54 : I2C1_SDA -> SNAP_I2C_SDA
|
||||
CFG_FUNC0, // 55 : I2C1_SCL -> SNAP_I2C_SCL
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0, // 56 : ISP0_SDA -> I2C_CAM_REAR_SDA_1V8
|
||||
CFG_FUNC0, // 57 : ISP0_SCL -> I2C_CAM_REAR_SCL_1V8
|
||||
CFG_DISABLED | PULL_DOWN, // 58 : ISP1_SDA -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 59 : ISP1_SCL -> NC
|
||||
CFG_FUNC0 | PULL_DOWN, // 60 : MIPI_VSYNC -> SNAP_MIPI_VSYNC
|
||||
CFG_FUNC0 | PULL_DOWN, // 61 : TMR32_PWM0 -> GYRO_INT2
|
||||
CFG_FUNC0 | PULL_DOWN, // 62 : TMR32_PWM1 -> ACCEL_INT1_L
|
||||
CFG_FUNC0, // 63 : TMR32_PWM2 -> WLAN_TIMESYNC
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // 64 : SWI_DATA -> NC
|
||||
CFG_FUNC0, // 65 : DWI_DI -> DWI_AP_DI
|
||||
CFG_FUNC0, // 66 : DWI_DO -> DWI_AP_DO
|
||||
CFG_FUNC0, // 67 : DWI_CLK -> DWI_AP_CLK
|
||||
CFG_OUT_0, // 68 : SENSOR0_RST -> CAM_REAR_SHUTDOWN_L
|
||||
CFG_FUNC0, // 69 : SENSOR0_CLK -> CAM_REAR_CLK
|
||||
CFG_DISABLED | PULL_DOWN, // 70 : SENSOR1_RST -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 71 : SENSOR1_CLK -> NC
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED | PULL_DOWN, // 72 : ISP0_PRE_FLASH -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 73 : ISP0_FLASH -> NC
|
||||
CFG_DISABLED, // 74 : ISP1_PRE_FLASH -> NC
|
||||
CFG_DISABLED, // 75 : ISP1_FLASH -> NC
|
||||
CFG_FUNC0, // 76 : I2S0_MCK -> CODEC_MCLK
|
||||
CFG_FUNC0, // 77 : I2S0_LRCK -> CODEC_LRCLK
|
||||
CFG_FUNC0, // 78 : I2S0_BCLK -> CODEC_BCLK
|
||||
CFG_DISABLED | PULL_DOWN, // 79 : I2S0_DOUT -> NC
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0, // 80 : I2S0_DIN -> CODEC_TO_DUT_DIN
|
||||
CFG_DISABLED, // 81 : I2S1_MCK -> NC
|
||||
CFG_FUNC0, // 82 : I2S1_LRCK -> BT_PCM_SYNC
|
||||
CFG_FUNC0, // 83 : I2S1_BCLK -> BT_PCM_CLK
|
||||
CFG_FUNC0, // 84 : I2S1_DOUT -> BT_PCM_IN
|
||||
CFG_FUNC0, // 85 : I2S1_DIN -> BT_PCM_OUT
|
||||
CFG_DISABLED, // 86 : I2S2_MCK -> NC
|
||||
CFG_FUNC0, // 87 : I2S2_LRCK -> SPKR_AMP_MCA_FSYNC
|
||||
|
||||
/* Port 11 */
|
||||
CFG_FUNC0, // 88 : I2S2_BCLK -> SPKR_AMP_MCA_BCLK
|
||||
CFG_FUNC0 | PULL_DOWN, // 89 : I2S2_DOUT -> SPKR_AMP_MCA_SDATA
|
||||
CFG_DISABLED, // 90 : I2S2_DIN -> NC
|
||||
CFG_FUNC0, // 91 : I2S3_MCK -> SNAP_I2S_MCLK_H4A
|
||||
CFG_FUNC0, // 92 : I2S3_LRCK -> SNAP_I2S_LRCK
|
||||
CFG_FUNC0, // 93 : I2S3_BCLK -> SNAP_I2S_BCLK
|
||||
CFG_FUNC0, // 94 : I2S3_DOUT -> DUT_DOUT_TO_SNAP_I2S
|
||||
CFG_FUNC0, // 95 : I2S3_DIN -> SNAP_TO_DUT_I2S_DIN
|
||||
|
||||
/* Port 12 */
|
||||
CFG_IN, // 96 : SPI0_SCLK -> BRD_ID0
|
||||
CFG_IN, // 97 : SPI0_MOSI -> BRD_ID1
|
||||
CFG_IN, // 98 : SPI0_MISO -> BRD_ID2
|
||||
CFG_DISABLED, // 99 : SPI0_SSIN -> NC
|
||||
CFG_FUNC0, // 100 : SPI1_SCLK -> SNAP_SPI_CLK
|
||||
CFG_FUNC0, // 101 : SPI1_MOSI -> SNAP_SPI_MOSI
|
||||
CFG_FUNC0, // 102 : SPI1_MISO -> SNAP_SPI_MISO
|
||||
CFG_FUNC0, // 103 : SPI1_SSIN -> SNAP_MCU_SPI_CS_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // 104 : SPI2_SCLK -> NC
|
||||
CFG_DISABLED, // 105 : SPI2_MOSI -> NC
|
||||
CFG_DISABLED, // 106 : SPI2_MISO -> NC
|
||||
CFG_DISABLED, // 107 : SPI2_SSIN -> NC
|
||||
CFG_DISABLED, // 108 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 109 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 110 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 111 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 113 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 114 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 115 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 116 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 117 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 118 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 119 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // 120 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 121 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 122 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 123 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0, // 128 : UART4_TXD -> WLAN_DBG_UART_RXD
|
||||
CFG_FUNC0, // 129 : UART4_RXD -> WLAN_DBG_UART_TXD
|
||||
CFG_DISABLED | PULL_DOWN, // 130 : UART4_RTSN -> NC
|
||||
CFG_IN, // 131 : UART4_CTSN -> PMU_AMUX_AY_CTRL
|
||||
CFG_DISABLED | PULL_DOWN, // 132 : SDIO0_DATA[3] -> SDIO0_DATA[3]
|
||||
CFG_DISABLED | PULL_DOWN, // 133 : SDIO0_DATA[2] -> SDIO0_DATA[2]
|
||||
CFG_DISABLED | PULL_DOWN, // 134 : SDIO0_DATA[1] -> SDIO0_DATA[1]
|
||||
CFG_DISABLED | PULL_DOWN, // 135 : SDIO0_DATA[0] -> SDIO0_DATA[0]
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED | PULL_DOWN, // 136 : SDIO0_CMD -> SDIO0_CMD
|
||||
CFG_DISABLED | PULL_DOWN, // 137 : SDIO0_CLK -> SDIO0_CLK
|
||||
CFG_DISABLED | PULL_DOWN, // 138 : FMI0_CEN[3] -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 139 : FMI0_CEN[2] -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 140 : FMI0_CEN[1] -> NC
|
||||
CFG_FUNC0, // 141 : FMI0_CEN[0] -> F0CE0_L
|
||||
CFG_FUNC0, // 142 : FMI0_CLE -> F0CLE
|
||||
CFG_FUNC0, // 143 : FMI0_ALE -> F0ALE
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : FMI0_REN -> F0RE_L
|
||||
CFG_FUNC0, // 145 : FMI0_WEN -> F0WE_L
|
||||
CFG_FUNC0, // 146 : FMI0_IO[7] -> F0AD<7>
|
||||
CFG_FUNC0, // 147 : FMI0_IO[6] -> F0AD<6>
|
||||
CFG_FUNC0, // 148 : FMI0_IO[5] -> F0AD<5>
|
||||
CFG_FUNC0, // 149 : FMI0_IO[4] -> F0AD<4>
|
||||
CFG_DISABLED, // 150 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 151 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // 152 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 153 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 154 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 155 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 156 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 157 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 158 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 159 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 20 */
|
||||
CFG_FUNC0, // 160 : FMI0_DQS -> F0DQS
|
||||
CFG_FUNC0, // 161 : FMI0_IO[3] -> F0AD<3>
|
||||
CFG_FUNC0, // 162 : FMI0_IO[2] -> F0AD<2>
|
||||
CFG_FUNC0, // 163 : FMI0_IO[1] -> F0AD<1>
|
||||
CFG_FUNC0, // 164 : FMI0_IO[0] -> F0AD<0>
|
||||
CFG_DISABLED | PULL_DOWN, // 165 : FMI1_CEN[3] ->
|
||||
CFG_DISABLED | PULL_DOWN, // 166 : FMI1_CEN[2] ->
|
||||
CFG_DISABLED | PULL_DOWN, // 167 : FMI1_CEN[1] ->
|
||||
|
||||
/* Port 21 */
|
||||
CFG_FUNC0, // 168 : FMI1_CEN[0] -> F1CE0_L
|
||||
CFG_FUNC0, // 169 : FMI1_CLE -> F1CLE
|
||||
CFG_FUNC0, // 170 : FMI1_ALE -> F1ALE
|
||||
CFG_FUNC0, // 171 : FMI1_REN -> F1RE_L
|
||||
CFG_FUNC0, // 172 : FMI1_WEN -> F1WE_L
|
||||
CFG_FUNC0, // 173 : FMI1_IO[7] -> F1AD<7>
|
||||
CFG_FUNC0, // 174 : FMI1_IO[6] -> F1AD<6>
|
||||
CFG_FUNC0, // 175 : FMI1_IO[5] -> F1AD<5>
|
||||
|
||||
/* Port 22 */
|
||||
CFG_FUNC0, // 176 : FMI1_IO[4] -> F1AD<4>
|
||||
CFG_FUNC0, // 177 : FMI1_DQS -> F1DQS
|
||||
CFG_FUNC0, // 178 : FMI1_IO[3] -> F1AD<3>
|
||||
CFG_FUNC0, // 179 : FMI1_IO[2] -> F1AD<2>
|
||||
CFG_FUNC0, // 180 : FMI1_IO[1] -> F1AD<1>
|
||||
CFG_FUNC0, // 181 : FMI1_IO[0] -> F1AD<0>
|
||||
CFG_DISABLED, // 182 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 183 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED, // 184 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 185 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 186 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 187 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 188 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 189 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 190 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 191 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 24 */
|
||||
CFG_FUNC0, // 192 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0, // 193 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0, // 194 : UART0_TXD -> DUT_TXD
|
||||
CFG_FUNC0 | PULL_DOWN, // 195 : UART0_RXD -> DUT_RXD
|
||||
CFG_DISABLED | PULL_DOWN, // 196 : UART5_RTXD -> NC
|
||||
CFG_DISABLED | PULL_DOWN, // 197 : DP_HPD -> GND
|
||||
CFG_FUNC0 | PULL_DOWN, // 198 : TST_CLKOUT -> TST_CLKOUT
|
||||
CFG_DISABLED | PULL_DOWN, // 199 : TST_STPCLK -> GND
|
||||
|
||||
/* Port 25 */
|
||||
CFG_FUNC0, // 200 : WDOG -> H4A_WDOG
|
||||
CFG_DISABLED, // 201 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 202 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 203 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 204 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 205 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 206 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 207 : UNSPECIFIED -> UNSPECIFIED
|
||||
};
|
||||
|
||||
struct pinconfig_map {
|
||||
uint32_t board_id;
|
||||
uint32_t board_id_mask;
|
||||
const uint32_t *pinconfigs[GPIOC_COUNT];
|
||||
};
|
||||
|
||||
static const struct pinconfig_map cfg_map[] = {
|
||||
{ 0, 1, { pinconfig_ap_0 } },
|
||||
{ 1, 1, { pinconfig_dev_0 } },
|
||||
};
|
||||
|
||||
const uint32_t * target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
static const struct pinconfig_map *selected_map = NULL;
|
||||
|
||||
if (selected_map == NULL) {
|
||||
uint32_t board_id = platform_get_board_id();
|
||||
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
|
||||
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
|
||||
selected_map = &cfg_map[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (selected_map == NULL)
|
||||
panic("no default pinconfig for board id %u", board_id);
|
||||
}
|
||||
|
||||
ASSERT(gpioc < GPIOC_COUNT);
|
||||
return selected_map->pinconfigs[gpioc];
|
||||
}
|
||||
@@ -0,0 +1,43 @@
|
||||
# Copyright (C) 2010-2012 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D1881=1 \
|
||||
TARGET_HIGH_SOC_VOLTAGE=CHIPID_SOC_VOLTAGE_MED \
|
||||
TARGET_HIGH_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_MED \
|
||||
TARGET_CPU_SOURCE=2 \
|
||||
TARGET_MIPI_DSI_SOURCE=1 \
|
||||
TARGET_MANAGED2H_SOURCE=0 \
|
||||
TARGET_MANAGED2L_SOURCE=0 \
|
||||
TARGET_MANAGED2H_DIV=1 \
|
||||
TARGET_MANAGED2L_DIV=2 \
|
||||
TARGET_PCLK1_SOURCE=1 \
|
||||
TARGET_PCLK1_DIV=4 \
|
||||
TARGET_GFX_SOURCE=2 \
|
||||
TARGET_GFX_SLC_SOURCE=3 \
|
||||
TARGET_IOP_SOURCE=3 \
|
||||
TARGET_LPERFS_SOURCE=3 \
|
||||
TARGET_HPERFNRT_SOURCE=0 \
|
||||
TARGET_USE_HSIC=1 \
|
||||
TARGET_DSIM_CONFIG=0x00400000 \
|
||||
TARGET_DSIM_DPHYCTL=0x30 \
|
||||
TARGET_DSIM_SUPPRESS=0x1 \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
AMC_CHANNEL_WIDTH=4 \
|
||||
WIFI_DTPATH=\"arm-io/usb-complex/usb-ehci/wlan\" \
|
||||
WITH_TARGET_USB_CONFIG=1
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
Reference in new issue
Block a user