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@@ -0,0 +1,27 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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||||
*
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||||
* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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*/
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#ifndef __TARGET_ADBE_SETTINGS_H
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#define __TARGET_ADBE_SETTINGS_H
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static struct adbe_v2_tuneable adbe_tuneables[] = {
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{
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.name = "default",
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.adbe0_vblank_pos_vbi_pulse = 0x0000,
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.adbe0_vblank_clk_gate_wakeup = 0x0000,
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.adbe0_vblank_clk_gate_idle = 0x0001,
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.adbe0_vblank_busy_finish = 0,
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.adbe0_tunable_mode_ctrl = 0,
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.adbe0_aap_support = 1,
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.adbe0_aap_format_control_reg1 = (AAP_FORMAT_CONTROL_REG1_AUTOPOS | AAP_FORMAT_CONTROL_REG1_RSVD(8) | AAP_FORMAT_CONTROL_REG1_VS_POL),
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},
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};
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#endif
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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||||
*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ASPNANDCONFIG_H
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#define __TARGET_ASPNANDCONFIG_H
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//MLC devices
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#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
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#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_DIES_IN_PARALLEL 4
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#define ASPNAND_READ_DIES_IN_PARALLEL 4
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#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
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//TLC devices
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#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
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// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
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#define ASPNAND_INDIRECTION_MEMORY (2*1024*1024)
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#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
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#endif
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@@ -0,0 +1,46 @@
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/*
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* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* iphone7,x specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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/* Board Revision */
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#define GPIO_BOARD_REV0 GPIO( 9, 2) // 74 : GPIO[34]
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#define GPIO_BOARD_REV1 GPIO( 9, 1) // 73 : GPIO[35]
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#define GPIO_BOARD_REV2 GPIO( 9, 0) // 72 : GPIO[36]
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#define GPIO_BOARD_REV3 GPIO( 8, 7) // 71 : GPIO[37]
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/* Miscellaneous Pins */
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/* Display reset */
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#define GPIO_LCD_RST GPIO( 0, 1) // 1 : ULPI_STP -> AP_TO_LCM_RESET_L
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#define GPIO_LCD_RST_POLARITY (0) // active low
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/* Ringer Switch */
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#define GPIO_RINGER_AB GPIO(16, 3) // 131 : GPIO[40] -> BUTTON_TO_AP_RINGER_A
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/* D2186 watchdog tickle, 'KEEPACT' */
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#define GPIO_WDOG_TICKLE GPIO(13, 3) // 107 : GPIO[19] -> AP_TO_PMU_KEEPACT
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/* which IICs to initialize */
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#define IICS_MASK (7)
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#define TRISTAR_IIC_BUS (0)
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#define DISPLAY_PMU_IIC_BUS (0)
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,115 @@
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD2186_ACTIVE3, 0xAE }, // Current OTP enables LDO{1,2,3,4,5,7}, disable LDO4.
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{ PMU_IIC_BUS, kD2186_ACTIVE6, 0x37 }, // enable BUCK3_SW1, BUCK3_SW2, BUCK3_SW3, BUCK4_SW1, BUCK4_SW2
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{ PMU_IIC_BUS, kD2186_ACTIVE3, 0xBE }, // enable LDO4 along with LDO{1,2,3,5,7}
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{ PMU_IIC_BUS, kD2186_BUCK1_VSEL, 0x80 }, // rdar://14689066 TODO: remove when not necessary
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{ PMU_IIC_BUS, kD2186_OUT_32K, 0x49 }, // enable OUT32 clock
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{ PMU_IIC_BUS, kD2186_BUCK6_VSEL, 0x26 }, // <rdar://problem/15038492> N56/T133 Adi PMU: Change default voltage on BUCK6 to 2.0375 V
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{ PMU_IIC_BUS, kD2186_LDO9_VSEL, 0x44 }, // <rdar://problem/15047684> N56/T133/N61 Front Camera AVDD Voltage setting from PMU
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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};
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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{ PMU_IIC_BUS, kD2186_GPIO1_CONF1, 0x88 }, // CHG_TO_PMU_INT_L In, L Low, No Wake, PU
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{ PMU_IIC_BUS, kD2186_GPIO1_CONF2, 0x72 }, // CHG_TO_PMU_INT_L POR
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{ PMU_IIC_BUS, kD2186_GPIO2_CONF1, 0x8a }, // BB_TO_PMU_HOST_WAKE_L In, L Low, Wake, PU
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{ PMU_IIC_BUS, kD2186_GPIO2_CONF2, 0x72 }, // BB_TO_PMU_HOST_WAKE_L POR
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{ PMU_IIC_BUS, kD2186_GPIO3_CONF1, 0x01 }, // PMU_TO_BB_RST_R_L Out 0, Low , Push-Pull
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{ PMU_IIC_BUS, kD2186_GPIO3_CONF2, 0x12 }, // PMU_TO_BB_RST_R_L VBUCK3
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{ PMU_IIC_BUS, kD2186_GPIO4_CONF1, 0x82 }, // TRISTAR_TO_AP_INT In, L High, Wake, PU
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{ PMU_IIC_BUS, kD2186_GPIO4_CONF2, 0x72 }, // TRISTAR_TO_AP_INT POR
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{ PMU_IIC_BUS, kD2186_GPIO5_CONF1, 0x83 }, // STOCKHOLM_TO_PMU_HOST_WAKE_L In, L High, Wake, PD
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{ PMU_IIC_BUS, kD2186_GPIO5_CONF2, 0x72 }, // STOCKHOLM_TO_PMU_HOST_WAKE_L POR
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{ PMU_IIC_BUS, kD2186_GPIO6_CONF1, 0x01 }, // PMU_TO_OSCAR_RESET_CLK_32K_L Out 0, Push-Pull
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{ PMU_IIC_BUS, kD2186_GPIO6_CONF2, 0x12 }, // PMU_TO_OSCAR_RESET_CLK_32K_L VBUCK3
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{ PMU_IIC_BUS, kD2186_GPIO7_CONF1, 0x83 }, // WLAN_TO_PMU_HOST_WAKE In, L High, Wake, PD
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{ PMU_IIC_BUS, kD2186_GPIO7_CONF2, 0x72 }, // WLAN_TO_PMU_HOST_WAKE POR
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{ PMU_IIC_BUS, kD2186_GPIO8_CONF1, 0xA2 }, // CODEC_TO_PMU_MIKEY_INT_L In, Any Edge, Wake, PU
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{ PMU_IIC_BUS, kD2186_GPIO8_CONF2, 0x12 }, // CODEC_TO_PMU_MIKEY_INT_L VBUCK3
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{ PMU_IIC_BUS, kD2186_GPIO9_CONF1, 0x01 }, // PMU_TO_BT_REG_ON_R Out 0, Push-Pull
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{ PMU_IIC_BUS, kD2186_GPIO9_CONF2, 0x12 }, // PMU_TO_BT_REG_ON_R VBUCK3
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{ PMU_IIC_BUS, kD2186_GPIO10_CONF1, 0x92 }, // BT_TO_PMU_HOST_WAKE In, R Edge, Wake, Push-Pull
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{ PMU_IIC_BUS, kD2186_GPIO10_CONF2, 0x72 }, // BT_TO_PMU_HOST_WAKE Disabled
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// { PMU_IIC_BUS, kD2186_GPIO11_CONF1, 0x01 }, // PMU_TO_WLAN_REG_ON_R Out 0, Push-Pull
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{ PMU_IIC_BUS, kD2186_GPIO11_CONF1, 0x03 }, // PMU_TO_WLAN_REG_ON_R Out 1, Push-Pull (FIXME! rdar://14957372)
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{ PMU_IIC_BUS, kD2186_GPIO11_CONF2, 0x12 }, // PMU_TO_WLAN_REG_ON_R VBUCK3
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{ PMU_IIC_BUS, kD2186_GPIO12_CONF1, 0x08}, // AP_TO_I2C0_SCL Out, nReset, PU
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{ PMU_IIC_BUS, kD2186_GPIO12_CONF2, 0x72 }, // AP_TO_I2C0_SCL POR
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{ PMU_IIC_BUS, kD2186_GPIO13_CONF1, 0x83 }, // OSCAR_TO_PMU_HOST_WAKE In, In, L High, Wake, PD
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{ PMU_IIC_BUS, kD2186_GPIO13_CONF2, 0x72 }, // OSCAR_TO_PMU_HOST_WAKE POR
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{ PMU_IIC_BUS, kD2186_GPIO14_CONF1, 0x91 }, // NC
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{ PMU_IIC_BUS, kD2186_GPIO14_CONF2, 0x72 }, // POR
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{ PMU_IIC_BUS, kD2186_GPIO15_CONF1, 0x01 }, // PMU_TO_BB_VBUS_DET Out 0, Low, Push-Pull
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{ PMU_IIC_BUS, kD2186_GPIO15_CONF2, 0x02 }, // PMU_TO_BB_VBUS_DET VCC_MAIN
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{ PMU_IIC_BUS, kD2186_GPIO16_CONF1, 0x91 }, // NC
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{ PMU_IIC_BUS, kD2186_GPIO16_CONF2, 0x72 }, // POR
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{ PMU_IIC_BUS, kD2186_GPIO17_CONF1, 0x9A }, // WLAN_TO_PMU_PCIE_WAKE_L In, F Edge, Wake, PU
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{ PMU_IIC_BUS, kD2186_GPIO17_CONF2, 0x12 }, // WLAN_TO_PMU_PCIE_WAKE_L VBUCK3
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{ PMU_IIC_BUS, kD2186_GPIO18_CONF1, 0x01 }, // PMU_TO_ACC_SW_ON Out 0, Low, Push-Pull
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{ PMU_IIC_BUS, kD2186_GPIO18_CONF2, 0x12 }, // PMU_TO_ACC_SW_ON VBUCK3
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{ PMU_IIC_BUS, kD2186_GPIO19_CONF1, 0x93 }, // NC_HALL1_TO_PMU_WAKE In, R Edge, Wake, PD
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{ PMU_IIC_BUS, kD2186_GPIO19_CONF2, 0x12 }, // NC_HALL1_TO_PMU_WAKE VBUCK3
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{ PMU_IIC_BUS, kD2186_GPIO20_CONF1, 0x93 }, // NC_HALL2_TO_PMU_WAKE In, R Edge, Wake, PD
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{ PMU_IIC_BUS, kD2186_GPIO20_CONF2, 0x12 }, // NC_HALL2_TO_PMU_WAKE VBUCK3
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{ PMU_IIC_BUS, kD2186_GPIO21_CONF1, 0x91 }, // NC
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{ PMU_IIC_BUS, kD2186_GPIO21_CONF2, 0x72 }, // POR
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// TODO: configure debounce for WAS kD2045_GPIO_DEB2,kD2045_GPIO_DEB5,kD2045_GPIO_DEB6?
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{ PMU_IIC_BUS, kD2186_BUCK_DWI_CTRL0, 0x07 }, // enable DWI for BUCK0, BUCK1, BUCK2
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{ PMU_IIC_BUS, kD2186_SYS_CTRL2, 0x11 }, // enable HIB_32kHz (for WIFI/BT) and DWI
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// TODO: verify
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{ PMU_IIC_BUS, kD2186_ACT_TO_HIB_DLY, 0x03 }, // set ACT_TO_HIB_DLY to 3 (6ms)
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};
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static const struct core_rails_struct soc_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2186_BUCK2_VSEL }
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};
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static const struct core_rails_struct cpu_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2186_BUCK0_VSEL }
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};
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static const struct core_rails_struct ram_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2186_BUCK5_VSEL }
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};
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#endif /* POWERCONFIG_PMU_SETUP */
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#define NO_BATTERY_VOLTAGE 2700
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#define MIN_BOOT_BATTERY_VOLTAGE 3600
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#define TARGET_BOOT_BATTERY_VOLTAGE 3700
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#define TARGET_BOOT_BATTERY_CAPACITY 50
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#define PRECHARGE_BACKLIGHT_LEVEL 824
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#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
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#define ACC_PWR_LDO (6)
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#endif
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@@ -0,0 +1,23 @@
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/*
|
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* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
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#ifndef __TARGET_UARTCONFIG_H
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#define __TARGET_UARTCONFIG_H
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/* define one debug serial ports */
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#define DEBUG_SERIAL_PORT (0)
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#define HDQGAUGE_SERIAL_PORT (5)
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#if SUPPORT_FPGA
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#define UART_OVERSAMPLE_OVERRIDE (11)
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#endif
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#endif
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@@ -0,0 +1,92 @@
|
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/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
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#include <debug.h>
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#include <drivers/power.h>
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#include <lib/env.h>
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#include <lib/mib.h>
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#include <platform.h>
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#include <platform/gpiodef.h>
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#include <platform/soc/chipid.h>
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#include <target.h>
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#include <platform/soc/hwclocks.h>
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MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
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MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
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void target_early_init(void)
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{
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}
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void target_late_init(void)
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{
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clock_gate(CLK_UART7, 0);
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}
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void target_init(void)
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{
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#if WITH_HW_FLASH_NOR
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flash_nor_init(SPI_NOR0);
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#endif
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}
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void target_quiesce_hardware(void)
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{
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}
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void target_poweroff(void)
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{
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}
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||||
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||||
int target_bootprep(enum boot_target target)
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{
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return 0;
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}
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bool target_should_recover(void)
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||||
{
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||||
return platform_get_request_dfu2() && power_has_usb();
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||||
}
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||||
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||||
bool target_should_poweron(bool *cold_button_boot)
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{
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||||
if (power_get_boot_flag() == kPowerBootFlagColdButton)
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*cold_button_boot = true;
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||||
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return true;
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||||
}
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||||
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||||
bool target_should_poweroff(bool at_boot)
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{
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return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
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}
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||||
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||||
#if APPLICATION_IBOOT
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||||
void target_watchdog_tickle(void)
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||||
{
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uint32_t value = gpio_read(GPIO_WDOG_TICKLE);
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gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
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}
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||||
#endif // APPLICATION_IBOOT
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||||
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||||
#if WITH_ENV
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||||
void target_setup_default_environment(void)
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||||
{
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||||
// boot-device is set in platform's init.c
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||||
env_set("wifiaddr", "7E:77:77:77:77:77", 0);
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}
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||||
#endif
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||||
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||||
#if WITH_DEVICETREE
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||||
int target_update_device_tree(void)
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||||
{
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||||
return 0;
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||||
}
|
||||
#endif // WITH_DEVICETREE
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||||
@@ -0,0 +1,282 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* THIS STRUCT IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: rev 0v7
|
||||
I/O Spreadsheet tracker: <rdar://problem/14388548> N56 | IOSpreadsheet
|
||||
*/
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 0 : ULPI_DIR -> LCM_TO_AP_HIFA_BSYNC
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 1 : ULPI_STP -> AP_TO_LCM_RESET_L
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 2 : ULPI_NXT -> AP_TO_TOUCH_AND_MAMBA_RESET_L
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 3 : ULPI_DATA[7] -> TOUCH_TO_AP_INT_L
|
||||
CFG_DISABLED | PULL_DOWN, // 4 : ULPI_DATA[6] -> NC
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 5 : ULPI_DATA[5] -> NC
|
||||
CFG_IN | DRIVE_X4 | SLOW_SLEW, // 6 : ULPI_DATA[4] -> DISPLAY_TO_AP_ID1
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 7 : ULPI_CLK -> OSCAR_TO_PMU_HOST_WAKE
|
||||
|
||||
/* Port 1 */
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 8 : ULPI_DATA[3] -> AP_TO_LEDDRV_EN
|
||||
CFG_IN | DRIVE_X4 | SLOW_SLEW, // 9 : ULPI_DATA[2] -> DISPLAY_TO_AP_ID0
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 10 : ULPI_DATA[1] -> AP_BI_OSCAR_SWDIO_1V8
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 11 : ULPI_DATA[0] -> AP_TO_OSCAR_SWDCLK_1V8
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 12 : SPI1_SCLK -> AP_TO_CODEC_SPI_CLK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 13 : SPI1_MOSI -> AP_TO_CODEC_SPI_MOSI
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 14 : SPI1_MISO -> CODEC_TO_AP_SPI_MISO
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 15 : SPI1_SSIN -> AP_TO_CODEC_SPI_CS_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_IN | SLOW_SLEW, // 32 : GPIO[11] -> BUTTON_TO_AP_MENU_KEY_L
|
||||
CFG_IN | SLOW_SLEW, // 33 : GPIO[12] -> BUTTON_TO_AP_HOLD_KEY_L
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 34 : I2S3_MCK -> ALS_TO_AP_INT_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 35 : I2S3_LRCK -> AP_TO_BB_I2S3_LRCLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 36 : I2S3_BCLK -> 45_AP_TO_BB_I2S3_BCLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 37 : I2S3_DOUT -> AP_TO_BB_I2S3_DOUT
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 38 : I2S3_DIN -> BB_TO_AP_I2S3_DIN
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 39 : CLK32K_OUT -> 45_AP_TO_TOUCH_CLK32K_RESET_L
|
||||
|
||||
/* Port 5 */
|
||||
CFG_IN | SLOW_SLEW, // 40 : PCIE_CLKREQ0_N -> NC
|
||||
CFG_FUNC0 | PULL_UP, // 41 : PCIE_CLKREQ1_N -> WLAN_TO_AP_PCIE1_CLKREQ_L
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 42 : NAND_SYS_CLK -> NC
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 43 : GPIO[0] -> AP_TO_HEADSET_HS3_CTRL
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 44 : GPIO[1] -> AP_TO_HEADSET_HS4_CTRL
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 45 : GPIO[2] -> BUTTON_TO_AP_VOL_UP_L
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 46 : GPIO[3] -> BUTTON_TO_AP_VOL_DOWN_L
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 47 : GPIO[4] -> SPKAMP_TO_AP_INT_L
|
||||
|
||||
/* Port 6 */
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 48 : GPIO[5] -> AP_TO_SPKAMP_BEE_GEES
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 49 : GPIO[6] -> AP_TO_SPKAMP_RESET_L
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 50 : GPIO[7] -> AP_TO_BT_WAKE
|
||||
CFG_IN | SLOW_SLEW, // 51 : GPIO[14] -> HALL_TO_PMU_AP_WAKE
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 52 : GPIO[16] -> BOARD_ID3
|
||||
CFG_OUT_0 | PULL_DOWN | SLOW_SLEW, // 53 : GPIO[17] -> AP_TO_STOCKHOLM_SIM_SEL
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 54 : GPIO[18] -> BOOT_CONFIG0
|
||||
CFG_DISABLED | PULL_DOWN, // 55 : GPIO[20] -> NC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 56 : GPIO[21] -> BB_TO_AP_DEVICE_RDY
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 57 : UART5_RTXD -> AP_TO_TIGRIS_SWI
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 58 : UART8_TXD -> AP_TO_OSCAR_UART_TXD
|
||||
CFG_FUNC0 | SLOW_SLEW, // 59 : UART8_RXD -> OSCAR_TO_AP_UART_RXD
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 60 : SPI0_SCLK -> BOARD_ID0
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 61 : SPI0_MOSI -> BOARD_ID1
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 62 : SPI0_MISO -> BOARD_ID2
|
||||
CFG_OUT_1 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 63 : SPI0_SSIN -> NC
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 64 : I2C2_SDA -> AP_BI_I2C2_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 65 : I2C2_SCL -> AP_TO_I2C2_SCL
|
||||
CFG_DISABLED | SLOW_SLEW, // 66 : GPIO[22] -> BB_TO_AP_HSIC1_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 67 : GPIO[23] -> AP_TO_BB_HOST_RDY
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 68 : GPIO[25] -> BOOT_CONFIG1
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 69 : GPIO[28] -> BOOT_CONFIG2
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 70 : GPIO[29] -> BOARD_ID4
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 71 : GPIO[34] -> BOARD_REV3
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 72 : GPIO[35] -> BOARD_REV2
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 73 : GPIO[36] -> BOARD_REV1
|
||||
CFG_DISABLED | PULL_UP | SLOW_SLEW, // 74 : GPIO[37] -> BOARD_REV0
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 75 : GPIO[39] -> NC
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 76 : GPIO[42] -> AP_TO_VIBE_EN
|
||||
CFG_OUT_1 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 77 : GPIO[43] -> AP_TO_WLAN_PCIE1_RST_L
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 78 : DISP_VSYNC -> NC
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 79 : UART0_TXD -> AP_TO_TRISTAR_DEBUG_UART0_TXD
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW, // 80 : UART0_RXD -> TRISTAR_TO_AP_DEBUG_UART0_RXD
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 81 : TMR32_PWM0 -> OSCAR_BI_AP_TIME_SYNC_HOST_INT
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 82 : TMR32_PWM1 -> AP_TO_VIBE_TRIG
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 83 : TMR32_PWM2 -> HALL_TO_AP_GPIO
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 84 : UART6_TXD -> AP_TO_TRISTAR_ACC_UART6_TXD
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW, // 85 : UART6_RXD -> TRISTAR_TO_AP_ACC_UART6_RXD
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 86 : I2C3_SDA -> NC
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 87 : I2C3_SCL -> NC
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 12 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 96 : I2C0_SDA -> AP_BI_I2C0_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 97 : I2C0_SCL -> AP_TO_I2C0_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 98 : GPIO[38] -> AP_TO_BB_COREDUMP
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : UART2_TXD -> AP_TO_BB_UART2_TXD
|
||||
CFG_FUNC0 | SLOW_SLEW, // 100 : UART2_RXD -> BB_TO_AP_UART2_RXD
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : UART2_RTSN -> AP_TO_BB_UART2_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 102 : UART2_CTSN -> BB_TO_AP_UART2_CTS_L
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 103 : DWI_DO -> 45_AP_TO_PMU_AND_BL_DWI_DO
|
||||
|
||||
/* Port 13 */
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 104 : DWI_CLK -> 45_AP_TO_PMU_AND_BL_DWI_CLK_H7P
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 105 : WDOG -> AP_TO_PMU_RESET_IN
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 106 : GPIO[13] -> PMU_TO_AP_IRQ_L
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 107 : GPIO[19] -> AP_TO_PMU_KEEPACT
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 108 : GPIO[26] -> FORCE_DFU
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 109 : GPIO[27] -> NC
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW, // 110 : SOCHOT0 -> PMU_TO_AP_PRE_UVLO_L_R
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW, // 111 : SOCHOT1 -> AP_TO_PMU_SOCHOT1_L_R
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 113 : TST_CLKOUT -> AP_TO_PMU_TEST_CLKOUT
|
||||
CFG_DISABLED | SLOW_SLEW, // 114 : GPIO[8] -> AP_TO_BB_RST_L
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW, // 115 : GPIO[9] -> AP_TO_WLAN_JTAG_SWCLK
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW, // 116 : GPIO[10] -> AP_TO_WLAN_JTAG_SWDIO
|
||||
CFG_OUT_0 | SLOW_SLEW, // 117 : GPIO[15] -> AP_TO_BB_WAKE_MODEM
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 118 : UART4_TXD -> AP_TO_WLAN_UART4_TXD
|
||||
CFG_FUNC0 | SLOW_SLEW, // 119 : UART4_RXD -> WLAN_TO_AP_UART4_RXD
|
||||
|
||||
/* Port 15 */
|
||||
CFG_OUT_1 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 120 : UART4_RTSN -> AP_TO_WLAN_UART4_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 121 : UART4_CTSN -> WLAN_TO_AP_UART4_CTS_L
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 122 : SPI3_MOSI -> NC
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 123 : SPI3_MISO -> NC
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 124 : SPI3_SCLK -> NC
|
||||
CFG_IN | SLOW_SLEW, // 125 : SPI3_SSIN -> BB_TO_AP_GPS_SYNC
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 126 : GPIO[24] -> BB_TO_AP_RESET_DET_L
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 127 : GPIO[30] -> CODEC_TO_AP_INT_L
|
||||
|
||||
/* Port 16 */
|
||||
CFG_IN | DRIVE_X4 | SLOW_SLEW, // 128 : GPIO[31] -> AP_TO_RADIO_ON_L
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW, // 129 : GPIO[32] -> AP_TO_BB_JTAG_SWCLK
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW, // 130 : GPIO[33] -> AP_TO_BB_JTAG_SWDIO
|
||||
CFG_IN | SLOW_SLEW, // 131 : GPIO[40] -> BUTTON_TO_AP_RINGER_A
|
||||
CFG_DISABLED | SLOW_SLEW, // 132 : GPIO[41] -> BB_TO_AP_IPC_GPIO
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 133 : I2S4_MCK -> TRISTAR_TO_AP_INT
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 134 : I2S4_LRCK -> AP_TO_CODEC_VSP_I2S4_LRCLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 135 : I2S4_BCLK -> 45_AP_TO_CODEC_VSP_I2S4_BCLK
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 136 : I2S4_DOUT -> AP_TO_CODEC_VSP_I2S4_DOUT
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 137 : I2S4_DIN -> CODEC_TO_AP_VSP_I2S4_DIN
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 138 : I2C1_SDA -> AP_BI_I2C1_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 139 : I2C1_SCL -> AP_TO_I2C1_SCL
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 160 : I2S0_LRCK -> AP_TO_CODEC_ASP_I2S0_LRCLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 161 : I2S0_BCLK -> 45_AP_TO_CODEC_ASP_I2S0_BCLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 162 : I2S0_DOUT -> AP_TO_CODEC_ASP_I2S0_DOUT
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 163 : I2S0_DIN -> CODEC_TO_AP_ASP_I2S0_DIN
|
||||
CFG_DISABLED | PULL_DOWN, // 164 : I2S1_MCK -> NC
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 165 : I2S1_LRCK -> AP_TO_BT_I2S1_LRCLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 166 : I2S1_BCLK -> 45_AP_TO_BT_I2S1_BCLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 167 : I2S1_DOUT -> AP_TO_BT_I2S1_DOUT
|
||||
|
||||
/* Port 21 */
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 168 : I2S1_DIN -> BT_TO_AP_I2S1_DIN
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 169 : I2S2_LRCK -> AP_TO_CODEC_XSP_I2S2_LRCLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 170 : I2S2_BCLK -> 45_AP_TO_CODEC_XSP_I2S2_BCLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 171 : I2S2_DOUT -> AP_TO_CODEC_XSP_I2S2_DOUT
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 172 : I2S2_DIN -> CODEC_TO_AP_XSP_I2S2_DIN
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 173 : UART1_TXD -> AP_TO_BT_UART1_TXD
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW, // 174 : UART1_RXD -> BT_TO_AP_UART1_RXD
|
||||
CFG_OUT_1 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 175 : UART1_RTSN -> AP_TO_BT_UART1_RTS_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW, // 176 : UART1_CTSN -> BT_TO_AP_UART1_CTS_L
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 177 : EDP_HPD -> AP_TO_STOCKHOLM_EN
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 178 : UART3_TXD -> AP_TO_STOCKHOLM_UART3_TXD
|
||||
CFG_FUNC0 | SLOW_SLEW, // 179 : UART3_RXD -> STOCKHOLM_TO_AP_UART3_RXD
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 180 : UART3_RTSN -> AP_TO_STOCKHOLM_UART3_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 181 : UART3_CTSN -> STOCKHOLM_TO_AP_UART3_CTS_L
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 182 : SPI2_SCLK -> AP_TO_TOUCH_SPI_CLK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 183 : SPI2_MOSI -> AP_TO_TOUCH_SPI_MOSI
|
||||
|
||||
/* Port 23 */
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 184 : SPI2_MISO -> TOUCH_TO_AP_SPI_MISO
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 185 : SPI2_SSIN -> AP_TO_TOUCH_SPI_CS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 186 : ISP0_SDA -> AP_BI_RCAM_I2C_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 187 : ISP0_SCL -> AP_TO_RCAM_I2C_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 188 : ISP1_SDA -> AP_BI_FCAM_I2C_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 189 : ISP1_SCL -> AP_TO_FCAM_I2C_SCL
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 190 : SENSOR0_RST -> AP_TO_RCAM_SHUTDOWN
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 191 : SENSOR0_CLK -> 45_AP_TO_RCAM_CLK_R
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 192 : SENSOR0_XSHUTDOWN -> AP_TO_STOCKHOLM_DWLD_REQ
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 193 : SENSOR0_ISTRB -> BUTTON_TO_AP_SKEY_L
|
||||
CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 194 : ISP_UART0_TXD -> NC_AP_ISP_TO_OSCAR_UART_TXD
|
||||
CFG_FUNC0 | SLOW_SLEW, // 195 : ISP_UART0_RXD -> NC_OSCAR_TO_AP_ISP_UART_RXD
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 196 : SENSOR1_RST -> AP_TO_FCAM_SHUTDOWN
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 197 : SENSOR1_CLK -> 45_AP_TO_FCAM_CLK_R
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 198 : SENSOR1_XSHUTDOWN -> CAM_EXT_LDO_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 199 : SENSOR1_ISTRB -> STOCKHOLM_TO_PMU_HOST_WAKE
|
||||
|
||||
/* Port 25 */
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 200 : UART7_TXD -> AP_TO_WLAN_DEVICE_WAKE
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 201 : UART7_RXD -> NC
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 202 : I2S0_MCK -> 45_AP_TO_CODEC_I2S0_MCLK_R
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 203 : I2S2_MCK -> 45_AP_TO_SPKAMP_I2S2_MCLK_R
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
return gpio_default_cfg;
|
||||
}
|
||||
@@ -0,0 +1,38 @@
|
||||
# Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2186=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_V2 \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=CHIPID_SOC_VOLTAGE_VMIN \
|
||||
TARGET_VID0_CLK_CFG=0x86100000 \
|
||||
TARGET_CORE_PHY_TMR_LPCLK_CFG=0x00330087 \
|
||||
TARGET_CORE_PHY_TMR_CFG=0x256f0000 \
|
||||
TARGET_PHY_STOP_WAIT_TIME=0x28 \
|
||||
DISPLAY_IPHONE_TUNABLES=1 \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_SOC=2 \
|
||||
BUCK_GPU=1 \
|
||||
TARGET_HS_2_LP_DATA_TIME=0 \
|
||||
TARGET_LP_2_HS_DATA_TIME=0 \
|
||||
TARGET_HS_2_LP_CLOCK_TIME=0 \
|
||||
TARGET_LP_2_HS_CLOCK_TIME=0
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
Reference in new issue
Block a user