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Chris Nutter committed 2023-07-08 13:03:17 -07:00
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target/ipad2b/include/target/display_gamma_tables.h
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/*
* Copyright (C) 2010, 2013-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Computer, Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_DISPLAY_GAMMA_TABLES_H
#define __TARGET_DISPLAY_GAMMA_TABLES_H
/* K9x display gamma tables */
static const display_gamma_table ipad2b_display_gamma_tables[] =
{
{
0x00951149, 0x00FFFF7F, // LGD table 8/19/2012
{
0x62, 0x0a, 0x4d, 0x40, 0x07, 0x2b, 0x03, 0x34,
0x34, 0xc0, 0x31, 0xc0, 0xdd, 0xdd, 0x34, 0x4d,
0xd3, 0xd0, 0x74, 0xd3, 0xd0, 0x34, 0x34, 0xdd,
0x34, 0x4d, 0xd3, 0x74, 0xc7, 0xdd, 0xdd, 0xc4,
0x71, 0x70, 0x1c, 0xc7, 0x01, 0xc0, 0x01, 0x70,
0x00, 0xd0, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x0d,
0xd0, 0xd0, 0x40, 0x13, 0xd0, 0x1d, 0xd3, 0x00,
0xc0, 0x01, 0x37, 0x34, 0x34, 0x34, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x62, 0x0a, 0x4d, 0x40, 0x07, 0x2b, 0x03, 0x34,
0x34, 0xc0, 0x31, 0xc0, 0xdd, 0xdd, 0x34, 0x4d,
0xd3, 0xd0, 0x74, 0xd3, 0xd0, 0x34, 0x34, 0xdd,
0x34, 0x4d, 0xd3, 0x74, 0xc7, 0xdd, 0xdd, 0xc4,
0x71, 0x70, 0x1c, 0xc7, 0x01, 0xc0, 0x01, 0x70,
0x00, 0xd0, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x0d,
0xd0, 0xd0, 0x40, 0x13, 0xd0, 0x1d, 0xd3, 0x00,
0xc0, 0x01, 0x37, 0x34, 0x34, 0x34, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x62, 0x0a, 0x4d, 0x40, 0x07, 0x2b, 0x03, 0x34,
0x34, 0xc0, 0x31, 0xc0, 0xdd, 0xdd, 0x34, 0x4d,
0xd3, 0xd0, 0x74, 0xd3, 0xd0, 0x34, 0x34, 0xdd,
0x34, 0x4d, 0xd3, 0x74, 0xc7, 0xdd, 0xdd, 0xc4,
0x71, 0x70, 0x1c, 0xc7, 0x01, 0xc0, 0x01, 0x70,
0x00, 0xd0, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x0d,
0xd0, 0xd0, 0x40, 0x13, 0xd0, 0x1d, 0xd3, 0x00,
0xc0, 0x01, 0x37, 0x34, 0x34, 0x34, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
},
{
0x00A41149, 0x00FFFF7F, // AUO table 8/20/2012
{
0x62, 0x0a, 0x0d, 0x01, 0xdd, 0x01, 0x00, 0x00,
0x00, 0xc7, 0x0d, 0x1c, 0x07, 0x07, 0xc7, 0x71,
0x70, 0x1c, 0x1c, 0x77, 0xdc, 0xc1, 0x71, 0x70,
0xc7, 0x71, 0x70, 0xc0, 0x01, 0x07, 0x00, 0x00,
0x00, 0x00, 0x1c, 0x70, 0x70, 0x70, 0x00, 0x07,
0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d,
0x00, 0x00, 0x74, 0xc7, 0x1d, 0x77, 0x37, 0x4d,
0x43, 0x03, 0x70, 0xc0, 0x01, 0x00, 0x34, 0xdd,
0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x62, 0x0a, 0x40, 0x77, 0x34, 0x1d, 0x07, 0x70,
0x70, 0xdc, 0x00, 0x00, 0xc7, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x71,
0xdc, 0x71, 0x07, 0xc7, 0xc1, 0x71, 0x1c, 0x00,
0x00, 0x70, 0x00, 0x00, 0x07, 0x1c, 0x1c, 0x00,
0x00, 0x00, 0x70, 0x0d, 0x40, 0x03, 0xd0, 0x00,
0x0d, 0x34, 0xd0, 0x1d, 0x1c, 0x70, 0xdc, 0xdd,
0xdd, 0xdd, 0x34, 0x40, 0x03, 0x34, 0x1d, 0x77,
0xdc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x62, 0x0a, 0x4d, 0x40, 0x13, 0x00, 0x40, 0xd3,
0x00, 0xc0, 0x4d, 0x73, 0x00, 0x00, 0xc0, 0x01,
0x70, 0x00, 0x07, 0x07, 0x07, 0x1c, 0xc0, 0x01,
0x07, 0x00, 0x70, 0x00, 0x07, 0x40, 0x03, 0x00,
0x00, 0x00, 0x07, 0x70, 0x00, 0x00, 0x00, 0x00,
0x07, 0x0d, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00,
0x40, 0xd3, 0xdd, 0xdd, 0x0d, 0x0d, 0x00, 0x00,
0xc0, 0x71, 0x77, 0x77, 0x77, 0x77, 0x1c, 0xc7,
0xdd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
}
};
#endif
target/ipad2b/include/target/gpiodef.h
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/*
* Copyright (C) 2011 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_GPIODEF_H
#define __TARGET_GPIODEF_H
/* K93a specific gpio -> pin mappings */
#include <platform/gpio.h>
/* define target-specific gpios in a generic fashion here. */
#define GPIO_LCD_RST GPIO( 4, 4)
#define GPIO_LCD_RST_POLARITY (0)
#define GPIO_LCD_PWR_EN GPIO( 4, 3)
#define GPIO_RINGER_AB GPIO( 0, 4)
#define POWER_GPIO_BATTERY_SWI (5)
#define POWER_GPIO_BATTERY_SWI_CONFIG_OUTPUT 0x0B
#define POWER_GPIO_BATTERY_SWI_CONFIG_INPUT 0xD8
/* Board Revision */
#define GPIO_BOARD_REV0 GPIO( 4, 5)
#define GPIO_BOARD_REV1 GPIO( 4, 6)
#define GPIO_BOARD_REV2 GPIO( 4, 7)
/* which IICs to initialize */
#define IICS_MASK (7)
#define TRISTAR_IIC_BUS (0)
/* D1946 watchdog tickle, 'KEEPACT' */
#define GPIO_WDOG_TICKLE GPIO(2, 3)
#endif /* ! __TARGET_GPIODEF_H */
target/ipad2b/include/target/nand_spec_tables.h
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// Copyright (C) 2008-2010 Apple, Inc. All rights reserved.
//
// This document is the property of Apple, Inc.
// It is considered confidential and proprietary.
//
// This document may not be reproduced or transmitted in any form,
// in whole or in part, without the express written permission of
// Apple, Inc.
//
// NOTE: This is a generated file and should not be hand-edited!
//
// =============================================================================
// Nand Geometry Table
static NandGeometry _nandGeometryTable[] =
{
};
// =============================================================================
// Nand Timing Table
static NandTiming _nandTimingTable[] =
{
};
#if (defined (AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
// =============================================================================
// NandChipId Description
const NandChipIdDescription _nandChipIdDescriptionTable[] =
{
};
// =============================================================================
// Nand Description Table
static const NandDescription _nandDescriptionTable[] =
{
};
const UInt32 _nandDescriptionTableSize = sizeof(_nandDescriptionTable) / sizeof(NandDescription);
#endif // (defined(AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
// =============================================================================
// Nand Board Support Table
static NandBoardSupport _nandBoardSupportTable[] =
{
};
// =============================================================================
// Nand Board Timing Table
static NandBoardInfo _nandBoardInfo =
{
/* controlDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
/* dataDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
/* chipEnableDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
/* socToNandRiseNanosecs */ 10,
/* socToNandFallNanosecs */ 10,
/* nandToSocRiseNanosecs */ 10,
/* nandToSocFallNanosecs */ 10,
/* landing map */
{
0x00000101
},
/* useToggleMode */ TRUE32,
/* useDiffDQSMode */ FALSE32,
/* useDiffREMode */ FALSE32,
/* useVref */ TRUE32,
/* useSingleHostChannel */ FALSE32,
/* allowSingleChipEnable */ TRUE32
};
static NandFormat _nandFormatPpn =
{
/* metaPerLogicalPage */ 16,
/* validMetaPerLogicalPage */ 16,
/* logicalPageSize */ 4096
};
static NandFormat _nandFormatRaw =
{
/* metaPerLogicalPage */ 12,
/* validMetaPerLogicalPage */ 10,
/* logicalPageSize */ 0
};
target/ipad2b/include/target/pinconfig.h
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/*
* Copyright (C) 2009-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
/* Default P105/6/7 SoC Pin Configuration from rev 2.1 */
/* Different drive strength for AP and DEV. */
#if PIN_CFG_AP
#define AP_DEV_DRIVE_STR(ap, dev) DRIVE_##ap
#elif PIN_CFG_DEV
#define AP_DEV_DRIVE_STR(ap, dev) DRIVE_##dev
#endif
#if TARGET_HAS_BASEBAND
#define IF_BB(x, y) (x)
#else
#define IF_BB(x, y) (y)
#endif
#if PIN_CFG_AP
static const u_int32_t gpio_default_cfg_ap[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#elif PIN_CFG_DEV
static const u_int32_t gpio_default_cfg_dev[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#endif
/* Port 0 */
CFG_IN, // GPIO0 -> MENU_KEY (REQUEST_DFU2)
CFG_IN, // GPIO1 -> HOLD_KEY (REQUEST_DFU1)
CFG_IN | PULL_UP, // GPIO2 -> GPIO_BTN_VOL_UP_L
CFG_IN | PULL_UP, // GPIO3 -> GPIO_BTN_VOL_DOWN_L
CFG_IN, // GPIO4 -> GPIO_BTN_SRL_L
CFG_OUT_0 | DRIVE_X1, // GPIO5 -> GPIO_SPKAMP_RST_L
CFG_OUT_0 | DRIVE_X1, // GPIO6 -> GPIO_SPKAMP_KEEPALIVE
CFG_IN | PULL_UP, // GPIO7 -> GPIO_SPKAMP_LEFT_IRQ_L
/* Port 1 */
CFG_IN | PULL_UP, // GPIO8 -> GPIO_CODEC_IRQ_L
CFG_OUT_0 | DRIVE_X1, // GPIO9 -> GPIO_BT_WAKE
IF_BB(CFG_IN, CFG_DISABLED | PULL_DOWN), // GPIO10 -> GPIO_BB_RST_L
CFG_DISABLED | PULL_DOWN, // GPIO11 -> GPIO_BB_GSM_TXBURST
IF_BB(CFG_OUT_0, CFG_DISABLED | PULL_DOWN) | DRIVE_X1, // GPIO12 -> GPIO_BB_IPC_GPIO
IF_BB(CFG_IN, CFG_DISABLED) | PULL_DOWN, // GPIO13 -> GPIO_BB_HSIC1_REMOTE_WAKE
CFG_DISABLED | PULL_DOWN, // GPIO14 -> GPIO_BB_GPS_SYNC
IF_BB(CFG_IN, CFG_DISABLED) | PULL_DOWN, // GPIO15 -> GPIO_BB_RST_DET_L
/* Port 2 */
CFG_DISABLED, // GPIO16 -> GPIO_BOARD_ID3
IF_BB(CFG_OUT_0, CFG_DISABLED | PULL_DOWN) | DRIVE_X1, // GPIO17 -> GPIO_BB_HSIC_HOST_RDY
CFG_DISABLED, // GPIO18 -> GPIO_BOOT_CONFIG0
CFG_IN | PULL_UP, // GPIO19 -> GPIO_PMU_IRQ_L
CFG_OUT_0 | DRIVE_X1, // GPIO20 -> GPIO_PMU_KEEPACT
CFG_OUT_0 | DRIVE_X1, // GPIO21 -> GPIO_GRAPE_RST_L
CFG_IN | PULL_UP, // GPIO22 -> GPIO_GRAPE_IRQ_L
IF_BB(CFG_IN, CFG_DISABLED | PULL_DOWN) | DRIVE_X1, // GPIO23 -> GPIO_BB_RADIO_ON_L
/* Port 3 */
IF_BB(CFG_IN, CFG_DISABLED) | PULL_DOWN, // GPIO24 -> GPIO_BB_HSIC_DEV_RDY
CFG_DISABLED, // GPIO25 -> GPIO_BOOT_CONFIG1
CFG_IN | PULL_DOWN, // GPIO26 -> GPIO_FORCE_DFU
CFG_OUT_0 | PULL_DOWN | DRIVE_X1, // GPIO27 -> GPIO_DFU_STATUS
CFG_DISABLED, // GPIO28 -> GPIO_BOOT_CONFIG2
CFG_DISABLED, // GPIO29 -> GPIO_BOOT_CONFIG3
IF_BB(CFG_IN, CFG_DISABLED | PULL_DOWN), // GPIO30 -> GPIO_PROX_IRQ_L
CFG_DISABLED, // GPIO31 ->
/* Port 4 */
CFG_IN | PULL_DOWN, // GPIO32 -> GPIO_ACCEL_IRQ2_L
CFG_IN | PULL_DOWN, // GPIO33 -> GPIO_GYRO_IRQ1
CFG_IN | PULL_DOWN, // GPIO34 -> GPIO_WLAN_HSIC_RESUME
CFG_OUT_0 | DRIVE_X1, // GPIO35 -> GPIO_MLC_PWR_EN
CFG_OUT_0 | DRIVE_X1, // GPIO36 -> GPIO_MLC_RST_1V8_L
CFG_DISABLED, // EHCI_PORT_PWR[0] -> GPIO_BOARD_REV0
CFG_DISABLED, // EHCI_PORT_PWR[1] -> GPIO_BOARD_REV1
CFG_DISABLED, // EHCI_PORT_PWR[2] -> GPIO_BOARD_REV2
/* Port 5 */
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X3), // UART1_TXD -> UART1_BT_TXD
CFG_FUNC0, // UART1_RXD -> UART1_BT_RXD
CFG_OUT_1 | AP_DEV_DRIVE_STR(X1, X3), // UART1_RTSN -> UART1_BT_RTS_L
CFG_FUNC0, // UART1_CTSN -> UART1_BT_CTS_L
CFG_FUNC0 | DRIVE_X1, // UART2_TXD -> UART2_ACC_TXD
CFG_FUNC0, // UART2_RXD -> UART2_ACC_RXD
CFG_IN | PULL_UP, // UART2_RTSN -> GPIO_SPKAMP_RIGHT_IRQ_L
CFG_IN | PULL_UP, // UART2_CTSN -> GPIO_ALS_IRQ_L
/* Port 6 */
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X3), // UART3_TXD -> UART3_WLAN_TXD
CFG_FUNC0, // UART3_RXD -> UART3_WLAN_RXD
CFG_OUT_0 | DRIVE_X1, // UART3_RTSN -> GPIO_WLAN_HSIC_HOST_RDY
CFG_IN | PULL_DOWN, // UART3_CTSN -> GPIO_WLAN_HSIC_DEV_RDY
CFG_FUNC0 | DRIVE_X2, // I2C0_SDA -> I2C0_SDA
CFG_FUNC0 | DRIVE_X2, // I2C0_SCL -> I2C0_SCL
CFG_FUNC0 | DRIVE_X2, // I2C1_SDA -> I2C1_SDA
CFG_FUNC0 | DRIVE_X2, // I2C1_SCL -> I2C1_SCL
/* Port 7 */
CFG_FUNC0 | DRIVE_X2, // ISP0_SDA -> ISP0_CAM_REAR_SDA
CFG_FUNC0 | DRIVE_X2, // ISP0_SCL -> ISP0_CAM_REAR_SCL
CFG_FUNC0 | DRIVE_X2, // ISP1_SDA -> ISP1_CAM_FRONT_SDA
CFG_FUNC0 | DRIVE_X2, // ISP1_SCL -> ISP1_CAM_FRONT_SCL
CFG_DISABLED | PULL_DOWN, // MIPI_VSYNC -> DISPLAY_SYNC
CFG_FUNC0 | PULL_DOWN, // TMR32_PWM0 -> GPIO_GYRO_IRQ2
CFG_FUNC0 | PULL_DOWN, // TMR32_PWM1 -> GPIO_ACCEL_IRQ1_L
CFG_FUNC0 | DRIVE_X2, // TMR32_PWM2 -> AP_CLK_32K_CUMULUS
/* Port 8 */
CFG_DISABLED, // SWI_DATA ->
CFG_FUNC0 | PULL_DOWN, // DWI_DI -> DWI_DI
CFG_FUNC0 | DRIVE_X2, // DWI_DO -> DWI_DO
CFG_FUNC0 | DRIVE_X2, // DWI_CLK -> DWI_CLK
CFG_OUT_1 | DRIVE_X1, // SENSOR0_RST -> ISP0_CAM_REAR_SHUTDOWN
CFG_OUT_0 | DRIVE_X3, // SENSOR0_CLK -> ISP0_CAM_REAR_CLK_R
CFG_OUT_1 | DRIVE_X1, // SENSOR1_RST -> ISP1_CAM_FRONT_SHUTDOWN
CFG_OUT_0 | DRIVE_X3, // SENSOR1_CLK -> ISP1_CAM_FRONT_CLK_R
/* Port 9 */
CFG_DISABLED, // ISP0_PRE_FLASH ->
CFG_DISABLED, // ISP0_FLASH ->
CFG_DISABLED, // ISP1_PRE_FLASH ->
CFG_DISABLED, // ISP1_FLASH ->
CFG_FUNC0 | DRIVE_X3, // I2S0_MCK -> I2S0_CODEC_ASP_MCK_R
CFG_FUNC0 | DRIVE_X2, // I2S0_LRCK -> I2S0_CODEC_ASP_LRCK
CFG_FUNC0 | DRIVE_X2, // I2S0_BCLK -> I2S0_CODEC_ASP_BCLK
CFG_FUNC0 | DRIVE_X2, // I2S0_DOUT -> I2S0_CODEC_ASP_DOUT
/* Port 10 */
CFG_FUNC0, // I2S0_DIN -> I2S0_CODEC_ASP_DIN
CFG_FUNC0 | DRIVE_X3, // I2S1_MCK -> I2S1_SPKAMP_MCK_R
CFG_FUNC0 | DRIVE_X2, // I2S1_LRCK -> I2S1_SPKAMP_LRCK
CFG_FUNC0 | DRIVE_X2, // I2S1_BCLK -> I2S1_SPKAMP_BCLK
CFG_FUNC0 | DRIVE_X2, // I2S1_DOUT -> I2S1_SPKAMP_DOUT
CFG_FUNC0, // I2S1_DIN -> I2S1_SPKAMP_DIN
CFG_IN, // I2S2_MCK -> PMU_GPIO_TRISTAR_IRQ
CFG_FUNC0 | DRIVE_X2, // I2S2_LRCK -> I2S2_CODEC_XSP_LRCK
/* Port 11 */
CFG_FUNC0 | DRIVE_X2, // I2S2_BCLK -> I2S2_CODEC_XSP_BCLK
CFG_FUNC0 | DRIVE_X2, // I2S2_DOUT -> I2S2_CODEC_XSP_DOUT
CFG_FUNC0, // I2S2_DIN -> I2S2_CODEC_XSP_DIN
CFG_IN, // I2S3_MCK -> GPIO_ACC_SW_POK_L
CFG_FUNC0 | DRIVE_X2, // I2S3_LRCK -> I2S3_BT_LRCK
CFG_FUNC0 | DRIVE_X2, // I2S3_BCLK -> I2S3_BT_BCLK
CFG_FUNC0 | DRIVE_X2, // I2S3_DOUT -> I2S3_BT_DOUT
CFG_FUNC0, // I2S3_DIN -> I2S3_BT_DIN
/* Port 12 */
CFG_DISABLED, // SPI0_SCLK -> GPIO_BOARD_ID0
CFG_DISABLED, // SPI0_MOSI -> GPIO_BOARD_ID1
CFG_DISABLED, // SPI0_MISO -> GPIO_BOARD_ID2
CFG_DISABLED | PULL_UP, // SPI0_SSIN ->
CFG_FUNC0 | DRIVE_X2, // SPI1_SCLK -> SPI1_GRAPE_SCLK
CFG_FUNC0 | DRIVE_X2, // SPI1_MOSI -> SPI1_GRAPE_MOSI
CFG_FUNC0, // SPI1_MISO -> SPI1_GRAPE_MISO
CFG_OUT_1 | DRIVE_X1, // SPI1_SSIN -> SPI1_GRAPE_CS_L
/* Port 13 */
CFG_FUNC0 | DRIVE_X2, // SPI2_SCLK -> SPI2_CODEC_SCLK
CFG_FUNC0 | DRIVE_X2, // SPI2_MOSI -> SPI2_CODEC_MOSI
CFG_FUNC0, // SPI2_MISO -> SPI2_CODEC_MISO
CFG_OUT_1 | DRIVE_X1, // SPI2_SSIN -> SPI2_CODEC_CS_L
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
/* Port 14 */
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
/* Port 15 */
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
/* Port 16 */
IF_BB(CFG_IN, CFG_DISABLED | PULL_DOWN) | AP_DEV_DRIVE_STR(X1, X3), // UART4_TXD -> UART4_BB_TXD
IF_BB(CFG_FUNC0, CFG_DISABLED | PULL_DOWN), // UART4_RXD -> UART4_BB_RXD
IF_BB(CFG_IN, CFG_DISABLED | PULL_DOWN) | AP_DEV_DRIVE_STR(X1, X3), // UART4_RTSN -> UART4_BB_RTS_L
IF_BB(CFG_FUNC0, CFG_DISABLED | PULL_DOWN), // UART4_CTSN -> UART4_BB_CTS_L
CFG_OUT_0 | DRIVE_X1, // SDIO0_DATA3 -> GPIO_ACC_SW_EN
IF_BB(CFG_DISABLED, CFG_DISABLED | PULL_DOWN), // SDIO0_DATA2 -> BB_JTAG_TRST_L
IF_BB(CFG_DISABLED, CFG_DISABLED | PULL_DOWN), // SDIO0_DATA1 -> BB_JTAG_TDO
IF_BB(CFG_DISABLED, CFG_DISABLED | PULL_DOWN), // SDIO0_DATA0 -> BB_JTAG_TDI
/* Port 17 */
IF_BB(CFG_DISABLED, CFG_DISABLED | PULL_DOWN), // SDIO0_CMD -> BB_JTAG_TMS
IF_BB(CFG_DISABLED, CFG_DISABLED | PULL_DOWN), // SDIO0_CLK -> BB_JTAG_TCK
CFG_DISABLED, // FMI0_CEN3 ->
CFG_DISABLED, // FMI0_CEN2 ->
CFG_DISABLED, // FMI0_CEN1 ->
CFG_FUNC0 | DRIVE_X1, // FMI0_CEN0 -> FMI0_CE0_L
CFG_FUNC0 | DRIVE_X1, // FMI0_CLE -> FMI0_CLE
CFG_FUNC0 | DRIVE_X1, // FMI0_ALE -> FMI0_ALE
/* Port 18 */
CFG_FUNC0 | DRIVE_X1, // FMI0_REN -> FMI0_RE_N
CFG_FUNC0 | DRIVE_X1, // FMI0_WEN -> FMI0_WE_L
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI0_IO7 -> FMI0_AD<7>
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI0_IO6 -> FMI0_AD<6>
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI0_IO5 -> FMI0_AD<5>
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI0_IO4 -> FMI0_AD<4>
CFG_DISABLED, // ->
CFG_DISABLED, // ->
/* Port 19 */
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
/* Port 20 */
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI0_DQS -> FMI0_DQS_P
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI0_IO3 -> FMI0_AD<3>
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI0_IO2 -> FMI0_AD<2>
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI0_IO1 -> FMI0_AD<1>
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI0_IO0 -> FMI0_AD<0>
CFG_DISABLED, // FMI1_CEN3 ->
CFG_DISABLED, // FMI1_CEN2 ->
CFG_DISABLED, // FMI1_CEN1 ->
/* Port 21 */
CFG_FUNC0 | DRIVE_X1, // FMI1_CEN0 -> FMI1_CE0_L
CFG_FUNC0 | DRIVE_X1, // FMI1_CLE -> FMI1_CLE
CFG_FUNC0 | DRIVE_X1, // FMI1_ALE -> FMI1_ALE
CFG_FUNC0 | DRIVE_X1, // FMI1_REN -> FMI1_RE_N
CFG_FUNC0 | DRIVE_X1, // FMI1_WEN -> FMI1_WE_L
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI1_IO7 -> FMI1_AD<7>
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI1_IO6 -> FMI1_AD<6>
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI1_IO5 -> FMI1_AD<5>
/* Port 22 */
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI1_IO4 -> FMI1_AD<4>
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI1_DQS -> FMI1_DQS_P
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI1_IO3 -> FMI1_AD<3>
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI1_IO2 -> FMI1_AD<2>
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI1_IO1 -> FMI1_AD<1>
CFG_FUNC0 | BUS_HOLD | DRIVE_X1, // FMI1_IO0 -> FMI1_AD<0>
CFG_DISABLED, // ->
CFG_DISABLED, // ->
/* Port 23 */
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
/* Port 24 */
CFG_FUNC0 | DRIVE_X2, // I2C2_SDA -> I2C2_SDA
CFG_FUNC0 | DRIVE_X2, // I2C2_SCL -> I2C2_SCL
CFG_FUNC0 | DRIVE_X1, // UART0_TXD -> UART0_DEBUG_TXD
CFG_FUNC0, // UART0_RXD -> UART0_DEBUG_RXD
CFG_FUNC0 | DRIVE_X2, // UART5_RTXD -> UART5_BATT_RTXD
CFG_DISABLED, // DP_HPD ->
CFG_DISABLED, // TST_CLKOUT -> TP_SOC_TST_CLKOUT
CFG_DISABLED, // TST_STPCLK -> SOC_TST_STPCLK
/* Port 25 */
CFG_FUNC0 | DRIVE_X1, // WDOG -> SOC_WDOG
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
CFG_DISABLED, // ->
};
#undef AP_DEV_DRIVE_STR
#undef IF_BB
target/ipad2b/include/target/powerconfig.h
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/*
* Copyright (C) 2010 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_POWERCONFIG_H
#define __TARGET_POWERCONFIG_H
#include <drivers/gasgauge.h>
/* configuration per target */
#define PMU_IIC_BUS 0
/* this configuration is very PMU specific and must be included exactly once in power.c */
#ifdef POWERCONFIG_PMU_SETUP
static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
{
{ PMU_IIC_BUS, kDIALOG_LDO_CONTROL, 0x00 }, // Force bypass off
{ PMU_IIC_BUS, kD1946_LDO1, 0x0A }, // PP3V0_SPARE1 3.00V
{ PMU_IIC_BUS, kD1946_LDO2, 0x0A }, // PP1V7_VA_VCP 1.70V
{ PMU_IIC_BUS, kD1946_LDO3, 0x0A }, // PP3V0_S2R_TRISTAR 3.00V
{ PMU_IIC_BUS, kD1946_LDO4, 0x18 }, // PP3V0_SENSOR 3.00V
{ PMU_IIC_BUS, kD1946_LDO5, 0x0E }, // PP3V2_SPARE2 3.20V
{ PMU_IIC_BUS, kD1946_LDO6, 0x10 }, // PP3V3_ACC 3.30V
{ PMU_IIC_BUS, kD1946_LDO7, 0x03 }, // PP1V8_CAM 1.80V
{ PMU_IIC_BUS, kD1946_LDO8, 0x14 }, // PP3V0_S2R_HALL 3.00V
{ PMU_IIC_BUS, kD1946_LDO9, 0x01 }, // PP1V2_CAM 1.30V
{ PMU_IIC_BUS, kD1946_LDO10, 0x02 }, // PP2V8_CAM_AF 2.60V
{ PMU_IIC_BUS, kD1946_LDO11, 0x16 }, // PP2V8_CAM 2.80V
{ PMU_IIC_BUS, kD1946_LDO12, 0x10 }, // PP1V0 1.00V
{ PMU_IIC_BUS, kDIALOG_LDO_CONTROL, 0x00 }, // Leave bypass off
};
static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
{
{ PMU_IIC_BUS, kD1946_ACTIVE1, 0xDD }, // Everything but BUCK1 and LDO1
{ PMU_IIC_BUS, kD1946_ACTIVE2, 0xB9 }, // LDO5, 6, and 10 are off
{ PMU_IIC_BUS, kD1946_ACTIVE3, 0x61 }, // LDO12, Buck5, and WLED Boost
{ PMU_IIC_BUS, kD1946_ACTIVE4, 0xA0 }, // CPU1V8_SW and CPU1V2_SW
{ PMU_IIC_BUS, kD1946_LCM_CONTROL1, 0x05 }, // unused 5.25V
{ PMU_IIC_BUS, kD1946_LCM_CONTROL2, 0x0E }, // unused 5.70V
{ PMU_IIC_BUS, kD1946_LCM_CONTROL3, 0x00 }, // BB_VBUS_DET 5.00V
{ PMU_IIC_BUS, kD1946_LCM_BST_CONTROL, 0x14 }, // VBOOST_LCM 6.00V
};
static const struct pmu_setup_struct pmu_warm_init[] =
{
{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2, 0x10 }, // HIB_32K on, DWI off
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_A, 0x00 },
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_B, 0x00 },
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_C, 0x00 },
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_D, 0x00 },
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_E, 0x00 },
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_F, 0x00 },
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_G, 0x00 },
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_H, 0x00 },
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_K, 0x00 },
};
static const struct pmu_setup_struct pmu_cold_init[] =
{
{ PMU_IIC_BUS, kD1946_BUCK4, 0x9B }, // BUCK4 1.21V
{ PMU_IIC_BUS, kD1946_BUCK4_HIB, 0x9B }, // BUCK4_HIB 1.21V
{ PMU_IIC_BUS, kD1946_SYS_GPIO_1, 0x11 }, // PMU_CLK_32K_CUMULUS Out 0, Push-Pull, CPU_1V8
{ PMU_IIC_BUS, kD1946_SYS_GPIO_2, 0x49 }, // PMU_CLK_32K_WLAN CLK32K, Pull Down, VBUCK3
{ PMU_IIC_BUS, kD1946_SYS_GPIO_3, 0x09 }, // PMU_GPIO_BT_REG_ON Out 0, Push-Pull, VBUCK3
{ PMU_IIC_BUS, kD1946_SYS_GPIO_4, 0x09 }, // PMU_GPIO_WLAN_REG_ON Out 0, Push-Pull, VBUCK3
{ PMU_IIC_BUS, kD1946_SYS_GPIO_5, 0x18 }, // PMU_GPIO_BB_RST_L Out 0, OD/PU, Disable Pull-Up
{ PMU_IIC_BUS, kD1946_SYS_GPIO_6, 0xDA }, // UART5_BATT_RTXD In, F Edge, Wake, Pull Up, Disable Pull-Up
{ PMU_IIC_BUS, kD1946_SYS_GPIO_7, 0xBA }, // PMU_GPIO_BT_HOST_WAKE In, R Edge, Wake, Pull Down, Disable Pull-Up
{ PMU_IIC_BUS, kD1946_SYS_GPIO_8, 0xBA }, // PMU_GPIO_WLAN_HOST_WAKE In, R Edge, Wake, Pull Down, Disable Pull-Up
#if TARGET_HAS_BASEBAND
{ PMU_IIC_BUS, kD1946_SYS_GPIO_9, 0xBA }, // PMU_GPIO_BB_WAKE In, R Edge, Wake, No Pull Down, Disable Pull-Up
#else
{ PMU_IIC_BUS, kD1946_SYS_GPIO_9, 0xB9 }, // PMU_GPIO_BB_WAKE In, R Edge, No Wake, Pull Down, Disable Pull-Up
#endif
{ PMU_IIC_BUS, kD1946_SYS_GPIO_10, 0xEA }, // PMU_GPIO_CODEC_HS_IRQ_L In, Any Edge, Wake, Pull Up, VBUCK3
{ PMU_IIC_BUS, kD1946_SYS_GPIO_11, 0xC8 }, // PMU_GPIO_CODEC_RST_L In, F Edge, No Wake, VBUCK3 (for internal PU)
{ PMU_IIC_BUS, kD1946_SYS_GPIO_12, 0xB9 }, // PMU_GPIO_TRISTAR_IRQ In, R Edge, No Wake, Pull Down
{ PMU_IIC_BUS, kD1946_SYS_GPIO_13, 0xFA }, // PMU_GPIO_HALL_IRQ_1 In, Change, Wake, Pull Up
{ PMU_IIC_BUS, kD1946_SYS_GPIO_14, 0xFA }, // PMU_GPIO_HALL_IRQ_2 In, Change, Wake, Pull Up
{ PMU_IIC_BUS, kD1946_SYS_GPIO_15, 0xB9 }, // PMU_GPIO_HALL_IRQ_3 In, R Edge, No Wake, Pull Down, Disable Pull-Up
{ PMU_IIC_BUS, kD1946_SYS_GPIO_16, 0xF8 }, // PMU_GPIO_HALL_IRQ_4 In, Change, No Wake, Disable Pull-Up
{ PMU_IIC_BUS, kD1946_SYS_GPIO_17, 0xB9 }, // unused In, R Edge, No Wake, Pull Down, Disable Pull-Up
{ PMU_IIC_BUS, kD1946_SYS_GPIO_18, 0xB9 }, // unused In, R Edge, No Wake, Pull Down, Disable Pull-Up
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB1, 0x12 }, // 10ms debounce
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB2, 0x12 }, // 10ms debounce
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB3, 0x12 }, // 10ms debounce
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB4, 0x12 }, // 10ms debounce
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB5, 0x12 }, // 10ms debounce
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB6, 0x12 }, // 10ms debounce
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB7, 0x12 }, // 10ms debounce
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB8, 0x12 }, // 10ms debounce
{ PMU_IIC_BUS, kD1946_SYS_GPIO_DEB9, 0x12 }, // 10ms debounce
// <rdar://problem/8932682>
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x02 },
{ PMU_IIC_BUS, kD1946_TEST_MODE, 0x01 }, // Enable test mode
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x01 },
{ PMU_IIC_BUS, kD1946_WLED_CONTROL5, 0x00 }, // set WLED to IDAC always
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x02 },
{ PMU_IIC_BUS, kD1946_TEST_MODE, 0x00 }, // Disable test mode
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x00 },
};
static const struct pmu_setup_struct pmu_backlight_enable[] =
{
{ PMU_IIC_BUS, kDIALOG_WLED_ISET, 0xD4 }, // 50% value from OS
{ PMU_IIC_BUS, kDIALOG_WLED_ISET2, 0x00 },
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, // enable all LED strings
(kDIALOG_WLED_CONTROL_WLED_ENABLE1 |
kDIALOG_WLED_CONTROL_WLED_ENABLE2 |
kDIALOG_WLED_CONTROL_WLED_ENABLE3 |
kDIALOG_WLED_CONTROL_WLED_ENABLE4 |
kDIALOG_WLED_CONTROL_WLED_ENABLE5 |
kDIALOG_WLED_CONTROL_WLED_ENABLE6) },
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL2, // enable LED Power
(kDIALOG_WLED_CONTROL2_WLED_RAMP_EN |
kDIALOG_WLED_CONTROL2_WLED_DITH_EN) }
};
static const struct pmu_setup_struct pmu_backlight_disable[] =
{
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, 0x0 } // disable LED power
};
static const struct core_rails_struct soc_rails[] =
{
{ PMU_IIC_BUS, 0, kDIALOG_BUCK2 }
};
static const struct core_rails_struct cpu_rails[] =
{
{ PMU_IIC_BUS, 0, kDIALOG_BUCK0 }
};
#endif /* POWERCONFIG_PMU_SETUP */
#define TARGET_USE_CHARGE_TABLE 1
static const struct power_charge_limits pmu_charge_table[16] = { // gas gauge can have up to 16 entries
{ 4000, 1000, 1600, 2520 }, // 10 - 16C
{ 4100, 1000, 1600, 2240 },
{ USHRT_MAX, 1000, 1600, 1320 },
{ 4000, 1500, 2100, 2520 }, // 15 - 21C
{ 4100, 1500, 2100, 2520 },
{ USHRT_MAX, 1500, 2100, 1320 },
{ 4000, 2000, 3500, 2520 }, // 20 - 35C
{ 4100, 2000, 3500, 2520 },
{ USHRT_MAX, 2000, 3500, 2240 },
{ 4000, 3400, 4500, 2520 }, // 34 - 45C
{ 4100, 3400, 4500, 2520 },
{ USHRT_MAX, 3400, 4500, 2240 },
};
// matches OTP for ICHG_TBAT_x
#define TARGET_ICHG_TBAT_MAX { 0x00, 0x00, 0x3f, 0x3f, 0x3f }
#define NO_BATTERY_VOLTAGE 2700
#define MIN_BOOT_BATTERY_VOLTAGE 3600
#define TARGET_BOOT_BATTERY_VOLTAGE 3700
#define TARGET_BOOT_BATTERY_CAPACITY 50
#define PRECHARGE_BACKLIGHT_LEVEL 1287 /* 10% brightness */
#define TARGET_PRECHARGE_ALWAYS_DISPLAY_IDLE 1
#define TARGET_MAX_USB_INPUT_CURRENT 2100
#define GASGAUGE_BATTERYID_BLOCK 1
#define GASGAUGE_CHARGETABLE_BLOCK 3
static const unsigned int atv_voltage_limit[16] = { 3600, 3650, 3700, 3750, 3800, 3850, 3900, 3950, 4000, 4050, 4100, 4150, 4200, 4250, 4300, 4350 };
static const unsigned int atv_current_limit[16] = { 0, 200, 440, 640, 880, 1120, 1320, 1560, 1760, 2000, 2240, 2440, 2520, 2520, 2520, 2520 };
#define ACC_PWR_LDO (6)
#endif
target/ipad2b/include/target/uartconfig.h
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/*
* Copyright (C) 2010 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_UARTCONFIG_H
#define __TARGET_UARTCONFIG_H
/* define two debug serial ports */
#define DEBUG_SERIAL_PORT (0)
/* define HDQ serial port */
#define HDQGAUGE_SERIAL_PORT (5)
#define UART_FLOWCONTROL_MASK (0x08)
#endif
target/ipad2b/include/target/usbconfig.h
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/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_USBCONFIG_H
#define __TARGET_USBCONFIG_H
#ifdef USBPHY_UOTGTUNE1
#undef USBPHY_UOTGTUNE1
#define USBPHY_UOTGTUNE1 (0x549)
#endif /* USBPHY_UOTGTUNE1 */
#ifdef USBPHY_UOTGTUNE2
#undef USBPHY_UOTGTUNE2
#define USBPHY_UOTGTUNE2 (0x2FF3)
#endif /* USBPHY_UOTGTUNE2 */
#endif /* __TARGET_USBCONFIG_H */