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Chris Nutter committed 2023-07-08 13:03:17 -07:00
commit 1bf4efd552
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target/ipad3b/include/target/gpiodef.h
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/*
* Copyright (C) 2011 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_GPIODEF_H
#define __TARGET_GPIODEF_H
/* P101/P102/P103 specific gpio -> pin mappings */
#include <platform/gpio.h>
/* define target-specific gpios in a generic fashion here. */
#define GPIO_LCD_PWR_EN GPIO(26, 0)
#define GPIO_RINGER_AB GPIO(25, 2)
/* Board Revision */
#define GPIO_BOARD_REV0 GPIO( 4, 2)
#define GPIO_BOARD_REV1 GPIO( 4, 3)
#define GPIO_BOARD_REV2 GPIO( 4, 4)
/* which IICs to initialize */
#define IICS_MASK (7)
#define TRISTAR_IIC_BUS (0)
/* PMU watchdog tickle; connected to GPIO_PMU_KEEPACT */
#define GPIO_WDOG_TICKLE GPIO(24, 2)
// Configure both FMI0 & FMI1 to use differential DQS with DQ set to DQVREF
#define FMI_DIFF_SEL (0x36)
#endif /* ! __TARGET_GPIODEF_H */
target/ipad3b/include/target/nand_spec_tables.h
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// Copyright (C) 2008-2011 Apple, Inc. All rights reserved.
//
// This document is the property of Apple, Inc.
// It is considered confidential and proprietary.
//
// This document may not be reproduced or transmitted in any form,
// in whole or in part, without the express written permission of
// Apple, Inc.
//
// NOTE: This is a generated file and should not be hand-edited!
//
// =============================================================================
// Nand Geometry Table
static NandGeometry _nandGeometryTable[] =
{
};
// =============================================================================
// Nand Timing Table
static NandTiming _nandTimingTable[] =
{
};
#if (defined (AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
// =============================================================================
// NandChipId Description
const NandChipIdDescription _nandChipIdDescriptionTable[] =
{
};
// =============================================================================
// Nand Description Table
static const NandDescription _nandDescriptionTable[] =
{
};
const UInt32 _nandDescriptionTableSize = sizeof(_nandDescriptionTable) / sizeof(NandDescription);
#endif // (defined(AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
// =============================================================================
// Nand Board Support Table
static NandBoardSupport _nandBoardSupportTable[] =
{
};
// =============================================================================
// Nand Board Timing Table
static NandBoardInfo _nandBoardInfo =
{
/* controlDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
/* dataDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
/* chipEnableDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
/* socToNandRiseNanosecs */ 10,
/* socToNandFallNanosecs */ 10,
/* nandToSocRiseNanosecs */ 10,
/* nandToSocFallNanosecs */ 10,
/* landing map */
{
0x00000101
},
/* useToggleMode */ TRUE32,
/* useDiffDQSMode */ FALSE32,
/* useDiffREMode */ FALSE32,
/* useVref */ TRUE32,
/* useSingleHostChannel */ FALSE32,
/* allowSingleChipEnable */ FALSE32
};
static NandFormat _nandFormatPpn =
{
/* metaPerLogicalPage */ 16,
/* validMetaPerLogicalPage */ 16,
/* logicalPageSize */ 4096
};
static NandFormat _nandFormatRaw =
{
/* metaPerLogicalPage */ 12,
/* validMetaPerLogicalPage */ 10,
/* logicalPageSize */ 0
};
target/ipad3b/include/target/pinconfig.h
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/*
* Copyright (C) 2011-2012 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
/* Default P101/P102/P103 SoC Pin Configuration
Based on I/O spreadsheet rev2p3
<rdar://problem/10363068> X140 IO Spreadsheet tracker
Do not modify without first requesting an update to the I/O spreadsheet
*/
#define CFG_RESERVED CFG_DISABLED
/* Different drive strength for AP and DEV. */
#if PIN_CFG_AP
#define AP_DEV_DRIVE_STR(ap, dev) DRIVE_##ap
#elif PIN_CFG_DEV
#define AP_DEV_DRIVE_STR(ap, dev) DRIVE_##dev
#endif
#if TARGET_HAS_BASEBAND
# define _IFF_BB(cfg) cfg
#else
# define _IFF_BB(cfg) CFG_DISABLED
#endif
#if PIN_CFG_AP
static const u_int32_t gpio_default_cfg_ap[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#elif PIN_CFG_DEV
static const u_int32_t gpio_default_cfg_dev[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#endif
/*
* config idx pad net notes
* ======== === ======== ================ ========================
*/
/* Port 0 */
CFG_IN, // 0: GPIO0 -> GPIO_BTN_HOME_L also connected to PMU
CFG_IN, // 1: GPIO1 -> GPIO_BTN_ONOFF_L also connected to PMU
_IFF_BB(CFG_IN | PULL_DOWN), // 2: GPIO2 -> GPIO_BB_HSIC_DEV_RDY baseband models only
CFG_IN | PULL_UP, // 3: GPIO3 -> GPIO_BTN_VOL_UP_L
CFG_IN | PULL_UP, // 4: GPIO4 -> GPIO_ALS_IRQ_L
CFG_OUT_0 | AP_DEV_DRIVE_STR(X2, X4), // 5: GPIO5 -> GPIO_BT_WAKE
_IFF_BB(CFG_OUT_0 | AP_DEV_DRIVE_STR(X2, X4)), // 6: GPIO6 -> GPIO_AP_MODEM_WAKE baseband models only
CFG_DISABLED | DRIVE_X2, // 7: GPIO7 -> BB_JTAG_TMS_RF
/* Port 1 */
_IFF_BB(CFG_IN | PULL_DOWN), // 8: GPIO10 -> GPIO_BB_RESET_DET_L baseband models only
CFG_IN | PULL_UP, // 9: GPIO11 -> GPIO_ACCEL_IRQ2_L
_IFF_BB(CFG_IN | PULL_DOWN), // 10: GPIO12 -> GPIO_BB_HSIC_RESUME baseband models only
CFG_OUT_0 | AP_DEV_DRIVE_STR(X2, X4), // 11: GPIO13 -> GPIO_WLAN_HSIC_HOST_RDY
CFG_IN | PULL_UP, // 12: GPIO14 -> GPIO_BTN_VOL_DOWN_L
_IFF_BB(CFG_IN), // 13: GPIO15 -> GPIO_BB_GSM_TXBURST baseband models only
CFG_RESERVED, // 14: (reserved)
CFG_RESERVED, // 15: (reserved)
/* Port 2 */
CFG_RESERVED, // 16: (reserved)
CFG_RESERVED, // 17: (reserved)
CFG_RESERVED, // 18: (reserved)
CFG_RESERVED, // 19: (reserved)
CFG_RESERVED, // 20: (reserved)
CFG_RESERVED, // 21: (reserved)
CFG_RESERVED, // 22: (reserved)
CFG_RESERVED, // 23: (reserved)
/* Port 3 */
CFG_RESERVED, // 24: (reserved)
CFG_RESERVED, // 25: (reserved)
CFG_RESERVED, // 26: (reserved)
CFG_RESERVED, // 27: (reserved)
CFG_RESERVED, // 28: (reserved)
CFG_RESERVED, // 29: (reserved)
CFG_RESERVED, // 30: (reserved)
CFG_RESERVED, // 31: (reserved)
/* Port 4 */
_IFF_BB(CFG_IN | DRIVE_X2), // 32: GPIO8 -> GPIO_BB_RST_L baseband models only
_IFF_BB(CFG_IN | AP_DEV_DRIVE_STR(X2, X4)), // 33: GPIO9 -> GPIO_BB_RADIO_ON baseband models only
CFG_DISABLED, // 34: EHCI_PORT_PWR0 -> GPIO_BRD_REV0
CFG_DISABLED, // 35: EHCI_PORT_PWR1 -> GPIO_BRD_REV1
CFG_DISABLED, // 36: EHCI_PORT_PWR2 -> GPIO_BRD_REV2
CFG_DISABLED, // 37: EHCI_PORT_PWR3 -> NC_EHCI_PORT_PWR3_AP
CFG_DISABLED, // 38: GPIO16 -> NC_GPIO_BOARD_ID_3
CFG_IN, // 39: GPIO17 -> PMU_GPIO_TS_INT
/* Port 5 */
CFG_DISABLED, // 40: GPIO18 -> GPIO_BOOT_CONFIG_0
_IFF_BB(CFG_IN | DRIVE_X2), // 41: GPIO19 -> GPIO_BB_GPS_SYNC baseband models only
_IFF_BB(CFG_IN | AP_DEV_DRIVE_STR(X2, X6)), // 42: UART1_TXD -> UART1_BB_TXD baseband models only
_IFF_BB(CFG_FUNC0), // 43: UART1_RXD -> UART1_BB_RXD baseband models only
_IFF_BB(CFG_IN | AP_DEV_DRIVE_STR(X2, X6)), // 44: UART1_RTSN -> UART1_BB_RTS_L baseband models only
_IFF_BB(CFG_FUNC0), // 45: UART1_CTSN -> UART1_BB_CTS_L baseband models only
CFG_DISABLED, // 46: FMI0_CEN3 -> NC_FMI0_CE3_L
CFG_DISABLED, // 47: FMI0_CEN2 -> NC_FMI0_CE2_L
/* Port 6 */
CFG_DISABLED, // 48: FMI0_CEN1 -> NC_FMI0_CE1_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 49: FMI0_CEN0 -> FMI0_CE0_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 50: FMI0_CLE -> FMI0_CLE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 51: FMI0_ALE -> FMI0_ALE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 52: FMI0_REN -> FMI0_RE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 53: FMI0_WEN -> FMI0_WE_L
CFG_DISABLED, // 54: FMI0_WENN -> NC_FMI0_RE
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 55: FMI0_IO7 -> FMI0_AD<7>
/* Port 7 */
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 56: FMI0_IO6 -> FMI0_AD<6>
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 57: FMI0_IO5 -> FMI0_AD<5>
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 58: FMI0_IO4 -> FMI0_AD<4>
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 59: FMI0_DQS -> FMI0_DQS
CFG_DISABLED, // 60: FMI0_DQSN -> NC_FMI0_DQSN
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 61: FMI0_IO3 -> FMI0_AD<3>
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 62: FMI0_IO2 -> FMI0_AD<2>
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 63: FMI0_IO1 -> FMI0_AD<1>
/* Port 8 */
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 64: FMI0_IO0 -> FMI0_AD<0>
CFG_DISABLED, // 65: FMI0_CEN7 -> NC_FMI0_CE7_L
CFG_DISABLED, // 66: FMI0_CEN6 -> NC_FMI0_CE6_L
CFG_DISABLED, // 67: FMI0_CEN5 -> NC_FMI0_CE5_L
CFG_DISABLED, // 68: FMI0_CEN4 -> NC_FMI0_CE4_L
CFG_DISABLED, // 69: FMI1_CEN3 -> NC_FMI1_CE3_L
CFG_DISABLED, // 70: FMI1_CEN2 -> NC_FMI1_CE2_L
CFG_DISABLED, // 71: FMI1_CEN1 -> NC_FMI1_CE1_L
/* Port 9 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 72: FMI1_CEN0 -> FMI1_CE0_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 73: FMI1_CLE -> FMI1_CLE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 74: FMI1_ALE -> FMI1_ALE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 75: FMI1_REN -> FMI1_RE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 76: FMI1_WEN -> FMI1_WE_L
CFG_DISABLED, // 77: FMI1_WENN ->
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 78: FMI1_IO7 -> FMI1_AD<7>
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 79: FMI1_IO6 -> FMI1_AD<6>
/* Port 10 */
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 80: FMI1_IO5 -> FMI1_AD<5>
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 81: FMI1_IO4 -> FMI1_AD<4>
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 82: FMI1_DQS -> FMI1_DQS
CFG_DISABLED, // 83: FMI1_DQSN -> FMI1_DQSN
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 84: FMI1_IO3 -> FMI1_AD<3>
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 85: FMI1_IO2 -> FMI1_AD<2>
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 86: FMI1_IO1 -> FMI1_AD<1>
CFG_FUNC0 | BUS_HOLD | DRIVE_X2 | SLOW_SLEW, // 87: FMI1_IO0 -> FMI1_AD<0>
/* Port 11 */
CFG_DISABLED, // 88: FMI1_CEN7 -> NC_FMI1_CE7_L
CFG_DISABLED, // 89: FMI1_CEN6 -> NC_FMI1_CE6_L
CFG_DISABLED, // 90: FMI1_CEN5 -> NC_FMI1_CE5_L
CFG_DISABLED, // 91: FMI1_CEN4 -> NC_FMI1_CE4_L
CFG_FUNC0 | AP_DEV_DRIVE_STR(X2, X6), // 92: UART2_TXD -> UART2_TS_ACC_TXD
CFG_FUNC0 | PULL_UP, // 93: UART2_RXD -> UART2_TS_ACC_RXD
CFG_DISABLED, // 94: UART2_RTSN -> NC_UART2_RTSN
CFG_DISABLED | DRIVE_X2, // 95: UART2_CTSN -> BB_JTAG_TCK_RF
/* Port 12 */
CFG_FUNC0 | AP_DEV_DRIVE_STR(X2, X6), // 96: UART3_TXD -> UART3_BT_TXD
CFG_FUNC0 | PULL_UP, // 97: UART3_RXD -> UART3_BT_RXD
CFG_OUT_1 | AP_DEV_DRIVE_STR(X2, X6), // 98: UART3_RTSN -> UART3_BT_RTS_L
CFG_FUNC0 | PULL_UP, // 99: UART3_CTSN -> UART3_BT_CTS_L
CFG_FUNC0 | AP_DEV_DRIVE_STR(X2, X6), // 100: UART4_TXD -> UART4_WLAN_TXD
CFG_FUNC0 | PULL_UP, // 101: UART4_RXD -> UART4_WLAN_RXD
CFG_DISABLED, // 102: UART4_RTSN -> NC_UART4_RTS_L
CFG_DISABLED, // 103: UART4_CTSN -> NC_UART4_CTS_L
/* Port 13 */
CFG_FUNC0 | AP_DEV_DRIVE_STR(X2, X6), // 104: UART6_TXD -> UART6_AP_TXD
CFG_FUNC0 | PULL_UP, // 105: UART6_RXD -> UART6_AP_RXD
CFG_DISABLED, // 106: UART6_RTSN -> NC_UART6_RTSN
CFG_DISABLED, // 107: UART6_CTSN -> NC_UART6_CTSN
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 108: SPI1_SCLK -> SPI1_CODEC_SCLK
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 109: SPI1_MOSI -> SPI1_CODEC_MOSI
CFG_FUNC0, // 110: SPI1_MISO -> SPI1_CODEC_MISO
CFG_OUT_1 | AP_DEV_DRIVE_STR(X4, X6), // 111: SPI1_SSIN -> SPI1_CODEC_CS_L
/* Port 14 */
CFG_DISABLED, // 112: SPI0_SCLK -> GPIO_BOARD_ID_0
CFG_DISABLED, // 113: SPI0_MOSI -> GPIO_BOARD_ID_1
CFG_DISABLED, // 114: SPI0_MISO -> GPIO_BOARD_ID_2
CFG_DISABLED, // 115: SPI0_SSIN -> TP_SPI0_SSIN
CFG_DISABLED, // 116: SPI2_SCLK -> BB_JTAG_TDO_RF
CFG_DISABLED | DRIVE_X2, // 117: SPI2_MOSI -> BB_JTAG_TDI_RF
CFG_DISABLED | DRIVE_X2, // 118: SPI2_MISO -> BB_JTAG_TRST_RF_L
_IFF_BB(CFG_OUT_0 | AP_DEV_DRIVE_STR(X2, X4)), // 119: SPI2_SSIN -> GPIO_BB_HSIC_HOST_RDY baseband models only
/* Port 15 */
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 120: I2C0_SDA -> I2C0_SDA_1V8
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 121: I2C0_SCL -> I2C0_SCL_1V8
CFG_FUNC0 | AP_DEV_DRIVE_STR(X2, X6), // 122: I2C1_SDA -> I2C1_SDA_1V8
CFG_FUNC0 | AP_DEV_DRIVE_STR(X2, X6), // 123: I2C1_SCL -> I2C1_SCL_1V8
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 124: ISP0_SDA -> ISP0_CAM_RF_I2C_SDA
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 125: ISP0_SCL -> ISP0_CAM_RF_I2C_SCL
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 126: ISP1_SDA -> ISP1_CAM_FF_I2C_SDA
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 127: ISP1_SCL -> ISP1_CAM_FF_I2C_SCL
/* Port 16 */
CFG_DISABLED, // 128: MIPI_VSYNC -> NC_MIPI_VSYNC_H5
CFG_FUNC0 | PULL_DOWN, // 129: TMR32_PWM0 -> GPIO_GYRO_IRQ2
CFG_FUNC0 | PULL_UP, // 130: TMR32_PWM1 -> GPIO_ACCEL_IRQ1_L
CFG_DISABLED, // 131: TMR32_PWM2 -> NC_TMR32_PWM2_AP
CFG_DISABLED, // 132: SWI_DATA -> NC_SWI_AP
CFG_FUNC0 | PULL_DOWN, // 133: DWI_DI -> DWI_AP_DI
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 134: DWI_DO -> DWI_AP_DO
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 135: DWI_CLK -> DWI_AP_CLK
/* Port 17 */
CFG_OUT_1 | DRIVE_X2, // 136: SENSOR0_RST -> ISP0_CAM_RF_SHUTDOWN
CFG_OUT_0 | AP_DEV_DRIVE_STR(X4, X6), // 137: SENSOR0_CLK -> ISP0_CAM_RF_CLK_R
CFG_OUT_0 | PULL_DOWN | DRIVE_X2, // 138: SENSOR1_RST -> ISP1_CAM_FF_SHUTDOWN_L
CFG_OUT_0 | AP_DEV_DRIVE_STR(X4, X6), // 139: SENSOR1_CLK -> ISP1_CAM_FF_CLK_R
CFG_RESERVED, // 140: (reserved)
CFG_RESERVED, // 141: (reserved)
CFG_RESERVED, // 142: (reserved)
CFG_RESERVED, // 143: (reserved)
/* Port 18 */
CFG_RESERVED, // 144: (reserved)
CFG_RESERVED, // 145: (reserved)
CFG_RESERVED, // 146: (reserved)
CFG_RESERVED, // 147: (reserved)
CFG_RESERVED, // 148: (reserved)
CFG_RESERVED, // 149: (reserved)
CFG_RESERVED, // 150: (reserved)
CFG_RESERVED, // 151: (reserved)
/* Port 19 */
CFG_RESERVED, // 152: (reserved)
CFG_RESERVED, // 153: (reserved)
CFG_RESERVED, // 154: (reserved)
CFG_RESERVED, // 155: (reserved)
CFG_RESERVED, // 156: (reserved)
CFG_RESERVED, // 157: (reserved)
CFG_RESERVED, // 158: (reserved)
CFG_RESERVED, // 159: (reserved)
/* Port 20 */
CFG_FUNC0 | DRIVE_X4, // 160: CPU0_SWITCH -> CPU0_SWITCH
CFG_FUNC0 | DRIVE_X4, // 161: CPU1_SWITCH -> CPU1_SWITCH
CFG_DISABLED, // 162: ISP0_PRE_FLASH -> NC_ISP0_CAM_RF_FLASH
CFG_OUT_0 | DRIVE_X4, // 163: ISP0_FLASH -> ISP0_CAM_RF_RST_L
CFG_DISABLED | DRIVE_X4, // 164: ISP1_PRE_FLASH -> SOCHOT0_L
CFG_FUNC1 | DRIVE_X4, // 165: ISP1_FLASH -> SOCHOT1_L
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 166: I2S0_MCK -> I2S0_CODEC_ASP_MCK
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 167: I2S0_LRCK -> I2S0_CODEC_ASP_LRCK
/* Port 21 */
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 168: I2S0_BCLK -> I2S0_CODEC_ASP_BCLK
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 169: I2S0_DOUT -> I2S0_CODEC_ASP_DOUT
CFG_FUNC0, // 170: I2S0_DIN -> I2S0_CODEC_ASP_DIN
CFG_FUNC0 | DRIVE_X2, // 171: I2S1_MCK -> I2S1_SPKAMP_MCK
CFG_FUNC0 | DRIVE_X2, // 172: I2S1_LRCK -> I2S1_SPKAMP_LRCK
CFG_FUNC0 | DRIVE_X2, // 173: I2S1_BCLK -> I2S1_SPKAMP_BCLK
CFG_FUNC0 | DRIVE_X2, // 174: I2S1_DOUT -> I2S1_SPKAMP_DOUT
CFG_FUNC0, // 175: I2S1_DIN -> I2S1_SPKAMP_DIN
/* Port 22 */
CFG_DISABLED, // 176: I2S2_MCK -> NC_I2S2_MCK
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 177: I2S2_LRCK -> I2S2_BT_LRCK
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 178: I2S2_BCLK -> I2S2_BT_BCLK
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 179: I2S2_DOUT -> I2S2_BT_DOUT
CFG_FUNC0, // 180: I2S2_DIN -> I2S2_BT_DIN
CFG_DISABLED, // 181: I2S3_MCK -> NC_I2S3_MCK
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 182: I2S3_LRCK -> I2S3_CODEC_XSP_LRCK
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 183: I2S3_BCLK -> I2S3_CODEC_XSP_BCLK
/* Port 23 */
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 184: I2S3_DOUT -> I2S3_CODEC_XSP_DOUT
CFG_FUNC0, // 185: I2S3_DIN -> I2S3_CODEC_XSP_DIN
CFG_DISABLED, // 186: I2S4_MCK -> NC_I2S4_MCK
CFG_DISABLED, // 187: I2S4_LRCK -> NC_I2S4_LRCK
CFG_DISABLED, // 188: I2S4_BCLK -> NC_I2S4_BCLK
CFG_DISABLED, // 189: I2S4_DOUT -> NC_I2S4_DOUT
CFG_DISABLED, // 190: I2S4_DIN -> NC_I2S4_DIN
CFG_DISABLED, // 191: SPDIF -> NC_AP_GPIO216
/* Port 24 */
CFG_IN, // 192: GPIO20 -> GPIO_PROX_IRQ_L
CFG_IN | PULL_DOWN, // 193: GPIO21 -> GPIO_GYRO_IRQ1
CFG_OUT_0 | DRIVE_X2, // 194: GPIO22 -> GPIO_PMU_KEEPACT
CFG_IN | PULL_UP, // 195: GPIO23 -> GPIO_PMU_IRQ_L
CFG_IN | PULL_DOWN, // 196: GPIO24 -> GPIO_WLAN_HSIC_DEV_RDY
CFG_DISABLED, // 197: GPIO25 -> GPIO_BOOT_CONFIG_1
CFG_IN | PULL_DOWN, // 198: GPIO26 -> GPIO_FORCE_DFU
CFG_OUT_0 | PULL_DOWN | DRIVE_X1, // 199: GPIO27 -> GPIO_DFU_STATUS
/* Port 25 */
CFG_DISABLED, // 200: GPIO28 -> GPIO_BOOT_CONFIG_2
CFG_DISABLED, // 201: GPIO29 -> GPIO_BOOT_CONFIG_3
CFG_IN, // 202: GPIO30 -> GPIO_BTN_SRL_L a.k.a. ringer switch
CFG_IN | PULL_UP, // 203: GPIO31 -> GPIO_GRAPE_IRQ_L
CFG_IN | PULL_DOWN, // 204: GPIO32 -> GPIO_WL_HSIC_RESUME
CFG_OUT_0 | DRIVE_X2, // 205: GPIO33 -> GPIO_SPKAMP_RST_L
CFG_OUT_0 | DRIVE_X2, // 206: GPIO34 -> GPIO_SPKAMP_KEEPALIVE
CFG_IN | PULL_UP, // 207: GPIO35 -> GPIO_SPKAMP_RIGHT_IRQ_L
/* Port 26 */
CFG_OUT_0 | DRIVE_X2, // 208: GPIO36 -> PM_LCDVDD_PWREN
CFG_IN | PULL_UP, // 209: GPIO37 -> GPIO_SPKAMP_LEFT_IRQ_L
CFG_IN | PULL_UP, // 210: GPIO38 -> SPK_ID
CFG_IN | PULL_UP, // 211: GPIO39 -> GPIO_CODEC_IRQ_L
CFG_RESERVED, // 212: (reserved)
CFG_RESERVED, // 213: (reserved)
CFG_RESERVED, // 214: (reserved)
CFG_RESERVED, // 215: (reserved)
/* Port 27 */
CFG_RESERVED, // 216: (reserved)
CFG_RESERVED, // 217: (reserved)
CFG_RESERVED, // 218: (reserved)
CFG_RESERVED, // 219: (reserved)
CFG_RESERVED, // 220: (reserved)
CFG_RESERVED, // 221: (reserved)
CFG_RESERVED, // 222: (reserved)
CFG_RESERVED, // 223: (reserved)
/* Port 28 */
CFG_FUNC0 | DRIVE_X4, // 224: SPI3_MOSI -> SPI3_GRAPE_MOSI
CFG_FUNC0, // 225: SPI3_MISO -> SPI3_GRAPE_MISO
CFG_FUNC0 | DRIVE_X4, // 226: SPI3_SCLK -> SPI3_GRAPE_SCLK
CFG_OUT_1 | AP_DEV_DRIVE_STR(X4, X6), // 227: SPI3_SSIN -> SPI3_GRAPE_CS_L
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 228: I2C2_SDA -> I2C2_SDA_3V0
CFG_FUNC0 | AP_DEV_DRIVE_STR(X4, X6), // 229: I2C2_SCL -> I2C2_SCL_3V0
CFG_OUT_1 | DRIVE_X2, // 230: GPIO_3V0 -> GPIO_GRAPE_FW_DNLD_EN_L
CFG_OUT_0 | DRIVE_X2, // 231: GPIO_3V1 -> GPIO_GRAPE_RST_L
/* Port 29 */
CFG_DISABLED, // 232: DP_HPD -> NC_DP_HPD
CFG_FUNC0, // 233: EDP_HPD -> EDP_HPD
CFG_DISABLED, // 234: UART0_TXD -> NC_UART0_TXD
CFG_DISABLED, // 235: UART0_RXD -> NC_UART0_RXD
CFG_FUNC1 | AP_DEV_DRIVE_STR(X1, X6), // 236: UART5_RXD -> UART5_BATTERY_TRXD
CFG_DISABLED, // 237: UART5_TXD -> NC_UART5_TXD
CFG_DISABLED, // 238: TST_CLKOUT -> TP_AP_TST_CLKOUT
CFG_IN, // 239: TST_STPCLK -> AP_TST_STPCLK
/* Port 30 */
CFG_FUNC0 | DRIVE_X2, // 240: WDOG -> AP_WDOG
CFG_RESERVED, // 241: (reserved)
CFG_RESERVED, // 242: (reserved)
CFG_RESERVED, // 243: (reserved)
CFG_RESERVED, // 244: (reserved)
CFG_RESERVED, // 245: (reserved)
CFG_RESERVED, // 246: (reserved)
CFG_RESERVED, // 247: (reserved)
};
#undef AP_DEV_DRIVE_STR
#undef _IFF_BB
target/ipad3b/include/target/powerconfig.h
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/*
* Copyright (C) 2011-2012 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_POWERCONFIG_H
#define __TARGET_POWERCONFIG_H
#include <drivers/gasgauge.h>
/* configuration per target */
#define PMU_IIC_BUS 0
/* this configuration is very PMU specific and must be included exactly once in power.c */
#ifdef POWERCONFIG_PMU_SETUP
static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
{
{ PMU_IIC_BUS, kDIALOG_LDO_CONTROL, 0x00 }, // Force bypass off
{ PMU_IIC_BUS, kD2018_LDO1, 0x24 }, // PP3V0_GRAPE 3.00V
{ PMU_IIC_BUS, kD2018_LDO2, 0x2A }, // PP1V7_VA_VCP 1.70V
{ PMU_IIC_BUS, kD2018_LDO3, 0x0E }, // PP3V2_S2R_USBMUX 3.20V
{ PMU_IIC_BUS, kD2018_LDO4, 0x18 }, // PP3V0_SENSOR 3.00V
{ PMU_IIC_BUS, kD2018_LDO5, 0x1A }, // LDO5 3.00V
{ PMU_IIC_BUS, kD2018_LDO6, 0x10 }, // PP3V3_ACC 3.30V
{ PMU_IIC_BUS, kD2018_LDO7, 0x12 }, // PP3V0_S2R_TRISTAR 3.00V
{ PMU_IIC_BUS, kD2018_LDO8, 0x14 }, // PP3V0_S2R_HALL 3.00V
{ PMU_IIC_BUS, kD2018_LDO9, 0x12 }, // PP3V0_IO 3.00V
{ PMU_IIC_BUS, kD2018_LDO10, 0x0A }, // LDO10 3.00V
{ PMU_IIC_BUS, kD2018_LDO11, 0x16 }, // PP2V8_CAM 2.80V
{ PMU_IIC_BUS, kD2018_LDO12, 0x10 }, // PP1V0 1.00V
{ PMU_IIC_BUS, kDIALOG_LDO_CONTROL, 0x00 }, // Leave bypass off
};
static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
{
{ PMU_IIC_BUS, kD2018_ACTIVE1, 0x7F }, // Everything but LDO1
{ PMU_IIC_BUS, kD2018_ACTIVE2, 0xE7 }, // Everything but LDO5 and LDO6
{ PMU_IIC_BUS, kD2018_ACTIVE3, 0xC6 }, // LDO11, LDO12, LDO16, and CP
{ PMU_IIC_BUS, kD2018_ACTIVE4, 0xAC }, // CPU1V2 and CPU1V8, CPUA&CPUB switches
{ PMU_IIC_BUS, kD2018_ACTIVE5, 0x03 }, // WLEDA/B BST
{ PMU_IIC_BUS, kD2018_LCM_CONTROL1, 0x05 }, // unused 5.25
{ PMU_IIC_BUS, kD2018_LCM_CONTROL2, 0x05 }, // unused 5.25V
{ PMU_IIC_BUS, kD2018_LCM_CONTROL3, 0x00 }, // BB_VBUS_DET 5.00V
{ PMU_IIC_BUS, kD2018_LCM_BST_CONTROL, 0x14 }, // VBOOST_LCM 6.00V
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 1 },
{ PMU_IIC_BUS, kD2018_TRIM_CONF68, 0x1A }, // <rdar://problem/11840985> BUCK0-A, BUCK0-B = Forced Sync mode
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0 },
};
static const struct pmu_setup_struct pmu_warm_init[] =
{
{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2, 0x10 }, // HIB_32K on, DWI off
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_A, 0x00 },
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_B, 0x00 },
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_C, 0x00 },
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_D, 0x00 },
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_E, 0x00 },
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_F, 0x00 },
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_G, 0x00 },
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_H, 0x00 },
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_I, 0x00 },
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_J, 0x00 },
};
static const struct pmu_setup_struct pmu_cold_init[] =
{
/* GPIO configuration from I/O spreadsheet.
Request spreadsheet update before modifying
<rdar://problem/10363068> X140 IO Spreadsheet tracker
The following differences from OTP are intentional:
- GPIO6: Enable wake
- GPIO7: Enable wake
- GPIO8: Enable wake
- GPIO9: Enable wake
- GPIO10: Enable wake, any edge trigger
*/
{ PMU_IIC_BUS, kD2018_BUCK4, 0x98 }, // BUCK4 1.2V
{ PMU_IIC_BUS, kD2018_BUCK4_HIB, 0x98 }, // BUCK4_HIB 1.2V
{ PMU_IIC_BUS, kD2018_SYS_GPIO_1, 0x11 }, // PMU_GPIO_CLK_32K_GRAPE Out 0, Push-Pull, CPU_1V8
{ PMU_IIC_BUS, kD2018_SYS_GPIO_2, 0x49 }, // PMU_GPIO_CLK_32K_WLAN CLK32K, Push-Pull, VBUCK3
{ PMU_IIC_BUS, kD2018_SYS_GPIO_3, 0x09 }, // PMU_GPIO_BT_RST_L Out 0, Push-Pull, VBUCK3
{ PMU_IIC_BUS, kD2018_SYS_GPIO_4, 0x09 }, // PMU_GPIO_WLAN_RST_L Out 0, Push-Pull, VBUCK3
{ PMU_IIC_BUS, kD2018_SYS_GPIO_5, 0x09 }, // PMU_GPIO_BB_RST_L Out 0, Push-Pull, VBUCK3
{ PMU_IIC_BUS, kD2018_SYS_GPIO_6, 0xDA }, // PMU_GPIO_BATTERY_SWI In, F Edge, Wake, Pull Up, Disable Pull-Up
{ PMU_IIC_BUS, kD2018_SYS_GPIO_7, 0xBA }, // PMU_GPIO_BT_HOST_WAKE In, R Edge, Wake, Pull Down, Disable Pull-Up
{ PMU_IIC_BUS, kD2018_SYS_GPIO_8, 0xBA }, // PMU_GPIO_WLAN_HOST_WAKE In, R Edge, Wake, Pull Down, Disable Pull-Up
#if TARGET_HAS_BASEBAND
{ PMU_IIC_BUS, kD2018_SYS_GPIO_9, 0xBA }, // PMU_GPIO_BB_HOST_WAKE In, R Edge, Wake, No Pull Down, Disable Pull-Up
#else
{ PMU_IIC_BUS, kD2018_SYS_GPIO_9, 0xB9 }, // PMU_GPIO_BB_HOST_WAKE In, R Edge, No Wake, Pull Down, Disable Pull-Up
#endif
{ PMU_IIC_BUS, kD2018_SYS_GPIO_10, 0xEA }, // PMU_GPIO_CODEC_HS_INT_L In, Any Edge, Wake, Pull Down, Disable Pull-Up
{ PMU_IIC_BUS, kD2018_SYS_GPIO_11, 0xB9 }, // unused In, R Edge, No Wake, Pull Down, Disable Pull-Up
{ PMU_IIC_BUS, kD2018_SYS_GPIO_12, 0x7B }, // PMU_GPIO_TS_INT In, Hi level, Wake, Pull Down, Disable Pull-Up
{ PMU_IIC_BUS, kD2018_SYS_GPIO_13, 0xFA }, // PMU_GPIO_HALL_IRQ_1 In, Any Edge, Wake, Pull Up, Disable Pull-Up
{ PMU_IIC_BUS, kD2018_SYS_GPIO_14, 0xC8 }, // PMU_GPIO_CODEC_RST_L In, F Edge, No Wake, Pull Up, VBUCK3
{ PMU_IIC_BUS, kD2018_SYS_GPIO_15, 0xFA }, // PMU_GPIO_HALL_IRQ_2 In, Any Edge, Wake, Pull Up, Disable Pull-Up
{ PMU_IIC_BUS, kD2018_SYS_GPIO_16, 0xB9 }, // unused In, R Edge, No Wake, Pull Down, Disable Pull-Up
{ PMU_IIC_BUS, kD2018_SYS_GPIO_17, 0x01 }, // PMU_GPIO_BB_VBUS_DET Out 0, Push-Pull, VCC_MAIN
{ PMU_IIC_BUS, kD2018_SYS_GPIO_DEB1, 0x12 }, // 10ms debounce
{ PMU_IIC_BUS, kD2018_SYS_GPIO_DEB2, 0x12 }, // 10ms debounce
{ PMU_IIC_BUS, kD2018_SYS_GPIO_DEB3, 0x02 }, // no debounce on GPIO6
{ PMU_IIC_BUS, kD2018_SYS_GPIO_DEB4, 0x10 }, // no debounce on GPIO7
{ PMU_IIC_BUS, kD2018_SYS_GPIO_DEB5, 0x02 }, // no debounce on GPIO10
{ PMU_IIC_BUS, kD2018_SYS_GPIO_DEB6, 0x12 }, // 10ms debounce
{ PMU_IIC_BUS, kD2018_SYS_GPIO_DEB7, 0x12 }, // 10ms debounce
{ PMU_IIC_BUS, kD2018_SYS_GPIO_DEB8, 0x12 }, // 10ms debounce
{ PMU_IIC_BUS, kD2018_SYS_GPIO_DEB9, 0x12 }, // 10ms debounce
{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2, 0x11 }, // enable HIB_32kHz (for WIFI/BT) & DWI
{ PMU_IIC_BUS, kD2018_TDEV1_RISE, 0x04 }, // <rdar://problem/10657558> PMU support for SOCHOT1
{ PMU_IIC_BUS, kD2018_TDEV2_RISE, 0x04 } // <rdar://problem/10657558> PMU support for SOCHOT1
};
static const struct pmu_setup_struct pmu_cold_init_a0_samples[] =
{
// <rdar://problem/10608368> P102: WLED boost frequency incorrectly set to 2MHz in the initial A0 samples
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x03 }, // bank 3
{ PMU_IIC_BUS, 0xd2, 0x01 }, // testmode
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x01 }, // bank 1
{ PMU_IIC_BUS, 0xf1, 0x88 }, // WLED boost frequency 1 MHz
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x03 }, // bank 3
{ PMU_IIC_BUS, 0xd2, 0x00 }, // disable testmode
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x00 }, // bank 0
};
static const struct pmu_setup_struct pmu_backlight_enable[] =
{
{ PMU_IIC_BUS, kDIALOG_WLED_ISET, 0xD4 }, // 50% value from OS
{ PMU_IIC_BUS, kDIALOG_WLED_ISET2, 0x00 },
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, // enable all LED strings
(kDIALOG_WLED_CONTROL_WLED_ENABLE1 |
kDIALOG_WLED_CONTROL_WLED_ENABLE2 |
kDIALOG_WLED_CONTROL_WLED_ENABLE3 |
kDIALOG_WLED_CONTROL_WLED_ENABLE4 |
kDIALOG_WLED_CONTROL_WLED_ENABLE5 |
kDIALOG_WLED_CONTROL_WLED_ENABLE6) },
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL2, // enable LED Power
(kDIALOG_WLED_CONTROL2_WLED_RAMP_EN |
kDIALOG_WLED_CONTROL2_WLED_DITH_EN) }
};
static const struct pmu_setup_struct pmu_backlight_disable[] =
{
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, 0x0 } // disable LED power
};
static const struct core_rails_struct soc_rails[] =
{
{ PMU_IIC_BUS, 0, kDIALOG_BUCK2 }
};
static const struct core_rails_struct cpu_rails[] =
{
{ PMU_IIC_BUS, 0, kDIALOG_BUCK0 }
};
static const struct core_rails_struct ram_rails[] =
{
{ PMU_IIC_BUS, 0, kD2018_LDO16 }
};
#endif /* POWERCONFIG_PMU_SETUP */
#define TARGET_USE_CHARGE_TABLE 1
static const struct power_charge_limits pmu_charge_table[16] = { // gas gauge can have up to 16 entries
{ 4000, 1000, 1600, 3150 }, // 10 - 16C 0.27C
{ 4100, 1000, 1600, 2350 }, // 0.27C
{ USHRT_MAX, 1000, 1600, 1350 }, // 0.11C
{ 4000, 1500, 2100, 3150 }, // 15 - 21C 0.27C
{ 4100, 1500, 2100, 3150 }, // 0.27C
{ USHRT_MAX, 1500, 2100, 2350 }, // 0.2C
{ 4000, 2000, 3500, 3150 }, // 20 - 35C 0.27C
{ 4100, 2000, 3500, 3150 }, // 0.27C
{ USHRT_MAX, 2000, 3500, 3150 }, // 0.27C
{ 4000, 3400, 4500, 3150 }, // 34 - 45C 0.27C
{ 4100, 3400, 4500, 3150 }, // 0.27C
{ USHRT_MAX, 3400, 4500, 3150 }, // 0.27C
};
#define NO_BATTERY_VOLTAGE 2700
#define MIN_BOOT_BATTERY_VOLTAGE 3600
#define TARGET_BOOT_BATTERY_VOLTAGE 3700
#define TARGET_BOOT_BATTERY_CAPACITY 50
#define PRECHARGE_BACKLIGHT_LEVEL 1287 /* 10% brightness */
#define TARGET_PRECHARGE_ALWAYS_DISPLAY_IDLE 1
#define TARGET_MAX_USB_INPUT_CURRENT 2400
#define GASGAUGE_BATTERYID_BLOCK 1
#define GASGAUGE_CHARGETABLE_BLOCK 3
static const unsigned int atv_voltage_limit[16] = { 3600, 3650, 3700, 3750, 3800, 3850, 3900, 3950, 4000, 4050, 4100, 4150, 4200, 4250, 4300, 4350 };
static const unsigned int atv_current_limit[16] = { 150, 350, 550, 750, 950, 1150, 1350, 1550, 1750, 1950, 2150, 2350, 2550, 2750, 2950, 3150 };
#define ACC_PWR_LDO (6)
#endif
target/ipad3b/include/target/radioconfig.h
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/*
* Copyright (C) 2011 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_RADIOCONFIG_H
#define __TARGET_RADIOCONFIG_H
/* configuration per target */
// XXX config below remains as copied from
// '.../targets/ipad3/include/target/radioconfig';
// confirm settings remain appropriate for P101/P102/P103
#define RADIO_VERIFY_BASEBAND_EXISTS 1
static const gpio_t target_radio_quiesce_pins[] =
{
GPIO_UART1_TXD
};
#define RADIO_ENABLE_IMEI_OVERRIDE 0
#endif /* ! __TARGET_RADIOCONFIG_H */
target/ipad3b/include/target/uartconfig.h
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/*
* Copyright (C) 2011 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_UARTCONFIG_H
#define __TARGET_UARTCONFIG_H
/* define two debug serial ports */
#define DEBUG_SERIAL_PORT (6)
/* define radio serial port */
#define RADIO_SERIAL_PORT (1)
#define RADIO_MAX_READ_ERRORS (10)
/* define HDQ serial port */
#define HDQGAUGE_SERIAL_PORT (5)
#define UART_FLOWCONTROL_MASK (0x08)
#endif
target/ipad3b/init.c
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/*
* Copyright (C) 2011-2015 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <debug.h>
#include <drivers/display.h>
#include <drivers/flash_nor.h>
#include <drivers/iic.h>
#include <drivers/power.h>
#include <lib/devicetree.h>
#include <lib/env.h>
#include <lib/mib.h>
#include <lib/syscfg.h>
#include <platform.h>
#include <platform/gpio.h>
#include <platform/gpiodef.h>
#include <platform/memmap.h>
#include <sys.h>
#include <sys/boot.h>
#include <sys/menu.h>
#include <sys/task.h>
#include <target.h>
#include <target/powerconfig.h>
#define P101_PROTO0_BOARD (0)
#define P101_PROTO2_BOARD (1)
#define P101_EVT_BOARD (2)
static u_int32_t ipad3b_get_board_rev(void);
static void amelia_init();
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 90);
#if (APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC))
#include <drivers/displayport/displayport.h>
static dp_t dp;
#endif
void target_early_init(void)
{
}
void target_late_init(void)
{
if (target_config_ap()) {
// Deprecate Proto0/1
// Since board revs are shared between dev boards and enclosures,
// depreate only enclosures
if (ipad3b_get_board_rev() < P101_PROTO2_BOARD)
platform_not_supported();
}
}
void target_init(void)
{
// Cold-boot defaults for GPIOs where pinconfig.h differs,
// and it can't wait for the AppleARMFunction creation.
unsigned int i;
// <rdar://problem/11580048> P102 use 18.5mA for IRATE setting, not OTP value of 21mA
if (ipad3b_get_board_rev() <= P101_EVT_BOARD) {
const uint8_t pmu_data[] = {
0x23,0x03, // bank 3
0xd2,0x01, // enter test mode
0x23,0x01, // bank 1
0x89,0x21, // WLED_CTRL4 16kHz, 18.5mA
0x23,0x03, // bank 3
0xd2,0x00, // exit test mode
0x23,0x00 // bank 0
};
for (i = 0; i < sizeof(pmu_data); i += 2)
iic_write(0, 0x78, &pmu_data[i], 2);
}
// lower VDD_UNDER to 2.9V
{
uint8_t pmu_data[] = {
0x23,0x03, // bank 3
0xd2,0x01, // enter test mode
0x23,0x01, // bank 1
0xd5,0x00, // TRIM/CONF73
0x23,0x03, // bank 3
0xd2,0x00, // exit test mode
0x23,0x00 // bank 0
};
for (i = 0; i < sizeof(pmu_data); i += 2) {
if (i == 6) {
iic_read(0, 0x78, &pmu_data[i], 1, &pmu_data[i+1], 1, IIC_NORMAL);
pmu_data[i+1] = (pmu_data[i+1] & ~7) | 2; // VDD_FAULT = 2.9V
}
iic_write(0, 0x78, &pmu_data[i], 2);
}
}
#if WITH_HW_FLASH_NOR
flash_nor_init(SPI_NOR0);
#endif
}
void target_quiesce_hardware(void)
{
}
void target_poweroff(void)
{
}
int target_bootprep(enum boot_target target)
{
switch (target) {
case BOOT_DARWIN:
case BOOT_DARWIN_RESTORE:
case BOOT_DIAGS:
break;
default:
; // do nothing
}
return 0;
}
bool target_should_recover(void)
{
return platform_get_request_dfu2() && power_has_usb();
}
bool target_should_poweron(bool *cold_button_boot)
{
#if WITH_HW_POWER
if (power_get_boot_flag() == kPowerBootFlagColdButton) *cold_button_boot = true;
#else
*cold_button_boot = false;
#endif
return !*cold_button_boot || platform_get_request_dfu1();
}
bool target_should_poweroff(bool at_boot)
{
return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
}
#if APPLICATION_IBOOT
void target_watchdog_tickle(void)
{
u_int32_t value = gpio_read(GPIO_WDOG_TICKLE);
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
}
#endif // APPLICATION_IBOOT
void * target_get_display_configuration(void)
{
#if (APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC))
dp.mode = 0x1;
dp.type = 0x1;
dp.min_link_rate = 0x6;
dp.max_link_rate = 0x6;
dp.lanes = 0x4;
dp.ssc = 0x0;
dp.alpm = 0x0;
dp.vrr_enable = 0x0;
dp.vrr_on = 0x0;
return ((void *)(&dp));
#else
return NULL;
#endif
}
#if WITH_ENV
void target_setup_default_environment(void)
{
// XXX follow up on 'display-timing' below setting below
env_set("boot-device", "nand0", 0);
env_set("display-color-space","RGB888", 0);
env_set("display-timing", "ipad3", 0);
}
#endif
#if WITH_DEVICETREE
int target_update_device_tree(void)
{
DTNode *node;
#if WITH_HW_DISPLAY_EDP
DTNode *clcd_node = NULL, *backlight_node = NULL, *lcd_node = NULL;
#endif
uint32_t propSize, propCnt;
char *propName;
void *propData;
// Update the DWI node with the actual voltages
if (FindNode(0, "arm-io/dwi", &node)) {
propName = "voltages-buck0";
if (FindProperty(node, &propName, &propData, &propSize)) {
propCnt = propSize / sizeof(u_int32_t);
platform_get_cpu_voltages(propCnt, propData);
platform_convert_voltages(0, propCnt, propData);
}
propName = "voltages-buck2";
if (FindProperty(node, &propName, &propData, &propSize)) {
propCnt = propSize / sizeof(u_int32_t);
platform_get_soc_voltages(propCnt, propData);
platform_convert_voltages(2, propCnt, propData);
}
}
#if WITH_HW_DISPLAY_EDP
if (FindNode(0, DP_DTPATH, &node)) {
extern int edp_update_device_tree(DTNode *edp_node, DTNode *lcd_node, DTNode *clcd_node, DTNode *backlight_node);
FindNode(0, "arm-io/clcd", &clcd_node);
FindNode(0, DP_DTPATH "/lcd", &lcd_node);
FindNode(0, "backlight", &backlight_node);
edp_update_device_tree(node, lcd_node, clcd_node, backlight_node);
}
#endif
// Update the bottom prox calibration data
if (FindNode(0, "arm-io/i2c1/prox", &node)) {
propName = "prox-calibration-blob";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('CPCl', propData, propSize);
}
}
// Update the backlight calibration data
if (FindNode(0, "backlight", &node)) {
propName = "backlight-calibration";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('BLCl', propData, propSize);
}
}
// Update the compass calibration data
if (FindNode(0, "arm-io/i2c1/compass", &node)) {
propName = "compass-calibration";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('CPAS', propData, propSize);
}
}
// Update als node with calibration data
if (FindNode(0, "arm-io/i2c2/als", &node)) {
propName = "backlight-leakage-channel0";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('ALC0', propData, propSize);
}
propName = "backlight-leakage-channel1";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('ALC1', propData, propSize);
}
propName = "alsCalibration";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('AlsC', propData, propSize);
}
propName = "als-colorCfg";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('ClrC', propData, propSize);
}
}
// Update the gyro calibration data
if (FindNode(0, "arm-io/i2c2/gyro", &node)) {
propName = "low-temp-offset";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('LTGO', propData, propSize);
}
propName = "high-temp-offset";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('HTGO', propData, propSize);
}
propName = "gyro-sensitivity-calibration";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('GSCl', propData, propSize);
}
propName = "gyro-sens-matrix-inverse";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('GSCi', propData, propSize);
}
propName = "gyro-temp-table";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('GYTT', propData, propSize);
}
propName = "gyro-interrupt-calibration";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('GICl', propData, propSize);
}
}
// Update the gyro1 calibration data
if (FindNode(0, "arm-io/i2c2/gyro1", &node)) {
propName = "low-temp-offset";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('LTGO', propData, propSize);
}
propName = "high-temp-offset";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('HTGO', propData, propSize);
}
propName = "gyro-sensitivity-calibration";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('GSCl', propData, propSize);
}
propName = "gyro-sens-matrix-inverse";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('GSCi', propData, propSize);
}
propName = "gyro-temp-table";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('GYTT', propData, propSize);
}
propName = "gyro-interrupt-calibration";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('GICl', propData, propSize);
}
}
// Update accelerometer calibration data
if (FindNode(0, "arm-io/i2c2/accelerometer", &node)) {
propName = "low-temp-accel-offset";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('LTAO', propData, propSize);
}
propName = "accel-sensitivity-calibration";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('ASCl', propData, propSize);
}
}
// Update the speaker calibration data
if (FindNode(0, "arm-io/i2c0/audio-speaker0", &node)) {
propName = "speaker-rdc";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('SRdc', propData, propSize);
}
propName = "speaker-config";
if (FindProperty(node, &propName, &propData, &propSize)) {
uint8_t vpbr[2];
if (syscfgCopyDataForTag('VPBR', vpbr, sizeof(vpbr)) == 2) {
((uint8_t *)propData)[12] = (((uint8_t *)propData)[12] & ~0x1f) | ((vpbr[0] - 6) & 0x1f);
((uint8_t *)propData)[32] = (((uint8_t *)propData)[12] & ~0x1f) | ((vpbr[1] - 6) & 0x1f);
}
uint8_t vbst[2];
if (syscfgCopyDataForTag('VBST', vbst, sizeof(vbst)) == 2) {
((uint8_t *)propData)[16] = vbst[0];
((uint8_t *)propData)[36] = vbst[1];
}
}
}
// Update camera calibration data
if (FindNode(0, "arm-io/isp", &node)) {
propName = "camera-calibration";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('CmCl', propData, propSize);
}
}
// Dev1 audio config
if (target_config_dev()) {
if (ipad3b_get_board_rev() < P101_PROTO2_BOARD) {
// disable speaker nodes
if (FindNode(0, "arm-io/i2c0/audio-speaker0", &node)) {
propName = "reg";
if (FindProperty(node, &propName, &propData, &propSize)) {
strlcpy(propName, "AAPL,ignore", kPropNameLength);
}
}
if (FindNode(0, "arm-io/i2c0/audio-speaker1", &node)) {
propName = "reg";
if (FindProperty(node, &propName, &propData, &propSize)) {
strlcpy(propName, "AAPL,ignore", kPropNameLength);
}
}
// restore built-in speaker
if (FindNode(0, "arm-io/spi1/audio-codec", &node)) {
propName = "function-spkr_mute_xxx";
if (FindProperty(node, &propName, &propData, &propSize)) {
strlcpy(propName, "function-spkr_mute", kPropNameLength);
}
propName = "aout1-speaker_xxx";
if (FindProperty(node, &propName, &propData, &propSize)) {
strlcpy(propName, "aout1-speaker", kPropNameLength);
}
propName = "aout2-speaker_xxx";
if (FindProperty(node, &propName, &propData, &propSize)) {
strlcpy(propName, "aout2-speaker", kPropNameLength);
}
}
}
}
return 0;
}
#endif
static u_int32_t ipad3b_get_board_rev(void)
{
u_int32_t gpio_board_rev;
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PUP);
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PUP);
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PUP);
spin(100); // Wait 100us
gpio_board_rev =
(gpio_read(GPIO_BOARD_REV2) << 2) |
(gpio_read(GPIO_BOARD_REV1) << 1) |
(gpio_read(GPIO_BOARD_REV0) << 0);
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
return (gpio_board_rev & 0x7);
}
target/ipad3b/pinconfig.c
+29
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/*
* Copyright (C) 2009-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <drivers/apple/gpio.h>
#include <platform/soc/hwregbase.h>
#include <target.h>
#define PIN_CFG_AP 1
#include <target/pinconfig.h>
#undef PIN_CFG_AP
#define PIN_CFG_DEV 1
#include <target/pinconfig.h>
#undef PIN_CFG_DEV
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
{
if (target_config_ap())
return gpio_default_cfg_ap;
else
return gpio_default_cfg_dev;
}
target/ipad3b/properties.c
+46
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/*
* Copyright (C) 2011-2012 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <debug.h>
#include <target.h>
#include <target/powerconfig.h>
#if WITH_DEVICETREE
bool
target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
{
int length = 0;
bool result = false;
if ((result = target_get_property_base(prop, data, maxdata, retlen)) == false) {
switch(prop) {
case TARGET_PROPERTY_RESTORE_BACKLIGHT_LEVEL:
// fix the restore backlight level at the precharge level,
// to make sure the backlight does not cause the battery to
// drain during restore
if (maxdata >= (ssize_t)sizeof(uint32_t)) {
result = true;
length = sizeof(uint32_t);
*(uint32_t *)data = PRECHARGE_BACKLIGHT_LEVEL;
}
break;
default:
break;
}
}
if (retlen != NULL) *retlen = length;
return result;
}
#endif
target/ipad3b/rules.mk
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# Copyright (C) 2011 Apple Inc. All rights reserved.
#
# This document is the property of Apple Inc.
# It is considered confidential and proprietary.
#
# This document may not be reproduced or transmitted in any form,
# in whole or in part, without the express written permission of
# Apple Inc.
#
LOCAL_DIR := $(GET_LOCAL_DIR)
TARGET_DIR := $(LOCAL_DIR)
OPTIONS += \
DIALOG_D2018=1 \
TARGET_BOOT_CPU_VOLTAGE=0 \
TARGET_BOOT_RAM_VOLTAGE=CHIPID_RAM_VOLTAGE_LOW \
TARGET_BOOT_SOC_VOLTAGE=CHIPID_SOC_VOLTAGE_MED \
TARGET_DWI_FREQUENCY=24000000 \
TARGET_DWI_TRANSFER_GAP_US=5 \
TARGET_USE_HSIC=1 \
TARGET_HAS_BASEBAND=$(TARGET_HAS_BASEBAND) \
AMC_NUM_CHANNELS=4 \
AMC_NUM_RANKS=1 \
AMC_CHANNEL_WIDTH=4 \
DP_DTPATH=\"arm-io/edp\" \
MULTITOUCH_DTPATH=\"arm-io/spi3/multi-touch\" \
WIFI_DTPATH=\"arm-io/usb-complex/usb-ehci0/wlan\" \
USBDEVICE_DTPATH=\"arm-io/usb0-complex/usb0-device\" \
DPTX_PLL_CTL_VALUE=0x14 \
DPTX_ANALOG_CTL_2_VALUE=0x0d \
DPTX_ANALOG_CTL_3_VALUE=0x60 \
DPTX_FINE_PRE_EMPHASIS_VOLTAGE_VALUE=2
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
ALL_OBJS += $(LOCAL_DIR)/init.o \
$(LOCAL_DIR)/pinconfig.o
ifneq ($(PRODUCT),LLB)
ALL_OBJS += \
$(LOCAL_DIR)/properties.o
endif