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@@ -0,0 +1,27 @@
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/*
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* Copyright (C) 2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
|
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* Apple Inc.
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*/
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#ifndef __TARGET_ADBE_SETTINGS_H
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#define __TARGET_ADBE_SETTINGS_H
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static struct adbe_v1_tuneable adbe_tuneables[] = {
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{
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.name = "default",
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.adbe0_vblank_pos_vbi_pulse = 0x0000,
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.adbe0_vblank_clk_gate_wakeup = 0x0000,
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.adbe0_vblank_clk_gate_idle = 0x0001,
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.adbe0_vblank_blk_idle_dpb = 0x0000,
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.adbe0_vblank_blk_idle_aap = 0x0000,
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.adbe0_tunable_mode_ctrl = (DBEMODECNTL_DYN_CLK_GATE_ENABLE | DBEMODECNTL_AFC_TEARDOWN_ENABLE | DBEMODECNTL_PMGR_CLK_GATE_ENABL| DBEMODECNTL_BLK_CLK_GATE_ENABLE),
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.adbe0_aap_support = 1,
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},
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};
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#endif
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@@ -0,0 +1,107 @@
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/*
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* Copyright (C) 2011-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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static const struct amc_param amc_params = {
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.flags = (FLAG_AMC_PARAM_BUSTAT23 | FLAG_AMC_PARAM_SLOW_BOOT | FLAG_AMC_PARAM_ZQCL),
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.tREFi = 0x5d,
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.longsrcnt = 0x2008,
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.srextrarefcnt = 0x00020000,
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.rdlat = 6,
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.wrlat = 3,
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.phyrdlat = 10,
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.phywrlat = 2,
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.pdn = 0x22000403,
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.read = 0x00000203,
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.bustat = 0x00222209,
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.bustat2 = 0x00222209,
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.derate = 0x2483135b,
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.mcphyupdate = 0x05030000,
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.autoref_params = 0x00000021,
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.pwrmngtparam_small = 0x00011000,
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.pwrmngtparam_guided = 0x01801000,
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.chnldec = 0x00050000,
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.aref_freq0 = 0x00000110,
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.schen_default = 0x00000110,
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.mr1 = 0x44,
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.mr2 = 0x1a,
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.mr3 = 0x01,
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.pwrmngten_default = 0x00100100,
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.mcphyupdate1 = 0x00000001,
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.odts = 0x190,
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.readleveling = 0x00000300,
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.offset_shift_hynix = 0,
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.offset_shift_elpida = 1,
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.offset_shift_elpida25nm = -2,
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.freq = {
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{ // 800MHz
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.cas = 0x00000308,
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.pch = 0x00030612,
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.act = 0x12040908,
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.autoref = 0x19350000,
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.selfref = 0x00039060,
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.modereg = 0x20250782,
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.mifcassch = 0x00000110,
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.arefparam = 0x0c022131,
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},
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{ // 400MHz
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.cas = 0x00000005,
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.pch = 0x00000009,
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.act = 0x09020505,
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.autoref = 0x0d1b0000,
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.selfref = 0x0001d000,
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.modereg = 0x00130000,
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.mifcassch = 0x00000000,
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.arefparam = 0x00000101,
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},
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{ // 200MHz
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.cas = 0x00000003,
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.pch = 0x00000005,
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.act = 0x08020303,
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.autoref = 0x070e0000,
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.selfref = 0x0000f000,
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.modereg = 0x000a0000,
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.mifcassch = 0x00000000,
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.arefparam = 0x00000101,
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},
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{ // 50MHz
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.cas = 0x00000003,
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.pch = 0x00000003,
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.act = 0x08020303,
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.autoref = 0x02040000,
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.selfref = 0x00004000,
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.modereg = 0x00030000,
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.mifcassch = 0x00000000,
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.arefparam = 0x00000101,
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}
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}
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};
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static const struct amc_tunable amc_tunables[] = {
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{ &rAMC_MCSARBCFG, 0x00000001 },
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{ &rAMC_OPIDLETMR, 0x00200000 },
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{ &rAMC_OPTMRADJPARAM, 0x20400064 },
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{ &rAMC_MIFACTSCH, 0x00000001 },
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{ &rAMC_MIFCASSCH_FREQ(0), 0x10000010 },
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{ &rAMC_PSQRQCTL0, 0xff010110 },
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{ &rAMC_PSQRQCTL1, 0x00001728 },
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{ &rAMC_PSQRQTIMER0, 0x00000040 },
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{ &rAMC_PSQRQTIMER1, 0x00000014 },
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{ &rAMC_PSQRQTIMER2, 0x00000040 },
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{ &rAMC_PSQRQBRST, 0x04100410 },
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{ &rAMC_PSQRQSCHCRD, 0x00101400 },
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{ &rAMC_PSQWQCTL0, 0x00010100 },
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{ &rAMC_PSQWQBRST, 0x04100410 },
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{ &rAMC_PSQWQSCHCRD, 0x00101400 },
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{ &rAMC_MCUQOS, 0x00001919 },
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{ &rAMC_MCUQOSLLT, 0x0000011f },
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};
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ASPNANDCONFIG_H
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#define __TARGET_ASPNANDCONFIG_H
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//MLC devices
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#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 4
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#define ASPNAND_ERASE_DIES_IN_PARALLEL 8
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#define ASPNAND_READ_DIES_IN_PARALLEL 8
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#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
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//TLC devices
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#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
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// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
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#define ASPNAND_INDIRECTION_MEMORY (4*1024*1024)
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#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
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#endif
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@@ -0,0 +1,37 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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||||
* It is considered confidential and proprietary.
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||||
*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* iPad4,x specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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#define GPIO_LCD_PWR_EN GPIO( 2, 7)
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#define GPIO_RINGER_AB GPIO(13, 6)
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/* Board Revision */
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#define GPIO_BOARD_REV0 GPIO(14, 6)
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#define GPIO_BOARD_REV1 GPIO(14, 5)
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#define GPIO_BOARD_REV2 GPIO(14, 4)
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#define GPIO_BOARD_REV3 GPIO(14, 3)
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/* which IICs to initialize */
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#define IICS_MASK (0x5)
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#define TRISTAR_IIC_BUS (2)
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/* D2089 watchdog tickle, 'KEEPACT' */
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#define GPIO_WDOG_TICKLE GPIO(12, 6)
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,787 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
|
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* in whole or in part, without the express written permission of
|
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* Apple Inc.
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*/
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/* THIS STRUCT IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
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I/O Spreadsheet version: rev 1.10
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I/O Spreadsheet tracker: <rdar://problem/12012942> J72 IO Spreadsheet
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*/
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/* Different drive strength for AP and DEV. */
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#if PIN_CFG_AP
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#define AP_DEV_DRIVE_STR(ap, dev) DRIVE_##ap
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#elif PIN_CFG_DEV
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#define AP_DEV_DRIVE_STR(ap, dev) DRIVE_##dev
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#endif
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#ifdef SUB_TARGET_J71
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#if PIN_CFG_AP
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static const u_int32_t gpio_default_cfg_ap[GPIO_GROUP_COUNT * GPIOPADPINS] = {
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#elif PIN_CFG_DEV
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static const u_int32_t gpio_default_cfg_dev[GPIO_GROUP_COUNT * GPIOPADPINS] = {
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#endif
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/* Port 0 */
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CFG_DISABLED, // 0 : TST_CLKOUT -> SOC_TST_CLKOUT
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CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 1 : WDOG -> WDOG_SOC
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CFG_IN, // 2 : GPIO[0] -> GPIO_BTN_HOME_L
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CFG_IN, // 3 : GPIO[1] -> GPIO_BTN_ONOFF_L
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CFG_IN | PULL_UP, // 4 : GPIO[2] -> GPIO_BTN_VOL_DOWN_L
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CFG_IN | PULL_UP, // 5 : GPIO[3] -> GPIO_BTN_VOL_UP_L
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CFG_IN | PULL_UP, // 6 : GPIO[4] -> GPIO_CAM_ALS2SOC_IRQ_L
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CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : GPIO[5] -> GPIO_BT_WAKE
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/* Port 1 */
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CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 8 : GPIO[6] -> GPIO_SOC2BB_WAKE_MODEM
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CFG_DISABLED, // 9 : GPIO[7] -> NC_GPIO7
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CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 10 : GPIO[8] -> GPIO_SOC2BB_RST_L
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CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 11 : GPIO[9] -> GPIO_SOC2BB_RADIO_ON_L
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CFG_DISABLED | PULL_DOWN, // 12 : GPIO[10] -> GPIO_BB2SOC_RESET_DET_L
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CFG_DISABLED, // 13 : GPIO[11] -> NC_GPIO11
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CFG_IN | DRIVE_X2 | SLOW_SLEW, // 14 : GPIO[12] -> GPIO_SOC2OSCAR_DBGEN
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CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 15 : GPIO[13] -> GPIO_SOC2GRAPE_RESET_L
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/* Port 2 */
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CFG_DISABLED, // 16 : GPIO[14] -> NC_GPIO14
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CFG_DISABLED, // 17 : GPIO[15] -> GPIO_BB2SOC_GSM_TXBURST
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CFG_DISABLED, // 18 : GPIO[16] -> GPIO_BOARD_ID_3
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CFG_IN, // 19 : GPIO[17] -> GPIO_TS2SOC2PMU_INT
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CFG_DISABLED, // 20 : GPIO[18] -> GPIO_BOOT_CONFIG_0
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CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 21 : GPIO[19] -> GPIO_BB2SOC_GPS_SYNC
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CFG_IN, // 22 : GPIO[20] -> GPIO_PROX2SOC_IRQ_L
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CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 23 : GPIO[21] -> GPIO_SOC2LCD_PWREN
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/* Port 3 */
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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/* Port 4 */
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CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 32 : UART1_TXD -> UART1_SOC2BT_TX
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CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 33 : UART1_RXD -> UART1_BT2SOC_TX
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CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 34 : UART1_RTSN -> UART1_SOC2BT_RTS_L
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CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 35 : UART1_CTSN -> UART1_BT2SOC_RTS_L
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CFG_IN | DRIVE_X2 | SLOW_SLEW, // 36 : UART2_TXD -> UART2_SOC2WLAN_TX
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CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 37 : UART2_RXD -> UART2_WLAN2SOC_TX
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CFG_DISABLED, // 38 : UART2_RTSN -> NC_GPIO_UART2_RTSN
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CFG_DISABLED, // 39 : UART2_CTSN -> NC_GPIO_UART2_CTSN
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/* Port 5 */
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CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 40 : UART3_TXD -> UART3_SOC2BB_TX
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CFG_DISABLED | SLOW_SLEW, // 41 : UART3_RXD -> UART3_BB2SOC_TX
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CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 42 : UART3_RTSN -> UART3_SOC2BB_RTS_L
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CFG_DISABLED | SLOW_SLEW, // 43 : UART3_CTSN -> UART3_BB2SOC_RTS_L
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CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 44 : UART5_RTXD -> UART5_BATT_TRXD
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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/* Port 6 */
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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/* Port 7 */
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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/* Port 8 */
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CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 64 : UART4_TXD -> UART4_SOC2OSCAR_TXD
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CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : UART4_RXD -> UART4_OSCAR2SOC_RXD
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CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 66 : UART4_RTSN -> GPIO_OSCAR_RESET_L
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CFG_IN, // 67 : UART4_CTSN -> PMU_GPIO_OSCAR2PMU_HOST_WAKE
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CFG_DISABLED, // 68 : SPI1_SCLK -> NC_SPI1_SCLK
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CFG_DISABLED, // 69 : SPI1_MOSI -> NC_SPI1_MOSI
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CFG_DISABLED, // 70 : SPI1_MISO -> NC_SPI1_MISO
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CFG_DISABLED, // 71 : SPI1_SSIN -> NC_SPI1_SSIN
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/* Port 9 */
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||||
CFG_DISABLED, // 72 : SPI0_SCLK -> GPIO_BOARD_ID_0
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CFG_DISABLED, // 73 : SPI0_MOSI -> GPIO_BOARD_ID_1
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CFG_DISABLED, // 74 : SPI0_MISO -> GPIO_BOARD_ID_2
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||||
CFG_DISABLED, // 75 : SPI0_SSIN -> NC_SPI0_SSIN
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||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 76 : SPI2_SCLK -> SPI2_GRAPE_SCLK
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CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 77 : SPI2_MOSI -> SPI2_GRAPE_MOSI
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CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 78 : SPI2_MISO -> SPI2_GRAPE_MISO
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CFG_OUT_1 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 79 : SPI2_SSIN -> SPI2_GRAPE_CS_L
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/* Port 10 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 80 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 81 : I2C0_SCL -> I2C0_SCL_1V8
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CFG_DISABLED, // 82 : I2C1_SDA -> I2C1_SOC2OSCAR_SWDIO_1V8
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CFG_DISABLED, // 83 : I2C1_SCL -> I2C1_SOC2OSCAR_SWDCLK_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 84 : ISP0_SDA -> ISP0_CAM_REAR_SDA
|
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CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 85 : ISP0_SCL -> ISP0_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 86 : ISP1_SDA -> ISP1_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 87 : ISP1_SCL -> ISP1_CAM_FRONT_SCL
|
||||
|
||||
/* Port 11 */
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 88 : SENSOR0_RST -> ISP0_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 89 : SENSOR0_CLK -> ISP0_CAM_REAR_CLK_R
|
||||
CFG_DISABLED, // 90 : SENSOR0_XSHUTDOWN -> NC_SENSOR0_XSHUTDOWN
|
||||
CFG_DISABLED, // 91 : SENSOR0_ISTRB -> BB_IPC_GPIO
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 92 : SENSOR1_RST -> ISP1_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 93 : SENSOR1_CLK -> ISP1_CAM_FRONT_CLK_R
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 94 : SENSOR1_XSHUTDOWN -> AUD_SPKRAMP_MUTE_L
|
||||
CFG_DISABLED, // 95 : SENSOR1_ISTRB -> NC_SENSOR1_ISTRB
|
||||
|
||||
/* Port 12 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 96 : SPI3_MOSI -> SPI3_CODEC_MOSI
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 97 : SPI3_MISO -> SPI3_CODEC_MISO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 98 : SPI3_SCLK -> SPI3_CODEC_SCLK
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 99 : SPI3_SSIN -> SPI3_CODEC_CS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 100 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 101 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 102 : GPIO[22] -> GPIO_SOC2PMU_KEEPACT
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_PMU2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_IN | PULL_UP, // 104 : GPIO[24] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CONFIG_1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_OUT_0 | SLOW_SLEW, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CONFIG_2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_BOOT_CONFIG_3
|
||||
CFG_IN, // 110 : GPIO[30] -> GPIO_BTN_SRL_L
|
||||
CFG_IN | PULL_UP, // 111 : GPIO[31] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : GPIO[32] -> NC_GPIO32
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 113 : GPIO[33] -> GPIO_HS3_SHUNT_EN
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 114 : GPIO[34] -> GPIO_HS4_SHUNT_EN
|
||||
CFG_DISABLED, // 115 : GPIO[35] -> GPIO_BRD_REV3
|
||||
CFG_DISABLED, // 116 : GPIO[36] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 117 : GPIO[37] -> GPIO_BRD_REV1
|
||||
CFG_DISABLED, // 118 : GPIO[38] -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 119 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 120 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | DRIVE_X2, // 121 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 122 : UART0_TXD -> UART0_SOC_TXD
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW, // 123 : UART0_RXD -> UART0_SOC_RXD
|
||||
CFG_FUNC0 | SLOW_SLEW, // 124 : DWI_DI -> SOC_TST_CPUSWITCH_OUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 125 : DWI_DO -> DWI_AP_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 126 : DWI_CLK -> DWI_AP_CLK
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 128 : I2S0_LRCK -> I2S0_CODEC_ASP_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 129 : I2S0_BCLK -> I2S0_CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 130 : I2S0_DOUT -> I2S0_CODEC_ASP_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 131 : I2S0_DIN -> I2S0_CODEC_ASP_DIN
|
||||
CFG_DISABLED, // 132 : I2S1_MCK -> NC_I2S1_MCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 133 : I2S1_LRCK -> I2S1_CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 134 : I2S1_BCLK -> I2S1_CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 135 : I2S1_DOUT -> I2S1_CODEC_XSP_DOUT
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 136 : I2S1_DIN -> I2S1_CODEC_XSP_DIN
|
||||
CFG_DISABLED, // 137 : I2S2_LRCK -> NC_I2S2_LRCK
|
||||
CFG_DISABLED, // 138 : I2S2_BCLK -> NC_I2S2_BCLK
|
||||
CFG_DISABLED, // 139 : I2S2_DOUT -> NC_I2S2_DOUT
|
||||
CFG_DISABLED, // 140 : I2S2_DIN -> NC_I2S2_DIN
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 141 : I2S3_MCK -> BB_JTAG_TRST_L
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 142 : I2S3_LRCK -> BB_JTAG_TDO
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 143 : I2S3_BCLK -> BB_JTAG_TDI
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 144 : I2S3_DOUT -> BB_JTAG_TMS
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S3_DIN -> BB_JTAG_TCK
|
||||
CFG_DISABLED, // 146 : I2S4_MCK -> NC_I2S4_MCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 147 : I2S4_LRCK -> I2S4_SOC2BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 148 : I2S4_BCLK -> I2S4_SOC2BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 149 : I2S4_DOUT -> I2S4_SOC2BT_DATA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 150 : I2S4_DIN -> I2S4_BT2SOC_DATA
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 160 : TMR32_PWM0 -> OSCAR_TIME_SYNC_HOST_INT
|
||||
CFG_DISABLED, // 161 : TMR32_PWM1 -> NC_TMR32_PWM1
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 162 : TMR32_PWM2 -> CLK_32K_SOC2CUMULUS
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 163 : SIO_7816UART0_SDA -> HSIC1_SOC2WLAN_HOST_RDY
|
||||
CFG_IN, // 164 : SIO_7816UART0_SCL -> HSIC1_WLAN2SOC_DEVICE_RDY
|
||||
CFG_IN | PULL_DOWN, // 165 : SIO_7816UART0_RST -> HSIC1_WLAN2SOC_REMOTE_WAKE
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 166 : SIO_7816UART1_SDA -> HSIC2_SOC2BB_HOST_RDY
|
||||
CFG_DISABLED | PULL_DOWN, // 167 : SIO_7816UART1_SCL -> HSIC2_BB2SOC_DEVICE_RDY
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED | PULL_DOWN, // 168 : SIO_7816UART1_RST -> HSIC2_BB2SOC_REMOTE_WAKE
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 169 : UART6_TXD -> UART6_TS_ACC_TXD
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 170 : UART6_RXD -> UART6_TS_ACC_RXD
|
||||
CFG_FUNC0 | FAST_SLEW, // 171 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | FAST_SLEW, // 172 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 24 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 192 : EDP_HPD -> EDP_HPD
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 193 : I2S0_MCK -> I2S0_CODEC_ASP_MCK
|
||||
CFG_DISABLED, // 194 : I2S2_MCK -> NC_I2S2_MCK
|
||||
};
|
||||
#endif /* SUB_TARGET_J71 */
|
||||
|
||||
#ifdef SUB_TARGET_J72
|
||||
#if PIN_CFG_AP
|
||||
static const u_int32_t gpio_default_cfg_ap[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
#elif PIN_CFG_DEV
|
||||
static const u_int32_t gpio_default_cfg_dev[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
#endif
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED, // 0 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 1 : WDOG -> WDOG_SOC
|
||||
CFG_IN, // 2 : GPIO[0] -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 3 : GPIO[1] -> GPIO_BTN_ONOFF_L
|
||||
CFG_IN | PULL_UP, // 4 : GPIO[2] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_IN | PULL_UP, // 5 : GPIO[3] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 6 : GPIO[4] -> GPIO_CAM_ALS2SOC_IRQ_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : GPIO[5] -> GPIO_BT_WAKE
|
||||
|
||||
/* Port 1 */
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 8 : GPIO[6] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_DISABLED, // 9 : GPIO[7] -> NC_GPIO7
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 10 : GPIO[8] -> GPIO_SOC2BB_RST_L
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 11 : GPIO[9] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_IN | PULL_DOWN, // 12 : GPIO[10] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_DISABLED, // 13 : GPIO[11] -> NC_GPIO11
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 14 : GPIO[12] -> GPIO_SOC2OSCAR_DBGEN
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 15 : GPIO[13] -> GPIO_SOC2GRAPE_RESET_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // 16 : GPIO[14] -> NC_GPIO14
|
||||
CFG_IN, // 17 : GPIO[15] -> GPIO_BB2SOC_GSM_TXBURST
|
||||
CFG_DISABLED, // 18 : GPIO[16] -> GPIO_BOARD_ID_3
|
||||
CFG_IN, // 19 : GPIO[17] -> GPIO_TS2SOC2PMU_INT
|
||||
CFG_DISABLED, // 20 : GPIO[18] -> GPIO_BOOT_CONFIG_0
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 21 : GPIO[19] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN, // 22 : GPIO[20] -> GPIO_PROX2SOC_IRQ_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 23 : GPIO[21] -> GPIO_SOC2LCD_PWREN
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 32 : UART1_TXD -> UART1_SOC2BT_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 33 : UART1_RXD -> UART1_BT2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 34 : UART1_RTSN -> UART1_SOC2BT_RTS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 35 : UART1_CTSN -> UART1_BT2SOC_RTS_L
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 36 : UART2_TXD -> UART2_SOC2WLAN_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 37 : UART2_RXD -> UART2_WLAN2SOC_TX
|
||||
CFG_DISABLED, // 38 : UART2_RTSN -> NC_GPIO_UART2_RTSN
|
||||
CFG_DISABLED, // 39 : UART2_CTSN -> NC_GPIO_UART2_CTSN
|
||||
|
||||
/* Port 5 */
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 40 : UART3_TXD -> UART3_SOC2BB_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : UART3_RXD -> UART3_BB2SOC_TX
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 42 : UART3_RTSN -> UART3_SOC2BB_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 43 : UART3_CTSN -> UART3_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 44 : UART5_RTXD -> UART5_BATT_TRXD
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 64 : UART4_TXD -> UART4_SOC2OSCAR_TXD
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : UART4_RXD -> UART4_OSCAR2SOC_RXD
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 66 : UART4_RTSN -> GPIO_OSCAR_RESET_L
|
||||
CFG_IN, // 67 : UART4_CTSN -> PMU_GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_DISABLED, // 68 : SPI1_SCLK -> NC_SPI1_SCLK
|
||||
CFG_DISABLED, // 69 : SPI1_MOSI -> NC_SPI1_MOSI
|
||||
CFG_DISABLED, // 70 : SPI1_MISO -> NC_SPI1_MISO
|
||||
CFG_DISABLED, // 71 : SPI1_SSIN -> NC_SPI1_SSIN
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // 72 : SPI0_SCLK -> GPIO_BOARD_ID_0
|
||||
CFG_DISABLED, // 73 : SPI0_MOSI -> GPIO_BOARD_ID_1
|
||||
CFG_DISABLED, // 74 : SPI0_MISO -> GPIO_BOARD_ID_2
|
||||
CFG_DISABLED, // 75 : SPI0_SSIN -> NC_SPI0_SSIN
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 76 : SPI2_SCLK -> SPI2_GRAPE_SCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 77 : SPI2_MOSI -> SPI2_GRAPE_MOSI
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 78 : SPI2_MISO -> SPI2_GRAPE_MISO
|
||||
CFG_OUT_1 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 79 : SPI2_SSIN -> SPI2_GRAPE_CS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 80 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 81 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_DISABLED, // 82 : I2C1_SDA -> I2C1_SOC2OSCAR_SWDIO_1V8
|
||||
CFG_DISABLED, // 83 : I2C1_SCL -> I2C1_SOC2OSCAR_SWDCLK_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 84 : ISP0_SDA -> ISP0_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 85 : ISP0_SCL -> ISP0_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 86 : ISP1_SDA -> ISP1_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 87 : ISP1_SCL -> ISP1_CAM_FRONT_SCL
|
||||
|
||||
/* Port 11 */
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 88 : SENSOR0_RST -> ISP0_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 89 : SENSOR0_CLK -> ISP0_CAM_REAR_CLK_R
|
||||
CFG_DISABLED, // 90 : SENSOR0_XSHUTDOWN -> NC_SENSOR0_XSHUTDOWN
|
||||
CFG_DISABLED, // 91 : SENSOR0_ISTRB -> BB_IPC_GPIO
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 92 : SENSOR1_RST -> ISP1_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 93 : SENSOR1_CLK -> ISP1_CAM_FRONT_CLK_R
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 94 : SENSOR1_XSHUTDOWN -> AUD_SPKRAMP_MUTE_L
|
||||
CFG_DISABLED, // 95 : SENSOR1_ISTRB -> NC_SENSOR1_ISTRB
|
||||
|
||||
/* Port 12 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 96 : SPI3_MOSI -> SPI3_CODEC_MOSI
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 97 : SPI3_MISO -> SPI3_CODEC_MISO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 98 : SPI3_SCLK -> SPI3_CODEC_SCLK
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 99 : SPI3_SSIN -> SPI3_CODEC_CS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 100 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 101 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 102 : GPIO[22] -> GPIO_SOC2PMU_KEEPACT
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_PMU2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_IN | PULL_UP, // 104 : GPIO[24] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CONFIG_1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_OUT_0 | SLOW_SLEW, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CONFIG_2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_BOOT_CONFIG_3
|
||||
CFG_IN, // 110 : GPIO[30] -> GPIO_BTN_SRL_L
|
||||
CFG_IN | PULL_UP, // 111 : GPIO[31] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : GPIO[32] -> NC_GPIO32
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 113 : GPIO[33] -> GPIO_HS3_SHUNT_EN
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 114 : GPIO[34] -> GPIO_HS4_SHUNT_EN
|
||||
CFG_DISABLED, // 115 : GPIO[35] -> GPIO_BRD_REV3
|
||||
CFG_DISABLED, // 116 : GPIO[36] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 117 : GPIO[37] -> GPIO_BRD_REV1
|
||||
CFG_DISABLED, // 118 : GPIO[38] -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 119 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 120 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | DRIVE_X2, // 121 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 122 : UART0_TXD -> UART0_SOC_TXD
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW, // 123 : UART0_RXD -> UART0_SOC_RXD
|
||||
CFG_FUNC0 | SLOW_SLEW, // 124 : DWI_DI -> SOC_TST_CPUSWITCH_OUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 125 : DWI_DO -> DWI_AP_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 126 : DWI_CLK -> DWI_AP_CLK
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 128 : I2S0_LRCK -> I2S0_CODEC_ASP_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 129 : I2S0_BCLK -> I2S0_CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 130 : I2S0_DOUT -> I2S0_CODEC_ASP_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 131 : I2S0_DIN -> I2S0_CODEC_ASP_DIN
|
||||
CFG_DISABLED, // 132 : I2S1_MCK -> NC_I2S1_MCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 133 : I2S1_LRCK -> I2S1_CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 134 : I2S1_BCLK -> I2S1_CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 135 : I2S1_DOUT -> I2S1_CODEC_XSP_DOUT
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 136 : I2S1_DIN -> I2S1_CODEC_XSP_DIN
|
||||
CFG_DISABLED, // 137 : I2S2_LRCK -> NC_I2S2_LRCK
|
||||
CFG_DISABLED, // 138 : I2S2_BCLK -> NC_I2S2_BCLK
|
||||
CFG_DISABLED, // 139 : I2S2_DOUT -> NC_I2S2_DOUT
|
||||
CFG_DISABLED, // 140 : I2S2_DIN -> NC_I2S2_DIN
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 141 : I2S3_MCK -> BB_JTAG_TRST_L
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 142 : I2S3_LRCK -> BB_JTAG_TDO
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 143 : I2S3_BCLK -> BB_JTAG_TDI
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 144 : I2S3_DOUT -> BB_JTAG_TMS
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S3_DIN -> BB_JTAG_TCK
|
||||
CFG_DISABLED, // 146 : I2S4_MCK -> NC_I2S4_MCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 147 : I2S4_LRCK -> I2S4_SOC2BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 148 : I2S4_BCLK -> I2S4_SOC2BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 149 : I2S4_DOUT -> I2S4_SOC2BT_DATA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 150 : I2S4_DIN -> I2S4_BT2SOC_DATA
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 160 : TMR32_PWM0 -> OSCAR_TIME_SYNC_HOST_INT
|
||||
CFG_DISABLED, // 161 : TMR32_PWM1 -> NC_TMR32_PWM1
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 162 : TMR32_PWM2 -> CLK_32K_SOC2CUMULUS
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 163 : SIO_7816UART0_SDA -> HSIC1_SOC2WLAN_HOST_RDY
|
||||
CFG_IN, // 164 : SIO_7816UART0_SCL -> HSIC1_WLAN2SOC_DEVICE_RDY
|
||||
CFG_IN | PULL_DOWN, // 165 : SIO_7816UART0_RST -> HSIC1_WLAN2SOC_REMOTE_WAKE
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 166 : SIO_7816UART1_SDA -> HSIC2_SOC2BB_HOST_RDY
|
||||
CFG_IN | PULL_DOWN, // 167 : SIO_7816UART1_SCL -> HSIC2_BB2SOC_DEVICE_RDY
|
||||
|
||||
/* Port 21 */
|
||||
CFG_IN | PULL_DOWN, // 168 : SIO_7816UART1_RST -> HSIC2_BB2SOC_REMOTE_WAKE
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 169 : UART6_TXD -> UART6_TS_ACC_TXD
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 170 : UART6_RXD -> UART6_TS_ACC_RXD
|
||||
CFG_FUNC0 | FAST_SLEW, // 171 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | FAST_SLEW, // 172 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 24 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 192 : EDP_HPD -> EDP_HPD
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 193 : I2S0_MCK -> I2S0_CODEC_ASP_MCK
|
||||
CFG_DISABLED, // 194 : I2S2_MCK -> NC_I2S2_MCK
|
||||
};
|
||||
#endif /* SUB_TARGET_J72 */
|
||||
|
||||
#ifdef SUB_TARGET_J73
|
||||
#if PIN_CFG_AP
|
||||
static const u_int32_t gpio_default_cfg_ap[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
#elif PIN_CFG_DEV
|
||||
static const u_int32_t gpio_default_cfg_dev[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
#endif
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED, // 0 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 1 : WDOG -> WDOG_SOC
|
||||
CFG_IN, // 2 : GPIO[0] -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 3 : GPIO[1] -> GPIO_BTN_ONOFF_L
|
||||
CFG_IN | PULL_UP, // 4 : GPIO[2] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_IN | PULL_UP, // 5 : GPIO[3] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 6 : GPIO[4] -> GPIO_CAM_ALS2SOC_IRQ_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : GPIO[5] -> GPIO_BT_WAKE
|
||||
|
||||
/* Port 1 */
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 8 : GPIO[6] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_DISABLED, // 9 : GPIO[7] -> NC_GPIO7
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 10 : GPIO[8] -> GPIO_SOC2BB_RST_L
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 11 : GPIO[9] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_IN | PULL_DOWN, // 12 : GPIO[10] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_DISABLED, // 13 : GPIO[11] -> NC_GPIO11
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 14 : GPIO[12] -> GPIO_SOC2OSCAR_DBGEN
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 15 : GPIO[13] -> GPIO_SOC2GRAPE_RESET_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // 16 : GPIO[14] -> NC_GPIO14
|
||||
CFG_IN, // 17 : GPIO[15] -> GPIO_BB2SOC_GSM_TXBURST
|
||||
CFG_DISABLED, // 18 : GPIO[16] -> GPIO_BOARD_ID_3
|
||||
CFG_IN, // 19 : GPIO[17] -> GPIO_TS2SOC2PMU_INT
|
||||
CFG_DISABLED, // 20 : GPIO[18] -> GPIO_BOOT_CONFIG_0
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 21 : GPIO[19] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN, // 22 : GPIO[20] -> GPIO_PROX2SOC_IRQ_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 23 : GPIO[21] -> GPIO_SOC2LCD_PWREN
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 32 : UART1_TXD -> UART1_SOC2BT_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 33 : UART1_RXD -> UART1_BT2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 34 : UART1_RTSN -> UART1_SOC2BT_RTS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 35 : UART1_CTSN -> UART1_BT2SOC_RTS_L
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 36 : UART2_TXD -> UART2_SOC2WLAN_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 37 : UART2_RXD -> UART2_WLAN2SOC_TX
|
||||
CFG_DISABLED, // 38 : UART2_RTSN -> NC_GPIO_UART2_RTSN
|
||||
CFG_DISABLED, // 39 : UART2_CTSN -> NC_GPIO_UART2_CTSN
|
||||
|
||||
/* Port 5 */
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 40 : UART3_TXD -> UART3_SOC2BB_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : UART3_RXD -> UART3_BB2SOC_TX
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 42 : UART3_RTSN -> UART3_SOC2BB_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 43 : UART3_CTSN -> UART3_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 44 : UART5_RTXD -> UART5_BATT_TRXD
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 64 : UART4_TXD -> UART4_SOC2OSCAR_TXD
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : UART4_RXD -> UART4_OSCAR2SOC_RXD
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 66 : UART4_RTSN -> GPIO_OSCAR_RESET_L
|
||||
CFG_IN, // 67 : UART4_CTSN -> PMU_GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_DISABLED, // 68 : SPI1_SCLK -> NC_SPI1_SCLK
|
||||
CFG_DISABLED, // 69 : SPI1_MOSI -> NC_SPI1_MOSI
|
||||
CFG_DISABLED, // 70 : SPI1_MISO -> NC_SPI1_MISO
|
||||
CFG_DISABLED, // 71 : SPI1_SSIN -> NC_SPI1_SSIN
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // 72 : SPI0_SCLK -> GPIO_BOARD_ID_0
|
||||
CFG_DISABLED, // 73 : SPI0_MOSI -> GPIO_BOARD_ID_1
|
||||
CFG_DISABLED, // 74 : SPI0_MISO -> GPIO_BOARD_ID_2
|
||||
CFG_DISABLED, // 75 : SPI0_SSIN -> NC_SPI0_SSIN
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 76 : SPI2_SCLK -> SPI2_GRAPE_SCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 77 : SPI2_MOSI -> SPI2_GRAPE_MOSI
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 78 : SPI2_MISO -> SPI2_GRAPE_MISO
|
||||
CFG_OUT_1 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 79 : SPI2_SSIN -> SPI2_GRAPE_CS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 80 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 81 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_DISABLED, // 82 : I2C1_SDA -> I2C1_SOC2OSCAR_SWDIO_1V8
|
||||
CFG_DISABLED, // 83 : I2C1_SCL -> I2C1_SOC2OSCAR_SWDCLK_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 84 : ISP0_SDA -> ISP0_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 85 : ISP0_SCL -> ISP0_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 86 : ISP1_SDA -> ISP1_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 87 : ISP1_SCL -> ISP1_CAM_FRONT_SCL
|
||||
|
||||
/* Port 11 */
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 88 : SENSOR0_RST -> ISP0_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 89 : SENSOR0_CLK -> ISP0_CAM_REAR_CLK_R
|
||||
CFG_DISABLED, // 90 : SENSOR0_XSHUTDOWN -> NC_SENSOR0_XSHUTDOWN
|
||||
CFG_DISABLED, // 91 : SENSOR0_ISTRB -> BB_IPC_GPIO
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 92 : SENSOR1_RST -> ISP1_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 93 : SENSOR1_CLK -> ISP1_CAM_FRONT_CLK_R
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 94 : SENSOR1_XSHUTDOWN -> AUD_SPKRAMP_MUTE_L
|
||||
CFG_DISABLED, // 95 : SENSOR1_ISTRB -> NC_SENSOR1_ISTRB
|
||||
|
||||
/* Port 12 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 96 : SPI3_MOSI -> SPI3_CODEC_MOSI
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 97 : SPI3_MISO -> SPI3_CODEC_MISO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 98 : SPI3_SCLK -> SPI3_CODEC_SCLK
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 99 : SPI3_SSIN -> SPI3_CODEC_CS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 100 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 101 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 102 : GPIO[22] -> GPIO_SOC2PMU_KEEPACT
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_PMU2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_IN | PULL_UP, // 104 : GPIO[24] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CONFIG_1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_OUT_0 | SLOW_SLEW, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CONFIG_2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_BOOT_CONFIG_3
|
||||
CFG_IN, // 110 : GPIO[30] -> GPIO_BTN_SRL_L
|
||||
CFG_IN | PULL_UP, // 111 : GPIO[31] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : GPIO[32] -> NC_GPIO32
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 113 : GPIO[33] -> GPIO_HS3_SHUNT_EN
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 114 : GPIO[34] -> GPIO_HS4_SHUNT_EN
|
||||
CFG_DISABLED, // 115 : GPIO[35] -> GPIO_BRD_REV3
|
||||
CFG_DISABLED, // 116 : GPIO[36] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 117 : GPIO[37] -> GPIO_BRD_REV1
|
||||
CFG_DISABLED, // 118 : GPIO[38] -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 119 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 120 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | DRIVE_X2, // 121 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 122 : UART0_TXD -> UART0_SOC_TXD
|
||||
CFG_FUNC0 | PULL_UP | SLOW_SLEW, // 123 : UART0_RXD -> UART0_SOC_RXD
|
||||
CFG_FUNC0 | SLOW_SLEW, // 124 : DWI_DI -> SOC_TST_CPUSWITCH_OUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 125 : DWI_DO -> DWI_AP_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 126 : DWI_CLK -> DWI_AP_CLK
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 128 : I2S0_LRCK -> I2S0_CODEC_ASP_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 129 : I2S0_BCLK -> I2S0_CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 130 : I2S0_DOUT -> I2S0_CODEC_ASP_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 131 : I2S0_DIN -> I2S0_CODEC_ASP_DIN
|
||||
CFG_DISABLED, // 132 : I2S1_MCK -> NC_I2S1_MCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 133 : I2S1_LRCK -> I2S1_CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 134 : I2S1_BCLK -> I2S1_CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 135 : I2S1_DOUT -> I2S1_CODEC_XSP_DOUT
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 136 : I2S1_DIN -> I2S1_CODEC_XSP_DIN
|
||||
CFG_DISABLED, // 137 : I2S2_LRCK -> NC_I2S2_LRCK
|
||||
CFG_DISABLED, // 138 : I2S2_BCLK -> NC_I2S2_BCLK
|
||||
CFG_DISABLED, // 139 : I2S2_DOUT -> NC_I2S2_DOUT
|
||||
CFG_DISABLED, // 140 : I2S2_DIN -> NC_I2S2_DIN
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 141 : I2S3_MCK -> BB_JTAG_TRST_L
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 142 : I2S3_LRCK -> BB_JTAG_TDO
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 143 : I2S3_BCLK -> BB_JTAG_TDI
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 144 : I2S3_DOUT -> BB_JTAG_TMS
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S3_DIN -> BB_JTAG_TCK
|
||||
CFG_DISABLED, // 146 : I2S4_MCK -> NC_I2S4_MCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 147 : I2S4_LRCK -> I2S4_SOC2BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 148 : I2S4_BCLK -> I2S4_SOC2BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 149 : I2S4_DOUT -> I2S4_SOC2BT_DATA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 150 : I2S4_DIN -> I2S4_BT2SOC_DATA
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 160 : TMR32_PWM0 -> OSCAR_TIME_SYNC_HOST_INT
|
||||
CFG_DISABLED, // 161 : TMR32_PWM1 -> NC_TMR32_PWM1
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 162 : TMR32_PWM2 -> CLK_32K_SOC2CUMULUS
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 163 : SIO_7816UART0_SDA -> HSIC1_SOC2WLAN_HOST_RDY
|
||||
CFG_IN, // 164 : SIO_7816UART0_SCL -> HSIC1_WLAN2SOC_DEVICE_RDY
|
||||
CFG_IN | PULL_DOWN, // 165 : SIO_7816UART0_RST -> HSIC1_WLAN2SOC_REMOTE_WAKE
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 166 : SIO_7816UART1_SDA -> HSIC2_SOC2BB_HOST_RDY
|
||||
CFG_IN | PULL_DOWN, // 167 : SIO_7816UART1_SCL -> HSIC2_BB2SOC_DEVICE_RDY
|
||||
|
||||
/* Port 21 */
|
||||
CFG_IN | PULL_DOWN, // 168 : SIO_7816UART1_RST -> HSIC2_BB2SOC_REMOTE_WAKE
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 169 : UART6_TXD -> UART6_TS_ACC_TXD
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 170 : UART6_RXD -> UART6_TS_ACC_RXD
|
||||
CFG_FUNC0 | FAST_SLEW, // 171 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | FAST_SLEW, // 172 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 24 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 192 : EDP_HPD -> EDP_HPD
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 193 : I2S0_MCK -> I2S0_CODEC_ASP_MCK
|
||||
CFG_DISABLED, // 194 : I2S2_MCK -> NC_I2S2_MCK
|
||||
};
|
||||
#endif /* SUB_TARGET_J73 */
|
||||
|
||||
#undef AP_DEV_DRIVE_STR
|
||||
@@ -0,0 +1,146 @@
|
||||
#ifndef __TARGET_POWERCONFIG_H
|
||||
#define __TARGET_POWERCONFIG_H
|
||||
|
||||
#include <drivers/gasgauge.h>
|
||||
|
||||
/* configuration per target */
|
||||
|
||||
#define PMU_IIC_BUS 0
|
||||
|
||||
/* this configuration is very PMU specific and must be included exactly once in power.c */
|
||||
#ifdef POWERCONFIG_PMU_SETUP
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
|
||||
{
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kD2089_ACTIVE2, 0x03 }, // WLEDA/B BST
|
||||
{ PMU_IIC_BUS, kD2089_HIBERNATE3, 0x88 }, // pp3v0_s2r_sensor (LDO3)
|
||||
{ PMU_IIC_BUS, kD2089_HIBERNATE6, 0x24 }, // pp1v8_s2r_sw3 (buck3_sw3) and pp1v2_s2r_sw2 (buck4_sw2)
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_warm_init[] =
|
||||
{
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_cold_init[] =
|
||||
{
|
||||
/* GPIO configuration from I/O spreadsheet.
|
||||
<rdar://problem/12012942> J72 IO Spreadsheet
|
||||
Request spreadsheet update before modifying
|
||||
|
||||
The following differences from OTP are intentional:
|
||||
- GPIO6: Enable wake
|
||||
- GPIO7: Enable wake
|
||||
- GPIO8: Enable wake
|
||||
- GPIO9: Enable wake (baseband targets)
|
||||
- GPIO10: Enable wake
|
||||
- GPIO11: Enable wake
|
||||
- GPIO12: Hi level interrupt, enable wake
|
||||
- GPIO16: Enable wake
|
||||
*/
|
||||
{ PMU_IIC_BUS, kD2089_GPIO1, 0x49 }, // PMU_GPIO_CLK_32K_OSCAR 32k, Push-Pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD2089_GPIO2, 0x49 }, // PMU_GPIO_CLK_32K_WLAN 32k, Push-Pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD2089_GPIO3, 0x09 }, // PMU_GPIO_BT_REG_ON Out 0, Push-Pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD2089_GPIO4, 0x09 }, // PMU_GPIO_WLAN_REG_ON Out 0, Push-Pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD2089_GPIO5, 0x09 }, // PMU_GPIO_PMU2BB_RST_L Out 0, Push-Pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD2089_GPIO6, 0xDA }, // UART5_BATT_TRXD In, F Edge, Wake, PD
|
||||
{ PMU_IIC_BUS, kD2089_GPIO7, 0xBA }, // PMU_GPIO_BT2PMU_HOST_WAKE In, R Edge, Wake, No PU
|
||||
{ PMU_IIC_BUS, kD2089_GPIO8, 0xBA }, // PMU_GPIO_WLAN2PMU_HOST_WAKE In, R Edge, Wake, No PU
|
||||
#if TARGET_HAS_BASEBAND
|
||||
{ PMU_IIC_BUS, kD2089_GPIO9, 0x7A }, // PMU_GPIO_BB2PMU_HOST_WAKE In, L High, Wake, No PU
|
||||
#else
|
||||
{ PMU_IIC_BUS, kD2089_GPIO9, 0xB9 }, // PMU_GPIO_BB2PMU_HOST_WAKE In, R Edge, No Wake, PD, No PU
|
||||
#endif
|
||||
{ PMU_IIC_BUS, kD2089_GPIO10, 0xEA }, // PMU_GPIO_CODEC_HS_INT_L In, Any Edge, Wake, PU, VBUCK3
|
||||
{ PMU_IIC_BUS, kD2089_GPIO11, 0xFA }, // PMU_GPIO_MB_HALL1_IRQ In, Any Edge, Wake, No PU
|
||||
{ PMU_IIC_BUS, kD2089_GPIO12, 0x7B }, // GPIO_TS2SOC2PMU_INT In, L High, Wake, PD, No PU
|
||||
{ PMU_IIC_BUS, kD2089_GPIO13, 0xF8 }, // PMU_GPIO_MB_HALL2_IRQ In, Any Edge, No PU
|
||||
{ PMU_IIC_BUS, kD2089_GPIO14, 0xC8 }, // PMU_GPIO_CODEC_RST_L In, F Edge, PU, VBUCK3
|
||||
{ PMU_IIC_BUS, kD2089_GPIO15, 0xB9 }, // GPIO_NAVAJO2SOC_INT In, R Edge, No Wake, PD, No PU
|
||||
{ PMU_IIC_BUS, kD2089_GPIO16, 0x7B }, // PMU_GPIO_OSCAR2PMU_HOST_WAKE In, L High, Wake, PD, No PU
|
||||
{ PMU_IIC_BUS, kD2089_GPIO17, 0x01 }, // PMU_GPIO_BB_VBUS_DET Out 0, Push-Pull, VCC_MAIN
|
||||
|
||||
{ PMU_IIC_BUS, kD2089_BUCK_DWI_CTRL0, 0x03 }, // enable DWI for BUCK0, BUCK1
|
||||
{ PMU_IIC_BUS, kD2089_ACT_TO_HIB_DLY, 0x03 }, // set ACT_TO_HIB_DLY to 3 (6ms)
|
||||
{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2, 0x11 }, // enable HIB_32kHz (for WIFI/BT) and DWI
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_backlight_enable[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_ISET, 0xD4 }, // 50% value from OS
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_ISET2, 0x00 },
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, // enable all LED strings
|
||||
(kDIALOG_WLED_CONTROL_WLED_ENABLE1 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE2 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE3 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE4 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE5 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE6) },
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_OPTIONS, // enable LED Power
|
||||
(kDIALOG_WLED_CONTROL2_WLED_RAMP_EN |
|
||||
kDIALOG_WLED_CONTROL2_WLED_DITH_EN) }
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_backlight_disable[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, 0x0 } // disable LED power
|
||||
};
|
||||
|
||||
static const struct core_rails_struct soc_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2089_BUCK2_VSEL }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct cpu_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2089_BUCK0_VSEL }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct ram_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2089_BUCK5_VSEL }
|
||||
};
|
||||
|
||||
#endif /* POWERCONFIG_PMU_SETUP */
|
||||
|
||||
#define TARGET_USE_CHARGE_TABLE 1
|
||||
static const struct power_charge_limits pmu_charge_table[16] = {
|
||||
{ 4000, 1000, 1600, 3150 }, // 10 - 16C
|
||||
{ 4100, 1000, 1600, 3150 },
|
||||
{ 4200, 1000, 1600, 3150 },
|
||||
{ USHRT_MAX, 1000, 1600, 2550 },
|
||||
{ 4000, 1500, 2100, 3150 }, // 15 - 21C
|
||||
{ 4100, 1500, 2100, 3150 },
|
||||
{ 4200, 1500, 2100, 3150 },
|
||||
{ USHRT_MAX, 1500, 2100, 2550 },
|
||||
{ 4000, 2000, 3500, 3150 }, // 20 - 35C
|
||||
{ 4100, 2000, 3500, 3150 },
|
||||
{ 4200, 2000, 3500, 3150 },
|
||||
{ USHRT_MAX, 2000, 3500, 3150 },
|
||||
{ 4000, 3400, 4500, 3150 }, // 34 - 45C
|
||||
{ 4100, 3400, 4500, 3150 },
|
||||
{ 4200, 3400, 4500, 3150 },
|
||||
{ USHRT_MAX, 3400, 4500, 3150 }
|
||||
};
|
||||
|
||||
#define NO_BATTERY_VOLTAGE 2700
|
||||
#define MIN_BOOT_BATTERY_VOLTAGE 3600
|
||||
#define TARGET_BOOT_BATTERY_VOLTAGE 3700
|
||||
#define TARGET_BOOT_BATTERY_CAPACITY 50
|
||||
#define PRECHARGE_BACKLIGHT_LEVEL 1287 /* 10% brightness */
|
||||
#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
|
||||
#define TARGET_PRECHARGE_ALWAYS_DISPLAY_IDLE 1
|
||||
#define TARGET_MAX_USB_INPUT_CURRENT 2400
|
||||
|
||||
#define GASGAUGE_BATTERYID_BLOCK 1
|
||||
#define GASGAUGE_CHARGETABLE_BLOCK 3
|
||||
|
||||
static const unsigned int atv_voltage_limit[16] = { 3600, 3650, 3700, 3750, 3800, 3850, 3900, 3950, 4000, 4050, 4100, 4150, 4200, 4250, 4300, 4350 };
|
||||
static const unsigned int atv_current_limit[16] = { 150, 350, 550, 750, 950, 1150, 1350, 1550, 1750, 1950, 2150, 2350, 2550, 2750, 2950, 3150 };
|
||||
|
||||
#define ACC_PWR_LDO (6)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2012, 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define one debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (0)
|
||||
|
||||
#define HDQGAUGE_SERIAL_PORT (5)
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define UART_OVERSAMPLE_OVERRIDE (11)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_USBCONFIG_H
|
||||
#define __TARGET_USBCONFIG_H
|
||||
|
||||
#ifdef USBPHY_OTGTUNE0
|
||||
|
||||
#undef USBPHY_OTGTUNE0
|
||||
#define USBPHY_OTGTUNE0 (0x3644D3F3)
|
||||
|
||||
#endif /* USBPHY_OTGTUNE0 */
|
||||
|
||||
#endif /* __TARGET_USBCONFIG_H */
|
||||
@@ -0,0 +1,387 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/display.h>
|
||||
#include <drivers/flash_nor.h>
|
||||
#include <drivers/iic.h>
|
||||
#include <drivers/power.h>
|
||||
#include <lib/devicetree.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <lib/syscfg.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <sys.h>
|
||||
#include <sys/boot.h>
|
||||
#include <sys/menu.h>
|
||||
#include <sys/task.h>
|
||||
#include <target.h>
|
||||
#include <platform/soc/display_color_manager_tables.h>
|
||||
|
||||
#define IPAD4_DEV1_PROTO0_BOARD (0x0)
|
||||
#define IPAD4_PROTO0_TS2_BOARD (0x1)
|
||||
#define IPAD4_PROTO1_TS2_BOARD (0x2)
|
||||
#define IPAD4_PROTO1_TS1_BOARD (0x3)
|
||||
#define IPAD4_PROTO2_BOARD (0x5)
|
||||
#define IPAD4_EVT1_BOARD (0x6)
|
||||
#define IPAD4_DVT_BOARD (0x7)
|
||||
|
||||
static bool gpio_board_rev_valid;
|
||||
static u_int32_t gpio_board_rev;
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
MIB_CONSTANT(kMIBTargetDisplayCMEngammaTablePtr, kOIDTypeStruct, (void *)linear_rgb_engamma_tables);
|
||||
MIB_CONSTANT(kMIBTargetDisplayCMEngammaTableCount, kOIDTypeUInt32, ARRAY_SIZE(linear_rgb_engamma_tables));
|
||||
MIB_CONSTANT(kMIBTargetDisplayCMDegammaTablePtr, kOIDTypeStruct, (void *)linear_rgb_degamma_tables);
|
||||
MIB_CONSTANT(kMIBTargetDisplayCMDegammaTableCount, kOIDTypeUInt32, ARRAY_SIZE(linear_rgb_degamma_tables));
|
||||
MIB_CONSTANT(kMIBTargetDisplayCMMatrixTablePtr, kOIDTypeStruct, (void *)linear_identity_matrix_tables);
|
||||
MIB_CONSTANT(kMIBTargetDisplayCMMatrixTableCount, kOIDTypeUInt32, ARRAY_SIZE(linear_identity_matrix_tables));
|
||||
|
||||
// Don't panic for these targets because of <rdar://problem/14236421>.
|
||||
MIB_CONSTANT(kMIBTargetPanicOnUnknownDclrVersion, kOIDTypeBoolean, false);
|
||||
#if (APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC))
|
||||
#include <drivers/displayport/displayport.h>
|
||||
static dp_t dp;
|
||||
#endif
|
||||
|
||||
static u_int32_t ipad4_get_board_rev(void)
|
||||
{
|
||||
|
||||
if (!gpio_board_rev_valid) {
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV3, GPIO_PUP);
|
||||
|
||||
spin(100); // Wait 100us
|
||||
|
||||
gpio_board_rev =
|
||||
(gpio_read(GPIO_BOARD_REV3) << 3) |
|
||||
(gpio_read(GPIO_BOARD_REV2) << 2) |
|
||||
(gpio_read(GPIO_BOARD_REV1) << 1) |
|
||||
(gpio_read(GPIO_BOARD_REV0) << 0);
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_DFLT);
|
||||
|
||||
gpio_board_rev_valid = true;
|
||||
}
|
||||
|
||||
return gpio_board_rev;
|
||||
}
|
||||
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
unsigned i;
|
||||
|
||||
// <rdar://problem/13712093> and <rdar://problem/13840183> J72 : Change LDO5 voltage for EVT build
|
||||
if (ipad4_get_board_rev() == IPAD4_EVT1_BOARD) {
|
||||
const uint8_t pmu_data[] = {
|
||||
0x03, 0x28, 0x47,
|
||||
};
|
||||
|
||||
for (i = 0; i < sizeof(pmu_data); i += 3)
|
||||
iic_write(0, 0x78, &pmu_data[i], 3);
|
||||
}
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return platform_get_request_dfu2() && power_has_usb();
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
#if WITH_HW_POWER
|
||||
if (power_get_boot_flag() == kPowerBootFlagColdButton) *cold_button_boot = true;
|
||||
#else
|
||||
*cold_button_boot = false;
|
||||
#endif // WITH_HW_POWER
|
||||
|
||||
return !*cold_button_boot || platform_get_request_dfu1();
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
u_int32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
void * target_get_display_configuration(void)
|
||||
{
|
||||
#if (APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC))
|
||||
dp.mode = 0x1;
|
||||
dp.type = 0x1;
|
||||
dp.min_link_rate = 0x6;
|
||||
dp.max_link_rate = 0x6;
|
||||
dp.lanes = 0x4;
|
||||
dp.ssc = 0x0;
|
||||
dp.alpm = 0x0;
|
||||
dp.vrr_enable = 0x0;
|
||||
dp.vrr_on = 0x0;
|
||||
return ((void *)(&dp));
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
env_set("boot-device", "asp_nand", 0);
|
||||
env_set("display-color-space","RGB888", 0);
|
||||
env_set("display-timing", "ipad4", 0);
|
||||
}
|
||||
|
||||
#endif // WITH_ENV
|
||||
|
||||
bool target_has_tristar2(void)
|
||||
{
|
||||
return ipad4_get_board_rev() != IPAD4_DEV1_PROTO0_BOARD && ipad4_get_board_rev() != IPAD4_PROTO1_TS1_BOARD;
|
||||
}
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
#if WITH_HW_DISPLAY_EDP
|
||||
DTNode *clcd_node = NULL, *backlight_node = NULL, *lcd_node = NULL;
|
||||
#endif
|
||||
DTNode *node;
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
#if WITH_HW_DISPLAY_EDP
|
||||
if (FindNode(0, DP_DTPATH, &node)) {
|
||||
extern int edp_update_device_tree(DTNode *edp_node, DTNode *lcd_node, DTNode *clcd_node, DTNode *backlight_node);
|
||||
FindNode(0, "arm-io/disp0", &clcd_node);
|
||||
FindNode(0, DP_DTPATH "/lcd", &lcd_node);
|
||||
FindNode(0, "backlight", &backlight_node);
|
||||
edp_update_device_tree(node, lcd_node, clcd_node, backlight_node);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Update the codec node with acoustic transducer scale data
|
||||
{
|
||||
uint8_t atscData[20];
|
||||
|
||||
if (syscfgCopyDataForTag('ATSc', atscData, sizeof(atscData)) > 0) {
|
||||
// Update codec
|
||||
if (FindNode(0, "arm-io/spi3/audio-codec", &node)) {
|
||||
propName = "at-scale-imic";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
memcpy(propData, &atscData[0], sizeof(uint32_t));
|
||||
}
|
||||
propName = "at-scale-smic";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
memcpy(propData, &atscData[4], sizeof(uint32_t));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Update the backlight calibration data
|
||||
if (FindNode(0, "backlight", &node)) {
|
||||
propName = "backlight-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('BLCl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the compass calibration data
|
||||
if (FindNode(0, "arm-io/uart4/oscar/compass", &node)) {
|
||||
propName = "compass-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('CPAS', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the gyro calibration data
|
||||
if (FindNode(0, "arm-io/uart4/oscar/gyro", &node)) {
|
||||
propName = "gyro-orientation";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GRot', propData, propSize);
|
||||
}
|
||||
propName = "gyro-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GSCl', propData, propSize);
|
||||
}
|
||||
propName = "gyro-temp-table";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GYTT', propData, propSize);
|
||||
}
|
||||
propName = "gyro-interrupt-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GICl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update accelerometer calibration data
|
||||
if (FindNode(0, "arm-io/uart4/oscar/accelerometer", &node)) {
|
||||
propName = "accel-orientation";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ARot', propData, propSize);
|
||||
}
|
||||
propName = "low-temp-accel-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LTAO', propData, propSize);
|
||||
}
|
||||
propName = "accel-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ASCl', propData, propSize);
|
||||
}
|
||||
propName = "accel-interrupt-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('AICl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
{
|
||||
char *prox_node_name = "arm-io/i2c3/prox-i2c3";
|
||||
char *als_node_name = "arm-io/i2c3/als-i2c3";
|
||||
|
||||
if (ipad4_get_board_rev() < IPAD4_DVT_BOARD) {
|
||||
prox_node_name = "arm-io/i2c0/prox-i2c0";
|
||||
als_node_name = "arm-io/i2c0/als-i2c0";
|
||||
}
|
||||
|
||||
// Update the bottom prox calibration data
|
||||
if (FindNode(0, prox_node_name, &node)) {
|
||||
propName = "AAPL,ignore";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
|
||||
propName = "prox-calibration-blob";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('CPCl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the als calibration data
|
||||
if (FindNode(0, als_node_name, &node)) {
|
||||
propName = "AAPL,ignore";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
|
||||
propName = "alsCalibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LSCI', propData, propSize);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// TriStar 1 on older systems
|
||||
if (!target_has_tristar2()) {
|
||||
if (FindNode(0, "arm-io/i2c2/tristar", &node)) {
|
||||
propName = "compatible";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
strlcpy(propData, "tristar,cbtl1608", kPropNameLength);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Update charger calibration data
|
||||
if (FindNode(0, "charger", &node)) {
|
||||
propName = "usb-input-limit-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('CBAT', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif // WITH_DEVICETREE
|
||||
|
||||
#if WITH_PAINT
|
||||
|
||||
// The default background is expected to to be black and the artwork is expected
|
||||
// to be white. This arrangement will be inverted depending upon the cover glass
|
||||
// color of the device.
|
||||
|
||||
// Sample DClr_override values for testing devices without DClr syscfg entries (enclosure/cover glass):
|
||||
// gray/black: setenv DClr_override 000200009B9899003C3B3B0000000000
|
||||
// silver/white: setenv DClr_override 00020000D8D9D700E3E4E10000000000
|
||||
|
||||
static color_policy_invert_t target_cover_glass_color_table[] = {
|
||||
{ RGB( 59, 59, 60), false }, // Black - black background, white logo
|
||||
{ RGB(225, 228, 227), true }, // White - white background, black logo
|
||||
};
|
||||
|
||||
color_policy_t *target_color_map_init(enum colorspace cs, color_policy_t *color_policy)
|
||||
{
|
||||
// Must have a color policy structure passed in.
|
||||
if (color_policy == NULL)
|
||||
goto fail;
|
||||
|
||||
// We only support the RGB888 colorspace.
|
||||
if (cs != CS_RGB888)
|
||||
goto fail;
|
||||
|
||||
color_policy->policy_type = COLOR_MAP_POLICY_INVERT;
|
||||
color_policy->color_table = (void *)target_cover_glass_color_table;
|
||||
color_policy->color_count = ARRAY_SIZE(target_cover_glass_color_table);
|
||||
color_policy->map_color = NULL; // Use standard remapper
|
||||
|
||||
return color_policy;
|
||||
|
||||
fail:
|
||||
return NULL;
|
||||
}
|
||||
#endif // WITH_PAINT
|
||||
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) 2009-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <target.h>
|
||||
|
||||
#define PIN_CFG_AP 1
|
||||
#include <target/pinconfig.h>
|
||||
#undef PIN_CFG_AP
|
||||
|
||||
#define PIN_CFG_DEV 1
|
||||
#include <target/pinconfig.h>
|
||||
#undef PIN_CFG_DEV
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
if (target_config_ap())
|
||||
return gpio_default_cfg_ap;
|
||||
else
|
||||
return gpio_default_cfg_dev;
|
||||
}
|
||||
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <target.h>
|
||||
#include <target/powerconfig.h>
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
bool
|
||||
target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
|
||||
{
|
||||
int length = 0;
|
||||
bool result = false;
|
||||
|
||||
if ((result = target_get_property_base(prop, data, maxdata, retlen)) == false) {
|
||||
switch(prop) {
|
||||
case TARGET_PROPERTY_RESTORE_BACKLIGHT_LEVEL:
|
||||
// fix the restore backlight level at the precharge level,
|
||||
// to make sure the backlight does not cause the battery to
|
||||
// drain during restore
|
||||
if (maxdata >= (ssize_t)sizeof(uint32_t)) {
|
||||
result = true;
|
||||
length = sizeof(uint32_t);
|
||||
*(uint32_t *)data = PRECHARGE_BACKLIGHT_LEVEL;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (retlen != NULL) *retlen = length;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,47 @@
|
||||
# Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2089=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_MED \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=0 \
|
||||
TARGET_HAS_BASEBAND=$(TARGET_HAS_BASEBAND) \
|
||||
TARGET_SPARE0_CLK_CFG=0x83000006 \
|
||||
TARGET_VID0_CLK_CFG=0x81000000 \
|
||||
DISPLAY_LANDSCAPE_IPAD_TUNABLES=1 \
|
||||
TARGET_ENABLE_CM=1 \
|
||||
TARGET_DDR_798M=1 \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
WITH_TARGET_AMC_PARAMS=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
TARGET_ADBE0_VBLANK_POSITION=0xF0000 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_GPU=1 \
|
||||
WITH_CPU_APSC=1 \
|
||||
BT_DTPATH=\"arm-io/uart1/bluetooth\" \
|
||||
DP_DTPATH=\"arm-io/displayport\" \
|
||||
MULTITOUCH_DTPATH=\"arm-io/spi2/multi-touch\" \
|
||||
WIFI_DTPATH=\"arm-io/usb-complex/usb-ehci0/wlan\" \
|
||||
WITH_TARGET_USB_CONFIG=1
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
|
||||
ifneq ($(PRODUCT),LLB)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/properties.o
|
||||
endif
|
||||
Reference in new issue
Block a user