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@@ -0,0 +1,30 @@
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/*
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* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ADBE_SETTINGS_H
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#define __TARGET_ADBE_SETTINGS_H
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static struct adbe_v2_tuneable adbe_tuneables[] = {
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{
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.name = "default",
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.adbe0_vblank_pos_vbi_pulse = 0x000e,
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.adbe0_vblank_clk_gate_wakeup = 0x000e,
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.adbe0_vblank_clk_gate_idle = 0x0000,
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.adbe0_vblank_busy_finish = 2,
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.adbe0_tunable_mode_ctrl = (DBEMODECNTL_DPB_BUSY_MASK | \
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DBEMODECNTL_PMGR_CLK_GATE_ENABLE | \
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DBEMODECNTL_DYN_CLK_GATE_ENABLE | \
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DBEMODECNTL_BLK_CLK_GATE_ENABLE),
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.adbe0_aap_support = 1,
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.adbe0_aap_format_control_reg1 = (AAP_FORMAT_CONTROL_REG1_AUTOPOS | AAP_FORMAT_CONTROL_REG1_RSVD(8) | AAP_FORMAT_CONTROL_REG1_VS_POL),
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},
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};
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#endif
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@@ -0,0 +1,103 @@
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/*
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* Copyright (C) 2014,2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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||||
*
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||||
* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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/* Memory settings taken from j42d (2 GB), SEG signed off that they are the same (800MHz vs 792MHz) */
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static const struct amc_param amc_params = {
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.lat = 0x00060300,
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.phyrdwrtim = 0x00020a04,
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.tREFi = 0x5d,
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.pdn = 0x22000403,
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.derate = 0x24831359,
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.read = 0x00000203,
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.bustat = 0x00222209,
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.bustat2 = 0x00222209,
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.pwrmngten_default = 0x00100100,
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.schen_default = 0x00001110,
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.mcphyupdate = 0x15030000,
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.mcphyupdate1 = 0x00000003,
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.arefparam = 0x0ca2b532,
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.longsr = 0x05022008,
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.mr1 = 0x44,
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.mr2 = 0x1a,
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.mr3 = 0x03,
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.addrcfg = 0x00030201,
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.mccchnldec = 0x00060010,
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.mcuchnhash = 0x0ffffd54,
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.mcschnldec = 0x00010200,
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.qbrparam = 0x00050200,
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.odts = 0x00000320,
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.addrmapmode = 0x00000601,
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.readleveling = 0x00000300,
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.freq = {
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{ // 800MHz
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.cas = 0x00000308,
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.pch = 0x00030612,
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.act = 0x12040908,
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.autoref = 0x25550000,
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.selfref = 0x00059060,
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.modereg = 0x20250782,
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},
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{ // 400MHz
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.cas = 0x00000005,
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.pch = 0x00000009,
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.act = 0x09020505,
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.autoref = 0x132b0000,
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.selfref = 0x0002d000,
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.modereg = 0x00130000,
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},
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{ // 200MHz
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.cas = 0x00000003,
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.pch = 0x00000005,
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.act = 0x05010303,
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.autoref = 0x0a160000,
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.selfref = 0x00017000,
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.modereg = 0x000a0000,
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},
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{ // 50MHz
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.cas = 0x00000002,
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.pch = 0x00000002,
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.act = 0x04010202,
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.autoref = 0x03050000,
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.selfref = 0x00006000,
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.modereg = 0x00030000,
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}
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}
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};
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static const struct amc_tunable amc_tunables[] = {
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{ &rAMC_MCSARBCFG, 0x00000001 },
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{ &rAMC_OPIDLETMR, 0x00200000 },
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{ &rAMC_OPTMRADJPARAM, 0x20400064 },
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{ &rAMC_MIFACTSCH, 0x00000001 },
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{ &rAMC_MIFCASSCH_FREQ(0), 0x10000010 },
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{ &rAMC_PSQRQCTL0, 0xff010110 },
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{ &rAMC_PSQRQCTL1, 0x00001700 },
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{ &rAMC_PSQRQTIMER0, 0x00000040 },
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{ &rAMC_PSQRQTIMER1, 0x00000014 },
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{ &rAMC_PSQRQTIMER2, 0x00000040 },
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{ &rAMC_PSQRQBRST, 0x04100410 },
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{ &rAMC_PSQRQSCHCRD, 0x00101400 },
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{ &rAMC_PSQWQCTL0, 0x00010100 },
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#if DISPLAY_D600_TUNABLES
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{ &rAMC_PSQWQCTL1, 0x00000bd4 },
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#else
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{ &rAMC_PSQWQCTL1, 0x00000158 },
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#endif
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{ &rAMC_PSQWQBRST, 0x04080410 },
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{ &rAMC_PSQWQSCHCRD, 0x00101400 },
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{ &rAMC_MCUQOSLLT, 0x0000011f },
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#if DISPLAY_D600_TUNABLES
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{ &rAMC_PWRMNGTPARAM, 0x0c003000 },
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#else
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{ &rAMC_PWRMNGTPARAM, 0x01803000 },
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#endif
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};
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ASPNANDCONFIG_H
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#define __TARGET_ASPNANDCONFIG_H
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//MLC devices
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#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
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#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 4
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#define ASPNAND_ERASE_DIES_IN_PARALLEL 8
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#define ASPNAND_READ_DIES_IN_PARALLEL 4
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#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
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//TLC devices
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#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 4
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#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 4
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#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
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// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
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#define ASPNAND_INDIRECTION_MEMORY (4*1024*1024)
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#define ASPNAND_LEGACY_INDIRECTION_MEMORY (4*1024*1024)
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#endif
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@@ -0,0 +1,19 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef TARGET_BOARDID_H
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#define TARGET_BOARDID_H
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#define TARGET_BOARD_ID_J96AP (8)
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#define TARGET_BOARD_ID_J96DEV (9)
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#define TARGET_BOARD_ID_J97AP (10)
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#define TARGET_BOARD_ID_J97DEV (11)
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#endif
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@@ -0,0 +1,41 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* ipad5,x specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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/* Board Revision */
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#define GPIO_BOARD_REV0 GPIO( 14, 2) // 118 : GPIO[8]
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#define GPIO_BOARD_REV1 GPIO( 14, 3) // 117 : GPIO[9]
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#define GPIO_BOARD_REV2 GPIO( 14, 4) // 116 : GPIO[10]
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/* Miscellaneous Pins */
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#define GPIO_PMU_LCD_PWR_EN (17)
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/* Ringer Switch */
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#define GPIO_RINGER_AB GPIO( 5 , 7) // 131 : GPIO[4] -> gpio_btn_srl_l
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/* D2207 watchdog tickle, 'KEEPACT' */
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#define GPIO_WDOG_TICKLE GPIO( 6, 7) // 55 : GPIO[20] -> gpio_soc2pmu_keepact
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/* which IICs to initialize */
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#define IICS_MASK (0xD)
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#define TRISTAR_IIC_BUS (0)
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#define BACKLIGHT_IIC_BUS (0)
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,20 @@
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/*
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* Copyright (C) 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
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* Apple Inc.
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*/
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#ifndef LPDP_SETTINGS_H
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#define LPDP_SETTINGS_H
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static struct lpdp_port_calibration lpdp_port_calibration_table[1][1] = {
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{ {LPDP_PHY_LANE_VREG_ADJ_280_mV, 0}, },
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};
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#define LPDP_PORT_CALIBRATION_TABLE_FIXED (true)
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#endif
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@@ -0,0 +1,121 @@
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD2207_HIBERNATE6, 0x22 }, // DVDD must be on <rdar://problem/20080758>
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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};
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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/* <rdar://problem/14957338> J96-J97 IO spreadsheet tracker */
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#if TARGET_HAS_BASEBAND
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{ PMU_IIC_BUS, kD2207_GPIO5, 0x09}, // PMU_GPIO_PMU2BBPMU_RST_L Out 0, Push-Pull, VBUCK3
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#else
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{ PMU_IIC_BUS, kD2207_GPIO5, 0xB9}, // PMU_GPIO_PMU2BBPMU_RST_L In, R Edge, PD
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#endif
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{ PMU_IIC_BUS, kD2207_GPIO6, 0xDA}, // UART5_BATT_TRXD In, F Edge, Wake, PD
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{ PMU_IIC_BUS, kD2207_GPIO7, 0xBA}, // PMU_GPIO_BT_HOST_WAKE In, R Edge, Wake, PD
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{ PMU_IIC_BUS, kD2207_GPIO8, 0x7B}, // PMU_GPIO_WLAN_HOST_WAKE In, Hi level, Wake, PD
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#if TARGET_HAS_BASEBAND
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{ PMU_IIC_BUS, kD2207_GPIO9, 0x8A}, // PMU_GPIO_BB2PMU_HOST_WAKE In, Active low, Wake, PU, VBUCK3
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#else
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{ PMU_IIC_BUS, kD2207_GPIO9, 0xB9}, // PMU_GPIO_BB2PMU_HOST_WAKE In, R Edge, PD
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#endif
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{ PMU_IIC_BUS, kD2207_GPIO10, 0xEA}, // PMU_GPIO_CODEC_HS_INT_L In, Any Edge, Wake, PU, VBUCK3
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{ PMU_IIC_BUS, kD2207_GPIO11, 0xFA}, // PMU_GPIO_MB_HALL0_IRQ In, Any Edge, Wake, No PU
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{ PMU_IIC_BUS, kD2207_GPIO12, 0x7B}, // GPIO_TS2SOC2PMU_INT In, Hi level, Wake, PD
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{ PMU_IIC_BUS, kD2207_GPIO13, 0xF8}, // PMU_GPIO_MB_HALL1_IRQ In, Any Edge, NoWake, No PU
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{ PMU_IIC_BUS, kD2207_GPIO14, 0xB8}, // PMU_GPIO_WLAN2PMU_PCIE_WAKE_L In, R Edge, PU
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{ PMU_IIC_BUS, kD2207_GPIO16, 0x7B}, // PMU_GPIO_OSCAR2PMU_HOST_WAKE In, Hi level, Wake, PD
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{ PMU_IIC_BUS, kD2207_GPIO21, 0xF8}, // PMU_GPIO_MB_HALL2_IRQ In, Any Edge, NoWake, No PU
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{ PMU_IIC_BUS, kD2207_BUCK_DWI_CTRL0, 0x23}, // enable DWI for BUCK0, BUCK1, BUCK5
|
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{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2, 0x11}, // DWI_EN HIB_32K (for WiFi/BT) <rdar://problem/16257601>
|
||||
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||||
{ PMU_IIC_BUS, kDIALOG_TEST_ACCESS, kDIALOG_TEST_ACCESS_ENA}, // enable TEST Access
|
||||
{ PMU_IIC_BUS, kD2207_PRE_UVLO_CONF, 0x06}, // SOCHOT0 save power in sleep, disable pull-up <rdar://21643083>
|
||||
{ PMU_IIC_BUS, kDIALOG_TEST_ACCESS, kDIALOG_TEST_ACCESS_DIS}, // disable TEST Access
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_backlight_enable[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_ISET, 0xD4 }, // 50% value from OS
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_ISET2, 0x00 },
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, // enable all LED strings
|
||||
(kDIALOG_WLED_CONTROL_WLED_ENABLE1 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE2 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE3 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE4 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE5 |
|
||||
kDIALOG_WLED_CONTROL_WLED_ENABLE6) },
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_OPTIONS, // enable LED Power
|
||||
(kDIALOG_WLED_CONTROL2_WLED_RAMP_EN |
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||||
kDIALOG_WLED_CONTROL2_WLED_DITH_EN) }
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_backlight_disable[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, 0x0 } // disable LED power
|
||||
};
|
||||
|
||||
static const struct core_rails_struct soc_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2207_BUCK5_VSEL }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct cpu_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2207_BUCK0_VSEL }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct ram_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD2207_BUCK2_VSEL }
|
||||
};
|
||||
|
||||
#define TARGET_USE_CHARGE_TABLE 1
|
||||
static const struct power_charge_limits pmu_charge_table[16] = {
|
||||
{ 4100, 1000, 1500, 1004 }, // 10 - 15C
|
||||
{ 4200, 1000, 1500, 1004 },
|
||||
{ USHRT_MAX, 1000, 1500, 1004 },
|
||||
{ 4100, 1500, 2000, 2509 }, // 15 - 20C
|
||||
{ 4200, 1500, 2000, 2007 },
|
||||
{ USHRT_MAX, 1500, 2000, 1004 },
|
||||
{ 4100, 2000, 4500, 2509 }, // 20 - 45C
|
||||
{ 4200, 2000, 4500, 2509 },
|
||||
{ USHRT_MAX, 2000, 4500, 2007 },
|
||||
};
|
||||
|
||||
#endif /* POWERCONFIG_PMU_SETUP */
|
||||
|
||||
#define NO_BATTERY_VOLTAGE 2700
|
||||
#define MIN_BOOT_BATTERY_VOLTAGE 3600
|
||||
#define TARGET_BOOT_BATTERY_VOLTAGE 3700
|
||||
#define TARGET_BOOT_BATTERY_CAPACITY 60
|
||||
#define PRECHARGE_BACKLIGHT_LEVEL 824
|
||||
#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
|
||||
#define TARGET_PRECHARGE_ALWAYS_DISPLAY_IDLE 1
|
||||
#define TARGET_MAX_USB_INPUT_CURRENT 2400
|
||||
|
||||
#define ACC_PWR_LDO (6)
|
||||
|
||||
#define GASGAUGE_BATTERYID_BLOCK 1
|
||||
// no charge table
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define one debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (0)
|
||||
|
||||
#define HDQGAUGE_SERIAL_PORT (5)
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define UART_OVERSAMPLE_OVERRIDE (11)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in new issue
Block a user