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@@ -0,0 +1,30 @@
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/*
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* Copyright (C) 2013-2104 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ADBE_SETTINGS_H
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#define __TARGET_ADBE_SETTINGS_H
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static struct adbe_v2_tuneable adbe_tuneables[] = {
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{
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.name = "default",
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.adbe0_vblank_pos_vbi_pulse = 0x0005,
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.adbe0_vblank_clk_gate_wakeup = 0x0005,
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.adbe0_vblank_clk_gate_idle = 0x0000,
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.adbe0_vblank_busy_finish = 2,
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.adbe0_tunable_mode_ctrl = (DBEMODECNTL_DPB_BUSY_MASK | \
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DBEMODECNTL_PMGR_CLK_GATE_ENABLE | \
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DBEMODECNTL_DYN_CLK_GATE_ENABLE | \
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DBEMODECNTL_BLK_CLK_GATE_ENABLE),
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.adbe0_aap_support = 1,
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.adbe0_aap_format_control_reg1 = (AAP_FORMAT_CONTROL_REG1_AUTOPOS | AAP_FORMAT_CONTROL_REG1_RSVD(8) | AAP_FORMAT_CONTROL_REG1_VS_POL),
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},
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};
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#endif
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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||||
* This document is the property of Apple Computer, Inc.
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||||
* It is considered confidential and proprietary.
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||||
*
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||||
* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ASPNANDCONFIG_H
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#define __TARGET_ASPNANDCONFIG_H
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//MLC devices
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#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
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#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 4
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#define ASPNAND_ERASE_DIES_IN_PARALLEL 8
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#define ASPNAND_READ_DIES_IN_PARALLEL 4
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#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
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//TLC devices
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#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 4
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#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 4
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#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
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// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
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#define ASPNAND_INDIRECTION_MEMORY (4*1024*1024)
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#define ASPNAND_LEGACY_INDIRECTION_MEMORY (4*1024*1024)
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#endif
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@@ -0,0 +1,19 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef TARGET_BOARDID_H
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#define TARGET_BOARDID_H
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#define TARGET_BOARD_ID_J81AP (6)
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#define TARGET_BOARD_ID_J81DEV (7)
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#define TARGET_BOARD_ID_J82AP (2)
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#define TARGET_BOARD_ID_J82DEV (3)
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#endif
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@@ -0,0 +1,37 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* ipad5,x specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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/* Board Revision */
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#define GPIO_BOARD_REV0 GPIO( 20, 1) // 161 : ULPI_NXT
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#define GPIO_BOARD_REV1 GPIO( 19, 7) // 159 : ULPI_DIR
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#define GPIO_BOARD_REV2 GPIO( 21, 0) // 168 : ULPI_DATA[2]
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#define GPIO_BOARD_REV3 GPIO( 20, 3) // 163 : ULPI_DATA[6]
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/* Miscellaneous Pins */
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#define GPIO_PMU_LCD_PWR_EN (17)
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/* D2207 watchdog tickle, 'KEEPACT' */
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#define GPIO_WDOG_TICKLE GPIO( 10, 7) // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
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/* which IICs to initialize */
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#define IICS_MASK (0xF)
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#define TRISTAR_IIC_BUS (0)
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,20 @@
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/*
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* Copyright (C) 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef LPDP_SETTINGS_H
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#define LPDP_SETTINGS_H
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static struct lpdp_port_calibration lpdp_port_calibration_table[1][1] = {
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{ {LPDP_PHY_LANE_VREG_ADJ_360_mV, 0}, },
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};
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#define LPDP_PORT_CALIBRATION_TABLE_FIXED (true)
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#endif
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@@ -0,0 +1,113 @@
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD2207_HIBERNATE3, 0xAA }, // enable LDO7 (Tristar), LDO5(Mesa) and LDO3(Sensors), LDO1(Hall) <rdar://16167964>
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{ PMU_IIC_BUS, kD2207_HIBERNATE6, 0x26 }, // enable BUCK4_SW2+BUCK3_SW3+BUCK3_SW2 (Oscar Rails, DVDD) in hibernate
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{ PMU_IIC_BUS, kD2207_ACTIVE2, 0x03 }, // WLEDA/WLEDB enable
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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};
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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/* <rdar://problem/14847504> J82 IO Spreadsheet */
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#ifndef TARGET_HAS_BASEBAND
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{ PMU_IIC_BUS, kD2207_GPIO5, 0xB9}, // GPIO_PMU2BBPMU_RESET_R_L In, R Edge, PD
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#endif
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{ PMU_IIC_BUS, kD2207_GPIO6, 0xDA}, // UART_BATT_HDQ In, F Edge, Wake, No PU
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{ PMU_IIC_BUS, kD2207_GPIO7, 0xBA}, // GPIO_BT2PMU_HOST_WAKE In, R Edge, Wake, No PU
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{ PMU_IIC_BUS, kD2207_GPIO8, 0x7B}, // GPIO_WLAN2PMU_HOST_WAKE In, Hi level, Wake, PD
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#ifdef TARGET_HAS_BASEBAND
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{ PMU_IIC_BUS, kD2207_GPIO9, 0x8A}, // GPIO_BB2PMU_HOST_WAKE_L In, Active low, Wake, PU, VBUCK3
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#else
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{ PMU_IIC_BUS, kD2207_GPIO9, 0xB9}, // GPIO_BB2PMU_HOST_WAKE_L In, R Edge, PD
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#endif
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{ PMU_IIC_BUS, kD2207_GPIO10, 0xEA}, // GPIO_CODEC2PMU_HS_IRQ_L In, Any Edge, Wake, PU, VBUCK3
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{ PMU_IIC_BUS, kD2207_GPIO11, 0xFA}, // GPIO_HALL2PMU_IRQ0 In, Any Edge, Wake, No PU
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{ PMU_IIC_BUS, kD2207_GPIO12, 0x7B}, // GPIO_TS2SOC2PMU_IRQ In, Hi level, Wake, PD
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{ PMU_IIC_BUS, kD2207_GPIO16, 0x7B}, // GPIO_OSCAR2PMU_HOST_WAKE In, Hi level, Wake, PD
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{ PMU_IIC_BUS, kD2207_BUCK_DWI_CTRL0, 0x23 }, // enable DWI for BUCK0, BUCK1, BUCK5 <rdar://16369016>
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{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2, 0x11 }, // DWI_EN HIB_32K (for WiFi/BT) <rdar://15647984>
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};
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static const struct pmu_setup_struct pmu_backlight_enable[] =
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{
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{ PMU_IIC_BUS, kDIALOG_WLED_ISET, 0xD4 }, // 50% value from OS
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{ PMU_IIC_BUS, kDIALOG_WLED_ISET2, 0x00 },
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{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, // enable all LED strings
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(kDIALOG_WLED_CONTROL_WLED_ENABLE1 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE2 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE3 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE4 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE5 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE6) },
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{ PMU_IIC_BUS, kDIALOG_WLED_OPTIONS, // enable LED Power
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(kDIALOG_WLED_CONTROL2_WLED_RAMP_EN |
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kDIALOG_WLED_CONTROL2_WLED_DITH_EN) }
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};
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static const struct pmu_setup_struct pmu_backlight_disable[] =
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{
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{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, 0x0 } // disable LED power
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};
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static const struct core_rails_struct soc_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2207_BUCK2_VSEL }
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};
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static const struct core_rails_struct cpu_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2207_BUCK0_VSEL }
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};
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static const struct core_rails_struct ram_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2207_BUCK5_VSEL }
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};
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#endif /* POWERCONFIG_PMU_SETUP */
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#define TARGET_USE_CHARGE_TABLE 1
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// Need this only once in lib/power/power.c
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#if POWERCONFIG_CHARGE_TABLE
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static const struct power_charge_limits pmu_charge_table[16] = {
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{ 4200, 1000, 1500, 1511 }, { USHRT_MAX, 1000, 1500, 756 }, // 10°C < T ≤ 15°C
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{ 4200, 1500, 2000, 3021 }, { USHRT_MAX, 1500, 2000, 2266 }, // 15°C < T ≤ 20°C
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{ 4200, 2000, 4500, 3021 }, { USHRT_MAX, 2000, 4500, 3021 }, // 20°C < T ≤ 45°C
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};
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#endif
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#define NO_BATTERY_VOLTAGE 2700
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#define MIN_BOOT_BATTERY_VOLTAGE 3600
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#define TARGET_BOOT_BATTERY_VOLTAGE 3700
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#define TARGET_BOOT_BATTERY_CAPACITY 50
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#define PRECHARGE_BACKLIGHT_LEVEL 824
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#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
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#define TARGET_PRECHARGE_ALWAYS_DISPLAY_IDLE 1
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#define TARGET_MAX_USB_INPUT_CURRENT 2400
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#define ACC_PWR_LDO (6)
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#define GASGAUGE_BATTERYID_BLOCK 1
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// NOTE: this product doesn't have a charge table
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#endif
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@@ -0,0 +1,23 @@
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/*
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* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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||||
*/
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#ifndef __TARGET_UARTCONFIG_H
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#define __TARGET_UARTCONFIG_H
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/* define one debug serial ports */
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#define DEBUG_SERIAL_PORT (0)
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#define HDQGAUGE_SERIAL_PORT (5)
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#if SUPPORT_FPGA
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#define UART_OVERSAMPLE_OVERRIDE (11)
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#endif
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#endif
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@@ -0,0 +1,522 @@
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/*
|
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* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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||||
*/
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#include <debug.h>
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#include <drivers/power.h>
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#include <drivers/iic.h>
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#include <lib/env.h>
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#include <lib/mib.h>
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#include <lib/syscfg.h>
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#include <platform.h>
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#include <platform/gpiodef.h>
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#include <platform/soc/chipid.h>
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#include <target.h>
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#include <drivers/display.h>
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#if (APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC))
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#include <drivers/displayport/displayport.h>
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#endif
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// Board ids
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#define J81_AP_BOARD_ID (0x6)
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#define J81_DEV_BOARD_ID (0x7)
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#define J82_AP_BOARD_ID (0x2)
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#define J82_DEV_BOARD_ID (0x3)
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// Board revs
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#define J81_DEV1_BOARD_REV (0x2)
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#define J81_PROTO2_BOARD_REV (0x4)
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#define J81_PREEVT_BOARD_REV (0x5)
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static uint32_t ipad5b_get_board_rev(void);
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typedef enum {
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DISPLAY_UNKNOWN = 0,
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DISPLAY_J72 = 2,
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DISPLAY_POR = 3,
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} ipad5b_display_t;
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static bool gpio_board_rev_valid;
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static uint32_t gpio_board_rev;
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static bool gpio_display_id_valid;
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static ipad5b_display_t display_panel;
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// Display panel id sense pins
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#define GPIO_DISPLAY_ID0 GPIO( 18, 1) // 145: I2S4_MCK -> GPIO_DISPLAY_ID0 (JA118)
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#define GPIO_DISPLAY_ID1 GPIO( 5, 3) // 43 : I2S1_MCK -> GPIO_DISPLAY_ID1 (JA119)
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MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
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||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
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||||
#if (APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC))
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||||
static dp_t dp;
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||||
#endif
|
||||
|
||||
void ipad5b_detect_display(void)
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||||
{
|
||||
/*-----------------------------
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||||
Display ID [1:0] = [GPIO43: GPIO145]
|
||||
|
||||
Display ID [1:0]
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||||
POR 0b11 (no jumpers stuffed)
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||||
J72 0b10 (JA118 stuffed)
|
||||
Unused 0b01 (JA119 stuffed)
|
||||
Unused 0b00 (both JA118 and JA119 stuffed)
|
||||
|
||||
S/W Read Flow
|
||||
1. Set GPIO as input
|
||||
2. Enable PU and disable PD
|
||||
3. Read
|
||||
------------------------------*/
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||||
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||||
static const char *display_panel_name[] = {
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[DISPLAY_UNKNOWN] = "Unknown",
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[DISPLAY_J72] = "J72",
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||||
[DISPLAY_POR] = "POR",
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||||
};
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||||
|
||||
gpio_configure(GPIO_DISPLAY_ID0, GPIO_CFG_IN);
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gpio_configure(GPIO_DISPLAY_ID1, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(GPIO_DISPLAY_ID0, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_DISPLAY_ID1, GPIO_PUP);
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||||
|
||||
spin(100); // Wait 100us
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||||
|
||||
display_panel = (gpio_read(GPIO_DISPLAY_ID1) << 1) | gpio_read(GPIO_DISPLAY_ID0);
|
||||
|
||||
dprintf(DEBUG_INFO, "Display panel = %s\n",
|
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display_panel_name[display_panel]);
|
||||
|
||||
gpio_configure(GPIO_DISPLAY_ID0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_DISPLAY_ID1, GPIO_CFG_DFLT);
|
||||
gpio_display_id_valid = true;
|
||||
}
|
||||
|
||||
static uint32_t ipad5b_get_board_rev(void)
|
||||
{
|
||||
if (!gpio_board_rev_valid) {
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV3, GPIO_PUP);
|
||||
|
||||
spin(100); // Wait 100us
|
||||
|
||||
gpio_board_rev =
|
||||
(gpio_read(GPIO_BOARD_REV3) << 3) |
|
||||
(gpio_read(GPIO_BOARD_REV2) << 2) |
|
||||
(gpio_read(GPIO_BOARD_REV1) << 1) |
|
||||
(gpio_read(GPIO_BOARD_REV0) << 0);
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_DFLT);
|
||||
|
||||
gpio_board_rev_valid = true;
|
||||
}
|
||||
|
||||
return gpio_board_rev;
|
||||
}
|
||||
|
||||
uint32_t target_get_display_panel_type(void)
|
||||
{
|
||||
if (!gpio_display_id_valid) {
|
||||
ipad5b_detect_display();
|
||||
}
|
||||
return display_panel;
|
||||
}
|
||||
|
||||
static void target_fixup_pmu(void)
|
||||
{
|
||||
#if WITH_HW_POWER
|
||||
int pmu_get_data(int dev, uint16_t reg, uint8_t *byte);
|
||||
int pmu_set_data(int dev, uint16_t reg, uint8_t byte, bool do_confirm);
|
||||
int rc;
|
||||
uint8_t trc;
|
||||
|
||||
rc=pmu_get_data(0, 0x0001, &trc);
|
||||
if ( rc<0 ) {
|
||||
dprintf(DEBUG_CRITICAL, "PMU: cannot read TRC (%d)\n", rc);
|
||||
} else if ( trc==0x6 || trc==0x7 ) {
|
||||
rc=pmu_set_data(0, 0x7000, 0x1d, 0); // test mode
|
||||
if ( rc<0 ) {
|
||||
dprintf(DEBUG_INFO, "PMU: cannot enter test mode (%d)\n", rc);
|
||||
} else {
|
||||
rc=pmu_set_data(0, 0x002A, 0x0B, 0);
|
||||
if ( rc<0 ) dprintf(DEBUG_INFO, "PMU: cannot change PRE_UVLO_ADJ (%d)\n", rc);
|
||||
|
||||
rc=pmu_set_data(0, 0x7000, 0x00, 0);
|
||||
if ( rc<0 ) panic("PMU: cannot exit test mode (%d)", rc);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
if (target_config_dev()) {
|
||||
// Read the panel id early
|
||||
target_get_display_panel_type();
|
||||
} else {
|
||||
if (ipad5b_get_board_rev() < J81_PROTO2_BOARD_REV) {
|
||||
platform_not_supported();
|
||||
}
|
||||
}
|
||||
#if PRODUCT_LLB || PRODUCT_IBSS
|
||||
pmgr_update_dvfm(platform_get_board_id(),ipad5b_get_board_rev());
|
||||
pmgr_update_gfx_states(platform_get_board_id(),ipad5b_get_board_rev());
|
||||
target_fixup_pmu();
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return platform_get_request_dfu2() && power_has_usb();
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
#if WITH_HW_POWER
|
||||
if (power_get_boot_flag() == kPowerBootFlagColdButton) *cold_button_boot = true;
|
||||
#else
|
||||
*cold_button_boot = false;
|
||||
#endif // WITH_HW_POWER
|
||||
|
||||
return !*cold_button_boot || platform_get_request_dfu1();
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
uint32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
void * target_get_display_configuration(void)
|
||||
{
|
||||
#if (APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC))
|
||||
dp.mode = 0x1;
|
||||
dp.type = 0x1;
|
||||
dp.min_link_rate = 0x6;
|
||||
dp.max_link_rate = 0x6;
|
||||
dp.lanes = 0x4;
|
||||
dp.ssc = 0x0;
|
||||
dp.alpm = 0x0;
|
||||
dp.vrr_enable = 0x0;
|
||||
dp.vrr_on = 0x0;
|
||||
dp.rx_n1= 0x0;
|
||||
dp.rx_n2= 0x0;
|
||||
dp.rx_n3= 0x0;
|
||||
dp.rx_n5= 0x0;
|
||||
dp.fast_link_training = true;
|
||||
return ((void *)(&dp));
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
// boot-device is set in platform's init.c
|
||||
env_set("display-color-space","RGB888", 0);
|
||||
env_set("display-timing", "ipad4", 0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
#if WITH_HW_DISPLAY_EDP
|
||||
DTNode *clcd_node = NULL, *backlight_node = NULL, *lcd_node = NULL;
|
||||
DTNode *lpdp_node = NULL;
|
||||
DTNode *node;
|
||||
#endif
|
||||
|
||||
uint32_t propSize;
|
||||
char *propName, *propNamePOR;
|
||||
void *propData;
|
||||
|
||||
#if WITH_HW_DISPLAY_EDP
|
||||
if (FindNode(0, DP_DTPATH, &node)) {
|
||||
extern int edp_update_device_tree(DTNode *edp_node, DTNode *lcd_node, DTNode *clcd_node, DTNode *backlight_node);
|
||||
FindNode(0, "arm-io/disp0", &clcd_node);
|
||||
FindNode(0, DP_DTPATH "/lcd", &lcd_node);
|
||||
FindNode(0, "backlight", &backlight_node);
|
||||
edp_update_device_tree(node, lcd_node, clcd_node, backlight_node);
|
||||
|
||||
extern int lpdp_phy_update_device_tree(DTNode *lpdp_node);
|
||||
FindNode(0, DPPHY_DTPATH, &lpdp_node);
|
||||
lpdp_phy_update_device_tree(lpdp_node);
|
||||
}
|
||||
#endif
|
||||
|
||||
if (target_config_dev()) {
|
||||
// multi-touch compatibilty to j72
|
||||
if (FindNode(0, MULTITOUCH_DTPATH, &node)) {
|
||||
propName = "compatible";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
memset(propData, 0, propSize);
|
||||
if (DISPLAY_J72 == target_get_display_panel_type()) {
|
||||
strlcpy(propData, "multi-touch,j72", propSize);
|
||||
} else {
|
||||
strlcpy(propData, "multi-touch,j82", propSize);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (ipad5b_get_board_rev() == J81_DEV1_BOARD_REV) {
|
||||
// mesa pwr hooked up differently on boards with revs earlier than 3
|
||||
if (FindNode(0, "arm-io/spi2/mesa", &node)) {
|
||||
propName = "function-mesa_pwr_preprotorev3";
|
||||
propNamePOR = "function-mesa_pwr";
|
||||
if (FindProperty(node, &propName, &propData, &propSize) &&
|
||||
FindProperty(node, &propNamePOR, &propData, &propSize)) {
|
||||
strlcpy(propName, "function-mesa_pwr", kPropNameLength);
|
||||
propNamePOR[0] = '~';
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Update the codec node with acoustic transducer scale data
|
||||
{
|
||||
uint8_t atscData[20];
|
||||
|
||||
if (syscfgCopyDataForTag('ATSc', atscData, sizeof(atscData)) > 0) {
|
||||
// Update codec
|
||||
if (FindNode(0, "arm-io/spi1/audio-codec", &node)) {
|
||||
propName = "at-scale-imic";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
memcpy(propData, &atscData[0], sizeof(uint32_t));
|
||||
}
|
||||
propName = "at-scale-smic";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
memcpy(propData, &atscData[4], sizeof(uint32_t));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Update the speaker calibration data
|
||||
if (FindNode(0, "arm-io/i2c1/audio-speaker0", &node)) {
|
||||
propName = "speaker-calib";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('SpCl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the als calibration data for all nodes that may be present on the dev board
|
||||
if (FindNode(0, "arm-io/i2c2/als1", &node)) {
|
||||
propName = "alsCalibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LSCI', propData, propSize);
|
||||
}
|
||||
}
|
||||
if (FindNode(0, "arm-io/i2c2/als2", &node)) {
|
||||
propName = "alsCalibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LSCI', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the backlight calibration data
|
||||
if (FindNode(0, "backlight", &node)) {
|
||||
propName = "backlight-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('BLCl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the compass calibration data
|
||||
if (FindNode(0, "arm-io/uart8/oscar/compass", &node)) {
|
||||
propName = "compass-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('CPAS', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the gyro calibration data
|
||||
if (FindNode(0, "arm-io/uart8/oscar/gyro", &node)) {
|
||||
propName = "gyro-orientation";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GRot', propData, propSize);
|
||||
}
|
||||
propName = "gyro-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GSCl', propData, propSize);
|
||||
}
|
||||
propName = "gyro-temp-table";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GYTT', propData, propSize);
|
||||
}
|
||||
propName = "gyro-interrupt-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GICl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update accelerometer calibration data
|
||||
if (FindNode(0, "arm-io/uart8/oscar/accelerometer", &node)) {
|
||||
propName = "accel-orientation";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ARot', propData, propSize);
|
||||
}
|
||||
propName = "low-temp-accel-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LTAO', propData, propSize);
|
||||
}
|
||||
propName = "accel-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ASCl', propData, propSize);
|
||||
}
|
||||
propName = "accel-interrupt-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('AICl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update pressure sensor calibration data
|
||||
if (FindNode(0, "arm-io/uart8/oscar/pressure", &node)) {
|
||||
propName = "pressure-offset-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('SPPO', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update charger calibration data
|
||||
if (FindNode(0, "charger", &node)) {
|
||||
propName = "usb-input-limit-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('CBAT', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update halleffect button -- remove when pre-EVT hardware deprecated
|
||||
if (FindNode(0, "buttons", &node)) {
|
||||
if (ipad5b_get_board_rev() < J81_PREEVT_BOARD_REV) {
|
||||
propName = "function-button_halleffect-preevt";
|
||||
propNamePOR = "function-button_halleffect";
|
||||
if (FindProperty(node, &propName, &propData, &propSize) &&
|
||||
FindProperty(node, &propNamePOR, &propData, &propSize)) {
|
||||
strlcpy(propName, "function-button_halleffect", kPropNameLength);
|
||||
propNamePOR[0] = '~';
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// WLAN Capri A0 workarounds -- !!!FIXME!!! Remove this when Capri A0 is deprecated
|
||||
// <rdar://problem/16597296> Remove Capri A0 PCIe hacks
|
||||
if (FindNode(0, "arm-io/apcie/pci-bridge1/wlan", &node)) {
|
||||
if (chipid_get_chip_revision() > CHIP_REVISION_A0) {
|
||||
// Disable workarounds for Capri A1 and later.
|
||||
propName = "acpie-l1ss-workaround";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
propName = "pci-wake-l1pm-disable";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
} else {
|
||||
// Fix up the hacks for Capri A0
|
||||
propName = "pci-l1pm-control";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
propName = "pci-l1pm-control-a0";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propName[16] = '\0';
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif // WITH_DEVICETREE
|
||||
|
||||
#if WITH_PAINT
|
||||
|
||||
// The default background is expected to to be black and the artwork is expected
|
||||
// to be white. This arrangement will be inverted depending upon the cover glass
|
||||
// color of the device.
|
||||
|
||||
// Sample DClr_override values for testing devices without DClr syscfg entries (enclosure/cover glass):
|
||||
// gray/black: setenv DClr_override 000200009B9899003C3B3B0000000000
|
||||
// silver/white: setenv DClr_override 00020000D8D9D700E3E4E10000000000
|
||||
|
||||
static color_policy_invert_t target_cover_glass_color_table[] = {
|
||||
{ RGB( 59, 59, 60), false }, // Black - black background, white logo
|
||||
{ RGB(225, 228, 227), true }, // White - white background, black logo
|
||||
};
|
||||
|
||||
color_policy_t *target_color_map_init(enum colorspace cs, color_policy_t *color_policy)
|
||||
{
|
||||
// Must have a color policy structure passed in.
|
||||
if (color_policy == NULL)
|
||||
goto fail;
|
||||
|
||||
// We only support the RGB888 colorspace.
|
||||
if (cs != CS_RGB888)
|
||||
goto fail;
|
||||
|
||||
color_policy->policy_type = COLOR_MAP_POLICY_INVERT;
|
||||
color_policy->color_table = (void *)target_cover_glass_color_table;
|
||||
color_policy->color_count = ARRAY_SIZE(target_cover_glass_color_table);
|
||||
color_policy->map_color = NULL; // Use standard remapper
|
||||
|
||||
return color_policy;
|
||||
|
||||
fail:
|
||||
return NULL;
|
||||
}
|
||||
#endif // WITH_PAINT
|
||||
@@ -0,0 +1,989 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: rev 1.2
|
||||
I/O Spreadsheet tracker: <rdar://problem/14847504> J82 IO Spreadsheet
|
||||
Conversion command: csvtopinconfig.py --soc capri --config-column j81:J81 --config-column j82:J82 --copyright 2013-2014 --radar '<rdar://problem/14847504> J82 IO Spreadsheet' <filename>
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
#include <target/boardid.h>
|
||||
|
||||
static const uint32_t pinconfig_j81ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 15 : UART3_RXD -> UART_BT2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 33 : UART3_CTSN -> UART_BT2SOC_RTS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED, // 43 : I2S1_MCK -> GPIO_DISPLAY_ID1
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_GRAPE_MISO
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_DISABLED, // 53 : TMR32_PWM1 -> NC_TMR32_PWM1
|
||||
CFG_DISABLED, // 54 : TMR32_PWM2 -> NC_TMR32_PWM2
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC_CPU_SLEEP_STATUS
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_DISABLED, // 61 : ISP_UART0_TXD -> NC_ISP_UART0_TXD
|
||||
CFG_DISABLED, // 62 : ISP_UART0_RXD -> NC_ISP_UART0_RXD
|
||||
CFG_DISABLED, // 63 : UART7_TXD -> NC_UART7_TXD
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // 64 : UART7_RXD -> NC_UART7_RXD
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_DISABLED, // 70 : SPI0_SSIN -> NC_SPI0_SSIN
|
||||
CFG_FUNC0 | DRIVE_X6 | SLOW_SLEW | INPUT_SCHMITT, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_DOUT
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // 80 : GPIO[0] -> NC_SOC_GPIO00
|
||||
CFG_DISABLED, // 81 : GPIO[1] -> NC_SOC_GPIO01
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_DISABLED, // 85 : GPIO[5] -> NC_SOC_GPIO05
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // 88 : GPIO[8] -> NC_SOC_GPIO08
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_ALS2SOC_DEVBRD_IRQ_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> NC_SOC_GPIO10
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_DISABLED, // 94 : GPIO[14] -> NC_SOC_GPIO14
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_DISABLED, // 99 : GPIO[19] -> NC_SOC_GPIO19
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED | PULL_DOWN, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> NC_BOARD_ID4
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_MIC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_DISABLED | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_DISABLED | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_DISABLED | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2OSCAR_TX
|
||||
CFG_FUNC0, // 123 : UART8_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_DISABLED | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BB_TX
|
||||
CFG_DISABLED, // 141 : UART1_RXD -> UART_BB2SOC_TX
|
||||
CFG_DISABLED | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_DISABLED, // 143 : UART1_CTSN -> UART_BB2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED, // 145 : I2S4_MCK -> GPIO_DISPLAY_ID0
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_DISABLED, // 150 : I2S2_LRCK -> NC_I2S2_LRCK
|
||||
CFG_DISABLED, // 151 : I2S2_BCLK -> NC_I2S2_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // 152 : I2S2_DOUT -> NC_I2S2_DOUT
|
||||
CFG_DISABLED, // 153 : I2S2_DIN -> NC_I2S2_DIN
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 156 : SPI1_MISO -> SPI_CODEC_MISO
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_32K
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // 160 : ULPI_STP -> GPIO_SOC2DEVBRD_S3E_WAKE
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_DISABLED, // 167 : ULPI_DATA[3] -> GPIO_SOC2DEVBRD_S3E_RESET2_L
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_DISABLED, // 171 : DWI1_DO -> NC_DWI1_DO
|
||||
CFG_DISABLED, // 172 : DWI1_CLK -> NC_DWI1_CLK
|
||||
CFG_DISABLED, // 173 : PCIE_CLKREQ0_N -> NC_PCIE_CLKREQ0_N
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED, // 175 : PCIE_CLKREQ2_N -> PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED, // 176 : PCIE_CLKREQ3_N -> NC_PCIE_CLKREQ3_N
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> CLK_SOC2DEVBRD_PCIE_24MHZ
|
||||
CFG_DISABLED, // 178 : PCIE_PERST0_N -> NC_PERST0
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> NC_PERST3
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_DISABLED, // 183 : I2S2_MCK -> NC_I2S2_MCLK
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_j81dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 15 : UART3_RXD -> UART_BT2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_OUT_1 | DRIVE_X4 | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 33 : UART3_CTSN -> UART_BT2SOC_RTS_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED, // 43 : I2S1_MCK -> GPIO_DISPLAY_ID1
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_GRAPE_MISO
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_OUT_1 | DRIVE_X4 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_DISABLED, // 53 : TMR32_PWM1 -> NC_TMR32_PWM1
|
||||
CFG_DISABLED, // 54 : TMR32_PWM2 -> NC_TMR32_PWM2
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC_CPU_SLEEP_STATUS
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_DISABLED, // 61 : ISP_UART0_TXD -> NC_ISP_UART0_TXD
|
||||
CFG_DISABLED, // 62 : ISP_UART0_RXD -> NC_ISP_UART0_RXD
|
||||
CFG_DISABLED, // 63 : UART7_TXD -> NC_UART7_TXD
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // 64 : UART7_RXD -> NC_UART7_RXD
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_DISABLED, // 70 : SPI0_SSIN -> NC_SPI0_SSIN
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_DOUT
|
||||
CFG_IN | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // 80 : GPIO[0] -> NC_SOC_GPIO00
|
||||
CFG_DISABLED, // 81 : GPIO[1] -> NC_SOC_GPIO01
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_DISABLED, // 85 : GPIO[5] -> NC_SOC_GPIO05
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // 88 : GPIO[8] -> NC_SOC_GPIO08
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_ALS2SOC_DEVBRD_IRQ_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> NC_SOC_GPIO10
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_DISABLED, // 94 : GPIO[14] -> NC_SOC_GPIO14
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_DISABLED, // 99 : GPIO[19] -> NC_SOC_GPIO19
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED | PULL_DOWN, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> NC_BOARD_ID4
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_MIC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_DISABLED | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_DISABLED | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_IN | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2OSCAR_TX
|
||||
CFG_FUNC0, // 123 : UART8_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X4 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BB_TX
|
||||
CFG_DISABLED, // 141 : UART1_RXD -> UART_BB2SOC_TX
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_DISABLED, // 143 : UART1_CTSN -> UART_BB2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED, // 145 : I2S4_MCK -> GPIO_DISPLAY_ID0
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_DISABLED, // 150 : I2S2_LRCK -> NC_I2S2_LRCK
|
||||
CFG_DISABLED, // 151 : I2S2_BCLK -> NC_I2S2_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // 152 : I2S2_DOUT -> NC_I2S2_DOUT
|
||||
CFG_DISABLED, // 153 : I2S2_DIN -> NC_I2S2_DIN
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 156 : SPI1_MISO -> SPI_CODEC_MISO
|
||||
CFG_OUT_1 | DRIVE_X4 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_32K
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // 160 : ULPI_STP -> GPIO_SOC2DEVBRD_S3E_WAKE
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_DISABLED, // 167 : ULPI_DATA[3] -> GPIO_SOC2DEVBRD_S3E_RESET2_L
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_DISABLED, // 171 : DWI1_DO -> NC_DWI1_DO
|
||||
CFG_DISABLED, // 172 : DWI1_CLK -> NC_DWI1_CLK
|
||||
CFG_DISABLED, // 173 : PCIE_CLKREQ0_N -> NC_PCIE_CLKREQ0_N
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED, // 175 : PCIE_CLKREQ2_N -> PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED, // 176 : PCIE_CLKREQ3_N -> NC_PCIE_CLKREQ3_N
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> CLK_SOC2DEVBRD_PCIE_24MHZ
|
||||
CFG_DISABLED, // 178 : PCIE_PERST0_N -> NC_PERST0
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> NC_PERST3
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_DISABLED, // 183 : I2S2_MCK -> NC_I2S2_MCLK
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_j82ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 15 : UART3_RXD -> UART_BT2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 33 : UART3_CTSN -> UART_BT2SOC_RTS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED, // 43 : I2S1_MCK -> GPIO_DISPLAY_ID1
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_GRAPE_MISO
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_DISABLED, // 53 : TMR32_PWM1 -> NC_TMR32_PWM1
|
||||
CFG_DISABLED, // 54 : TMR32_PWM2 -> NC_TMR32_PWM2
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC_CPU_SLEEP_STATUS
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_DISABLED, // 61 : ISP_UART0_TXD -> NC_ISP_UART0_TXD
|
||||
CFG_DISABLED, // 62 : ISP_UART0_RXD -> NC_ISP_UART0_RXD
|
||||
CFG_DISABLED, // 63 : UART7_TXD -> NC_UART7_TXD
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // 64 : UART7_RXD -> NC_UART7_RXD
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_DISABLED, // 70 : SPI0_SSIN -> NC_SPI0_SSIN
|
||||
CFG_FUNC0 | DRIVE_X6 | SLOW_SLEW | INPUT_SCHMITT, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_DOUT
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // 80 : GPIO[0] -> NC_SOC_GPIO00
|
||||
CFG_DISABLED, // 81 : GPIO[1] -> NC_SOC_GPIO01
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_DISABLED, // 85 : GPIO[5] -> NC_SOC_GPIO05
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // 88 : GPIO[8] -> NC_SOC_GPIO08
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_ALS2SOC_DEVBRD_IRQ_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> NC_SOC_GPIO10
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_DISABLED, // 94 : GPIO[14] -> NC_SOC_GPIO14
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_DISABLED, // 99 : GPIO[19] -> NC_SOC_GPIO19
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED | PULL_DOWN, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_IN | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> NC_BOARD_ID4
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_MIC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_IN | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_IN | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_IN | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2OSCAR_TX
|
||||
CFG_FUNC0, // 123 : UART8_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_IN | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BB_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BB2SOC_TX
|
||||
CFG_IN | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BB2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED, // 145 : I2S4_MCK -> GPIO_DISPLAY_ID0
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_DISABLED, // 150 : I2S2_LRCK -> NC_I2S2_LRCK
|
||||
CFG_DISABLED, // 151 : I2S2_BCLK -> NC_I2S2_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // 152 : I2S2_DOUT -> NC_I2S2_DOUT
|
||||
CFG_DISABLED, // 153 : I2S2_DIN -> NC_I2S2_DIN
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 156 : SPI1_MISO -> SPI_CODEC_MISO
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_32K
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // 160 : ULPI_STP -> GPIO_SOC2DEVBRD_S3E_WAKE
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_DISABLED, // 167 : ULPI_DATA[3] -> GPIO_SOC2DEVBRD_S3E_RESET2_L
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_DISABLED, // 171 : DWI1_DO -> NC_DWI1_DO
|
||||
CFG_DISABLED, // 172 : DWI1_CLK -> NC_DWI1_CLK
|
||||
CFG_DISABLED, // 173 : PCIE_CLKREQ0_N -> NC_PCIE_CLKREQ0_N
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED, // 175 : PCIE_CLKREQ2_N -> PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED, // 176 : PCIE_CLKREQ3_N -> NC_PCIE_CLKREQ3_N
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> CLK_SOC2DEVBRD_PCIE_24MHZ
|
||||
CFG_DISABLED, // 178 : PCIE_PERST0_N -> NC_PERST0
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> NC_PERST3
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_DISABLED, // 183 : I2S2_MCK -> NC_I2S2_MCLK
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_j82dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 15 : UART3_RXD -> UART_BT2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_OUT_1 | DRIVE_X4 | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 33 : UART3_CTSN -> UART_BT2SOC_RTS_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED, // 43 : I2S1_MCK -> GPIO_DISPLAY_ID1
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_GRAPE_MISO
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_OUT_1 | DRIVE_X4 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_DISABLED, // 53 : TMR32_PWM1 -> NC_TMR32_PWM1
|
||||
CFG_DISABLED, // 54 : TMR32_PWM2 -> NC_TMR32_PWM2
|
||||
CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC_CPU_SLEEP_STATUS
|
||||
CFG_DISABLED | DRIVE_X4 | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_DISABLED, // 61 : ISP_UART0_TXD -> NC_ISP_UART0_TXD
|
||||
CFG_DISABLED, // 62 : ISP_UART0_RXD -> NC_ISP_UART0_RXD
|
||||
CFG_DISABLED, // 63 : UART7_TXD -> NC_UART7_TXD
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // 64 : UART7_RXD -> NC_UART7_RXD
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_DISABLED, // 70 : SPI0_SSIN -> NC_SPI0_SSIN
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_BCLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_DOUT
|
||||
CFG_IN | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // 80 : GPIO[0] -> NC_SOC_GPIO00
|
||||
CFG_DISABLED, // 81 : GPIO[1] -> NC_SOC_GPIO01
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_DISABLED, // 85 : GPIO[5] -> NC_SOC_GPIO05
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // 88 : GPIO[8] -> NC_SOC_GPIO08
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_ALS2SOC_DEVBRD_IRQ_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> NC_SOC_GPIO10
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_DISABLED, // 94 : GPIO[14] -> NC_SOC_GPIO14
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_DISABLED, // 99 : GPIO[19] -> NC_SOC_GPIO19
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED | PULL_DOWN, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> NC_BOARD_ID4
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_MIC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_IN | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_IN | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_IN | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2OSCAR_TX
|
||||
CFG_FUNC0, // 123 : UART8_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X4 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BB_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BB2SOC_TX
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BB2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED, // 145 : I2S4_MCK -> GPIO_DISPLAY_ID0
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_DISABLED, // 150 : I2S2_LRCK -> NC_I2S2_LRCK
|
||||
CFG_DISABLED, // 151 : I2S2_BCLK -> NC_I2S2_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // 152 : I2S2_DOUT -> NC_I2S2_DOUT
|
||||
CFG_DISABLED, // 153 : I2S2_DIN -> NC_I2S2_DIN
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 156 : SPI1_MISO -> SPI_CODEC_MISO
|
||||
CFG_OUT_1 | DRIVE_X4 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_32K
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // 160 : ULPI_STP -> GPIO_SOC2DEVBRD_S3E_WAKE
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_DISABLED, // 167 : ULPI_DATA[3] -> GPIO_SOC2DEVBRD_S3E_RESET2_L
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_DISABLED, // 171 : DWI1_DO -> NC_DWI1_DO
|
||||
CFG_DISABLED, // 172 : DWI1_CLK -> NC_DWI1_CLK
|
||||
CFG_DISABLED, // 173 : PCIE_CLKREQ0_N -> NC_PCIE_CLKREQ0_N
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED, // 175 : PCIE_CLKREQ2_N -> PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED, // 176 : PCIE_CLKREQ3_N -> NC_PCIE_CLKREQ3_N
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> CLK_SOC2DEVBRD_PCIE_24MHZ
|
||||
CFG_DISABLED, // 178 : PCIE_PERST0_N -> NC_PERST0
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> NC_PERST3
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_DISABLED, // 183 : I2S2_MCK -> NC_I2S2_MCLK
|
||||
};
|
||||
|
||||
struct pinconfig_map {
|
||||
uint32_t board_id;
|
||||
uint32_t board_id_mask;
|
||||
const uint32_t *pinconfigs[GPIOC_COUNT];
|
||||
};
|
||||
|
||||
static const struct pinconfig_map cfg_map[] = {
|
||||
{ TARGET_BOARD_ID_J81AP, ~0, { pinconfig_j81ap_0 } },
|
||||
{ TARGET_BOARD_ID_J81DEV, ~0, { pinconfig_j81dev_0 } },
|
||||
{ TARGET_BOARD_ID_J82AP, ~0, { pinconfig_j82ap_0 } },
|
||||
{ TARGET_BOARD_ID_J82DEV, ~0, { pinconfig_j82dev_0 } },
|
||||
};
|
||||
|
||||
const uint32_t * target_get_default_gpio_cfg(int gpioc)
|
||||
{
|
||||
static const struct pinconfig_map *selected_map = NULL;
|
||||
|
||||
if (selected_map == NULL) {
|
||||
uint32_t board_id = platform_get_board_id();
|
||||
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
|
||||
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
|
||||
selected_map = &cfg_map[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (selected_map == NULL)
|
||||
panic("no default pinconfig for board id %u", board_id);
|
||||
}
|
||||
|
||||
ASSERT(gpioc < GPIOC_COUNT);
|
||||
return selected_map->pinconfigs[gpioc];
|
||||
}
|
||||
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <target.h>
|
||||
#include <target/powerconfig.h>
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
bool
|
||||
target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
|
||||
{
|
||||
int length = 0;
|
||||
bool result = false;
|
||||
|
||||
if ((result = target_get_property_base(prop, data, maxdata, retlen)) == false) {
|
||||
switch(prop) {
|
||||
case TARGET_PROPERTY_RESTORE_BACKLIGHT_LEVEL:
|
||||
// fix the restore backlight level at the precharge level,
|
||||
// to make sure the backlight does not cause the battery to
|
||||
// drain during restore
|
||||
if (maxdata >= (ssize_t)sizeof(uint32_t)) {
|
||||
result = true;
|
||||
length = sizeof(uint32_t);
|
||||
*(uint32_t *)data = PRECHARGE_BACKLIGHT_LEVEL;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (retlen != NULL) *retlen = length;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,50 @@
|
||||
# Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
# BUCK_CPU, BUCK_GPU and BUCK_RAM should be reviewed
|
||||
# if any changed happen in drivers/dialog/pmu/power.c:power_get_buck_value()
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2207=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_V2 \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=CHIPID_SOC_VOLTAGE_VMIN \
|
||||
TARGET_HAS_BASEBAND=$(TARGET_HAS_BASEBAND) \
|
||||
TARGET_VID0_CLK_CFG=0x86100000 \
|
||||
TARGET_CORE_PHY_TMR_LPCLK_CFG=0x00330087 \
|
||||
TARGET_CORE_PHY_TMR_CFG=0x256f0000 \
|
||||
TARGET_PHY_STOP_WAIT_TIME=0x28 \
|
||||
TARGET_DDR_798M=1 \
|
||||
DISPLAY_LANDSCAPE_IPAD_TUNABLES=1 \
|
||||
PMU_LCD_PWR_EN=1 \
|
||||
AMC_NUM_CHANNELS=4 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_GPU=2 \
|
||||
BUCK_RAM=1 \
|
||||
MULTITOUCH_DTPATH=\"arm-io/spi3/multi-touch\" \
|
||||
WIFI_DTPATH=\"arm-io/uart2/wlan\" \
|
||||
DP_DTPATH=\"arm-io/displayport\" \
|
||||
DPPHY_DTPATH=\"arm-io/lpdp-phy\" \
|
||||
BT_DTPATH=\"arm-io/uart3/bluetooth\"
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
|
||||
ifneq ($(PRODUCT),LLB)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/properties.o
|
||||
endif
|
||||
Reference in new issue
Block a user