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@@ -0,0 +1,44 @@
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/*
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* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ADBE_SETTINGS_H
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#define __TARGET_ADBE_SETTINGS_H
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static struct adbe_v2_tuneable adbe_tuneables[] = {
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{
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.name = "default",
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.adbe0_vblank_pos_vbi_pulse = 0x0132,
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.adbe0_vblank_clk_gate_wakeup = 0x0132,
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.adbe0_vblank_clk_gate_idle = 0x0000,
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.adbe0_vblank_busy_finish = 2,
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.adbe0_tunable_mode_ctrl = (DBEMODECNTL_DPB_BUSY_MASK | \
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DBEMODECNTL_PMGR_CLK_GATE_ENABLE | \
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DBEMODECNTL_DYN_CLK_GATE_ENABLE | \
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DBEMODECNTL_BLK_CLK_GATE_ENABLE),
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.adbe0_aap_support = 1,
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.adbe0_aap_format_control_reg1 = (AAP_FORMAT_CONTROL_REG1_AUTOPOS | AAP_FORMAT_CONTROL_REG1_RSVD(8) | AAP_FORMAT_CONTROL_REG1_VS_POL),
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},
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{
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.name = "camelia",
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.adbe0_vblank_pos_vbi_pulse = 0x0000,
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.adbe0_vblank_clk_gate_wakeup = 0x0000,
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.adbe0_vblank_clk_gate_idle = 0x0001,
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.adbe0_vblank_busy_finish = 0,
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.adbe0_tunable_mode_ctrl = (DBEMODECNTL_DPB_BUSY_MASK | \
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DBEMODECNTL_PMGR_CLK_GATE_ENABLE | \
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DBEMODECNTL_DYN_CLK_GATE_ENABLE | \
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DBEMODECNTL_BLK_CLK_GATE_ENABLE),
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.adbe0_aap_support = 1,
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.adbe0_aap_format_control_reg1 = (AAP_FORMAT_CONTROL_REG1_AUTOPOS | AAP_FORMAT_CONTROL_REG1_RSVD(8) | AAP_FORMAT_CONTROL_REG1_VS_POL),
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},
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};
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#endif
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ASPNANDCONFIG_H
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#define __TARGET_ASPNANDCONFIG_H
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//MLC devices
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#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 4
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#define ASPNAND_ERASE_DIES_IN_PARALLEL 8
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#define ASPNAND_READ_DIES_IN_PARALLEL 8
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#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
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//TLC devices
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#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
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// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
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#define ASPNAND_INDIRECTION_MEMORY (8*1024*1024)
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#define ASPNAND_LEGACY_INDIRECTION_MEMORY ASPNAND_INDIRECTION_MEMORY
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#endif
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@@ -0,0 +1,35 @@
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/*
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* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef TARGET_BOARDID_H
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#define TARGET_BOARDID_H
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#define TARGET_BOARD_ID_J98AP (12)
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#define TARGET_BOARD_ID_J98DEV (13)
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#define TARGET_BOARD_ID_J99AP (4)
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#define TARGET_BOARD_ID_J99DEV (5)
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// Board revs
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#define J98_DEV1_BOARD_REV (0x0)
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#define J98_DEV2_BOARD_REV (0x1)
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// board revs on AP are reversed
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// <rdar://problem/16314440> J99: Display timing selection on Form Factor is incorrect
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#define J99_PROTO0_BOARD_REV_LOCAL (0xE)
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#define J99_PROTO0_BOARD_REV_CHINA (0xD)
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#define J99_PROTO1_BOARD_REV_LOCAL (0xC)
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#define J99_PROTO1_BOARD_REV_CHINA (0xB)
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#define J99_PROTO2_BOARD_REV (0xA)
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#define J99_PROTO3_BOARD_REV (0x9)
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#define J99_PROTO3_P9_BOARD_REV (0x8)
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#define J99_EVT_BOARD_REV (0x7)
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#define J99_EVT_PLUS_BOARD_REV (0x6)
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#define J99_EVT2_BOARD_REV (0x5)
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#endif
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@@ -0,0 +1,42 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* ipad5,x specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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/* Board Revision */
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#define GPIO_BOARD_REV0 GPIO( 20, 1) // 161 : ULPI_NXT
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#define GPIO_BOARD_REV1 GPIO( 19, 7) // 159 : ULPI_DIR
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#define GPIO_BOARD_REV2 GPIO( 21, 0) // 168 : ULPI_DATA[2]
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#define GPIO_BOARD_REV3 GPIO( 20, 3) // 163 : ULPI_DATA[6]
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/* Miscellaneous Pins */
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#define GPIO_PMU_LCD_PWR_EN (17)
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/* D2207 watchdog tickle, 'KEEPACT' */
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#define GPIO_WDOG_TICKLE GPIO( 10, 7) // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
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/* Enable for GPU UVD */
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#define GPIO_SOC2GPUUVD_EN GPIO( 10, 0)
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/* which IICs to initialize */
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#define IICS_MASK (0xF)
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#define TRISTAR_IIC_BUS (0)
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#define BACKLIGHT_IIC_BUS (0)
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,20 @@
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/*
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* Copyright (C) 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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||||
*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef LPDP_SETTINGS_H
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#define LPDP_SETTINGS_H
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static struct lpdp_port_calibration lpdp_port_calibration_table[1][1] = {
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{ {LPDP_PHY_LANE_VREG_ADJ_360_mV, 0}, },
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};
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#define LPDP_PORT_CALIBRATION_TABLE_FIXED (true)
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#endif
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@@ -0,0 +1,120 @@
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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#define CHARGER_IIC_BUS 3
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD2207_HIBERNATE6, 0x24 }, // enable BUCK4_SW2+BUCK3_SW3 (Oscar Rails) in hibernate
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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};
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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{ PMU_IIC_BUS, kD2207_GPIO3, 0xDA}, // GPIO_IOXPNDR_INT_L In, F Edge, No Push-Pull, No Wake, PU
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{ PMU_IIC_BUS, kD2207_GPIO4, 0x7B}, // GPIO_TS2ORIONSOC2PMU_IRQ In, R Edge, No Push-Pull, No Wake, PU
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#if TARGET_HAS_BASEBAND
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{ PMU_IIC_BUS, kD2207_GPIO5, 0x09}, // GPIO_PMU2BBPMU_RESET_L Out 0, Push-Pull, VBUCK3
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#else
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{ PMU_IIC_BUS, kD2207_GPIO5, 0xB9}, // GPIO_PMU2BBPMU_RESET_L In, R Edge, PD
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#endif
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{ PMU_IIC_BUS, kD2207_GPIO6, 0xDA}, // UART_BATT_HDQ In, F Edge, Wake, PD
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{ PMU_IIC_BUS, kD2207_GPIO7, 0xBA}, // GPIO_BT2PMU_HOST_WAKE In, R Edge, Wake, PD
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{ PMU_IIC_BUS, kD2207_GPIO8, 0x7B}, // GPIO_WLAN2PMU_HOST_WAKE In, R Edge, No Pull-Up, No Wake, PD
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#if TARGET_HAS_BASEBAND
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{ PMU_IIC_BUS, kD2207_GPIO9, 0x8A}, // GPIO_BB2PMU_HOST_WAKE_L In, Active low, Wake, PU, VBUCK3
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#else
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{ PMU_IIC_BUS, kD2207_GPIO9, 0xB9}, // GPIO_BB2PMU_HOST_WAKE_L In, R Edge, PD
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#endif
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{ PMU_IIC_BUS, kD2207_GPIO10, 0xEA}, // GPIO_CODEC2PMU_HS_IRQ_L In, Any Edge, Wake, PU, VBUCK3
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{ PMU_IIC_BUS, kD2207_GPIO11, 0xFB}, // GPIO_HALL2PMU_IRQ0 Both Edges, Wake, PD
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{ PMU_IIC_BUS, kD2207_GPIO12, 0x7B}, // GPIO_TS2SOC2PMU_IRQ In, Hi level, Wake, PD
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{ PMU_IIC_BUS, kD2207_GPIO13, 0xEA}, // GPIO_HALL2PMU_IRQ1 Both Edges, VBUCK3, Wake, PU
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{ PMU_IIC_BUS, kD2207_GPIO14, 0xB8}, // PCIE_WLAN2PMU_WAKE_L In, F Edge, VBUCK3, No Wake, PU
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{ PMU_IIC_BUS, kD2207_GPIO15, 0xDA}, // GPIO_GANGES2SOC2PMU_IRQ_L In, F Edge, Wake, PD
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{ PMU_IIC_BUS, kD2207_GPIO16, 0x7B}, // GPIO_OSCAR2PMU_HOST_WAKE In, Hi level, Wake, PD
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{ PMU_IIC_BUS, kD2207_BUCK_DWI_CTRL0, 0x23 }, // enable DWI for BUCK0, BUCK1, BUCK5
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{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2, 0x11 }, // HIB_32K (for WiFi/BT) + DWI_EN
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};
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static const struct pmu_setup_struct pmu_backlight_enable[] =
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{
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{ PMU_IIC_BUS, kDIALOG_WLED_ISET, 0xD4 }, // 50% value from OS
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{ PMU_IIC_BUS, kDIALOG_WLED_ISET2, 0x00 },
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{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, // enable all LED strings
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(kDIALOG_WLED_CONTROL_WLED_ENABLE1 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE2 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE3 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE4 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE5 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE6) },
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{ PMU_IIC_BUS, kDIALOG_WLED_OPTIONS, // enable LED Power
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(kDIALOG_WLED_CONTROL2_WLED_RAMP_EN |
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kDIALOG_WLED_CONTROL2_WLED_DITH_EN) }
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};
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static const struct pmu_setup_struct pmu_backlight_disable[] =
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{
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{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, 0x0 } // disable LED power
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};
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static const struct core_rails_struct soc_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2207_BUCK2_VSEL }
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};
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static const struct core_rails_struct cpu_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2207_BUCK0_VSEL }
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};
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static const struct core_rails_struct ram_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2207_BUCK5_VSEL }
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};
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#define TARGET_USE_CHARGE_TABLE 1
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static const struct power_charge_limits pmu_charge_table[16] = {
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{ 4100, 1000, 1500, 2018 }, // 10 - 15C
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{ 4200, 1000, 1500, 2018 },
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{ USHRT_MAX, 1000, 1500, 2018 },
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{ 4100, 1500, 2000, 6053 }, // 15 - 20C
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{ 4200, 1500, 2000, 4035 },
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{ USHRT_MAX, 1500, 2000, 2018 },
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{ 4100, 2000, 4500, 6053 }, // 20 - 45C
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{ 4200, 2000, 4500, 5044 },
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{ USHRT_MAX, 2000, 4500, 4035 },
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};
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#endif /* POWERCONFIG_PMU_SETUP */
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#define NO_BATTERY_VOLTAGE 2700
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#define MIN_BOOT_BATTERY_VOLTAGE 3600
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#define TARGET_BOOT_BATTERY_VOLTAGE 3700
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#define TARGET_BOOT_BATTERY_CAPACITY 50
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#define PRECHARGE_BACKLIGHT_LEVEL 824
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#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
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#define TARGET_MAX_USB_INPUT_CURRENT 2400
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#define TARGET_PRECHARGE_ALWAYS_DISPLAY_IDLE 1
|
||||
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||||
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#define ACC_PWR_LDO (6)
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||||
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#define GASGAUGE_BATTERYID_BLOCK 1
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||||
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#endif
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@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
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||||
#define __TARGET_UARTCONFIG_H
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||||
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||||
/* define one debug serial ports */
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||||
#define DEBUG_SERIAL_PORT (0)
|
||||
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||||
#define HDQGAUGE_SERIAL_PORT (5)
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||||
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||||
#endif
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||||
@@ -0,0 +1,995 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/power.h>
|
||||
#include <drivers/iic.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
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||||
#include <lib/devicetree.h>
|
||||
#include <lib/syscfg.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/soc/chipid.h>
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||||
#include <target.h>
|
||||
#include <target/boardid.h>
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||||
#include <drivers/display.h>
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||||
#if (APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC))
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#include <drivers/displayport/displayport.h>
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||||
#endif
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||||
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||||
// Display panel type
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||||
typedef enum {
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||||
DISPLAY_PANEL_TYPE_UNKNOWN = 0,
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||||
DISPLAY_PANEL_TYPE_CAMELIA,
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||||
DISPLAY_PANEL_TYPE_TULIP,
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||||
// Metadata
|
||||
DISPLAY_PANEL_TYPE_COUNT
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||||
} display_panel_type;
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||||
|
||||
static const char *display_panel_types[] = {
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||||
"UNKNOWN",
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||||
"j99POC",
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||||
"ipad5c",
|
||||
};
|
||||
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||||
typedef enum {
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||||
DISPLAY_SWITCH_TYPE_UNKNOWN = 0,
|
||||
DISPLAY_SWITCH_TYPE_TEMP_KONA,
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||||
DISPLAY_SWITCH_TYPE_KONA,
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||||
// Metadata
|
||||
DISPLAY_SWITCH_TYPE_COUNT
|
||||
} display_switch_type;
|
||||
|
||||
static const char *display_switch_types[] = {
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||||
"UNKNOWN",
|
||||
"multi-touch,j99-st",
|
||||
"multi-touch,j99",
|
||||
};
|
||||
|
||||
// Display panel id sense pins
|
||||
#define DISPLAY_TO_AP_ID0 GPIO(22, 5) // 181 : PCIE_PERST3_N -> GPIO_DEVDOG_DETECT
|
||||
|
||||
uint32_t ipad5c_get_board_rev(void);
|
||||
static void ipad5c_get_display_info(void);
|
||||
uint32_t target_get_display_panel_type(void);
|
||||
uint32_t target_get_display_switch_type(void);
|
||||
|
||||
static bool gpio_board_rev_valid;
|
||||
static bool gpio_display_id_valid;
|
||||
static uint32_t gpio_board_rev;
|
||||
static display_panel_type display_panel;
|
||||
static display_switch_type display_switch;
|
||||
#if (APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC))
|
||||
static dp_t dp;
|
||||
#endif
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, -90);
|
||||
|
||||
bool check_is_board_deprecated = false;
|
||||
|
||||
uint32_t ipad5c_get_board_rev(void)
|
||||
{
|
||||
if (!gpio_board_rev_valid) {
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV3, GPIO_PUP);
|
||||
|
||||
spin(100); // Wait 100us
|
||||
|
||||
gpio_board_rev =
|
||||
(gpio_read(GPIO_BOARD_REV3) << 3) |
|
||||
(gpio_read(GPIO_BOARD_REV2) << 2) |
|
||||
(gpio_read(GPIO_BOARD_REV1) << 1) |
|
||||
(gpio_read(GPIO_BOARD_REV0) << 0);
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_DFLT);
|
||||
|
||||
gpio_board_rev_valid = true;
|
||||
}
|
||||
|
||||
return gpio_board_rev;
|
||||
}
|
||||
// The panel id pin mappings are described by the following id pin states:
|
||||
|
||||
// ID0 Panel Switch
|
||||
// ---- ----- -----
|
||||
// PD Camelia Temp_kona
|
||||
// PU Tulip Temp_kona
|
||||
// Open Tulip Kona
|
||||
|
||||
static void ipad5c_get_display_info(void)
|
||||
{
|
||||
if (target_config_ap()) {
|
||||
uint32_t get_board_rev;
|
||||
get_board_rev = ipad5c_get_board_rev();
|
||||
switch(get_board_rev) {
|
||||
case J99_PROTO0_BOARD_REV_LOCAL:
|
||||
case J99_PROTO0_BOARD_REV_CHINA:
|
||||
display_panel = DISPLAY_PANEL_TYPE_CAMELIA;
|
||||
display_switch = DISPLAY_SWITCH_TYPE_TEMP_KONA;
|
||||
break;
|
||||
case J99_PROTO1_BOARD_REV_LOCAL:
|
||||
case J99_PROTO1_BOARD_REV_CHINA:
|
||||
case J99_PROTO2_BOARD_REV:
|
||||
display_panel = DISPLAY_PANEL_TYPE_TULIP;
|
||||
display_switch = DISPLAY_SWITCH_TYPE_TEMP_KONA;
|
||||
break;
|
||||
default:
|
||||
display_panel = DISPLAY_PANEL_TYPE_TULIP;
|
||||
display_switch = DISPLAY_SWITCH_TYPE_KONA;
|
||||
break;
|
||||
}
|
||||
dprintf(DEBUG_INFO, "get_board_rev %d Display panel = %s\nDisplay switch = %s\n",
|
||||
get_board_rev,
|
||||
display_panel_types[display_panel],
|
||||
display_switch_types[display_switch]);
|
||||
} else {
|
||||
const char *id0;
|
||||
|
||||
gpio_configure(DISPLAY_TO_AP_ID0, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(DISPLAY_TO_AP_ID0, GPIO_PUP);
|
||||
|
||||
spin(100); // Wait 100us
|
||||
|
||||
if (gpio_read(DISPLAY_TO_AP_ID0)) {
|
||||
// ID0 could be externally pulled low or it could be
|
||||
// floating. Change the polarity of the internal pull.
|
||||
gpio_configure_pupdn(DISPLAY_TO_AP_ID0, GPIO_PDN);
|
||||
spin(100); // Wait 100us
|
||||
|
||||
if (!gpio_read(DISPLAY_TO_AP_ID0)) {
|
||||
// ID0 is open.
|
||||
id0 = "open";
|
||||
display_panel = DISPLAY_PANEL_TYPE_TULIP;
|
||||
display_switch = DISPLAY_SWITCH_TYPE_KONA;
|
||||
gpio_display_id_valid = true;
|
||||
} else {
|
||||
// ID0 has an external pull up.
|
||||
id0 = "pu";
|
||||
display_panel = DISPLAY_PANEL_TYPE_TULIP;
|
||||
display_switch = DISPLAY_SWITCH_TYPE_TEMP_KONA;
|
||||
gpio_display_id_valid = true;
|
||||
}
|
||||
|
||||
} else {
|
||||
// ID1 has an external pull down.
|
||||
id0 = "pd";
|
||||
display_panel = DISPLAY_PANEL_TYPE_CAMELIA;
|
||||
display_switch = DISPLAY_SWITCH_TYPE_TEMP_KONA;
|
||||
gpio_display_id_valid = true;
|
||||
}
|
||||
|
||||
dprintf(DEBUG_INFO, "%spanel id pin state: id0=%s\n",
|
||||
gpio_display_id_valid ? "" : "Unknown", id0);
|
||||
|
||||
ASSERT(display_panel < DISPLAY_PANEL_TYPE_COUNT);
|
||||
ASSERT(display_switch < DISPLAY_SWITCH_TYPE_COUNT);
|
||||
|
||||
dprintf(DEBUG_INFO, "Display panel = %s\nDisplay switch = %s\n",
|
||||
display_panel_types[display_panel],
|
||||
display_switch_types[display_switch]);
|
||||
|
||||
gpio_configure(DISPLAY_TO_AP_ID0, GPIO_CFG_DFLT);
|
||||
gpio_display_id_valid = true;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t target_get_display_panel_type(void)
|
||||
{
|
||||
if (!gpio_display_id_valid) {
|
||||
ipad5c_get_display_info();
|
||||
}
|
||||
return display_panel;
|
||||
}
|
||||
|
||||
uint32_t target_get_display_switch_type(void)
|
||||
{
|
||||
if (!gpio_display_id_valid) {
|
||||
ipad5c_get_display_info();
|
||||
}
|
||||
return display_switch;
|
||||
}
|
||||
|
||||
bool is_board_deprecated(void) {
|
||||
uint32_t board_id;
|
||||
uint32_t board_rev;
|
||||
|
||||
board_id = platform_get_board_id();
|
||||
board_rev = ipad5c_get_board_rev();
|
||||
|
||||
//Check Dev boards first.
|
||||
if (( board_id == TARGET_BOARD_ID_J98DEV || board_id == TARGET_BOARD_ID_J99DEV) && (board_rev == J98_DEV1_BOARD_REV)) {
|
||||
return true;
|
||||
}
|
||||
|
||||
//Check AP boards
|
||||
switch(board_rev) {
|
||||
case J99_PROTO0_BOARD_REV_LOCAL:
|
||||
case J99_PROTO0_BOARD_REV_CHINA:
|
||||
case J99_PROTO1_BOARD_REV_LOCAL:
|
||||
case J99_PROTO1_BOARD_REV_CHINA:
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
#if WITH_HW_POWER
|
||||
int pmu_set_data(int dev, uint16_t reg, uint8_t byte, bool do_confirm);
|
||||
int charger_set_data(int dev, uint16_t reg, uint8_t byte, bool do_confirm);
|
||||
#endif
|
||||
|
||||
// TODO: Abstract DPOT code in a DPOT driver
|
||||
// Begin DPOT code
|
||||
#define GPU_UVD_DPOT_IIC_BUS (3)
|
||||
|
||||
#define GPU_UVD_DPOT_IIC_ADDRESS (0xA0)
|
||||
|
||||
/* Register addresses for GPU UVD DPOT */
|
||||
#define GPU_UVD_DPOT_IVRA (0x00)
|
||||
#define GPU_UVD_DPOT_IVRB (0x01)
|
||||
#define GPU_UVD_DPOT_ACR (0x10)
|
||||
|
||||
#define GPU_UVD_DPOT_READ_MISMATCH_ERROR (-2)
|
||||
#define GPU_UVD_DPOT_INVALID_WIPER_ERROR (-3)
|
||||
|
||||
typedef enum {
|
||||
GPU_UVD_DPOT_WIPER_A,
|
||||
GPU_UVD_DPOT_WIPER_B
|
||||
} gpu_uvd_dpot_wiper;
|
||||
|
||||
#if PRODUCT_LLB || PRODUCT_IBSS
|
||||
static void gpu_uvd_dpot_error(int error_code)
|
||||
{
|
||||
panic("GPU UVD: Error communicating with DPOT (%d)\n", error_code);
|
||||
}
|
||||
|
||||
static void gpu_uvd_dpot_poll_busy_bit(void)
|
||||
{
|
||||
int rc = 0;
|
||||
uint8_t read_data[2] = { 0 };
|
||||
uint8_t busy;
|
||||
|
||||
do {
|
||||
read_data[0] = GPU_UVD_DPOT_ACR;
|
||||
if ((rc = iic_read(GPU_UVD_DPOT_IIC_BUS, GPU_UVD_DPOT_IIC_ADDRESS, &read_data[0], 1, &read_data[1], 1, IIC_COMBINED)))
|
||||
gpu_uvd_dpot_error(rc);
|
||||
|
||||
busy = (read_data[1] >> 5) & 0x1;
|
||||
} while (busy);
|
||||
}
|
||||
|
||||
static uint8_t gpu_uvd_dpot_get_wiper_voltage(gpu_uvd_dpot_wiper wiper)
|
||||
{
|
||||
int rc = 0;
|
||||
uint8_t read_data[2] = { 0 };
|
||||
|
||||
switch (wiper) {
|
||||
case GPU_UVD_DPOT_WIPER_A:
|
||||
read_data[0] = GPU_UVD_DPOT_IVRA;
|
||||
break;
|
||||
case GPU_UVD_DPOT_WIPER_B:
|
||||
read_data[0] = GPU_UVD_DPOT_IVRB;
|
||||
break;
|
||||
default:
|
||||
gpu_uvd_dpot_error(GPU_UVD_DPOT_INVALID_WIPER_ERROR);
|
||||
}
|
||||
|
||||
if ((rc = iic_read(GPU_UVD_DPOT_IIC_BUS, GPU_UVD_DPOT_IIC_ADDRESS, &read_data[0], 1, &read_data[1], 1, IIC_COMBINED)))
|
||||
gpu_uvd_dpot_error(rc);
|
||||
|
||||
return read_data[1];
|
||||
}
|
||||
|
||||
static void gpu_uvd_dpot_set_wiper_voltage(gpu_uvd_dpot_wiper wiper, uint8_t wiper_voltage)
|
||||
{
|
||||
int rc = 0;
|
||||
uint8_t write_data[2];
|
||||
uint8_t written_wiper_voltage;
|
||||
|
||||
switch (wiper) {
|
||||
case GPU_UVD_DPOT_WIPER_A:
|
||||
write_data[0] = GPU_UVD_DPOT_IVRA;
|
||||
break;
|
||||
case GPU_UVD_DPOT_WIPER_B:
|
||||
write_data[0] = GPU_UVD_DPOT_IVRB;
|
||||
break;
|
||||
default:
|
||||
gpu_uvd_dpot_error(GPU_UVD_DPOT_INVALID_WIPER_ERROR);
|
||||
}
|
||||
|
||||
write_data[1] = wiper_voltage;
|
||||
|
||||
if ((rc = iic_write(GPU_UVD_DPOT_IIC_BUS, GPU_UVD_DPOT_IIC_ADDRESS, write_data, 2)))
|
||||
gpu_uvd_dpot_error(rc);
|
||||
|
||||
gpu_uvd_dpot_poll_busy_bit();
|
||||
|
||||
written_wiper_voltage = gpu_uvd_dpot_get_wiper_voltage(wiper);
|
||||
|
||||
if (written_wiper_voltage != write_data[1]) {
|
||||
dprintf(DEBUG_CRITICAL, "GPU UVD: Error writing to GPU_UVD_DPOT_WIPER%s. Expected (0x%x) but read (0x%x).\n",
|
||||
((wiper == GPU_UVD_DPOT_WIPER_A) ? "A" : "B"), write_data[1], written_wiper_voltage);
|
||||
gpu_uvd_dpot_error(GPU_UVD_DPOT_READ_MISMATCH_ERROR);
|
||||
}
|
||||
}
|
||||
|
||||
static bool gpu_uvd_dpot_is_nvmem_writable(void)
|
||||
{
|
||||
int rc = 0;
|
||||
uint8_t read_data[2] = { 0 };
|
||||
|
||||
read_data[0] = GPU_UVD_DPOT_ACR;
|
||||
|
||||
if ((rc = iic_read(GPU_UVD_DPOT_IIC_BUS, GPU_UVD_DPOT_IIC_ADDRESS, &read_data[0], 1, &read_data[1], 1, IIC_COMBINED)))
|
||||
gpu_uvd_dpot_error(rc);
|
||||
|
||||
return read_data[1] != 0xc0;
|
||||
}
|
||||
|
||||
static void gpu_uvd_dpot_set_nvmem_writable(bool enable)
|
||||
{
|
||||
// Clearing ACR[7] bit enables NV writes; ACR[6] always set to disable shutdown mode
|
||||
uint8_t acr_config = (enable) ? 0x40 : 0xc0;
|
||||
uint8_t write_data[2];
|
||||
uint8_t read_data[2];
|
||||
int rc = 0;
|
||||
|
||||
write_data[0] = GPU_UVD_DPOT_ACR;
|
||||
write_data[1] = acr_config;
|
||||
|
||||
if ((rc = iic_write(GPU_UVD_DPOT_IIC_BUS, GPU_UVD_DPOT_IIC_ADDRESS, write_data, 2)))
|
||||
gpu_uvd_dpot_error(rc);
|
||||
|
||||
gpu_uvd_dpot_poll_busy_bit();
|
||||
|
||||
read_data[0] = GPU_UVD_DPOT_ACR;
|
||||
if ((rc = iic_read(GPU_UVD_DPOT_IIC_BUS, GPU_UVD_DPOT_IIC_ADDRESS, &read_data[0], 1, &read_data[1], 1, IIC_COMBINED)))
|
||||
gpu_uvd_dpot_error(rc);
|
||||
|
||||
if (read_data[1] != write_data[1]) {
|
||||
dprintf(DEBUG_CRITICAL, "GPU UVD: Error writing to GPU_UVD_DPOT_ACR. Expected (0x%x) but read (0x%x).\n",
|
||||
write_data[1], read_data[1]);
|
||||
gpu_uvd_dpot_error(GPU_UVD_DPOT_READ_MISMATCH_ERROR);
|
||||
}
|
||||
}
|
||||
|
||||
static void gpu_uvd_dpot_init(void)
|
||||
{
|
||||
uint32_t wiper_voltage_a, wiper_voltage_b;
|
||||
uint32_t pmu_v_uvd_voltage;
|
||||
|
||||
// Get V4 voltage, convert to PMU VSEL, and convert back to mV to get actual PMU output for wiper equations
|
||||
pmu_v_uvd_voltage = chipid_get_gpu_voltage(CHIPID_GPU_VOLTAGE_V_UVD);
|
||||
platform_convert_voltages(BUCK_GPU, 1, &pmu_v_uvd_voltage);
|
||||
pmu_v_uvd_voltage = platform_get_dwi_to_mv(BUCK_GPU, pmu_v_uvd_voltage);
|
||||
|
||||
// Use 32-bit fixed point arithmetic with a scaling factor of 1e4 to determine wiper voltage codes
|
||||
// Take ceiling of integer division using ceiling(x/y) = truncate[(x + y - 1) / y]
|
||||
// Code_UVD,det = Code_WiperA = 1280.06 * (VSEL_P6,volts - 0.08) - 1216.51
|
||||
wiper_voltage_a = (128006 * pmu_v_uvd_voltage - 10240480 - 121651000 + 100000 - 1) / 100000;
|
||||
// Code_ARM,th = Code_WiperB = 1280.06 * (VSEL_P6,volts - 0.045) - 1216.51
|
||||
wiper_voltage_b = (128006 * pmu_v_uvd_voltage - 5760270 - 121651000 + 100000 - 1) / 100000;
|
||||
|
||||
gpio_write(GPIO_SOC2GPUUVD_EN, 1); // Enable GPU UVD system
|
||||
|
||||
spin(10000); // Wait 10 ms for GPU UVD setup
|
||||
|
||||
gpu_uvd_dpot_poll_busy_bit();
|
||||
|
||||
// Check to configure Wiper A (minimize EEPROM writes to maximize on 100k write cycle endurance)
|
||||
if (gpu_uvd_dpot_get_wiper_voltage(GPU_UVD_DPOT_WIPER_A) != wiper_voltage_a) {
|
||||
if (!gpu_uvd_dpot_is_nvmem_writable())
|
||||
gpu_uvd_dpot_set_nvmem_writable(true);
|
||||
|
||||
gpu_uvd_dpot_set_wiper_voltage(GPU_UVD_DPOT_WIPER_A, wiper_voltage_a);
|
||||
}
|
||||
|
||||
// Check to configure Wiper B
|
||||
if (gpu_uvd_dpot_get_wiper_voltage(GPU_UVD_DPOT_WIPER_B) != wiper_voltage_b) {
|
||||
if (!gpu_uvd_dpot_is_nvmem_writable())
|
||||
gpu_uvd_dpot_set_nvmem_writable(true);
|
||||
|
||||
gpu_uvd_dpot_set_wiper_voltage(GPU_UVD_DPOT_WIPER_B, wiper_voltage_b);
|
||||
}
|
||||
|
||||
// Check to disable non-volatile writes
|
||||
if (gpu_uvd_dpot_is_nvmem_writable())
|
||||
gpu_uvd_dpot_set_nvmem_writable(false);
|
||||
|
||||
gpio_write(GPIO_SOC2GPUUVD_EN, 0); // Disable GPU UVD system
|
||||
}
|
||||
#endif
|
||||
// End DPOT code
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
// Get the display panel type.
|
||||
ipad5c_get_display_info();
|
||||
|
||||
#if WITH_HW_POWER
|
||||
int rc;
|
||||
const uint32_t bid=platform_get_board_id();
|
||||
if ( bid == TARGET_BOARD_ID_J98DEV || bid == TARGET_BOARD_ID_J99DEV ) {
|
||||
rc = pmu_set_data(0, 0x040e, 0xc8, true);
|
||||
if ( rc!=0 ) dprintf(DEBUG_INFO, "pmu: write failed (%d)\n", rc);
|
||||
}
|
||||
#if PRODUCT_LLB || PRODUCT_IBSS
|
||||
// <rdar://problem/18601044> J99 EVT+ Hall-Effect Sensor IRQs change
|
||||
if (!target_config_ap() || (ipad5c_get_board_rev() > J99_EVT_PLUS_BOARD_REV)) {
|
||||
// GPIO11
|
||||
rc = pmu_set_data(0, 0x040a, 0xea, true);
|
||||
if (rc != 0) dprintf(DEBUG_INFO, "pmu: write failed (%d)\n", rc);
|
||||
|
||||
// GPIO13
|
||||
rc = pmu_set_data(0, 0x040c, 0xe8, true);
|
||||
if (rc != 0) dprintf(DEBUG_INFO, "pmu: write failed (%d)\n", rc);
|
||||
}
|
||||
#if 0
|
||||
// this change is making charge to not charge <rdar://problem/19146740>, disabling ...
|
||||
// for detecting VCENTER on Ganges rdar://18532953
|
||||
// set VSET to 3.73V allowing VCenter to 3.83 :: Vset + 100mV
|
||||
charger_set_data(3, 0x1f8, 0x00, true);
|
||||
charger_set_data(3, 0x1f9, 0x80, true);
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#if PRODUCT_LLB || PRODUCT_IBSS
|
||||
pmgr_update_dvfm(platform_get_board_id(),ipad5c_get_board_rev());
|
||||
pmgr_update_gfx_states(platform_get_board_id(),ipad5c_get_board_rev());
|
||||
|
||||
if (pmgr_check_gpu_use650MHz_binned(platform_get_board_id(), ipad5c_get_board_rev()) ||
|
||||
pmgr_check_gpu_use650MHz_unbinned(platform_get_board_id(), ipad5c_get_board_rev())) {
|
||||
gpu_uvd_dpot_init();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
//Check if board is deprecated
|
||||
if (check_is_board_deprecated && is_board_deprecated()) {
|
||||
platform_not_supported();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return platform_get_request_dfu2() && power_has_usb();
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
#if WITH_HW_POWER
|
||||
if (power_get_boot_flag() == kPowerBootFlagColdButton) *cold_button_boot = true;
|
||||
#else
|
||||
*cold_button_boot = false;
|
||||
#endif // WITH_HW_POWER
|
||||
|
||||
return !*cold_button_boot || platform_get_request_dfu1();
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
uint32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
void * target_get_display_configuration(void)
|
||||
{
|
||||
#if (APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC))
|
||||
switch(target_get_display_panel_type()){
|
||||
case DISPLAY_PANEL_TYPE_CAMELIA:
|
||||
dp.mode = 0x1;
|
||||
dp.type = 0x1;
|
||||
dp.min_link_rate = 0xa;
|
||||
dp.max_link_rate = 0xa;
|
||||
dp.lanes = 0x4;
|
||||
dp.ssc = 0x0;
|
||||
dp.alpm = 0x0;
|
||||
dp.vrr_enable = 0x1;
|
||||
dp.vrr_on = 0x0;
|
||||
dp.rx_n1= 0x0;
|
||||
dp.rx_n2= 0x0;
|
||||
dp.rx_n3= 0x0;
|
||||
dp.rx_n5= 0x0;
|
||||
dp.fast_link_training = true;
|
||||
break;
|
||||
case DISPLAY_PANEL_TYPE_TULIP:
|
||||
dp.mode = 0x1;
|
||||
dp.type = 0x1;
|
||||
dp.min_link_rate = 0xc;
|
||||
dp.max_link_rate = 0xc;
|
||||
dp.lanes = 0x4;
|
||||
dp.ssc = 0x0;
|
||||
dp.alpm = 0x1;
|
||||
dp.vrr_enable = 0x1;
|
||||
dp.vrr_on = 0x1;
|
||||
dp.rx_n1= 25;
|
||||
dp.rx_n2= 2;
|
||||
dp.rx_n3= 16030;
|
||||
dp.rx_n5= 0x0;
|
||||
dp.fast_link_training = true;
|
||||
break;
|
||||
}
|
||||
return ((void *)(&dp));
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
uint32_t panel_type_index;
|
||||
// boot-device is set in platform's init.c
|
||||
env_set("display-color-space","RGB888", 0);
|
||||
panel_type_index = target_get_display_panel_type();
|
||||
env_set("display-timing", display_panel_types[panel_type_index], 0);
|
||||
|
||||
if (panel_type_index == DISPLAY_PANEL_TYPE_CAMELIA) {
|
||||
env_set("adfe-tunables", "camelia", 0);
|
||||
env_set("adbe-tunables", "camelia", 0);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
// <rdar://problem/17365777> J99 Proto2: Update Device Tree to move BT & WiFi Enable Controls to the IOExpander
|
||||
void target_ipad5c_use_pmu_gpios_wlan_bt(void)
|
||||
{
|
||||
DTNode *node;
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
if (FindNode(0, WIFI_DTPATH, &node)) {
|
||||
//Fix reg on property
|
||||
propName = "function-reg_on_p1";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
memset(propName, 0, kPropNameLength);
|
||||
strlcpy(propName, "function-reg_on", kPropNameLength);
|
||||
}
|
||||
propName = "function-reg_on";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
// Disable the proto2 and greater property
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
|
||||
//Fix bluetooth
|
||||
if (FindNode(0, BT_DTPATH, &node)) {
|
||||
//Fix reg on property
|
||||
propName = "function-power_enable_p1";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
memset(propName, 0, kPropNameLength);
|
||||
strlcpy(propName, "function-power_enable", kPropNameLength);
|
||||
}
|
||||
propName = "function-power_enable";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
// Disable the proto2 and greater property
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
//disable the gpio expander driver
|
||||
if (FindNode(0, "arm-io/i2c3/tca7408", &node)) {
|
||||
propName = "compatible";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
// Disable the proto2 and greater property
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void hid_update_device_tree()
|
||||
{
|
||||
DTNode *node;
|
||||
char *propName;
|
||||
uint32_t propSize;
|
||||
void *propData;
|
||||
|
||||
|
||||
if (FindNode(0, "arm-io/spi1/multi-touch", &node)) {
|
||||
propName = "compatible";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
memset(propData, 0, propSize);
|
||||
strlcpy(propData, display_switch_types[display_switch], propSize);
|
||||
}
|
||||
if (display_switch != DISPLAY_SWITCH_TYPE_KONA) {
|
||||
//Fix up the device tree to support pre Kona touch
|
||||
propName = "function-clock_enable";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
propName = "function-clock_enPre3";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
strlcpy(propName, "function-clock_enable", strlen(propName)+1);
|
||||
}
|
||||
propName = "function-power_ana";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
propName = "function-power_pp3";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
strlcpy(propName, "function-power_ana", strlen(propName)+1);
|
||||
}
|
||||
} else {
|
||||
propName = "swd-flash-update";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
propName = "multitouch-to-display-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('MtDO', propData, propSize);
|
||||
}
|
||||
propName = "firefly-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('FfCl', propData, propSize);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//Remove when all HW prior to EVT is deprecated
|
||||
static void ipad5c_set_old_backlight_values(DTNode *node)
|
||||
{
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
propName = "milliAmps2DACPart1MaxCurrent";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
((uint32_t *)propData)[0] = 0x00030000;
|
||||
}
|
||||
propName = "milliAmps2DACPart2MaxCurrent";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
((uint32_t *)propData)[0] = 0x00140000;
|
||||
}
|
||||
propName = "calibratedMaxCurrent";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
((uint32_t *)propData)[0] = 0x0011E3D7;
|
||||
}
|
||||
propName = "calibratedMidCurrent";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
((uint32_t *)propData)[0] = 0x00068000;
|
||||
}
|
||||
propName = "mA2Nits2ndOrderCoef";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
((uint32_t *)propData)[0] = 0xFFFFFFF9;
|
||||
}
|
||||
propName = "mA2Nits1stOrderCoef";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
((uint32_t *)propData)[0] = 0x00000ED1;
|
||||
}
|
||||
propName = "mA2Nits0thOrderCoef";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
((uint32_t *)propData)[0] = 0xFFFFFFDC;
|
||||
}
|
||||
propName = "nits2mAmps2ndOrderCoef";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
((uint32_t *)propData)[0] = 0x0000A100;
|
||||
}
|
||||
propName = "nits2mAmps1stOrderCoef";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
((uint32_t *)propData)[0] = 0x00114042;
|
||||
}
|
||||
propName = "nits2mAmps0thOrderCoef";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
((uint32_t *)propData)[0] = 0x000002B7;
|
||||
}
|
||||
}
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
#if WITH_HW_DISPLAY_EDP
|
||||
DTNode *clcd_node = NULL, *backlight_node = NULL, *lcd_node = NULL;
|
||||
DTNode *lpdp_node = NULL;
|
||||
DTNode *node;
|
||||
#endif
|
||||
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
dt_node_t *dtnode;
|
||||
|
||||
#if WITH_HW_DISPLAY_EDP
|
||||
if (FindNode(0, DP_DTPATH, &node)) {
|
||||
extern int edp_update_device_tree(DTNode *edp_node, DTNode *lcd_node, DTNode *clcd_node, DTNode *backlight_node);
|
||||
FindNode(0, "arm-io/disp0", &clcd_node);
|
||||
FindNode(0, DP_DTPATH "/lcd", &lcd_node);
|
||||
FindNode(0, "backlight", &backlight_node);
|
||||
edp_update_device_tree(node, lcd_node, clcd_node, backlight_node);
|
||||
|
||||
extern int lpdp_phy_update_device_tree(DTNode *lpdp_node);
|
||||
FindNode(0, DPPHY_DTPATH, &lpdp_node);
|
||||
lpdp_phy_update_device_tree(lpdp_node);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Update the codec node with acoustic transducer scale data
|
||||
{
|
||||
uint8_t atscData[20];
|
||||
|
||||
if (syscfgCopyDataForTag('ATSc', atscData, sizeof(atscData)) > 0) {
|
||||
// Update codec
|
||||
if (FindNode(0, "arm-io/spi3/audio-codec", &node)) {
|
||||
propName = "at-scale-imic";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
memcpy(propData, &atscData[0], sizeof(uint32_t));
|
||||
}
|
||||
propName = "at-scale-smic";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
memcpy(propData, &atscData[4], sizeof(uint32_t));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Update the speaker calibration data
|
||||
if (FindNode(0, "arm-io/i2c1/audio-speaker0", &node)) {
|
||||
propName = "speaker-calib";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('SpCl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the als calibration data for all nodes that may be present on the dev board
|
||||
if (FindNode(0, "arm-io/i2c2/als1", &node)) {
|
||||
propName = "alsCalibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LSCI', propData, propSize);
|
||||
}
|
||||
}
|
||||
if (FindNode(0, "arm-io/i2c2/als2", &node)) {
|
||||
propName = "alsCalibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LSCI', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the backlight calibration data
|
||||
if (FindNode(0, "backlight", &node)) {
|
||||
propName = "backlight-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('BLCl', propData, propSize);
|
||||
}
|
||||
|
||||
//<rdar://problem/18433591> J99: Update screen brightness settings for EVT systems
|
||||
//Default is evt. Fix preevt
|
||||
if (ipad5c_get_board_rev() > J99_EVT_BOARD_REV) {
|
||||
ipad5c_set_old_backlight_values(node);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the compass calibration data
|
||||
if (FindNode(0, "arm-io/uart7/oscar/compass", &node)) {
|
||||
propName = "compass-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('CPAS', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the gyro calibration data
|
||||
if (FindNode(0, "arm-io/uart7/oscar/gyro", &node)) {
|
||||
propName = "gyro-orientation";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GRot', propData, propSize);
|
||||
}
|
||||
propName = "gyro-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GSCl', propData, propSize);
|
||||
}
|
||||
propName = "gyro-temp-table";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GYTT', propData, propSize);
|
||||
}
|
||||
propName = "gyro-interrupt-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GICl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update accelerometer calibration data
|
||||
if (FindNode(0, "arm-io/uart7/oscar/accelerometer", &node)) {
|
||||
propName = "accel-orientation";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ARot', propData, propSize);
|
||||
}
|
||||
propName = "low-temp-accel-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LTAO', propData, propSize);
|
||||
}
|
||||
propName = "accel-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ASCl', propData, propSize);
|
||||
}
|
||||
propName = "accel-interrupt-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('AICl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update pressure sensor calibration data
|
||||
if (FindNode(0, "arm-io/uart7/oscar/pressure", &node)) {
|
||||
propName = "pressure-offset-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('SPPO', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// WLAN Capri A0 workarounds -- !!!FIXME!!! Remove this when Capri A0 is deprecated
|
||||
// <rdar://problem/16597296> Remove Capri A0 PCIe hacks
|
||||
if (FindNode(0, "arm-io/apcie/pci-bridge1/wlan", &node)) {
|
||||
if (chipid_get_chip_revision() > CHIP_REVISION_A0) {
|
||||
// Disable workarounds for Capri A1 and later.
|
||||
propName = "acpie-l1ss-workaround";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
propName = "pci-wake-l1pm-disable";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
} else {
|
||||
// Fix up the hacks for Capri A0
|
||||
propName = "pci-l1pm-control";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
propName = "pci-l1pm-control-a0";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propName[16] = '\0';
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
const uint32_t board_id = platform_get_board_id();
|
||||
// IO expander GPIO 4 is not used on EVT2, so disable function-acc_sw_en.
|
||||
if ((board_id == TARGET_BOARD_ID_J98AP || board_id == TARGET_BOARD_ID_J99AP) && (ipad5c_get_board_rev() <= J99_EVT2_BOARD_REV)) {
|
||||
if (FindNode(0, "dock-orion", &node)) {
|
||||
propName = "function-acc_sw_en";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
} else {
|
||||
// Undo IO expander otp-data values in device tree, which were set for EVT2.
|
||||
if (FindNode(0, "arm-io/i2c3/tca7408", &node)) {
|
||||
propName = "otp-data";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
((uint32_t *)propData)[0] = 0xff000000;
|
||||
((uint32_t *)propData)[1] = 0x00000000;
|
||||
}
|
||||
}
|
||||
}
|
||||
/*
|
||||
* Need to support HW which does not have the GPIO Expander.
|
||||
* HW before Proto2 do not have the expander
|
||||
* HW before Dev2 do not have the expander
|
||||
*/
|
||||
if (((board_id == TARGET_BOARD_ID_J98AP || board_id == TARGET_BOARD_ID_J99AP) && (ipad5c_get_board_rev() >= J99_PROTO1_BOARD_REV_CHINA)) ||
|
||||
((board_id == TARGET_BOARD_ID_J98DEV || board_id == TARGET_BOARD_ID_J99DEV) && (ipad5c_get_board_rev() < J98_DEV2_BOARD_REV))) {
|
||||
target_ipad5c_use_pmu_gpios_wlan_bt();
|
||||
}
|
||||
|
||||
// EVT2 (or dev boards with dip switches set to EVT2) will use the micro based Orion
|
||||
// Older revs will continue to support TriStar based Orion for bring-up
|
||||
if (ipad5c_get_board_rev() == J99_EVT2_BOARD_REV) {
|
||||
// Enable Micro Orion
|
||||
if (dt_find_node(0, "arm-io/i2c1/orion-ic", &dtnode)) {
|
||||
propName = "AAPL,ignore";
|
||||
if (dt_get_prop(dtnode, &propName, &propData, &propSize)) {
|
||||
dt_remove_prop(dtnode, propName);
|
||||
}
|
||||
}
|
||||
// Enable aod flashing of Orion's FW
|
||||
if (dt_find_node(0, "arm-io/aod4", &dtnode)) {
|
||||
propName = "AAPL,ignore";
|
||||
if (dt_get_prop(dtnode, &propName, &propData, &propSize)) {
|
||||
dt_remove_prop(dtnode, propName);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
// Enable TriStar Orion
|
||||
if (dt_find_node(0, "arm-io/i2c1/tristar-orion", &dtnode)) {
|
||||
propName = "AAPL,ignore";
|
||||
if (dt_get_prop(dtnode, &propName, &propData, &propSize)) {
|
||||
dt_remove_prop(dtnode, propName);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
hid_update_device_tree();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif // WITH_DEVICETREE
|
||||
|
||||
#if WITH_PAINT
|
||||
|
||||
// The default background is expected to to be black and the artwork is expected
|
||||
// to be white. This arrangement will be inverted depending upon the cover glass
|
||||
// color of the device.
|
||||
|
||||
// Sample DClr_override values for testing devices without DClr syscfg entries (enclosure/cover glass):
|
||||
// gray/black: setenv DClr_override 000200009B9899003C3B3B0000000000
|
||||
// silver/white: setenv DClr_override 00020000D8D9D700E3E4E10000000000
|
||||
|
||||
static color_policy_invert_t target_cover_glass_color_table[] = {
|
||||
{ RGB( 59, 59, 60), false }, // Black - black background, white logo
|
||||
{ RGB(225, 228, 227), true }, // White - white background, black logo
|
||||
};
|
||||
|
||||
color_policy_t *target_color_map_init(enum colorspace cs, color_policy_t *color_policy)
|
||||
{
|
||||
// Must have a color policy structure passed in.
|
||||
if (color_policy == NULL)
|
||||
goto fail;
|
||||
|
||||
// We only support the RGB888 colorspace.
|
||||
if (cs != CS_RGB888)
|
||||
goto fail;
|
||||
|
||||
color_policy->policy_type = COLOR_MAP_POLICY_INVERT;
|
||||
color_policy->color_table = (void *)target_cover_glass_color_table;
|
||||
color_policy->color_count = ARRAY_SIZE(target_cover_glass_color_table);
|
||||
color_policy->map_color = NULL; // Use standard remapper
|
||||
|
||||
return color_policy;
|
||||
|
||||
fail:
|
||||
return NULL;
|
||||
}
|
||||
#endif // WITH_PAINT
|
||||
@@ -0,0 +1,83 @@
|
||||
/*
|
||||
* Copyright (C) 2009-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <target.h>
|
||||
#include <target/boardid.h>
|
||||
|
||||
extern uint32_t ipad5c_get_board_rev(void);
|
||||
extern const uint32_t* target_get_proto2_gpio_cfg(uint32_t gpioc);
|
||||
extern const uint32_t* target_get_proto3_gpio_cfg(uint32_t gpioc);
|
||||
extern const uint32_t* target_get_evt_gpio_cfg(uint32_t gpioc);
|
||||
extern const uint32_t* target_get_evt2_gpio_cfg(uint32_t gpioc);
|
||||
|
||||
extern bool check_is_board_deprecated;
|
||||
|
||||
static bool board_rev_determined;
|
||||
static bool use_dummy_pinconfig;
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
// HACK: -- the first call into target_get_default_gpio_cfg() reads
|
||||
// and attempts to restore BOARD_REV[3:0] to GPIO_CFG_DEFAULT.
|
||||
//
|
||||
// This will result in a recursive call back into target_get_default_gpio_cfg.
|
||||
// To break the recursion, while determining board rev we can reply with any pinconfig
|
||||
// since it's only being used for BOARD_REV[3:0] and it's CFG_DISABLED in all pinconfigs
|
||||
//
|
||||
// Remove this after we no longer have BOARD_REV-dependent pinconfigs.
|
||||
if (use_dummy_pinconfig)
|
||||
{
|
||||
return target_get_evt_gpio_cfg(gpioc);
|
||||
}
|
||||
if (!board_rev_determined)
|
||||
{
|
||||
use_dummy_pinconfig = true;
|
||||
(void)ipad5c_get_board_rev();
|
||||
use_dummy_pinconfig = false;
|
||||
|
||||
board_rev_determined = true;
|
||||
}
|
||||
|
||||
if (!target_config_ap()) {
|
||||
//For dev boards, just use the current settings for proto 1 until it changes
|
||||
switch (ipad5c_get_board_rev()) {
|
||||
case J98_DEV2_BOARD_REV:
|
||||
return target_get_proto3_gpio_cfg(gpioc);
|
||||
|
||||
default:
|
||||
goto fail;
|
||||
}
|
||||
} else {
|
||||
// Current AP products have several pinconfigs depending on board revision.
|
||||
switch (ipad5c_get_board_rev()) {
|
||||
case J99_PROTO2_BOARD_REV:
|
||||
return target_get_proto2_gpio_cfg(gpioc);
|
||||
|
||||
case J99_PROTO3_BOARD_REV:
|
||||
case J99_PROTO3_P9_BOARD_REV:
|
||||
return target_get_proto3_gpio_cfg(gpioc);
|
||||
case J99_EVT_BOARD_REV:
|
||||
return target_get_evt_gpio_cfg(gpioc);
|
||||
case J99_EVT2_BOARD_REV:
|
||||
return target_get_evt2_gpio_cfg(gpioc);
|
||||
default:
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
fail:
|
||||
//Allow more of the HW to get far enough to detect a deprecated board
|
||||
check_is_board_deprecated = true;
|
||||
|
||||
return target_get_evt_gpio_cfg(gpioc);
|
||||
}
|
||||
@@ -0,0 +1,989 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: rev 3.5.0
|
||||
I/O Spreadsheet tracker: 19787800
|
||||
Conversion command: csvtopinconfig.py --soc capri --prefix evt --config-column 'j99:J99 Config' --config-column 'j98:J98 Config' --pupd-column 'j99:J99 PU/PD' --pupd-column 'j98:J98 PU/PD' --copyright 2013-2015 --radar 19787800 <filename>
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
#include <target/boardid.h>
|
||||
|
||||
static const uint32_t pinconfig_evt_j98ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BB_TX
|
||||
CFG_DISABLED | PULL_DOWN, // 15 : UART3_RXD -> UART_BB2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_DISABLED | PULL_DOWN, // 33 : UART3_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_CODEC_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_OUT_1 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 53 : TMR32_PWM1 -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_IN, // 54 : TMR32_PWM2 -> GPUUVD2SOC_OUT_L
|
||||
CFG_OUT_0 | PULL_DOWN | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC
|
||||
CFG_DISABLED | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_IN | PULL_UP, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 63 : UART7_TXD -> UART_SOC2OSCAR_TX
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0, // 64 : UART7_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN, // 70 : SPI0_SSIN -> GPIO_TS2ORIONSOC2PMU_IRQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 80 : GPIO[0] -> GPIO_SOC2GPUUVD_EN
|
||||
CFG_OUT_1 | SLOW_SLEW, // 81 : GPIO[1] -> GPIO_SOC2TT_XBAR_EN_PULSE_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_OUT_1 | SLOW_SLEW, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_IN, // 88 : GPIO[8] -> GPIO_GANGES2SOC2PMU_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2CODEC_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 94 : GPIO[14] -> GPIO_SOC2TT_SW_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : GPIO[19] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED | PULL_DOWN, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_TT2SOC_SMI_L
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_RC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_DISABLED | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_DISABLED | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_DISABLED | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2USBPDMCU_TX
|
||||
CFG_DISABLED, // 123 : UART8_RXD -> UART_USBPDMCU2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BT2SOC_TX
|
||||
CFG_OUT_1 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BT2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 156 : SPI1_MISO -> SPI_GRAPE_MISO
|
||||
CFG_OUT_1 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_24M
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0, // 160 : ULPI_STP -> SOC2USBPDMCU_RESET_L
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_IN, // 167 : ULPI_DATA[3] -> USBPDMCU2SOC_IRQ
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 175 : PCIE_CLKREQ2_N -> NC_PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_IN, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> NC
|
||||
CFG_OUT_0 | SLOW_SLEW, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> NC_PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> GPIO_DEVDOG_DETECT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_FUNC0 | SLOW_SLEW, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_evt_j98dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BB_TX
|
||||
CFG_DISABLED | PULL_DOWN, // 15 : UART3_RXD -> UART_BB2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_DISABLED | PULL_DOWN, // 33 : UART3_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_CODEC_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_OUT_1 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 53 : TMR32_PWM1 -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_IN, // 54 : TMR32_PWM2 -> GPUUVD2SOC_OUT_L
|
||||
CFG_OUT_0 | PULL_DOWN | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC
|
||||
CFG_DISABLED | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_IN | PULL_UP, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 63 : UART7_TXD -> UART_SOC2OSCAR_TX
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0, // 64 : UART7_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN, // 70 : SPI0_SSIN -> GPIO_TS2ORIONSOC2PMU_IRQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 80 : GPIO[0] -> GPIO_SOC2GPUUVD_EN
|
||||
CFG_OUT_1 | SLOW_SLEW, // 81 : GPIO[1] -> GPIO_SOC2TT_XBAR_EN_PULSE_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_OUT_1 | SLOW_SLEW, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_IN, // 88 : GPIO[8] -> GPIO_GANGES2SOC2PMU_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2CODEC_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 94 : GPIO[14] -> GPIO_SOC2TT_SW_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : GPIO[19] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED | PULL_DOWN, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_TT2SOC_SMI_L
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_RC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_DISABLED | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_DISABLED | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2USBPDMCU_TX
|
||||
CFG_DISABLED, // 123 : UART8_RXD -> UART_USBPDMCU2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BT2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BT2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 156 : SPI1_MISO -> SPI_GRAPE_MISO
|
||||
CFG_OUT_1 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_24M
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0, // 160 : ULPI_STP -> SOC2USBPDMCU_RESET_L
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_IN, // 167 : ULPI_DATA[3] -> USBPDMCU2SOC_IRQ
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 175 : PCIE_CLKREQ2_N -> NC_PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_IN, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> NC
|
||||
CFG_OUT_0 | SLOW_SLEW, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> NC_PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> GPIO_DEVDOG_DETECT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_evt_j99ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_IN | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BB_TX
|
||||
CFG_FUNC0, // 15 : UART3_RXD -> UART_BB2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_IN | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_FUNC0, // 33 : UART3_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_CODEC_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_OUT_1 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 53 : TMR32_PWM1 -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_IN, // 54 : TMR32_PWM2 -> GPUUVD2SOC_OUT_L
|
||||
CFG_OUT_0 | PULL_DOWN | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC
|
||||
CFG_DISABLED | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_IN | PULL_UP, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 63 : UART7_TXD -> UART_SOC2OSCAR_TX
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0, // 64 : UART7_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN, // 70 : SPI0_SSIN -> GPIO_TS2ORIONSOC2PMU_IRQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 80 : GPIO[0] -> GPIO_SOC2GPUUVD_EN
|
||||
CFG_OUT_1 | SLOW_SLEW, // 81 : GPIO[1] -> GPIO_SOC2TT_XBAR_EN_PULSE_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_OUT_1 | SLOW_SLEW, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_IN, // 88 : GPIO[8] -> GPIO_GANGES2SOC2PMU_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2CODEC_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 94 : GPIO[14] -> GPIO_SOC2TT_SW_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : GPIO[19] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_IN | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_TT2SOC_SMI_L
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_RC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_IN | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_OUT_0 | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_IN | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_IN | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2USBPDMCU_TX
|
||||
CFG_FUNC0, // 123 : UART8_RXD -> UART_USBPDMCU2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BT2SOC_TX
|
||||
CFG_OUT_1 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BT2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 156 : SPI1_MISO -> SPI_GRAPE_MISO
|
||||
CFG_OUT_1 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_24M
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0, // 160 : ULPI_STP -> SOC2USBPDMCU_RESET_L
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_IN, // 167 : ULPI_DATA[3] -> USBPDMCU2SOC_IRQ
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 175 : PCIE_CLKREQ2_N -> NC_PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_IN, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> NC
|
||||
CFG_OUT_0 | SLOW_SLEW, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> NC_PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> GPIO_DEVDOG_DETECT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_FUNC0 | SLOW_SLEW, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_evt_j99dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BB_TX
|
||||
CFG_FUNC0, // 15 : UART3_RXD -> UART_BB2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_FUNC0, // 33 : UART3_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_CODEC_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_OUT_1 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 53 : TMR32_PWM1 -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_IN, // 54 : TMR32_PWM2 -> GPUUVD2SOC_OUT_L
|
||||
CFG_OUT_0 | PULL_DOWN | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC
|
||||
CFG_DISABLED | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_IN | PULL_UP, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 63 : UART7_TXD -> UART_SOC2OSCAR_TX
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0, // 64 : UART7_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN, // 70 : SPI0_SSIN -> GPIO_TS2ORIONSOC2PMU_IRQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 80 : GPIO[0] -> GPIO_SOC2GPUUVD_EN
|
||||
CFG_OUT_1 | SLOW_SLEW, // 81 : GPIO[1] -> GPIO_SOC2TT_XBAR_EN_PULSE_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_OUT_1 | SLOW_SLEW, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_IN, // 88 : GPIO[8] -> GPIO_GANGES2SOC2PMU_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2CODEC_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 94 : GPIO[14] -> GPIO_SOC2TT_SW_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : GPIO[19] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_IN | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_TT2SOC_SMI_L
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_RC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_IN | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_OUT_0 | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_IN | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_IN | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2USBPDMCU_TX
|
||||
CFG_FUNC0, // 123 : UART8_RXD -> UART_USBPDMCU2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BT2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BT2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 156 : SPI1_MISO -> SPI_GRAPE_MISO
|
||||
CFG_OUT_1 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_24M
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0, // 160 : ULPI_STP -> SOC2USBPDMCU_RESET_L
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_IN, // 167 : ULPI_DATA[3] -> USBPDMCU2SOC_IRQ
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 175 : PCIE_CLKREQ2_N -> NC_PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_IN, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> NC
|
||||
CFG_OUT_0 | SLOW_SLEW, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> NC_PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> GPIO_DEVDOG_DETECT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
};
|
||||
|
||||
struct pinconfig_map {
|
||||
uint32_t board_id;
|
||||
uint32_t board_id_mask;
|
||||
const uint32_t *pinconfigs[GPIOC_COUNT];
|
||||
};
|
||||
|
||||
static const struct pinconfig_map cfg_map[] = {
|
||||
{ TARGET_BOARD_ID_J98AP, ~0, { pinconfig_evt_j98ap_0 } },
|
||||
{ TARGET_BOARD_ID_J98DEV, ~0, { pinconfig_evt_j98dev_0 } },
|
||||
{ TARGET_BOARD_ID_J99AP, ~0, { pinconfig_evt_j99ap_0 } },
|
||||
{ TARGET_BOARD_ID_J99DEV, ~0, { pinconfig_evt_j99dev_0 } },
|
||||
};
|
||||
|
||||
const uint32_t * target_get_evt_gpio_cfg(int gpioc)
|
||||
{
|
||||
static const struct pinconfig_map *selected_map = NULL;
|
||||
|
||||
if (selected_map == NULL) {
|
||||
uint32_t board_id = platform_get_board_id();
|
||||
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
|
||||
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
|
||||
selected_map = &cfg_map[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (selected_map == NULL)
|
||||
panic("no default pinconfig for board id %u", board_id);
|
||||
}
|
||||
|
||||
ASSERT(gpioc < GPIOC_COUNT);
|
||||
return selected_map->pinconfigs[gpioc];
|
||||
}
|
||||
@@ -0,0 +1,989 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: rev 4.3.0
|
||||
I/O Spreadsheet tracker: 19473089
|
||||
Conversion command: csvtopinconfig.py --soc capri --prefix evt2 --config-column 'j99:J99 Config' --config-column 'j98:J98 Config' --pupd-column 'j99:J99 PU/PD' --pupd-column 'j98:J98 PU/PD' --copyright 2015 --radar 19473089 <filename>
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
#include <target/boardid.h>
|
||||
|
||||
static const uint32_t pinconfig_evt2_j98ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BB_TX
|
||||
CFG_DISABLED | PULL_DOWN, // 15 : UART3_RXD -> UART_BB2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_DISABLED | PULL_DOWN, // 33 : UART3_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_CODEC_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_OUT_1 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 53 : TMR32_PWM1 -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_IN, // 54 : TMR32_PWM2 -> GPUUVD2SOC_OUT_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 55 : DISP_VSYNC -> ORIONMCU_SWDIO_1V8
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC
|
||||
CFG_DISABLED | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_IN | PULL_UP, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 63 : UART7_TXD -> UART_SOC2OSCAR_TX
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0, // 64 : UART7_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN, // 70 : SPI0_SSIN -> GPIO_TS2ORIONSOC2PMU_IRQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 80 : GPIO[0] -> GPIO_SOC2GPUUVD_EN
|
||||
CFG_OUT_1 | SLOW_SLEW, // 81 : GPIO[1] -> GPIO_SOC2TT_XBAR_EN_PULSE_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_OUT_1 | SLOW_SLEW, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_IN, // 88 : GPIO[8] -> GPIO_GANGES2SOC2PMU_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2CODEC_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 94 : GPIO[14] -> GPIO_SOC2TT_SW_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : GPIO[19] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED | PULL_DOWN, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_TT2SOC_SMI_L
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_RC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_DISABLED | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_DISABLED | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 122 : UART8_TXD -> SOC2USBPDMCU_SWCLK
|
||||
CFG_DISABLED, // 123 : UART8_RXD -> SOC2USBPDMCU_SWDIO
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BT2SOC_TX
|
||||
CFG_OUT_1 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BT2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 156 : SPI1_MISO -> SPI_GRAPE_MISO
|
||||
CFG_OUT_1 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 158 : CLK32K_OUT -> ORIONMCU_SWCLK_1V8
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0, // 160 : ULPI_STP -> SOC2USBPDMCU_RESET_L
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_IN, // 167 : ULPI_DATA[3] -> USBPDMCU2SOC_IRQ
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 175 : PCIE_CLKREQ2_N -> NC_PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_IN, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> NC
|
||||
CFG_OUT_0 | SLOW_SLEW, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> NC_PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> GPIO_DEVDOG_DETECT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_FUNC0 | SLOW_SLEW, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_evt2_j98dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BB_TX
|
||||
CFG_DISABLED | PULL_DOWN, // 15 : UART3_RXD -> UART_BB2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_DISABLED | PULL_DOWN, // 33 : UART3_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_CODEC_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_OUT_1 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 53 : TMR32_PWM1 -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_IN, // 54 : TMR32_PWM2 -> GPUUVD2SOC_OUT_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 55 : DISP_VSYNC -> ORIONMCU_SWDIO_1V8
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC
|
||||
CFG_DISABLED | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_IN | PULL_UP, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 63 : UART7_TXD -> UART_SOC2OSCAR_TX
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0, // 64 : UART7_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN, // 70 : SPI0_SSIN -> GPIO_TS2ORIONSOC2PMU_IRQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 80 : GPIO[0] -> GPIO_SOC2GPUUVD_EN
|
||||
CFG_OUT_1 | SLOW_SLEW, // 81 : GPIO[1] -> GPIO_SOC2TT_XBAR_EN_PULSE_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_OUT_1 | SLOW_SLEW, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_IN, // 88 : GPIO[8] -> GPIO_GANGES2SOC2PMU_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2CODEC_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 94 : GPIO[14] -> GPIO_SOC2TT_SW_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : GPIO[19] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED | PULL_DOWN, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_TT2SOC_SMI_L
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_RC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_DISABLED | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_DISABLED | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 122 : UART8_TXD -> SOC2USBPDMCU_SWCLK
|
||||
CFG_DISABLED, // 123 : UART8_RXD -> SOC2USBPDMCU_SWDIO
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BT2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BT2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 156 : SPI1_MISO -> SPI_GRAPE_MISO
|
||||
CFG_OUT_1 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 158 : CLK32K_OUT -> ORIONMCU_SWCLK_1V8
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0, // 160 : ULPI_STP -> SOC2USBPDMCU_RESET_L
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_IN, // 167 : ULPI_DATA[3] -> USBPDMCU2SOC_IRQ
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 175 : PCIE_CLKREQ2_N -> NC_PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_IN, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> NC
|
||||
CFG_OUT_0 | SLOW_SLEW, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> NC_PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> GPIO_DEVDOG_DETECT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_evt2_j99ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_IN | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BB_TX
|
||||
CFG_FUNC0, // 15 : UART3_RXD -> UART_BB2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_IN | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_FUNC0, // 33 : UART3_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_CODEC_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_OUT_1 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 53 : TMR32_PWM1 -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_IN, // 54 : TMR32_PWM2 -> GPUUVD2SOC_OUT_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 55 : DISP_VSYNC -> ORIONMCU_SWDIO_1V8
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC
|
||||
CFG_DISABLED | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_IN | PULL_UP, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 63 : UART7_TXD -> UART_SOC2OSCAR_TX
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0, // 64 : UART7_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN, // 70 : SPI0_SSIN -> GPIO_TS2ORIONSOC2PMU_IRQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 80 : GPIO[0] -> GPIO_SOC2GPUUVD_EN
|
||||
CFG_OUT_1 | SLOW_SLEW, // 81 : GPIO[1] -> GPIO_SOC2TT_XBAR_EN_PULSE_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_OUT_1 | SLOW_SLEW, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_IN, // 88 : GPIO[8] -> GPIO_GANGES2SOC2PMU_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2CODEC_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 94 : GPIO[14] -> GPIO_SOC2TT_SW_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : GPIO[19] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_IN | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_TT2SOC_SMI_L
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_RC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_IN | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_OUT_0 | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_IN | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_IN | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 122 : UART8_TXD -> SOC2USBPDMCU_SWCLK
|
||||
CFG_DISABLED, // 123 : UART8_RXD -> SOC2USBPDMCU_SWDIO
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BT2SOC_TX
|
||||
CFG_OUT_1 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BT2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 156 : SPI1_MISO -> SPI_GRAPE_MISO
|
||||
CFG_OUT_1 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 158 : CLK32K_OUT -> ORIONMCU_SWCLK_1V8
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0, // 160 : ULPI_STP -> SOC2USBPDMCU_RESET_L
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_IN, // 167 : ULPI_DATA[3] -> USBPDMCU2SOC_IRQ
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 175 : PCIE_CLKREQ2_N -> NC_PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_IN, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> NC
|
||||
CFG_OUT_0 | SLOW_SLEW, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> NC_PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> GPIO_DEVDOG_DETECT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_FUNC0 | SLOW_SLEW, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_evt2_j99dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BB_TX
|
||||
CFG_FUNC0, // 15 : UART3_RXD -> UART_BB2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_FUNC0, // 33 : UART3_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_CODEC_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_OUT_1 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 53 : TMR32_PWM1 -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_IN, // 54 : TMR32_PWM2 -> GPUUVD2SOC_OUT_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 55 : DISP_VSYNC -> ORIONMCU_SWDIO_1V8
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC
|
||||
CFG_DISABLED | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_IN | PULL_UP, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 63 : UART7_TXD -> UART_SOC2OSCAR_TX
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0, // 64 : UART7_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN, // 70 : SPI0_SSIN -> GPIO_TS2ORIONSOC2PMU_IRQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 80 : GPIO[0] -> GPIO_SOC2GPUUVD_EN
|
||||
CFG_OUT_1 | SLOW_SLEW, // 81 : GPIO[1] -> GPIO_SOC2TT_XBAR_EN_PULSE_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_OUT_1 | SLOW_SLEW, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_IN, // 88 : GPIO[8] -> GPIO_GANGES2SOC2PMU_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2CODEC_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 94 : GPIO[14] -> GPIO_SOC2TT_SW_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : GPIO[19] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_IN | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_TT2SOC_SMI_L
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_RC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_IN | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_OUT_0 | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_IN | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_IN | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 122 : UART8_TXD -> SOC2USBPDMCU_SWCLK
|
||||
CFG_DISABLED, // 123 : UART8_RXD -> SOC2USBPDMCU_SWDIO
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BT2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BT2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 156 : SPI1_MISO -> SPI_GRAPE_MISO
|
||||
CFG_OUT_1 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 158 : CLK32K_OUT -> ORIONMCU_SWCLK_1V8
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0, // 160 : ULPI_STP -> SOC2USBPDMCU_RESET_L
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_IN, // 167 : ULPI_DATA[3] -> USBPDMCU2SOC_IRQ
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 175 : PCIE_CLKREQ2_N -> NC_PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_IN, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> NC
|
||||
CFG_OUT_0 | SLOW_SLEW, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> NC_PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> GPIO_DEVDOG_DETECT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
};
|
||||
|
||||
struct pinconfig_map {
|
||||
uint32_t board_id;
|
||||
uint32_t board_id_mask;
|
||||
const uint32_t *pinconfigs[GPIOC_COUNT];
|
||||
};
|
||||
|
||||
static const struct pinconfig_map cfg_map[] = {
|
||||
{ TARGET_BOARD_ID_J98AP, ~0, { pinconfig_evt2_j98ap_0 } },
|
||||
{ TARGET_BOARD_ID_J98DEV, ~0, { pinconfig_evt2_j98dev_0 } },
|
||||
{ TARGET_BOARD_ID_J99AP, ~0, { pinconfig_evt2_j99ap_0 } },
|
||||
{ TARGET_BOARD_ID_J99DEV, ~0, { pinconfig_evt2_j99dev_0 } },
|
||||
};
|
||||
|
||||
const uint32_t * target_get_evt2_gpio_cfg(int gpioc)
|
||||
{
|
||||
static const struct pinconfig_map *selected_map = NULL;
|
||||
|
||||
if (selected_map == NULL) {
|
||||
uint32_t board_id = platform_get_board_id();
|
||||
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
|
||||
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
|
||||
selected_map = &cfg_map[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (selected_map == NULL)
|
||||
panic("no default pinconfig for board id %u", board_id);
|
||||
}
|
||||
|
||||
ASSERT(gpioc < GPIOC_COUNT);
|
||||
return selected_map->pinconfigs[gpioc];
|
||||
}
|
||||
@@ -0,0 +1,989 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: rev 1.14.0
|
||||
I/O Spreadsheet tracker: None
|
||||
Conversion command: csvtopinconfig.py --soc capri --prefix proto2 --config-column 'j99:J99 Config' --config-column 'j98:J98 Config' --pupd-column 'j99:J99 PU/PD' --pupd-column 'j98:J98 PU/PD' --copyright 2013-2014 <filename>
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
#include <target/boardid.h>
|
||||
|
||||
static const uint32_t pinconfig_proto2_j98ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BB_TX
|
||||
CFG_DISABLED | PULL_DOWN, // 15 : UART3_RXD -> UART_BB2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_DISABLED | PULL_DOWN, // 33 : UART3_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_CODEC_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_OUT_1 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 53 : TMR32_PWM1 -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_DISABLED | PULL_DOWN, // 54 : TMR32_PWM2 -> NC_JTAG_BB_TCK
|
||||
CFG_OUT_0 | PULL_DOWN | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC
|
||||
CFG_DISABLED | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_IN | PULL_UP, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 63 : UART7_TXD -> UART_SOC2OSCAR_TX
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0, // 64 : UART7_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN, // 70 : SPI0_SSIN -> GPIO_TS2ORIONSOC2PMU_IRQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 80 : GPIO[0] -> GPIO_SOC2TT_MUX_SEL
|
||||
CFG_OUT_1 | SLOW_SLEW, // 81 : GPIO[1] -> GPIO_SOC2TT_XBAR_EN_PULSE_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_OUT_1 | SLOW_SLEW, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_IN, // 88 : GPIO[8] -> GPIO_GANGES2SOC2PMU_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2CODEC_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 94 : GPIO[14] -> GPIO_SOC2TT_SW_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : GPIO[19] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED | PULL_DOWN, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_TT2SOC_SMI_L
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_RC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_DISABLED | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_DISABLED | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_DISABLED | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2USBPDMCU_TX
|
||||
CFG_DISABLED, // 123 : UART8_RXD -> UART_USBPDMCU2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BT2SOC_TX
|
||||
CFG_OUT_1 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BT2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 156 : SPI1_MISO -> SPI_GRAPE_MISO
|
||||
CFG_OUT_1 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_DISABLED, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_24M
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0, // 160 : ULPI_STP -> SOC2USBPDMCU_RESET_L
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_IN | PULL_DOWN, // 167 : ULPI_DATA[3] -> USBPDMCU2SOC_IRQ
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 175 : PCIE_CLKREQ2_N -> NC_PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> NC
|
||||
CFG_OUT_0 | SLOW_SLEW, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> NC_PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> GPIO_DEVDOG_DETECT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_FUNC0 | SLOW_SLEW, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_proto2_j98dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BB_TX
|
||||
CFG_DISABLED | PULL_DOWN, // 15 : UART3_RXD -> UART_BB2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_DISABLED | PULL_DOWN, // 33 : UART3_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_CODEC_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_OUT_1 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 53 : TMR32_PWM1 -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_DISABLED | PULL_DOWN, // 54 : TMR32_PWM2 -> NC_JTAG_BB_TCK
|
||||
CFG_OUT_0 | PULL_DOWN | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC
|
||||
CFG_DISABLED | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_IN | PULL_UP, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 63 : UART7_TXD -> UART_SOC2OSCAR_TX
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0, // 64 : UART7_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN, // 70 : SPI0_SSIN -> GPIO_TS2ORIONSOC2PMU_IRQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 80 : GPIO[0] -> GPIO_SOC2TT_MUX_SEL
|
||||
CFG_OUT_1 | SLOW_SLEW, // 81 : GPIO[1] -> GPIO_SOC2TT_XBAR_EN_PULSE_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_OUT_1 | SLOW_SLEW, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_IN, // 88 : GPIO[8] -> GPIO_GANGES2SOC2PMU_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2CODEC_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 94 : GPIO[14] -> GPIO_SOC2TT_SW_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : GPIO[19] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED | PULL_DOWN, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_TT2SOC_SMI_L
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_RC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_DISABLED | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_DISABLED | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2USBPDMCU_TX
|
||||
CFG_DISABLED, // 123 : UART8_RXD -> UART_USBPDMCU2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BT2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BT2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 156 : SPI1_MISO -> SPI_GRAPE_MISO
|
||||
CFG_OUT_1 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_DISABLED, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_24M
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0, // 160 : ULPI_STP -> SOC2USBPDMCU_RESET_L
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_IN | PULL_DOWN, // 167 : ULPI_DATA[3] -> USBPDMCU2SOC_IRQ
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 175 : PCIE_CLKREQ2_N -> NC_PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> NC
|
||||
CFG_OUT_0 | SLOW_SLEW, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> NC_PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> GPIO_DEVDOG_DETECT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_proto2_j99ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_IN | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BB_TX
|
||||
CFG_FUNC0, // 15 : UART3_RXD -> UART_BB2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_IN | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_FUNC0, // 33 : UART3_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_CODEC_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_OUT_1 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 53 : TMR32_PWM1 -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_DISABLED, // 54 : TMR32_PWM2 -> NC_JTAG_BB_TCK
|
||||
CFG_OUT_0 | PULL_DOWN | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC
|
||||
CFG_DISABLED | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_IN | PULL_UP, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 63 : UART7_TXD -> UART_SOC2OSCAR_TX
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0, // 64 : UART7_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN, // 70 : SPI0_SSIN -> GPIO_TS2ORIONSOC2PMU_IRQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 80 : GPIO[0] -> GPIO_SOC2TT_MUX_SEL
|
||||
CFG_OUT_1 | SLOW_SLEW, // 81 : GPIO[1] -> GPIO_SOC2TT_XBAR_EN_PULSE_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_OUT_1 | SLOW_SLEW, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_IN, // 88 : GPIO[8] -> GPIO_GANGES2SOC2PMU_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2CODEC_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 94 : GPIO[14] -> GPIO_SOC2TT_SW_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : GPIO[19] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_IN | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_TT2SOC_SMI_L
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_RC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_IN | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_OUT_0 | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_IN | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_IN | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2USBPDMCU_TX
|
||||
CFG_FUNC0, // 123 : UART8_RXD -> UART_USBPDMCU2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BT2SOC_TX
|
||||
CFG_OUT_1 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BT2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 156 : SPI1_MISO -> SPI_GRAPE_MISO
|
||||
CFG_OUT_1 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_DISABLED, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_24M
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0, // 160 : ULPI_STP -> SOC2USBPDMCU_RESET_L
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_IN | PULL_DOWN, // 167 : ULPI_DATA[3] -> USBPDMCU2SOC_IRQ
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 175 : PCIE_CLKREQ2_N -> NC_PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> NC
|
||||
CFG_OUT_0 | SLOW_SLEW, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> NC_PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> GPIO_DEVDOG_DETECT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_FUNC0 | SLOW_SLEW, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_proto2_j99dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BB_TX
|
||||
CFG_FUNC0, // 15 : UART3_RXD -> UART_BB2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_FUNC0, // 33 : UART3_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_CODEC_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_OUT_1 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 53 : TMR32_PWM1 -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_DISABLED, // 54 : TMR32_PWM2 -> NC_JTAG_BB_TCK
|
||||
CFG_OUT_0 | PULL_DOWN | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC
|
||||
CFG_DISABLED | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_IN | PULL_UP, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 63 : UART7_TXD -> UART_SOC2OSCAR_TX
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0, // 64 : UART7_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN, // 70 : SPI0_SSIN -> GPIO_TS2ORIONSOC2PMU_IRQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 80 : GPIO[0] -> GPIO_SOC2TT_MUX_SEL
|
||||
CFG_OUT_1 | SLOW_SLEW, // 81 : GPIO[1] -> GPIO_SOC2TT_XBAR_EN_PULSE_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_OUT_1 | SLOW_SLEW, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_IN, // 88 : GPIO[8] -> GPIO_GANGES2SOC2PMU_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2CODEC_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 94 : GPIO[14] -> GPIO_SOC2TT_SW_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : GPIO[19] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_IN | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_TT2SOC_SMI_L
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_RC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_IN | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_OUT_0 | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_IN | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_IN | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2USBPDMCU_TX
|
||||
CFG_FUNC0, // 123 : UART8_RXD -> UART_USBPDMCU2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BT2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BT2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 156 : SPI1_MISO -> SPI_GRAPE_MISO
|
||||
CFG_OUT_1 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_DISABLED, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_24M
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0, // 160 : ULPI_STP -> SOC2USBPDMCU_RESET_L
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_IN | PULL_DOWN, // 167 : ULPI_DATA[3] -> USBPDMCU2SOC_IRQ
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 175 : PCIE_CLKREQ2_N -> NC_PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> NC
|
||||
CFG_OUT_0 | SLOW_SLEW, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> NC_PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> GPIO_DEVDOG_DETECT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
};
|
||||
|
||||
struct pinconfig_map {
|
||||
uint32_t board_id;
|
||||
uint32_t board_id_mask;
|
||||
const uint32_t *pinconfigs[GPIOC_COUNT];
|
||||
};
|
||||
|
||||
static const struct pinconfig_map cfg_map[] = {
|
||||
{ TARGET_BOARD_ID_J98AP, ~0, { pinconfig_proto2_j98ap_0 } },
|
||||
{ TARGET_BOARD_ID_J98DEV, ~0, { pinconfig_proto2_j98dev_0 } },
|
||||
{ TARGET_BOARD_ID_J99AP, ~0, { pinconfig_proto2_j99ap_0 } },
|
||||
{ TARGET_BOARD_ID_J99DEV, ~0, { pinconfig_proto2_j99dev_0 } },
|
||||
};
|
||||
|
||||
const uint32_t * target_get_proto2_gpio_cfg(int gpioc)
|
||||
{
|
||||
static const struct pinconfig_map *selected_map = NULL;
|
||||
|
||||
if (selected_map == NULL) {
|
||||
uint32_t board_id = platform_get_board_id();
|
||||
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
|
||||
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
|
||||
selected_map = &cfg_map[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (selected_map == NULL)
|
||||
panic("no default pinconfig for board id %u", board_id);
|
||||
}
|
||||
|
||||
ASSERT(gpioc < GPIOC_COUNT);
|
||||
return selected_map->pinconfigs[gpioc];
|
||||
}
|
||||
@@ -0,0 +1,989 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: rev 2.1.0
|
||||
I/O Spreadsheet tracker: 17851336
|
||||
Conversion command: csvtopinconfig.py --soc capri --prefix proto3 --config-column 'j99:J99 Config' --config-column 'j98:J98 Config' --pupd-column 'j99:J99 PU/PD' --pupd-column 'j98:J98 PU/PD' --copyright 2013-2014 --radar 17851336 <filename>
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
#include <target/boardid.h>
|
||||
|
||||
static const uint32_t pinconfig_proto3_j98ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BB_TX
|
||||
CFG_DISABLED | PULL_DOWN, // 15 : UART3_RXD -> UART_BB2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_DISABLED | PULL_DOWN, // 33 : UART3_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_CODEC_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_OUT_1 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 53 : TMR32_PWM1 -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_DISABLED | PULL_DOWN, // 54 : TMR32_PWM2 -> NC_JTAG_BB_TCK
|
||||
CFG_OUT_0 | PULL_DOWN | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC
|
||||
CFG_DISABLED | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_IN | PULL_UP, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 63 : UART7_TXD -> UART_SOC2OSCAR_TX
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0, // 64 : UART7_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN, // 70 : SPI0_SSIN -> GPIO_TS2ORIONSOC2PMU_IRQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 80 : GPIO[0] -> GPIO_SOC2TT_MUX_SEL
|
||||
CFG_OUT_1 | SLOW_SLEW, // 81 : GPIO[1] -> GPIO_SOC2TT_XBAR_EN_PULSE_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_OUT_1 | SLOW_SLEW, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_IN, // 88 : GPIO[8] -> GPIO_GANGES2SOC2PMU_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2CODEC_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 94 : GPIO[14] -> GPIO_SOC2TT_SW_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : GPIO[19] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED | PULL_DOWN, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_TT2SOC_SMI_L
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_RC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_DISABLED | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_DISABLED | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_DISABLED | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2USBPDMCU_TX
|
||||
CFG_DISABLED, // 123 : UART8_RXD -> UART_USBPDMCU2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BT2SOC_TX
|
||||
CFG_OUT_1 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BT2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 156 : SPI1_MISO -> SPI_GRAPE_MISO
|
||||
CFG_OUT_1 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_24M
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0, // 160 : ULPI_STP -> SOC2USBPDMCU_RESET_L
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_IN, // 167 : ULPI_DATA[3] -> USBPDMCU2SOC_IRQ
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 175 : PCIE_CLKREQ2_N -> NC_PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> NC
|
||||
CFG_OUT_0 | SLOW_SLEW, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> NC_PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> GPIO_DEVDOG_DETECT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_FUNC0 | SLOW_SLEW, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_proto3_j98dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BB_TX
|
||||
CFG_DISABLED | PULL_DOWN, // 15 : UART3_RXD -> UART_BB2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_DISABLED | PULL_DOWN, // 33 : UART3_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_CODEC_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_OUT_1 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 53 : TMR32_PWM1 -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_DISABLED | PULL_DOWN, // 54 : TMR32_PWM2 -> NC_JTAG_BB_TCK
|
||||
CFG_OUT_0 | PULL_DOWN | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC
|
||||
CFG_DISABLED | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_IN | PULL_UP, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 63 : UART7_TXD -> UART_SOC2OSCAR_TX
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0, // 64 : UART7_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN, // 70 : SPI0_SSIN -> GPIO_TS2ORIONSOC2PMU_IRQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 80 : GPIO[0] -> GPIO_SOC2TT_MUX_SEL
|
||||
CFG_OUT_1 | SLOW_SLEW, // 81 : GPIO[1] -> GPIO_SOC2TT_XBAR_EN_PULSE_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_OUT_1 | SLOW_SLEW, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_IN, // 88 : GPIO[8] -> GPIO_GANGES2SOC2PMU_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2CODEC_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 94 : GPIO[14] -> GPIO_SOC2TT_SW_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : GPIO[19] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED | PULL_DOWN, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_TT2SOC_SMI_L
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_RC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_DISABLED | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_DISABLED | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2USBPDMCU_TX
|
||||
CFG_DISABLED, // 123 : UART8_RXD -> UART_USBPDMCU2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BT2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BT2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 156 : SPI1_MISO -> SPI_GRAPE_MISO
|
||||
CFG_OUT_1 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_24M
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0, // 160 : ULPI_STP -> SOC2USBPDMCU_RESET_L
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_IN, // 167 : ULPI_DATA[3] -> USBPDMCU2SOC_IRQ
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 175 : PCIE_CLKREQ2_N -> NC_PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> NC
|
||||
CFG_OUT_0 | SLOW_SLEW, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> NC_PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> GPIO_DEVDOG_DETECT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_proto3_j99ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_IN | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BB_TX
|
||||
CFG_FUNC0, // 15 : UART3_RXD -> UART_BB2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_IN | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_FUNC0, // 33 : UART3_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_CODEC_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_OUT_1 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 53 : TMR32_PWM1 -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_DISABLED, // 54 : TMR32_PWM2 -> NC_JTAG_BB_TCK
|
||||
CFG_OUT_0 | PULL_DOWN | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC
|
||||
CFG_DISABLED | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_IN | PULL_UP, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 63 : UART7_TXD -> UART_SOC2OSCAR_TX
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0, // 64 : UART7_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN, // 70 : SPI0_SSIN -> GPIO_TS2ORIONSOC2PMU_IRQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 80 : GPIO[0] -> GPIO_SOC2TT_MUX_SEL
|
||||
CFG_OUT_1 | SLOW_SLEW, // 81 : GPIO[1] -> GPIO_SOC2TT_XBAR_EN_PULSE_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_OUT_1 | SLOW_SLEW, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_IN, // 88 : GPIO[8] -> GPIO_GANGES2SOC2PMU_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2CODEC_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 94 : GPIO[14] -> GPIO_SOC2TT_SW_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : GPIO[19] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_IN | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_TT2SOC_SMI_L
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_RC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_IN | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_OUT_0 | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_IN | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_IN | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2USBPDMCU_TX
|
||||
CFG_FUNC0, // 123 : UART8_RXD -> UART_USBPDMCU2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BT2SOC_TX
|
||||
CFG_OUT_1 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BT2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | SLOW_SLEW, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 156 : SPI1_MISO -> SPI_GRAPE_MISO
|
||||
CFG_OUT_1 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_24M
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0, // 160 : ULPI_STP -> SOC2USBPDMCU_RESET_L
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_IN, // 167 : ULPI_DATA[3] -> USBPDMCU2SOC_IRQ
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 175 : PCIE_CLKREQ2_N -> NC_PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> NC
|
||||
CFG_OUT_0 | SLOW_SLEW, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> NC_PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> GPIO_DEVDOG_DETECT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_FUNC0 | SLOW_SLEW, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_proto3_j99dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // 0 : MENU_KEY_L -> GPIO_BTN_HOME_L
|
||||
CFG_IN, // 1 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : ISP0_SDA -> ISP_CAM_REAR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 3 : ISP0_SCL -> ISP_CAM_REAR_SCL
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 4 : ISP1_SDA -> ISP_CAM_FRONT_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 5 : ISP1_SCL -> ISP_CAM_FRONT_SCL
|
||||
CFG_OUT_0 | SLOW_SLEW, // 6 : SENSOR0_RST -> ISP_CAM_REAR_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 7 : SENSOR0_CLK -> ISP_CAM_REAR_CLK_R
|
||||
|
||||
/* Port 1 */
|
||||
CFG_IN | PULL_UP, // 8 : SENSOR0_XSHUTDOWN -> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 9 : SENSOR0_ISTRB -> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 10 : SENSOR1_RST -> ISP_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 11 : SENSOR1_CLK -> ISP_CAM_FRONT_CLK_R
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 12 : SENSOR1_XSHUTDOWN -> GPIO_SOC2ROTTERDAM_EN
|
||||
CFG_IN | PULL_DOWN | SLOW_SLEW, // 13 : SENSOR1_ISTRB -> GPIO_SOC2ROTTERDAM_DWLD_REQ
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 14 : UART3_TXD -> UART_SOC2BB_TX
|
||||
CFG_FUNC0, // 15 : UART3_RXD -> UART_BB2SOC_TX
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_IN | DRIVE_X2 | SLOW_SLEW, // 32 : UART3_RTSN -> UART_SOC2BB_RTS_L
|
||||
CFG_FUNC0, // 33 : UART3_CTSN -> UART_BB2SOC_RTS_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 34 : UART5_RTXD -> UART_BATT_HDQ
|
||||
CFG_FUNC0 | SLOW_SLEW, // 35 : DWI0_DO -> DWI_SOC2PMU_DO
|
||||
CFG_FUNC0 | SLOW_SLEW, // 36 : DWI0_CLK -> DWI_SOC2PMU_CLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 37 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 38 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 39 : I2S0_LRCK -> I2S_SOC2CODEC_ASP_LRCK
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 40 : I2S0_BCLK -> I2S_SOC2CODEC_ASP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 41 : I2S0_DOUT -> I2S_SOC2CODEC_ASP_DOUT
|
||||
CFG_FUNC0, // 42 : I2S0_DIN -> I2S_CODEC2SOC_ASP_DOUT
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 43 : I2S1_MCK -> SWD_KONA_CLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 44 : I2S1_LRCK -> I2S_SOC2CODEC_XSP_LRCK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 45 : I2S1_BCLK -> I2S_SOC2CODEC_XSP_BCLK
|
||||
CFG_FUNC0 | SLOW_SLEW, // 46 : I2S1_DOUT -> I2S_SOC2CODEC_XSP_DOUT
|
||||
CFG_FUNC0, // 47 : I2S1_DIN -> I2S_CODEC2SOC_XSP_DOUT
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 48 : SPI3_MOSI -> SPI_CODEC_MOSI
|
||||
CFG_FUNC0, // 49 : SPI3_MISO -> SPI_CODEC_MISO
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 50 : SPI3_SCLK -> SPI_CODEC_SCLK_R
|
||||
CFG_OUT_1 | SLOW_SLEW, // 51 : SPI3_SSIN -> SPI_CODEC_CS_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 52 : TMR32_PWM0 -> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
|
||||
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 53 : TMR32_PWM1 -> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
|
||||
CFG_DISABLED, // 54 : TMR32_PWM2 -> NC_JTAG_BB_TCK
|
||||
CFG_OUT_0 | PULL_DOWN | SLOW_SLEW, // 55 : DISP_VSYNC -> DISPLAY_SYNC
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | SLOW_SLEW, // 56 : WDOG -> WDOG_SOC
|
||||
CFG_FUNC0, // 57 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | SLOW_SLEW, // 58 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_DISABLED, // 59 : CPU_SLEEP_STATUS -> NC
|
||||
CFG_DISABLED | SLOW_SLEW, // 60 : TST_CLKOUT -> SOC_TST_CLKOUT
|
||||
CFG_IN | PULL_UP, // 61 : ISP_UART0_TXD -> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
|
||||
CFG_IN | PULL_UP, // 62 : ISP_UART0_RXD -> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 63 : UART7_TXD -> UART_SOC2OSCAR_TX
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0, // 64 : UART7_RXD -> UART_OSCAR2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 65 : I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_DISABLED, // 67 : SPI0_SCLK -> GPIO_BRD_ID0
|
||||
CFG_DISABLED, // 68 : SPI0_MOSI -> GPIO_BRD_ID1
|
||||
CFG_DISABLED, // 69 : SPI0_MISO -> GPIO_BRD_ID2
|
||||
CFG_IN, // 70 : SPI0_SSIN -> GPIO_TS2ORIONSOC2PMU_IRQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 71 : I2S3_MCK -> I2S_SOC2SPKRAMP_FH_MCK_R
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 72 : I2S3_LRCK -> I2S_SOC2SPKRAMP_FH_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 73 : I2S3_BCLK -> I2S_SOC2SPKRAMP_FH_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 74 : I2S3_DOUT -> I2S_SOC2SPKRAMP_FH_DOUT
|
||||
CFG_FUNC0, // 75 : I2S3_DIN -> I2S_SPKRAMP2SOC_FH_DOUT
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 76 : UART4_TXD -> UART_SOC2ROTTERDAM_TX
|
||||
CFG_FUNC0, // 77 : UART4_RXD -> UART_ROTTERDAM2SOC_TX
|
||||
CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW, // 78 : UART4_RTSN -> UART_SOC2ROTTERDAM_RTS_L
|
||||
CFG_FUNC0, // 79 : UART4_CTSN -> UART_ROTTERDAM2SOC_RTS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_OUT_0 | SLOW_SLEW, // 80 : GPIO[0] -> GPIO_SOC2TT_MUX_SEL
|
||||
CFG_OUT_1 | SLOW_SLEW, // 81 : GPIO[1] -> GPIO_SOC2TT_XBAR_EN_PULSE_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 82 : GPIO[2] -> GPIO_SOC2GRAPE_RESET_L
|
||||
CFG_IN, // 83 : GPIO[3] -> GPIO_TS2SOC2PMU_IRQ
|
||||
CFG_IN | PULL_UP, // 84 : GPIO[4] -> GPIO_GRAPE2SOC_IRQ_L
|
||||
CFG_OUT_1 | SLOW_SLEW, // 85 : GPIO[5] -> GPIO_SOC2TT_XBAR_DIS_PULSE_L
|
||||
CFG_IN | PULL_UP, // 86 : GPIO[6] -> GPIO_PMU2SOC_IRQ_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 87 : GPIO[7] -> GPIO_SOC2PMU_KEEPACT
|
||||
|
||||
/* Port 11 */
|
||||
CFG_IN, // 88 : GPIO[8] -> GPIO_GANGES2SOC2PMU_IRQ_L
|
||||
CFG_DISABLED, // 89 : GPIO[9] -> GPIO_TT2SOC_WAKE_L
|
||||
CFG_DISABLED, // 90 : GPIO[10] -> GPIO_SOC2CODEC_RESET_L
|
||||
CFG_DISABLED | PULL_DOWN | SLOW_SLEW, // 91 : GPIO[11] -> GPIO_BB_IPC
|
||||
CFG_IN | PULL_UP, // 92 : GPIO[12] -> GPIO_BTN_VOL_UP_L
|
||||
CFG_IN | PULL_UP, // 93 : GPIO[13] -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_OUT_0 | SLOW_SLEW, // 94 : GPIO[14] -> GPIO_SOC2TT_SW_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 95 : GPIO[15] -> GPIO_SOC2GRAPE_EXT_SW_ON
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : GPIO[16] -> GPIO_BRD_ID3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 97 : GPIO[17] -> GPIO_SOC2BB_COREDUMP
|
||||
CFG_DISABLED, // 98 : GPIO[18] -> GPIO_BOOT_CFG0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 99 : GPIO[19] -> GPIO_SOC2TT_LDO_EN
|
||||
CFG_OUT_0 | SLOW_SLEW, // 100 : GPIO[20] -> GPIO_SOC2BB_WAKE_MODEM
|
||||
CFG_OUT_0 | SLOW_SLEW, // 101 : GPIO[21] -> GPIO_SOC2SPKRAMP_KEEPALIVE
|
||||
CFG_DISABLED, // 102 : GPIO[22] -> GPIO_BB2SOC_GPS_SYNC
|
||||
CFG_IN | PULL_UP, // 103 : GPIO[23] -> GPIO_HP_ALS2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_IN | SLOW_SLEW, // 104 : GPIO[24] -> GPIO_SOC2BB_RADIO_ON_L
|
||||
CFG_DISABLED, // 105 : GPIO[25] -> GPIO_BOOT_CFG1
|
||||
CFG_IN, // 106 : GPIO[26] -> GPIO_FORCE_DFU
|
||||
CFG_DISABLED, // 107 : GPIO[27] -> TP_GPIO_DFU_STATUS
|
||||
CFG_DISABLED, // 108 : GPIO[28] -> GPIO_BOOT_CFG2
|
||||
CFG_DISABLED, // 109 : GPIO[29] -> GPIO_TT2SOC_SMI_L
|
||||
CFG_IN | PULL_UP, // 110 : GPIO[30] -> GPIO_RC_ALS2SOC_IRQ_L
|
||||
CFG_DISABLED, // 111 : GPIO[31] -> GPIO_BOOT_CFG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_IN, // 112 : GPIO[32] -> GPIO_OSCAR2PMU_HOST_WAKE
|
||||
CFG_IN | PULL_DOWN, // 113 : GPIO[33] -> HSIC_BB2SOC_DEVICE_RDY
|
||||
CFG_OUT_0 | SLOW_SLEW, // 114 : GPIO[34] -> HSIC_SOC2BB_HOST_RDY
|
||||
CFG_IN | PULL_DOWN, // 115 : GPIO[35] -> GPIO_BB2SOC_RESET_DET_L
|
||||
CFG_IN | PULL_UP, // 116 : GPIO[36] -> GPIO_CODEC2SOC_IRQ_L
|
||||
CFG_IN | SLOW_SLEW, // 117 : GPIO[37] -> GPIO_SOC2BB_RESET_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 118 : SPI2_SCLK -> SPI_MESA_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 119 : SPI2_MOSI -> SPI_MESA_MOSI
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SPI2_MISO -> SPI_MESA_MISO
|
||||
CFG_IN | PULL_DOWN, // 121 : SPI2_SSIN -> GPIO_MESA2SOC_IRQ
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 122 : UART8_TXD -> UART_SOC2USBPDMCU_TX
|
||||
CFG_FUNC0, // 123 : UART8_RXD -> UART_USBPDMCU2SOC_TX
|
||||
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 128 : UART0_TXD -> UART_SOC2DEBUG_TX
|
||||
CFG_FUNC0, // 129 : UART0_RXD -> UART_DEBUG2SOC_TX
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 130 : UART6_TXD -> UART_SOC2ACC_TX
|
||||
CFG_FUNC0, // 131 : UART6_RXD -> UART_ACC2SOC_TX
|
||||
CFG_FUNC0 | SLOW_SLEW, // 132 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | SLOW_SLEW, // 133 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 134 : I2C3_SDA -> I2C3_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 135 : I2C3_SCL -> I2C3_SCL_1V8
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 136 : UART2_TXD -> UART_SOC2WLAN_TX
|
||||
CFG_FUNC0, // 137 : UART2_RXD -> UART_WLAN2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 138 : UART2_RTSN -> UART_SOC2WLAN_RTS_L
|
||||
CFG_FUNC0, // 139 : UART2_CTSN -> UART_WLAN2SOC_RTS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 140 : UART1_TXD -> UART_SOC2BT_TX
|
||||
CFG_FUNC0, // 141 : UART1_RXD -> UART_BT2SOC_TX
|
||||
CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW, // 142 : UART1_RTSN -> UART_SOC2BT_RTS_L
|
||||
CFG_FUNC0, // 143 : UART1_CTSN -> UART_BT2SOC_RTS_L
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0, // 144 : EDP_HPD -> EDP_HPD
|
||||
CFG_DISABLED | DRIVE_X2 | SLOW_SLEW, // 145 : I2S4_MCK -> SWD_KONA_IO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 146 : I2S4_LRCK -> I2S_SOC2BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 147 : I2S4_BCLK -> I2S_SOC2BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 148 : I2S4_DOUT -> I2S_SOC2BT_DOUT
|
||||
CFG_FUNC0, // 149 : I2S4_DIN -> I2S_BT2SOC_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 150 : I2S2_LRCK -> I2S_SOC2SPKRAMP_CN_LRCK
|
||||
CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW, // 151 : I2S2_BCLK -> I2S_SOC2SPKRAMP_CN_BCLK
|
||||
|
||||
/* Port 19 */
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 152 : I2S2_DOUT -> I2S_SOC2SPKRAMP_CN_DOUT
|
||||
CFG_FUNC0, // 153 : I2S2_DIN -> I2S_SPKRAMP2SOC_CN_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 154 : SPI1_SCLK -> SPI_GRAPE_SCLK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 155 : SPI1_MOSI -> SPI_GRAPE_MOSI
|
||||
CFG_FUNC0, // 156 : SPI1_MISO -> SPI_GRAPE_MISO
|
||||
CFG_OUT_1 | SLOW_SLEW, // 157 : SPI1_SSIN -> SPI_GRAPE_CS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 158 : CLK32K_OUT -> CLK_SOC2GRAPE_24M
|
||||
CFG_DISABLED, // 159 : ULPI_DIR -> GPIO_BRD_REV1
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0, // 160 : ULPI_STP -> SOC2USBPDMCU_RESET_L
|
||||
CFG_DISABLED, // 161 : ULPI_NXT -> GPIO_BRD_REV0
|
||||
CFG_OUT_0 | SLOW_SLEW, // 162 : ULPI_DATA[7] -> GPIO_SOC2AJ_HS3_SHUNT_EN
|
||||
CFG_DISABLED, // 163 : ULPI_DATA[6] -> GPIO_BRD_REV3
|
||||
CFG_OUT_0 | SLOW_SLEW, // 164 : ULPI_DATA[5] -> GPIO_SOC2BT_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 165 : ULPI_DATA[4] -> GPIO_SOC2WLAN_WAKE
|
||||
CFG_OUT_0 | SLOW_SLEW, // 166 : ULPI_CLK -> GPIO_SOC2AJ_HS4_SHUNT_EN
|
||||
CFG_IN, // 167 : ULPI_DATA[3] -> USBPDMCU2SOC_IRQ
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : ULPI_DATA[2] -> GPIO_BRD_REV2
|
||||
CFG_DISABLED, // 169 : ULPI_DATA[1] -> SWD_OSCAR_IO_1V8
|
||||
CFG_DISABLED, // 170 : ULPI_DATA[0] -> SWD_OSCAR_CLK_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 171 : DWI1_DO -> DWI_SOC2BEACON_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 172 : DWI1_CLK -> DWI_SOC2BEACON_CLK
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 173 : PCIE_CLKREQ0_N -> PCIE_TT2SOC_CLKREQ_L
|
||||
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 174 : PCIE_CLKREQ1_N -> PCIE_WLAN2SOC_CLKREQ_L
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 175 : PCIE_CLKREQ2_N -> NC_PCIE_DEVBRD2SOC_CLKREQ_L
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED | INPUT_SCHMITT, // 176 : PCIE_CLKREQ3_N -> GPIO_TT2SOC_PWR_SW_OC
|
||||
CFG_DISABLED, // 177 : NAND_SYS_CLK -> NC
|
||||
CFG_OUT_0 | SLOW_SLEW, // 178 : PCIE_PERST0_N -> PCIE_SOC2TT_RESET_L
|
||||
CFG_IN | SLOW_SLEW, // 179 : PCIE_PERST1_N -> PCIE_SOC2WLAN_RESET_L
|
||||
CFG_DISABLED, // 180 : PCIE_PERST2_N -> NC_PCIE_SOC2DEVBRD_RESET_L
|
||||
CFG_DISABLED, // 181 : PCIE_PERST3_N -> GPIO_DEVDOG_DETECT
|
||||
CFG_FUNC0 | SLOW_SLEW, // 182 : I2S0_MCK -> I2S_SOC2CODEC_ASP_MCK_R
|
||||
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 183 : I2S2_MCK -> I2S_SOC2SPKRAMP_CN_MCK_R
|
||||
};
|
||||
|
||||
struct pinconfig_map {
|
||||
uint32_t board_id;
|
||||
uint32_t board_id_mask;
|
||||
const uint32_t *pinconfigs[GPIOC_COUNT];
|
||||
};
|
||||
|
||||
static const struct pinconfig_map cfg_map[] = {
|
||||
{ TARGET_BOARD_ID_J98AP, ~0, { pinconfig_proto3_j98ap_0 } },
|
||||
{ TARGET_BOARD_ID_J98DEV, ~0, { pinconfig_proto3_j98dev_0 } },
|
||||
{ TARGET_BOARD_ID_J99AP, ~0, { pinconfig_proto3_j99ap_0 } },
|
||||
{ TARGET_BOARD_ID_J99DEV, ~0, { pinconfig_proto3_j99dev_0 } },
|
||||
};
|
||||
|
||||
const uint32_t * target_get_proto3_gpio_cfg(int gpioc)
|
||||
{
|
||||
static const struct pinconfig_map *selected_map = NULL;
|
||||
|
||||
if (selected_map == NULL) {
|
||||
uint32_t board_id = platform_get_board_id();
|
||||
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
|
||||
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
|
||||
selected_map = &cfg_map[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (selected_map == NULL)
|
||||
panic("no default pinconfig for board id %u", board_id);
|
||||
}
|
||||
|
||||
ASSERT(gpioc < GPIOC_COUNT);
|
||||
return selected_map->pinconfigs[gpioc];
|
||||
}
|
||||
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <target.h>
|
||||
#include <target/powerconfig.h>
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
bool
|
||||
target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
|
||||
{
|
||||
int length = 0;
|
||||
bool result = false;
|
||||
|
||||
if ((result = target_get_property_base(prop, data, maxdata, retlen)) == false) {
|
||||
switch(prop) {
|
||||
case TARGET_PROPERTY_RESTORE_BACKLIGHT_LEVEL:
|
||||
// fix the restore backlight level at the precharge level,
|
||||
// to make sure the backlight does not cause the battery to
|
||||
// drain during restore
|
||||
if (maxdata >= (ssize_t)sizeof(uint32_t)) {
|
||||
result = true;
|
||||
length = sizeof(uint32_t);
|
||||
*(uint32_t *)data = PRECHARGE_BACKLIGHT_LEVEL;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (retlen != NULL) *retlen = length;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,56 @@
|
||||
# Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
# BUCK_CPU, BUCK_GPU and BUCK_RAM should be reviewed
|
||||
# if any changed happen in drivers/dialog/pmu/power.c:power_get_buck_value()
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2207=1 \
|
||||
DIALOG_D2231=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_V2 \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=CHIPID_SOC_VOLTAGE_VMIN \
|
||||
TARGET_HAS_BASEBAND=$(TARGET_HAS_BASEBAND) \
|
||||
TARGET_VID0_CLK_CFG=0x89100000 \
|
||||
TARGET_CORE_PHY_TMR_LPCLK_CFG=0x00330087 \
|
||||
TARGET_CORE_PHY_TMR_CFG=0x256f0000 \
|
||||
TARGET_PHY_STOP_WAIT_TIME=0x28 \
|
||||
TARGET_DDR_798M=1 \
|
||||
DISPLAY_LANDSCAPE_IPAD_TUNABLES=1 \
|
||||
TARGET_DITHER_TYPE=DITHER_BLUE_NOISE \
|
||||
PMU_LCD_PWR_EN=1 \
|
||||
AMC_NUM_CHANNELS=4 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_GPU=2 \
|
||||
BUCK_RAM=1 \
|
||||
MULTITOUCH_DTPATH=\"arm-io/spi1/multi-touch\" \
|
||||
WIFI_DTPATH=\"arm-io/uart2/wlan\" \
|
||||
DP_DTPATH=\"arm-io/displayport\" \
|
||||
DPPHY_DTPATH=\"arm-io/lpdp-phy\" \
|
||||
BT_DTPATH=\"arm-io/uart1/bluetooth\"
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o \
|
||||
$(LOCAL_DIR)/pinconfig_proto2.o \
|
||||
$(LOCAL_DIR)/pinconfig_proto3.o \
|
||||
$(LOCAL_DIR)/pinconfig_evt.o \
|
||||
$(LOCAL_DIR)/pinconfig_evt2.o
|
||||
|
||||
ifneq ($(PRODUCT),LLB)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/properties.o
|
||||
endif
|
||||
Reference in new issue
Block a user