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@@ -0,0 +1,48 @@
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/*
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* Copyright (C) 2011 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* iPhone5,x specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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#define GPIO_LCD_RST GPIO(25, 2)
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#define GPIO_LCD_RST_POLARITY (0)
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#define GPIO_LCD_CHKSUM GPIO( 4, 7)
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#define GPIO_RINGER_AB GPIO( 0, 4)
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/* Board Revision */
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#define GPIO_BOARD_REV0 GPIO( 2, 4)
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#define GPIO_BOARD_REV1 GPIO( 2, 5)
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#define GPIO_BOARD_REV2 GPIO( 2, 6)
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#define GPIO_BOARD_REV3 GPIO( 2, 7)
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/* Grape ID */
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#define GPIO_GRAPE_ID0 GPIO( 1, 5)
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#define GPIO_GRAPE_ID1 GPIO( 1, 4)
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#define GPIO_GRAPE_ID2 GPIO( 1, 3)
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/* which IICs to initialize */
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#define IICS_MASK (7)
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#define TRISTAR_IIC_BUS (0)
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/* D1972 watchdog tickle, 'KEEPACT' */
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#define GPIO_WDOG_TICKLE GPIO(2, 3)
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// Configure both FMI0 & FMI1 to use differential DQS with DQ set to DQVREF
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#define FMI_DIFF_SEL (0x36)
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,92 @@
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// Copyright (C) 2008-2010 Apple, Inc. All rights reserved.
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//
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// This document is the property of Apple, Inc.
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// It is considered confidential and proprietary.
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//
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// This document may not be reproduced or transmitted in any form,
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// in whole or in part, without the express written permission of
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// Apple, Inc.
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//
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// NOTE: This is a generated file and should not be hand-edited!
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//
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// =============================================================================
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// Nand Geometry Table
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static NandGeometry _nandGeometryTable[] =
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{
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};
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// =============================================================================
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// Nand Timing Table
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static NandTiming _nandTimingTable[] =
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{
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};
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#if (defined (AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
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// =============================================================================
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// NandChipId Description
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const NandChipIdDescription _nandChipIdDescriptionTable[] =
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{
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};
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// =============================================================================
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// Nand Description Table
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static const NandDescription _nandDescriptionTable[] =
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{
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};
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const UInt32 _nandDescriptionTableSize = sizeof(_nandDescriptionTable) / sizeof(NandDescription);
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#endif // (defined(AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
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// =============================================================================
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// Nand Board Support Table
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static NandBoardSupport _nandBoardSupportTable[] =
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{
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};
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// =============================================================================
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// Nand Board Timing Table
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static NandBoardInfo _nandBoardInfo =
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{
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/* controlDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* dataDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* chipEnableDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* socToNandRiseNanosecs */ 10,
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/* socToNandFallNanosecs */ 10,
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/* nandToSocRiseNanosecs */ 10,
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/* nandToSocFallNanosecs */ 10,
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/* landing map */
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{
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0x00000101
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},
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/* useToggleMode */ TRUE32,
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/* useDiffDQSMode */ FALSE32,
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/* useDiffREMode */ FALSE32,
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/* useVref */ TRUE32,
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/* useSingleHostChannel */ FALSE32,
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/* allowSingleChipEnable */ TRUE32
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};
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static NandFormat _nandFormatPpn =
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{
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/* metaPerLogicalPage */ 16,
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/* validMetaPerLogicalPage */ 16,
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/* logicalPageSize */ 4096
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};
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static NandFormat _nandFormatRaw =
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{
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/* metaPerLogicalPage */ 12,
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/* validMetaPerLogicalPage */ 10,
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/* logicalPageSize */ 0
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};
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@@ -0,0 +1,376 @@
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/*
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* Copyright (C) 2011-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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/* Default iPhone5,x SoC Pin Configuration */
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#if PIN_CFG_AP
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#define HI_DRIVE_STR DRIVE_X4
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#elif PIN_CFG_DEV
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#define HI_DRIVE_STR DRIVE_X6
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#endif
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#define BB_UART_DRIVE_STR DRIVE_X2
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#define BT_UART_DRIVE_STR DRIVE_X2
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#define DOCK_UART_DRIVE_STR DRIVE_X2
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#define SWI_UART_DRIVE_STR DRIVE_X1
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#define WIFI_UART_DRIVE_STR DRIVE_X2
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#define FMI_LO_SPEED_DRIVE_STR (DRIVE_X2 | SLOW_SLEW)
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#define FMI_HI_SPEED_DRIVE_STR (DRIVE_X2 | SLOW_SLEW)
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#define GRAPE_IO_DRIVE_STR DRIVE_X1
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#define GRAPE_CLK_DRIVE_STR DRIVE_X2
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#define DWI_DRIVE_STR DRIVE_X2
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#define I2C_DRIVE_STR DRIVE_X1
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#define I2S_DRIVE_STR DRIVE_X2
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#define CAM_I2C_DRIVE_STR DRIVE_X1
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#define CAM_STROBE_DRIVE_STR DRIVE_X1
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#define CAM_CLK_DRIVE_STR DRIVE_X2
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#define DISABLE_OPTIONAL_SIGNALS (1)
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#if PIN_CFG_AP
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static const uint32_t gpio_default_cfg_ap[GPIO_GROUP_COUNT * GPIOPADPINS] = {
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#elif PIN_CFG_DEV
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static const uint32_t gpio_default_cfg_dev[GPIO_GROUP_COUNT * GPIOPADPINS] = {
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#endif
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/* Port 0 */
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CFG_IN, // GPIO0 -> MENU_KEY_BUFF_L (REQUEST_DFU2)
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CFG_IN, // GPIO1 -> HOLD_KEY_BUFF_L (REQUEST_DFU1)
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CFG_IN | PULL_UP, // GPIO2 -> VOL_UP_L
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CFG_IN | PULL_UP, // GPIO3 -> VOL_DWN_L
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CFG_IN, // GPIO4 -> RINGER_A
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CFG_IN | PULL_UP, // GPIO5 -> SPKAMP_INT_L
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CFG_IN | PULL_UP, // GPIO6 -> PMU_IRQ_L
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CFG_OUT_0, // GPIO7 -> BT_WAKE
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/* Port 1 */
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CFG_IN, // GPIO8 -> BB_PMU_FET_ON
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CFG_OUT_0, // GPIO9 -> BEE_GEES
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CFG_IN, // GPIO10 -> BB_HSIC1_REMOTE_WAKE
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CFG_IN | PULL_UP, // GPIO11 -> WLAN_SDIO_DATA[2]
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CFG_IN | PULL_UP, // GPIO12 -> WLAN_SDIO_DATA[1]
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CFG_IN | PULL_UP, // GPIO13 -> WLAN_SDIO_DATA[0]
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CFG_IN, // GPIO14 -> WLAN_SDIO_CMP
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CFG_IN, // GPIO15 -> WLAN_SDIO_CLK
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/* Port 2 */
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CFG_DISABLED, // GPIO16 -> BOARD_ID[3]
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CFG_OUT_0, // GPIO17 -> AP_HSIC1_RDY
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CFG_DISABLED, // GPIO18 -> BOOT_CONFIG[0]
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CFG_OUT_0, // GPIO19 -> KEEPACT
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CFG_DISABLED, // EHCI_PORT_PWR[0] -> BOARD_REV0
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CFG_DISABLED, // EHCI_PORT_PWR[1] -> BOARD_REV1
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CFG_DISABLED, // EHCI_PORT_PWR[2] -> BOARD_REV2
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CFG_DISABLED, // EHCI_PORT_PWR[3] -> BOARD_REV3
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/* Port 3 */
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CFG_IN | BB_UART_DRIVE_STR, // UART1_TXD -> UART1_TXD
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CFG_FUNC0, // UART1_RXD -> UART1_RXD
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CFG_FUNC0 | BB_UART_DRIVE_STR, // UART1_RTSN -> UART1_RTS_L
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CFG_FUNC0, // UART1_CTSN -> UART1_CTS_L
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CFG_FUNC0 | DOCK_UART_DRIVE_STR, // UART2_TXD -> UART2_TXD
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CFG_FUNC0, // UART2_RXD -> UART2_RXD
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CFG_IN | PULL_DOWN, // UART2_RTSN -> ACCEL_INT1
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CFG_IN, // UART2_CTSN -> TRISTAR_INT
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/* Port 4 */
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CFG_FUNC0 | BT_UART_DRIVE_STR, // UART3_TXD -> UART3_TXD
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CFG_FUNC0, // UART3_RXD -> UART3_RXD
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CFG_OUT_1 | BT_UART_DRIVE_STR, // UART3_RTSN -> UART3_RTS_L
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CFG_FUNC0, // UART3_CTSN -> UART3_CTS_L
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CFG_FUNC0 | WIFI_UART_DRIVE_STR, // UART4_TXD/SPI4_MOSI -> UART4_TXD
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CFG_FUNC0, // UART4_RXD/SPI4_MISO -> UART4_RXD
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CFG_OUT_0, // UART4_RTSN/SPI4_SCLK -> CAM0_VDDCORE_EN
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#if PIN_CFG_AP
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CFG_OUT_0, // UART4_CTSN/SPI4_SSIN -> BB_JTAG_TRST_L
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#elif PIN_CFG_DEV
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CFG_IN, // UART4_CTSN/SPI4_SSIN -> LCD_ERSTB_L
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#else
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#error "unknown config"
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#endif
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/* Port 5 */
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CFG_FUNC0 | DOCK_UART_DRIVE_STR, // UART6_TXD -> UART6_TXD
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CFG_FUNC0, // UART6_RXD -> UART6_RXD
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CFG_OUT_0, // UART6_RTSN -> SPKAMP_RESET_L
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CFG_IN | PULL_DOWN, // UART6_CTSN -> BB_PP_SYNC
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CFG_FUNC1 | SWI_UART_DRIVE_STR, // UART5_RXD/UART5_RTXD -> UART5_RXD
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CFG_IN | PULL_DOWN, // UART5_TXD -> BB_RESET_DET_L
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CFG_FUNC0 | GRAPE_CLK_DRIVE_STR, // SPI1_SCLK -> SPI1_SCLK
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CFG_FUNC0 | GRAPE_IO_DRIVE_STR, // SPI1_MOSI -> SPI1_MOSI
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/* Port 6 */
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CFG_FUNC0, // SPI1_MISO -> SPI1_MISO
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CFG_OUT_0 | GRAPE_IO_DRIVE_STR, // SPI1_SSIN -> SPI1_CS_L
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CFG_DISABLED, // SPI0_SCLK -> SPI0_SCLK/BOARD_ID[0]
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CFG_DISABLED, // SPI0_MOSI -> SPI0_MOSI/BOARD_ID[1]
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CFG_DISABLED, // SPI0_MISO -> SPI0_MISO/BOARD_ID[2]
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CFG_DISABLED, // SPI0_SSIN -> SPI0_SSIN
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CFG_OUT_0, // SPI2_SCLK -> AP_HSIC3_RDY
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CFG_OUT_0, // SPI2_MOSI -> PMU_AMUX_BY_CTRL
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/* Port 7 */
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CFG_OUT_0, // SPI2_MISO -> PMU_AMUX_AY_CTRL
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CFG_IN | PULL_UP, // SPI2_SSIN -> DEV_HSIC3_RDY
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CFG_FUNC0 | I2C_DRIVE_STR, // I2C0_SDA -> I2C0_SDA_1V8
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CFG_FUNC0 | I2C_DRIVE_STR, // I2C0_SCL -> I2C0_SCL_1V8
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CFG_FUNC0 | I2C_DRIVE_STR, // I2C1_SDA -> I2C1_SDA_1V8
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CFG_FUNC0 | I2C_DRIVE_STR, // I2C1_SCL -> I2C1_SCL_1V8
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CFG_FUNC0 | CAM_I2C_DRIVE_STR, // ISP0_SDA -> CAM0_I2C_SDA
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CFG_FUNC0 | CAM_I2C_DRIVE_STR, // ISP0_SCL -> CAM0_I2C_SCL
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/* Port 8 */
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CFG_FUNC0 | CAM_I2C_DRIVE_STR, // ISP1_SDA -> CAM1_I2C_SDA
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CFG_FUNC0 | CAM_I2C_DRIVE_STR, // ISP1_SCL -> CAM1_I2C_SCL
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CFG_DISABLED, // MIPI_VSYNC -> MIPI_VSYNC
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CFG_FUNC0 | PULL_DOWN, // TMR32_PWM0 -> GYRO_INT2
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CFG_FUNC0, // TMR32_PWM1 -> VIB_PWM
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CFG_FUNC0 | GRAPE_IO_DRIVE_STR, // TMR32_PWM2 -> CLK32K_GRAPE_RESET_SOC_L
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CFG_DISABLED | PULL_DOWN, // SWI_DATA -> SWI_BLCTL
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CFG_FUNC0, // DWI_DI -> DWI_AP_DI
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/* Port 9 */
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CFG_FUNC0 | DWI_DRIVE_STR, // DWI_DO -> DWI_AP_DO
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CFG_FUNC0 | DWI_DRIVE_STR, // DWI_CLK -> DWI_AP_CLK
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CFG_OUT_0, // SENSOR0_RST -> CAM0_SHUTDOWN
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CFG_FUNC0 | CAM_CLK_DRIVE_STR, // SENSOR0_CLK -> CAM0_CLK
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CFG_OUT_0, // SENSOR1_RST -> CAM1_SHUTDOWN
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CFG_FUNC0 | CAM_CLK_DRIVE_STR, // SENSOR1_CLK -> CAM1_CLK
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CFG_FUNC0, // CPU0_SWITCH -> CPU0_SWITCH
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CFG_FUNC0, // CPU1_SWITCH -> CPU1_SWITCH
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/* Port 10 */
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CFG_OUT_0, // ISP0_PRE_FLASH -> CAM0_TORCH
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CFG_DISABLED, // ISP0_FLASH -> CLK32K_GRAPE_RESET_L
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CFG_DISABLED | PULL_DOWN, // ISP1_PRE_FLASH -> ISP1_PRE_FLASH
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CFG_DISABLED, // ISP1_FLASH ->
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CFG_FUNC0, // SPI3_MOSI -> CODEC_SPI_DIN
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CFG_FUNC0, // SPI3_MISO -> CODEC_SPI_DOUT
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CFG_FUNC0, // SPI3_SCLK -> CODEC_SPI_CLK
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CFG_OUT_1, // SPI3_SSIN -> CODEC_SPI_CS
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/* Port 11 */
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CFG_FUNC0, // I2C2_SDA -> I2C2_SDA_3V0
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CFG_FUNC0, // I2C2_SCL -> I2C2_SCL_3V0
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CFG_OUT_0, // GPIO_3V0 -> HS3_CONTROL
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CFG_OUT_0, // GPIO_3V1 -> HS4_CONTROL
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CFG_FUNC0 | PULL_DOWN, // DP_HPD -> DP_HPD
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CFG_DISABLED | PULL_DOWN, // LPDP_HPD -> LPDP_HPD
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CFG_OUT_1, // UART0_TXD -> FLASH_ENABLE
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CFG_OUT_0, // UART0_RXD -> VIB_PWM_EN
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/* Port 12 */
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CFG_DISABLED, // TST_CLKOUT -> TST_CLKOUT
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CFG_DISABLED, // TST_STPCLK -> TST_STPCLK
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CFG_FUNC0, // WDOG -> PMU_RESET_IN
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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/* Port 13 */
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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/* Port 14 */
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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/* Port 15 */
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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/* Port 16 */
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CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_MCK -> I2S0_MCLK
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CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_LRCK -> I2S0_LRCLK
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CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_BCLK -> I2S0_BCLK
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CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_DOUT -> I2S0_DOUT
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CFG_FUNC0, // I2S0_DIN -> I2S0_DIN
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CFG_DISABLED, // I2S1_MCK -> I2S1_MCLK
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CFG_FUNC0 | I2S_DRIVE_STR, // I2S1_LRCK -> I2S1_LRCLK
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CFG_FUNC0 | I2S_DRIVE_STR, // I2S1_BCLK -> I2S1_BCLK
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/* Port 17 */
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CFG_FUNC0 | I2S_DRIVE_STR, // I2S1_DOUT -> I2S1_DOUT
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CFG_FUNC0, // I2S1_DIN -> I2S1_DIN
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CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_MCK -> I2S_MCLK
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CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_LRCK -> I2S2_LRCK
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CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_BCLK -> I2S2_BCLK
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CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_DOUT -> I2S2_DOUT
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CFG_FUNC0, // I2S2_DIN -> I2S2_DIN
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CFG_DISABLED, // I2S3_MCK -> I2S3_MCLK
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/* Port 18 */
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CFG_FUNC0 | I2S_DRIVE_STR, // I2S3_LRCK -> I2S3_LRCK
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CFG_FUNC0 | I2S_DRIVE_STR, // I2S3_BCLK -> I2S3_BCLK
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CFG_FUNC0 | I2S_DRIVE_STR, // I2S3_DOUT -> I2S3_DOUT
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CFG_FUNC0, // I2S3_DIN -> I2S3_DIN
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CFG_DISABLED, // I2S4_MCK -> I2S4_MCLK
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CFG_FUNC0 | I2S_DRIVE_STR, // I2S4_LRCK -> I2S4_LRCK
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CFG_FUNC0 | I2S_DRIVE_STR, // I2S4_BCLK -> I2S4_BCLK
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CFG_FUNC0 | I2S_DRIVE_STR, // I2S4_DOUT -> I2S4_DOUT
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/* Port 19 */
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CFG_FUNC0, // I2S4_DIN -> I2S4_DIN
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#if PIN_CFG_DEV
|
||||
CFG_FUNC0, // SPDIF -> SPDIF
|
||||
#else
|
||||
CFG_DISABLED, // SPDIF -> SPDIF
|
||||
#endif
|
||||
CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR, // FMI0_CEN3 -> FMI0_CEN3_L
|
||||
CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR, // FMI0_CEN2 -> FMI0_CEN2_L
|
||||
CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR, // FMI0_CEN1 -> FMI0_CEN1_L
|
||||
CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR, // FMI0_CEN0 -> FMI0_CEN0_L
|
||||
CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR, // FMI0_CLE -> FMI0_CLE
|
||||
CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR, // FMI0_ALE -> FMI0_ALE
|
||||
|
||||
/* Port 20 */
|
||||
CFG_FUNC0 | FMI_HI_SPEED_DRIVE_STR, // FMI0_REN -> FMI0_RE_N
|
||||
CFG_FUNC0 | FMI_HI_SPEED_DRIVE_STR, // FMI0_WEN -> FMI0_WE_L
|
||||
#if DISABLE_OPTIONAL_SIGNALS
|
||||
CFG_DISABLED | PULL_DOWN | FMI_HI_SPEED_DRIVE_STR, // FMI0_WENN -> FMI0_RE_P
|
||||
#else
|
||||
CFG_FUNC0 | FMI_HI_SPEED_DRIVE_STR, // FMI0_WENN -> FMI0_RE_P
|
||||
#endif
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI0_IO7 -> FMI0_IO[7]
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI0_IO6 -> FMI0_IO[6]
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI0_IO5 -> FMI0_IO[5]
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI0_IO4 -> FMI0_IO[4]
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI0_DQS -> FMI0_DQS_P
|
||||
|
||||
/* Port 21 */
|
||||
#if DISABLE_OPTIONAL_SIGNALS
|
||||
CFG_DISABLED | PULL_UP | FMI_HI_SPEED_DRIVE_STR, // FMI0_DQSN -> FMI0_DQS_N
|
||||
#else
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI0_DQSN -> FMI0_DQS_N
|
||||
#endif
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI0_IO3 -> FMI0_IO[3]
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI0_IO2 -> FMI0_IO[2]
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI0_IO1 -> FMI0_IO[1]
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI0_IO0 -> FMI0_IO[0]
|
||||
CFG_DISABLED | FMI_LO_SPEED_DRIVE_STR, // FMI0_CEN7 ->
|
||||
CFG_DISABLED | FMI_LO_SPEED_DRIVE_STR, // FMI0_CEN6 ->
|
||||
CFG_DISABLED | FMI_LO_SPEED_DRIVE_STR, // FMI0_CEN5 ->
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED | FMI_LO_SPEED_DRIVE_STR, // FMI0_CEN4 ->
|
||||
CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR, // FMI1_CEN3 -> FMI1_CEN3_L
|
||||
CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR, // FMI1_CEN2 -> FMI1_CEN2_L
|
||||
CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR, // FMI1_CEN1 -> FMI1_CEN1_L
|
||||
CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR, // FMI1_CEN0 -> FMI1_CEN0_L
|
||||
CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR, // FMI1_CLE -> FMI1_CLE
|
||||
CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR, // FMI1_ALE -> FMI1_ALE
|
||||
CFG_FUNC0 | FMI_HI_SPEED_DRIVE_STR, // FMI1_REN -> FMI1_RE_N
|
||||
|
||||
/* Port 23 */
|
||||
CFG_FUNC0 | FMI_HI_SPEED_DRIVE_STR, // FMI1_WEN -> FMI1_WE_L
|
||||
#if DISABLE_OPTIONAL_SIGNALS
|
||||
CFG_DISABLED | PULL_DOWN | FMI_HI_SPEED_DRIVE_STR, // FMI1_WENN -> FMI1_RE_P
|
||||
#else
|
||||
CFG_FUNC0 | FMI_HI_SPEED_DRIVE_STR, // FMI1_WENN -> FMI1_RE_P
|
||||
#endif
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI1_IO7 -> FMI1_IO[7]
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI1_IO6 -> FMI1_IO[6]
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI1_IO5 -> FMI1_IO[5]
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI1_IO4 -> FMI1_IO[4]
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI1_DQS -> FMI1_DQS_P
|
||||
#if DISABLE_OPTIONAL_SIGNALS
|
||||
CFG_DISABLED | PULL_UP | FMI_HI_SPEED_DRIVE_STR, // FMI1_DQSN -> FMI1_DQS_N
|
||||
#else
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI1_DQSN -> FMI1_DQS_N
|
||||
#endif
|
||||
|
||||
/* Port 24 */
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI1_IO3 -> FMI1_IO[3]
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI1_IO2 -> FMI1_IO[2]
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI1_IO1 -> FMI1_IO[1]
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR, // FMI1_IO0 -> FMI1_IO[0]
|
||||
CFG_DISABLED | FMI_LO_SPEED_DRIVE_STR, // FMI1_CEN7 ->
|
||||
CFG_DISABLED | FMI_LO_SPEED_DRIVE_STR, // FMI1_CEN6 ->
|
||||
CFG_DISABLED | FMI_LO_SPEED_DRIVE_STR, // FMI1_CEN5 ->
|
||||
CFG_DISABLED | FMI_LO_SPEED_DRIVE_STR, // FMI1_CEN4 ->
|
||||
|
||||
/* Port 25 */
|
||||
CFG_OUT_0 | PULL_DOWN, // GPIO20 -> WLAN_HSIC3_RESUME
|
||||
CFG_IN | PULL_DOWN, // GPIO21 -> GRAPE_INT_L
|
||||
CFG_OUT_0, // GPIO22 -> LCD_RESET_L
|
||||
CFG_IN, // GPIO23 -> LCD_HIFA_BSYNC
|
||||
CFG_IN, // GPIO24 -> BB_RST_L
|
||||
CFG_DISABLED, // GPIO25 -> BOOT_CONFIG[1]
|
||||
CFG_IN | PULL_DOWN, // GPIO26 -> FORCE_DFU
|
||||
CFG_DISABLED | PULL_DOWN, // GPIO27 -> DFU_STATUS
|
||||
|
||||
/* Port 26 */
|
||||
CFG_DISABLED, // GPIO28 -> BOOT_CONFIG[2]
|
||||
CFG_DISABLED, // GPIO29 -> BOOT_CONFIG[3]
|
||||
CFG_IN | PULL_UP, // GPIO30 -> CODEC_INT_L
|
||||
CFG_IN | PULL_DOWN, // GPIO31 -> DEV_HSIC1_RDY
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
|
||||
/* Port 27 */
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
|
||||
/* Port 28 */
|
||||
CFG_IN, // GPIO32 -> RADIO_ON_L
|
||||
CFG_IN | PULL_DOWN, // GPIO33 -> GYRO_INT1
|
||||
CFG_IN | PULL_UP, // GPIO34 -> COMPASS_BRD_INT
|
||||
CFG_OUT_0, // GPIO35 -> AP_WAKE_MODEM
|
||||
CFG_IN | PULL_DOWN, // GPIO36 -> ACCEL_INT2_L
|
||||
CFG_OUT_0, // GPIO37 -> THS7380_SEL
|
||||
CFG_IN | PULL_UP, // GPIO38 -> ALS_INT_L
|
||||
CFG_OUT_0, // GPIO39 -> GRAPE_RESET_L
|
||||
};
|
||||
|
||||
#undef HI_DRIVE_STR
|
||||
#undef BB_UART_DRIVE_STR
|
||||
#undef BT_UART_DRIVE_STR
|
||||
#undef DOCK_UART_DRIVE_STR
|
||||
#undef SWI_UART_DRIVE_STR
|
||||
#undef WIFI_UART_DRIVE_STR
|
||||
#undef FMI_LO_SPEED_DRIVE_STR
|
||||
#undef FMI_HI_SPEED_DRIVE_STR
|
||||
#undef GRAPE_IO_DRIVE_STR
|
||||
#undef GRAPE_CLK_DRIVE_STR
|
||||
#undef DWI_DRIVE_STR
|
||||
#undef I2C_DRIVE_STR
|
||||
#undef I2S_DRIVE_STR
|
||||
#undef CAM_I2C_DRIVE_STR
|
||||
#undef CAM_STROBE_DRIVE_STR
|
||||
#undef CAM_CLK_DRIVE_STR
|
||||
#undef DISABLE_OPTIONAL_SIGNALS
|
||||
@@ -0,0 +1,138 @@
|
||||
/*
|
||||
* Copyright (C) 2010-2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_POWERCONFIG_H
|
||||
#define __TARGET_POWERCONFIG_H
|
||||
|
||||
/* configuration per target */
|
||||
|
||||
#define PMU_IIC_BUS 0
|
||||
|
||||
/* this configuration is very PMU specific and must be included exactly once in power.c */
|
||||
#ifdef POWERCONFIG_PMU_SETUP
|
||||
|
||||
/* Matched to D1972A2-OTP-AE-v2 */
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kD1972_LDO1, 0x0A }, // PP3V0_USB 3.00V
|
||||
{ PMU_IIC_BUS, kD1972_LDO2, 0x2A }, // PP1V7_VA_VCP 1.70V
|
||||
{ PMU_IIC_BUS, kD1972_LDO3, 0x0A }, // PP3V0_VIDEO 3.00V
|
||||
{ PMU_IIC_BUS, kD1972_LDO4, 0x0F }, // PP2V8_CAM0_AF 2.55V
|
||||
{ PMU_IIC_BUS, kD1972_LDO5, 0x0A }, // PP3V0_NAND 3.00V
|
||||
{ PMU_IIC_BUS, kD1972_LDO6, 0x10 }, // PP3V3_ACC 3.30V
|
||||
{ PMU_IIC_BUS, kD1972_LDO7, 0x0F }, // P3V0_IMU 3.00V
|
||||
{ PMU_IIC_BUS, kD1972_LDO8, 0x14 }, // PP3V0_USBMUX 3.00V
|
||||
|
||||
// <rdar://problem/12061759>
|
||||
{ PMU_IIC_BUS, kD1972_TEST_MODE, 0x1D },
|
||||
{ PMU_IIC_BUS, 0xF5, 0x01 },
|
||||
{ PMU_IIC_BUS, kD1972_LDO9, 0x13 }, // PP3V0_IO 3.10V
|
||||
{ PMU_IIC_BUS, 0xF5, 0x00 },
|
||||
{ PMU_IIC_BUS, kD1972_TEST_MODE, 0x00 },
|
||||
|
||||
{ PMU_IIC_BUS, kD1972_LDO10, 0x0A }, // PP3V0_OPTICAL 3.00V
|
||||
{ PMU_IIC_BUS, kD1972_LDO11, 0x17 }, // PP2V8_CAM_AVDD 2.85V
|
||||
{ PMU_IIC_BUS, kD1972_LDO12, 0x10 }, // PP1V0 1.00V
|
||||
{ PMU_IIC_BUS, kD1972_LDO16, 0xA0 }, // PP1V0_SRAM_PMU 1.00V
|
||||
{ PMU_IIC_BUS, kDIALOG_LDO_CONTROL, 0x00 }, // no bypass
|
||||
{ PMU_IIC_BUS, kD1972_BUCK_CTRL5, 0xD3 }, // Enable x_DWI_EN and CPUx_EN_CTRL
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kD1972_ACTIVE1, 0xFF }, // Everything on
|
||||
{ PMU_IIC_BUS, kD1972_ACTIVE2, 0xF4 }, // Everything but LDO3, LDO4, LDO6 on
|
||||
{ PMU_IIC_BUS, kD1972_ACTIVE3, 0xEB }, // WLED_BST, LCM_BST, LDO16, LDO_LCM2, LDO12, LDO11 on
|
||||
{ PMU_IIC_BUS, kD1972_ACTIVE4, 0xAD }, // CPU1V8, CPU1V2, CPUA_SW on
|
||||
{ PMU_IIC_BUS, kD1972_HIBERNATE1, 0x70 }, // BUCK3, BUCK4, LDO1 on
|
||||
{ PMU_IIC_BUS, kD1972_HIBERNATE2, 0x00 }, // Everything off
|
||||
{ PMU_IIC_BUS, kD1972_LCM_CONTROL1, 0x02 }, // PP5V1_GRAPE_VDDH_PMU 5.10V
|
||||
{ PMU_IIC_BUS, kD1972_LCM_CONTROL2, 0x0E }, // PP5V7_LCD_AVDDH_PMU 5.70V
|
||||
{ PMU_IIC_BUS, kD1972_LCM_CONTROL3, 0x00 }, // BB_VBUS_DET 5.00V
|
||||
{ PMU_IIC_BUS, kD1972_LCM_BST_CONTROL, 0x14 }, // LCM_VBOOST 6.00V
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_warm_init[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kDIALOG_ADC_CONTROL, kDIALOG_ADC_CONTROL_DEFAULTS },
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_cold_init[] =
|
||||
{
|
||||
/* Note: the following differences from OTP are intentional:
|
||||
- GPIO2,6,7,10 enable wake
|
||||
- GPIO5 enables CLK32
|
||||
- GPIO8 enables wake up and state change
|
||||
- GPIO10 pullup
|
||||
*/
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_1, 0xB9 }, // CLK32K_GRAPE_RESET_L In, R Edge, No Wake, No PU
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_2, 0xBA }, // BB_WAKE_AP In, R Edge, Wake, No PU
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_3, 0x09 }, // BB_PMU_ON_R_L Out 0, Push-Pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_4, 0x7A }, // TRISTAR_INT In, L High, Wake, No PU
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_5, 0x49 }, // CLK32K_WIFI Out 0, Push-Pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_6, 0xDA }, // BATTERY_SWI In, F Edge, Out Hib, Wake, PD, No PU
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_7, 0xBB }, // HOST_WAKE_WLAN In, R Edge, Wake, PD, No PU
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_8, 0xEA }, // MIKEY_INT_L In, Any Edge, Wake, PU, VBUCK3
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_9, 0x09 }, // BT_REG_ON_R Out 0, Push-Pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_10, 0xAA }, // HOST_WAKE_BT In, R Edge, Wake, PU, VBUCK3
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_11, 0x09 }, // WIFI_REG_ON_R Out 0, Push-Pull, VBUCK3
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_12, 0xB9 }, // PMU_DBG_GPIO12 In, R Edge, No Wake, No PU
|
||||
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_DEB1, 0x12 },
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_DEB2, 0x12 },
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_DEB3, 0x02 }, // no debounce on GPIO6 [OTP: 0x12]
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_DEB4, 0x02 }, // no debounce on GPIO8 [OTP: 0x12]
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_DEB5, 0x12 },
|
||||
{ PMU_IIC_BUS, kD1972_SYS_GPIO_DEB6, 0x12 },
|
||||
|
||||
{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2, 0x11 }, // enable HIB_32kHz (for WIFI/BT) & DWI
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_backlight_enable[] =
|
||||
{
|
||||
};
|
||||
|
||||
static const struct pmu_setup_struct pmu_backlight_disable[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, 0x0 } // disable LED power
|
||||
};
|
||||
|
||||
static const struct core_rails_struct soc_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kDIALOG_BUCK2 }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct cpu_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kDIALOG_BUCK0 }
|
||||
};
|
||||
|
||||
static const struct core_rails_struct ram_rails[] =
|
||||
{
|
||||
{ PMU_IIC_BUS, 0, kD1972_LDO16 }
|
||||
};
|
||||
|
||||
#endif /* POWERCONFIG_PMU_SETUP */
|
||||
|
||||
#define NO_BATTERY_VOLTAGE 2700
|
||||
#define MIN_BOOT_BATTERY_VOLTAGE 3600
|
||||
#define TARGET_BOOT_BATTERY_VOLTAGE 3700
|
||||
#define TARGET_BOOT_BATTERY_CAPACITY 50
|
||||
#define PRECHARGE_BACKLIGHT_LEVEL 824
|
||||
|
||||
#define TARGET_DISPLAY_VOLTAGE_BASE 6000
|
||||
#define TARGET_DISPLAY_VOLTAGE_SCALE 50
|
||||
#define TARGET_DISPLAY_BOOST_LDO kD1972_LCM_CONTROL2
|
||||
#define TARGET_DISPLAY_BOOST_OFFSET 300
|
||||
|
||||
#define ACC_PWR_LDO (6)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_RADIOCONFIG_H
|
||||
#define __TARGET_RADIOCONFIG_H
|
||||
|
||||
/* configuration per target */
|
||||
|
||||
#define RADIO_VERIFY_BASEBAND_EXISTS 1
|
||||
|
||||
static const gpio_t target_radio_quiesce_pins[] =
|
||||
{
|
||||
GPIO_UART1_TXD
|
||||
};
|
||||
|
||||
#define RADIO_ENABLE_IMEI_OVERRIDE 0
|
||||
|
||||
#endif /* ! __TARGET_RADIOCONFIG_H */
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define two debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (6)
|
||||
|
||||
/* define radio serial port */
|
||||
#define RADIO_SERIAL_PORT (1)
|
||||
#define RADIO_MAX_READ_ERRORS (10)
|
||||
|
||||
/* define HDQ serial port */
|
||||
#define HDQGAUGE_SERIAL_PORT (5)
|
||||
|
||||
#define UART_FLOWCONTROL_MASK (0x08)
|
||||
|
||||
#endif
|
||||
Reference in new issue
Block a user