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@@ -0,0 +1,27 @@
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/*
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* Copyright (C) 2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ADBE_SETTINGS_H
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#define __TARGET_ADBE_SETTINGS_H
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static struct adbe_v1_tuneable adbe_tuneables[] = {
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{
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.name = "default",
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.adbe0_vblank_pos_vbi_pulse = 0x0000,
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.adbe0_vblank_clk_gate_wakeup = 0x0000,
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.adbe0_vblank_clk_gate_idle = 0x0001,
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.adbe0_vblank_blk_idle_dpb = 0x0000,
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.adbe0_vblank_blk_idle_aap = 0x0000,
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.adbe0_tunable_mode_ctrl = (DBEMODECNTL_DYN_CLK_GATE_ENABLE | DBEMODECNTL_AFC_TEARDOWN_ENABLE | DBEMODECNTL_PMGR_CLK_GATE_ENABL| DBEMODECNTL_BLK_CLK_GATE_ENABLE),
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.adbe0_aap_support = 1,
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},
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};
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#endif
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@@ -0,0 +1,39 @@
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/*
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* Copyright (C) 2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ASPNANDCONFIG_H
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#define __TARGET_ASPNANDCONFIG_H
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//MLC devices
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#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
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#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_DIES_IN_PARALLEL 4
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#define ASPNAND_READ_DIES_IN_PARALLEL 4
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#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
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//TLC devices
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#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
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// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
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#define ASPNAND_INDIRECTION_MEMORY (4*1024*1024)
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#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
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#endif
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@@ -0,0 +1,46 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* iPhone6,x specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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#define GPIO_SOCHOT0_IN GPIO(15, 0) // BB_TO_AP_SOCHOT0
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#define GPIO_LCD_RST GPIO(12, 6) // AP_TO_LCM_RESET_L
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#define GPIO_LCD_RST_POLARITY (0)
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#define GPIO_X162_INT GPIO( 9, 7) // NAVAJO_TO_PMU_INT_H
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#define GPIO_RINGER_AB GPIO( 2, 0)
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#define GPIO_WDOG GPIO( 0, 1) // WDOG
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/* Board Revision */
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#define GPIO_BOARD_REV0 GPIO(14, 5)
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#define GPIO_BOARD_REV1 GPIO(14, 4)
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#define GPIO_BOARD_REV2 GPIO(14, 3)
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#define GPIO_BOARD_REV3 GPIO(14, 2)
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/* which IICs to initialize */
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#define IICS_MASK (3)
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#define TRISTAR_IIC_BUS (0)
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#define DISPLAY_PMU_IIC_BUS (0)
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/* D2094 watchdog tickle, 'KEEPACT' */
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#define GPIO_WDOG_TICKLE GPIO(2, 5)
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,91 @@
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD2045_ACTIVE3, 0xAE }, // Current OTP enables LDO{1,2,3,4,5,7}, disable LDO4.
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{ PMU_IIC_BUS, kD2045_ACTIVE6, 0x37 }, // enable BUCK3_SW1, BUCK3_SW2, BUCK3_SW3, BUCK4_SW1, BUCK4_SW2
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{ PMU_IIC_BUS, kD2045_ACTIVE3, 0xBE }, // enable LDO4 along with LDO{1,2,3,5,7}
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{ PMU_IIC_BUS, kD2045_HIBERNATE1, 0x18 },
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{ PMU_IIC_BUS, kD2045_HIBERNATE3, 0x18 },
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{ PMU_IIC_BUS, kD2045_HIBERNATE6, 0x24 },
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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};
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// NOTE: <rdar://problem/13296265> N51 PMU continuously reboots when VBatt is near UVLO
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// ** GPIO4,GPIO8, and GPIO12 are enabled using the gpio-activate-defaults property in the device tree.
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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{ PMU_IIC_BUS, kD2045_GPIO2, 0x7A }, // BB_TO_PMU_HOST_WAKE In, L High, Wake, No PU
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{ PMU_IIC_BUS, kD2045_GPIO3, 0x09 }, // PMU_TO_BB_RST_R_L Out 0, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD2045_GPIO4, 0x78 }, // TRISTAR_TO_AP_INT In, L High, Wake**, No PU
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{ PMU_IIC_BUS, kD2045_GPIO6, 0xDA }, // AP_BI_BATTERY_SWI In, F Edge, Out Hib, Wake, PD, No PU
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{ PMU_IIC_BUS, kD2045_GPIO7, 0xBB }, // WLAN_TO_PMU_HOST_WAKE In, R Edge, Wake, PD, No PU
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{ PMU_IIC_BUS, kD2045_GPIO8, 0xE8 }, // CODEC_TO_PMU_MIKEY_INT_L In, Any Edge, Wake**, PU, VBUCK3
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{ PMU_IIC_BUS, kD2045_GPIO9, 0x09 }, // PMU_TO_BT_REG_ON_R Out 0, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD2045_GPIO10, 0xAA }, // BT_TO_PMU_HOST_WAKE In, R Edge, Wake, PU, VBUCK3
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{ PMU_IIC_BUS, kD2045_GPIO11, 0x09 }, // PMU_TO_WLAN_REG_ON_R Out 0, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD2045_GPIO12, 0xB9 }, // NAVAJO_TO_PMU_INT_L In, R Edge, Wake**, No PU
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{ PMU_IIC_BUS, kD2045_GPIO13, 0x7B }, // OSCAR_TO_PMU_HOST_WAKE In, L High, Wake, PD, No PU
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{ PMU_IIC_BUS, kD2045_GPIO14, 0x49 }, // PMU_TO_OSCAR_CLK_32K Out 32K, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD2045_GPIO15, 0x01 }, // PMU_TO_BB_VBUS_DET Out 0, Push-Pull, VCC_MAIN
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{ PMU_IIC_BUS, kD2045_GPIO16, 0x38 }, // <rdar://problem/14062728> N5x PMU | Set GPIO16 to 0x38 to better support OTP-AQ on DVT boards
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{ PMU_IIC_BUS, kD2045_OUT_32K, 0x49 }, // OUT_32K (WLAN_CLK32K) Out 32K, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD2045_GPIO_DEB2, 0x12 },
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{ PMU_IIC_BUS, kD2045_GPIO_DEB5, 0x12 },
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{ PMU_IIC_BUS, kD2045_GPIO_DEB6, 0x12 },
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{ PMU_IIC_BUS, kD2045_BUCK_DWI_CTRL0, 0x03 }, // enable DWI for BUCK0, BUCK1
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{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2, 0x11 }, // enable HIB_32kHz (for WIFI/BT) and DWI
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{ PMU_IIC_BUS, kD2045_ACT_TO_HIB_DLY, 0x03 }, // set ACT_TO_HIB_DLY to 3 (6ms)
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{ PMU_IIC_BUS, 0x7000, 0x1D }, // Enable Test Mode
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{ PMU_IIC_BUS, kD2045_ADC_FSM_TRIM2, 0x00 }, // <rdar://problem/14276806> Enable offset correction on Amber IBUS ADC
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{ PMU_IIC_BUS, 0x7000, 0x00 }, // Disable Test Mode
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};
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static const struct core_rails_struct soc_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2045_BUCK2_VSEL }
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};
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static const struct core_rails_struct cpu_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2045_BUCK0_VSEL }
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};
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static const struct core_rails_struct ram_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2045_BUCK5_VSEL }
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};
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#endif /* POWERCONFIG_PMU_SETUP */
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#define NO_BATTERY_VOLTAGE 2700
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#define MIN_BOOT_BATTERY_VOLTAGE 3600
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#define TARGET_BOOT_BATTERY_VOLTAGE 3700
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#define TARGET_BOOT_BATTERY_CAPACITY 50
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#define PRECHARGE_BACKLIGHT_LEVEL 824
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#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
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#define ACC_PWR_LDO (6)
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#endif
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@@ -0,0 +1,23 @@
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/*
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* Copyright (C) 2012, 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
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#ifndef __TARGET_UARTCONFIG_H
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#define __TARGET_UARTCONFIG_H
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/* define one debug serial ports */
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#define DEBUG_SERIAL_PORT (0)
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#define HDQGAUGE_SERIAL_PORT (5)
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#if SUPPORT_FPGA
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#define UART_OVERSAMPLE_OVERRIDE (11)
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#endif
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#endif
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@@ -0,0 +1,571 @@
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/*
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* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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*/
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#include <debug.h>
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#include <drivers/display.h>
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#if WITH_HW_DISPLAY_PMU
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#include <drivers/display_pmu.h>
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#endif
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#include <drivers/flash_nor.h>
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#include <drivers/iic.h>
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#include <drivers/power.h>
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#include <lib/devicetree.h>
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#include <lib/env.h>
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#include <lib/mib.h>
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#include <lib/paint.h>
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#include <lib/syscfg.h>
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#include <platform.h>
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#include <platform/chipid.h>
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#include <platform/gpio.h>
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#include <platform/gpiodef.h>
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#include <platform/memmap.h>
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#include <platform/soc/hwregbase.h>
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#include <platform/soc/pmgr.h>
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#include <sys.h>
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#include <sys/boot.h>
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#include <sys/menu.h>
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#include <sys/task.h>
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#include <target.h>
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#include <platform/soc/display_color_manager_tables.h>
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///////////////////////////////////////////////////////////
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// CHESTNUT LDO assignment
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//
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// LCM SAGE GRAPE
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//
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// DEV1 1 2 3
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// N51-PROTO2 1 1 2
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// N53-PROTO2/2A 2 1 3
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// DEV2/EVT1 2 1 3
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//
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///////////////////////////////////////////////////////////
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#define N51_N53_DEV1_PROTO2_BOARD (0xF)
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#define N53_PROTO2A_BOARD (0xE)
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#define N51_N53_DEV2_BOARD (0xE)
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#define N51_EVT1_MAIN_BOARD (0xE)
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#define N51_EVT1_MESA_BOARD (0xD)
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#define N53_EVT1_MAIN_BOARD N51_EVT1_MESA_BOARD
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#define N51_N53_DEV3_BOARD (0xD) // XXX we got this wrong, should have matched EVT1C.
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#define N51_N53_EVT1A_BOARD (0xC)
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#define N51_N53_EVT1B_BOARD (0xB) // presumably
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#define N51_N53_EVT1C_BOARD (0xA)
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#define N51_N53_EVT2_BOARD (0x9)
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static uint32_t iphone6_get_board_rev(void);
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static bool gpio_board_rev_valid;
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static uint32_t gpio_board_rev;
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static uint32_t display_config;
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MIB_CONSTANT(kMIBTargetBacklight0I2CBus, kOIDTypeUInt32, 0);
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MIB_CONSTANT(kMIBTargetBacklight0I2CAddress, kOIDTypeUInt32, 0xC6);
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
MIB_CONSTANT(kMIBTargetDisplayCMEngammaTablePtr, kOIDTypeStruct, (void *)linear_rgb_engamma_tables);
|
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MIB_CONSTANT(kMIBTargetDisplayCMEngammaTableCount, kOIDTypeUInt32, ARRAY_SIZE(linear_rgb_engamma_tables));
|
||||
MIB_CONSTANT(kMIBTargetDisplayCMDegammaTablePtr, kOIDTypeStruct, (void *)linear_rgb_degamma_tables);
|
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MIB_CONSTANT(kMIBTargetDisplayCMDegammaTableCount, kOIDTypeUInt32, ARRAY_SIZE(linear_rgb_degamma_tables));
|
||||
MIB_CONSTANT(kMIBTargetDisplayCMMatrixTablePtr, kOIDTypeStruct, (void *)linear_identity_matrix_tables);
|
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MIB_CONSTANT(kMIBTargetDisplayCMMatrixTableCount, kOIDTypeUInt32, ARRAY_SIZE(linear_identity_matrix_tables));
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||||
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||||
static uint32_t iphone6_get_board_rev(void)
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{
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if (!gpio_board_rev_valid) {
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gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
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gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
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gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
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gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_IN);
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gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PDN);
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gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PDN);
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||||
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PDN);
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||||
gpio_configure_pupdn(GPIO_BOARD_REV3, GPIO_PDN);
|
||||
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||||
spin(100); // Wait 100us
|
||||
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||||
gpio_board_rev =
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(gpio_read(GPIO_BOARD_REV3) << 3) |
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||||
(gpio_read(GPIO_BOARD_REV2) << 2) |
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||||
(gpio_read(GPIO_BOARD_REV1) << 1) |
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||||
(gpio_read(GPIO_BOARD_REV0) << 0);
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
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||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
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gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_DFLT);
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||||
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||||
gpio_board_rev_valid = true;
|
||||
}
|
||||
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||||
return gpio_board_rev;
|
||||
}
|
||||
|
||||
static bool is_dev1_board()
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||||
{
|
||||
// DEV config: board-id == 1
|
||||
// DEV1 board-rev == 0xF
|
||||
if (((rPMGR_SCRATCH0 >> 16) & 0xf) == 1)
|
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return (iphone6_get_board_rev() == N51_N53_DEV1_PROTO2_BOARD);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool is_n51_proto2_board()
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||||
{
|
||||
// N51 board-id == 0
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||||
// Proto2 board-rev == 0xF
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||||
if (((rPMGR_SCRATCH0 >> 16) & 0xf) == 0)
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return (iphone6_get_board_rev() == N51_N53_DEV1_PROTO2_BOARD);
|
||||
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||||
return false;
|
||||
}
|
||||
|
||||
static bool is_n53_proto2_board()
|
||||
{
|
||||
// N53 board-id == 2
|
||||
// Proto2a board-rev == 0xF
|
||||
if (((rPMGR_SCRATCH0 >> 16) & 0xf) == 2)
|
||||
return (iphone6_get_board_rev() == N51_N53_DEV1_PROTO2_BOARD);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool is_mesa_supported()
|
||||
{
|
||||
// X162 INT line needs to be configured active high only on supported boards
|
||||
// Any DEV board and N51_EVT1_MESA_BOARD and all EVT2 boards and forward.
|
||||
|
||||
// Return true if DEV board.
|
||||
if ( (((rPMGR_SCRATCH0 >> 16) & 0xf) == 1) || (iphone6_get_board_rev() <= N51_EVT1_MESA_BOARD) )
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
}
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
if(is_mesa_supported()) {
|
||||
// Configure the X162 INT line to be active high.
|
||||
// Currently doing this for all DEV boards and EVT1 MESA board
|
||||
gpio_configure(GPIO_X162_INT, GPIO_CFG_IN);
|
||||
gpio_configure_pupdn(GPIO_X162_INT, GPIO_PDN);
|
||||
}
|
||||
if (iphone6_get_board_rev() == N51_N53_EVT1A_BOARD) {
|
||||
// <rdar://problem/12982626> Switch Tristar to Pulsing Con Detect mode for n5x and n48/n49
|
||||
iic_write(0, 0x35, (uint8_t[]){ 0x1e, 0x30 }, 2);
|
||||
}
|
||||
if ((iphone6_get_board_rev() <= N51_N53_EVT1A_BOARD) && (iphone6_get_board_rev() > N51_N53_EVT1C_BOARD)) {
|
||||
// LDO9 (PP2V8_CAM) to 2.85V <rdar://problem/12660594> (Amber >= A1 version)
|
||||
// NOTE: Boards with Amber A0 version is handled via power_init pmu_ldo_cold_setup_a0
|
||||
iic_write(0, 0xe8, (uint8_t[]){ 0x03, 0x48, 0x5A }, 3);
|
||||
}
|
||||
if (iphone6_get_board_rev() <= N51_N53_EVT1C_BOARD) {
|
||||
// <rdar://problem/13255750> Override pin config to support SOCHOT0 throttler circuit on N5x E1C+
|
||||
gpio_configure_pupdn(GPIO_SOCHOT0_IN, GPIO_NO_PUPDN);
|
||||
|
||||
// <rdar://problem/13180654> N5x | Set LDO9 to 2.80V for power throttler circuit
|
||||
// LDO9_VSEL = 2.8V (0.6V + 25mV*LDO9_VSEL)
|
||||
iic_write(0, 0xe8, (uint8_t[]){ 0x03, 0x48, 0x58 }, 3);
|
||||
|
||||
// <rdar://problem/13766537> N5x EVT2 | Change LDO3 and LDO13 voltages for Amber OTP-AP and older
|
||||
// For OTP-AP and older, which is determined by PMU register 0x0001 containing a value 0x16 or lower
|
||||
// - We need to overwrite LDO3 with 0x60 (used to be 0x64)
|
||||
// - And we need to overwrite LDO13 with 0x64 (used to be 0x60)
|
||||
|
||||
uint8_t addr[2] = {0x00,0x01};
|
||||
uint8_t data;
|
||||
if (iic_read(0, 0xe8, &addr, sizeof(addr), &data, sizeof(data), IIC_NORMAL) == 0) {
|
||||
if (data <= 0x16) {
|
||||
iic_write(0, 0xe8, (uint8_t[]){ 0x03, 0x18, 0x60 }, 3);
|
||||
iic_write(0, 0xe8, (uint8_t[]){ 0x03, 0x68, 0x64 }, 3);
|
||||
}
|
||||
}
|
||||
}
|
||||
else { // pre-EVT2 HW
|
||||
// Hack to support Mesa on older HW
|
||||
// // <rdar://problem/13503359> N5x EVT2 and beyond - increase drive strength of Mesa SPI_CLK to 8mA (x4), slow slew
|
||||
{
|
||||
uintptr_t mesa_spi_clk_gpio;
|
||||
uint32_t mesa_spi_clk_gpio_val;
|
||||
|
||||
mesa_spi_clk_gpio = (uintptr_t)(GPIO_BASE_ADDR + 0x130); // SPI2_SCLK -> AP_TO_NAVAJO_SPI2_CLK
|
||||
mesa_spi_clk_gpio_val = *(volatile uint32_t *)mesa_spi_clk_gpio;
|
||||
mesa_spi_clk_gpio_val &= ~(3 << 10); // reset drive strength
|
||||
mesa_spi_clk_gpio_val |= (1 << 10); // set drive strength to X2
|
||||
*(volatile uint32_t *)mesa_spi_clk_gpio = mesa_spi_clk_gpio_val;
|
||||
}
|
||||
}
|
||||
|
||||
// <rdar://problem/14181542> N5x AP_DEV: Enable GPIO5 for WLAN_CLK32K instead of CLK32K_OUT
|
||||
if (((rPMGR_SCRATCH0 >> 16) & 0xf) == 1) {
|
||||
iic_write(0, 0xe8, (uint8_t[]){ 0x04, 0x04, 0x49 }, 3); // GPIO5 Out 32K, Push-Pull, VBUCK3
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return platform_get_request_dfu2() && power_has_usb();
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
#if WITH_HW_POWER
|
||||
if (power_get_boot_flag() == kPowerBootFlagColdButton) *cold_button_boot = true;
|
||||
#else
|
||||
*cold_button_boot = false;
|
||||
#endif // WITH_HW_POWER
|
||||
|
||||
return !*cold_button_boot || platform_get_request_dfu1();
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
uint32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
void * target_get_display_configuration(void)
|
||||
{
|
||||
display_config = 0x00000da2;
|
||||
return ((void *)(&display_config));
|
||||
}
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
env_set("boot-device", "asp_nand", 0);
|
||||
env_set("display-color-space","RGB888", 0);
|
||||
env_set("display-timing", "n51", 0);
|
||||
}
|
||||
|
||||
#endif // WITH_ENV
|
||||
|
||||
bool target_has_tristar2(void)
|
||||
{
|
||||
return iphone6_get_board_rev() != N51_N53_DEV1_PROTO2_BOARD;
|
||||
}
|
||||
|
||||
#if WITH_HW_CHESTNUT
|
||||
uint8_t target_get_lcm_ldos(void)
|
||||
{
|
||||
if (is_n51_proto2_board())
|
||||
return DISPLAY_PMU_LDO(0);
|
||||
|
||||
return (DISPLAY_PMU_LDO(0) | DISPLAY_PMU_LDO(1));
|
||||
}
|
||||
#endif
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
#if WITH_HW_DISPLAY_PINOT
|
||||
DTNode *disp0_node, *backlight_node;
|
||||
#endif
|
||||
DTNode *node;
|
||||
uint32_t propSize;
|
||||
char *propName, *propStr;
|
||||
void *propData;
|
||||
|
||||
#if WITH_HW_DISPLAY_PINOT
|
||||
// Find the DISP0 (display-subsystem 0) node
|
||||
FindNode(0, "arm-io/disp0", &disp0_node);
|
||||
|
||||
if (FindNode(0, "arm-io/mipi-dsim/lcd", &node)) {
|
||||
extern int pinot_update_device_tree(DTNode *pinot_node, DTNode *clcd_node, DTNode *backlight_node);
|
||||
|
||||
FindNode(0, "backlight", &backlight_node);
|
||||
pinot_update_device_tree(node, disp0_node, backlight_node);
|
||||
|
||||
// Fix up LCM LDO for dev1 and n51proto2
|
||||
if (is_dev1_board() || is_n51_proto2_board()) {
|
||||
propName = "function-lcd_ldo";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
((uint8_t *)propData)[8] = 0; // V01 -> PP5V7_LCM_AVDDH_CHESTNUT
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
// Update the codec and speaker nodes with acoustic transducer scale data
|
||||
{
|
||||
uint8_t atscData[20];
|
||||
|
||||
if (syscfgCopyDataForTag('ATSc', atscData, sizeof(atscData)) > 0) {
|
||||
// Update codec
|
||||
if (FindNode(0, "arm-io/spi3/audio-codec", &node)) {
|
||||
propName = "at-scale-imic";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
memcpy(propData, &atscData[0], sizeof(uint32_t));
|
||||
}
|
||||
propName = "at-scale-smic";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
memcpy(propData, &atscData[4], sizeof(uint32_t));
|
||||
}
|
||||
propName = "at-scale-fmic";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
memcpy(propData, &atscData[8], sizeof(uint32_t));
|
||||
}
|
||||
propName = "at-scale-rcvr";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
memcpy(propData, &atscData[12], sizeof(uint32_t));
|
||||
}
|
||||
}
|
||||
// Update speaker
|
||||
if (FindNode(0, "arm-io/i2c0/audio-speaker", &node)) {
|
||||
propName = "at-scale";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
memcpy(propData, &atscData[16], sizeof(uint32_t));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Update the als calibration data
|
||||
if (FindNode(0, "arm-io/i2c1/als", &node)) {
|
||||
propName = "alsCalibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('AlsC', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the backlight calibration data
|
||||
if (FindNode(0, "backlight", &node)) {
|
||||
propName = "backlight-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
syscfgCopyDataForTag('BLCl', propData, propSize);
|
||||
}
|
||||
|
||||
// Update the compass calibration data
|
||||
if (FindNode(0, "arm-io/uart2/oscar/compass", &node)) {
|
||||
propName = "compass-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('CPAS', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the X162 calibration data
|
||||
if (FindNode(0, "arm-io/spi2/mesa", &node)) {
|
||||
propName = "calibration-blob";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('FSCl', propData, propSize);
|
||||
}
|
||||
propName = "modulation-ratio";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('NvMR', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the gyro calibration data
|
||||
if (FindNode(0, "arm-io/uart2/oscar/gyro", &node)) {
|
||||
propName = "gyro-orientation";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GRot', propData, propSize);
|
||||
}
|
||||
propName = "gyro-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GSCl', propData, propSize);
|
||||
}
|
||||
propName = "gyro-temp-table";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GYTT', propData, propSize);
|
||||
}
|
||||
propName = "gyro-interrupt-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GICl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update accelerometer calibration data
|
||||
if (FindNode(0, "arm-io/uart2/oscar/accelerometer", &node)) {
|
||||
propName = "accel-orientation";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ARot', propData, propSize);
|
||||
}
|
||||
propName = "low-temp-accel-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LTAO', propData, propSize);
|
||||
}
|
||||
propName = "accel-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ASCl', propData, propSize);
|
||||
}
|
||||
propName = "accel-interrupt-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('AICl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update prox calibration data
|
||||
if (FindNode(0, "arm-io/spi1/multi-touch", &node)) {
|
||||
propName = "prox-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
syscfgCopyDataForTag('PxCl', propData, propSize);
|
||||
}
|
||||
|
||||
// Update charger calibration data
|
||||
if (FindNode(0, "charger", &node)) {
|
||||
propName = "usb-input-limit-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
syscfgCopyDataForTag('CBAT', propData, propSize);
|
||||
}
|
||||
|
||||
// Update vibrator calibration data
|
||||
if (FindNode(0, "arm-io/i2c0/pmu/vib-pwm/vibrator", &node)) {
|
||||
uint32_t strong_vset;
|
||||
uint32_t weak_vset;
|
||||
|
||||
propName = "reg";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (syscfgCopyDataForTag('VLSg', (void *)&strong_vset, sizeof(strong_vset)) > 0)
|
||||
((uint32_t *)propData)[0] = strong_vset;
|
||||
}
|
||||
propName = "intensity-config";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (syscfgCopyDataForTag('VLWk', (void *)&weak_vset, sizeof(strong_vset)) > 0)
|
||||
((uint32_t *)propData)[1] = (((uint64_t)weak_vset << 32) + (strong_vset-1)) / strong_vset; // round up
|
||||
}
|
||||
}
|
||||
|
||||
// Multi-touch support
|
||||
if (FindNode(0, "arm-io/spi1/multi-touch", &node)) {
|
||||
propName = "compatible";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propStr = NULL;
|
||||
|
||||
if (is_dev1_board())
|
||||
propStr = "multi-touch,n41";
|
||||
else if (is_n51_proto2_board())
|
||||
propStr = "multi-touch,n51-p251";
|
||||
|
||||
if (propStr != NULL) {
|
||||
memset(propData, 0, propSize);
|
||||
strlcpy(propData, propStr, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Set Grape LDOs for proto2 board
|
||||
if (is_n51_proto2_board()) {
|
||||
propName = "function-power_ana";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
((uint8_t *)propData)[8] = 0x01; // V02 -> PP5V1_GRAPE_VDDH
|
||||
}
|
||||
}
|
||||
|
||||
// Display-pmu Sage LDO
|
||||
if (is_dev1_board()) {
|
||||
if (FindNode(0, "arm-io/i2c0/display-pmu", &node)) {
|
||||
propName = "sage-ldo";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
*(uint32_t *)propData = 0x01; // V02 -> PP5V7_SAGE_AVDDH_CHESTNUT
|
||||
}
|
||||
}
|
||||
|
||||
// TriStar 1 on older systems
|
||||
if (!target_has_tristar2()) {
|
||||
if (FindNode(0, "arm-io/i2c0/tristar", &node)) {
|
||||
propName = "compatible";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
strlcpy(propData, "tristar,cbtl1608", kPropNameLength);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Pre-E1C Camera AVDD LDO is coming from PMU LDO9
|
||||
if ((target_config_ap() && iphone6_get_board_rev() > N51_N53_EVT1C_BOARD) ||
|
||||
(!target_config_ap() && iphone6_get_board_rev() > N51_N53_DEV3_BOARD)) {
|
||||
if (FindNode(0, "arm-io/isp", &node)) {
|
||||
propName = "function-cam_avdd_ldo";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
|
||||
#if WITH_HW_DISPLAY_PMU
|
||||
display_pmu_update_device_tree("arm-io/i2c0/display-pmu");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif // WITH_DEVICETREE
|
||||
|
||||
#if WITH_PAINT
|
||||
|
||||
// The default background is expected to to be black and the artwork is expected
|
||||
// to be white. This arrangement will be inverted depending upon the cover glass
|
||||
// color of the device.
|
||||
|
||||
// Sample DClr_override values for testing devices without DClr syscfg entries (enclosure/cover glass):
|
||||
// gray/black: setenv DClr_override 000200009B9899003C3B3B0000000000
|
||||
// gold/white: setenv DClr_override 00020000B3C5D400E3E4E10000000000
|
||||
// silver/white: setenv DClr_override 00020000D8D9D700E3E4E10000000000
|
||||
|
||||
static color_policy_invert_t target_cover_glass_color_table[] = {
|
||||
{ RGB( 59, 59, 60), false }, // Black - black background, white logo
|
||||
{ RGB(225, 228, 227), true }, // White - white background, black logo
|
||||
};
|
||||
|
||||
color_policy_t *target_color_map_init(enum colorspace cs, color_policy_t *color_policy)
|
||||
{
|
||||
// Must have a color policy structure passed in.
|
||||
if (color_policy == NULL)
|
||||
goto fail;
|
||||
|
||||
// We only support the RGB888 colorspace.
|
||||
if (cs != CS_RGB888)
|
||||
goto fail;
|
||||
|
||||
color_policy->policy_type = COLOR_MAP_POLICY_INVERT;
|
||||
color_policy->color_table = (void *)target_cover_glass_color_table;
|
||||
color_policy->color_count = ARRAY_SIZE(target_cover_glass_color_table);
|
||||
color_policy->map_color = NULL; // Use standard remapper
|
||||
|
||||
return color_policy;
|
||||
|
||||
fail:
|
||||
return NULL;
|
||||
}
|
||||
#endif // WITH_PAINT
|
||||
@@ -0,0 +1,306 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
/* N51/N53 (iPhone6,x) Pin Configuration */
|
||||
|
||||
/*
|
||||
* N51 pinlist v0.21
|
||||
* <rdar://problem/11763484> N51 HW ERS | System | Pinlist
|
||||
*/
|
||||
|
||||
#define CFG_DISABLED_SS_X4 (CFG_DISABLED | SLOW_SLEW | DRIVE_X4 )
|
||||
#define CFG_DISABLED_SS_X1 (CFG_DISABLED | SLOW_SLEW | DRIVE_X1 )
|
||||
#define CFG_DISABLED_SS_X4_PD (CFG_DISABLED | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
|
||||
#define CFG_DISABLED_SS_X1_PD (CFG_DISABLED | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
|
||||
#define CFG_DISABLED_SS_X4_PU (CFG_DISABLED | SLOW_SLEW | DRIVE_X4 | PULL_UP )
|
||||
#define CFG_DISABLED_SS_X1_PU (CFG_DISABLED | SLOW_SLEW | DRIVE_X1 | PULL_UP )
|
||||
#define CFG_IN_SS_X1 (CFG_IN | SLOW_SLEW | DRIVE_X1 )
|
||||
#define CFG_IN_SS_X2 (CFG_IN | SLOW_SLEW | DRIVE_X2 )
|
||||
#define CFG_IN_SS_X4 (CFG_IN | SLOW_SLEW | DRIVE_X4 )
|
||||
#define CFG_IN_SS_X4_PD (CFG_IN | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
|
||||
#define CFG_IN_SS_X1_PD (CFG_IN | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
|
||||
#define CFG_IN_SS_X4_PU (CFG_IN | SLOW_SLEW | DRIVE_X4 | PULL_UP )
|
||||
#define CFG_IN_SS_X1_PU (CFG_IN | SLOW_SLEW | DRIVE_X1 | PULL_UP )
|
||||
#define CFG_OUT_0_SS_X4 (CFG_OUT_0 | SLOW_SLEW | DRIVE_X4 )
|
||||
#define CFG_OUT_0_SS_X4_PD (CFG_OUT_0 | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
|
||||
#define CFG_OUT_0_SS_X2_PD (CFG_OUT_0 | SLOW_SLEW | DRIVE_X2 | PULL_DOWN)
|
||||
#define CFG_OUT_0_SS_X1_PD (CFG_OUT_0 | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
|
||||
#define CFG_OUT_1_SS_X4 (CFG_OUT_1 | SLOW_SLEW | DRIVE_X4 )
|
||||
#define CFG_OUT_1_SS_X4_PU (CFG_OUT_1 | SLOW_SLEW | DRIVE_X4 | PULL_UP )
|
||||
#define CFG_OUT_1_SS_X1_PU (CFG_OUT_1 | SLOW_SLEW | DRIVE_X1 | PULL_UP )
|
||||
#define CFG_FUNC0_SS_X1 (CFG_FUNC0 | SLOW_SLEW | DRIVE_X1 )
|
||||
#define CFG_FUNC0_SS_X2 (CFG_FUNC0 | SLOW_SLEW | DRIVE_X2 )
|
||||
#define CFG_FUNC0_SS_X4 (CFG_FUNC0 | SLOW_SLEW | DRIVE_X4 )
|
||||
#define CFG_FUNC0_SS_X4_PD (CFG_FUNC0 | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
|
||||
#define CFG_FUNC0_SS_X2_PD (CFG_FUNC0 | SLOW_SLEW | DRIVE_X2 | PULL_DOWN)
|
||||
#define CFG_FUNC0_SS_X1_PD (CFG_FUNC0 | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
|
||||
#define CFG_FUNC0_SS_X4_PU (CFG_FUNC0 | SLOW_SLEW | DRIVE_X4 | PULL_UP )
|
||||
#define CFG_FUNC0_SS_X1_PU (CFG_FUNC0 | SLOW_SLEW | DRIVE_X1 | PULL_UP )
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
/* Port 0 */
|
||||
CFG_DISABLED_SS_X4_PD, // TST_CLKOUT -> AP_TO_PMU_TEST_CLKOUT
|
||||
CFG_FUNC0_SS_X4_PD, // WDOG -> WDOG_SOC
|
||||
CFG_IN_SS_X1, // GPIO0 -> BUTTON_TO_AP_MENU_KEY_BUFF_L (REQUEST_DFU2)
|
||||
CFG_IN_SS_X1, // GPIO1 -> BUTTON_TO_AP_HOLD_KEY_BUFF_L (REQUEST_DFU1)
|
||||
CFG_IN_SS_X1_PU, // GPIO2 -> BUTTON_TO_AP_VOL_UP_L
|
||||
CFG_IN_SS_X1_PU, // GPIO3 -> BUTTON_TO_AP_VOL_DOWN_L
|
||||
CFG_IN_SS_X1_PU, // GPIO4 -> SPKAMP_TO_AP_INT_L
|
||||
CFG_OUT_0_SS_X4_PD, // GPIO5 -> AP_TO_SPKAMP_BEE_GEES
|
||||
|
||||
/* Port 1 */
|
||||
CFG_OUT_0_SS_X4_PD, // GPIO6 -> AP_TO_SPKAMP_RESET_L
|
||||
CFG_OUT_0_SS_X4_PD, // GPIO7 -> AP_TO_BT_WAKE
|
||||
CFG_IN_SS_X4, // GPIO8 -> AP_TO_BB_RST_L
|
||||
CFG_DISABLED_SS_X4, // GPIO9 -> AP_TO_BB_JTAG_TDI
|
||||
CFG_DISABLED_SS_X4_PD, // GPIO10 -> AP_TO_BB_JTAG_TDO
|
||||
CFG_DISABLED_SS_X4_PD, // GPIO11 -> AP_TO_HEADSET_HS3_CTRL
|
||||
CFG_DISABLED_SS_X4_PD, // GPIO12 -> AP_TO_HEADSET_HS4_CTRL
|
||||
CFG_IN_SS_X1_PU, // GPIO13 -> PMU_TO_AP_IRQ_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_IN_SS_X1, // GPIO14 -> BUTTON_TO_AP_RINGER_A
|
||||
CFG_OUT_0_SS_X4, // GPIO15 -> AP_TO_BB_WAKE_MODEM
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO16 -> N/C -> BOARD_ID[3]
|
||||
CFG_IN_SS_X1, // GPIO17 -> AP_TO_OSCAR_DBGEN
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO18 -> BOARD_INFO -> BOOT_CONFIG[0]
|
||||
CFG_DISABLED_SS_X4_PD, // GPIO19 -> AP_TO_PMU_KEEPACT
|
||||
CFG_IN_SS_X1_PU, // GPIO20 -> TOUCH_TO_AP_INT_L
|
||||
CFG_OUT_0_SS_X4_PD, // GPIO21 -> AP_TO_TOUCH_GRAPE_RESET_L
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_FUNC0_SS_X4_PU, // UART1_TXD -> AP_TO_BT_UART1_TXD
|
||||
CFG_FUNC0_SS_X1_PU, // UART1_RXD -> BT_TO_AP_UART1_RXD
|
||||
CFG_OUT_1_SS_X4_PU, // UART1_RTSN -> AP_TO_BT_UART1_RTS_L
|
||||
CFG_FUNC0_SS_X1_PU, // UART1_CTSN -> BT_TO_AP_UART1_CTS_L
|
||||
CFG_FUNC0_SS_X4_PU, // UART2_TXD -> AP_TO_OSCAR_UART2_TXD
|
||||
CFG_FUNC0_SS_X1_PU, // UART2_RXD -> OSCAR_TO_AP_UART2_RXD
|
||||
CFG_OUT_1_SS_X4_PU, // UART2_RTSN -> AP_TO_OSCAR_RESET_L
|
||||
CFG_IN_SS_X1_PD, // UART2_CTSN -> OSCAR_TO_PMU_HOST_WAKE
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0_SS_X4, // UART3_TXD -> AP_TO_WLAN_UART3_TXD
|
||||
CFG_FUNC0_SS_X1, // UART3_RXD -> WLAN_TO_AP_UART3_RXD
|
||||
CFG_DISABLED_SS_X1_PD, // UART3_RTSN -> BB_TO_AP_PP_SYNC
|
||||
CFG_OUT_0_SS_X4_PD, // UART3_CTSN -> AP_TO_RCAM_VDDCORE_EN
|
||||
CFG_FUNC0_SS_X2, // UART5_RXD -> AP_BI_BATTERY_SWI
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 8 */
|
||||
CFG_OUT_0_SS_X4, // UART4_TXD -> AP_TO_BB_UART4_TXD
|
||||
CFG_FUNC0_SS_X1, // UART4_RXD -> BB_TO_AP_UART4_RXD
|
||||
CFG_OUT_0_SS_X4, // UART4_RTSN -> AP_TO_BB_UART4_RTS_L
|
||||
CFG_FUNC0_SS_X1, // UART4_CTSN -> BB_TO_AP_UART4_CTS_L
|
||||
CFG_FUNC0_SS_X4_PD, // SPI1_SCLK -> AP_TO_TOUCH_SPI1_CLK
|
||||
CFG_FUNC0_SS_X4_PD, // SPI1_MOSI -> AP_TO_TOUCH_SPI1_MOSI
|
||||
CFG_FUNC0_SS_X1_PD, // SPI1_MISO -> TOUCH_TO_AP_SPI1_MISO
|
||||
CFG_FUNC0_SS_X4_PU, // SPI1_SSIN -> AP_TO_TOUCH_SPI1_CS_L
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED_SS_X1_PU, // SPI0_SCLK -> N/C -> SPI0_SCLK/BOARD_ID[0]
|
||||
CFG_DISABLED_SS_X1_PU, // SPI0_MOSI -> N/C -> SPI0_MOSI/BOARD_ID[1]
|
||||
CFG_DISABLED_SS_X1_PU, // SPI0_MISO -> N/C -> SPI0_MISO/BOARD_ID[2]
|
||||
CFG_DISABLED_SS_X1_PD, // SPI0_SSIN -> N/C
|
||||
CFG_FUNC0_SS_X4, // SPI2_SCLK -> AP_TO_NAVAJO_SPI2_CLK
|
||||
CFG_FUNC0_SS_X2, // SPI2_MOSI -> AP_TO_NAVAJO_SPI2_MOSI
|
||||
CFG_FUNC0_SS_X2_PD, // SPI2_MISO -> NAVAJO_TO_AP_SPI2_MISO
|
||||
CFG_IN_SS_X1_PD, // SPI2_SSIN -> NAVAJO_TO_PMU_INT_H
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0_SS_X4, // I2C0_SDA -> AP_BI_I2C0_SDA
|
||||
CFG_FUNC0_SS_X4, // I2C0_SCL -> AP_TO_I2C0_SDA
|
||||
CFG_FUNC0_SS_X4, // I2C1_SDA -> AP_BI_I2C1_SDA
|
||||
CFG_FUNC0_SS_X4, // I2C1_SCL -> AP_TO_ISC1_SCL
|
||||
CFG_FUNC0_SS_X2, // ISP0_SDA -> AP_BI_RCAM_I2C_SDA
|
||||
CFG_FUNC0_SS_X2, // ISP0_SCL -> AP_TO_RCAM_I2C_SCL
|
||||
CFG_FUNC0_SS_X2, // ISP1_SDA -> AP_TO_FCAM_I2C_SCL
|
||||
CFG_FUNC0_SS_X2, // ISP1_SCL -> AP_TO_FCAM_I2C_SCL
|
||||
|
||||
/* Port 11 */
|
||||
CFG_OUT_0_SS_X2_PD, // SENSOR0_RST -> AP_TO_RCAM_SHUTDOWN
|
||||
CFG_DISABLED_SS_X4_PD, // SENSOR0_CLK -> 45_AP_TO_RCAM_CLK_R
|
||||
CFG_DISABLED_SS_X1_PD, // SENSOR0_XSHUTDOWN -> N/C
|
||||
CFG_DISABLED_SS_X1, // SENSOR0_ISTRB -> BB_TO_AP_IPC_GPIO
|
||||
CFG_OUT_0_SS_X2_PD, // SENSOR1_RST -> AP_TO_FCAM_SHUTDOWN
|
||||
CFG_DISABLED_SS_X4_PD, // SENSOR1_CLK -> 45_AP_TO_FCAM_CLK_R
|
||||
CFG_OUT_0_SS_X4_PD, // SENSOR1_XSHUTDOWN -> CAM_EXT_LDO_EN
|
||||
CFG_OUT_0_SS_X4_PD, // SENSOR1_ISTRB -> AP_TO_LEDDRV_EN
|
||||
|
||||
/* Port 12 */
|
||||
CFG_FUNC0_SS_X4_PD, // SPI3_MOSI -> AP_TO_CODEC_SPI3_MOSI
|
||||
CFG_FUNC0_SS_X1_PD, // SPI3_MISO -> CODEC_TO_AP_SPI3_MISO
|
||||
CFG_FUNC0_SS_X4_PD, // SPI3_SCLK -> AP_TO_CODEC_SPI3_CLK
|
||||
CFG_FUNC0_SS_X4_PD, // SPI3_SSIN -> AP_TO_CODEC_SPI3_CS_L
|
||||
CFG_DISABLED_SS_X1_PD, // I2C2_SDA -> N/C
|
||||
CFG_DISABLED_SS_X1_PD, // I2C2_SCL -> N/C
|
||||
CFG_OUT_0_SS_X4_PD, // GPIO22 -> AP_TO_LCM_RESET_L
|
||||
CFG_DISABLED_SS_X1_PD, // GPIO23 -> LCM_TO_AP_HIFA_BSYNC
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED_SS_X1_PD, // GPIO24 -> BB_TO_AP_RESET_DET_L
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO25 -> BOARD_INFO -> BOOT_CONFIG[1]
|
||||
CFG_DISABLED_SS_X1_PD, // GPIO26 -> FORCE_DFU
|
||||
CFG_DISABLED_SS_X1_PD, // GPIO27 -> DFU_STATUS
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO28 -> N/C -> BOOT_CONFIG[2]
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO29 -> N/C -> BOOT_CONFIG[3]
|
||||
CFG_IN_SS_X1_PU, // GPIO30 -> CODEC_TO_AP_INT_L
|
||||
CFG_IN_SS_X4, // GPIO31 -> AP_TO_RADIO_ON_L
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED_SS_X4, // GPIO32 -> AP_TO_BB_JTAG_TCK
|
||||
CFG_DISABLED_SS_X4, // GPIO33 -> AP_TO_BB_JTAG_TMS
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO34 -> BOARD_INFO -> BOARD_REV3
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO35 -> BOARD_INFO -> BOARD_REV2
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO36 -> BOARD_INFO -> BOARD_REV1
|
||||
CFG_DISABLED_SS_X1_PU, // GPIO37 -> BOARD_INFO -> BOARD_REV0
|
||||
CFG_DISABLED_SS_X1_PD, // GPIO38 -> N/C
|
||||
CFG_DISABLED_SS_X1_PD, // DISPLAY_SYNC -> N/C
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0_SS_X1_PU, // SOCHOT0 -> BB_TO_AP_SOCHOT0
|
||||
CFG_FUNC0_SS_X4, // SOCHOT1 -> AP_TO_PMU_SOCHOT1
|
||||
CFG_FUNC0_SS_X4_PU, // UART0_TXD -> AP_TO_TRISTAR_DEBUG_UART0_TXD
|
||||
CFG_FUNC0_SS_X1_PU, // UART0_RXD -> TRISTAR_TO_AP_DEBUG_UART0_RXD
|
||||
CFG_DISABLED_SS_X1_PD, // DWI_DI -> N/C
|
||||
CFG_FUNC0_SS_X1_PD, // DWI_D0 -> 45_AP_TO_PMU_DWI_DO
|
||||
CFG_FUNC0_SS_X1_PD, // DWI_CLK -> 45_AP_TO_PMU_DWI_CLK
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0_SS_X4_PD, // I2S0_LRCK -> AP_TO_CODEC_ASP_I2S0_LRCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S0_BCLK -> 45_AP_TO_CODEC_ASP_I2S0_BCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S0_DOUT -> AP_TO_CODEC_ASP_I2S0_DOUT
|
||||
CFG_FUNC0_SS_X1_PD, // I2S0_DIN -> CODEC_TO_AP_ASP_I2S0_DIN
|
||||
CFG_DISABLED_SS_X4, // I2S1_MCK -> AP_TO_BB_JTAG_TRST_L
|
||||
CFG_FUNC0_SS_X4_PD, // I2S1_LRCK -> AP_TO_BB_I2S1_LRCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S1_BCLK -> 45_AP_TO_BB_I2S1_BCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S1_DOUT -> AP_TO_BB_I2S1_DOUT
|
||||
|
||||
/* Port 17 */
|
||||
CFG_FUNC0_SS_X1_PD, // I2S1_DIN -> BB_TO_AP_I2S1_DIN
|
||||
CFG_FUNC0_SS_X4_PD, // I2S2_LRCK -> AP_TO_CODEC_XSP_I2S2_LRCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S2_BCLK -> 45_AP_TO_CODEC_XSP_I2S2_BCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S2_DOUT -> AP_TO_CODEC_XSP_I2S2_DOUT
|
||||
CFG_FUNC0_SS_X1_PD, // I2S2_DIN -> CODEC_TO_AP_XSP_I2S2_DIN
|
||||
CFG_IN_SS_X1_PU, // I2S3_MCK -> ALS_TO_AP_INT_L
|
||||
CFG_FUNC0_SS_X4_PD, // I2S3_LRCK -> AP_TO_BT_I2S3_LRCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S3_BCLK -> 45_AP_TO_BT_I2S3_BCLK
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0_SS_X4_PD, // I2S3_DOUT -> AP_TO_BT_I2S3_DOUT
|
||||
CFG_FUNC0_SS_X1_PD, // I2S3_DIN -> BT_TO_AP_I2S3_DIN
|
||||
CFG_IN_SS_X1_PD, // I2S4_MCK -> TRISTAR_TO_AP_INT
|
||||
CFG_FUNC0_SS_X4_PD, // I2S4_LRCK -> AP_TO_CODEC_VSP_I2S4_LRCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S4_BCLK -> 45_AP_TO_CODEC_VSP_I2S4_BCLK
|
||||
CFG_FUNC0_SS_X4_PD, // I2S4_DOUT -> AP_TO_CODEC_VSP_I2S4_DOUT
|
||||
CFG_FUNC0_SS_X1_PD, // I2S4_DIN -> CODEC_TO_AP_VSP_I2S4_DIN
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 20 */
|
||||
CFG_OUT_0_SS_X4_PD, // TMR32_PWM0 -> OSCAR_BI_AP_TIME_SYNC_HOST_INT
|
||||
CFG_DISABLED_SS_X4_PD, // TMR32_PWM1 -> AP_TO_PMU_VIBE_PWM_EN
|
||||
CFG_FUNC0_SS_X4, // TMR32_PWM2 -> 45_AP_TO_TOUCH_CLK32K_RESET_L
|
||||
CFG_OUT_0_SS_X4, // SIO_7816UART0_SDA -> AP_TO_BB_HSIC1_RDY
|
||||
CFG_DISABLED_SS_X1_PD, // SIO_7816UART0_SCL -> BB_TO_AP_HSIC1_RDY
|
||||
CFG_DISABLED_SS_X1_PD, // SIO_7816UART0_RST -> BB_TO_AP_HSIC1_REMOTE_WAKE
|
||||
CFG_OUT_0_SS_X4, // SIO_7816UART1_SDA -> AP_TO_WLAN_HSIC2_RDY
|
||||
CFG_IN_SS_X1_PD, // SIO_7816UART1_SCL -> WLAN_TO_AP_HSIC2_RDY
|
||||
|
||||
/* Port 21 */
|
||||
CFG_IN_SS_X1_PD, // SIO_7816UART0_RST -> WLAN_TO_AP_HSIC2_REMOTE_WAKE
|
||||
CFG_FUNC0_SS_X4_PU, // UART6_TXD -> AP_TO_TRISTAR_ACC_UART6_TXD
|
||||
CFG_FUNC0_SS_X1_PU, // UART6_RXD -> TRISTAR_TO_AP_ACC_UART6_RXD
|
||||
CFG_DISABLED_SS_X4_PD, // I2C3_SDA -> AP_BI_OSCAR_SWDIO_1V8
|
||||
CFG_DISABLED_SS_X4_PD, // I2C3_SCL -> AP_TO_OSCAR_SWDCLK_1V8
|
||||
CFG_DISABLED_SS_X1_PD, // EDP_HPD -> N/C
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED_SS_X1_PD, // EPD_HPD -> N/C
|
||||
CFG_FUNC0_SS_X4_PD, // I2S0_MCK -> 45_AP_TO_CODEC_I2S_MCLK_R
|
||||
CFG_FUNC0_SS_X4_PD, // I2S2_MCK -> 45_AP_TO_SPKAMP_I2S2_MCLK_R
|
||||
CFG_DISABLED_SS_X1_PD, // TESTMODE -> N/C
|
||||
CFG_DISABLED_SS_X1_PD, // FAST_SCAN_CLK -> N/C
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
return gpio_default_cfg;
|
||||
}
|
||||
@@ -0,0 +1,44 @@
|
||||
# Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2045=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_MED \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=0 \
|
||||
TARGET_VID0_CLK_CFG=0x86100000 \
|
||||
DISPLAY_IPHONE_TUNABLES=1 \
|
||||
TARGET_ENABLE_CM=1 \
|
||||
TARGET_DDR_798M=1 \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
TARGET_CHESTNUT_USE_LOW_RIPPLE_MODE=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
TARGET_DSIM_CONFIG=0x00400000 \
|
||||
TARGET_DSIM_DPHYCTL=0x30 \
|
||||
TARGET_DSIM_UP_CODE=0x1 \
|
||||
TARGET_DSIM_DOWN_CODE=0x1 \
|
||||
TARGET_DSIM_SUPPRESS=0x1 \
|
||||
WITH_HW_AGC_MIPI=1 \
|
||||
TARGET_ADBE0_VBLANK_POSITION=0xF0000 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_GPU=1 \
|
||||
WITH_CPU_APSC=1 \
|
||||
MULTITOUCH_DTPATH=\"arm-io/spi1/multi-touch\" \
|
||||
WIFI_DTPATH=\"arm-io/usb-complex/usb-ehci1/wlan\" \
|
||||
BT_DTPATH=\"arm-io/uart1/bluetooth\"
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
Reference in new issue
Block a user