first and last commit

target/iphone6/include/target/adbe_settings.h

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+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __TARGET_ADBE_SETTINGS_H
+#define __TARGET_ADBE_SETTINGS_H
+
+static struct adbe_v1_tuneable adbe_tuneables[] = {
+	{
+		.name = "default",
+		.adbe0_vblank_pos_vbi_pulse	= 0x0000,
+		.adbe0_vblank_clk_gate_wakeup 	= 0x0000,
+		.adbe0_vblank_clk_gate_idle 	= 0x0001,
+		.adbe0_vblank_blk_idle_dpb	= 0x0000,
+		.adbe0_vblank_blk_idle_aap	= 0x0000,
+		.adbe0_tunable_mode_ctrl	= (DBEMODECNTL_DYN_CLK_GATE_ENABLE | DBEMODECNTL_AFC_TEARDOWN_ENABLE | DBEMODECNTL_PMGR_CLK_GATE_ENABL| DBEMODECNTL_BLK_CLK_GATE_ENABLE),
+		.adbe0_aap_support		= 1,
+	},
+};
+
+#endif

target/iphone6/include/target/aspnandconfig.h

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+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __TARGET_ASPNANDCONFIG_H
+#define __TARGET_ASPNANDCONFIG_H
+
+//MLC devices
+#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
+#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
+#define ASPNAND_ERASE_DIES_IN_PARALLEL 4
+#define ASPNAND_READ_DIES_IN_PARALLEL 4
+#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
+#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
+#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
+#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
+
+//TLC devices
+#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
+#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
+#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
+#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
+#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
+#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
+#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
+#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
+
+// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
+#define ASPNAND_INDIRECTION_MEMORY (4*1024*1024)
+#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
+
+
+#endif

target/iphone6/include/target/gpiodef.h

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+/*
+ * Copyright (C) 2012-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __TARGET_GPIODEF_H
+#define __TARGET_GPIODEF_H
+
+/* iPhone6,x specific gpio -> pin mappings */
+
+#include <platform/gpio.h>
+
+/* define target-specific gpios in a generic fashion here. */
+#define GPIO_SOCHOT0_IN		GPIO(15, 0)		// BB_TO_AP_SOCHOT0
+
+#define GPIO_LCD_RST            GPIO(12, 6)		// AP_TO_LCM_RESET_L
+#define GPIO_LCD_RST_POLARITY   (0)
+
+#define GPIO_X162_INT		GPIO( 9, 7)		// NAVAJO_TO_PMU_INT_H
+
+#define GPIO_RINGER_AB		GPIO( 2, 0)
+
+#define GPIO_WDOG		GPIO( 0, 1)		// WDOG
+
+/* Board Revision */
+#define GPIO_BOARD_REV0		GPIO(14, 5)
+#define GPIO_BOARD_REV1		GPIO(14, 4)
+#define GPIO_BOARD_REV2		GPIO(14, 3)
+#define GPIO_BOARD_REV3		GPIO(14, 2)
+
+/* which IICs to initialize */
+#define IICS_MASK		(3)
+
+#define TRISTAR_IIC_BUS		(0)
+
+#define DISPLAY_PMU_IIC_BUS	(0)
+
+/* D2094 watchdog tickle, 'KEEPACT' */
+#define GPIO_WDOG_TICKLE	GPIO(2, 5)
+
+#endif /* ! __TARGET_GPIODEF_H */

target/iphone6/include/target/powerconfig.h

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+#ifndef __TARGET_POWERCONFIG_H
+#define __TARGET_POWERCONFIG_H
+
+/* configuration per target */
+
+#define PMU_IIC_BUS		0
+
+/* this configuration is very PMU specific and must be included exactly once in power.c */
+#ifdef POWERCONFIG_PMU_SETUP
+
+static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
+{
+};
+
+static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
+{
+	{ PMU_IIC_BUS, kD2045_ACTIVE3, 		0xAE },		// Current OTP enables LDO{1,2,3,4,5,7}, disable LDO4.
+	{ PMU_IIC_BUS, kD2045_ACTIVE6, 		0x37 },		// enable BUCK3_SW1, BUCK3_SW2, BUCK3_SW3, BUCK4_SW1, BUCK4_SW2
+	{ PMU_IIC_BUS, kD2045_ACTIVE3, 		0xBE },		// enable LDO4 along with LDO{1,2,3,5,7}
+
+	{ PMU_IIC_BUS, kD2045_HIBERNATE1, 0x18 },
+	{ PMU_IIC_BUS, kD2045_HIBERNATE3, 0x18 },
+	{ PMU_IIC_BUS, kD2045_HIBERNATE6, 0x24 },
+};
+
+static const struct pmu_setup_struct pmu_warm_init[] =
+{
+};
+
+// NOTE:  <rdar://problem/13296265> N51 PMU continuously reboots when VBatt is near UVLO
+//	  ** GPIO4,GPIO8, and GPIO12 are enabled using the gpio-activate-defaults property in the device tree.
+
+static const struct pmu_setup_struct pmu_cold_init[] =
+{
+	{ PMU_IIC_BUS, kD2045_GPIO2,		0x7A }, 	// BB_TO_PMU_HOST_WAKE		In, L High, Wake, No PU
+	{ PMU_IIC_BUS, kD2045_GPIO3,		0x09 }, 	// PMU_TO_BB_RST_R_L		Out 0, Push-Pull, VBUCK3
+	{ PMU_IIC_BUS, kD2045_GPIO4,		0x78 }, 	// TRISTAR_TO_AP_INT		In, L High, Wake**, No PU
+	{ PMU_IIC_BUS, kD2045_GPIO6,		0xDA }, 	// AP_BI_BATTERY_SWI		In, F Edge, Out Hib, Wake, PD, No PU
+	{ PMU_IIC_BUS, kD2045_GPIO7,		0xBB }, 	// WLAN_TO_PMU_HOST_WAKE	In, R Edge, Wake, PD, No PU
+	{ PMU_IIC_BUS, kD2045_GPIO8,		0xE8 }, 	// CODEC_TO_PMU_MIKEY_INT_L	In, Any Edge, Wake**, PU, VBUCK3
+	{ PMU_IIC_BUS, kD2045_GPIO9,		0x09 }, 	// PMU_TO_BT_REG_ON_R		Out 0, Push-Pull, VBUCK3
+	{ PMU_IIC_BUS, kD2045_GPIO10,		0xAA }, 	// BT_TO_PMU_HOST_WAKE		In, R Edge, Wake, PU, VBUCK3
+	{ PMU_IIC_BUS, kD2045_GPIO11,		0x09 }, 	// PMU_TO_WLAN_REG_ON_R		Out 0, Push-Pull, VBUCK3
+	{ PMU_IIC_BUS, kD2045_GPIO12,		0xB9 }, 	// NAVAJO_TO_PMU_INT_L		In, R Edge, Wake**, No PU
+	{ PMU_IIC_BUS, kD2045_GPIO13,		0x7B }, 	// OSCAR_TO_PMU_HOST_WAKE	In, L High, Wake, PD, No PU
+	{ PMU_IIC_BUS, kD2045_GPIO14,		0x49 }, 	// PMU_TO_OSCAR_CLK_32K		Out 32K, Push-Pull, VBUCK3
+	{ PMU_IIC_BUS, kD2045_GPIO15,		0x01 }, 	// PMU_TO_BB_VBUS_DET		Out 0, Push-Pull, VCC_MAIN
+	{ PMU_IIC_BUS, kD2045_GPIO16,		0x38 }, 	// <rdar://problem/14062728> N5x PMU | Set GPIO16 to 0x38 to better support OTP-AQ on DVT boards
+	{ PMU_IIC_BUS, kD2045_OUT_32K, 		0x49 },		// OUT_32K (WLAN_CLK32K)	Out 32K, Push-Pull, VBUCK3
+
+	{ PMU_IIC_BUS, kD2045_GPIO_DEB2,	0x12 },
+	{ PMU_IIC_BUS, kD2045_GPIO_DEB5,	0x12 },
+	{ PMU_IIC_BUS, kD2045_GPIO_DEB6,	0x12 },
+
+	{ PMU_IIC_BUS, kD2045_BUCK_DWI_CTRL0, 	0x03 },		// enable DWI for BUCK0, BUCK1
+	{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2,	0x11 },		// enable HIB_32kHz (for WIFI/BT) and DWI
+
+	{ PMU_IIC_BUS, kD2045_ACT_TO_HIB_DLY,	0x03 },		// set ACT_TO_HIB_DLY to 3 (6ms)
+
+	{ PMU_IIC_BUS, 0x7000,			0x1D },	// Enable Test Mode
+	{ PMU_IIC_BUS, kD2045_ADC_FSM_TRIM2,	0x00 },	// <rdar://problem/14276806> Enable offset correction on Amber IBUS ADC
+	{ PMU_IIC_BUS, 0x7000,			0x00 },	// Disable Test Mode
+};
+
+static const struct core_rails_struct soc_rails[] =
+{
+	{ PMU_IIC_BUS, 0, kD2045_BUCK2_VSEL }
+};
+
+static const struct core_rails_struct cpu_rails[] =
+{
+	{ PMU_IIC_BUS, 0, kD2045_BUCK0_VSEL }
+};
+
+static const struct core_rails_struct ram_rails[] =
+{
+	{ PMU_IIC_BUS, 0, kD2045_BUCK5_VSEL }
+};
+
+#endif /* POWERCONFIG_PMU_SETUP */
+
+#define NO_BATTERY_VOLTAGE		2700
+#define MIN_BOOT_BATTERY_VOLTAGE	3600
+#define TARGET_BOOT_BATTERY_VOLTAGE	3700
+#define TARGET_BOOT_BATTERY_CAPACITY	50
+#define PRECHARGE_BACKLIGHT_LEVEL	824
+#define ALWAYS_BOOT_BATTERY_VOLTAGE	(TARGET_BOOT_BATTERY_VOLTAGE + 100)
+
+#define ACC_PWR_LDO			(6)
+
+#endif

target/iphone6/include/target/uartconfig.h

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+/*
+ * Copyright (C) 2012, 2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __TARGET_UARTCONFIG_H
+#define __TARGET_UARTCONFIG_H
+
+/* define one debug serial ports */
+#define DEBUG_SERIAL_PORT		(0)
+
+#define HDQGAUGE_SERIAL_PORT		(5)
+
+#if SUPPORT_FPGA
+#define UART_OVERSAMPLE_OVERRIDE        (11)
+#endif
+
+#endif