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Chris Nutter committed 2023-07-08 13:03:17 -07:00
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target/ipod6/include/target/adbe_settings.h
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/*
* Copyright (C) 2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Computer, Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_ADBE_SETTINGS_H
#define __TARGET_ADBE_SETTINGS_H
static struct adbe_v3_tuneable adbe_tuneables[] = {
{
.name = "default",
.adbe0_vblank_clk_gate_wakeup = 0x0000,
.adbe0_vblank_clk_gate_idle = 0x0001,
.adbe0_tunable_nrt_ctl = (ADBE_NRT_CTL_ADISP_CLK_GATE_ENABLE | ADBE_NRT_CTL_ADBE_CLK_GATE_ENABLE | ADBE_NRT_CTL_BLK_CLK_GATE_ENABLE),
.adbe0_aap_support = 0,
},
};
#endif
target/ipod6/include/target/amcconfig.h
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/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#if SUPPORT_FPGA
static const struct amc_param amc_params = {
.flags = FLAG_AMC_PARAM_BUSTAT23 | FLAG_AMC_PARAM_ENABLE_AIU | FLAG_AMC_PARAM_LEGACY | FLAG_AMC_PARAM_ZQCL,
.freqsel = 3,
.tREFi = 0x28,
.longsrcnt = 0x2008,
.srextrarefcnt = (0x2 << 16),
.rdlat = 4,
.wrlat = 2,
.phyrdlat = 6,
.phywrlat = 1,
.pdn = 0x22000103,
.read = 0x00000101,
.bustat = 0x00222209,
.bustat2 = 0x00222209,
.derate = 0x08210212,
.mcphyupdate = 0x05030000,
.mcphyupdate1 = 0x00000004,
.autoref_params = 0x1a1a1a1a,
.chnldec = 0x00050001,
.qbrparam = 0x00510000,
.odts = 0x190,
.aref_freq0 = 0x00000110,
.pwrmngtparam_small = 0x00011000,
.pwrmngtparam_guided = 0x01803000,
.schen_default = 0x00000110,
.pwrmngten_default = 0x00100100,
.addrcfg = 0x00020201,
.bankhash0 = 0x00006db6,
.bankhash1 = 0x00005b6d,
.bankhash2 = 0x000036db,
.bootclkdivsr = 1,
.mr1 = 0xc4,
.mr3 = 0x2,
.mr2 = 0x6,
.mr63 = 0xfc,
.freq = {
{ // 533MHz
.cas = 0x00000202,
.pch = 0x00010202,
.act = 0x04010202,
.autoref = 0x02030000,
.selfref = 0x00003040,
.modereg = 0x20020722,
.arefparam = 0x0c022131,
.mifcassch = 0x00000110,
.trefbwbasecyc = 0x0000002d,
},
{ // -- unused
.cas = 0x00000002,
.pch = 0x00000002,
.act = 0x04010202,
.autoref = 0x02030000,
.selfref = 0x00003000,
.modereg = 0x00020000,
.arefparam = 0x00000101,
.mifcassch = 0x00000000,
.trefbwbasecyc = 0x00000017,
},
{ // -- unused
.cas = 0x00000002,
.pch = 0x00000002,
.act = 0x04010202,
.autoref = 0x02030000,
.selfref = 0x00003000,
.modereg = 0x00020000,
.arefparam = 0x00000101,
.mifcassch = 0x00000000,
.trefbwbasecyc = 0x0000000c,
},
{ // 24MHz
.cas = 0x00000002,
.pch = 0x00000002,
.act = 0x04010202,
.autoref = 0x02030000,
.selfref = 0x00003000,
.modereg = 0x00020000,
.arefparam = 0x00000101,
.mifcassch = 0x00000010,
}
}
};
static const struct amc_tunable amc_tunables[] = {
{ &rAMC_AIUPRT_CFG, 0x00070000},
{ &rAMC_AIUPRT_RD_GEN, 0x80000018},
{ &rAMC_AIU_CHNLTM, 0x40003101},
{ &rAMC_AIU_RDBRSTLEN, 0x01010101},
{ &rAMC_AIU_RDMAXCRD, 0x3012097f},
{ &rAMC_AIU_RDREFL, 0x280f087f},
{ &rAMC_AIU_WRBRSTLEN, 0x01010101},
{ &rAMC_AIU_WRMAXCRD, 0x3012097f},
{ &rAMC_AIU_WRREFL, 0x280f087f},
{ &rAMC_AIU_CPUSPCREQ, 0x00000013},
{ &rAMC_AIU_GFXSPCREQ, 0x00000019},
{ &rAMC_AIU_NRTSPCREQ, 0x00000019},
{ &rAMC_AIU_RTSPCREQ, 0x00000013},
{ &rAMC_AIU_WPQSCH, 0x08000800},
{ &rAMC_AIU_THOTLEN, 0x00000030},
{ &rAMC_AIU_THOTLCPUPARAM, 0x00000084},
{ &rAMC_AIU_THOTLRTPARAM, 0x00000084},
{ &rAMC_AIU_THOTLNRTPARAM, 0x00000080},
{ &rAMC_AIU_THOTLGFXPARAM, 0x00000080},
{ &rAMC_AIU_PUSHEN, 0x00001100},
{ &rAMC_AIU_THOTLCPUPARAM2, 0x00c00040},
{ &rAMC_AIU_THOTLRTPARAM2, 0x00c00040},
{ &rAMC_AIU_THOTLNRTPARAM2, 0x00000040},
{ &rAMC_AIU_THOTLGFXPARAM2, 0x00000040},
{ &rAMC_AIU_LLTSCHCTL, 0x00000001},
{ &rAMC_OPIDLETMR, 0x00200000},
{ &rAMC_OPTMRADJPARAM, 0x20400064},
{ &rAMC_MIFACTSCH, 0x00000001},
{ &rAMC_PSQRQCTL0, 0x01010000},
{ &rAMC_PSQRQCTL1, 0x0000132a},
{ &rAMC_PSQRQTIMER0, 0x00000018},
{ &rAMC_PSQRQTIMER1, 0x00000006},
{ &rAMC_PSQRQTIMER2, 0x00000020},
{ &rAMC_PSQRQBRST, 0x040c040c},
{ &rAMC_PSQRQSCHCRD, 0x002028f5},
{ &rAMC_PSQWQCTL1, 0x00000180},
{ &rAMC_PSQWQBRST, 0x02020208},
{ &rAMC_PSQWQSCHCRD, 0x000405f5},
{ &rAMC_MCUQOS, 0x00010f04},
{ &rAMC_MCUQOSLLT, 0x00010108},
{0, 0},
};
#else
#error "Not supported for this target"
#endif
target/ipod6/include/target/ampconfig.h
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/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
/*
* The amc_param struct is defined in drivers/apple/amp/amp.h, and this
* file should only by included from that amp.c.
*/
#if SUPPORT_FPGA
static struct amp_params amc_phy_params = {
.freq = {
{
.caoutdllscl = 0x00000008,
.dqsindllscl = 0x00000008,
.rdcapcfg = 0x21020304
},
{
.caoutdllscl = 0x00000010,
.dqsindllscl = 0x00000010,
.rdcapcfg = 0x31020307
},
{
.caoutdllscl = 0x00000020,
.dqsindllscl = 0x00000020,
.rdcapcfg = 0x51020305
},
{
.caoutdllscl = 0x0000003f,
.dqsindllscl = 0x0000003f,
.rdcapcfg = 0x61020304
}
},
.drive_strength = 0x12121212,
};
#else
#error "Not supported for this target"
#endif
target/ipod6/include/target/aspnandconfig.h
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/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Computer, Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_ASPNANDCONFIG_H
#define __TARGET_ASPNANDCONFIG_H
//MLC devices
#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 1
#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 1
#define ASPNAND_ERASE_DIES_IN_PARALLEL 1
#define ASPNAND_READ_DIES_IN_PARALLEL 1
#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 1
#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 1
#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 1
#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 1
//TLC devices
#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 1
#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 1
#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 1
#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 1
#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 1
#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 1
#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 1
#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 1
// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
#define ASPNAND_INDIRECTION_MEMORY (2*1024*1024)
#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
#endif
target/ipod6/include/target/cjay.h
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/*
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef _Cjay_h_
#define _Cjay_h_
// Seajay calibration
typedef struct __attribute__((packed)) {
uint8_t Version;
uint16_t Magic;
uint8_t IsNotCalibrated;
uint32_t NumOfItems;
uint32_t SizeOfItems;
} SeajayCalHdr;
typedef struct __attribute__((packed)) {
uint32_t Status;
uint32_t Offset; // Q15.16 fixed point, 4 bytes
uint32_t pad1;
uint32_t Gain; // Q15.16 fixed point, 4 bytes
uint32_t pad2;
} SeajayCalItem;
typedef struct __attribute__((packed)) {
SeajayCalHdr Hdr;
SeajayCalItem Item;
} SeajayCal;
enum {
kCalStatus_NoCal = 0x0, /* This means that we haven't done any calibration */
kCalStatus_Offset = 0x1, /* Offset has been calibrated */
kCalStatus_Gain = 0x2, /* Gain has been calibrated */
kCalStatus_All = 0x3, /* Both gain & offset have been calibrated */
};
#define SEAJAY_CAL_VERSION 0x2
#define SEAJAY_CAL_MAGIC 0xabcd
#endif /* _Cjay_h_ */
target/ipod6/include/target/display_gamma_tables.h
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/*
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Computer, Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_DISPLAY_GAMMA_TABLES_H
#define __TARGET_DISPLAY_GAMMA_TABLES_H
/* display gamma tables */
static const uint32_t target_gp_csc_matrix[3][3] = {
{ 0x0c66, 0x0399, 0x0000 },
{ 0x002f, 0x0fd0, 0x0000 },
{ 0x0046, 0x0144, 0x0e74 },
};
/*
* The table is auto generated by a tool in iOS.
* Unfortunately it includes one more entry than needed for degamma LUT entry.
* Hence the code should accomodate it
*/
#define ADP_CM_DEGAMMA_PAIRED_LUT_COUNT 65
#define ADP_CM_DEGAMMA_PAIRED_LUT_SIZE (ADP_CM_DEGAMMA_PAIRED_LUT_COUNT - 1)
static const uint32_t target_gp_degamma_tables[ADP_CM_DEGAMMA_PAIRED_LUT_COUNT] = {
0x00000000, // LUT[0000] 0x0000 (0.00000000) -> 0x0000 (0.00000000) | LUT[0001] 0x0008 (0.00782014) -> 0x0000 (0.00002318)
0x00020001, // LUT[0002] 0x0010 (0.01564027) -> 0x0001 (0.00010650) | LUT[0003] 0x0018 (0.02346041) -> 0x0002 (0.00025986)
0x00070004, // LUT[0004] 0x0020 (0.03128055) -> 0x0004 (0.00048933) | LUT[0005] 0x0028 (0.03910068) -> 0x0007 (0.00079948)
0x000e000a, // LUT[0006] 0x0030 (0.04692082) -> 0x000a (0.00119400) | LUT[0007] 0x0038 (0.05474096) -> 0x000e (0.00167605)
0x00180012, // LUT[0008] 0x0040 (0.06256109) -> 0x0012 (0.00224838) | LUT[0009] 0x0048 (0.07038123) -> 0x0018 (0.00291343)
0x0025001e, // LUT[0010] 0x0050 (0.07820137) -> 0x001e (0.00367343) | LUT[0011] 0x0058 (0.08602151) -> 0x0025 (0.00453039)
0x0036002d, // LUT[0012] 0x0060 (0.09384164) -> 0x002d (0.00548618) | LUT[0013] 0x0068 (0.10166178) -> 0x0036 (0.00654255)
0x0049003f, // LUT[0014] 0x0070 (0.10948192) -> 0x003f (0.00770111) | LUT[0015] 0x0078 (0.11730205) -> 0x0049 (0.00896339)
0x00610055, // LUT[0016] 0x0080 (0.12512219) -> 0x0055 (0.01033084) | LUT[0017] 0x0088 (0.13294233) -> 0x0061 (0.01180482)
0x007b006e, // LUT[0018] 0x0090 (0.14076246) -> 0x006e (0.01338662) | LUT[0019] 0x0098 (0.14858260) -> 0x007b (0.01507751)
0x009a008a, // LUT[0020] 0x00a0 (0.15640274) -> 0x008a (0.01687864) | LUT[0021] 0x00a8 (0.16422287) -> 0x009a (0.01879118)
0x00bc00ab, // LUT[0022] 0x00b0 (0.17204301) -> 0x00ab (0.02081620) | LUT[0023] 0x00b8 (0.17986315) -> 0x00bc (0.02295476)
0x00e200ce, // LUT[0024] 0x00c0 (0.18768328) -> 0x00ce (0.02520788) | LUT[0025] 0x00c8 (0.19550342) -> 0x00e2 (0.02757653)
0x010c00f6, // LUT[0026] 0x00d0 (0.20332356) -> 0x00f6 (0.03006166) | LUT[0027] 0x00d8 (0.21114370) -> 0x010c (0.03266419)
0x01390122, // LUT[0028] 0x00e0 (0.21896383) -> 0x0122 (0.03538500) | LUT[0029] 0x00e8 (0.22678397) -> 0x0139 (0.03822497)
0x016b0151, // LUT[0030] 0x00f0 (0.23460411) -> 0x0151 (0.04118493) | LUT[0031] 0x00f8 (0.24242424) -> 0x016b (0.04426570)
0x01a00185, // LUT[0032] 0x0100 (0.25024438) -> 0x0185 (0.04746807) | LUT[0033] 0x0108 (0.25806452) -> 0x01a0 (0.05079281)
0x01da01bc, // LUT[0034] 0x0110 (0.26588465) -> 0x01bc (0.05424069) | LUT[0035] 0x0118 (0.27370479) -> 0x01da (0.05781244)
0x021701f8, // LUT[0036] 0x0120 (0.28152493) -> 0x01f8 (0.06150878) | LUT[0037] 0x0128 (0.28934506) -> 0x0217 (0.06533041)
0x02590237, // LUT[0038] 0x0130 (0.29716520) -> 0x0237 (0.06927802) | LUT[0039] 0x0138 (0.30498534) -> 0x0259 (0.07335230)
0x029f027b, // LUT[0040] 0x0140 (0.31280547) -> 0x027b (0.07755388) | LUT[0041] 0x0148 (0.32062561) -> 0x029f (0.08188344)
0x02e902c3, // LUT[0042] 0x0150 (0.32844575) -> 0x02c3 (0.08634158) | LUT[0043] 0x0158 (0.33626588) -> 0x02e9 (0.09092895)
0x0337030f, // LUT[0044] 0x0160 (0.34408602) -> 0x030f (0.09564614) | LUT[0045] 0x0168 (0.35190616) -> 0x0337 (0.10049376)
0x038a0360, // LUT[0046] 0x0170 (0.35972630) -> 0x0360 (0.10547239) | LUT[0047] 0x0178 (0.36754643) -> 0x038a (0.11058262)
0x03e103b5, // LUT[0048] 0x0180 (0.37536657) -> 0x03b5 (0.11582500) | LUT[0049] 0x0188 (0.38318671) -> 0x03e1 (0.12120009)
0x043c040e, // LUT[0050] 0x0190 (0.39100684) -> 0x040e (0.12670845) | LUT[0051] 0x0198 (0.39882698) -> 0x043c (0.13235062)
0x049c046b, // LUT[0052] 0x01a0 (0.40664712) -> 0x046b (0.13812711) | LUT[0053] 0x01a8 (0.41446725) -> 0x049c (0.14403847)
0x050004cd, // LUT[0054] 0x01b0 (0.42228739) -> 0x04cd (0.15008519) | LUT[0055] 0x01b8 (0.43010753) -> 0x0500 (0.15626780)
0x05690534, // LUT[0056] 0x01c0 (0.43792766) -> 0x0534 (0.16258678) | LUT[0057] 0x01c8 (0.44574780) -> 0x0569 (0.16904264)
0x05d6059f, // LUT[0058] 0x01d0 (0.45356794) -> 0x059f (0.17563585) | LUT[0059] 0x01d8 (0.46138807) -> 0x05d6 (0.18236689)
0x0647060e, // LUT[0060] 0x01e0 (0.46920821) -> 0x060e (0.18923625) | LUT[0061] 0x01e8 (0.47702835) -> 0x0647 (0.19624437)
0x06be0682, // LUT[0062] 0x01f0 (0.48484848) -> 0x0682 (0.20339173) | LUT[0063] 0x01f8 (0.49266862) -> 0x06be (0.21067878)
0x073806fb, // LUT[0064] 0x0200 (0.50048876) -> 0x06fb (0.21810595) | LUT[0065] 0x0208 (0.50830890) -> 0x0738 (0.22567371)
0x07b80778, // LUT[0066] 0x0210 (0.51612903) -> 0x0778 (0.23338247) | LUT[0067] 0x0218 (0.52394917) -> 0x07b8 (0.24123268)
0x083c07f9, // LUT[0068] 0x0220 (0.53176931) -> 0x07f9 (0.24922476) | LUT[0069] 0x0228 (0.53958944) -> 0x083c (0.25735913)
0x08c50880, // LUT[0070] 0x0230 (0.54740958) -> 0x0880 (0.26563620) | LUT[0071] 0x0238 (0.55522972) -> 0x08c5 (0.27405640)
0x0952090b, // LUT[0072] 0x0240 (0.56304985) -> 0x090b (0.28262012) | LUT[0073] 0x0248 (0.57086999) -> 0x0952 (0.29132776)
0x09e4099b, // LUT[0074] 0x0250 (0.57869013) -> 0x099b (0.30017973) | LUT[0075] 0x0258 (0.58651026) -> 0x09e4 (0.30917641)
0x0a7b0a2f, // LUT[0076] 0x0260 (0.59433040) -> 0x0a2f (0.31831821) | LUT[0077] 0x0268 (0.60215054) -> 0x0a7b (0.32760549)
0x0b170ac9, // LUT[0078] 0x0270 (0.60997067) -> 0x0ac9 (0.33703865) | LUT[0079] 0x0278 (0.61779081) -> 0x0b17 (0.34661805)
0x0bb80b67, // LUT[0080] 0x0280 (0.62561095) -> 0x0b67 (0.35634408) | LUT[0081] 0x0288 (0.63343109) -> 0x0bb8 (0.36621710)
0x0c5d0c0a, // LUT[0082] 0x0290 (0.64125122) -> 0x0c0a (0.37623748) | LUT[0083] 0x0298 (0.64907136) -> 0x0c5d (0.38640557)
0x0d070cb2, // LUT[0084] 0x02a0 (0.65689150) -> 0x0cb2 (0.39672175) | LUT[0085] 0x02a8 (0.66471163) -> 0x0d07 (0.40718635)
0x0db60d5e, // LUT[0086] 0x02b0 (0.67253177) -> 0x0d5e (0.41779974) | LUT[0087] 0x02b8 (0.68035191) -> 0x0db6 (0.42856227)
0x0e6a0e10, // LUT[0088] 0x02c0 (0.68817204) -> 0x0e10 (0.43947427) | LUT[0089] 0x02c8 (0.69599218) -> 0x0e6a (0.45053610)
0x0f230ec6, // LUT[0090] 0x02d0 (0.70381232) -> 0x0ec6 (0.46174808) | LUT[0091] 0x02d8 (0.71163245) -> 0x0f23 (0.47311056)
0x0fe10f82, // LUT[0092] 0x02e0 (0.71945259) -> 0x0f82 (0.48462387) | LUT[0093] 0x02e8 (0.72727273) -> 0x0fe1 (0.49628833)
0x10a41042, // LUT[0094] 0x02f0 (0.73509286) -> 0x1042 (0.50810428) | LUT[0095] 0x02f8 (0.74291300) -> 0x10a4 (0.52007204)
0x116c1107, // LUT[0096] 0x0300 (0.75073314) -> 0x1107 (0.53219194) | LUT[0097] 0x0308 (0.75855327) -> 0x116c (0.54446428)
0x123911d1, // LUT[0098] 0x0310 (0.76637341) -> 0x11d1 (0.55688939) | LUT[0099] 0x0318 (0.77419355) -> 0x1239 (0.56946758)
0x130a12a1, // LUT[0100] 0x0320 (0.78201369) -> 0x12a1 (0.58219916) | LUT[0101] 0x0328 (0.78983382) -> 0x130a (0.59508445)
0x13e11375, // LUT[0102] 0x0330 (0.79765396) -> 0x1375 (0.60812374) | LUT[0103] 0x0338 (0.80547410) -> 0x13e1 (0.62131734)
0x14bd144f, // LUT[0104] 0x0340 (0.81329423) -> 0x144f (0.63466555) | LUT[0105] 0x0348 (0.82111437) -> 0x14bd (0.64816867)
0x159e152d, // LUT[0106] 0x0350 (0.82893451) -> 0x152d (0.66182700) | LUT[0107] 0x0358 (0.83675464) -> 0x159e (0.67564083)
0x16841611, // LUT[0108] 0x0360 (0.84457478) -> 0x1611 (0.68961046) | LUT[0109] 0x0368 (0.85239492) -> 0x1684 (0.70373617)
0x177016f9, // LUT[0110] 0x0370 (0.86021505) -> 0x16f9 (0.71801825) | LUT[0111] 0x0378 (0.86803519) -> 0x1770 (0.73245699)
0x186017e7, // LUT[0112] 0x0380 (0.87585533) -> 0x17e7 (0.74705268) | LUT[0113] 0x0388 (0.88367546) -> 0x1860 (0.76180559)
0x195618da, // LUT[0114] 0x0390 (0.89149560) -> 0x18da (0.77671600) | LUT[0115] 0x0398 (0.89931574) -> 0x1956 (0.79178419)
0x1a5019d2, // LUT[0116] 0x03a0 (0.90713587) -> 0x19d2 (0.80701044) | LUT[0117] 0x03a8 (0.91495601) -> 0x1a50 (0.82239502)
0x1b501ad0, // LUT[0118] 0x03b0 (0.92277615) -> 0x1ad0 (0.83793821) | LUT[0119] 0x03b8 (0.93059629) -> 0x1b50 (0.85364027)
0x1c551bd2, // LUT[0120] 0x03c0 (0.93841642) -> 0x1bd2 (0.86950147) | LUT[0121] 0x03c8 (0.94623656) -> 0x1c55 (0.88552207)
0x1d601cda, // LUT[0122] 0x03d0 (0.95405670) -> 0x1cda (0.90170236) | LUT[0123] 0x03d8 (0.96187683) -> 0x1d60 (0.91804257)
0x1e6f1de7, // LUT[0124] 0x03e0 (0.96969697) -> 0x1de7 (0.93454299) | LUT[0125] 0x03e8 (0.97751711) -> 0x1e6f (0.95120386)
0x1f841ef9, // LUT[0126] 0x03f0 (0.98533724) -> 0x1ef9 (0.96802545) | LUT[0127] 0x03f8 (0.99315738) -> 0x1f84 (0.98500801)
0x29782011, // LUT[0128] 0x0400 (1.00097752) -> 0x2011 (1.00215180) | LUT[0129] 0x047f (1.12512219) -> 0x2978 (1.29610241)
};
#define ADP_CM_ENGAMMA_PAIRED_LUT_COUNT 513
#define ADP_CM_ENGAMMA_PAIRED_LUT_SIZE (ADP_CM_ENGAMMA_PAIRED_LUT_COUNT - 1)
static const uint32_t target_gp_engamma_tables[ADP_CM_ENGAMMA_PAIRED_LUT_COUNT] = {
0x002c0000, // LUT[0000] 0x0000 (0.00000000) -> 0x0000 (0.00000000) | LUT[0001] 0x0008 (0.00097668) -> 0x002c (0.04282584)
0x0048003c, // LUT[0002] 0x0010 (0.00195336) -> 0x003c (0.05868644) | LUT[0003] 0x0018 (0.00293005) -> 0x0048 (0.07056336)
0x005b0052, // LUT[0004] 0x0020 (0.00390673) -> 0x0052 (0.08042102) | LUT[0005] 0x0028 (0.00488341) -> 0x005b (0.08900606)
0x006a0063, // LUT[0006] 0x0030 (0.00586009) -> 0x0063 (0.09669657) | LUT[0007] 0x0038 (0.00683677) -> 0x006a (0.10371496)
0x00770071, // LUT[0008] 0x0040 (0.00781345) -> 0x0071 (0.11020502) | LUT[0009] 0x0048 (0.00879014) -> 0x0077 (0.11626595)
0x0082007d, // LUT[0010] 0x0050 (0.00976682) -> 0x007d (0.12196954) | LUT[0011] 0x0058 (0.01074350) -> 0x0082 (0.12736974)
0x008d0088, // LUT[0012] 0x0060 (0.01172018) -> 0x0088 (0.13250823) | LUT[0013] 0x0068 (0.01269686) -> 0x008d (0.13741806)
0x00960091, // LUT[0014] 0x0070 (0.01367354) -> 0x0091 (0.14212590) | LUT[0015] 0x0078 (0.01465023) -> 0x0096 (0.14665365)
0x009f009a, // LUT[0016] 0x0080 (0.01562691) -> 0x009a (0.15101956) | LUT[0017] 0x0088 (0.01660359) -> 0x009f (0.15523902)
0x00a700a3, // LUT[0018] 0x0090 (0.01758027) -> 0x00a3 (0.15932515) | LUT[0019] 0x0098 (0.01855695) -> 0x00a7 (0.16328924)
0x00af00ab, // LUT[0020] 0x00a0 (0.01953363) -> 0x00ab (0.16714108) | LUT[0021] 0x00a8 (0.02051032) -> 0x00af (0.17088924)
0x00b600b3, // LUT[0022] 0x00b0 (0.02148700) -> 0x00b3 (0.17454124) | LUT[0023] 0x00b8 (0.02246368) -> 0x00b6 (0.17810378)
0x00bd00ba, // LUT[0024] 0x00c0 (0.02344036) -> 0x00ba (0.18158279) | LUT[0025] 0x00c8 (0.02441704) -> 0x00bd (0.18498359)
0x00c400c1, // LUT[0026] 0x00d0 (0.02539372) -> 0x00c1 (0.18831098) | LUT[0027] 0x00d8 (0.02637041) -> 0x00c4 (0.19156926)
0x00ca00c7, // LUT[0028] 0x00e0 (0.02734709) -> 0x00c7 (0.19476237) | LUT[0029] 0x00e8 (0.02832377) -> 0x00ca (0.19789385)
0x00d100ce, // LUT[0030] 0x00f0 (0.02930045) -> 0x00ce (0.20096697) | LUT[0031] 0x00f8 (0.03027713) -> 0x00d1 (0.20398471)
0x00d700d4, // LUT[0032] 0x0100 (0.03125382) -> 0x00d4 (0.20694980) | LUT[0033] 0x0108 (0.03223050) -> 0x00d7 (0.20986477)
0x00dd00da, // LUT[0034] 0x0110 (0.03320718) -> 0x00da (0.21273195) | LUT[0035] 0x0118 (0.03418386) -> 0x00dd (0.21555348)
0x00e200df, // LUT[0036] 0x0120 (0.03516054) -> 0x00df (0.21833138) | LUT[0037] 0x0128 (0.03613722) -> 0x00e2 (0.22106750)
0x00e800e5, // LUT[0038] 0x0130 (0.03711391) -> 0x00e5 (0.22376357) | LUT[0039] 0x0138 (0.03809059) -> 0x00e8 (0.22642122)
0x00ed00ea, // LUT[0040] 0x0140 (0.03906727) -> 0x00ea (0.22904195) | LUT[0041] 0x0148 (0.04004395) -> 0x00ed (0.23162717)
0x00f200f0, // LUT[0042] 0x0150 (0.04102063) -> 0x00f0 (0.23417823) | LUT[0043] 0x0158 (0.04199731) -> 0x00f2 (0.23669637)
0x00f700f5, // LUT[0044] 0x0160 (0.04297400) -> 0x00f5 (0.23918276) | LUT[0045] 0x0168 (0.04395068) -> 0x00f7 (0.24163852)
0x00fc00fa, // LUT[0046] 0x0170 (0.04492736) -> 0x00fa (0.24406469) | LUT[0047] 0x0178 (0.04590404) -> 0x00fc (0.24646225)
0x010100ff, // LUT[0048] 0x0180 (0.04688072) -> 0x00ff (0.24883215) | LUT[0049] 0x0188 (0.04785740) -> 0x0101 (0.25117527)
0x01060103, // LUT[0050] 0x0190 (0.04883409) -> 0x0103 (0.25349245) | LUT[0051] 0x0198 (0.04981077) -> 0x0106 (0.25578449)
0x010a0108, // LUT[0052] 0x01a0 (0.05078745) -> 0x0108 (0.25805214) | LUT[0053] 0x01a8 (0.05176413) -> 0x010a (0.26029612)
0x010f010d, // LUT[0054] 0x01b0 (0.05274081) -> 0x010d (0.26251713) | LUT[0055] 0x01b8 (0.05371749) -> 0x010f (0.26471581)
0x01130111, // LUT[0056] 0x01c0 (0.05469418) -> 0x0111 (0.26689280) | LUT[0057] 0x01c8 (0.05567086) -> 0x0113 (0.26904868)
0x01180115, // LUT[0058] 0x01d0 (0.05664754) -> 0x0115 (0.27118403) | LUT[0059] 0x01d8 (0.05762422) -> 0x0118 (0.27329939)
0x011c011a, // LUT[0060] 0x01e0 (0.05860090) -> 0x011a (0.27539529) | LUT[0061] 0x01e8 (0.05957759) -> 0x011c (0.27747221)
0x0120011e, // LUT[0062] 0x01f0 (0.06055427) -> 0x011e (0.27953065) | LUT[0063] 0x01f8 (0.06153095) -> 0x0120 (0.28157105)
0x01240122, // LUT[0064] 0x0200 (0.06250763) -> 0x0122 (0.28359387) | LUT[0065] 0x0208 (0.06348431) -> 0x0124 (0.28559951)
0x01280126, // LUT[0066] 0x0210 (0.06446099) -> 0x0126 (0.28758840) | LUT[0067] 0x0218 (0.06543768) -> 0x0128 (0.28956091)
0x012c012a, // LUT[0068] 0x0220 (0.06641436) -> 0x012a (0.29151743) | LUT[0069] 0x0228 (0.06739104) -> 0x012c (0.29345832)
0x0130012e, // LUT[0070] 0x0230 (0.06836772) -> 0x012e (0.29538393) | LUT[0071] 0x0238 (0.06934440) -> 0x0130 (0.29729459)
0x01340132, // LUT[0072] 0x0240 (0.07032108) -> 0x0132 (0.29919062) | LUT[0073] 0x0248 (0.07129777) -> 0x0134 (0.30107235)
0x01380136, // LUT[0074] 0x0250 (0.07227445) -> 0x0136 (0.30294007) | LUT[0075] 0x0258 (0.07325113) -> 0x0138 (0.30479407)
0x013c013a, // LUT[0076] 0x0260 (0.07422781) -> 0x013a (0.30663463) | LUT[0077] 0x0268 (0.07520449) -> 0x013c (0.30846204)
0x013f013d, // LUT[0078] 0x0270 (0.07618117) -> 0x013d (0.31027654) | LUT[0079] 0x0278 (0.07715786) -> 0x013f (0.31207840)
0x01430141, // LUT[0080] 0x0280 (0.07813454) -> 0x0141 (0.31386786) | LUT[0081] 0x0288 (0.07911122) -> 0x0143 (0.31564515)
0x01470145, // LUT[0082] 0x0290 (0.08008790) -> 0x0145 (0.31741053) | LUT[0083] 0x0298 (0.08106458) -> 0x0147 (0.31916419)
0x014a0148, // LUT[0084] 0x02a0 (0.08204126) -> 0x0148 (0.32090637) | LUT[0085] 0x02a8 (0.08301795) -> 0x014a (0.32263727)
0x014e014c, // LUT[0086] 0x02b0 (0.08399463) -> 0x014c (0.32435710) | LUT[0087] 0x02b8 (0.08497131) -> 0x014e (0.32606606)
0x0151014f, // LUT[0088] 0x02c0 (0.08594799) -> 0x014f (0.32776434) | LUT[0089] 0x02c8 (0.08692467) -> 0x0151 (0.32945212)
0x01540153, // LUT[0090] 0x02d0 (0.08790136) -> 0x0153 (0.33112959) | LUT[0091] 0x02d8 (0.08887804) -> 0x0154 (0.33279692)
0x01580156, // LUT[0092] 0x02e0 (0.08985472) -> 0x0156 (0.33445429) | LUT[0093] 0x02e8 (0.09083140) -> 0x0158 (0.33610186)
0x015b015a, // LUT[0094] 0x02f0 (0.09180808) -> 0x015a (0.33773979) | LUT[0095] 0x02f8 (0.09278476) -> 0x015b (0.33936825)
0x015e015d, // LUT[0096] 0x0300 (0.09376145) -> 0x015d (0.34098739) | LUT[0097] 0x0308 (0.09473813) -> 0x015e (0.34259735)
0x01620160, // LUT[0098] 0x0310 (0.09571481) -> 0x0160 (0.34419828) | LUT[0099] 0x0318 (0.09669149) -> 0x0162 (0.34579033)
0x01650163, // LUT[0100] 0x0320 (0.09766817) -> 0x0163 (0.34737363) | LUT[0101] 0x0328 (0.09864485) -> 0x0165 (0.34894832)
0x01680167, // LUT[0102] 0x0330 (0.09962154) -> 0x0167 (0.35051452) | LUT[0103] 0x0338 (0.10059822) -> 0x0168 (0.35207237)
0x016b016a, // LUT[0104] 0x0340 (0.10157490) -> 0x016a (0.35362200) | LUT[0105] 0x0348 (0.10255158) -> 0x016b (0.35516352)
0x016e016d, // LUT[0106] 0x0350 (0.10352826) -> 0x016d (0.35669705) | LUT[0107] 0x0358 (0.10450494) -> 0x016e (0.35822270)
0x01720170, // LUT[0108] 0x0360 (0.10548163) -> 0x0170 (0.35974061) | LUT[0109] 0x0368 (0.10645831) -> 0x0172 (0.36125086)
0x01750173, // LUT[0110] 0x0370 (0.10743499) -> 0x0173 (0.36275358) | LUT[0111] 0x0378 (0.10841167) -> 0x0175 (0.36424886)
0x01780176, // LUT[0112] 0x0380 (0.10938835) -> 0x0176 (0.36573681) | LUT[0113] 0x0388 (0.11036503) -> 0x0178 (0.36721754)
0x017b0179, // LUT[0114] 0x0390 (0.11134172) -> 0x0179 (0.36869113) | LUT[0115] 0x0398 (0.11231840) -> 0x017b (0.37015769)
0x017e017c, // LUT[0116] 0x03a0 (0.11329508) -> 0x017c (0.37161731) | LUT[0117] 0x03a8 (0.11427176) -> 0x017e (0.37307008)
0x0181017f, // LUT[0118] 0x03b0 (0.11524844) -> 0x017f (0.37451609) | LUT[0119] 0x03b8 (0.11622513) -> 0x0181 (0.37595544)
0x01840182, // LUT[0120] 0x03c0 (0.11720181) -> 0x0182 (0.37738820) | LUT[0121] 0x03c8 (0.11817849) -> 0x0184 (0.37881447)
0x01860185, // LUT[0122] 0x03d0 (0.11915517) -> 0x0185 (0.38023432) | LUT[0123] 0x03d8 (0.12013185) -> 0x0186 (0.38164784)
0x01890188, // LUT[0124] 0x03e0 (0.12110853) -> 0x0188 (0.38305510) | LUT[0125] 0x03e8 (0.12208522) -> 0x0189 (0.38445618)
0x018c018b, // LUT[0126] 0x03f0 (0.12306190) -> 0x018b (0.38585117) | LUT[0127] 0x03f8 (0.12403858) -> 0x018c (0.38724013)
0x018f018e, // LUT[0128] 0x0400 (0.12501526) -> 0x018e (0.38862313) | LUT[0129] 0x0408 (0.12599194) -> 0x018f (0.39000026)
0x01920190, // LUT[0130] 0x0410 (0.12696862) -> 0x0190 (0.39137157) | LUT[0131] 0x0418 (0.12794531) -> 0x0192 (0.39273715)
0x01950193, // LUT[0132] 0x0420 (0.12892199) -> 0x0193 (0.39409704) | LUT[0133] 0x0428 (0.12989867) -> 0x0195 (0.39545134)
0x01970196, // LUT[0134] 0x0430 (0.13087535) -> 0x0196 (0.39680008) | LUT[0135] 0x0438 (0.13185203) -> 0x0197 (0.39814335)
0x019a0199, // LUT[0136] 0x0440 (0.13282871) -> 0x0199 (0.39948120) | LUT[0137] 0x0448 (0.13380540) -> 0x019a (0.40081370)
0x019d019b, // LUT[0138] 0x0450 (0.13478208) -> 0x019b (0.40214090) | LUT[0139] 0x0458 (0.13575876) -> 0x019d (0.40346287)
0x019f019e, // LUT[0140] 0x0460 (0.13673544) -> 0x019e (0.40477966) | LUT[0141] 0x0468 (0.13771212) -> 0x019f (0.40609133)
0x01a201a1, // LUT[0142] 0x0470 (0.13868880) -> 0x01a1 (0.40739793) | LUT[0143] 0x0478 (0.13966549) -> 0x01a2 (0.40869953)
0x01a501a3, // LUT[0144] 0x0480 (0.14064217) -> 0x01a3 (0.40999617) | LUT[0145] 0x0488 (0.14161885) -> 0x01a5 (0.41128790)
0x01a701a6, // LUT[0146] 0x0490 (0.14259553) -> 0x01a6 (0.41257479) | LUT[0147] 0x0498 (0.14357221) -> 0x01a7 (0.41385688)
0x01aa01a9, // LUT[0148] 0x04a0 (0.14454890) -> 0x01a9 (0.41513422) | LUT[0149] 0x04a8 (0.14552558) -> 0x01aa (0.41640686)
0x01ad01ab, // LUT[0150] 0x04b0 (0.14650226) -> 0x01ab (0.41767485) | LUT[0151] 0x04b8 (0.14747894) -> 0x01ad (0.41893824)
0x01af01ae, // LUT[0152] 0x04c0 (0.14845562) -> 0x01ae (0.42019707) | LUT[0153] 0x04c8 (0.14943230) -> 0x01af (0.42145140)
0x01b201b0, // LUT[0154] 0x04d0 (0.15040899) -> 0x01b0 (0.42270125) | LUT[0155] 0x04d8 (0.15138567) -> 0x01b2 (0.42394670)
0x01b401b3, // LUT[0156] 0x04e0 (0.15236235) -> 0x01b3 (0.42518776) | LUT[0157] 0x04e8 (0.15333903) -> 0x01b4 (0.42642449)
0x01b701b5, // LUT[0158] 0x04f0 (0.15431571) -> 0x01b5 (0.42765694) | LUT[0159] 0x04f8 (0.15529239) -> 0x01b7 (0.42888513)
0x01b901b8, // LUT[0160] 0x0500 (0.15626908) -> 0x01b8 (0.43010912) | LUT[0161] 0x0508 (0.15724576) -> 0x01b9 (0.43132895)
0x01bc01ba, // LUT[0162] 0x0510 (0.15822244) -> 0x01ba (0.43254465) | LUT[0163] 0x0518 (0.15919912) -> 0x01bc (0.43375626)
0x01be01bd, // LUT[0164] 0x0520 (0.16017580) -> 0x01bd (0.43496383) | LUT[0165] 0x0528 (0.16115248) -> 0x01be (0.43616738)
0x01c101bf, // LUT[0166] 0x0530 (0.16212917) -> 0x01bf (0.43736696) | LUT[0167] 0x0538 (0.16310585) -> 0x01c1 (0.43856261)
0x01c301c2, // LUT[0168] 0x0540 (0.16408253) -> 0x01c2 (0.43975436) | LUT[0169] 0x0548 (0.16505921) -> 0x01c3 (0.44094225)
0x01c601c4, // LUT[0170] 0x0550 (0.16603589) -> 0x01c4 (0.44212631) | LUT[0171] 0x0558 (0.16701257) -> 0x01c6 (0.44330657)
0x01c801c7, // LUT[0172] 0x0560 (0.16798926) -> 0x01c7 (0.44448308) | LUT[0173] 0x0568 (0.16896594) -> 0x01c8 (0.44565586)
0x01ca01c9, // LUT[0174] 0x0570 (0.16994262) -> 0x01c9 (0.44682495) | LUT[0175] 0x0578 (0.17091930) -> 0x01ca (0.44799038)
0x01cd01cb, // LUT[0176] 0x0580 (0.17189598) -> 0x01cb (0.44915218) | LUT[0177] 0x0588 (0.17287267) -> 0x01cd (0.45031039)
0x01cf01ce, // LUT[0178] 0x0590 (0.17384935) -> 0x01ce (0.45146503) | LUT[0179] 0x0598 (0.17482603) -> 0x01cf (0.45261615)
0x01d101d0, // LUT[0180] 0x05a0 (0.17580271) -> 0x01d0 (0.45376375) | LUT[0181] 0x05a8 (0.17677939) -> 0x01d1 (0.45490789)
0x01d401d3, // LUT[0182] 0x05b0 (0.17775607) -> 0x01d3 (0.45604859) | LUT[0183] 0x05b8 (0.17873276) -> 0x01d4 (0.45718587)
0x01d601d5, // LUT[0184] 0x05c0 (0.17970944) -> 0x01d5 (0.45831976) | LUT[0185] 0x05c8 (0.18068612) -> 0x01d6 (0.45945030)
0x01d801d7, // LUT[0186] 0x05d0 (0.18166280) -> 0x01d7 (0.46057751) | LUT[0187] 0x05d8 (0.18263948) -> 0x01d8 (0.46170142)
0x01db01d9, // LUT[0188] 0x05e0 (0.18361616) -> 0x01d9 (0.46282206) | LUT[0189] 0x05e8 (0.18459285) -> 0x01db (0.46393945)
0x01dd01dc, // LUT[0190] 0x05f0 (0.18556953) -> 0x01dc (0.46505362) | LUT[0191] 0x05f8 (0.18654621) -> 0x01dd (0.46616459)
0x01df01de, // LUT[0192] 0x0600 (0.18752289) -> 0x01de (0.46727240) | LUT[0193] 0x0608 (0.18849957) -> 0x01df (0.46837707)
0x01e101e0, // LUT[0194] 0x0610 (0.18947625) -> 0x01e0 (0.46947861) | LUT[0195] 0x0618 (0.19045294) -> 0x01e1 (0.47057707)
0x01e401e3, // LUT[0196] 0x0620 (0.19142962) -> 0x01e3 (0.47167245) | LUT[0197] 0x0628 (0.19240630) -> 0x01e4 (0.47276480)
0x01e601e5, // LUT[0198] 0x0630 (0.19338298) -> 0x01e5 (0.47385412) | LUT[0199] 0x0638 (0.19435966) -> 0x01e6 (0.47494044)
0x01e801e7, // LUT[0200] 0x0640 (0.19533634) -> 0x01e7 (0.47602379) | LUT[0201] 0x0648 (0.19631303) -> 0x01e8 (0.47710420)
0x01ea01e9, // LUT[0202] 0x0650 (0.19728971) -> 0x01e9 (0.47818167) | LUT[0203] 0x0658 (0.19826639) -> 0x01ea (0.47925624)
0x01ec01eb, // LUT[0204] 0x0660 (0.19924307) -> 0x01eb (0.48032792) | LUT[0205] 0x0668 (0.20021975) -> 0x01ec (0.48139674)
0x01ef01ee, // LUT[0206] 0x0670 (0.20119644) -> 0x01ee (0.48246272) | LUT[0207] 0x0678 (0.20217312) -> 0x01ef (0.48352589)
0x01f101f0, // LUT[0208] 0x0680 (0.20314980) -> 0x01f0 (0.48458625) | LUT[0209] 0x0688 (0.20412648) -> 0x01f1 (0.48564384)
0x01f301f2, // LUT[0210] 0x0690 (0.20510316) -> 0x01f2 (0.48669867) | LUT[0211] 0x0698 (0.20607984) -> 0x01f3 (0.48775077)
0x01f501f4, // LUT[0212] 0x06a0 (0.20705653) -> 0x01f4 (0.48880015) | LUT[0213] 0x06a8 (0.20803321) -> 0x01f5 (0.48984683)
0x01f701f6, // LUT[0214] 0x06b0 (0.20900989) -> 0x01f6 (0.49089084) | LUT[0215] 0x06b8 (0.20998657) -> 0x01f7 (0.49193218)
0x01f901f8, // LUT[0216] 0x06c0 (0.21096325) -> 0x01f8 (0.49297089) | LUT[0217] 0x06c8 (0.21193993) -> 0x01f9 (0.49400698)
0x01fb01fa, // LUT[0218] 0x06d0 (0.21291662) -> 0x01fa (0.49504047) | LUT[0219] 0x06d8 (0.21389330) -> 0x01fb (0.49607138)
0x01fe01fd, // LUT[0220] 0x06e0 (0.21486998) -> 0x01fd (0.49709972) | LUT[0221] 0x06e8 (0.21584666) -> 0x01fe (0.49812552)
0x020001ff, // LUT[0222] 0x06f0 (0.21682334) -> 0x01ff (0.49914878) | LUT[0223] 0x06f8 (0.21780002) -> 0x0200 (0.50016954)
0x02020201, // LUT[0224] 0x0700 (0.21877671) -> 0x0201 (0.50118780) | LUT[0225] 0x0708 (0.21975339) -> 0x0202 (0.50220359)
0x02040203, // LUT[0226] 0x0710 (0.22073007) -> 0x0203 (0.50321691) | LUT[0227] 0x0718 (0.22170675) -> 0x0204 (0.50422779)
0x02060205, // LUT[0228] 0x0720 (0.22268343) -> 0x0205 (0.50523625) | LUT[0229] 0x0728 (0.22366011) -> 0x0206 (0.50624230)
0x02080207, // LUT[0230] 0x0730 (0.22463680) -> 0x0207 (0.50724595) | LUT[0231] 0x0738 (0.22561348) -> 0x0208 (0.50824723)
0x020a0209, // LUT[0232] 0x0740 (0.22659016) -> 0x0209 (0.50924614) | LUT[0233] 0x0748 (0.22756684) -> 0x020a (0.51024271)
0x020c020b, // LUT[0234] 0x0750 (0.22854352) -> 0x020b (0.51123695) | LUT[0235] 0x0758 (0.22952021) -> 0x020c (0.51222887)
0x020e020d, // LUT[0236] 0x0760 (0.23049689) -> 0x020d (0.51321850) | LUT[0237] 0x0768 (0.23147357) -> 0x020e (0.51420584)
0x0210020f, // LUT[0238] 0x0770 (0.23245025) -> 0x020f (0.51519091) | LUT[0239] 0x0778 (0.23342693) -> 0x0210 (0.51617372)
0x02120211, // LUT[0240] 0x0780 (0.23440361) -> 0x0211 (0.51715430) | LUT[0241] 0x0788 (0.23538030) -> 0x0212 (0.51813265)
0x02140213, // LUT[0242] 0x0790 (0.23635698) -> 0x0213 (0.51910878) | LUT[0243] 0x0798 (0.23733366) -> 0x0214 (0.52008272)
0x02160215, // LUT[0244] 0x07a0 (0.23831034) -> 0x0215 (0.52105448) | LUT[0245] 0x07a8 (0.23928702) -> 0x0216 (0.52202406)
0x02180217, // LUT[0246] 0x07b0 (0.24026370) -> 0x0217 (0.52299149) | LUT[0247] 0x07b8 (0.24124039) -> 0x0218 (0.52395678)
0x021a0219, // LUT[0248] 0x07c0 (0.24221707) -> 0x0219 (0.52491993) | LUT[0249] 0x07c8 (0.24319375) -> 0x021a (0.52588097)
0x021c021b, // LUT[0250] 0x07d0 (0.24417043) -> 0x021b (0.52683991) | LUT[0251] 0x07d8 (0.24514711) -> 0x021c (0.52779676)
0x021e021d, // LUT[0252] 0x07e0 (0.24612379) -> 0x021d (0.52875153) | LUT[0253] 0x07e8 (0.24710048) -> 0x021e (0.52970424)
0x0220021f, // LUT[0254] 0x07f0 (0.24807716) -> 0x021f (0.53065489) | LUT[0255] 0x07f8 (0.24905384) -> 0x0220 (0.53160351)
0x02220221, // LUT[0256] 0x0800 (0.25003052) -> 0x0221 (0.53255010) | LUT[0257] 0x0808 (0.25100720) -> 0x0222 (0.53349467)
0x02240223, // LUT[0258] 0x0810 (0.25198388) -> 0x0223 (0.53443724) | LUT[0259] 0x0818 (0.25296057) -> 0x0224 (0.53537782)
0x02260225, // LUT[0260] 0x0820 (0.25393725) -> 0x0225 (0.53631642) | LUT[0261] 0x0828 (0.25491393) -> 0x0226 (0.53725306)
0x02280227, // LUT[0262] 0x0830 (0.25589061) -> 0x0227 (0.53818774) | LUT[0263] 0x0838 (0.25686729) -> 0x0228 (0.53912047)
0x02290228, // LUT[0264] 0x0840 (0.25784398) -> 0x0228 (0.54005127) | LUT[0265] 0x0848 (0.25882066) -> 0x0229 (0.54098016)
0x022b022a, // LUT[0266] 0x0850 (0.25979734) -> 0x022a (0.54190713) | LUT[0267] 0x0858 (0.26077402) -> 0x022b (0.54283220)
0x022d022c, // LUT[0268] 0x0860 (0.26175070) -> 0x022c (0.54375538) | LUT[0269] 0x0868 (0.26272738) -> 0x022d (0.54467669)
0x022f022e, // LUT[0270] 0x0870 (0.26370407) -> 0x022e (0.54559613) | LUT[0271] 0x0878 (0.26468075) -> 0x022f (0.54651372)
0x02310230, // LUT[0272] 0x0880 (0.26565743) -> 0x0230 (0.54742946) | LUT[0273] 0x0888 (0.26663411) -> 0x0231 (0.54834337)
0x02330232, // LUT[0274] 0x0890 (0.26761079) -> 0x0232 (0.54925545) | LUT[0275] 0x0898 (0.26858747) -> 0x0233 (0.55016572)
0x02350234, // LUT[0276] 0x08a0 (0.26956416) -> 0x0234 (0.55107418) | LUT[0277] 0x08a8 (0.27054084) -> 0x0235 (0.55198085)
0x02370236, // LUT[0278] 0x08b0 (0.27151752) -> 0x0236 (0.55288574) | LUT[0279] 0x08b8 (0.27249420) -> 0x0237 (0.55378885)
0x02380237, // LUT[0280] 0x08c0 (0.27347088) -> 0x0237 (0.55469020) | LUT[0281] 0x08c8 (0.27444756) -> 0x0238 (0.55558980)
0x023a0239, // LUT[0282] 0x08d0 (0.27542425) -> 0x0239 (0.55648765) | LUT[0283] 0x08d8 (0.27640093) -> 0x023a (0.55738377)
0x023c023b, // LUT[0284] 0x08e0 (0.27737761) -> 0x023b (0.55827816) | LUT[0285] 0x08e8 (0.27835429) -> 0x023c (0.55917083)
0x023e023d, // LUT[0286] 0x08f0 (0.27933097) -> 0x023d (0.56006180) | LUT[0287] 0x08f8 (0.28030765) -> 0x023e (0.56095107)
0x0240023f, // LUT[0288] 0x0900 (0.28128434) -> 0x023f (0.56183865) | LUT[0289] 0x0908 (0.28226102) -> 0x0240 (0.56272455)
0x02410241, // LUT[0290] 0x0910 (0.28323770) -> 0x0241 (0.56360879) | LUT[0291] 0x0918 (0.28421438) -> 0x0241 (0.56449136)
0x02430242, // LUT[0292] 0x0920 (0.28519106) -> 0x0242 (0.56537227) | LUT[0293] 0x0928 (0.28616775) -> 0x0243 (0.56625155)
0x02450244, // LUT[0294] 0x0930 (0.28714443) -> 0x0244 (0.56712918) | LUT[0295] 0x0938 (0.28812111) -> 0x0245 (0.56800519)
0x02470246, // LUT[0296] 0x0940 (0.28909779) -> 0x0246 (0.56887959) | LUT[0297] 0x0948 (0.29007447) -> 0x0247 (0.56975237)
0x02490248, // LUT[0298] 0x0950 (0.29105115) -> 0x0248 (0.57062355) | LUT[0299] 0x0958 (0.29202784) -> 0x0249 (0.57149314)
0x024a024a, // LUT[0300] 0x0960 (0.29300452) -> 0x024a (0.57236114) | LUT[0301] 0x0968 (0.29398120) -> 0x024a (0.57322757)
0x024c024b, // LUT[0302] 0x0970 (0.29495788) -> 0x024b (0.57409243) | LUT[0303] 0x0978 (0.29593456) -> 0x024c (0.57495573)
0x024e024d, // LUT[0304] 0x0980 (0.29691124) -> 0x024d (0.57581747) | LUT[0305] 0x0988 (0.29788793) -> 0x024e (0.57667767)
0x0250024f, // LUT[0306] 0x0990 (0.29886461) -> 0x024f (0.57753633) | LUT[0307] 0x0998 (0.29984129) -> 0x0250 (0.57839347)
0x02510251, // LUT[0308] 0x09a0 (0.30081797) -> 0x0251 (0.57924908) | LUT[0309] 0x09a8 (0.30179465) -> 0x0251 (0.58010318)
0x02530252, // LUT[0310] 0x09b0 (0.30277133) -> 0x0252 (0.58095577) | LUT[0311] 0x09b8 (0.30374802) -> 0x0253 (0.58180686)
0x02550254, // LUT[0312] 0x09c0 (0.30472470) -> 0x0254 (0.58265647) | LUT[0313] 0x09c8 (0.30570138) -> 0x0255 (0.58350458)
0x02570256, // LUT[0314] 0x09d0 (0.30667806) -> 0x0256 (0.58435122) | LUT[0315] 0x09d8 (0.30765474) -> 0x0257 (0.58519640)
0x02580258, // LUT[0316] 0x09e0 (0.30863142) -> 0x0258 (0.58604011) | LUT[0317] 0x09e8 (0.30960811) -> 0x0258 (0.58688236)
0x025a0259, // LUT[0318] 0x09f0 (0.31058479) -> 0x0259 (0.58772317) | LUT[0319] 0x09f8 (0.31156147) -> 0x025a (0.58856253)
0x025c025b, // LUT[0320] 0x0a00 (0.31253815) -> 0x025b (0.58940046) | LUT[0321] 0x0a08 (0.31351483) -> 0x025c (0.59023697)
0x025e025d, // LUT[0322] 0x0a10 (0.31449152) -> 0x025d (0.59107205) | LUT[0323] 0x0a18 (0.31546820) -> 0x025e (0.59190572)
0x025f025e, // LUT[0324] 0x0a20 (0.31644488) -> 0x025e (0.59273799) | LUT[0325] 0x0a28 (0.31742156) -> 0x025f (0.59356885)
0x02610260, // LUT[0326] 0x0a30 (0.31839824) -> 0x0260 (0.59439832) | LUT[0327] 0x0a38 (0.31937492) -> 0x0261 (0.59522640)
0x02630262, // LUT[0328] 0x0a40 (0.32035161) -> 0x0262 (0.59605311) | LUT[0329] 0x0a48 (0.32132829) -> 0x0263 (0.59687844)
0x02640263, // LUT[0330] 0x0a50 (0.32230497) -> 0x0263 (0.59770240) | LUT[0331] 0x0a58 (0.32328165) -> 0x0264 (0.59852500)
0x02660265, // LUT[0332] 0x0a60 (0.32425833) -> 0x0265 (0.59934625) | LUT[0333] 0x0a68 (0.32523501) -> 0x0266 (0.60016615)
0x02680267, // LUT[0334] 0x0a70 (0.32621170) -> 0x0267 (0.60098471) | LUT[0335] 0x0a78 (0.32718838) -> 0x0268 (0.60180193)
0x02690268, // LUT[0336] 0x0a80 (0.32816506) -> 0x0268 (0.60261782) | LUT[0337] 0x0a88 (0.32914174) -> 0x0269 (0.60343239)
0x026b026a, // LUT[0338] 0x0a90 (0.33011842) -> 0x026a (0.60424564) | LUT[0339] 0x0a98 (0.33109510) -> 0x026b (0.60505758)
0x026d026c, // LUT[0340] 0x0aa0 (0.33207179) -> 0x026c (0.60586822) | LUT[0341] 0x0aa8 (0.33304847) -> 0x026d (0.60667755)
0x026e026d, // LUT[0342] 0x0ab0 (0.33402515) -> 0x026d (0.60748560) | LUT[0343] 0x0ab8 (0.33500183) -> 0x026e (0.60829235)
0x0270026f, // LUT[0344] 0x0ac0 (0.33597851) -> 0x026f (0.60909782) | LUT[0345] 0x0ac8 (0.33695519) -> 0x0270 (0.60990202)
0x02720271, // LUT[0346] 0x0ad0 (0.33793188) -> 0x0271 (0.61070494) | LUT[0347] 0x0ad8 (0.33890856) -> 0x0272 (0.61150661)
0x02730272, // LUT[0348] 0x0ae0 (0.33988524) -> 0x0272 (0.61230701) | LUT[0349] 0x0ae8 (0.34086192) -> 0x0273 (0.61310616)
0x02750274, // LUT[0350] 0x0af0 (0.34183860) -> 0x0274 (0.61390406) | LUT[0351] 0x0af8 (0.34281529) -> 0x0275 (0.61470071)
0x02760276, // LUT[0352] 0x0b00 (0.34379197) -> 0x0276 (0.61549613) | LUT[0353] 0x0b08 (0.34476865) -> 0x0276 (0.61629032)
0x02780277, // LUT[0354] 0x0b10 (0.34574533) -> 0x0277 (0.61708329) | LUT[0355] 0x0b18 (0.34672201) -> 0x0278 (0.61787503)
0x027a0279, // LUT[0356] 0x0b20 (0.34769869) -> 0x0279 (0.61866555) | LUT[0357] 0x0b28 (0.34867538) -> 0x027a (0.61945487)
0x027b027b, // LUT[0358] 0x0b30 (0.34965206) -> 0x027b (0.62024298) | LUT[0359] 0x0b38 (0.35062874) -> 0x027b (0.62102989)
0x027d027c, // LUT[0360] 0x0b40 (0.35160542) -> 0x027c (0.62181561) | LUT[0361] 0x0b48 (0.35258210) -> 0x027d (0.62260013)
0x027f027e, // LUT[0362] 0x0b50 (0.35355878) -> 0x027e (0.62338348) | LUT[0363] 0x0b58 (0.35453547) -> 0x027f (0.62416564)
0x0280027f, // LUT[0364] 0x0b60 (0.35551215) -> 0x027f (0.62494663) | LUT[0365] 0x0b68 (0.35648883) -> 0x0280 (0.62572645)
0x02820281, // LUT[0366] 0x0b70 (0.35746551) -> 0x0281 (0.62650510) | LUT[0367] 0x0b78 (0.35844219) -> 0x0282 (0.62728260)
0x02830283, // LUT[0368] 0x0b80 (0.35941887) -> 0x0283 (0.62805894) | LUT[0369] 0x0b88 (0.36039556) -> 0x0283 (0.62883413)
0x02850284, // LUT[0370] 0x0b90 (0.36137224) -> 0x0284 (0.62960817) | LUT[0371] 0x0b98 (0.36234892) -> 0x0285 (0.63038108)
0x02860286, // LUT[0372] 0x0ba0 (0.36332560) -> 0x0286 (0.63115285) | LUT[0373] 0x0ba8 (0.36430228) -> 0x0286 (0.63192349)
0x02880287, // LUT[0374] 0x0bb0 (0.36527896) -> 0x0287 (0.63269300) | LUT[0375] 0x0bb8 (0.36625565) -> 0x0288 (0.63346139)
0x028a0289, // LUT[0376] 0x0bc0 (0.36723233) -> 0x0289 (0.63422866) | LUT[0377] 0x0bc8 (0.36820901) -> 0x028a (0.63499483)
0x028b028a, // LUT[0378] 0x0bd0 (0.36918569) -> 0x028a (0.63575988) | LUT[0379] 0x0bd8 (0.37016237) -> 0x028b (0.63652383)
0x028d028c, // LUT[0380] 0x0be0 (0.37113906) -> 0x028c (0.63728668) | LUT[0381] 0x0be8 (0.37211574) -> 0x028d (0.63804844)
0x028e028e, // LUT[0382] 0x0bf0 (0.37309242) -> 0x028e (0.63880911) | LUT[0383] 0x0bf8 (0.37406910) -> 0x028e (0.63956869)
0x0290028f, // LUT[0384] 0x0c00 (0.37504578) -> 0x028f (0.64032720) | LUT[0385] 0x0c08 (0.37602246) -> 0x0290 (0.64108462)
0x02910291, // LUT[0386] 0x0c10 (0.37699915) -> 0x0291 (0.64184098) | LUT[0387] 0x0c18 (0.37797583) -> 0x0291 (0.64259626)
0x02930292, // LUT[0388] 0x0c20 (0.37895251) -> 0x0292 (0.64335048) | LUT[0389] 0x0c28 (0.37992919) -> 0x0293 (0.64410364)
0x02940294, // LUT[0390] 0x0c30 (0.38090587) -> 0x0294 (0.64485575) | LUT[0391] 0x0c38 (0.38188255) -> 0x0294 (0.64560680)
0x02960295, // LUT[0392] 0x0c40 (0.38285924) -> 0x0295 (0.64635681) | LUT[0393] 0x0c48 (0.38383592) -> 0x0296 (0.64710578)
0x02980297, // LUT[0394] 0x0c50 (0.38481260) -> 0x0297 (0.64785370) | LUT[0395] 0x0c58 (0.38578928) -> 0x0298 (0.64860060)
0x02990298, // LUT[0396] 0x0c60 (0.38676596) -> 0x0298 (0.64934646) | LUT[0397] 0x0c68 (0.38774264) -> 0x0299 (0.65009129)
0x029b029a, // LUT[0398] 0x0c70 (0.38871933) -> 0x029a (0.65083510) | LUT[0399] 0x0c78 (0.38969601) -> 0x029b (0.65157790)
0x029c029b, // LUT[0400] 0x0c80 (0.39067269) -> 0x029b (0.65231968) | LUT[0401] 0x0c88 (0.39164937) -> 0x029c (0.65306044)
0x029e029d, // LUT[0402] 0x0c90 (0.39262605) -> 0x029d (0.65380020) | LUT[0403] 0x0c98 (0.39360273) -> 0x029e (0.65453896)
0x029f029e, // LUT[0404] 0x0ca0 (0.39457942) -> 0x029e (0.65527672) | LUT[0405] 0x0ca8 (0.39555610) -> 0x029f (0.65601348)
0x02a102a0, // LUT[0406] 0x0cb0 (0.39653278) -> 0x02a0 (0.65674925) | LUT[0407] 0x0cb8 (0.39750946) -> 0x02a1 (0.65748404)
0x02a202a1, // LUT[0408] 0x0cc0 (0.39848614) -> 0x02a1 (0.65821784) | LUT[0409] 0x0cc8 (0.39946283) -> 0x02a2 (0.65895066)
0x02a402a3, // LUT[0410] 0x0cd0 (0.40043951) -> 0x02a3 (0.65968250) | LUT[0411] 0x0cd8 (0.40141619) -> 0x02a4 (0.66041337)
0x02a502a4, // LUT[0412] 0x0ce0 (0.40239287) -> 0x02a4 (0.66114327) | LUT[0413] 0x0ce8 (0.40336955) -> 0x02a5 (0.66187220)
0x02a702a6, // LUT[0414] 0x0cf0 (0.40434623) -> 0x02a6 (0.66260018) | LUT[0415] 0x0cf8 (0.40532292) -> 0x02a7 (0.66332719)
0x02a802a7, // LUT[0416] 0x0d00 (0.40629960) -> 0x02a7 (0.66405325) | LUT[0417] 0x0d08 (0.40727628) -> 0x02a8 (0.66477836)
0x02aa02a9, // LUT[0418] 0x0d10 (0.40825296) -> 0x02a9 (0.66550252) | LUT[0419] 0x0d18 (0.40922964) -> 0x02aa (0.66622573)
0x02ab02aa, // LUT[0420] 0x0d20 (0.41020632) -> 0x02aa (0.66694801) | LUT[0421] 0x0d28 (0.41118301) -> 0x02ab (0.66766934)
0x02ac02ac, // LUT[0422] 0x0d30 (0.41215969) -> 0x02ac (0.66838975) | LUT[0423] 0x0d38 (0.41313637) -> 0x02ac (0.66910922)
0x02ae02ad, // LUT[0424] 0x0d40 (0.41411305) -> 0x02ad (0.66982776) | LUT[0425] 0x0d48 (0.41508973) -> 0x02ae (0.67054538)
0x02af02af, // LUT[0426] 0x0d50 (0.41606641) -> 0x02af (0.67126209) | LUT[0427] 0x0d58 (0.41704310) -> 0x02af (0.67197787)
0x02b102b0, // LUT[0428] 0x0d60 (0.41801978) -> 0x02b0 (0.67269274) | LUT[0429] 0x0d68 (0.41899646) -> 0x02b1 (0.67340670)
0x02b202b2, // LUT[0430] 0x0d70 (0.41997314) -> 0x02b2 (0.67411975) | LUT[0431] 0x0d78 (0.42094982) -> 0x02b2 (0.67483190)
0x02b402b3, // LUT[0432] 0x0d80 (0.42192650) -> 0x02b3 (0.67554315) | LUT[0433] 0x0d88 (0.42290319) -> 0x02b4 (0.67625350)
0x02b502b5, // LUT[0434] 0x0d90 (0.42387987) -> 0x02b5 (0.67696296) | LUT[0435] 0x0d98 (0.42485655) -> 0x02b5 (0.67767152)
0x02b702b6, // LUT[0436] 0x0da0 (0.42583323) -> 0x02b6 (0.67837920) | LUT[0437] 0x0da8 (0.42680991) -> 0x02b7 (0.67908599)
0x02b802b7, // LUT[0438] 0x0db0 (0.42778660) -> 0x02b7 (0.67979190) | LUT[0439] 0x0db8 (0.42876328) -> 0x02b8 (0.68049693)
0x02ba02b9, // LUT[0440] 0x0dc0 (0.42973996) -> 0x02b9 (0.68120109) | LUT[0441] 0x0dc8 (0.43071664) -> 0x02ba (0.68190438)
0x02bb02ba, // LUT[0442] 0x0dd0 (0.43169332) -> 0x02ba (0.68260679) | LUT[0443] 0x0dd8 (0.43267000) -> 0x02bb (0.68330834)
0x02bc02bc, // LUT[0444] 0x0de0 (0.43364669) -> 0x02bc (0.68400903) | LUT[0445] 0x0de8 (0.43462337) -> 0x02bc (0.68470885)
0x02be02bd, // LUT[0446] 0x0df0 (0.43560005) -> 0x02bd (0.68540782) | LUT[0447] 0x0df8 (0.43657673) -> 0x02be (0.68610593)
0x02bf02bf, // LUT[0448] 0x0e00 (0.43755341) -> 0x02bf (0.68680320) | LUT[0449] 0x0e08 (0.43853009) -> 0x02bf (0.68749961)
0x02c102c0, // LUT[0450] 0x0e10 (0.43950678) -> 0x02c0 (0.68819518) | LUT[0451] 0x0e18 (0.44048346) -> 0x02c1 (0.68888990)
0x02c202c1, // LUT[0452] 0x0e20 (0.44146014) -> 0x02c1 (0.68958379) | LUT[0453] 0x0e28 (0.44243682) -> 0x02c2 (0.69027684)
0x02c402c3, // LUT[0454] 0x0e30 (0.44341350) -> 0x02c3 (0.69096905) | LUT[0455] 0x0e38 (0.44439018) -> 0x02c4 (0.69166044)
0x02c502c4, // LUT[0456] 0x0e40 (0.44536687) -> 0x02c4 (0.69235099) | LUT[0457] 0x0e48 (0.44634355) -> 0x02c5 (0.69304072)
0x02c602c6, // LUT[0458] 0x0e50 (0.44732023) -> 0x02c6 (0.69372963) | LUT[0459] 0x0e58 (0.44829691) -> 0x02c6 (0.69441772)
0x02c802c7, // LUT[0460] 0x0e60 (0.44927359) -> 0x02c7 (0.69510499) | LUT[0461] 0x0e68 (0.45025027) -> 0x02c8 (0.69579145)
0x02c902c8, // LUT[0462] 0x0e70 (0.45122696) -> 0x02c8 (0.69647709) | LUT[0463] 0x0e78 (0.45220364) -> 0x02c9 (0.69716192)
0x02cb02ca, // LUT[0464] 0x0e80 (0.45318032) -> 0x02ca (0.69784595) | LUT[0465] 0x0e88 (0.45415700) -> 0x02cb (0.69852918)
0x02cc02cb, // LUT[0466] 0x0e90 (0.45513368) -> 0x02cb (0.69921160) | LUT[0467] 0x0e98 (0.45611037) -> 0x02cc (0.69989323)
0x02cd02cd, // LUT[0468] 0x0ea0 (0.45708705) -> 0x02cd (0.70057406) | LUT[0469] 0x0ea8 (0.45806373) -> 0x02cd (0.70125410)
0x02cf02ce, // LUT[0470] 0x0eb0 (0.45904041) -> 0x02ce (0.70193334) | LUT[0471] 0x0eb8 (0.46001709) -> 0x02cf (0.70261180)
0x02d002cf, // LUT[0472] 0x0ec0 (0.46099377) -> 0x02cf (0.70328947) | LUT[0473] 0x0ec8 (0.46197046) -> 0x02d0 (0.70396637)
0x02d202d1, // LUT[0474] 0x0ed0 (0.46294714) -> 0x02d1 (0.70464248) | LUT[0475] 0x0ed8 (0.46392382) -> 0x02d2 (0.70531781)
0x02d302d2, // LUT[0476] 0x0ee0 (0.46490050) -> 0x02d2 (0.70599237) | LUT[0477] 0x0ee8 (0.46587718) -> 0x02d3 (0.70666615)
0x02d402d4, // LUT[0478] 0x0ef0 (0.46685386) -> 0x02d4 (0.70733917) | LUT[0479] 0x0ef8 (0.46783055) -> 0x02d4 (0.70801142)
0x02d602d5, // LUT[0480] 0x0f00 (0.46880723) -> 0x02d5 (0.70868290) | LUT[0481] 0x0f08 (0.46978391) -> 0x02d6 (0.70935362)
0x02d702d6, // LUT[0482] 0x0f10 (0.47076059) -> 0x02d6 (0.71002358) | LUT[0483] 0x0f18 (0.47173727) -> 0x02d7 (0.71069278)
0x02d802d8, // LUT[0484] 0x0f20 (0.47271395) -> 0x02d8 (0.71136123) | LUT[0485] 0x0f28 (0.47369064) -> 0x02d8 (0.71202892)
0x02da02d9, // LUT[0486] 0x0f30 (0.47466732) -> 0x02d9 (0.71269587) | LUT[0487] 0x0f38 (0.47564400) -> 0x02da (0.71336206)
0x02db02da, // LUT[0488] 0x0f40 (0.47662068) -> 0x02da (0.71402751) | LUT[0489] 0x0f48 (0.47759736) -> 0x02db (0.71469222)
0x02dc02dc, // LUT[0490] 0x0f50 (0.47857404) -> 0x02dc (0.71535619) | LUT[0491] 0x0f58 (0.47955073) -> 0x02dc (0.71601941)
0x02de02dd, // LUT[0492] 0x0f60 (0.48052741) -> 0x02dd (0.71668190) | LUT[0493] 0x0f68 (0.48150409) -> 0x02de (0.71734366)
0x02df02df, // LUT[0494] 0x0f70 (0.48248077) -> 0x02df (0.71800468) | LUT[0495] 0x0f78 (0.48345745) -> 0x02df (0.71866498)
0x02e102e0, // LUT[0496] 0x0f80 (0.48443414) -> 0x02e0 (0.71932455) | LUT[0497] 0x0f88 (0.48541082) -> 0x02e1 (0.71998339)
0x02e202e1, // LUT[0498] 0x0f90 (0.48638750) -> 0x02e1 (0.72064151) | LUT[0499] 0x0f98 (0.48736418) -> 0x02e2 (0.72129891)
0x02e302e3, // LUT[0500] 0x0fa0 (0.48834086) -> 0x02e3 (0.72195559) | LUT[0501] 0x0fa8 (0.48931754) -> 0x02e3 (0.72261156)
0x02e502e4, // LUT[0502] 0x0fb0 (0.49029423) -> 0x02e4 (0.72326681) | LUT[0503] 0x0fb8 (0.49127091) -> 0x02e5 (0.72392135)
0x02e602e5, // LUT[0504] 0x0fc0 (0.49224759) -> 0x02e5 (0.72457518) | LUT[0505] 0x0fc8 (0.49322427) -> 0x02e6 (0.72522830)
0x02e702e7, // LUT[0506] 0x0fd0 (0.49420095) -> 0x02e7 (0.72588072) | LUT[0507] 0x0fd8 (0.49517763) -> 0x02e7 (0.72653244)
0x02e902e8, // LUT[0508] 0x0fe0 (0.49615432) -> 0x02e8 (0.72718345) | LUT[0509] 0x0fe8 (0.49713100) -> 0x02e9 (0.72783377)
0x02ea02e9, // LUT[0510] 0x0ff0 (0.49810768) -> 0x02e9 (0.72848339) | LUT[0511] 0x0ff8 (0.49908436) -> 0x02ea (0.72913231)
0x02eb02eb, // LUT[0512] 0x1000 (0.50006104) -> 0x02eb (0.72978055) | LUT[0513] 0x1008 (0.50103772) -> 0x02eb (0.73042809)
0x02ed02ec, // LUT[0514] 0x1010 (0.50201441) -> 0x02ec (0.73107494) | LUT[0515] 0x1018 (0.50299109) -> 0x02ed (0.73172111)
0x02ee02ed, // LUT[0516] 0x1020 (0.50396777) -> 0x02ed (0.73236660) | LUT[0517] 0x1028 (0.50494445) -> 0x02ee (0.73301140)
0x02ef02ef, // LUT[0518] 0x1030 (0.50592113) -> 0x02ef (0.73365552) | LUT[0519] 0x1038 (0.50689781) -> 0x02ef (0.73429897)
0x02f102f0, // LUT[0520] 0x1040 (0.50787450) -> 0x02f0 (0.73494174) | LUT[0521] 0x1048 (0.50885118) -> 0x02f1 (0.73558383)
0x02f202f1, // LUT[0522] 0x1050 (0.50982786) -> 0x02f1 (0.73622525) | LUT[0523] 0x1058 (0.51080454) -> 0x02f2 (0.73686601)
0x02f302f2, // LUT[0524] 0x1060 (0.51178122) -> 0x02f2 (0.73750609) | LUT[0525] 0x1068 (0.51275791) -> 0x02f3 (0.73814551)
0x02f402f4, // LUT[0526] 0x1070 (0.51373459) -> 0x02f4 (0.73878427) | LUT[0527] 0x1078 (0.51471127) -> 0x02f4 (0.73942236)
0x02f602f5, // LUT[0528] 0x1080 (0.51568795) -> 0x02f5 (0.74005979) | LUT[0529] 0x1088 (0.51666463) -> 0x02f6 (0.74069657)
0x02f702f6, // LUT[0530] 0x1090 (0.51764131) -> 0x02f6 (0.74133269) | LUT[0531] 0x1098 (0.51861800) -> 0x02f7 (0.74196815)
0x02f802f8, // LUT[0532] 0x10a0 (0.51959468) -> 0x02f8 (0.74260296) | LUT[0533] 0x10a8 (0.52057136) -> 0x02f8 (0.74323713)
0x02fa02f9, // LUT[0534] 0x10b0 (0.52154804) -> 0x02f9 (0.74387064) | LUT[0535] 0x10b8 (0.52252472) -> 0x02fa (0.74450351)
0x02fb02fa, // LUT[0536] 0x10c0 (0.52350140) -> 0x02fa (0.74513573) | LUT[0537] 0x10c8 (0.52447809) -> 0x02fb (0.74576730)
0x02fc02fc, // LUT[0538] 0x10d0 (0.52545477) -> 0x02fc (0.74639824) | LUT[0539] 0x10d8 (0.52643145) -> 0x02fc (0.74702854)
0x02fd02fd, // LUT[0540] 0x10e0 (0.52740813) -> 0x02fd (0.74765820) | LUT[0541] 0x10e8 (0.52838481) -> 0x02fd (0.74828722)
0x02ff02fe, // LUT[0542] 0x10f0 (0.52936149) -> 0x02fe (0.74891561) | LUT[0543] 0x10f8 (0.53033818) -> 0x02ff (0.74954337)
0x030002ff, // LUT[0544] 0x1100 (0.53131486) -> 0x02ff (0.75017050) | LUT[0545] 0x1108 (0.53229154) -> 0x0300 (0.75079700)
0x03010301, // LUT[0546] 0x1110 (0.53326822) -> 0x0301 (0.75142287) | LUT[0547] 0x1118 (0.53424490) -> 0x0301 (0.75204812)
0x03030302, // LUT[0548] 0x1120 (0.53522158) -> 0x0302 (0.75267275) | LUT[0549] 0x1128 (0.53619827) -> 0x0303 (0.75329675)
0x03040303, // LUT[0550] 0x1130 (0.53717495) -> 0x0303 (0.75392013) | LUT[0551] 0x1138 (0.53815163) -> 0x0304 (0.75454290)
0x03050305, // LUT[0552] 0x1140 (0.53912831) -> 0x0305 (0.75516505) | LUT[0553] 0x1148 (0.54010499) -> 0x0305 (0.75578658)
0x03060306, // LUT[0554] 0x1150 (0.54108168) -> 0x0306 (0.75640751) | LUT[0555] 0x1158 (0.54205836) -> 0x0306 (0.75702782)
0x03080307, // LUT[0556] 0x1160 (0.54303504) -> 0x0307 (0.75764752) | LUT[0557] 0x1168 (0.54401172) -> 0x0308 (0.75826661)
0x03090308, // LUT[0558] 0x1170 (0.54498840) -> 0x0308 (0.75888510) | LUT[0559] 0x1178 (0.54596508) -> 0x0309 (0.75950299)
0x030a030a, // LUT[0560] 0x1180 (0.54694177) -> 0x030a (0.76012027) | LUT[0561] 0x1188 (0.54791845) -> 0x030a (0.76073695)
0x030b030b, // LUT[0562] 0x1190 (0.54889513) -> 0x030b (0.76135303) | LUT[0563] 0x1198 (0.54987181) -> 0x030b (0.76196851)
0x030d030c, // LUT[0564] 0x11a0 (0.55084849) -> 0x030c (0.76258340) | LUT[0565] 0x11a8 (0.55182517) -> 0x030d (0.76319769)
0x030e030d, // LUT[0566] 0x11b0 (0.55280186) -> 0x030d (0.76381139) | LUT[0567] 0x11b8 (0.55377854) -> 0x030e (0.76442450)
0x030f030f, // LUT[0568] 0x11c0 (0.55475522) -> 0x030f (0.76503702) | LUT[0569] 0x11c8 (0.55573190) -> 0x030f (0.76564896)
0x03110310, // LUT[0570] 0x11d0 (0.55670858) -> 0x0310 (0.76626030) | LUT[0571] 0x11d8 (0.55768526) -> 0x0311 (0.76687106)
0x03120311, // LUT[0572] 0x11e0 (0.55866195) -> 0x0311 (0.76748124) | LUT[0573] 0x11e8 (0.55963863) -> 0x0312 (0.76809084)
0x03130312, // LUT[0574] 0x11f0 (0.56061531) -> 0x0312 (0.76869985) | LUT[0575] 0x11f8 (0.56159199) -> 0x0313 (0.76930829)
0x03140314, // LUT[0576] 0x1200 (0.56256867) -> 0x0314 (0.76991615) | LUT[0577] 0x1208 (0.56354535) -> 0x0314 (0.77052343)
0x03150315, // LUT[0578] 0x1210 (0.56452204) -> 0x0315 (0.77113015) | LUT[0579] 0x1218 (0.56549872) -> 0x0315 (0.77173629)
0x03170316, // LUT[0580] 0x1220 (0.56647540) -> 0x0316 (0.77234185) | LUT[0581] 0x1228 (0.56745208) -> 0x0317 (0.77294685)
0x03180317, // LUT[0582] 0x1230 (0.56842876) -> 0x0317 (0.77355128) | LUT[0583] 0x1238 (0.56940545) -> 0x0318 (0.77415515)
0x03190319, // LUT[0584] 0x1240 (0.57038213) -> 0x0319 (0.77475845) | LUT[0585] 0x1248 (0.57135881) -> 0x0319 (0.77536119)
0x031a031a, // LUT[0586] 0x1250 (0.57233549) -> 0x031a (0.77596336) | LUT[0587] 0x1258 (0.57331217) -> 0x031a (0.77656498)
0x031c031b, // LUT[0588] 0x1260 (0.57428885) -> 0x031b (0.77716604) | LUT[0589] 0x1268 (0.57526554) -> 0x031c (0.77776653)
0x031d031c, // LUT[0590] 0x1270 (0.57624222) -> 0x031c (0.77836648) | LUT[0591] 0x1278 (0.57721890) -> 0x031d (0.77896587)
0x031e031d, // LUT[0592] 0x1280 (0.57819558) -> 0x031d (0.77956470) | LUT[0593] 0x1288 (0.57917226) -> 0x031e (0.78016299)
0x031f031f, // LUT[0594] 0x1290 (0.58014894) -> 0x031f (0.78076072) | LUT[0595] 0x1298 (0.58112563) -> 0x031f (0.78135791)
0x03210320, // LUT[0596] 0x12a0 (0.58210231) -> 0x0320 (0.78195455) | LUT[0597] 0x12a8 (0.58307899) -> 0x0321 (0.78255064)
0x03220321, // LUT[0598] 0x12b0 (0.58405567) -> 0x0321 (0.78314619) | LUT[0599] 0x12b8 (0.58503235) -> 0x0322 (0.78374119)
0x03230322, // LUT[0600] 0x12c0 (0.58600903) -> 0x0322 (0.78433566) | LUT[0601] 0x12c8 (0.58698572) -> 0x0323 (0.78492958)
0x03240324, // LUT[0602] 0x12d0 (0.58796240) -> 0x0324 (0.78552297) | LUT[0603] 0x12d8 (0.58893908) -> 0x0324 (0.78611581)
0x03250325, // LUT[0604] 0x12e0 (0.58991576) -> 0x0325 (0.78670813) | LUT[0605] 0x12e8 (0.59089244) -> 0x0325 (0.78729990)
0x03270326, // LUT[0606] 0x12f0 (0.59186912) -> 0x0326 (0.78789115) | LUT[0607] 0x12f8 (0.59284581) -> 0x0327 (0.78848186)
0x03280327, // LUT[0608] 0x1300 (0.59382249) -> 0x0327 (0.78907204) | LUT[0609] 0x1308 (0.59479917) -> 0x0328 (0.78966169)
0x03290328, // LUT[0610] 0x1310 (0.59577585) -> 0x0328 (0.79025082) | LUT[0611] 0x1318 (0.59675253) -> 0x0329 (0.79083941)
0x032a032a, // LUT[0612] 0x1320 (0.59772921) -> 0x032a (0.79142749) | LUT[0613] 0x1328 (0.59870590) -> 0x032a (0.79201503)
0x032b032b, // LUT[0614] 0x1330 (0.59968258) -> 0x032b (0.79260206) | LUT[0615] 0x1338 (0.60065926) -> 0x032b (0.79318856)
0x032d032c, // LUT[0616] 0x1340 (0.60163594) -> 0x032c (0.79377455) | LUT[0617] 0x1348 (0.60261262) -> 0x032d (0.79436001)
0x032e032d, // LUT[0618] 0x1350 (0.60358931) -> 0x032d (0.79494496) | LUT[0619] 0x1358 (0.60456599) -> 0x032e (0.79552940)
0x032f032e, // LUT[0620] 0x1360 (0.60554267) -> 0x032e (0.79611331) | LUT[0621] 0x1368 (0.60651935) -> 0x032f (0.79669672)
0x03300330, // LUT[0622] 0x1370 (0.60749603) -> 0x0330 (0.79727961) | LUT[0623] 0x1378 (0.60847271) -> 0x0330 (0.79786199)
0x03310331, // LUT[0624] 0x1380 (0.60944940) -> 0x0331 (0.79844386) | LUT[0625] 0x1388 (0.61042608) -> 0x0331 (0.79902523)
0x03330332, // LUT[0626] 0x1390 (0.61140276) -> 0x0332 (0.79960608) | LUT[0627] 0x1398 (0.61237944) -> 0x0333 (0.80018643)
0x03340333, // LUT[0628] 0x13a0 (0.61335612) -> 0x0333 (0.80076628) | LUT[0629] 0x13a8 (0.61433280) -> 0x0334 (0.80134562)
0x03350334, // LUT[0630] 0x13b0 (0.61530949) -> 0x0334 (0.80192446) | LUT[0631] 0x13b8 (0.61628617) -> 0x0335 (0.80250280)
0x03360336, // LUT[0632] 0x13c0 (0.61726285) -> 0x0336 (0.80308064) | LUT[0633] 0x13c8 (0.61823953) -> 0x0336 (0.80365798)
0x03370337, // LUT[0634] 0x13d0 (0.61921621) -> 0x0337 (0.80423482) | LUT[0635] 0x13d8 (0.62019289) -> 0x0337 (0.80481117)
0x03380338, // LUT[0636] 0x13e0 (0.62116958) -> 0x0338 (0.80538702) | LUT[0637] 0x13e8 (0.62214626) -> 0x0338 (0.80596238)
0x033a0339, // LUT[0638] 0x13f0 (0.62312294) -> 0x0339 (0.80653724) | LUT[0639] 0x13f8 (0.62409962) -> 0x033a (0.80711162)
0x033b033a, // LUT[0640] 0x1400 (0.62507630) -> 0x033a (0.80768550) | LUT[0641] 0x1408 (0.62605298) -> 0x033b (0.80825890)
0x033c033b, // LUT[0642] 0x1410 (0.62702967) -> 0x033b (0.80883181) | LUT[0643] 0x1418 (0.62800635) -> 0x033c (0.80940423)
0x033d033d, // LUT[0644] 0x1420 (0.62898303) -> 0x033d (0.80997617) | LUT[0645] 0x1428 (0.62995971) -> 0x033d (0.81054762)
0x033e033e, // LUT[0646] 0x1430 (0.63093639) -> 0x033e (0.81111859) | LUT[0647] 0x1438 (0.63191308) -> 0x033e (0.81168908)
0x0340033f, // LUT[0648] 0x1440 (0.63288976) -> 0x033f (0.81225908) | LUT[0649] 0x1448 (0.63386644) -> 0x0340 (0.81282861)
0x03410340, // LUT[0650] 0x1450 (0.63484312) -> 0x0340 (0.81339766) | LUT[0651] 0x1458 (0.63581980) -> 0x0341 (0.81396623)
0x03420341, // LUT[0652] 0x1460 (0.63679648) -> 0x0341 (0.81453432) | LUT[0653] 0x1468 (0.63777317) -> 0x0342 (0.81510194)
0x03430342, // LUT[0654] 0x1470 (0.63874985) -> 0x0342 (0.81566909) | LUT[0655] 0x1478 (0.63972653) -> 0x0343 (0.81623576)
0x03440344, // LUT[0656] 0x1480 (0.64070321) -> 0x0344 (0.81680196) | LUT[0657] 0x1488 (0.64167989) -> 0x0344 (0.81736769)
0x03450345, // LUT[0658] 0x1490 (0.64265657) -> 0x0345 (0.81793296) | LUT[0659] 0x1498 (0.64363326) -> 0x0345 (0.81849775)
0x03460346, // LUT[0660] 0x14a0 (0.64460994) -> 0x0346 (0.81906207) | LUT[0661] 0x14a8 (0.64558662) -> 0x0346 (0.81962593)
0x03480347, // LUT[0662] 0x14b0 (0.64656330) -> 0x0347 (0.82018933) | LUT[0663] 0x14b8 (0.64753998) -> 0x0348 (0.82075226)
0x03490348, // LUT[0664] 0x14c0 (0.64851666) -> 0x0348 (0.82131473) | LUT[0665] 0x14c8 (0.64949335) -> 0x0349 (0.82187673)
0x034a0349, // LUT[0666] 0x14d0 (0.65047003) -> 0x0349 (0.82243828) | LUT[0667] 0x14d8 (0.65144671) -> 0x034a (0.82299936)
0x034b034b, // LUT[0668] 0x14e0 (0.65242339) -> 0x034b (0.82355999) | LUT[0669] 0x14e8 (0.65340007) -> 0x034b (0.82412016)
0x034c034c, // LUT[0670] 0x14f0 (0.65437675) -> 0x034c (0.82467987) | LUT[0671] 0x14f8 (0.65535344) -> 0x034c (0.82523912)
0x034d034d, // LUT[0672] 0x1500 (0.65633012) -> 0x034d (0.82579793) | LUT[0673] 0x1508 (0.65730680) -> 0x034d (0.82635628)
0x034f034e, // LUT[0674] 0x1510 (0.65828348) -> 0x034e (0.82691417) | LUT[0675] 0x1518 (0.65926016) -> 0x034f (0.82747162)
0x0350034f, // LUT[0676] 0x1520 (0.66023685) -> 0x034f (0.82802861) | LUT[0677] 0x1528 (0.66121353) -> 0x0350 (0.82858516)
0x03510350, // LUT[0678] 0x1530 (0.66219021) -> 0x0350 (0.82914126) | LUT[0679] 0x1538 (0.66316689) -> 0x0351 (0.82969691)
0x03520351, // LUT[0680] 0x1540 (0.66414357) -> 0x0351 (0.83025211) | LUT[0681] 0x1548 (0.66512025) -> 0x0352 (0.83080687)
0x03530352, // LUT[0682] 0x1550 (0.66609694) -> 0x0352 (0.83136118) | LUT[0683] 0x1558 (0.66707362) -> 0x0353 (0.83191506)
0x03540354, // LUT[0684] 0x1560 (0.66805030) -> 0x0354 (0.83246848) | LUT[0685] 0x1568 (0.66902698) -> 0x0354 (0.83302147)
0x03550355, // LUT[0686] 0x1570 (0.67000366) -> 0x0355 (0.83357402) | LUT[0687] 0x1578 (0.67098034) -> 0x0355 (0.83412613)
0x03560356, // LUT[0688] 0x1580 (0.67195703) -> 0x0356 (0.83467780) | LUT[0689] 0x1588 (0.67293371) -> 0x0356 (0.83522903)
0x03580357, // LUT[0690] 0x1590 (0.67391039) -> 0x0357 (0.83577983) | LUT[0691] 0x1598 (0.67488707) -> 0x0358 (0.83633019)
0x03590358, // LUT[0692] 0x15a0 (0.67586375) -> 0x0358 (0.83688012) | LUT[0693] 0x15a8 (0.67684043) -> 0x0359 (0.83742962)
0x035a0359, // LUT[0694] 0x15b0 (0.67781712) -> 0x0359 (0.83797868) | LUT[0695] 0x15b8 (0.67879380) -> 0x035a (0.83852731)
0x035b035a, // LUT[0696] 0x15c0 (0.67977048) -> 0x035a (0.83907551) | LUT[0697] 0x15c8 (0.68074716) -> 0x035b (0.83962328)
0x035c035b, // LUT[0698] 0x15d0 (0.68172384) -> 0x035b (0.84017062) | LUT[0699] 0x15d8 (0.68270052) -> 0x035c (0.84071754)
0x035d035d, // LUT[0700] 0x15e0 (0.68367721) -> 0x035d (0.84126403) | LUT[0701] 0x15e8 (0.68465389) -> 0x035d (0.84181009)
0x035e035e, // LUT[0702] 0x15f0 (0.68563057) -> 0x035e (0.84235573) | LUT[0703] 0x15f8 (0.68660725) -> 0x035e (0.84290094)
0x035f035f, // LUT[0704] 0x1600 (0.68758393) -> 0x035f (0.84344573) | LUT[0705] 0x1608 (0.68856062) -> 0x035f (0.84399010)
0x03610360, // LUT[0706] 0x1610 (0.68953730) -> 0x0360 (0.84453405) | LUT[0707] 0x1618 (0.69051398) -> 0x0361 (0.84507758)
0x03620361, // LUT[0708] 0x1620 (0.69149066) -> 0x0361 (0.84562069) | LUT[0709] 0x1628 (0.69246734) -> 0x0362 (0.84616338)
0x03630362, // LUT[0710] 0x1630 (0.69344402) -> 0x0362 (0.84670565) | LUT[0711] 0x1638 (0.69442071) -> 0x0363 (0.84724751)
0x03640363, // LUT[0712] 0x1640 (0.69539739) -> 0x0363 (0.84778895) | LUT[0713] 0x1648 (0.69637407) -> 0x0364 (0.84832998)
0x03650364, // LUT[0714] 0x1650 (0.69735075) -> 0x0364 (0.84887059) | LUT[0715] 0x1658 (0.69832743) -> 0x0365 (0.84941079)
0x03660365, // LUT[0716] 0x1660 (0.69930411) -> 0x0365 (0.84995058) | LUT[0717] 0x1668 (0.70028080) -> 0x0366 (0.85048996)
0x03670367, // LUT[0718] 0x1670 (0.70125748) -> 0x0367 (0.85102892) | LUT[0719] 0x1678 (0.70223416) -> 0x0367 (0.85156748)
0x03680368, // LUT[0720] 0x1680 (0.70321084) -> 0x0368 (0.85210563) | LUT[0721] 0x1688 (0.70418752) -> 0x0368 (0.85264337)
0x03690369, // LUT[0722] 0x1690 (0.70516420) -> 0x0369 (0.85318071) | LUT[0723] 0x1698 (0.70614089) -> 0x0369 (0.85371764)
0x036a036a, // LUT[0724] 0x16a0 (0.70711757) -> 0x036a (0.85425416) | LUT[0725] 0x16a8 (0.70809425) -> 0x036a (0.85479028)
0x036c036b, // LUT[0726] 0x16b0 (0.70907093) -> 0x036b (0.85532600) | LUT[0727] 0x16b8 (0.71004761) -> 0x036c (0.85586131)
0x036d036c, // LUT[0728] 0x16c0 (0.71102429) -> 0x036c (0.85639623) | LUT[0729] 0x16c8 (0.71200098) -> 0x036d (0.85693074)
0x036e036d, // LUT[0730] 0x16d0 (0.71297766) -> 0x036d (0.85746485) | LUT[0731] 0x16d8 (0.71395434) -> 0x036e (0.85799857)
0x036f036e, // LUT[0732] 0x16e0 (0.71493102) -> 0x036e (0.85853188) | LUT[0733] 0x16e8 (0.71590770) -> 0x036f (0.85906480)
0x0370036f, // LUT[0734] 0x16f0 (0.71688439) -> 0x036f (0.85959732) | LUT[0735] 0x16f8 (0.71786107) -> 0x0370 (0.86012945)
0x03710370, // LUT[0736] 0x1700 (0.71883775) -> 0x0370 (0.86066118) | LUT[0737] 0x1708 (0.71981443) -> 0x0371 (0.86119252)
0x03720372, // LUT[0738] 0x1710 (0.72079111) -> 0x0372 (0.86172347) | LUT[0739] 0x1718 (0.72176779) -> 0x0372 (0.86225402)
0x03730373, // LUT[0740] 0x1720 (0.72274448) -> 0x0373 (0.86278418) | LUT[0741] 0x1728 (0.72372116) -> 0x0373 (0.86331395)
0x03740374, // LUT[0742] 0x1730 (0.72469784) -> 0x0374 (0.86384333) | LUT[0743] 0x1738 (0.72567452) -> 0x0374 (0.86437232)
0x03750375, // LUT[0744] 0x1740 (0.72665120) -> 0x0375 (0.86490093) | LUT[0745] 0x1748 (0.72762788) -> 0x0375 (0.86542914)
0x03760376, // LUT[0746] 0x1750 (0.72860457) -> 0x0376 (0.86595697) | LUT[0747] 0x1758 (0.72958125) -> 0x0376 (0.86648442)
0x03770377, // LUT[0748] 0x1760 (0.73055793) -> 0x0377 (0.86701147) | LUT[0749] 0x1768 (0.73153461) -> 0x0377 (0.86753815)
0x03790378, // LUT[0750] 0x1770 (0.73251129) -> 0x0378 (0.86806444) | LUT[0751] 0x1778 (0.73348797) -> 0x0379 (0.86859035)
0x037a0379, // LUT[0752] 0x1780 (0.73446466) -> 0x0379 (0.86911587) | LUT[0753] 0x1788 (0.73544134) -> 0x037a (0.86964102)
0x037b037a, // LUT[0754] 0x1790 (0.73641802) -> 0x037a (0.87016579) | LUT[0755] 0x1798 (0.73739470) -> 0x037b (0.87069017)
0x037c037b, // LUT[0756] 0x17a0 (0.73837138) -> 0x037b (0.87121418) | LUT[0757] 0x17a8 (0.73934806) -> 0x037c (0.87173781)
0x037d037c, // LUT[0758] 0x17b0 (0.74032475) -> 0x037c (0.87226106) | LUT[0759] 0x17b8 (0.74130143) -> 0x037d (0.87278394)
0x037e037d, // LUT[0760] 0x17c0 (0.74227811) -> 0x037d (0.87330644) | LUT[0761] 0x17c8 (0.74325479) -> 0x037e (0.87382856)
0x037f037e, // LUT[0762] 0x17d0 (0.74423147) -> 0x037e (0.87435031) | LUT[0763] 0x17d8 (0.74520816) -> 0x037f (0.87487169)
0x03800380, // LUT[0764] 0x17e0 (0.74618484) -> 0x0380 (0.87539269) | LUT[0765] 0x17e8 (0.74716152) -> 0x0380 (0.87591333)
0x03810381, // LUT[0766] 0x17f0 (0.74813820) -> 0x0381 (0.87643359) | LUT[0767] 0x17f8 (0.74911488) -> 0x0381 (0.87695348)
0x03820382, // LUT[0768] 0x1800 (0.75009156) -> 0x0382 (0.87747300) | LUT[0769] 0x1808 (0.75106825) -> 0x0382 (0.87799216)
0x03830383, // LUT[0770] 0x1810 (0.75204493) -> 0x0383 (0.87851094) | LUT[0771] 0x1818 (0.75302161) -> 0x0383 (0.87902936)
0x03840384, // LUT[0772] 0x1820 (0.75399829) -> 0x0384 (0.87954741) | LUT[0773] 0x1828 (0.75497497) -> 0x0384 (0.88006510)
0x03850385, // LUT[0774] 0x1830 (0.75595165) -> 0x0385 (0.88058242) | LUT[0775] 0x1838 (0.75692834) -> 0x0385 (0.88109937)
0x03860386, // LUT[0776] 0x1840 (0.75790502) -> 0x0386 (0.88161597) | LUT[0777] 0x1848 (0.75888170) -> 0x0386 (0.88213219)
0x03870387, // LUT[0778] 0x1850 (0.75985838) -> 0x0387 (0.88264806) | LUT[0779] 0x1858 (0.76083506) -> 0x0387 (0.88316357)
0x03890388, // LUT[0780] 0x1860 (0.76181174) -> 0x0388 (0.88367871) | LUT[0781] 0x1868 (0.76278843) -> 0x0389 (0.88419350)
0x038a0389, // LUT[0782] 0x1870 (0.76376511) -> 0x0389 (0.88470792) | LUT[0783] 0x1878 (0.76474179) -> 0x038a (0.88522199)
0x038b038a, // LUT[0784] 0x1880 (0.76571847) -> 0x038a (0.88573570) | LUT[0785] 0x1888 (0.76669515) -> 0x038b (0.88624905)
0x038c038b, // LUT[0786] 0x1890 (0.76767183) -> 0x038b (0.88676204) | LUT[0787] 0x1898 (0.76864852) -> 0x038c (0.88727468)
0x038d038c, // LUT[0788] 0x18a0 (0.76962520) -> 0x038c (0.88778696) | LUT[0789] 0x18a8 (0.77060188) -> 0x038d (0.88829889)
0x038e038d, // LUT[0790] 0x18b0 (0.77157856) -> 0x038d (0.88881047) | LUT[0791] 0x18b8 (0.77255524) -> 0x038e (0.88932169)
0x038f038e, // LUT[0792] 0x18c0 (0.77353193) -> 0x038e (0.88983256) | LUT[0793] 0x18c8 (0.77450861) -> 0x038f (0.89034308)
0x0390038f, // LUT[0794] 0x18d0 (0.77548529) -> 0x038f (0.89085324) | LUT[0795] 0x18d8 (0.77646197) -> 0x0390 (0.89136306)
0x03910390, // LUT[0796] 0x18e0 (0.77743865) -> 0x0390 (0.89187253) | LUT[0797] 0x18e8 (0.77841533) -> 0x0391 (0.89238164)
0x03920391, // LUT[0798] 0x18f0 (0.77939202) -> 0x0391 (0.89289041) | LUT[0799] 0x18f8 (0.78036870) -> 0x0392 (0.89339884)
0x03930392, // LUT[0800] 0x1900 (0.78134538) -> 0x0392 (0.89390691) | LUT[0801] 0x1908 (0.78232206) -> 0x0393 (0.89441464)
0x03940394, // LUT[0802] 0x1910 (0.78329874) -> 0x0394 (0.89492202) | LUT[0803] 0x1918 (0.78427542) -> 0x0394 (0.89542906)
0x03950395, // LUT[0804] 0x1920 (0.78525211) -> 0x0395 (0.89593575) | LUT[0805] 0x1928 (0.78622879) -> 0x0395 (0.89644210)
0x03960396, // LUT[0806] 0x1930 (0.78720547) -> 0x0396 (0.89694811) | LUT[0807] 0x1938 (0.78818215) -> 0x0396 (0.89745378)
0x03970397, // LUT[0808] 0x1940 (0.78915883) -> 0x0397 (0.89795910) | LUT[0809] 0x1948 (0.79013551) -> 0x0397 (0.89846408)
0x03980398, // LUT[0810] 0x1950 (0.79111220) -> 0x0398 (0.89896872) | LUT[0811] 0x1958 (0.79208888) -> 0x0398 (0.89947302)
0x03990399, // LUT[0812] 0x1960 (0.79306556) -> 0x0399 (0.89997699) | LUT[0813] 0x1968 (0.79404224) -> 0x0399 (0.90048061)
0x039a039a, // LUT[0814] 0x1970 (0.79501892) -> 0x039a (0.90098390) | LUT[0815] 0x1978 (0.79599560) -> 0x039a (0.90148685)
0x039b039b, // LUT[0816] 0x1980 (0.79697229) -> 0x039b (0.90198946) | LUT[0817] 0x1988 (0.79794897) -> 0x039b (0.90249174)
0x039c039c, // LUT[0818] 0x1990 (0.79892565) -> 0x039c (0.90299368) | LUT[0819] 0x1998 (0.79990233) -> 0x039c (0.90349529)
0x039d039d, // LUT[0820] 0x19a0 (0.80087901) -> 0x039d (0.90399656) | LUT[0821] 0x19a8 (0.80185570) -> 0x039d (0.90449750)
0x039e039e, // LUT[0822] 0x19b0 (0.80283238) -> 0x039e (0.90499811) | LUT[0823] 0x19b8 (0.80380906) -> 0x039e (0.90549839)
0x039f039f, // LUT[0824] 0x19c0 (0.80478574) -> 0x039f (0.90599833) | LUT[0825] 0x19c8 (0.80576242) -> 0x039f (0.90649794)
0x03a003a0, // LUT[0826] 0x19d0 (0.80673910) -> 0x03a0 (0.90699723) | LUT[0827] 0x19d8 (0.80771579) -> 0x03a0 (0.90749618)
0x03a103a1, // LUT[0828] 0x19e0 (0.80869247) -> 0x03a1 (0.90799480) | LUT[0829] 0x19e8 (0.80966915) -> 0x03a1 (0.90849310)
0x03a203a2, // LUT[0830] 0x19f0 (0.81064583) -> 0x03a2 (0.90899107) | LUT[0831] 0x19f8 (0.81162251) -> 0x03a2 (0.90948871)
0x03a303a3, // LUT[0832] 0x1a00 (0.81259919) -> 0x03a3 (0.90998602) | LUT[0833] 0x1a08 (0.81357588) -> 0x03a3 (0.91048301)
0x03a403a4, // LUT[0834] 0x1a10 (0.81455256) -> 0x03a4 (0.91097967) | LUT[0835] 0x1a18 (0.81552924) -> 0x03a4 (0.91147601)
0x03a503a5, // LUT[0836] 0x1a20 (0.81650592) -> 0x03a5 (0.91197203) | LUT[0837] 0x1a28 (0.81748260) -> 0x03a5 (0.91246772)
0x03a603a6, // LUT[0838] 0x1a30 (0.81845928) -> 0x03a6 (0.91296309) | LUT[0839] 0x1a38 (0.81943597) -> 0x03a6 (0.91345813)
0x03a703a7, // LUT[0840] 0x1a40 (0.82041265) -> 0x03a7 (0.91395286) | LUT[0841] 0x1a48 (0.82138933) -> 0x03a7 (0.91444726)
0x03a803a8, // LUT[0842] 0x1a50 (0.82236601) -> 0x03a8 (0.91494134) | LUT[0843] 0x1a58 (0.82334269) -> 0x03a8 (0.91543510)
0x03a903a9, // LUT[0844] 0x1a60 (0.82431937) -> 0x03a9 (0.91592855) | LUT[0845] 0x1a68 (0.82529606) -> 0x03a9 (0.91642167)
0x03ab03aa, // LUT[0846] 0x1a70 (0.82627274) -> 0x03aa (0.91691448) | LUT[0847] 0x1a78 (0.82724942) -> 0x03ab (0.91740696)
0x03ac03ab, // LUT[0848] 0x1a80 (0.82822610) -> 0x03ab (0.91789914) | LUT[0849] 0x1a88 (0.82920278) -> 0x03ac (0.91839099)
0x03ad03ac, // LUT[0850] 0x1a90 (0.83017947) -> 0x03ac (0.91888253) | LUT[0851] 0x1a98 (0.83115615) -> 0x03ad (0.91937375)
0x03ae03ad, // LUT[0852] 0x1aa0 (0.83213283) -> 0x03ad (0.91986466) | LUT[0853] 0x1aa8 (0.83310951) -> 0x03ae (0.92035526)
0x03af03ae, // LUT[0854] 0x1ab0 (0.83408619) -> 0x03ae (0.92084554) | LUT[0855] 0x1ab8 (0.83506287) -> 0x03af (0.92133550)
0x03b003af, // LUT[0856] 0x1ac0 (0.83603956) -> 0x03af (0.92182516) | LUT[0857] 0x1ac8 (0.83701624) -> 0x03b0 (0.92231450)
0x03b103b0, // LUT[0858] 0x1ad0 (0.83799292) -> 0x03b0 (0.92280353) | LUT[0859] 0x1ad8 (0.83896960) -> 0x03b1 (0.92329226)
0x03b203b1, // LUT[0860] 0x1ae0 (0.83994628) -> 0x03b1 (0.92378067) | LUT[0861] 0x1ae8 (0.84092296) -> 0x03b2 (0.92426877)
0x03b303b2, // LUT[0862] 0x1af0 (0.84189965) -> 0x03b2 (0.92475656) | LUT[0863] 0x1af8 (0.84287633) -> 0x03b3 (0.92524404)
0x03b403b3, // LUT[0864] 0x1b00 (0.84385301) -> 0x03b3 (0.92573122) | LUT[0865] 0x1b08 (0.84482969) -> 0x03b4 (0.92621809)
0x03b503b4, // LUT[0866] 0x1b10 (0.84580637) -> 0x03b4 (0.92670465) | LUT[0867] 0x1b18 (0.84678305) -> 0x03b5 (0.92719091)
0x03b603b5, // LUT[0868] 0x1b20 (0.84775974) -> 0x03b5 (0.92767685) | LUT[0869] 0x1b28 (0.84873642) -> 0x03b6 (0.92816250)
0x03b703b6, // LUT[0870] 0x1b30 (0.84971310) -> 0x03b6 (0.92864784) | LUT[0871] 0x1b38 (0.85068978) -> 0x03b7 (0.92913287)
0x03b703b7, // LUT[0872] 0x1b40 (0.85166646) -> 0x03b7 (0.92961760) | LUT[0873] 0x1b48 (0.85264314) -> 0x03b7 (0.93010203)
0x03b803b8, // LUT[0874] 0x1b50 (0.85361983) -> 0x03b8 (0.93058616) | LUT[0875] 0x1b58 (0.85459651) -> 0x03b8 (0.93106998)
0x03b903b9, // LUT[0876] 0x1b60 (0.85557319) -> 0x03b9 (0.93155350) | LUT[0877] 0x1b68 (0.85654987) -> 0x03b9 (0.93203672)
0x03ba03ba, // LUT[0878] 0x1b70 (0.85752655) -> 0x03ba (0.93251964) | LUT[0879] 0x1b78 (0.85850324) -> 0x03ba (0.93300227)
0x03bb03bb, // LUT[0880] 0x1b80 (0.85947992) -> 0x03bb (0.93348459) | LUT[0881] 0x1b88 (0.86045660) -> 0x03bb (0.93396661)
0x03bc03bc, // LUT[0882] 0x1b90 (0.86143328) -> 0x03bc (0.93444833) | LUT[0883] 0x1b98 (0.86240996) -> 0x03bc (0.93492976)
0x03bd03bd, // LUT[0884] 0x1ba0 (0.86338664) -> 0x03bd (0.93541089) | LUT[0885] 0x1ba8 (0.86436333) -> 0x03bd (0.93589172)
0x03be03be, // LUT[0886] 0x1bb0 (0.86534001) -> 0x03be (0.93637226) | LUT[0887] 0x1bb8 (0.86631669) -> 0x03be (0.93685250)
0x03bf03bf, // LUT[0888] 0x1bc0 (0.86729337) -> 0x03bf (0.93733244) | LUT[0889] 0x1bc8 (0.86827005) -> 0x03bf (0.93781209)
0x03c003c0, // LUT[0890] 0x1bd0 (0.86924673) -> 0x03c0 (0.93829145) | LUT[0891] 0x1bd8 (0.87022342) -> 0x03c0 (0.93877051)
0x03c103c1, // LUT[0892] 0x1be0 (0.87120010) -> 0x03c1 (0.93924928) | LUT[0893] 0x1be8 (0.87217678) -> 0x03c1 (0.93972776)
0x03c203c2, // LUT[0894] 0x1bf0 (0.87315346) -> 0x03c2 (0.94020594) | LUT[0895] 0x1bf8 (0.87413014) -> 0x03c2 (0.94068383)
0x03c303c3, // LUT[0896] 0x1c00 (0.87510682) -> 0x03c3 (0.94116143) | LUT[0897] 0x1c08 (0.87608351) -> 0x03c3 (0.94163875)
0x03c403c4, // LUT[0898] 0x1c10 (0.87706019) -> 0x03c4 (0.94211577) | LUT[0899] 0x1c18 (0.87803687) -> 0x03c4 (0.94259250)
0x03c503c5, // LUT[0900] 0x1c20 (0.87901355) -> 0x03c5 (0.94306894) | LUT[0901] 0x1c28 (0.87999023) -> 0x03c5 (0.94354509)
0x03c603c6, // LUT[0902] 0x1c30 (0.88096691) -> 0x03c6 (0.94402096) | LUT[0903] 0x1c38 (0.88194360) -> 0x03c6 (0.94449653)
0x03c703c7, // LUT[0904] 0x1c40 (0.88292028) -> 0x03c7 (0.94497182) | LUT[0905] 0x1c48 (0.88389696) -> 0x03c7 (0.94544683)
0x03c803c8, // LUT[0906] 0x1c50 (0.88487364) -> 0x03c8 (0.94592155) | LUT[0907] 0x1c58 (0.88585032) -> 0x03c8 (0.94639598)
0x03c903c9, // LUT[0908] 0x1c60 (0.88682701) -> 0x03c9 (0.94687012) | LUT[0909] 0x1c68 (0.88780369) -> 0x03c9 (0.94734398)
0x03ca03ca, // LUT[0910] 0x1c70 (0.88878037) -> 0x03ca (0.94781756) | LUT[0911] 0x1c78 (0.88975705) -> 0x03ca (0.94829086)
0x03cb03cb, // LUT[0912] 0x1c80 (0.89073373) -> 0x03cb (0.94876387) | LUT[0913] 0x1c88 (0.89171041) -> 0x03cb (0.94923659)
0x03cc03cc, // LUT[0914] 0x1c90 (0.89268710) -> 0x03cc (0.94970904) | LUT[0915] 0x1c98 (0.89366378) -> 0x03cc (0.95018120)
0x03cd03cd, // LUT[0916] 0x1ca0 (0.89464046) -> 0x03cd (0.95065308) | LUT[0917] 0x1ca8 (0.89561714) -> 0x03cd (0.95112468)
0x03ce03cd, // LUT[0918] 0x1cb0 (0.89659382) -> 0x03cd (0.95159601) | LUT[0919] 0x1cb8 (0.89757050) -> 0x03ce (0.95206705)
0x03cf03ce, // LUT[0920] 0x1cc0 (0.89854719) -> 0x03ce (0.95253781) | LUT[0921] 0x1cc8 (0.89952387) -> 0x03cf (0.95300829)
0x03d003cf, // LUT[0922] 0x1cd0 (0.90050055) -> 0x03cf (0.95347849) | LUT[0923] 0x1cd8 (0.90147723) -> 0x03d0 (0.95394842)
0x03d103d0, // LUT[0924] 0x1ce0 (0.90245391) -> 0x03d0 (0.95441807) | LUT[0925] 0x1ce8 (0.90343059) -> 0x03d1 (0.95488744)
0x03d203d1, // LUT[0926] 0x1cf0 (0.90440728) -> 0x03d1 (0.95535653) | LUT[0927] 0x1cf8 (0.90538396) -> 0x03d2 (0.95582535)
0x03d303d2, // LUT[0928] 0x1d00 (0.90636064) -> 0x03d2 (0.95629389) | LUT[0929] 0x1d08 (0.90733732) -> 0x03d3 (0.95676216)
0x03d403d3, // LUT[0930] 0x1d10 (0.90831400) -> 0x03d3 (0.95723015) | LUT[0931] 0x1d18 (0.90929068) -> 0x03d4 (0.95769786)
0x03d503d4, // LUT[0932] 0x1d20 (0.91026737) -> 0x03d4 (0.95816531) | LUT[0933] 0x1d28 (0.91124405) -> 0x03d5 (0.95863248)
0x03d603d5, // LUT[0934] 0x1d30 (0.91222073) -> 0x03d5 (0.95909937) | LUT[0935] 0x1d38 (0.91319741) -> 0x03d6 (0.95956600)
0x03d703d6, // LUT[0936] 0x1d40 (0.91417409) -> 0x03d6 (0.96003235) | LUT[0937] 0x1d48 (0.91515078) -> 0x03d7 (0.96049843)
0x03d803d7, // LUT[0938] 0x1d50 (0.91612746) -> 0x03d7 (0.96096424) | LUT[0939] 0x1d58 (0.91710414) -> 0x03d8 (0.96142978)
0x03d803d8, // LUT[0940] 0x1d60 (0.91808082) -> 0x03d8 (0.96189505) | LUT[0941] 0x1d68 (0.91905750) -> 0x03d8 (0.96236005)
0x03d903d9, // LUT[0942] 0x1d70 (0.92003418) -> 0x03d9 (0.96282477) | LUT[0943] 0x1d78 (0.92101087) -> 0x03d9 (0.96328923)
0x03da03da, // LUT[0944] 0x1d80 (0.92198755) -> 0x03da (0.96375342) | LUT[0945] 0x1d88 (0.92296423) -> 0x03da (0.96421735)
0x03db03db, // LUT[0946] 0x1d90 (0.92394091) -> 0x03db (0.96468100) | LUT[0947] 0x1d98 (0.92491759) -> 0x03db (0.96514439)
0x03dc03dc, // LUT[0948] 0x1da0 (0.92589427) -> 0x03dc (0.96560751) | LUT[0949] 0x1da8 (0.92687096) -> 0x03dc (0.96607037)
0x03dd03dd, // LUT[0950] 0x1db0 (0.92784764) -> 0x03dd (0.96653296) | LUT[0951] 0x1db8 (0.92882432) -> 0x03dd (0.96699528)
0x03de03de, // LUT[0952] 0x1dc0 (0.92980100) -> 0x03de (0.96745734) | LUT[0953] 0x1dc8 (0.93077768) -> 0x03de (0.96791913)
0x03df03df, // LUT[0954] 0x1dd0 (0.93175436) -> 0x03df (0.96838066) | LUT[0955] 0x1dd8 (0.93273105) -> 0x03df (0.96884193)
0x03e003e0, // LUT[0956] 0x1de0 (0.93370773) -> 0x03e0 (0.96930293) | LUT[0957] 0x1de8 (0.93468441) -> 0x03e0 (0.96976367)
0x03e103e1, // LUT[0958] 0x1df0 (0.93566109) -> 0x03e1 (0.97022414) | LUT[0959] 0x1df8 (0.93663777) -> 0x03e1 (0.97068436)
0x03e203e1, // LUT[0960] 0x1e00 (0.93761445) -> 0x03e1 (0.97114431) | LUT[0961] 0x1e08 (0.93859114) -> 0x03e2 (0.97160400)
0x03e303e2, // LUT[0962] 0x1e10 (0.93956782) -> 0x03e2 (0.97206343) | LUT[0963] 0x1e18 (0.94054450) -> 0x03e3 (0.97252260)
0x03e403e3, // LUT[0964] 0x1e20 (0.94152118) -> 0x03e3 (0.97298151) | LUT[0965] 0x1e28 (0.94249786) -> 0x03e4 (0.97344016)
0x03e503e4, // LUT[0966] 0x1e30 (0.94347455) -> 0x03e4 (0.97389856) | LUT[0967] 0x1e38 (0.94445123) -> 0x03e5 (0.97435669)
0x03e603e5, // LUT[0968] 0x1e40 (0.94542791) -> 0x03e5 (0.97481456) | LUT[0969] 0x1e48 (0.94640459) -> 0x03e6 (0.97527218)
0x03e703e6, // LUT[0970] 0x1e50 (0.94738127) -> 0x03e6 (0.97572954) | LUT[0971] 0x1e58 (0.94835795) -> 0x03e7 (0.97618664)
0x03e803e7, // LUT[0972] 0x1e60 (0.94933464) -> 0x03e7 (0.97664348) | LUT[0973] 0x1e68 (0.95031132) -> 0x03e8 (0.97710007)
0x03e903e8, // LUT[0974] 0x1e70 (0.95128800) -> 0x03e8 (0.97755641) | LUT[0975] 0x1e78 (0.95226468) -> 0x03e9 (0.97801248)
0x03e903e9, // LUT[0976] 0x1e80 (0.95324136) -> 0x03e9 (0.97846831) | LUT[0977] 0x1e88 (0.95421804) -> 0x03e9 (0.97892387)
0x03ea03ea, // LUT[0978] 0x1e90 (0.95519473) -> 0x03ea (0.97937919) | LUT[0979] 0x1e98 (0.95617141) -> 0x03ea (0.97983425)
0x03eb03eb, // LUT[0980] 0x1ea0 (0.95714809) -> 0x03eb (0.98028905) | LUT[0981] 0x1ea8 (0.95812477) -> 0x03eb (0.98074361)
0x03ec03ec, // LUT[0982] 0x1eb0 (0.95910145) -> 0x03ec (0.98119791) | LUT[0983] 0x1eb8 (0.96007813) -> 0x03ec (0.98165196)
0x03ed03ed, // LUT[0984] 0x1ec0 (0.96105482) -> 0x03ed (0.98210575) | LUT[0985] 0x1ec8 (0.96203150) -> 0x03ed (0.98255930)
0x03ee03ee, // LUT[0986] 0x1ed0 (0.96300818) -> 0x03ee (0.98301259) | LUT[0987] 0x1ed8 (0.96398486) -> 0x03ee (0.98346563)
0x03ef03ef, // LUT[0988] 0x1ee0 (0.96496154) -> 0x03ef (0.98391843) | LUT[0989] 0x1ee8 (0.96593822) -> 0x03ef (0.98437097)
0x03f003ef, // LUT[0990] 0x1ef0 (0.96691491) -> 0x03ef (0.98482326) | LUT[0991] 0x1ef8 (0.96789159) -> 0x03f0 (0.98527531)
0x03f103f0, // LUT[0992] 0x1f00 (0.96886827) -> 0x03f0 (0.98572710) | LUT[0993] 0x1f08 (0.96984495) -> 0x03f1 (0.98617865)
0x03f203f1, // LUT[0994] 0x1f10 (0.97082163) -> 0x03f1 (0.98662995) | LUT[0995] 0x1f18 (0.97179832) -> 0x03f2 (0.98708100)
0x03f303f2, // LUT[0996] 0x1f20 (0.97277500) -> 0x03f2 (0.98753180) | LUT[0997] 0x1f28 (0.97375168) -> 0x03f3 (0.98798236)
0x03f403f3, // LUT[0998] 0x1f30 (0.97472836) -> 0x03f3 (0.98843267) | LUT[0999] 0x1f38 (0.97570504) -> 0x03f4 (0.98888274)
0x03f503f4, // LUT[1000] 0x1f40 (0.97668172) -> 0x03f4 (0.98933256) | LUT[1001] 0x1f48 (0.97765841) -> 0x03f5 (0.98978213)
0x03f503f5, // LUT[1002] 0x1f50 (0.97863509) -> 0x03f5 (0.99023146) | LUT[1003] 0x1f58 (0.97961177) -> 0x03f5 (0.99068054)
0x03f603f6, // LUT[1004] 0x1f60 (0.98058845) -> 0x03f6 (0.99112938) | LUT[1005] 0x1f68 (0.98156513) -> 0x03f6 (0.99157798)
0x03f703f7, // LUT[1006] 0x1f70 (0.98254181) -> 0x03f7 (0.99202633) | LUT[1007] 0x1f78 (0.98351850) -> 0x03f7 (0.99247444)
0x03f803f8, // LUT[1008] 0x1f80 (0.98449518) -> 0x03f8 (0.99292231) | LUT[1009] 0x1f88 (0.98547186) -> 0x03f8 (0.99336994)
0x03f903f9, // LUT[1010] 0x1f90 (0.98644854) -> 0x03f9 (0.99381732) | LUT[1011] 0x1f98 (0.98742522) -> 0x03f9 (0.99426446)
0x03fa03fa, // LUT[1012] 0x1fa0 (0.98840190) -> 0x03fa (0.99471136) | LUT[1013] 0x1fa8 (0.98937859) -> 0x03fa (0.99515802)
0x03fb03fb, // LUT[1014] 0x1fb0 (0.99035527) -> 0x03fb (0.99560444) | LUT[1015] 0x1fb8 (0.99133195) -> 0x03fb (0.99605062)
0x03fc03fb, // LUT[1016] 0x1fc0 (0.99230863) -> 0x03fb (0.99649656) | LUT[1017] 0x1fc8 (0.99328531) -> 0x03fc (0.99694226)
0x03fd03fc, // LUT[1018] 0x1fd0 (0.99426199) -> 0x03fc (0.99738772) | LUT[1019] 0x1fd8 (0.99523868) -> 0x03fd (0.99783294)
0x03fe03fd, // LUT[1020] 0x1fe0 (0.99621536) -> 0x03fd (0.99827793) | LUT[1021] 0x1fe8 (0.99719204) -> 0x03fe (0.99872268)
0x03ff03fe, // LUT[1022] 0x1ff0 (0.99816872) -> 0x03fe (0.99916718) | LUT[1023] 0x1ff8 (0.99914540) -> 0x03ff (0.99961146)
0x043703ff, // LUT[1024] 0x2000 (1.00012209) -> 0x03ff (1.00005549) | LUT[1025] 0x23ff (1.12501526) -> 0x0437 (1.05500332)
};
#endif
target/ipod6/include/target/gpiodef.h
+65
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/*
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_GPIODEF_H
#define __TARGET_GPIODEF_H
/* iPod6,x specific gpio -> pin mappings */
#include <platform/gpio.h>
/* BOARD_REV mapping */
#define BOARD_REV_DEV4 0x0e
#define BOARD_REV_PROTO2A 0x0e
#define BOARD_REV_PROTO2B 0x0d
#define BOARD_REV_PROTO2X_CARDINAL 0x0c
#define BOARD_REV_PROTO2B_ALT_CARBON 0x0b
#define BOARD_REV_PROTO2D 0x0a
#define BOARD_REV_PROTO2F 0x09
#define BOARD_REV_EVT 0x08
#define BOARD_REV_EVT_ALT_CARBON 0x07
#define BOARD_REV_DVTb_ALT_CARBON 0x06
#define BOARD_REV_DVTb_CARDINAL 0x05
#define BOARD_REV_PVT_OPA2376 0x03
extern uint32_t ipod6_get_board_rev();
/* define target-specific gpios in a generic fashion here. */
#define GPIO_ALT_BOOST_ID GPIOC(GPIO_AP, 5, 3) // GPIO11
#define GPIO_SPU_TO_OPAL_CS_L GPIOC(GPIO_SPU, 5, 1) // 41 : SPU_SPI_CS_TRIG[10] -> SCM_SPU_TO_OPAL_CS_L
/* which IICs to initialize */
#define IICS_MASK (3)
#define TRISTAR_IIC_BUS (0)
#define DISPLAY_PMU_IIC_BUS (1)
/* Miscellaneous Pins */
#define GPIO_PMU_LCD_RST (11)
#define PMU_LCD_PWR_VCI (5)
#define PMU_LCD_PWR_DVDD (0xe)
#define PMU_LDO_OPAL (0x8)
/*
* support of video or command mode
*/
extern bool product_target_is_display_in_video_mode();
extern uint32_t product_target_get_ulps_in_delay(void);
extern uint32_t product_target_get_ulps_end_delay(void);
extern uint32_t product_target_get_ulps_out_delay(void);
extern bool product_target_no_burst_mode();
#define TARGET_DISP_VIDEO_MODE product_target_is_display_in_video_mode()
#define TARGET_DSI_ULPS_IN_DELAY product_target_get_ulps_in_delay()
#define TARGET_DSI_ULPS_END_DELAY product_target_get_ulps_end_delay()
#define TARGET_DSI_ULPS_OUT_DELAY product_target_get_ulps_out_delay()
#define TARGET_NO_BURST_MODE product_target_no_burst_mode()
#endif /* ! __TARGET_GPIODEF_H */
target/ipod6/include/target/powerconfig.h
+76
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@@ -0,0 +1,76 @@
/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Computer, Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_POWERCONFIG_H
#define __TARGET_POWERCONFIG_H
/* configuration per target */
#define PMU_IIC_BUS 0
#define CHARGER_IIC_BUS 0
/* this configuration is very PMU specific and must be included exactly once in power.c */
#ifdef POWERCONFIG_PMU_SETUP
static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
{
};
static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
{
{ PMU_IIC_BUS, kD2238_BUCK2_VSEL, 0xc0 }, // <rdar://problem/18072042> M7 - Memory VDDQ and VDD2 Nominal Voltage
};
static const struct pmu_setup_struct pmu_warm_init[] =
{
};
static const struct pmu_setup_struct pmu_cold_init[] =
{
{ PMU_IIC_BUS, kD2238_ALL_RAILS_CONF, 0x00 }, // enable SOC_VDD_ALL_RAILS_ON processing
{ PMU_IIC_BUS, kD2238_GPIO14_CONF1, 0x93 }, // <rdar://problem/15821471> PMU register 0x041A needs to be changed to 0x93 during boot-up
{ PMU_IIC_BUS, kD2238_GPIO12_CONF1, 0x00 }, // Display needs to be in reset
{ PMU_IIC_BUS, kDIALOG_CHARGE_CONTROL_VSET, 0x3f }, // <rdar://problem/16344890> n27: PMU CV voltage needs to be changed from POR
{ PMU_IIC_BUS, kD2238_SLOT_TIMINGS_PWR_HALT_UP5, 0x0 }, // <rdar://problem/18457522> HALT to ACTIVE power sequence 7ms instead of 4ms
{ PMU_IIC_BUS, kD2238_SLOT_TIMINGS_PWR_HALT_UP6, 0x3 },
{ PMU_IIC_BUS, kD2238_BUCK2_VSEL_HALT, 0xB3 }, // <rdar://problem/18300732> M7 - Memory VDDQ and VDD2 Voltage changes to 1.16V in Halt/Hibernate
};
static const struct core_rails_struct soc_rails[] =
{
};
static const struct core_rails_struct cpu_rails[] =
{
};
static const struct core_rails_struct ram_rails[] =
{
};
#endif /* POWERCONFIG_PMU_SETUP */
#define NO_BATTERY_VOLTAGE 2700
#define MIN_BOOT_BATTERY_VOLTAGE 3600
#define TARGET_BOOT_BATTERY_VOLTAGE 3700
#define TARGET_BOOT_BATTERY_CAPACITY 0 // rely on SOCF flag only
#define TARGET_PRECHARGE_GG_FLAG_MASK kHDQRegFlagsMaskSOCF
#define PRECHARGE_BACKLIGHT_LEVEL 517
#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
#define TARGET_FORCE_DEBUG_PRECHARGE 1 // always precharge if "debug" precharge bit set
#define TARGET_CHARGER_HEADROOM 150
#define TARGET_CHARGER_MAX_VRECT 7500
#define TARGET_CHARGER_NEEDS_MAX_VRECT(rem_cap, max_cap) (((rem_cap) * 1000) <= ((max_cap) * 15)) /* 1.5% or lower */
#define ACC_PWR_LDO (0) // ACC_PWR not connected
#endif
target/ipod6/include/target/uartconfig.h
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/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_UARTCONFIG_H
#define __TARGET_UARTCONFIG_H
/* define one debug serial ports */
#define DEBUG_SERIAL_PORT (0)
#define HDQGAUGE_SERIAL_PORT (3)
#if SUPPORT_FPGA
#define UART_OVERSAMPLE_OVERRIDE (11)
#endif
#endif
target/ipod6/init.c
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/*
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <debug.h>
#include <drivers/display.h>
#if WITH_HW_DISPLAY_PMU
#include <drivers/display_pmu.h>
#endif
#include <drivers/flash_nor.h>
#include <drivers/iic.h>
#include <drivers/power.h>
#include <lib/devicetree.h>
#include <lib/env.h>
#include <lib/mib.h>
#include <lib/paint.h>
#include <lib/syscfg.h>
#include <platform.h>
#include <platform/chipid.h>
#include <platform/gpio.h>
#include <platform/gpiodef.h>
#include <platform/memmap.h>
#include <platform/soc/hwregbase.h>
#include <platform/soc/pmgr.h>
#include <sys.h>
#include <sys/boot.h>
#include <sys/menu.h>
#include <sys/task.h>
#include <target.h>
#include "init_fpga.h"
#include "init_product.h"
#include "init_sim.h"
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
void target_early_init(void)
{
#if !CONFIG_FPGA && !CONFIG_SIM
product_target_early_init();
#endif
}
void target_late_init(void)
{
#if !CONFIG_FPGA && !CONFIG_SIM
product_target_late_init();
#endif
}
void target_init(void)
{
#if WITH_HW_FLASH_NOR
flash_nor_init(SPI_NOR0);
#endif
}
void target_quiesce_hardware(void)
{
}
void target_poweroff(void)
{
}
int target_bootprep(enum boot_target target)
{
return 0;
}
bool target_should_recover(void)
{
#if CONFIG_SIM
return sim_target_should_recover();
#elif CONFIG_FPGA
return fpga_target_should_recover();
#else
return product_target_should_recover();
#endif
}
bool target_should_poweron(bool *cold_button_boot)
{
#if CONFIG_SIM
return sim_target_should_poweron(cold_button_boot);
#elif CONFIG_FPGA
return fpga_target_should_poweron(cold_button_boot);
#else
return product_target_should_poweron(cold_button_boot);
#endif
}
bool target_should_poweroff(bool at_boot)
{
#if CONFIG_SIM
return sim_target_should_poweroff(at_boot);
#elif CONFIG_FPGA
return fpga_target_should_poweroff(at_boot);
#else
return product_target_should_poweroff(at_boot);
#endif
}
#if WITH_ENV
void target_setup_default_environment(void)
{
#if CONFIG_SIM
sim_target_setup_default_environment();
#elif CONFIG_FPGA
fpga_target_setup_default_environment();
#else
product_target_setup_default_environment();
#endif
}
#endif // WITH_ENV
#if WITH_DEVICETREE
int target_update_device_tree(void)
{
#if CONFIG_SIM
return sim_target_update_device_tree();
#elif CONFIG_FPGA
return fpga_target_update_device_tree();
#else
return product_target_update_device_tree();
#endif
}
#endif // WITH_DEVICETREE
target/ipod6/init_fpga.c
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/*
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <debug.h>
#include <drivers/flash_nor.h>
#include <lib/devicetree.h>
#include <lib/env.h>
#include <lib/mib.h>
#include <platform.h>
#include <platform/gpiodef.h>
#include <platform/memmap.h>
#include <sys.h>
#include <sys/menu.h>
#include <sys/task.h>
#include <target.h>
bool fpga_target_should_recover(void)
{
return false;
}
bool fpga_target_should_poweron(bool *cold_button_boot)
{
*cold_button_boot = true;
return true;
}
bool fpga_target_should_poweroff(bool at_boot)
{
return false;
}
#if !PRODUCT_LLB
bool target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
{
return false;
}
#endif
#if WITH_ENV
void fpga_target_setup_default_environment(void)
{
env_set("boot-args", " debug=0x14e serial=3 amfi_unrestrict_task_for_pid=1 amfi_allow_any_signature=1 amfi_get_out_of_my_way=1 cs_enforcement_disable=1 no-dockfifo-uart=1", 0);
env_set("boot-device", "asp_nand", 0);
env_set("display-color-space","RGB888", 0);
env_set("display-timing", "fpga-wsvga", 0); /* defaults to no display support */
env_set("ramdisk-delay", "180000000", 0); /* This tells PurpleRestore to slow down; rdar://6345846 */
env_set("idle-off", "false", 0);
env_set("bootdelay", "3", 0);
env_set("debug-uarts", "3", 0);
}
#endif
#if WITH_DEVICETREE
int fpga_target_update_device_tree(void)
{
return 0;
}
#endif
bool target_do_chargetrap(void)
{
return false;
}
bool target_needs_chargetrap(void)
{
return false;
}
#if !WITH_HW_POWER
bool power_needs_thermal_trap(void)
{
return false;
}
bool power_needs_precharge(void)
{
return false;
}
void power_cancel_buttonwait(void)
{
}
bool power_do_chargetrap(void)
{
return false;
}
bool power_is_suspended(void)
{
return false;
}
void power_will_resume(void)
{
}
bool power_has_usb(void)
{
return false;
}
int power_read_dock_id(unsigned *id)
{
return -1;
}
bool power_get_diags_dock(void)
{
return false;
}
u_int32_t power_get_boot_battery_level(void)
{
return 0;
}
int power_get_nvram(u_int8_t key, u_int8_t *data)
{
return -1;
}
int power_set_nvram(u_int8_t key, u_int8_t data)
{
return -1;
}
int power_set_soc_voltage(unsigned mv, int override)
{
return -1;
}
bool force_usb_power = false;
void power_set_usb_state(bool configured, bool suspended)
{
}
int power_backlight_enable(u_int32_t backlight_level)
{
return 0;
}
#endif /* ! WITH_HW_POWER */
target/ipod6/init_fpga.h
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/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef _TARGET_INIT_FPGA_H
#define _TARGET_INIT_FPGA_H
bool fpga_target_should_recover(void);
bool fpga_target_should_poweron(bool *cold_button_boot);
bool fpga_target_should_poweroff(bool at_boot);
void fpga_target_setup_default_environment(void);
int fpga_target_update_device_tree(void);
#endif /* ! _TARGET_INIT_FPGA_H */
target/ipod6/init_product.c
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target/ipod6/init_product.h
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/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef _TARGET_INIT_PRODUCT_H
#define _TARGET_INIT_PRODUCT_H
bool product_target_should_recover(void);
bool product_target_should_poweron(bool *cold_button_boot);
bool product_target_should_poweroff(bool at_boot);
void product_target_early_init(void);
void product_target_late_init(void);
void product_target_setup_default_environment(void);
int product_target_update_device_tree(void);
#endif /* ! _TARGET_INIT_PRODUCT_H */
target/ipod6/init_sim.c
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/*
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <debug.h>
#include <drivers/flash_nor.h>
#include <lib/devicetree.h>
#include <lib/env.h>
#include <lib/mib.h>
#include <platform.h>
#include <platform/gpiodef.h>
#include <platform/memmap.h>
#include <sys.h>
#include <sys/menu.h>
#include <sys/task.h>
#include <target.h>
bool sim_target_should_recover(void)
{
return false;
}
bool sim_target_should_poweron(bool *cold_button_boot)
{
*cold_button_boot = true;
return true;
}
bool sim_target_should_poweroff(bool at_boot)
{
return false;
}
#if !PRODUCT_LLB
bool target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
{
return false;
}
#endif
#if WITH_ENV
void sim_target_setup_default_environment(void)
{
env_set("boot-args", "debug=0x14e serial=3 amfi=0x83 cs_enforcement_disable=1 -disable_aslr", ENV_PERSISTENT);
env_set("boot-device", "asp_nand", 0);
env_set("display-color-space","RGB888", 0);
env_set("display-timing", "POR_DISP_B_VID", 0);
env_set("idle-off", "false", 0);
// env_set("kaslr-slide", "0x10000000", 0);
env_set("kaslr-off", "true", 0);
env_set("wifiaddr", "12:22:33:44:55:66", 0);
env_set("ethaddr", "12:22:33:44:55:77", 0);
env_set("btaddr", "00:00:00:00:00:00", 0);
}
#endif
bool product_target_is_display_in_video_mode(void)
{
return true;
}
#if WITH_DEVICETREE
#define ROOT_DTPATH ""
int sim_target_update_device_tree(void)
{
DTNode *node;
uint32_t propSize;
char *propName;
void *propData;
// Overwrite the serial-number with data from the simplertc fastsim model
if (FindNode(0, ROOT_DTPATH, &node)) {
propName = "serial-number";
if (FindProperty(node, &propName, &propData, &propSize)) {
if (propSize != 0x20) {
dprintf(DEBUG_CRITICAL, "serial-number property size 0x%x (expected 0x20)\n", propSize);
return -1;
}
uint64_t *serial = (uint64_t *)propData;
serial[0] = *(volatile uint64_t *)0x4a000040;
serial[1] = *(volatile uint64_t *)0x4a000048;
serial[2] = *(volatile uint64_t *)0x4a000050;
serial[3] = *(volatile uint64_t *)0x4a000058;
}
}
// Overwrite the region-info with data from the simplertc fastsim model
if (FindNode(0, ROOT_DTPATH, &node)) {
propName = "region-info";
if (FindProperty(node, &propName, &propData, &propSize)) {
if (propSize != 0x20) {
dprintf(DEBUG_CRITICAL, "region-info property size 0x%x (expected 0x20)\n", propSize);
return -1;
}
uint64_t *region = (uint64_t *)propData;
region[0] = *(volatile uint64_t *)0x4a000060;
region[1] = *(volatile uint64_t *)0x4a000068;
region[2] = *(volatile uint64_t *)0x4a000070;
region[3] = *(volatile uint64_t *)0x4a000078;
}
}
if (FindNode(0, "arm-io/spu/iop-spu-nub", &node)) {
propName = "AAPL,ignore";
if (FindProperty(node, &propName, &propData, &propSize)) {
propName[0] = '~';
}
}
return 0;
}
#endif
bool target_do_chargetrap(void)
{
return false;
}
bool target_needs_chargetrap(void)
{
return false;
}
#if !WITH_HW_POWER
bool power_needs_precharge(void)
{
return false;
}
bool power_needs_thermal_trap(void)
{
return false;
}
void power_cancel_buttonwait(void)
{
}
bool power_do_chargetrap(void)
{
return false;
}
bool power_is_suspended(void)
{
return false;
}
void power_will_resume(void)
{
}
bool power_has_usb(void)
{
return false;
}
int power_read_dock_id(unsigned *id)
{
return -1;
}
bool power_get_diags_dock(void)
{
return false;
}
u_int32_t power_get_boot_battery_level(void)
{
return 0;
}
int power_get_nvram(u_int8_t key, u_int8_t *data)
{
return -1;
}
int power_set_nvram(u_int8_t key, u_int8_t data)
{
return -1;
}
int power_set_soc_voltage(unsigned mv, int override)
{
return -1;
}
bool force_usb_power = false;
void power_set_usb_state(bool configured, bool suspended)
{
}
int power_backlight_enable(u_int32_t backlight_level)
{
return 0;
}
#endif /* ! WITH_HW_POWER */
target/ipod6/init_sim.h
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/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef _TARGET_INIT_SIM_H
#define _TARGET_INIT_SIM_H
bool sim_target_should_recover(void);
bool sim_target_should_poweron(bool *cold_button_boot);
bool sim_target_should_poweroff(bool at_boot);
void sim_target_setup_default_environment(void);
int sim_target_update_device_tree(void);
#endif /* ! _TARGET_INIT_SIM_H */
target/ipod6/pinconfig_evt.c
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/*
* Copyright (C) 2014-2015 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
I/O Spreadsheet version: rev 0.4.1
I/O Spreadsheet tracker: 15171729
Conversion command: csvtopinconfig.py --radar 15171729 --soc m7 --prefix evt --copyright 2014-2015 <filename>
*/
#include <debug.h>
#include <drivers/apple/gpio.h>
#include <platform.h>
#include <platform/soc/hwregbase.h>
#include <stdint.h>
static const uint32_t pinconfig_evt_ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // 0 : I2S0_MCK -> GPIO_AP_TO_BERMUDA_CLK_XTAL1
CFG_FUNC0 | SLOW_SLEW, // 1 : I2S1_MCK -> I2S1_AP_TO_CODEC_MCLK_12M
CFG_FUNC0 | SLOW_SLEW, // 2 : SD_CLKOUT -> SDIO_AP_TO_WLAN_CLK
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 3 : SD_CMD_IO -> SDIO_AP_BI_WLAN_CMD
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 4 : SD_DATA_IO[0] -> SDIO_AP_BI_WLAN_DATA0
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 5 : SD_DATA_IO[1] -> SDIO_AP_BI_WLAN_DATA1
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 6 : SD_DATA_IO[2] -> SDIO_AP_BI_WLAN_DATA2
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 7 : SD_DATA_IO[3] -> SDIO_AP_BI_WLAN_DATA3
/* Port 1 */
CFG_FUNC0 | INPUT_SCHMITT, // 8 : SDIO_IRQ -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 9 : WL_HOST_WAKE -> GPIO_WLAN_TO_AP_IRQ
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 2 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 3 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 4 */
CFG_DISABLED, // 32 : GPIO[0] -> NC_AP_GPIO0
CFG_DISABLED, // 33 : GPIO[1] -> NC_AP_GPIO1
CFG_DISABLED, // 34 : GPIO[2] -> GPIO_BOOT_CONFIG_0
CFG_DISABLED, // 35 : GPIO[3] -> PP1V8_SW3C_SNS
CFG_DISABLED, // 36 : GPIO[4] -> NC_GPIO_BOOT_CONFIG_2
CFG_DISABLED, // 37 : GPIO[5] -> NC_GPIO_BOOT_CONFIG_3
CFG_DISABLED, // 38 : GPIO[6] -> GPIO_BOARD_ID_3
CFG_DISABLED, // 39 : GPIO[7] -> GPIO_BOARD_REV_0
/* Port 5 */
CFG_DISABLED, // 40 : GPIO[8] -> GPIO_BOARD_REV_1
CFG_DISABLED, // 41 : GPIO[9] -> GPIO_BOARD_REV_2
CFG_DISABLED, // 42 : GPIO[10] -> GPIO_BOARD_REV_3
CFG_DISABLED, // 43 : GPIO[11] -> NC_GPIO_DEV_BOOST_ALT_ID
CFG_OUT_0 | SLOW_SLEW, // 44 : GPIO[12] -> GPIO_AP_TO_BT_DEVICE_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 45 : GPIO[13] -> GPIO_CODEC_TO_AP_IRQ_L
CFG_DISABLED, // 46 : GPIO[14] -> NC_AP_GPIO14
CFG_OUT_0 | SLOW_SLEW, // 47 : GPIO[15] -> GPIO_AP_TO_BERMUDA_FW_DWLD_REQ
/* Port 6 */
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 48 : I2C1_SDA -> I2C1_AP_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 49 : I2C1_SCL -> I2C1_AP_1V8_SCL
CFG_DISABLED, // 50 : I2S0_LRCK -> NC_I2S0_LRCLK
CFG_DISABLED, // 51 : I2S0_BCLK -> NC_I2S0_BCLK
CFG_DISABLED, // 52 : I2S0_DOUT -> NC_I2S0_DOUT
CFG_DISABLED, // 53 : I2S0_DIN -> NC_I2S0_DIN
CFG_FUNC0, // 54 : I2S1_LRCK -> I2S1_CODEC_TO_AP_WCLK
CFG_FUNC0, // 55 : I2S1_BCLK -> I2S1_CODEC_TO_AP_BCLK
/* Port 7 */
CFG_FUNC0 | SLOW_SLEW, // 56 : I2S1_DOUT -> I2S1_AP_TO_CODEC_DATA
CFG_FUNC0, // 57 : I2S1_DIN -> I2S1_CODEC_TO_AP_DATA
CFG_FUNC0 | SLOW_SLEW, // 58 : UART1_TXD -> UART1_AP_TO_BT_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 59 : UART1_RXD -> UART1_BT_TO_AP_RXD
CFG_FUNC0 | SLOW_SLEW, // 60 : UART1_RTSN -> UART1_AP_TO_BT_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 61 : UART1_CTSN -> UART1_BT_TO_AP_CTS_L
CFG_FUNC0 | SLOW_SLEW, // 62 : UART2_TXD -> UART2_AP_TO_BERMUDA_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 63 : UART2_RXD -> UART2_BERMUDA_TO_AP_RXD
/* Port 8 */
CFG_FUNC0 | SLOW_SLEW, // 64 : UART2_RTSN -> UART2_AP_TO_BERMUDA_RTS_L
CFG_DISABLED | INPUT_SCHMITT, // 65 : UART2_CTSN -> UART2_BERMUDA_TO_AP_CTS_L
CFG_FUNC0 | SLOW_SLEW, // 66 : UART4_TXD -> UART4_AP_TO_WLAN_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 67 : UART4_RXD -> UART4_WLAN_TO_AP_RXD
CFG_FUNC0 | SLOW_SLEW, // 68 : UART3_RTXD -> UART3_AP_BI_GG_SWI
CFG_DISABLED, // 69 : CLK32K_OUT -> NC_CLK32K_OUT
CFG_DISABLED, // 70 : TST_CLKOUT -> AP_TST_CLKOUT
CFG_OUT_0 | SLOW_SLEW, // 71 : GPIO[16] -> AP_TO_SEAJAY_I2C_SDA_ENABLE
/* Port 9 */
CFG_DISABLED, // 72 : GPIO[17] -> GPIO_AP_TO_BSYNC_RESET_EN_L
CFG_DISABLED, // 73 : GPIO[18] -> GPIO_GRAPE_SWDCLK
CFG_DISABLED, // 74 : TMR32_PWM1 -> NC_TMR32_PWM1
CFG_IN | INPUT_SCHMITT, // 75 : TMR32_PWM2 -> DISP_BSYNC
CFG_FUNC0, // 76 : TMR32_PWM0 -> PMU_VDD_OK
CFG_FUNC0 | INPUT_SCHMITT, // 77 : DISP_TE -> DISP_BSYNC
CFG_DISABLED, // 78 : GPIO[19] -> GPIO_GRAPE_SWDIO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 79 : NAND_CEN[0] -> ANC_AP_TO_NAND_CEN<0>
/* Port 10 */
CFG_DISABLED, // 80 : NAND_CEN[1] -> NC_NAND_CEN1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 81 : NAND_IO[7] -> ANC_AP_BI_NAND_IO<7>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 82 : NAND_IO[6] -> ANC_AP_BI_NAND_IO<6>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 83 : NAND_IO[5] -> ANC_AP_BI_NAND_IO<5>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 84 : NAND_IO[4] -> ANC_AP_BI_NAND_IO<4>
CFG_DISABLED, // 85 : NAND_DQS -> NC_NAND_DQS
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 86 : NAND_REN -> ANC_AP_TO_NAND_RE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 87 : NAND_IO[3] -> ANC_AP_BI_NAND_IO<3>
/* Port 11 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 88 : NAND_IO[2] -> ANC_AP_BI_NAND_IO<2>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 89 : NAND_IO[1] -> ANC_AP_BI_NAND_IO<1>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 90 : NAND_IO[0] -> ANC_AP_BI_NAND_IO<0>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 91 : NAND_WEN -> ANC_AP_TO_NAND_WE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 92 : NAND_CLE -> ANC_AP_TO_NAND_CLE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 93 : NAND_ALE -> ANC_AP_TO_NAND_ALE
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 94 : I2C0_SDA -> I2C0_AP_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 95 : I2C0_SCL -> I2C0_AP_1V8_SCL
/* Port 12 */
CFG_DISABLED, // 96 : DISP_VSYNC -> NC_DISP_VSYNC
CFG_DISABLED, // 97 : SPI0_SCLK -> NC_GPIO_BOARD_ID_0
CFG_DISABLED, // 98 : SPI0_MOSI -> GPIO_BOARD_ID_1
CFG_DISABLED, // 99 : SPI0_MISO -> GPIO_BOARD_ID_2
CFG_DISABLED, // 100 : SPI0_SSIN -> NC_SPI0_MCK
CFG_FUNC0 | SLOW_SLEW, // 101 : UART0_TXD -> UART0_TXD
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 102 : UART0_RXD -> UART0_RXD
CFG_DISABLED, // 103 : SPI1_SCLK -> NC_SPI1_SCLK
/* Port 13 */
CFG_DISABLED, // 104 : SPI1_MOSI -> NC_SPI1_MOSI
CFG_DISABLED, // 105 : SPI1_MISO -> NC_SPI1_MISO
CFG_DISABLED, // 106 : SPI1_SSIN -> NC_SPI1_SSIN
CFG_DISABLED, // 107 : GPIO[20] -> NC_AP_GPIO20
CFG_OUT_0 | SLOW_SLEW, // 108 : GPIO[21] -> GPIO_AP_TO_WLAN_DEVICE_WAKE
CFG_IN | INPUT_SCHMITT, // 109 : GPIO[22] -> GPIO_TRISTAR_INT
CFG_DISABLED, // 110 : GPIO[23] -> GPIO_AP_TO_OPAL_LVBOOST_BUSY_L
CFG_IN, // 111 : GPIO[24] -> GPIO_OPAL_SWDIO
/* Port 14 */
CFG_IN, // 112 : GPIO[25] -> GPIO_OPAL_SWDCLK
CFG_DISABLED, // 113 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 114 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 115 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 116 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 117 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 118 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 119 : UNSPECIFIED -> UNSPECIFIED
/* Port 15 */
CFG_DISABLED, // 120 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 121 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 122 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 123 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
/* Port 16 */
CFG_DISABLED, // 128 : ENET_MDC -> NC_ENET_MDC
CFG_DISABLED, // 129 : ENET_MDIO -> NC_ENET_MDIO
CFG_DISABLED, // 130 : RMII_RXER -> GPIO_AP_TO_ORB_DEBUG
CFG_DISABLED, // 131 : RMII_TXEN -> NC_RMII_TXEN
CFG_DISABLED, // 132 : RMII_CLK -> NC_GPIO_DEV_DISPLAY_TO_AP_ID3
CFG_DISABLED, // 133 : RMII_TXD[0] -> NC_RMII_TXD0
CFG_DISABLED, // 134 : RMII_TXD[1] -> NC_FPGA_WL_REG_ON
CFG_DISABLED, // 135 : RMII_RXD[0] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID1
/* Port 17 */
CFG_DISABLED, // 136 : RMII_RXD[1] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID2
CFG_DISABLED, // 137 : RMII_CRSDV -> NC_GPIO_DEV_DISPLAY_TO_AP_ID0
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_evt_ap_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_IN | INPUT_SCHMITT, // 0 : REQUEST_DFU1 -> BUTTON1_BUFF_L
CFG_IN | INPUT_SCHMITT, // 1 : REQUEST_DFU2 -> LISA_BTN_BUFF_L
CFG_FUNC0 | INPUT_SCHMITT, // 2 : DOCK_CONNECT -> DOCK_CONNECT
CFG_DISABLED, // 3 : UNSPECIFIED -> UNSPECIFIED
CFG_OUT_0 | SLOW_SLEW, // 4 : SPU_UART0_TXD -> GPIO_SPU_TO_WLAN_CONTEXT_B
CFG_OUT_0 | SLOW_SLEW, // 5 : SPU_UART0_RXD -> GPIO_SPU_TO_WLAN_CONTEXT_A
CFG_DISABLED, // 6 : SPU_UART0_RTSN -> NC_SPU_UART0_RTSN
CFG_DISABLED, // 7 : SPU_UART0_CTSN -> NC_SPU_UART0_CTSN
/* Port 1 */
CFG_DISABLED, // 8 : SPU_UART1_TXD -> NC_SPU_UART1_TXD
CFG_DISABLED, // 9 : SPU_UART1_RXD -> NC_SPU_UART1_RXD
CFG_DISABLED, // 10 : SPU_UART1_RTSN -> NC_SPU_UART1_RTSN
CFG_DISABLED, // 11 : SPU_UART1_CTSN -> NC_SPU_UART1_CTSN
CFG_DISABLED, // 12 : SPU_GPIO[0] -> NC_SPU_GPIO0
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 13 : SPU_GPIO[1] -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_IN | INPUT_SCHMITT, // 14 : SPU_GPIO[2] -> GPIO_BT_TO_SPU_HOST_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 15 : SPU_GPIO[3] -> GPIO_SUNFISH_TO_SPU_INT_L
/* Port 2 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 16 : SPU_GPIO[4] -> GPIO_PMU_TO_SPU_IRQ_L
CFG_OUT_0 | SLOW_SLEW, // 17 : SPU_GPIO[5] -> GPIO_AP_TO_SEAJAY_RESET
CFG_OUT_0 | SLOW_SLEW, // 18 : SPU_GPIO[6] -> GPIO_SPU_TO_LVBOOST_EN
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 19 : SPU_GPIO[7] -> GPIO_BERMUDA_TO_SPU_HOST_WAKE
CFG_DISABLED, // 20 : SPU_GPIO[8] -> NC_SPU_GPIO8
CFG_OUT_0, // 21 : DFU_STATUS -> TP_DFU_STATUS
CFG_IN | PULL_DOWN, // 22 : FORCE_DFU -> TP_FORCE_DFU
CFG_FUNC0 | INPUT_SCHMITT, // 23 : PWR_GOOD -> PMU_TO_SPU_PWR_GOOD
/* Port 3 */
CFG_FUNC0 | SLOW_SLEW, // 24 : SOC_VDD_HI_LO -> SPU_TO_PMU_VDD_HI_LO
CFG_DISABLED, // 25 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 26 : DOCK_ATTENTION -> NC_DOCK_ATTENTION
CFG_DISABLED, // 27 : PMU_HOST_WAKE -> NC_PMU_HOST_WAKE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 28 : SPU_SPI_SCLK -> SPI_SPU_SCLK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 29 : SPU_SPI_MOSI -> SPI_SPU_MOSI
CFG_FUNC0 | PULL_DOWN, // 30 : SPU_SPI_MISO -> SPI_SPU_MISO
CFG_FUNC0 | SLOW_SLEW, // 31 : SPU_SPI_CS_TRIG[0] -> SCM_SPU_TO_GRAPE_CS_L
/* Port 4 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 32 : SPU_SPI_CS_TRIG[1] -> SCM_GRAPE_TO_SPU_HINT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 33 : SPU_SPI_CS_TRIG[2] -> SCM_OSMIUM_TO_SPU_INT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 34 : SPU_SPI_CS_TRIG[3] -> SCM_LISA_TO_SPU_INT_L
CFG_FUNC0 | SLOW_SLEW, // 35 : SPU_SPI_CS_TRIG[4] -> SCM_SPU_TO_CARBON_CS_L
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 36 : SPU_SPI_CS_TRIG[5] -> SCM_CARBON_TO_SPU_INT1
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 37 : SPU_SPI_CS_TRIG[6] -> SCM_CARBON_TO_SPU_INT2
CFG_DISABLED, // 38 : SPU_SPI_CS_TRIG[7] -> NC_SCM_SPU_TO_COMPASS_CS_L
CFG_DISABLED, // 39 : SPU_SPI_CS_TRIG[8] -> NC_SCM_COMPASS_TO_SPU_INT
/* Port 5 */
CFG_DISABLED, // 40 : SPU_SPI_CS_TRIG[9] -> NC_SPU_SPI_CS_TRIG9
CFG_FUNC0 | SLOW_SLEW, // 41 : SPU_SPI_CS_TRIG[10] -> SCM_SPU_TO_OPAL_CS_L
CFG_DISABLED, // 42 : SPU_SPI_CS_TRIG[11] -> NC_SPU_SPI_CS_TRIG11
CFG_IN | PULL_UP | INPUT_SCHMITT, // 43 : SPU_SPI_CS_TRIG[12] -> SCM_PT_TO_SPU_INT_L
CFG_DISABLED, // 44 : SPU_SPI_CS_TRIG[13] -> NC_SPU_SPI_CS_TRIG13
CFG_DISABLED, // 45 : SPU_SPI_CS_TRIG[14] -> NC_SPU_SPI_CS_TRIG14
CFG_DISABLED, // 46 : SPU_SPI_CS_TRIG[15] -> NC_SPU_SPI_CS_TRIG15
CFG_IN | PULL_UP, // 47 : SPU_GPIO[9] -> GPIO_SEAJAY_TO_SPU_PING_DET_L
/* Port 6 */
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 48 : SPU_I2C_SDA -> I2C_SPU_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 49 : SPU_I2C_SCL -> I2C_SPU_1V8_SCL
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_evt_dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // 0 : I2S0_MCK -> GPIO_AP_TO_BERMUDA_CLK_XTAL1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 1 : I2S1_MCK -> I2S1_AP_TO_CODEC_MCLK_12M
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : SD_CLKOUT -> SDIO_AP_TO_WLAN_CLK
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 3 : SD_CMD_IO -> SDIO_AP_BI_WLAN_CMD
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 4 : SD_DATA_IO[0] -> SDIO_AP_BI_WLAN_DATA0
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 5 : SD_DATA_IO[1] -> SDIO_AP_BI_WLAN_DATA1
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 6 : SD_DATA_IO[2] -> SDIO_AP_BI_WLAN_DATA2
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 7 : SD_DATA_IO[3] -> SDIO_AP_BI_WLAN_DATA3
/* Port 1 */
CFG_FUNC0 | INPUT_SCHMITT, // 8 : SDIO_IRQ -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 9 : WL_HOST_WAKE -> GPIO_WLAN_TO_AP_IRQ
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 2 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 3 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 4 */
CFG_DISABLED, // 32 : GPIO[0] -> NC_AP_GPIO0
CFG_DISABLED, // 33 : GPIO[1] -> NC_AP_GPIO1
CFG_DISABLED, // 34 : GPIO[2] -> GPIO_BOOT_CONFIG_0
CFG_DISABLED, // 35 : GPIO[3] -> PP1V8_SW3C_SNS
CFG_DISABLED, // 36 : GPIO[4] -> NC_GPIO_BOOT_CONFIG_2
CFG_DISABLED, // 37 : GPIO[5] -> NC_GPIO_BOOT_CONFIG_3
CFG_DISABLED, // 38 : GPIO[6] -> GPIO_BOARD_ID_3
CFG_DISABLED, // 39 : GPIO[7] -> GPIO_BOARD_REV_0
/* Port 5 */
CFG_DISABLED, // 40 : GPIO[8] -> GPIO_BOARD_REV_1
CFG_DISABLED, // 41 : GPIO[9] -> GPIO_BOARD_REV_2
CFG_DISABLED, // 42 : GPIO[10] -> GPIO_BOARD_REV_3
CFG_DISABLED, // 43 : GPIO[11] -> NC_GPIO_DEV_BOOST_ALT_ID
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 44 : GPIO[12] -> GPIO_AP_TO_BT_DEVICE_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 45 : GPIO[13] -> GPIO_CODEC_TO_AP_IRQ_L
CFG_DISABLED, // 46 : GPIO[14] -> NC_AP_GPIO14
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 47 : GPIO[15] -> GPIO_AP_TO_BERMUDA_FW_DWLD_REQ
/* Port 6 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 48 : I2C1_SDA -> I2C1_AP_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 49 : I2C1_SCL -> I2C1_AP_1V8_SCL
CFG_DISABLED, // 50 : I2S0_LRCK -> NC_I2S0_LRCLK
CFG_DISABLED, // 51 : I2S0_BCLK -> NC_I2S0_BCLK
CFG_DISABLED, // 52 : I2S0_DOUT -> NC_I2S0_DOUT
CFG_DISABLED, // 53 : I2S0_DIN -> NC_I2S0_DIN
CFG_FUNC0, // 54 : I2S1_LRCK -> I2S1_CODEC_TO_AP_WCLK
CFG_FUNC0, // 55 : I2S1_BCLK -> I2S1_CODEC_TO_AP_BCLK
/* Port 7 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 56 : I2S1_DOUT -> I2S1_AP_TO_CODEC_DATA
CFG_FUNC0, // 57 : I2S1_DIN -> I2S1_CODEC_TO_AP_DATA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 58 : UART1_TXD -> UART1_AP_TO_BT_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 59 : UART1_RXD -> UART1_BT_TO_AP_RXD
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 60 : UART1_RTSN -> UART1_AP_TO_BT_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 61 : UART1_CTSN -> UART1_BT_TO_AP_CTS_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 62 : UART2_TXD -> UART2_AP_TO_BERMUDA_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 63 : UART2_RXD -> UART2_BERMUDA_TO_AP_RXD
/* Port 8 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 64 : UART2_RTSN -> UART2_AP_TO_BERMUDA_RTS_L
CFG_DISABLED | INPUT_SCHMITT, // 65 : UART2_CTSN -> UART2_BERMUDA_TO_AP_CTS_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : UART4_TXD -> UART4_AP_TO_WLAN_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 67 : UART4_RXD -> UART4_WLAN_TO_AP_RXD
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 68 : UART3_RTXD -> UART3_AP_BI_GG_SWI
CFG_DISABLED, // 69 : CLK32K_OUT -> NC_CLK32K_OUT
CFG_DISABLED, // 70 : TST_CLKOUT -> AP_TST_CLKOUT
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 71 : GPIO[16] -> AP_TO_SEAJAY_I2C_SDA_ENABLE
/* Port 9 */
CFG_DISABLED, // 72 : GPIO[17] -> GPIO_AP_TO_BSYNC_RESET_EN_L
CFG_DISABLED, // 73 : GPIO[18] -> GPIO_GRAPE_SWDCLK
CFG_DISABLED, // 74 : TMR32_PWM1 -> NC_TMR32_PWM1
CFG_IN | INPUT_SCHMITT, // 75 : TMR32_PWM2 -> DISP_BSYNC
CFG_FUNC0, // 76 : TMR32_PWM0 -> PMU_VDD_OK
CFG_FUNC0 | INPUT_SCHMITT, // 77 : DISP_TE -> DISP_BSYNC
CFG_DISABLED, // 78 : GPIO[19] -> GPIO_GRAPE_SWDIO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 79 : NAND_CEN[0] -> ANC_AP_TO_NAND_CEN<0>
/* Port 10 */
CFG_DISABLED, // 80 : NAND_CEN[1] -> NC_NAND_CEN1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 81 : NAND_IO[7] -> ANC_AP_BI_NAND_IO<7>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 82 : NAND_IO[6] -> ANC_AP_BI_NAND_IO<6>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 83 : NAND_IO[5] -> ANC_AP_BI_NAND_IO<5>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 84 : NAND_IO[4] -> ANC_AP_BI_NAND_IO<4>
CFG_DISABLED, // 85 : NAND_DQS -> NC_NAND_DQS
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 86 : NAND_REN -> ANC_AP_TO_NAND_RE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 87 : NAND_IO[3] -> ANC_AP_BI_NAND_IO<3>
/* Port 11 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 88 : NAND_IO[2] -> ANC_AP_BI_NAND_IO<2>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 89 : NAND_IO[1] -> ANC_AP_BI_NAND_IO<1>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 90 : NAND_IO[0] -> ANC_AP_BI_NAND_IO<0>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 91 : NAND_WEN -> ANC_AP_TO_NAND_WE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 92 : NAND_CLE -> ANC_AP_TO_NAND_CLE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 93 : NAND_ALE -> ANC_AP_TO_NAND_ALE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 94 : I2C0_SDA -> I2C0_AP_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 95 : I2C0_SCL -> I2C0_AP_1V8_SCL
/* Port 12 */
CFG_DISABLED, // 96 : DISP_VSYNC -> NC_DISP_VSYNC
CFG_DISABLED, // 97 : SPI0_SCLK -> NC_GPIO_BOARD_ID_0
CFG_DISABLED, // 98 : SPI0_MOSI -> GPIO_BOARD_ID_1
CFG_DISABLED, // 99 : SPI0_MISO -> GPIO_BOARD_ID_2
CFG_DISABLED, // 100 : SPI0_SSIN -> NC_SPI0_MCK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 101 : UART0_TXD -> UART0_TXD
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 102 : UART0_RXD -> UART0_RXD
CFG_DISABLED, // 103 : SPI1_SCLK -> NC_SPI1_SCLK
/* Port 13 */
CFG_DISABLED, // 104 : SPI1_MOSI -> NC_SPI1_MOSI
CFG_DISABLED, // 105 : SPI1_MISO -> NC_SPI1_MISO
CFG_DISABLED, // 106 : SPI1_SSIN -> NC_SPI1_SSIN
CFG_DISABLED, // 107 : GPIO[20] -> NC_AP_GPIO20
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 108 : GPIO[21] -> GPIO_AP_TO_WLAN_DEVICE_WAKE
CFG_IN | INPUT_SCHMITT, // 109 : GPIO[22] -> GPIO_TRISTAR_INT
CFG_DISABLED, // 110 : GPIO[23] -> GPIO_AP_TO_OPAL_LVBOOST_BUSY_L
CFG_IN, // 111 : GPIO[24] -> GPIO_OPAL_SWDIO
/* Port 14 */
CFG_IN, // 112 : GPIO[25] -> GPIO_OPAL_SWDCLK
CFG_DISABLED, // 113 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 114 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 115 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 116 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 117 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 118 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 119 : UNSPECIFIED -> UNSPECIFIED
/* Port 15 */
CFG_DISABLED, // 120 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 121 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 122 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 123 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
/* Port 16 */
CFG_DISABLED, // 128 : ENET_MDC -> NC_ENET_MDC
CFG_DISABLED, // 129 : ENET_MDIO -> NC_ENET_MDIO
CFG_DISABLED, // 130 : RMII_RXER -> GPIO_AP_TO_ORB_DEBUG
CFG_DISABLED, // 131 : RMII_TXEN -> NC_RMII_TXEN
CFG_DISABLED, // 132 : RMII_CLK -> NC_GPIO_DEV_DISPLAY_TO_AP_ID3
CFG_DISABLED, // 133 : RMII_TXD[0] -> NC_RMII_TXD0
CFG_DISABLED, // 134 : RMII_TXD[1] -> NC_FPGA_WL_REG_ON
CFG_DISABLED, // 135 : RMII_RXD[0] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID1
/* Port 17 */
CFG_DISABLED, // 136 : RMII_RXD[1] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID2
CFG_DISABLED, // 137 : RMII_CRSDV -> NC_GPIO_DEV_DISPLAY_TO_AP_ID0
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_evt_dev_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_IN | INPUT_SCHMITT, // 0 : REQUEST_DFU1 -> BUTTON1_BUFF_L
CFG_IN | INPUT_SCHMITT, // 1 : REQUEST_DFU2 -> LISA_BTN_BUFF_L
CFG_FUNC0 | INPUT_SCHMITT, // 2 : DOCK_CONNECT -> DOCK_CONNECT
CFG_DISABLED, // 3 : UNSPECIFIED -> UNSPECIFIED
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 4 : SPU_UART0_TXD -> GPIO_SPU_TO_WLAN_CONTEXT_B
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 5 : SPU_UART0_RXD -> GPIO_SPU_TO_WLAN_CONTEXT_A
CFG_DISABLED, // 6 : SPU_UART0_RTSN -> NC_SPU_UART0_RTSN
CFG_DISABLED, // 7 : SPU_UART0_CTSN -> NC_SPU_UART0_CTSN
/* Port 1 */
CFG_DISABLED, // 8 : SPU_UART1_TXD -> NC_SPU_UART1_TXD
CFG_DISABLED, // 9 : SPU_UART1_RXD -> NC_SPU_UART1_RXD
CFG_DISABLED, // 10 : SPU_UART1_RTSN -> NC_SPU_UART1_RTSN
CFG_DISABLED, // 11 : SPU_UART1_CTSN -> NC_SPU_UART1_CTSN
CFG_DISABLED, // 12 : SPU_GPIO[0] -> NC_SPU_GPIO0
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 13 : SPU_GPIO[1] -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_IN | INPUT_SCHMITT, // 14 : SPU_GPIO[2] -> GPIO_BT_TO_SPU_HOST_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 15 : SPU_GPIO[3] -> GPIO_SUNFISH_TO_SPU_INT_L
/* Port 2 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 16 : SPU_GPIO[4] -> GPIO_PMU_TO_SPU_IRQ_L
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 17 : SPU_GPIO[5] -> GPIO_AP_TO_SEAJAY_RESET
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 18 : SPU_GPIO[6] -> GPIO_SPU_TO_LVBOOST_EN
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 19 : SPU_GPIO[7] -> GPIO_BERMUDA_TO_SPU_HOST_WAKE
CFG_DISABLED, // 20 : SPU_GPIO[8] -> NC_SPU_GPIO8
CFG_OUT_0, // 21 : DFU_STATUS -> TP_DFU_STATUS
CFG_IN | PULL_DOWN, // 22 : FORCE_DFU -> TP_FORCE_DFU
CFG_FUNC0 | INPUT_SCHMITT, // 23 : PWR_GOOD -> PMU_TO_SPU_PWR_GOOD
/* Port 3 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 24 : SOC_VDD_HI_LO -> SPU_TO_PMU_VDD_HI_LO
CFG_DISABLED, // 25 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 26 : DOCK_ATTENTION -> NC_DOCK_ATTENTION
CFG_DISABLED, // 27 : PMU_HOST_WAKE -> NC_PMU_HOST_WAKE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 28 : SPU_SPI_SCLK -> SPI_SPU_SCLK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 29 : SPU_SPI_MOSI -> SPI_SPU_MOSI
CFG_FUNC0 | PULL_DOWN, // 30 : SPU_SPI_MISO -> SPI_SPU_MISO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 31 : SPU_SPI_CS_TRIG[0] -> SCM_SPU_TO_GRAPE_CS_L
/* Port 4 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 32 : SPU_SPI_CS_TRIG[1] -> SCM_GRAPE_TO_SPU_HINT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 33 : SPU_SPI_CS_TRIG[2] -> SCM_OSMIUM_TO_SPU_INT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 34 : SPU_SPI_CS_TRIG[3] -> SCM_LISA_TO_SPU_INT_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 35 : SPU_SPI_CS_TRIG[4] -> SCM_SPU_TO_CARBON_CS_L
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 36 : SPU_SPI_CS_TRIG[5] -> SCM_CARBON_TO_SPU_INT1
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 37 : SPU_SPI_CS_TRIG[6] -> SCM_CARBON_TO_SPU_INT2
CFG_DISABLED, // 38 : SPU_SPI_CS_TRIG[7] -> NC_SCM_SPU_TO_COMPASS_CS_L
CFG_DISABLED, // 39 : SPU_SPI_CS_TRIG[8] -> NC_SCM_COMPASS_TO_SPU_INT
/* Port 5 */
CFG_DISABLED, // 40 : SPU_SPI_CS_TRIG[9] -> NC_SPU_SPI_CS_TRIG9
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 41 : SPU_SPI_CS_TRIG[10] -> SCM_SPU_TO_OPAL_CS_L
CFG_DISABLED, // 42 : SPU_SPI_CS_TRIG[11] -> NC_SPU_SPI_CS_TRIG11
CFG_IN | PULL_UP | INPUT_SCHMITT, // 43 : SPU_SPI_CS_TRIG[12] -> SCM_PT_TO_SPU_INT_L
CFG_DISABLED, // 44 : SPU_SPI_CS_TRIG[13] -> NC_SPU_SPI_CS_TRIG13
CFG_DISABLED, // 45 : SPU_SPI_CS_TRIG[14] -> NC_SPU_SPI_CS_TRIG14
CFG_DISABLED, // 46 : SPU_SPI_CS_TRIG[15] -> NC_SPU_SPI_CS_TRIG15
CFG_IN | PULL_UP, // 47 : SPU_GPIO[9] -> GPIO_SEAJAY_TO_SPU_PING_DET_L
/* Port 6 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 48 : SPU_I2C_SDA -> I2C_SPU_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 49 : SPU_I2C_SCL -> I2C_SPU_1V8_SCL
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
struct pinconfig_map {
uint32_t board_id;
uint32_t board_id_mask;
const uint32_t *pinconfigs[GPIOC_COUNT];
};
static const struct pinconfig_map cfg_map[] = {
{ 0, 1, { pinconfig_evt_ap_0, pinconfig_evt_ap_1 } },
{ 1, 1, { pinconfig_evt_dev_0, pinconfig_evt_dev_1 } },
};
const uint32_t * target_get_evt_gpio_cfg(int gpioc)
{
static const struct pinconfig_map *selected_map = NULL;
if (selected_map == NULL) {
uint32_t board_id = platform_get_board_id();
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
selected_map = &cfg_map[i];
break;
}
}
if (selected_map == NULL)
panic("no default pinconfig for board id %u", board_id);
}
ASSERT(gpioc < GPIOC_COUNT);
return selected_map->pinconfigs[gpioc];
}
target/ipod6/pinconfig_fpga.c
+312
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/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <debug.h>
#include <drivers/apple/gpio.h>
#include <platform/soc/hwregbase.h>
#include <target.h>
/* S7002 Target Pin Configuration */
static const uint32_t gpio_default_cfg[GPIO_0_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // I2S0_MCK ->
CFG_DISABLED, // I2S1_MCK ->
CFG_DISABLED, // SD_CLKOUT ->
CFG_DISABLED, // SD_CMD_IO ->
CFG_DISABLED, // SD_DATA_IO[0] ->
CFG_DISABLED, // SD_DATA_IO[1] ->
CFG_DISABLED, // SD_DATA_IO[2] ->
CFG_DISABLED, // SD_DATA_IO[3] ->
/* Port 1 */
CFG_DISABLED, // SDIO_IRQ ->
CFG_DISABLED, // WL_HOST_WAKE ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 2 */
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 3 */
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 4 */
CFG_DISABLED, // GPIO0 ->
CFG_DISABLED, // GPIO1 ->
CFG_DISABLED, // GPIO2 -> BOOT_CONFIG[0]
CFG_DISABLED, // GPIO3 -> BOOT_CONFIG[1]
CFG_DISABLED, // GPIO4 -> BOOT_CONFIG[2]
CFG_DISABLED, // GPIO5 -> BOOT_CONFIG[3]
CFG_DISABLED, // GPIO6 -> BOARD_ID[3]
CFG_DISABLED, // GPIO7 ->
/* Port 5 */
CFG_DISABLED, // GPIO8 ->
CFG_DISABLED, // GPIO9 ->
CFG_DISABLED, // GPIO10 ->
CFG_DISABLED, // GPIO11 ->
CFG_DISABLED, // GPIO12 ->
CFG_DISABLED, // GPIO13 ->
CFG_DISABLED, // GPIO14 ->
CFG_DISABLED, // GPIO15 ->
/* Port 6 */
CFG_DISABLED, // I2C1_SDA ->
CFG_DISABLED, // I2C1_SCL ->
CFG_DISABLED, // I2S0_LRCK ->
CFG_DISABLED, // I2S0_BCLK ->
CFG_DISABLED, // I2S0_DOUT ->
CFG_DISABLED, // I2S0_DIN ->
CFG_DISABLED, // I2S1_LRCK ->
CFG_DISABLED, // I2S1_BCLK ->
/* Port 7 */
CFG_DISABLED, // I2S1_DOUT ->
CFG_DISABLED, // I2S1_DIN ->
CFG_DISABLED, // UART1_TXD ->
CFG_DISABLED, // UART1_RXD ->
CFG_DISABLED, // UART1_RTSN ->
CFG_DISABLED, // UART1_CTSN ->
CFG_DISABLED, // UART2_TXD ->
CFG_DISABLED, // UART2_RXD ->
/* Port 8 */
CFG_DISABLED, // UART2_RTSN ->
CFG_DISABLED, // UART2_CTSN ->
CFG_DISABLED, // UART4_TXD ->
CFG_DISABLED, // UART4_RXD ->
CFG_DISABLED, // UART3_RTXD ->
CFG_DISABLED, // CLK32K_OUT ->
CFG_DISABLED, // TEST_CLKOUT ->
CFG_DISABLED, // GPIO16 ->
/* Port 9 */
CFG_DISABLED, // GPIO17 ->
CFG_DISABLED, // GPIO18 ->
CFG_DISABLED, // TMR32_PWM1 ->
CFG_DISABLED, // TMR32_PWM2 ->
CFG_DISABLED, // TMR32_PWM3 ->
CFG_DISABLED, // DISP_TE ->
CFG_DISABLED, // GPIO19 ->
CFG_DISABLED, // NAND_CEN[0] ->
/* Port 10 */
CFG_DISABLED, // NAND_CEN[1] ->
CFG_DISABLED, // NAND_IO[7] ->
CFG_DISABLED, // NAND_IO[6] ->
CFG_DISABLED, // NAND_IO[5] ->
CFG_DISABLED, // NAND_IO[4] ->
CFG_DISABLED, // NAND_DQS ->
CFG_DISABLED, // NAND_REN ->
CFG_DISABLED, // NAND_IO[3] ->
/* Port 11 */
CFG_DISABLED, // NAND_IO[2] ->
CFG_DISABLED, // NAND_IO[1] ->
CFG_DISABLED, // NAND_IO[0] ->
CFG_DISABLED, // NAND_WEN ->
CFG_DISABLED, // NAND_CLE ->
CFG_DISABLED, // NAND_ALE ->
CFG_DISABLED, // I2C0_SDA ->
CFG_DISABLED, // I2C0_SCL ->
/* Port 12 */
CFG_DISABLED, // DISPLAY_SYNC ->
CFG_DISABLED, // SPI0_SCLK -> SPI0_SCLK/BOARD_ID[0]
CFG_DISABLED, // SPI0_MOSI -> SPI0_MOSI/BOARD_ID[1]
CFG_DISABLED, // SPI0_MISO -> SPI0_MISO/BOARD_ID[2]
CFG_DISABLED, // SPI0_SSIN ->
CFG_DISABLED, // UART0_TXD ->
CFG_DISABLED, // UART0_RXD ->
CFG_DISABLED, // SPI1_SCLK ->
/* Port 13 */
CFG_DISABLED, // SPI1_MOSI ->
CFG_DISABLED, // SPI1_MISO ->
CFG_DISABLED, // SPI1_SSIN ->
CFG_DISABLED, // GPIO20 ->
CFG_DISABLED, // GPIO21 ->
CFG_DISABLED, // GPIO22 ->
CFG_DISABLED, // GPIO23 ->
CFG_DISABLED, // GPIO24 ->
/* Port 14 */
CFG_DISABLED, // GPIO25 ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 15 */
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 16 */
CFG_DISABLED, // ENET_MDC ->
CFG_DISABLED, // ENET_MDIO ->
CFG_DISABLED, // RMII_RXER ->
CFG_DISABLED, // RMII_TXEN ->
CFG_DISABLED, // RMII_CLK ->
CFG_DISABLED, // RMII_TXD[0] ->
CFG_DISABLED, // RMII_TXD[1] ->
CFG_DISABLED, // RMII_RXD[0] ->
/* Port 17 */
CFG_DISABLED, // RMII_RXD[1] ->
CFG_DISABLED, // RMII_RXD[0] ->
CFG_DISABLED, // RMII_CRSDV ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
};
static const uint32_t gpio_1_default_cfg[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // REQUEST_DFU1 ->
CFG_DISABLED, // REQUEST_DFU2 ->
CFG_DISABLED, // DOCK_CONNECT ->
CFG_DISABLED, // CLK32K_IN ->
CFG_DISABLED, // SPU_UART0_TXD ->
CFG_DISABLED, // SPU_UART0_RXD ->
CFG_DISABLED, // SPU_UART0_RTSN ->
CFG_DISABLED, // SPU_UART0_CTSN ->
/* Port 1 */
CFG_DISABLED, // SPU_UART1_TXD ->
CFG_DISABLED, // SPU_UART1_RXD ->
CFG_DISABLED, // SPU_UART1_RTSN ->
CFG_DISABLED, // SPU_UART1_CTSN ->
CFG_DISABLED, // SPU_GPIO[0] ->
CFG_DISABLED, // SPU_GPIO[1] ->
CFG_DISABLED, // SPU_GPIO[2] ->
CFG_DISABLED, // SPU_GPIO[3] ->
/* Port 2 */
CFG_DISABLED, // SPU_GPIO[4] ->
CFG_DISABLED, // SPU_GPIO[5] ->
CFG_DISABLED, // SPU_GPIO[6] ->
CFG_DISABLED, // SPU_GPIO[7] ->
CFG_DISABLED, // SPU_GPIO[8] ->
CFG_DISABLED, // DFU_STATUS ->
CFG_DISABLED, // FORCE_DFU ->
CFG_DISABLED, // POWER_GOOD ->
/* Port 3 */
CFG_DISABLED, // SOC_VDD_HI_LO ->
CFG_DISABLED, // SOC_VDD_ALL_ON ->
CFG_DISABLED, // DOCK_ATTENTION ->
CFG_DISABLED, // PMU_HOST_WAKE ->
CFG_DISABLED, // SPU_SPI_SCLK ->
CFG_DISABLED, // SPU_SPI_MOSI ->
CFG_DISABLED, // SPU_SPI_MISO ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[0] ->
/* Port 4 */
CFG_DISABLED, // SPU_SPI_CS_TRIG[1] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[2] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[3] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[4] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[5] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[6] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[7] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[8] ->
/* Port 5 */
CFG_DISABLED, // SPU_SPI_CS_TRIG[9] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[10] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[11] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[12] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[13] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[14] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[15] ->
CFG_DISABLED, // SPU_GPIO[9] ->
/* Port 6 */
CFG_DISABLED, // SPU_I2C_SDA ->
CFG_DISABLED, // SPU_I2C_SCL ->
CFG_DISABLED, // WDOG ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 7 */
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 8 */
CFG_DISABLED, // NULL ->
CFG_DISABLED, // RESETN -> RESET_L
CFG_DISABLED, // JTAG_TRSTN ->
CFG_DISABLED, // JTAG_SEL ->
CFG_DISABLED, // JTAG_TCK ->
CFG_DISABLED, // JTAG_TMS ->
CFG_DISABLED, // JTAG_TRTCK ->
CFG_DISABLED, // JTAG_TDO ->
/* Port 9 */
CFG_DISABLED, // JTAG_TDI ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
};
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
{
switch (gpioc) {
case 0:
return gpio_default_cfg;
case 1:
return gpio_1_default_cfg;
default:
panic("unknown GPIO controller");
}
}
target/ipod6/pinconfig_product.c
+82
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/*
* Copyright (C) 2009-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <debug.h>
#include <drivers/apple/gpio.h>
#include <platform/gpiodef.h>
#include <platform/soc/hwregbase.h>
#include <target.h>
extern const uint32_t* target_get_proto2a_gpio_cfg(uint32_t gpioc);
extern const uint32_t* target_get_proto2b_gpio_cfg(uint32_t gpioc);
extern const uint32_t* target_get_evt_gpio_cfg(uint32_t gpioc);
static bool board_rev_determined;
static bool use_dummy_pinconfig;
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
{
// HACK: -- the first call into target_get_default_gpio_cfg() reads
// and attempts to restore BOARD_REV[3:0] to GPIO_CFG_DEFAULT.
//
// This will result in a recursive call back into target_get_default_gpio_cfg.
// To break the recursion, while determining board rev we can reply with any pinconfig
// since it's only being used for BOARD_REV[3:0] and it's CFG_DISABLED in all pinconfigs
//
// Remove this after we no longer have BOARD_REV-dependent pinconfigs.
if (use_dummy_pinconfig)
{
return target_get_proto2a_gpio_cfg(gpioc);
}
if (!board_rev_determined)
{
use_dummy_pinconfig = true;
(void)ipod6_get_board_rev();
use_dummy_pinconfig = false;
board_rev_determined = true;
}
if (target_config_dev()) {
// Per radar 18904522 - dev board 0xF (dev3 board) has been depreciated, but this board
// rev settings will default to dev board 0xE (dev4 board) configuration
// Dev boards 0xE through 0xA are currently all based off the proto2b Dev config, per
// Board Rev tracker and email clarification from HW EE
if (ipod6_get_board_rev() >= 0xA)
return target_get_proto2b_gpio_cfg(gpioc);
else
panic("Unknown BOARD_REV 0x%x", ipod6_get_board_rev());
} else {
// Per radar 18904522 - ProtoN AP products have been depreciated
// All that remains are post-ProtoN AP products.
// The story gets more complicated here -- see Board Rev tracker spreadsheet
switch (ipod6_get_board_rev())
{
case BOARD_REV_PROTO2A:
return target_get_proto2a_gpio_cfg(gpioc);
break;
case BOARD_REV_PROTO2B:
case BOARD_REV_PROTO2X_CARDINAL:
case BOARD_REV_PROTO2B_ALT_CARBON:
case BOARD_REV_PROTO2D:
case BOARD_REV_PROTO2F:
return target_get_proto2b_gpio_cfg(gpioc);
break;
case 0 ... BOARD_REV_EVT:
// For anything EVT or newer, use EVT pinconfig for now.
return target_get_evt_gpio_cfg(gpioc);
break;
default:
panic("Unknown board revision 0x%x", ipod6_get_board_rev());
}
}
}
target/ipod6/pinconfig_proto2a.c
+566
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/*
* Copyright (C) 2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
I/O Spreadsheet version: rev 0.3.0
I/O Spreadsheet tracker: None
Conversion command: csvtopinconfig.py --soc m7 <filename> --prefix proto2a
*/
#include <debug.h>
#include <drivers/apple/gpio.h>
#include <platform.h>
#include <platform/soc/hwregbase.h>
#include <stdint.h>
static const uint32_t pinconfig_proto2a_ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // 0 : I2S0_MCK -> GPIO_AP_TO_BERMUDA_CLK_XTAL1
CFG_FUNC0 | SLOW_SLEW, // 1 : I2S1_MCK -> I2S1_AP_TO_CODEC_MCLK_12M
CFG_FUNC0 | SLOW_SLEW, // 2 : SD_CLKOUT -> SDIO_AP_TO_WLAN_CLK
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 3 : SD_CMD_IO -> SDIO_AP_BI_WLAN_CMD
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 4 : SD_DATA_IO[0] -> SDIO_AP_BI_WLAN_DATA0
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 5 : SD_DATA_IO[1] -> SDIO_AP_BI_WLAN_DATA1
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 6 : SD_DATA_IO[2] -> SDIO_AP_BI_WLAN_DATA2
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 7 : SD_DATA_IO[3] -> SDIO_AP_BI_WLAN_DATA3
/* Port 1 */
CFG_FUNC0 | INPUT_SCHMITT, // 8 : SDIO_IRQ -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 9 : WL_HOST_WAKE -> GPIO_WLAN_TO_AP_IRQ
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 2 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 3 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 4 */
CFG_DISABLED, // 32 : GPIO[0] -> NC_AP_GPIO0
CFG_DISABLED, // 33 : GPIO[1] -> NC_AP_GPIO1
CFG_DISABLED, // 34 : GPIO[2] -> GPIO_BOOT_CONFIG_0
CFG_DISABLED, // 35 : GPIO[3] -> PP1V8_SW3C_SNS
CFG_DISABLED, // 36 : GPIO[4] -> NC_GPIO_BOOT_CONFIG_2
CFG_DISABLED, // 37 : GPIO[5] -> NC_GPIO_BOOT_CONFIG_3
CFG_DISABLED, // 38 : GPIO[6] -> GPIO_BOARD_ID_3
CFG_DISABLED, // 39 : GPIO[7] -> GPIO_BOARD_REV_0
/* Port 5 */
CFG_DISABLED, // 40 : GPIO[8] -> GPIO_BOARD_REV_1
CFG_DISABLED, // 41 : GPIO[9] -> GPIO_BOARD_REV_2
CFG_DISABLED, // 42 : GPIO[10] -> GPIO_BOARD_REV_3
CFG_DISABLED, // 43 : GPIO[11] -> NC_GPIO_DEV_BOOST_ALT_ID
CFG_OUT_0 | SLOW_SLEW, // 44 : GPIO[12] -> GPIO_AP_TO_BT_DEVICE_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 45 : GPIO[13] -> GPIO_CODEC_TO_AP_IRQ_L
CFG_OUT_0 | SLOW_SLEW, // 46 : GPIO[14] -> GPIO_AP_TO_SEAJAY_RESET
CFG_OUT_0 | SLOW_SLEW, // 47 : GPIO[15] -> GPIO_AP_TO_BERMUDA_FW_DWLD_REQ
/* Port 6 */
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 48 : I2C1_SDA -> I2C1_AP_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 49 : I2C1_SCL -> I2C1_AP_1V8_SCL
CFG_DISABLED, // 50 : I2S0_LRCK -> NC_I2S0_LRCLK
CFG_DISABLED, // 51 : I2S0_BCLK -> NC_I2S0_BCLK
CFG_DISABLED, // 52 : I2S0_DOUT -> NC_I2S0_DOUT
CFG_DISABLED, // 53 : I2S0_DIN -> NC_I2S0_DIN
CFG_FUNC0, // 54 : I2S1_LRCK -> I2S1_CODEC_TO_AP_WCLK
CFG_FUNC0, // 55 : I2S1_BCLK -> I2S1_CODEC_TO_AP_BCLK
/* Port 7 */
CFG_FUNC0 | SLOW_SLEW, // 56 : I2S1_DOUT -> I2S1_AP_TO_CODEC_DATA
CFG_FUNC0, // 57 : I2S1_DIN -> I2S1_CODEC_TO_AP_DATA
CFG_FUNC0 | SLOW_SLEW, // 58 : UART1_TXD -> UART1_AP_TO_BT_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 59 : UART1_RXD -> UART1_BT_TO_AP_RXD
CFG_FUNC0 | SLOW_SLEW, // 60 : UART1_RTSN -> UART1_AP_TO_BT_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 61 : UART1_CTSN -> UART1_BT_TO_AP_CTS_L
CFG_FUNC0 | SLOW_SLEW, // 62 : UART2_TXD -> UART2_AP_TO_BERMUDA_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 63 : UART2_RXD -> UART2_BERMUDA_TO_AP_RXD
/* Port 8 */
CFG_FUNC0 | SLOW_SLEW, // 64 : UART2_RTSN -> UART2_AP_TO_BERMUDA_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 65 : UART2_CTSN -> UART2_BERMUDA_TO_AP_CTS_L
CFG_FUNC0 | SLOW_SLEW, // 66 : UART4_TXD -> UART4_AP_TO_WLAN_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 67 : UART4_RXD -> UART4_WLAN_TO_AP_RXD
CFG_FUNC0 | SLOW_SLEW, // 68 : UART3_RTXD -> UART3_AP_BI_GG_SWI
CFG_DISABLED, // 69 : CLK32K_OUT -> NC_CLK32K_OUT
CFG_DISABLED, // 70 : TST_CLKOUT -> AP_TST_CLKOUT
CFG_DISABLED, // 71 : GPIO[16] -> NC_AP_GPIO16
/* Port 9 */
CFG_IN, // 72 : GPIO[17] -> GPIO_SEAJAY_CLOAK_EN
CFG_DISABLED, // 73 : GPIO[18] -> GPIO_GRAPE_SWDCLK
CFG_DISABLED, // 74 : TMR32_PWM1 -> NC_TMR32_PWM1
CFG_DISABLED, // 75 : TMR32_PWM2 -> NC_TMR32_PWM2
CFG_FUNC0, // 76 : TMR32_PWM0 -> PMU_VDD_OK
CFG_FUNC0, // 77 : DISP_TE -> DISP_BSYNC
CFG_DISABLED, // 78 : GPIO[19] -> GPIO_GRAPE_SWDIO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 79 : NAND_CEN[0] -> ANC_AP_TO_NAND_CEN<0>
/* Port 10 */
CFG_DISABLED, // 80 : NAND_CEN[1] -> NC_NAND_CEN1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 81 : NAND_IO[7] -> ANC_AP_BI_NAND_IO<7>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 82 : NAND_IO[6] -> ANC_AP_BI_NAND_IO<6>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 83 : NAND_IO[5] -> ANC_AP_BI_NAND_IO<5>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 84 : NAND_IO[4] -> ANC_AP_BI_NAND_IO<4>
CFG_DISABLED, // 85 : NAND_DQS -> NC_NAND_DQS
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 86 : NAND_REN -> ANC_AP_TO_NAND_RE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 87 : NAND_IO[3] -> ANC_AP_BI_NAND_IO<3>
/* Port 11 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 88 : NAND_IO[2] -> ANC_AP_BI_NAND_IO<2>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 89 : NAND_IO[1] -> ANC_AP_BI_NAND_IO<1>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 90 : NAND_IO[0] -> ANC_AP_BI_NAND_IO<0>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 91 : NAND_WEN -> ANC_AP_TO_NAND_WE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 92 : NAND_CLE -> ANC_AP_TO_NAND_CLE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 93 : NAND_ALE -> ANC_AP_TO_NAND_ALE
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 94 : I2C0_SDA -> I2C0_AP_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 95 : I2C0_SCL -> I2C0_AP_1V8_SCL
/* Port 12 */
CFG_DISABLED, // 96 : DISP_VSYNC -> NC_DISP_VSYNC
CFG_DISABLED, // 97 : SPI0_SCLK -> NC_GPIO_BOARD_ID_0
CFG_DISABLED, // 98 : SPI0_MOSI -> GPIO_BOARD_ID_1
CFG_DISABLED, // 99 : SPI0_MISO -> GPIO_BOARD_ID_2
CFG_DISABLED, // 100 : SPI0_SSIN -> NC_SPI0_MCK
CFG_FUNC0 | SLOW_SLEW, // 101 : UART0_TXD -> UART0_TXD
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 102 : UART0_RXD -> UART0_RXD
CFG_DISABLED, // 103 : SPI1_SCLK -> NC_SPI1_SCLK
/* Port 13 */
CFG_DISABLED, // 104 : SPI1_MOSI -> NC_SPI1_MOSI
CFG_DISABLED, // 105 : SPI1_MISO -> NC_SPI1_MISO
CFG_DISABLED, // 106 : SPI1_SSIN -> NC_SPI1_SSIN
CFG_DISABLED, // 107 : GPIO[20] -> NC_AP_GPIO20
CFG_OUT_0 | SLOW_SLEW, // 108 : GPIO[21] -> GPIO_AP_TO_WLAN_DEVICE_WAKE
CFG_IN | INPUT_SCHMITT, // 109 : GPIO[22] -> GPIO_TRISTAR_INT
CFG_DISABLED, // 110 : GPIO[23] -> GPIO_AP_TO_OPAL_LVBOOST_BUSY_L
CFG_IN, // 111 : GPIO[24] -> GPIO_OPAL_SWDIO
/* Port 14 */
CFG_IN, // 112 : GPIO[25] -> GPIO_OPAL_SWDCLK
CFG_DISABLED, // 113 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 114 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 115 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 116 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 117 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 118 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 119 : UNSPECIFIED -> UNSPECIFIED
/* Port 15 */
CFG_DISABLED, // 120 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 121 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 122 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 123 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
/* Port 16 */
CFG_DISABLED, // 128 : ENET_MDC -> NC_ENET_MDC
CFG_DISABLED, // 129 : ENET_MDIO -> NC_ENET_MDIO
CFG_DISABLED, // 130 : RMII_RXER -> GPIO_AP_TO_ORB_DEBUG
CFG_DISABLED, // 131 : RMII_TXEN -> NC_RMII_TXEN
CFG_DISABLED, // 132 : RMII_CLK -> NC_GPIO_DEV_DISPLAY_TO_AP_ID3
CFG_DISABLED, // 133 : RMII_TXD[0] -> NC_RMII_TXD0
CFG_DISABLED, // 134 : RMII_TXD[1] -> NC_FPGA_WL_REG_ON
CFG_DISABLED, // 135 : RMII_RXD[0] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID1
/* Port 17 */
CFG_DISABLED, // 136 : RMII_RXD[1] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID2
CFG_DISABLED, // 137 : RMII_CRSDV -> NC_GPIO_DEV_DISPLAY_TO_AP_ID0
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_proto2a_ap_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_IN | INPUT_SCHMITT, // 0 : REQUEST_DFU1 -> BUTTON1_BUFF_L
CFG_IN | INPUT_SCHMITT, // 1 : REQUEST_DFU2 -> LISA_BTN_BUFF_L
CFG_FUNC0 | INPUT_SCHMITT, // 2 : DOCK_CONNECT -> DOCK_CONNECT
CFG_DISABLED, // 3 : UNSPECIFIED -> UNSPECIFIED
CFG_OUT_0 | SLOW_SLEW, // 4 : SPU_UART0_TXD -> GPIO_SPU_TO_WLAN_CONTEXT_B
CFG_OUT_0 | SLOW_SLEW, // 5 : SPU_UART0_RXD -> GPIO_SPU_TO_WLAN_CONTEXT_A
CFG_DISABLED, // 6 : SPU_UART0_RTSN -> NC_SPU_UART0_RTSN
CFG_DISABLED, // 7 : SPU_UART0_CTSN -> NC_SPU_UART0_CTSN
/* Port 1 */
CFG_DISABLED, // 8 : SPU_UART1_TXD -> NC_SPU_UART1_TXD
CFG_DISABLED, // 9 : SPU_UART1_RXD -> NC_SPU_UART1_RXD
CFG_DISABLED, // 10 : SPU_UART1_RTSN -> NC_SPU_UART1_RTSN
CFG_DISABLED, // 11 : SPU_UART1_CTSN -> NC_SPU_UART1_CTSN
CFG_DISABLED, // 12 : SPU_GPIO[0] -> NC_SPU_GPIO0
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 13 : SPU_GPIO[1] -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_IN | INPUT_SCHMITT, // 14 : SPU_GPIO[2] -> GPIO_BT_TO_SPU_HOST_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 15 : SPU_GPIO[3] -> GPIO_SUNFISH_TO_SPU_INT_L
/* Port 2 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 16 : SPU_GPIO[4] -> GPIO_PMU_TO_SPU_IRQ_L
CFG_DISABLED, // 17 : SPU_GPIO[5] -> NC_SPU_GPIO5
CFG_OUT_0 | SLOW_SLEW, // 18 : SPU_GPIO[6] -> GPIO_SPU_TO_LVBOOST_EN
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 19 : SPU_GPIO[7] -> GPIO_BERMUDA_TO_SPU_HOST_WAKE
CFG_DISABLED, // 20 : SPU_GPIO[8] -> NC_SPU_GPIO8
CFG_OUT_0, // 21 : DFU_STATUS -> TP_DFU_STATUS
CFG_IN | PULL_DOWN, // 22 : FORCE_DFU -> TP_FORCE_DFU
CFG_FUNC0 | INPUT_SCHMITT, // 23 : PWR_GOOD -> PMU_TO_SPU_PWR_GOOD
/* Port 3 */
CFG_FUNC0 | SLOW_SLEW, // 24 : SOC_VDD_HI_LO -> SPU_TO_PMU_VDD_HI_LO
CFG_DISABLED, // 25 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 26 : DOCK_ATTENTION -> NC_DOCK_ATTENTION
CFG_DISABLED, // 27 : PMU_HOST_WAKE -> NC_PMU_HOST_WAKE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 28 : SPU_SPI_SCLK -> SPI_SPU_SCLK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 29 : SPU_SPI_MOSI -> SPI_SPU_MOSI
CFG_FUNC0 | PULL_DOWN, // 30 : SPU_SPI_MISO -> SPI_SPU_MISO
CFG_FUNC0 | SLOW_SLEW, // 31 : SPU_SPI_CS_TRIG[0] -> SCM_SPU_TO_GRAPE_CS_L
/* Port 4 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 32 : SPU_SPI_CS_TRIG[1] -> SCM_GRAPE_TO_SPU_HINT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 33 : SPU_SPI_CS_TRIG[2] -> SCM_OSMIUM_TO_SPU_INT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 34 : SPU_SPI_CS_TRIG[3] -> SCM_LISA_TO_SPU_INT_L
CFG_FUNC0 | SLOW_SLEW, // 35 : SPU_SPI_CS_TRIG[4] -> SCM_SPU_TO_CARBON_CS_L
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 36 : SPU_SPI_CS_TRIG[5] -> SCM_CARBON_TO_SPU_INT1
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 37 : SPU_SPI_CS_TRIG[6] -> SCM_CARBON_TO_SPU_INT2
CFG_DISABLED, // 38 : SPU_SPI_CS_TRIG[7] -> NC_SCM_SPU_TO_COMPASS_CS_L
CFG_DISABLED, // 39 : SPU_SPI_CS_TRIG[8] -> NC_SCM_COMPASS_TO_SPU_INT
/* Port 5 */
CFG_DISABLED, // 40 : SPU_SPI_CS_TRIG[9] -> NC_SPU_SPI_CS_TRIG9
CFG_FUNC0 | SLOW_SLEW, // 41 : SPU_SPI_CS_TRIG[10] -> SCM_SPU_TO_OPAL_CS_L
CFG_DISABLED, // 42 : SPU_SPI_CS_TRIG[11] -> NC_SPU_SPI_CS_TRIG11
CFG_IN | PULL_UP | INPUT_SCHMITT, // 43 : SPU_SPI_CS_TRIG[12] -> SCM_PT_TO_SPU_INT_L
CFG_DISABLED, // 44 : SPU_SPI_CS_TRIG[13] -> NC_SPU_SPI_CS_TRIG13
CFG_DISABLED, // 45 : SPU_SPI_CS_TRIG[14] -> NC_SPU_SPI_CS_TRIG14
CFG_DISABLED, // 46 : SPU_SPI_CS_TRIG[15] -> NC_SPU_SPI_CS_TRIG15
CFG_IN | PULL_UP, // 47 : SPU_GPIO[9] -> GPIO_SEAJAY_TO_SPU_PING_DET_L
/* Port 6 */
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 48 : SPU_I2C_SDA -> I2C_SPU_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 49 : SPU_I2C_SCL -> I2C_SPU_1V8_SCL
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_proto2a_dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // 0 : I2S0_MCK -> GPIO_AP_TO_BERMUDA_CLK_XTAL1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 1 : I2S1_MCK -> I2S1_AP_TO_CODEC_MCLK_12M
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : SD_CLKOUT -> SDIO_AP_TO_WLAN_CLK
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 3 : SD_CMD_IO -> SDIO_AP_BI_WLAN_CMD
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 4 : SD_DATA_IO[0] -> SDIO_AP_BI_WLAN_DATA0
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 5 : SD_DATA_IO[1] -> SDIO_AP_BI_WLAN_DATA1
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 6 : SD_DATA_IO[2] -> SDIO_AP_BI_WLAN_DATA2
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 7 : SD_DATA_IO[3] -> SDIO_AP_BI_WLAN_DATA3
/* Port 1 */
CFG_FUNC0 | INPUT_SCHMITT, // 8 : SDIO_IRQ -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 9 : WL_HOST_WAKE -> GPIO_WLAN_TO_AP_IRQ
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 2 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 3 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 4 */
CFG_DISABLED, // 32 : GPIO[0] -> NC_AP_GPIO0
CFG_DISABLED, // 33 : GPIO[1] -> NC_AP_GPIO1
CFG_DISABLED, // 34 : GPIO[2] -> GPIO_BOOT_CONFIG_0
CFG_DISABLED, // 35 : GPIO[3] -> PP1V8_SW3C_SNS
CFG_DISABLED, // 36 : GPIO[4] -> NC_GPIO_BOOT_CONFIG_2
CFG_DISABLED, // 37 : GPIO[5] -> NC_GPIO_BOOT_CONFIG_3
CFG_DISABLED, // 38 : GPIO[6] -> GPIO_BOARD_ID_3
CFG_DISABLED, // 39 : GPIO[7] -> GPIO_BOARD_REV_0
/* Port 5 */
CFG_DISABLED, // 40 : GPIO[8] -> GPIO_BOARD_REV_1
CFG_DISABLED, // 41 : GPIO[9] -> GPIO_BOARD_REV_2
CFG_DISABLED, // 42 : GPIO[10] -> GPIO_BOARD_REV_3
CFG_DISABLED, // 43 : GPIO[11] -> NC_GPIO_DEV_BOOST_ALT_ID
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 44 : GPIO[12] -> GPIO_AP_TO_BT_DEVICE_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 45 : GPIO[13] -> GPIO_CODEC_TO_AP_IRQ_L
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 46 : GPIO[14] -> GPIO_AP_TO_SEAJAY_RESET
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 47 : GPIO[15] -> GPIO_AP_TO_BERMUDA_FW_DWLD_REQ
/* Port 6 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 48 : I2C1_SDA -> I2C1_AP_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 49 : I2C1_SCL -> I2C1_AP_1V8_SCL
CFG_DISABLED, // 50 : I2S0_LRCK -> NC_I2S0_LRCLK
CFG_DISABLED, // 51 : I2S0_BCLK -> NC_I2S0_BCLK
CFG_DISABLED, // 52 : I2S0_DOUT -> NC_I2S0_DOUT
CFG_DISABLED, // 53 : I2S0_DIN -> NC_I2S0_DIN
CFG_FUNC0, // 54 : I2S1_LRCK -> I2S1_CODEC_TO_AP_WCLK
CFG_FUNC0, // 55 : I2S1_BCLK -> I2S1_CODEC_TO_AP_BCLK
/* Port 7 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 56 : I2S1_DOUT -> I2S1_AP_TO_CODEC_DATA
CFG_FUNC0, // 57 : I2S1_DIN -> I2S1_CODEC_TO_AP_DATA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 58 : UART1_TXD -> UART1_AP_TO_BT_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 59 : UART1_RXD -> UART1_BT_TO_AP_RXD
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 60 : UART1_RTSN -> UART1_AP_TO_BT_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 61 : UART1_CTSN -> UART1_BT_TO_AP_CTS_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 62 : UART2_TXD -> UART2_AP_TO_BERMUDA_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 63 : UART2_RXD -> UART2_BERMUDA_TO_AP_RXD
/* Port 8 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 64 : UART2_RTSN -> UART2_AP_TO_BERMUDA_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 65 : UART2_CTSN -> UART2_BERMUDA_TO_AP_CTS_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : UART4_TXD -> UART4_AP_TO_WLAN_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 67 : UART4_RXD -> UART4_WLAN_TO_AP_RXD
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 68 : UART3_RTXD -> UART3_AP_BI_GG_SWI
CFG_DISABLED, // 69 : CLK32K_OUT -> NC_CLK32K_OUT
CFG_DISABLED, // 70 : TST_CLKOUT -> AP_TST_CLKOUT
CFG_DISABLED, // 71 : GPIO[16] -> NC_AP_GPIO16
/* Port 9 */
CFG_IN, // 72 : GPIO[17] -> GPIO_SEAJAY_CLOAK_EN
CFG_DISABLED, // 73 : GPIO[18] -> GPIO_GRAPE_SWDCLK
CFG_DISABLED, // 74 : TMR32_PWM1 -> NC_TMR32_PWM1
CFG_DISABLED, // 75 : TMR32_PWM2 -> NC_TMR32_PWM2
CFG_FUNC0, // 76 : TMR32_PWM0 -> PMU_VDD_OK
CFG_FUNC0, // 77 : DISP_TE -> DISP_BSYNC
CFG_DISABLED, // 78 : GPIO[19] -> GPIO_GRAPE_SWDIO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 79 : NAND_CEN[0] -> ANC_AP_TO_NAND_CEN<0>
/* Port 10 */
CFG_DISABLED, // 80 : NAND_CEN[1] -> NC_NAND_CEN1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 81 : NAND_IO[7] -> ANC_AP_BI_NAND_IO<7>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 82 : NAND_IO[6] -> ANC_AP_BI_NAND_IO<6>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 83 : NAND_IO[5] -> ANC_AP_BI_NAND_IO<5>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 84 : NAND_IO[4] -> ANC_AP_BI_NAND_IO<4>
CFG_DISABLED, // 85 : NAND_DQS -> NC_NAND_DQS
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 86 : NAND_REN -> ANC_AP_TO_NAND_RE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 87 : NAND_IO[3] -> ANC_AP_BI_NAND_IO<3>
/* Port 11 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 88 : NAND_IO[2] -> ANC_AP_BI_NAND_IO<2>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 89 : NAND_IO[1] -> ANC_AP_BI_NAND_IO<1>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 90 : NAND_IO[0] -> ANC_AP_BI_NAND_IO<0>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 91 : NAND_WEN -> ANC_AP_TO_NAND_WE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 92 : NAND_CLE -> ANC_AP_TO_NAND_CLE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 93 : NAND_ALE -> ANC_AP_TO_NAND_ALE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 94 : I2C0_SDA -> I2C0_AP_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 95 : I2C0_SCL -> I2C0_AP_1V8_SCL
/* Port 12 */
CFG_DISABLED, // 96 : DISP_VSYNC -> NC_DISP_VSYNC
CFG_DISABLED, // 97 : SPI0_SCLK -> NC_GPIO_BOARD_ID_0
CFG_DISABLED, // 98 : SPI0_MOSI -> GPIO_BOARD_ID_1
CFG_DISABLED, // 99 : SPI0_MISO -> GPIO_BOARD_ID_2
CFG_DISABLED, // 100 : SPI0_SSIN -> NC_SPI0_MCK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 101 : UART0_TXD -> UART0_TXD
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 102 : UART0_RXD -> UART0_RXD
CFG_DISABLED, // 103 : SPI1_SCLK -> NC_SPI1_SCLK
/* Port 13 */
CFG_DISABLED, // 104 : SPI1_MOSI -> NC_SPI1_MOSI
CFG_DISABLED, // 105 : SPI1_MISO -> NC_SPI1_MISO
CFG_DISABLED, // 106 : SPI1_SSIN -> NC_SPI1_SSIN
CFG_DISABLED, // 107 : GPIO[20] -> NC_AP_GPIO20
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 108 : GPIO[21] -> GPIO_AP_TO_WLAN_DEVICE_WAKE
CFG_IN | INPUT_SCHMITT, // 109 : GPIO[22] -> GPIO_TRISTAR_INT
CFG_DISABLED, // 110 : GPIO[23] -> GPIO_AP_TO_OPAL_LVBOOST_BUSY_L
CFG_IN, // 111 : GPIO[24] -> GPIO_OPAL_SWDIO
/* Port 14 */
CFG_IN, // 112 : GPIO[25] -> GPIO_OPAL_SWDCLK
CFG_DISABLED, // 113 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 114 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 115 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 116 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 117 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 118 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 119 : UNSPECIFIED -> UNSPECIFIED
/* Port 15 */
CFG_DISABLED, // 120 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 121 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 122 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 123 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
/* Port 16 */
CFG_DISABLED, // 128 : ENET_MDC -> NC_ENET_MDC
CFG_DISABLED, // 129 : ENET_MDIO -> NC_ENET_MDIO
CFG_DISABLED, // 130 : RMII_RXER -> GPIO_AP_TO_ORB_DEBUG
CFG_DISABLED, // 131 : RMII_TXEN -> NC_RMII_TXEN
CFG_DISABLED, // 132 : RMII_CLK -> NC_GPIO_DEV_DISPLAY_TO_AP_ID3
CFG_DISABLED, // 133 : RMII_TXD[0] -> NC_RMII_TXD0
CFG_DISABLED, // 134 : RMII_TXD[1] -> NC_FPGA_WL_REG_ON
CFG_DISABLED, // 135 : RMII_RXD[0] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID1
/* Port 17 */
CFG_DISABLED, // 136 : RMII_RXD[1] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID2
CFG_DISABLED, // 137 : RMII_CRSDV -> NC_GPIO_DEV_DISPLAY_TO_AP_ID0
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_proto2a_dev_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_IN | INPUT_SCHMITT, // 0 : REQUEST_DFU1 -> BUTTON1_BUFF_L
CFG_IN | INPUT_SCHMITT, // 1 : REQUEST_DFU2 -> LISA_BTN_BUFF_L
CFG_FUNC0 | INPUT_SCHMITT, // 2 : DOCK_CONNECT -> DOCK_CONNECT
CFG_DISABLED, // 3 : UNSPECIFIED -> UNSPECIFIED
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 4 : SPU_UART0_TXD -> GPIO_SPU_TO_WLAN_CONTEXT_B
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 5 : SPU_UART0_RXD -> GPIO_SPU_TO_WLAN_CONTEXT_A
CFG_DISABLED, // 6 : SPU_UART0_RTSN -> NC_SPU_UART0_RTSN
CFG_DISABLED, // 7 : SPU_UART0_CTSN -> NC_SPU_UART0_CTSN
/* Port 1 */
CFG_DISABLED, // 8 : SPU_UART1_TXD -> NC_SPU_UART1_TXD
CFG_DISABLED, // 9 : SPU_UART1_RXD -> NC_SPU_UART1_RXD
CFG_DISABLED, // 10 : SPU_UART1_RTSN -> NC_SPU_UART1_RTSN
CFG_DISABLED, // 11 : SPU_UART1_CTSN -> NC_SPU_UART1_CTSN
CFG_DISABLED, // 12 : SPU_GPIO[0] -> NC_SPU_GPIO0
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 13 : SPU_GPIO[1] -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_IN | INPUT_SCHMITT, // 14 : SPU_GPIO[2] -> GPIO_BT_TO_SPU_HOST_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 15 : SPU_GPIO[3] -> GPIO_SUNFISH_TO_SPU_INT_L
/* Port 2 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 16 : SPU_GPIO[4] -> GPIO_PMU_TO_SPU_IRQ_L
CFG_DISABLED, // 17 : SPU_GPIO[5] -> NC_SPU_GPIO5
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 18 : SPU_GPIO[6] -> GPIO_SPU_TO_LVBOOST_EN
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 19 : SPU_GPIO[7] -> GPIO_BERMUDA_TO_SPU_HOST_WAKE
CFG_DISABLED, // 20 : SPU_GPIO[8] -> NC_SPU_GPIO8
CFG_OUT_0, // 21 : DFU_STATUS -> TP_DFU_STATUS
CFG_IN | PULL_DOWN, // 22 : FORCE_DFU -> TP_FORCE_DFU
CFG_FUNC0 | INPUT_SCHMITT, // 23 : PWR_GOOD -> PMU_TO_SPU_PWR_GOOD
/* Port 3 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 24 : SOC_VDD_HI_LO -> SPU_TO_PMU_VDD_HI_LO
CFG_DISABLED, // 25 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 26 : DOCK_ATTENTION -> NC_DOCK_ATTENTION
CFG_DISABLED, // 27 : PMU_HOST_WAKE -> NC_PMU_HOST_WAKE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 28 : SPU_SPI_SCLK -> SPI_SPU_SCLK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 29 : SPU_SPI_MOSI -> SPI_SPU_MOSI
CFG_FUNC0 | PULL_DOWN, // 30 : SPU_SPI_MISO -> SPI_SPU_MISO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 31 : SPU_SPI_CS_TRIG[0] -> SCM_SPU_TO_GRAPE_CS_L
/* Port 4 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 32 : SPU_SPI_CS_TRIG[1] -> SCM_GRAPE_TO_SPU_HINT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 33 : SPU_SPI_CS_TRIG[2] -> SCM_OSMIUM_TO_SPU_INT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 34 : SPU_SPI_CS_TRIG[3] -> SCM_LISA_TO_SPU_INT_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 35 : SPU_SPI_CS_TRIG[4] -> SCM_SPU_TO_CARBON_CS_L
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 36 : SPU_SPI_CS_TRIG[5] -> SCM_CARBON_TO_SPU_INT1
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 37 : SPU_SPI_CS_TRIG[6] -> SCM_CARBON_TO_SPU_INT2
CFG_DISABLED, // 38 : SPU_SPI_CS_TRIG[7] -> NC_SCM_SPU_TO_COMPASS_CS_L
CFG_DISABLED, // 39 : SPU_SPI_CS_TRIG[8] -> NC_SCM_COMPASS_TO_SPU_INT
/* Port 5 */
CFG_DISABLED, // 40 : SPU_SPI_CS_TRIG[9] -> NC_SPU_SPI_CS_TRIG9
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 41 : SPU_SPI_CS_TRIG[10] -> SCM_SPU_TO_OPAL_CS_L
CFG_DISABLED, // 42 : SPU_SPI_CS_TRIG[11] -> NC_SPU_SPI_CS_TRIG11
CFG_IN | PULL_UP | INPUT_SCHMITT, // 43 : SPU_SPI_CS_TRIG[12] -> SCM_PT_TO_SPU_INT_L
CFG_DISABLED, // 44 : SPU_SPI_CS_TRIG[13] -> NC_SPU_SPI_CS_TRIG13
CFG_DISABLED, // 45 : SPU_SPI_CS_TRIG[14] -> NC_SPU_SPI_CS_TRIG14
CFG_DISABLED, // 46 : SPU_SPI_CS_TRIG[15] -> NC_SPU_SPI_CS_TRIG15
CFG_IN | PULL_UP, // 47 : SPU_GPIO[9] -> GPIO_SEAJAY_TO_SPU_PING_DET_L
/* Port 6 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 48 : SPU_I2C_SDA -> I2C_SPU_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 49 : SPU_I2C_SCL -> I2C_SPU_1V8_SCL
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
struct pinconfig_map {
uint32_t board_id;
uint32_t board_id_mask;
const uint32_t *pinconfigs[GPIOC_COUNT];
};
static const struct pinconfig_map cfg_map[] = {
{ 0, 1, { pinconfig_proto2a_ap_0, pinconfig_proto2a_ap_1 } },
{ 1, 1, { pinconfig_proto2a_dev_0, pinconfig_proto2a_dev_1 } },
};
const uint32_t * target_get_proto2a_gpio_cfg(int gpioc)
{
static const struct pinconfig_map *selected_map = NULL;
if (selected_map == NULL) {
uint32_t board_id = platform_get_board_id();
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
selected_map = &cfg_map[i];
break;
}
}
if (selected_map == NULL)
panic("no default pinconfig for board id %u", board_id);
}
ASSERT(gpioc < GPIOC_COUNT);
return selected_map->pinconfigs[gpioc];
}
target/ipod6/pinconfig_proto2b.c
+566
View File
@@ -0,0 +1,566 @@
/*
* Copyright (C) 2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
I/O Spreadsheet version: rev 0.3.6
I/O Spreadsheet tracker: 15171729
Conversion command: csvtopinconfig.py --soc m7 --radar 15171729 --prefix proto2b <filename>
*/
#include <debug.h>
#include <drivers/apple/gpio.h>
#include <platform.h>
#include <platform/soc/hwregbase.h>
#include <stdint.h>
static const uint32_t pinconfig_proto2b_ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // 0 : I2S0_MCK -> GPIO_AP_TO_BERMUDA_CLK_XTAL1
CFG_FUNC0 | SLOW_SLEW, // 1 : I2S1_MCK -> I2S1_AP_TO_CODEC_MCLK_12M
CFG_FUNC0 | SLOW_SLEW, // 2 : SD_CLKOUT -> SDIO_AP_TO_WLAN_CLK
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 3 : SD_CMD_IO -> SDIO_AP_BI_WLAN_CMD
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 4 : SD_DATA_IO[0] -> SDIO_AP_BI_WLAN_DATA0
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 5 : SD_DATA_IO[1] -> SDIO_AP_BI_WLAN_DATA1
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 6 : SD_DATA_IO[2] -> SDIO_AP_BI_WLAN_DATA2
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 7 : SD_DATA_IO[3] -> SDIO_AP_BI_WLAN_DATA3
/* Port 1 */
CFG_FUNC0 | INPUT_SCHMITT, // 8 : SDIO_IRQ -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 9 : WL_HOST_WAKE -> GPIO_WLAN_TO_AP_IRQ
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 2 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 3 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 4 */
CFG_DISABLED, // 32 : GPIO[0] -> NC_AP_GPIO0
CFG_DISABLED, // 33 : GPIO[1] -> NC_AP_GPIO1
CFG_DISABLED, // 34 : GPIO[2] -> GPIO_BOOT_CONFIG_0
CFG_DISABLED, // 35 : GPIO[3] -> PP1V8_SW3C_SNS
CFG_DISABLED, // 36 : GPIO[4] -> NC_GPIO_BOOT_CONFIG_2
CFG_DISABLED, // 37 : GPIO[5] -> NC_GPIO_BOOT_CONFIG_3
CFG_DISABLED, // 38 : GPIO[6] -> GPIO_BOARD_ID_3
CFG_DISABLED, // 39 : GPIO[7] -> GPIO_BOARD_REV_0
/* Port 5 */
CFG_DISABLED, // 40 : GPIO[8] -> GPIO_BOARD_REV_1
CFG_DISABLED, // 41 : GPIO[9] -> GPIO_BOARD_REV_2
CFG_DISABLED, // 42 : GPIO[10] -> GPIO_BOARD_REV_3
CFG_DISABLED, // 43 : GPIO[11] -> NC_GPIO_DEV_BOOST_ALT_ID
CFG_OUT_0 | SLOW_SLEW, // 44 : GPIO[12] -> GPIO_AP_TO_BT_DEVICE_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 45 : GPIO[13] -> GPIO_CODEC_TO_AP_IRQ_L
CFG_DISABLED, // 46 : GPIO[14] -> NC_AP_GPIO14
CFG_OUT_0 | SLOW_SLEW, // 47 : GPIO[15] -> GPIO_AP_TO_BERMUDA_FW_DWLD_REQ
/* Port 6 */
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 48 : I2C1_SDA -> I2C1_AP_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 49 : I2C1_SCL -> I2C1_AP_1V8_SCL
CFG_DISABLED, // 50 : I2S0_LRCK -> NC_I2S0_LRCLK
CFG_DISABLED, // 51 : I2S0_BCLK -> NC_I2S0_BCLK
CFG_DISABLED, // 52 : I2S0_DOUT -> NC_I2S0_DOUT
CFG_DISABLED, // 53 : I2S0_DIN -> NC_I2S0_DIN
CFG_FUNC0, // 54 : I2S1_LRCK -> I2S1_CODEC_TO_AP_WCLK
CFG_FUNC0, // 55 : I2S1_BCLK -> I2S1_CODEC_TO_AP_BCLK
/* Port 7 */
CFG_FUNC0 | SLOW_SLEW, // 56 : I2S1_DOUT -> I2S1_AP_TO_CODEC_DATA
CFG_FUNC0, // 57 : I2S1_DIN -> I2S1_CODEC_TO_AP_DATA
CFG_FUNC0 | SLOW_SLEW, // 58 : UART1_TXD -> UART1_AP_TO_BT_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 59 : UART1_RXD -> UART1_BT_TO_AP_RXD
CFG_FUNC0 | SLOW_SLEW, // 60 : UART1_RTSN -> UART1_AP_TO_BT_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 61 : UART1_CTSN -> UART1_BT_TO_AP_CTS_L
CFG_FUNC0 | SLOW_SLEW, // 62 : UART2_TXD -> UART2_AP_TO_BERMUDA_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 63 : UART2_RXD -> UART2_BERMUDA_TO_AP_RXD
/* Port 8 */
CFG_FUNC0 | SLOW_SLEW, // 64 : UART2_RTSN -> UART2_AP_TO_BERMUDA_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 65 : UART2_CTSN -> UART2_BERMUDA_TO_AP_CTS_L
CFG_FUNC0 | SLOW_SLEW, // 66 : UART4_TXD -> UART4_AP_TO_WLAN_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 67 : UART4_RXD -> UART4_WLAN_TO_AP_RXD
CFG_FUNC0 | SLOW_SLEW, // 68 : UART3_RTXD -> UART3_AP_BI_GG_SWI
CFG_DISABLED, // 69 : CLK32K_OUT -> NC_CLK32K_OUT
CFG_DISABLED, // 70 : TST_CLKOUT -> AP_TST_CLKOUT
CFG_DISABLED, // 71 : GPIO[16] -> NC_AP_GPIO16
/* Port 9 */
CFG_DISABLED, // 72 : GPIO[17] -> TP_AP_GPIO17
CFG_DISABLED, // 73 : GPIO[18] -> GPIO_GRAPE_SWDCLK
CFG_DISABLED, // 74 : TMR32_PWM1 -> NC_TMR32_PWM1
CFG_DISABLED, // 75 : TMR32_PWM2 -> NC_TMR32_PWM2
CFG_FUNC0, // 76 : TMR32_PWM0 -> PMU_VDD_OK
CFG_FUNC0, // 77 : DISP_TE -> DISP_BSYNC
CFG_DISABLED, // 78 : GPIO[19] -> GPIO_GRAPE_SWDIO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 79 : NAND_CEN[0] -> ANC_AP_TO_NAND_CEN<0>
/* Port 10 */
CFG_DISABLED, // 80 : NAND_CEN[1] -> NC_NAND_CEN1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 81 : NAND_IO[7] -> ANC_AP_BI_NAND_IO<7>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 82 : NAND_IO[6] -> ANC_AP_BI_NAND_IO<6>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 83 : NAND_IO[5] -> ANC_AP_BI_NAND_IO<5>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 84 : NAND_IO[4] -> ANC_AP_BI_NAND_IO<4>
CFG_DISABLED, // 85 : NAND_DQS -> NC_NAND_DQS
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 86 : NAND_REN -> ANC_AP_TO_NAND_RE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 87 : NAND_IO[3] -> ANC_AP_BI_NAND_IO<3>
/* Port 11 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 88 : NAND_IO[2] -> ANC_AP_BI_NAND_IO<2>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 89 : NAND_IO[1] -> ANC_AP_BI_NAND_IO<1>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 90 : NAND_IO[0] -> ANC_AP_BI_NAND_IO<0>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 91 : NAND_WEN -> ANC_AP_TO_NAND_WE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 92 : NAND_CLE -> ANC_AP_TO_NAND_CLE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 93 : NAND_ALE -> ANC_AP_TO_NAND_ALE
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 94 : I2C0_SDA -> I2C0_AP_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 95 : I2C0_SCL -> I2C0_AP_1V8_SCL
/* Port 12 */
CFG_DISABLED, // 96 : DISP_VSYNC -> NC_DISP_VSYNC
CFG_DISABLED, // 97 : SPI0_SCLK -> NC_GPIO_BOARD_ID_0
CFG_DISABLED, // 98 : SPI0_MOSI -> GPIO_BOARD_ID_1
CFG_DISABLED, // 99 : SPI0_MISO -> GPIO_BOARD_ID_2
CFG_DISABLED, // 100 : SPI0_SSIN -> NC_SPI0_MCK
CFG_FUNC0 | SLOW_SLEW, // 101 : UART0_TXD -> UART0_TXD
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 102 : UART0_RXD -> UART0_RXD
CFG_DISABLED, // 103 : SPI1_SCLK -> NC_SPI1_SCLK
/* Port 13 */
CFG_DISABLED, // 104 : SPI1_MOSI -> NC_SPI1_MOSI
CFG_DISABLED, // 105 : SPI1_MISO -> NC_SPI1_MISO
CFG_DISABLED, // 106 : SPI1_SSIN -> NC_SPI1_SSIN
CFG_DISABLED, // 107 : GPIO[20] -> NC_AP_GPIO20
CFG_OUT_0 | SLOW_SLEW, // 108 : GPIO[21] -> GPIO_AP_TO_WLAN_DEVICE_WAKE
CFG_IN | INPUT_SCHMITT, // 109 : GPIO[22] -> GPIO_TRISTAR_INT
CFG_DISABLED, // 110 : GPIO[23] -> GPIO_AP_TO_OPAL_LVBOOST_BUSY_L
CFG_IN, // 111 : GPIO[24] -> GPIO_OPAL_SWDIO
/* Port 14 */
CFG_IN, // 112 : GPIO[25] -> GPIO_OPAL_SWDCLK
CFG_DISABLED, // 113 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 114 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 115 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 116 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 117 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 118 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 119 : UNSPECIFIED -> UNSPECIFIED
/* Port 15 */
CFG_DISABLED, // 120 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 121 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 122 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 123 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
/* Port 16 */
CFG_DISABLED, // 128 : ENET_MDC -> NC_ENET_MDC
CFG_DISABLED, // 129 : ENET_MDIO -> NC_ENET_MDIO
CFG_DISABLED, // 130 : RMII_RXER -> GPIO_AP_TO_ORB_DEBUG
CFG_DISABLED, // 131 : RMII_TXEN -> NC_RMII_TXEN
CFG_DISABLED, // 132 : RMII_CLK -> NC_GPIO_DEV_DISPLAY_TO_AP_ID3
CFG_DISABLED, // 133 : RMII_TXD[0] -> NC_RMII_TXD0
CFG_DISABLED, // 134 : RMII_TXD[1] -> NC_FPGA_WL_REG_ON
CFG_DISABLED, // 135 : RMII_RXD[0] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID1
/* Port 17 */
CFG_DISABLED, // 136 : RMII_RXD[1] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID2
CFG_DISABLED, // 137 : RMII_CRSDV -> NC_GPIO_DEV_DISPLAY_TO_AP_ID0
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_proto2b_ap_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_IN | INPUT_SCHMITT, // 0 : REQUEST_DFU1 -> BUTTON1_BUFF_L
CFG_IN | INPUT_SCHMITT, // 1 : REQUEST_DFU2 -> LISA_BTN_BUFF_L
CFG_FUNC0 | INPUT_SCHMITT, // 2 : DOCK_CONNECT -> DOCK_CONNECT
CFG_DISABLED | INPUT_SCHMITT, // 3 : CLK32K_IN -> GPIO_PMU_TO_SPU_CLK32K_IN
CFG_OUT_0 | SLOW_SLEW, // 4 : SPU_UART0_TXD -> GPIO_SPU_TO_WLAN_CONTEXT_B
CFG_OUT_0 | SLOW_SLEW, // 5 : SPU_UART0_RXD -> GPIO_SPU_TO_WLAN_CONTEXT_A
CFG_DISABLED, // 6 : SPU_UART0_RTSN -> NC_SPU_UART0_RTSN
CFG_DISABLED, // 7 : SPU_UART0_CTSN -> NC_SPU_UART0_CTSN
/* Port 1 */
CFG_DISABLED, // 8 : SPU_UART1_TXD -> NC_SPU_UART1_TXD
CFG_DISABLED, // 9 : SPU_UART1_RXD -> NC_SPU_UART1_RXD
CFG_DISABLED, // 10 : SPU_UART1_RTSN -> NC_SPU_UART1_RTSN
CFG_DISABLED, // 11 : SPU_UART1_CTSN -> NC_SPU_UART1_CTSN
CFG_DISABLED, // 12 : SPU_GPIO[0] -> NC_SPU_GPIO0
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 13 : SPU_GPIO[1] -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_IN | INPUT_SCHMITT, // 14 : SPU_GPIO[2] -> GPIO_BT_TO_SPU_HOST_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 15 : SPU_GPIO[3] -> GPIO_SUNFISH_TO_SPU_INT_L
/* Port 2 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 16 : SPU_GPIO[4] -> GPIO_PMU_TO_SPU_IRQ_L
CFG_OUT_0 | SLOW_SLEW, // 17 : SPU_GPIO[5] -> GPIO_AP_TO_SEAJAY_RESET
CFG_OUT_0 | SLOW_SLEW, // 18 : SPU_GPIO[6] -> GPIO_SPU_TO_LVBOOST_EN
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 19 : SPU_GPIO[7] -> GPIO_BERMUDA_TO_SPU_HOST_WAKE
CFG_DISABLED, // 20 : SPU_GPIO[8] -> NC_SPU_GPIO8
CFG_OUT_0, // 21 : DFU_STATUS -> TP_DFU_STATUS
CFG_IN | PULL_DOWN, // 22 : FORCE_DFU -> TP_FORCE_DFU
CFG_FUNC0 | INPUT_SCHMITT, // 23 : PWR_GOOD -> PMU_TO_SPU_PWR_GOOD
/* Port 3 */
CFG_FUNC0 | SLOW_SLEW, // 24 : SOC_VDD_HI_LO -> SPU_TO_PMU_VDD_HI_LO
CFG_DISABLED, // 25 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 26 : DOCK_ATTENTION -> NC_DOCK_ATTENTION
CFG_DISABLED, // 27 : PMU_HOST_WAKE -> NC_PMU_HOST_WAKE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 28 : SPU_SPI_SCLK -> SPI_SPU_SCLK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 29 : SPU_SPI_MOSI -> SPI_SPU_MOSI
CFG_FUNC0 | PULL_DOWN, // 30 : SPU_SPI_MISO -> SPI_SPU_MISO
CFG_FUNC0 | SLOW_SLEW, // 31 : SPU_SPI_CS_TRIG[0] -> SCM_SPU_TO_GRAPE_CS_L
/* Port 4 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 32 : SPU_SPI_CS_TRIG[1] -> SCM_GRAPE_TO_SPU_HINT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 33 : SPU_SPI_CS_TRIG[2] -> SCM_OSMIUM_TO_SPU_INT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 34 : SPU_SPI_CS_TRIG[3] -> SCM_LISA_TO_SPU_INT_L
CFG_FUNC0 | SLOW_SLEW, // 35 : SPU_SPI_CS_TRIG[4] -> SCM_SPU_TO_CARBON_CS_L
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 36 : SPU_SPI_CS_TRIG[5] -> SCM_CARBON_TO_SPU_INT1
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 37 : SPU_SPI_CS_TRIG[6] -> SCM_CARBON_TO_SPU_INT2
CFG_DISABLED, // 38 : SPU_SPI_CS_TRIG[7] -> NC_SCM_SPU_TO_COMPASS_CS_L
CFG_DISABLED, // 39 : SPU_SPI_CS_TRIG[8] -> NC_SCM_COMPASS_TO_SPU_INT
/* Port 5 */
CFG_DISABLED, // 40 : SPU_SPI_CS_TRIG[9] -> NC_SPU_SPI_CS_TRIG9
CFG_FUNC0 | SLOW_SLEW, // 41 : SPU_SPI_CS_TRIG[10] -> SCM_SPU_TO_OPAL_CS_L
CFG_DISABLED, // 42 : SPU_SPI_CS_TRIG[11] -> NC_SPU_SPI_CS_TRIG11
CFG_IN | PULL_UP | INPUT_SCHMITT, // 43 : SPU_SPI_CS_TRIG[12] -> SCM_PT_TO_SPU_INT_L
CFG_DISABLED, // 44 : SPU_SPI_CS_TRIG[13] -> NC_SPU_SPI_CS_TRIG13
CFG_DISABLED, // 45 : SPU_SPI_CS_TRIG[14] -> NC_SPU_SPI_CS_TRIG14
CFG_DISABLED, // 46 : SPU_SPI_CS_TRIG[15] -> NC_SPU_SPI_CS_TRIG15
CFG_IN | PULL_UP, // 47 : SPU_GPIO[9] -> GPIO_SEAJAY_TO_SPU_PING_DET_L
/* Port 6 */
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 48 : SPU_I2C_SDA -> I2C_SPU_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 49 : SPU_I2C_SCL -> I2C_SPU_1V8_SCL
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_proto2b_dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // 0 : I2S0_MCK -> GPIO_AP_TO_BERMUDA_CLK_XTAL1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 1 : I2S1_MCK -> I2S1_AP_TO_CODEC_MCLK_12M
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : SD_CLKOUT -> SDIO_AP_TO_WLAN_CLK
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 3 : SD_CMD_IO -> SDIO_AP_BI_WLAN_CMD
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 4 : SD_DATA_IO[0] -> SDIO_AP_BI_WLAN_DATA0
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 5 : SD_DATA_IO[1] -> SDIO_AP_BI_WLAN_DATA1
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 6 : SD_DATA_IO[2] -> SDIO_AP_BI_WLAN_DATA2
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 7 : SD_DATA_IO[3] -> SDIO_AP_BI_WLAN_DATA3
/* Port 1 */
CFG_FUNC0 | INPUT_SCHMITT, // 8 : SDIO_IRQ -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 9 : WL_HOST_WAKE -> GPIO_WLAN_TO_AP_IRQ
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 2 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 3 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 4 */
CFG_DISABLED, // 32 : GPIO[0] -> NC_AP_GPIO0
CFG_DISABLED, // 33 : GPIO[1] -> NC_AP_GPIO1
CFG_DISABLED, // 34 : GPIO[2] -> GPIO_BOOT_CONFIG_0
CFG_DISABLED, // 35 : GPIO[3] -> PP1V8_SW3C_SNS
CFG_DISABLED, // 36 : GPIO[4] -> NC_GPIO_BOOT_CONFIG_2
CFG_DISABLED, // 37 : GPIO[5] -> NC_GPIO_BOOT_CONFIG_3
CFG_DISABLED, // 38 : GPIO[6] -> GPIO_BOARD_ID_3
CFG_DISABLED, // 39 : GPIO[7] -> GPIO_BOARD_REV_0
/* Port 5 */
CFG_DISABLED, // 40 : GPIO[8] -> GPIO_BOARD_REV_1
CFG_DISABLED, // 41 : GPIO[9] -> GPIO_BOARD_REV_2
CFG_DISABLED, // 42 : GPIO[10] -> GPIO_BOARD_REV_3
CFG_DISABLED, // 43 : GPIO[11] -> NC_GPIO_DEV_BOOST_ALT_ID
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 44 : GPIO[12] -> GPIO_AP_TO_BT_DEVICE_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 45 : GPIO[13] -> GPIO_CODEC_TO_AP_IRQ_L
CFG_DISABLED, // 46 : GPIO[14] -> NC_AP_GPIO14
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 47 : GPIO[15] -> GPIO_AP_TO_BERMUDA_FW_DWLD_REQ
/* Port 6 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 48 : I2C1_SDA -> I2C1_AP_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 49 : I2C1_SCL -> I2C1_AP_1V8_SCL
CFG_DISABLED, // 50 : I2S0_LRCK -> NC_I2S0_LRCLK
CFG_DISABLED, // 51 : I2S0_BCLK -> NC_I2S0_BCLK
CFG_DISABLED, // 52 : I2S0_DOUT -> NC_I2S0_DOUT
CFG_DISABLED, // 53 : I2S0_DIN -> NC_I2S0_DIN
CFG_FUNC0, // 54 : I2S1_LRCK -> I2S1_CODEC_TO_AP_WCLK
CFG_FUNC0, // 55 : I2S1_BCLK -> I2S1_CODEC_TO_AP_BCLK
/* Port 7 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 56 : I2S1_DOUT -> I2S1_AP_TO_CODEC_DATA
CFG_FUNC0, // 57 : I2S1_DIN -> I2S1_CODEC_TO_AP_DATA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 58 : UART1_TXD -> UART1_AP_TO_BT_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 59 : UART1_RXD -> UART1_BT_TO_AP_RXD
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 60 : UART1_RTSN -> UART1_AP_TO_BT_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 61 : UART1_CTSN -> UART1_BT_TO_AP_CTS_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 62 : UART2_TXD -> UART2_AP_TO_BERMUDA_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 63 : UART2_RXD -> UART2_BERMUDA_TO_AP_RXD
/* Port 8 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 64 : UART2_RTSN -> UART2_AP_TO_BERMUDA_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 65 : UART2_CTSN -> UART2_BERMUDA_TO_AP_CTS_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : UART4_TXD -> UART4_AP_TO_WLAN_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 67 : UART4_RXD -> UART4_WLAN_TO_AP_RXD
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 68 : UART3_RTXD -> UART3_AP_BI_GG_SWI
CFG_DISABLED, // 69 : CLK32K_OUT -> NC_CLK32K_OUT
CFG_DISABLED, // 70 : TST_CLKOUT -> AP_TST_CLKOUT
CFG_DISABLED, // 71 : GPIO[16] -> NC_AP_GPIO16
/* Port 9 */
CFG_DISABLED, // 72 : GPIO[17] -> TP_AP_GPIO17
CFG_DISABLED, // 73 : GPIO[18] -> GPIO_GRAPE_SWDCLK
CFG_DISABLED, // 74 : TMR32_PWM1 -> NC_TMR32_PWM1
CFG_DISABLED, // 75 : TMR32_PWM2 -> NC_TMR32_PWM2
CFG_FUNC0, // 76 : TMR32_PWM0 -> PMU_VDD_OK
CFG_FUNC0, // 77 : DISP_TE -> DISP_BSYNC
CFG_DISABLED, // 78 : GPIO[19] -> GPIO_GRAPE_SWDIO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 79 : NAND_CEN[0] -> ANC_AP_TO_NAND_CEN<0>
/* Port 10 */
CFG_DISABLED, // 80 : NAND_CEN[1] -> NC_NAND_CEN1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 81 : NAND_IO[7] -> ANC_AP_BI_NAND_IO<7>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 82 : NAND_IO[6] -> ANC_AP_BI_NAND_IO<6>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 83 : NAND_IO[5] -> ANC_AP_BI_NAND_IO<5>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 84 : NAND_IO[4] -> ANC_AP_BI_NAND_IO<4>
CFG_DISABLED, // 85 : NAND_DQS -> NC_NAND_DQS
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 86 : NAND_REN -> ANC_AP_TO_NAND_RE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 87 : NAND_IO[3] -> ANC_AP_BI_NAND_IO<3>
/* Port 11 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 88 : NAND_IO[2] -> ANC_AP_BI_NAND_IO<2>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 89 : NAND_IO[1] -> ANC_AP_BI_NAND_IO<1>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 90 : NAND_IO[0] -> ANC_AP_BI_NAND_IO<0>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 91 : NAND_WEN -> ANC_AP_TO_NAND_WE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 92 : NAND_CLE -> ANC_AP_TO_NAND_CLE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 93 : NAND_ALE -> ANC_AP_TO_NAND_ALE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 94 : I2C0_SDA -> I2C0_AP_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 95 : I2C0_SCL -> I2C0_AP_1V8_SCL
/* Port 12 */
CFG_DISABLED, // 96 : DISP_VSYNC -> NC_DISP_VSYNC
CFG_DISABLED, // 97 : SPI0_SCLK -> NC_GPIO_BOARD_ID_0
CFG_DISABLED, // 98 : SPI0_MOSI -> GPIO_BOARD_ID_1
CFG_DISABLED, // 99 : SPI0_MISO -> GPIO_BOARD_ID_2
CFG_DISABLED, // 100 : SPI0_SSIN -> NC_SPI0_MCK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 101 : UART0_TXD -> UART0_TXD
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 102 : UART0_RXD -> UART0_RXD
CFG_DISABLED, // 103 : SPI1_SCLK -> NC_SPI1_SCLK
/* Port 13 */
CFG_DISABLED, // 104 : SPI1_MOSI -> NC_SPI1_MOSI
CFG_DISABLED, // 105 : SPI1_MISO -> NC_SPI1_MISO
CFG_DISABLED, // 106 : SPI1_SSIN -> NC_SPI1_SSIN
CFG_DISABLED, // 107 : GPIO[20] -> NC_AP_GPIO20
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 108 : GPIO[21] -> GPIO_AP_TO_WLAN_DEVICE_WAKE
CFG_IN | INPUT_SCHMITT, // 109 : GPIO[22] -> GPIO_TRISTAR_INT
CFG_DISABLED, // 110 : GPIO[23] -> GPIO_AP_TO_OPAL_LVBOOST_BUSY_L
CFG_IN, // 111 : GPIO[24] -> GPIO_OPAL_SWDIO
/* Port 14 */
CFG_IN, // 112 : GPIO[25] -> GPIO_OPAL_SWDCLK
CFG_DISABLED, // 113 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 114 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 115 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 116 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 117 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 118 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 119 : UNSPECIFIED -> UNSPECIFIED
/* Port 15 */
CFG_DISABLED, // 120 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 121 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 122 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 123 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
/* Port 16 */
CFG_DISABLED, // 128 : ENET_MDC -> NC_ENET_MDC
CFG_DISABLED, // 129 : ENET_MDIO -> NC_ENET_MDIO
CFG_DISABLED, // 130 : RMII_RXER -> GPIO_AP_TO_ORB_DEBUG
CFG_DISABLED, // 131 : RMII_TXEN -> NC_RMII_TXEN
CFG_DISABLED, // 132 : RMII_CLK -> NC_GPIO_DEV_DISPLAY_TO_AP_ID3
CFG_DISABLED, // 133 : RMII_TXD[0] -> NC_RMII_TXD0
CFG_DISABLED, // 134 : RMII_TXD[1] -> NC_FPGA_WL_REG_ON
CFG_DISABLED, // 135 : RMII_RXD[0] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID1
/* Port 17 */
CFG_DISABLED, // 136 : RMII_RXD[1] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID2
CFG_DISABLED, // 137 : RMII_CRSDV -> NC_GPIO_DEV_DISPLAY_TO_AP_ID0
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_proto2b_dev_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_IN | INPUT_SCHMITT, // 0 : REQUEST_DFU1 -> BUTTON1_BUFF_L
CFG_IN | INPUT_SCHMITT, // 1 : REQUEST_DFU2 -> LISA_BTN_BUFF_L
CFG_FUNC0 | INPUT_SCHMITT, // 2 : DOCK_CONNECT -> DOCK_CONNECT
CFG_DISABLED | INPUT_SCHMITT, // 3 : CLK32K_IN -> GPIO_PMU_TO_SPU_CLK32K_IN
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 4 : SPU_UART0_TXD -> GPIO_SPU_TO_WLAN_CONTEXT_B
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 5 : SPU_UART0_RXD -> GPIO_SPU_TO_WLAN_CONTEXT_A
CFG_DISABLED, // 6 : SPU_UART0_RTSN -> NC_SPU_UART0_RTSN
CFG_DISABLED, // 7 : SPU_UART0_CTSN -> NC_SPU_UART0_CTSN
/* Port 1 */
CFG_DISABLED, // 8 : SPU_UART1_TXD -> NC_SPU_UART1_TXD
CFG_DISABLED, // 9 : SPU_UART1_RXD -> NC_SPU_UART1_RXD
CFG_DISABLED, // 10 : SPU_UART1_RTSN -> NC_SPU_UART1_RTSN
CFG_DISABLED, // 11 : SPU_UART1_CTSN -> NC_SPU_UART1_CTSN
CFG_DISABLED, // 12 : SPU_GPIO[0] -> NC_SPU_GPIO0
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 13 : SPU_GPIO[1] -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_IN | INPUT_SCHMITT, // 14 : SPU_GPIO[2] -> GPIO_BT_TO_SPU_HOST_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 15 : SPU_GPIO[3] -> GPIO_SUNFISH_TO_SPU_INT_L
/* Port 2 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 16 : SPU_GPIO[4] -> GPIO_PMU_TO_SPU_IRQ_L
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 17 : SPU_GPIO[5] -> GPIO_AP_TO_SEAJAY_RESET
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 18 : SPU_GPIO[6] -> GPIO_SPU_TO_LVBOOST_EN
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 19 : SPU_GPIO[7] -> GPIO_BERMUDA_TO_SPU_HOST_WAKE
CFG_DISABLED, // 20 : SPU_GPIO[8] -> NC_SPU_GPIO8
CFG_OUT_0, // 21 : DFU_STATUS -> TP_DFU_STATUS
CFG_IN | PULL_DOWN, // 22 : FORCE_DFU -> TP_FORCE_DFU
CFG_FUNC0 | INPUT_SCHMITT, // 23 : PWR_GOOD -> PMU_TO_SPU_PWR_GOOD
/* Port 3 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 24 : SOC_VDD_HI_LO -> SPU_TO_PMU_VDD_HI_LO
CFG_DISABLED, // 25 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 26 : DOCK_ATTENTION -> NC_DOCK_ATTENTION
CFG_DISABLED, // 27 : PMU_HOST_WAKE -> NC_PMU_HOST_WAKE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 28 : SPU_SPI_SCLK -> SPI_SPU_SCLK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 29 : SPU_SPI_MOSI -> SPI_SPU_MOSI
CFG_FUNC0 | PULL_DOWN, // 30 : SPU_SPI_MISO -> SPI_SPU_MISO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 31 : SPU_SPI_CS_TRIG[0] -> SCM_SPU_TO_GRAPE_CS_L
/* Port 4 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 32 : SPU_SPI_CS_TRIG[1] -> SCM_GRAPE_TO_SPU_HINT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 33 : SPU_SPI_CS_TRIG[2] -> SCM_OSMIUM_TO_SPU_INT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 34 : SPU_SPI_CS_TRIG[3] -> SCM_LISA_TO_SPU_INT_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 35 : SPU_SPI_CS_TRIG[4] -> SCM_SPU_TO_CARBON_CS_L
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 36 : SPU_SPI_CS_TRIG[5] -> SCM_CARBON_TO_SPU_INT1
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 37 : SPU_SPI_CS_TRIG[6] -> SCM_CARBON_TO_SPU_INT2
CFG_DISABLED, // 38 : SPU_SPI_CS_TRIG[7] -> NC_SCM_SPU_TO_COMPASS_CS_L
CFG_DISABLED, // 39 : SPU_SPI_CS_TRIG[8] -> NC_SCM_COMPASS_TO_SPU_INT
/* Port 5 */
CFG_DISABLED, // 40 : SPU_SPI_CS_TRIG[9] -> NC_SPU_SPI_CS_TRIG9
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 41 : SPU_SPI_CS_TRIG[10] -> SCM_SPU_TO_OPAL_CS_L
CFG_DISABLED, // 42 : SPU_SPI_CS_TRIG[11] -> NC_SPU_SPI_CS_TRIG11
CFG_IN | PULL_UP | INPUT_SCHMITT, // 43 : SPU_SPI_CS_TRIG[12] -> SCM_PT_TO_SPU_INT_L
CFG_DISABLED, // 44 : SPU_SPI_CS_TRIG[13] -> NC_SPU_SPI_CS_TRIG13
CFG_DISABLED, // 45 : SPU_SPI_CS_TRIG[14] -> NC_SPU_SPI_CS_TRIG14
CFG_DISABLED, // 46 : SPU_SPI_CS_TRIG[15] -> NC_SPU_SPI_CS_TRIG15
CFG_IN | PULL_UP, // 47 : SPU_GPIO[9] -> GPIO_SEAJAY_TO_SPU_PING_DET_L
/* Port 6 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 48 : SPU_I2C_SDA -> I2C_SPU_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 49 : SPU_I2C_SCL -> I2C_SPU_1V8_SCL
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
struct pinconfig_map {
uint32_t board_id;
uint32_t board_id_mask;
const uint32_t *pinconfigs[GPIOC_COUNT];
};
static const struct pinconfig_map cfg_map[] = {
{ 0, 1, { pinconfig_proto2b_ap_0, pinconfig_proto2b_ap_1 } },
{ 1, 1, { pinconfig_proto2b_dev_0, pinconfig_proto2b_dev_1 } },
};
const uint32_t * target_get_proto2b_gpio_cfg(int gpioc)
{
static const struct pinconfig_map *selected_map = NULL;
if (selected_map == NULL) {
uint32_t board_id = platform_get_board_id();
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
selected_map = &cfg_map[i];
break;
}
}
if (selected_map == NULL)
panic("no default pinconfig for board id %u", board_id);
}
ASSERT(gpioc < GPIOC_COUNT);
return selected_map->pinconfigs[gpioc];
}
target/ipod6/pinconfig_sim.c
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/*
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <debug.h>
#include <drivers/apple/gpio.h>
#include <platform/soc/hwregbase.h>
#include <target.h>
/* S7002 Target Pin Configuration */
static const uint32_t gpio_default_cfg[GPIO_0_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // I2S0_MCK ->
CFG_DISABLED, // I2S1_MCK ->
CFG_DISABLED, // SD_CLKOUT ->
CFG_DISABLED, // SD_CMD_IO ->
CFG_DISABLED, // SD_DATA_IO[0] ->
CFG_DISABLED, // SD_DATA_IO[1] ->
CFG_DISABLED, // SD_DATA_IO[2] ->
CFG_DISABLED, // SD_DATA_IO[3] ->
/* Port 1 */
CFG_DISABLED, // SDIO_IRQ ->
CFG_DISABLED, // WL_HOST_WAKE ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 2 */
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 3 */
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 4 */
CFG_DISABLED, // GPIO0 ->
CFG_DISABLED, // GPIO1 ->
CFG_DISABLED, // GPIO2 -> BOOT_CONFIG[0]
CFG_DISABLED, // GPIO3 -> BOOT_CONFIG[1]
CFG_DISABLED, // GPIO4 -> BOOT_CONFIG[2]
CFG_DISABLED, // GPIO5 -> BOOT_CONFIG[3]
CFG_DISABLED, // GPIO6 -> BOARD_ID[3]
CFG_DISABLED, // GPIO7 ->
/* Port 5 */
CFG_DISABLED, // GPIO8 ->
CFG_DISABLED, // GPIO9 ->
CFG_DISABLED, // GPIO10 ->
CFG_DISABLED, // GPIO11 ->
CFG_DISABLED, // GPIO12 ->
CFG_DISABLED, // GPIO13 ->
CFG_DISABLED, // GPIO14 ->
CFG_DISABLED, // GPIO15 ->
/* Port 6 */
CFG_DISABLED, // I2C1_SDA ->
CFG_DISABLED, // I2C1_SCL ->
CFG_DISABLED, // I2S0_LRCK ->
CFG_DISABLED, // I2S0_BCLK ->
CFG_DISABLED, // I2S0_DOUT ->
CFG_DISABLED, // I2S0_DIN ->
CFG_DISABLED, // I2S1_LRCK ->
CFG_DISABLED, // I2S1_BCLK ->
/* Port 7 */
CFG_DISABLED, // I2S1_DOUT ->
CFG_DISABLED, // I2S1_DIN ->
CFG_DISABLED, // UART1_TXD ->
CFG_DISABLED, // UART1_RXD ->
CFG_DISABLED, // UART1_RTSN ->
CFG_DISABLED, // UART1_CTSN ->
CFG_DISABLED, // UART2_TXD ->
CFG_DISABLED, // UART2_RXD ->
/* Port 8 */
CFG_DISABLED, // UART2_RTSN ->
CFG_DISABLED, // UART2_CTSN ->
CFG_DISABLED, // UART4_TXD ->
CFG_DISABLED, // UART4_RXD ->
CFG_DISABLED, // UART3_RTXD ->
CFG_DISABLED, // CLK32K_OUT ->
CFG_DISABLED, // TEST_CLKOUT ->
CFG_DISABLED, // GPIO16 ->
/* Port 9 */
CFG_DISABLED, // GPIO17 ->
CFG_DISABLED, // GPIO18 ->
CFG_DISABLED, // TMR32_PWM1 ->
CFG_DISABLED, // TMR32_PWM2 ->
CFG_DISABLED, // TMR32_PWM3 ->
CFG_DISABLED, // DISP_TE ->
CFG_DISABLED, // GPIO19 ->
CFG_DISABLED, // NAND_CEN[0] ->
/* Port 10 */
CFG_DISABLED, // NAND_CEN[1] ->
CFG_DISABLED, // NAND_IO[7] ->
CFG_DISABLED, // NAND_IO[6] ->
CFG_DISABLED, // NAND_IO[5] ->
CFG_DISABLED, // NAND_IO[4] ->
CFG_DISABLED, // NAND_DQS ->
CFG_DISABLED, // NAND_REN ->
CFG_DISABLED, // NAND_IO[3] ->
/* Port 11 */
CFG_DISABLED, // NAND_IO[2] ->
CFG_DISABLED, // NAND_IO[1] ->
CFG_DISABLED, // NAND_IO[0] ->
CFG_DISABLED, // NAND_WEN ->
CFG_DISABLED, // NAND_CLE ->
CFG_DISABLED, // NAND_ALE ->
CFG_DISABLED, // I2C0_SDA ->
CFG_DISABLED, // I2C0_SCL ->
/* Port 12 */
CFG_DISABLED, // DISPLAY_SYNC ->
CFG_DISABLED, // SPI0_SCLK -> SPI0_SCLK/BOARD_ID[0]
CFG_DISABLED, // SPI0_MOSI -> SPI0_MOSI/BOARD_ID[1]
CFG_DISABLED, // SPI0_MISO -> SPI0_MISO/BOARD_ID[2]
CFG_DISABLED, // SPI0_SSIN ->
CFG_DISABLED, // UART0_TXD ->
CFG_DISABLED, // UART0_RXD ->
CFG_DISABLED, // SPI1_SCLK ->
/* Port 13 */
CFG_DISABLED, // SPI1_MOSI ->
CFG_DISABLED, // SPI1_MISO ->
CFG_DISABLED, // SPI1_SSIN ->
CFG_DISABLED, // GPIO20 ->
CFG_DISABLED, // GPIO21 ->
CFG_DISABLED, // GPIO22 ->
CFG_DISABLED, // GPIO23 ->
CFG_DISABLED, // GPIO24 ->
/* Port 14 */
CFG_DISABLED, // GPIO25 ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 15 */
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 16 */
CFG_DISABLED, // ENET_MDC ->
CFG_DISABLED, // ENET_MDIO ->
CFG_DISABLED, // RMII_RXER ->
CFG_DISABLED, // RMII_TXEN ->
CFG_DISABLED, // RMII_CLK ->
CFG_DISABLED, // RMII_TXD[0] ->
CFG_DISABLED, // RMII_TXD[1] ->
CFG_DISABLED, // RMII_RXD[0] ->
/* Port 17 */
CFG_DISABLED, // RMII_RXD[1] ->
CFG_DISABLED, // RMII_RXD[0] ->
CFG_DISABLED, // RMII_CRSDV ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
};
static const uint32_t gpio_1_default_cfg[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // REQUEST_DFU1 ->
CFG_DISABLED, // REQUEST_DFU2 ->
CFG_DISABLED, // DOCK_CONNECT ->
CFG_DISABLED, // CLK32K_IN ->
CFG_DISABLED, // SPU_UART0_TXD ->
CFG_DISABLED, // SPU_UART0_RXD ->
CFG_DISABLED, // SPU_UART0_RTSN ->
CFG_DISABLED, // SPU_UART0_CTSN ->
/* Port 1 */
CFG_DISABLED, // SPU_UART1_TXD ->
CFG_DISABLED, // SPU_UART1_RXD ->
CFG_DISABLED, // SPU_UART1_RTSN ->
CFG_DISABLED, // SPU_UART1_CTSN ->
CFG_DISABLED, // SPU_GPIO[0] ->
CFG_DISABLED, // SPU_GPIO[1] ->
CFG_DISABLED, // SPU_GPIO[2] ->
CFG_DISABLED, // SPU_GPIO[3] ->
/* Port 2 */
CFG_DISABLED, // SPU_GPIO[4] ->
CFG_DISABLED, // SPU_GPIO[5] ->
CFG_DISABLED, // SPU_GPIO[6] ->
CFG_DISABLED, // SPU_GPIO[7] ->
CFG_DISABLED, // SPU_GPIO[8] ->
CFG_DISABLED, // DFU_STATUS ->
CFG_DISABLED, // FORCE_DFU ->
CFG_DISABLED, // POWER_GOOD ->
/* Port 3 */
CFG_DISABLED, // SOC_VDD_HI_LO ->
CFG_DISABLED, // SOC_VDD_ALL_ON ->
CFG_DISABLED, // DOCK_ATTENTION ->
CFG_DISABLED, // PMU_HOST_WAKE ->
CFG_DISABLED, // SPU_SPI_SCLK ->
CFG_DISABLED, // SPU_SPI_MOSI ->
CFG_DISABLED, // SPU_SPI_MISO ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[0] ->
/* Port 4 */
CFG_DISABLED, // SPU_SPI_CS_TRIG[1] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[2] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[3] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[4] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[5] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[6] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[7] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[8] ->
/* Port 5 */
CFG_DISABLED, // SPU_SPI_CS_TRIG[9] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[10] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[11] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[12] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[13] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[14] ->
CFG_DISABLED, // SPU_SPI_CS_TRIG[15] ->
CFG_DISABLED, // SPU_GPIO[9] ->
/* Port 6 */
CFG_DISABLED, // SPU_I2C_SDA ->
CFG_DISABLED, // SPU_I2C_SCL ->
CFG_DISABLED, // WDOG ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 7 */
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 8 */
CFG_DISABLED, // NULL ->
CFG_DISABLED, // RESETN -> RESET_L
CFG_DISABLED, // JTAG_TRSTN ->
CFG_DISABLED, // JTAG_SEL ->
CFG_DISABLED, // JTAG_TCK ->
CFG_DISABLED, // JTAG_TMS ->
CFG_DISABLED, // JTAG_TRTCK ->
CFG_DISABLED, // JTAG_TDO ->
/* Port 9 */
CFG_DISABLED, // JTAG_TDI ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
};
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
{
switch (gpioc) {
case 0:
return gpio_default_cfg;
case 1:
return gpio_1_default_cfg;
default:
panic("unknown GPIO controller");
}
}
target/ipod6/properties.c
+46
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/*
* Copyright (C) 2012 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <debug.h>
#include <target.h>
#include <target/powerconfig.h>
#if WITH_DEVICETREE
bool
target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
{
int length = 0;
bool result = false;
if ((result = target_get_property_base(prop, data, maxdata, retlen)) == false) {
switch(prop) {
case TARGET_PROPERTY_RESTORE_BACKLIGHT_LEVEL:
// fix the restore backlight level at the precharge level,
// to make sure the backlight does not cause the battery to
// drain during restore
if (maxdata >= (ssize_t)sizeof(uint32_t)) {
result = true;
length = sizeof(uint32_t);
*(uint32_t *)data = PRECHARGE_BACKLIGHT_LEVEL;
}
break;
default:
break;
}
}
if (retlen != NULL) *retlen = length;
return result;
}
#endif
target/ipod6/rules.mk
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# Copyright (C) 2013 Apple Inc. All rights reserved.
#
# This document is the property of Apple Inc.
# It is considered confidential and proprietary.
#
# This document may not be reproduced or transmitted in any form,
# in whole or in part, without the express written permission of
# Apple Inc.
#
LOCAL_DIR := $(GET_LOCAL_DIR)
TARGET_DIR := $(LOCAL_DIR)
OPTIONS += \
DIALOG_D2238=1 \
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_MED \
TARGET_BOOT_RAM_VOLTAGE=0 \
TARGET_BOOT_SOC_VOLTAGE=0 \
TARGET_PMU_DEV_ID=0x78 \
AMC_NUM_CHANNELS=1 \
AMC_NUM_RANKS=1 \
TARGET_DSIM_DPHYCTL=0x00003000 \
TARGET_DSIM_CONFIG=0x00400000 \
TARGET_DSIM_UP_CODE=0x1 \
TARGET_DSIM_DOWN_CODE=0x1 \
TARGET_DSIM_SUPPRESS=0x1 \
TARGET_USES_GP_CM=1 \
WITH_TARGET_CHARGETRAP=1 \
WITH_DALI=1 \
WIFI_DTPATH=\"arm-io/sdio\" \
BT_DTPATH=\"arm-io/uart1/bluetooth\" \
MULTITOUCH_DTPATH=\"arm-io/multi-touch\"
ifeq ($(CONFIG_SIM),true)
OPTIONS += \
CONFIG_SIM=1 \
AMP_CALIBRATION_SKIP=1
endif
ifeq ($(CONFIG_FPGA),true)
OPTIONS += \
CONFIG_FPGA=1 \
DISPLAY_FPGA_TUNABLES=1 \
SUPPORT_FPGA=1 \
AMP_CALIBRATION_SKIP=1 \
WITH_TARGET_AMC_PARAMS=1 \
WITH_TARGET_AMP_PARAMS=1
endif
ifeq ($(NO_WFI),true)
OPTIONS += \
NO_ARM_HALT=1
endif
ifeq ($(RECOVERY_MODE_IBSS),true)
OPTIONS += \
WITH_RECOVERY_MODE_IBSS=1
endif
ifeq ($(PRODUCT),LLB)
# iBoot on M7 is in block 0, so LLB needs to expose the "anc_llb" block device.
OPTIONS += \
WITH_LLB_BLKDEV=1
endif
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
ALL_OBJS += $(LOCAL_DIR)/init.o \
$(LOCAL_DIR)/target_prepare_dali.o
ifeq ($(CONFIG_SIM),true)
ALL_OBJS += $(LOCAL_DIR)/init_sim.o \
$(LOCAL_DIR)/pinconfig_sim.o
else
ifeq ($(CONFIG_FPGA),true)
ALL_OBJS += $(LOCAL_DIR)/init_fpga.o \
$(LOCAL_DIR)/pinconfig_fpga.o
else
ALL_OBJS += $(LOCAL_DIR)/init_product.o \
$(LOCAL_DIR)/pinconfig_product.o \
$(LOCAL_DIR)/pinconfig_proto2a.o \
$(LOCAL_DIR)/pinconfig_proto2b.o \
$(LOCAL_DIR)/pinconfig_evt.o
ifneq ($(PRODUCT),LLB)
ALL_OBJS += \
$(LOCAL_DIR)/properties.o
endif
endif
endif
ifeq ($(PRODUCT),iBoot)
# Fast NVRAM driver may be used by iBoot
OPTIONS += \
WITH_LLB_NVRAM=1 \
WITH_LLB_BLKDEV=1
endif
target/ipod6/target_prepare_dali.c
+178
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/*
* Copyright (C) 2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <debug.h>
#include <target.h>
#include <platform/memmap.h>
#include <platform/gpiodef.h>
#include <target/gpiodef.h>
#include <drivers/power.h>
#include <stdlib.h>
#include <lib/env.h>
#include <lib/syscfg.h>
#include <platform/dmin.h>
enum {
kRTKitArgBlockVersion1 = 'RTK1',
kDaliFWArgVersion1 = 'DAL1',
kDaliFWArgVersion2 = 'DAL2',
kDaliFWArgVersion3 = 'DAL3',
kDaliFWArgVersion4 = 'DAL4'
};
enum
{
kMode24hEnabledOffset = 0,
kRotateScreenOffset = 1,
kDaliDarkWakeOffset = 2, /* 0 = normal wake, 1 = scheduled thermal wake, don't paint screen */
kPmuDebugOffset = 3,
kIsChargerConnectedOffset = 4,
kPrechargeNeededOffset = 5
};
#define kUTCOffsetUnsetValue 0x7fffffffffffffffLL /* INT64_MAX. There's only 86400 seconds in a day */
typedef struct dali_payload_t {
uint32_t magic; /* = kDaliFWArgVersion3 */
uint32_t reserved;
uint8_t charFlags[8];
int64_t utcOffset; /* Set to either a valid offset, or kUTCOffsetUnsetValue if unset */
DMin_t dmin;
} dali_payload_t;
typedef struct dali_args_t {
uint32_t magic; /* = kRTKitArgBlockVersion1 */
uint32_t size; /* size of pending payload */
dali_payload_t payload;
} dali_args_t;
#define kDMinNVRAMKey "device-material"
static void save_dmin_to_nvram(const DMin_t* dmin)
{
#if WITH_LLB_NVRAM
if (target_needs_chargetrap())
panic("LLB NVRAM is read-only, it's a logic error to cache NVRAM here");
#endif
char dmin_ascii[2*sizeof(DMin_t) + 1];
const char* dmin_buffer = (const char*)(dmin);
for(unsigned long i = 0; i < sizeof(DMin_t); i++)
{
snprintf(dmin_ascii + 2*i, sizeof(dmin_ascii) - 2*i, "%02X", dmin_buffer[i]);
}
dmin_ascii[2*sizeof(DMin_t)] = '\0';
env_set(kDMinNVRAMKey, dmin_ascii, ENV_PERSISTENT);
// dprintf(DEBUG_INFO, "save_dmin_to_nvram: Set kDMinNVRAMKey = %s\n", dmin_ascii);
}
static int get_dmin_from_nvram(DMin_t* dest_dmin)
{
char* dest_buf = (char*)(dest_dmin);
const char* dmin_val = env_get(kDMinNVRAMKey);
if (dmin_val == NULL) {
// dprintf(DEBUG_INFO, "No DMin cached in NVRAM yet\n");
return -1;
}
unsigned int dmin_len = (unsigned int)strlen(dmin_val);
if (dmin_len > 2*sizeof(DMin_t) || (dmin_len & 0x1)) {
dprintf(DEBUG_CRITICAL, "Unexpected DMin key length %u, expected even and <= %zu\n", dmin_len, 2*sizeof(DMin_t));
return -2;
}
unsigned long i = 0;
unsigned long p = 0;
while ( i < dmin_len ) {
unsigned char byte = 0;
for (int j = 0; j < 2; j++) {
int shift_factor = 4*(1-j);
switch(dmin_val[i]) {
case '0' ... '9':
byte += (dmin_val[i] - '0') << shift_factor;
break;
case 'A' ... 'F':
byte += ((dmin_val[i] - 'A') + 10) << shift_factor;
break;
default:
dprintf(DEBUG_CRITICAL, "Non-hex digit in DMin NVRAM key: 0x%x\n", dmin_val[i]);
return -3;
}
i++;
}
dest_buf[p++] = byte;
}
return 0;
}
void
target_init_fast_dali()
{
DMin_t dmin;
bzero(&dmin, sizeof(DMin_t));
syscfgCopyDataForTag('DMin', (uint8_t*)&(dmin), sizeof(DMin_t));
save_dmin_to_nvram(&dmin);
}
static bool is_dark_wake()
{
bool powersupply_change_event, button_event, other_wake_event;
pmu_check_events(&powersupply_change_event, &button_event, &other_wake_event);
dprintf(DEBUG_INFO, "is_dark_wake: ps_changed = %d, button = %d, other = %d\n", powersupply_change_event, button_event, other_wake_event);
return !powersupply_change_event && !button_event;
}
void*
target_prepare_dali(void)
{
#if defined(PMU_LDO_OPAL) && WITH_HW_POWER
// <rdar://problem/17768885> Interim Solution: Turn off LDO8 in Dali mode/iBoot
// Opal uses a lot of power when held in reset. For sure we don't need it in Dali.
power_enable_ldo(PMU_LDO_OPAL, false);
#endif
#ifdef GPIO_SPU_TO_OPAL_CS_L
gpio_configure(GPIO_SPU_TO_OPAL_CS_L, GPIO_CFG_IN);
#endif
dali_args_t* args = (dali_args_t *)PANIC_BASE;
bzero(args, sizeof(dali_args_t));
args->magic = kRTKitArgBlockVersion1;
args->size = sizeof(dali_payload_t);
args->payload.magic = kDaliFWArgVersion3;
args->payload.charFlags[kMode24hEnabledOffset] = (env_get_uint("dali-24h-mode", 0) == 1);
args->payload.charFlags[kRotateScreenOffset] = (env_get_uint("display-rotation", 0) == 1);
args->payload.charFlags[kPmuDebugOffset] = (env_get_uint("dali-pmu-debug", 0) == 1);
#if WITH_HW_POWER
args->payload.charFlags[kDaliDarkWakeOffset] = (is_dark_wake());
args->payload.charFlags[kIsChargerConnectedOffset] = (power_has_usb());
args->payload.charFlags[kPrechargeNeededOffset] = (power_needs_precharge());
dprintf(DEBUG_INFO, "Charger Connected: %d, Precharge needed: %d\n", (int)args->payload.charFlags[kIsChargerConnectedOffset], (int)args->payload.charFlags[kPrechargeNeededOffset]);
#endif
if (get_dmin_from_nvram(&(args->payload.dmin)) < 0) {
dprintf(DEBUG_CRITICAL, "Unable to find DMin in NVRAM; booting into Dali mode with potentially incorrect DMin information!\n");
}
args->payload.utcOffset = kUTCOffsetUnsetValue;
const char* utcOffsetStr = env_get("utc-offset");
if (utcOffsetStr) {
args->payload.utcOffset = atoi(utcOffsetStr);
}
return args;
}