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/*
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* Copyright (C) 2011-2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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||||
* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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/*
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* The amc_param struct is defined in drivers/apple/amc/amc.h, and this
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* file should only by included from amc.c.
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*
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*/
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static const struct amc_param amc_params = {
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.flags = FLAG_AMC_PARAM_SLOW_BOOT | FLAG_AMC_PARAM_RECONFIG | FLAG_AMC_PARAM_ENABLE_AIU,
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.freqsel = 0,
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.tREFi = 0x5d,
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.longsrcnt = 0x0802,
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.srextrarefcnt = 0x00010000,
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.tREFi_1Gb = 0xbb,
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.longsrcnt_1Gb = 0x0401,
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.rdlat = 6,
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.wrlat = 3,
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.phyrdlat = 6, // rdlat
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.phywrlat = 3,
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.pdn = 0x33000303,
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.read = 0x00000102,
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.bustat = 0x00020002,
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.derate = 0x18620c46,
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.mcphyupdate = 0x00000009, // <rdar://problem/8199905> <rdar://problem/8256572>
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.pwrmngtparam_small = 0x00013000,
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.pwrmngtparam_guided = 0x00fa3000,
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.bootclkdivsr = 8,
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.aref_freq0 = 0x00100000,
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.aref_freq1 = 0x00000000,
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.chnldec = 0x00000F00,
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.arefparam = 0x06000000,
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.readleveling = 0x02000301,
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.freq = {
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{ // 256MHz
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.cas = 0x00000205,
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.pch = 0x0002040b,
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.act = 0x0d030605,
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.autoref = 0x1022a000,
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.selfref = 0x00024040,
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.modereg = 0x00180502,
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.mifcassch = 0x001f0101,
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.mifqmaxctrl = 0x00000000,
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},
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{ // 128.5MHz
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.cas = 0x00000003,
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.pch = 0x00000006,
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.act = 0x08020303,
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.autoref = 0x08110000,
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.selfref = 0x00012000,
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.modereg = 0x000c0000,
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.mifcassch = 0x00000000,
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.mifqmaxctrl = 0x00000000,
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},
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{ // 64.13MHz
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.cas = 0x00000003,
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.pch = 0x00000003,
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.act = 0x08020303,
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.autoref = 0x04090000,
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.selfref = 0x00009000,
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.modereg = 0x00060000,
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.mifcassch = 0x00000010,
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.mifqmaxctrl = 0x00000001,
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},
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{ // 50 & 24MHz
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.cas = 0x00000003,
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.pch = 0x00000003,
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.act = 0x08020303,
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.autoref = 0x03070000,
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.selfref = 0x00007000,
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.modereg = 0x00060000,
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.mifcassch = 0x00000010,
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.mifqmaxctrl = 0x00000001,
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}
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}
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};
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static const struct amc_tunable amc_tunables[] = {
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// These settings are common across all H4x and H5P. Channel decode and hashing
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// is done in mainline init code. Any tunables that match hardware defaults are
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// omitted here.
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{ &rAMC_AIUPRT_CFG, 0x00070000 }, // address error enable
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{ &rAMC_AIUPRT_RD_GEN, 0x00000018 }, // fence read detect on GFX
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{ &rAMC_AIUPRT_WR, 0x00000001 }, // out-of-order write, ignore B-bit
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{ &rAMC_AIU_RDBRSTLEN, 0x01010101 }, // burst len is 64B
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{ &rAMC_AIU_RDMINCRD, 0x7B7B7C7B }, // RT:NRT:CPU:GFX = 40:40:5:10
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{ &rAMC_AIU_WRBRSTLEN, 0x01010101 }, // burst len is 64B
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{ &rAMC_AIU_WRMINCRD, 0x7B7B7C7B }, // RT:NRT:CPU:GFX = 40:40:5:10
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{ &rAMC_AIU_CPUSPCREQ, 0x00000019 }, // CPU ageout timer
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{ &rAMC_AIU_GFXSPCREQ, 0x00000032 }, // GFX ageout timer
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{ &rAMC_AIU_NRTSPCREQ, 0x00000032 }, // Hperf-NRT ageout timer
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{ &rAMC_AIU_RTSPCREQ, 0x00000019 }, // Hperf-RT ageout timer
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{ &rAMC_AIU_WPQSCH, 0x10001000 }, // only supported for Hperf-RT
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{ &rAMC_AIU_THOTLCPUPARAM, 0x0A4640C4 },
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{ &rAMC_AIU_THOTLRTPARAM, 0x0A4640C4 },
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{ &rAMC_AIU_THOTLNRTPARAM, 0x00000000 },
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{ &rAMC_AIU_THOTLGFXPARAM, 0x00000000 },
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{ &rAMC_AIU_PUSHEN, 0x00001100 }, // only supported for Hperf-RT
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{ &rAMC_OPIDLETMR, 0x00200000 },
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{ &rAMC_OPTMRADJEN, 0x00000001 },
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{ &rAMC_OPTMRADJPARAM, 0x20400064 },
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{ &rAMC_MIFACTSCH, 0x00000001 },
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{ &rAMC_PSQRQTIMER0, 0x00000040 }, // RTG bypass up to 64 transactions
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{ &rAMC_PSQRQTIMER1, 0x00000018 }, // RTY bypass up to 24 transactions
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{ &rAMC_PSQRQTIMER2, 0x00000020 }, // RTG bypass up to 32 transactions
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{ &rAMC_PSQRQBRST, 0x040c040c }, // RTR transactions don't affect read burst size
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{ &rAMC_PSQRQSCHCRD, 0x002028f5 }, // read credits = 2 * write credits
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{ &rAMC_PSQWQBRST, 0x0208040c }, // RTR reads cause reduced write burst size
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{ &rAMC_PSQWQSCHCRD, 0x001014f5 }, // write credits = 1/2 * read credits
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{ &rAMC_MCUQOS, 0x00010f04 }, // RTG=4, RTY=15, enable pick-oldest-RTY
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// Platform specific
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{ &rAMC_AIU_RDMAXCRD, 0x2828050a }, // RT:NRT:CPU:GFX = 40:40:5:10
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{ &rAMC_AIU_RDREFL, 0x21210408 }, // 5/6 of AIURDMAXCRD fields
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{ &rAMC_AIU_WRMAXCRD, 0x2828050a }, // RT:NRT:CPU:GFX = 40:40:5:10
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{ &rAMC_AIU_WRREFL, 0x21210408 }, // 5/6 of AIUWRMAXCRD fields
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{ &rAMC_AIU_THOTLEN, 0x00001111 }, // enable throttling
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{ &rAMC_PSQWQCTL1, 0x000000C0 }, // ages write out faster than default (1/2 SelfRef)
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{ &rAMC_MCUQOSLLT, 0x00010104 },
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// There is a bug around write merge, which we believe is avoided
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// in current drivers: <rdar://problem/9076703>
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// Power and performance measurements of disabling write merging were
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// done: <rdar://problem/9092558> <rdar://problem/9087726>
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{ &rAMC_PSQWQCTL0, 0x00010100 }, // Write merge enable
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{ &rAMC_AIUPRT_ROTT_D1, 0x000C0000 },
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{ &rAMC_AIUPRT_ROTT_D2, 0x00000C0C },
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{ &rAMC_AIU_CHNLTM, 0x000000E1 },
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{ &rAMC_PSQWQTHR, 0x00171710 },
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{ &rAMC_PSQWQBRST, 0x01050105 },
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};
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@@ -0,0 +1,24 @@
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/*
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* Copyright (C) 2011 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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||||
* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
|
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* Apple Inc.
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*/
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/*
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* The amg_param struct is defined in drivers/apple/amg/amg.h, and this
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* file should only by included from amg.c.
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*/
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static const struct amg_params amc_phy_params = {
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.flags = 0,
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.core_config = 0x00001053,
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.read_latency = 0x0000669b,
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.gate_offset = 0x08080808,
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.freq_scale = 0x00e40488,
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.bit_time_ps = 3900,
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};
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@@ -0,0 +1,25 @@
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/*
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* Copyright (C) 2011 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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||||
* It is considered confidential and proprietary.
|
||||
*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* J33 specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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#define GPIO_BOARD_REV0 GPIO(4, 5)
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#define GPIO_BOARD_REV1 GPIO(4, 6)
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#define GPIO_BOARD_REV2 GPIO(4, 7)
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#define GPIO_BOARD_REV3 GPIO(7, 5)
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,92 @@
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// Copyright (C) 2008-2010 Apple, Inc. All rights reserved.
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//
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// This document is the property of Apple, Inc.
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// It is considered confidential and proprietary.
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//
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// This document may not be reproduced or transmitted in any form,
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// in whole or in part, without the express written permission of
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// Apple, Inc.
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//
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// NOTE: This is a generated file and should not be hand-edited!
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//
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// =============================================================================
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// Nand Geometry Table
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static NandGeometry _nandGeometryTable[] =
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{
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};
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// =============================================================================
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// Nand Timing Table
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static NandTiming _nandTimingTable[] =
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{
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};
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#if (defined (AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
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// =============================================================================
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// NandChipId Description
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const NandChipIdDescription _nandChipIdDescriptionTable[] =
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{
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};
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// =============================================================================
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// Nand Description Table
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static const NandDescription _nandDescriptionTable[] =
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{
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};
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const UInt32 _nandDescriptionTableSize = sizeof(_nandDescriptionTable) / sizeof(NandDescription);
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#endif // (defined(AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
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// =============================================================================
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// Nand Board Support Table
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static NandBoardSupport _nandBoardSupportTable[] =
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{
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};
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// =============================================================================
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// Nand Board Timing Table
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static NandBoardInfo _nandBoardInfo =
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{
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/* controlDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* dataDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* chipEnableDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* socToNandRiseNanosecs */ 3,
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/* socToNandFallNanosecs */ 3,
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/* nandToSocRiseNanosecs */ 3,
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/* nandToSocFallNanosecs */ 4,
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/* landing map */
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{
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0x00003333
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},
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/* useToggleMode */ FALSE32,
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/* useDiffDQSMode */ FALSE32,
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/* useDiffREMode */ FALSE32,
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/* useVref */ FALSE32,
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/* useSingleHostChannel */ FALSE32,
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/* allowSingleChipEnable */ FALSE32
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};
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static NandFormat _nandFormatPpn =
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{
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/* metaPerLogicalPage */ 16,
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/* validMetaPerLogicalPage */ 16,
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/* logicalPageSize */ 4096
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};
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static NandFormat _nandFormatRaw =
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{
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/* metaPerLogicalPage */ 12,
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/* validMetaPerLogicalPage */ 10,
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/* logicalPageSize */ 0
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};
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@@ -0,0 +1,97 @@
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/*
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* Copyright (C) 2009-2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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||||
*/
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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// XXX derived from values read from regs on K66 Dev 0 board; need to
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// reconcile these with OTP doc (which appears to differ) and intended
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// settings
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// XXX also, need to reconcile OTP settings between K66 Dev 0 and K66 Proto 0
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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{ PMU_IIC_BUS, kD1815_LDO1, 0x00 }, // PP2V5_BS 2.50V
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{ PMU_IIC_BUS, kD1815_LDO2, 0x1E }, // PP1V8_AP_PVDDP 1.80V
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{ PMU_IIC_BUS, kD1815_LDO3, 0x0A }, // PP3V0_USBMUX 3.00V
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{ PMU_IIC_BUS, kD1815_LDO4, 0x00 }, // PP1V8_AP_DAC 3.00V
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{ PMU_IIC_BUS, kD1815_LDO5, 0x0A }, // PPNNAD 3.00V
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{ PMU_IIC_BUS, kD1815_LDO6, 0x0A }, // PP3V0_MCU 3.00V
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{ PMU_IIC_BUS, kD1815_LDO7, 0x03 }, // PP1V8_AP_VDD 1.80V
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{ PMU_IIC_BUS, kD1815_LDO8, 0x00 }, // PP3V0_CPU 2.00V
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{ PMU_IIC_BUS, kD1815_LDO9, 0x00 }, // PP1V2_HSIC 1.20V
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{ PMU_IIC_BUS, kD1815_LDO10, 0x0A }, // PP3V0_IO 3.00V
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{ PMU_IIC_BUS, kD1815_LDO11, 0x02 }, // PP1V8_AP_VIDEO 1.80V
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{ PMU_IIC_BUS, kD1815_LDO12, 0x10 }, // PP1V0_AP 1.00V
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{ PMU_IIC_BUS, kD1815_LCM_CONTROL1, 0x05 }, // unused
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{ PMU_IIC_BUS, kD1815_LCM_CONTROL2, 0x0E }, // unused
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{ PMU_IIC_BUS, kD1815_LCM_CONTROL3, 0x00 }, // VBOOST_LCM 5.10V
|
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{ PMU_IIC_BUS, kDIALOG_LDO_CONTROL, 0x00 }, // Leave bypass off
|
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD1815_ACTIVE1, 0xFF }, //
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{ PMU_IIC_BUS, kD1815_ACTIVE2, 0x3F }, //
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{ PMU_IIC_BUS, kD1815_ACTIVE3, 0x0C }, // VBOOST_LCM, CPU_SW, WDig
|
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL, 0 }, // Disable SWI by default
|
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{ PMU_IIC_BUS, kDIALOG_ADC_CONTROL, kDIALOG_ADC_CONTROL_DEFAULTS },
|
||||
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||||
{ PMU_IIC_BUS, kDIALOG_BUCK_CONTROL2, 0xAA },
|
||||
|
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{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_A, 0xC0 },
|
||||
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_B, 0xFF },
|
||||
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_C, 0xBF },
|
||||
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_D, 0xFF },
|
||||
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_E, 0xAE },
|
||||
{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_F, 0xFF },
|
||||
};
|
||||
|
||||
// XXX: review setup for each GPIO and add back decoded description of each config
|
||||
static const struct pmu_setup_struct pmu_cold_init[] =
|
||||
{
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||||
{ PMU_IIC_BUS, kD1815_SYS_GPIO_1, 0xB9 }, // ENBL_USB_BUFF_L
|
||||
{ PMU_IIC_BUS, kD1815_SYS_GPIO_2, 0xBA }, // LAN_PME_PMU
|
||||
{ PMU_IIC_BUS, kD1815_SYS_GPIO_3, 0xBA }, // WLAN_WAKE_HOST
|
||||
{ PMU_IIC_BUS, kD1815_SYS_GPIO_4, 0x03 }, // ENET_PWR_EN_L
|
||||
{ PMU_IIC_BUS, kD1815_SYS_GPIO_5, 0x01 }, // WLAN_PWR_EN_L
|
||||
{ PMU_IIC_BUS, kD1815_SYS_GPIO_6, 0xFA }, // VBAT_DETECT
|
||||
{ PMU_IIC_BUS, kD1815_SYS_GPIO_7, 0xBA }, // BT_HOST_WAKE
|
||||
{ PMU_IIC_BUS, kD1815_SYS_GPIO_8, 0x18 }, // WLAN_RESET_L
|
||||
{ PMU_IIC_BUS, kD1815_SYS_GPIO_TEMP, 0x18 }, // LAN_RESET_L
|
||||
{ PMU_IIC_BUS, kD1815_SYS_GPIO_SPARE, 0x4B }, // WLAN_CLK32K_R
|
||||
{ PMU_IIC_BUS, kD1815_SYS_GPIO_DEB6, 0x80 }, // enable 32kHz clocks in hibernate
|
||||
};
|
||||
|
||||
static const struct core_rails_struct soc_rails[] =
|
||||
{
|
||||
};
|
||||
|
||||
#endif /* POWERCONFIG_PMU_SETUP */
|
||||
|
||||
#define TARGET_POWER_NO_BATTERY 1
|
||||
#define TARGET_POWER_USB_MASK STATUS_FLAG_MAKE(0, kD1815_STATUS_A_VBUS_EXT)
|
||||
#define ALWAYS_BOOT_BATTERY_VOLTAGE (3000)
|
||||
#define PRECHARGE_BACKLIGHT_LEVEL 103
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (C) 2009 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define two debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (2)
|
||||
|
||||
#define MCU_SERIAL_PORT (4)
|
||||
|
||||
#define UART_FLOWCONTROL_MASK (0x08)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,240 @@
|
||||
/*
|
||||
* Copyright (C) 2009-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#if (APPLICATION_IBOOT && PRODUCT_IBOOT)
|
||||
#include <drivers/displayport/displayport.h>
|
||||
#include <drivers/displayport.h>
|
||||
#endif
|
||||
#include <drivers/flash_nor.h>
|
||||
#include <drivers/iic.h>
|
||||
#include <drivers/power.h>
|
||||
#include <drivers/mcu.h>
|
||||
#include <lib/devicetree.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <lib/syscfg.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <sys.h>
|
||||
#include <sys/boot.h>
|
||||
#include <sys/menu.h>
|
||||
#include <sys/task.h>
|
||||
#include <target.h>
|
||||
#include <target/powerconfig.h>
|
||||
|
||||
// Do not delay iBoot by more than this amount from power on (microseconds).
|
||||
// Give up waiting for a boot logo and carry on at this point.
|
||||
#define kDPDeviceStartTimeout (8 * 1000 * 1000)
|
||||
|
||||
static u_int32_t j33_get_board_rev(void);
|
||||
extern utime_t gPowerOnTime;
|
||||
#if (APPLICATION_IBOOT && PRODUCT_IBOOT )
|
||||
#if WITH_HW_DISPLAY_DISPLAYPORT
|
||||
static dp_t dp_link_config = {
|
||||
.mode = 0,
|
||||
.type = 0,
|
||||
.min_link_rate = 0x6,
|
||||
.max_link_rate = 0x6,
|
||||
.lanes = 2,
|
||||
.ssc = 0,
|
||||
.alpm = 0,
|
||||
.vrr_enable = 0,
|
||||
.vrr_on = 0,
|
||||
};
|
||||
#endif
|
||||
#endif //(APPLICATION_IBOOT && PRODUCT_IBOOT)
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 1);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
|
||||
#if WITH_HW_MCU
|
||||
// Late display initialization. Needed to wait for MCU.
|
||||
mcu_init();
|
||||
#if WITH_HW_DISPLAY_DISPLAYPORT
|
||||
// Backgrounded. See dp_device_wait_started() call below.
|
||||
displayport_init(&dp_link_config);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
|
||||
#if WITH_HW_MCU
|
||||
// radar 9746416 -- UART4 left in interrupt mode will cause kernel panic
|
||||
mcu_quiesce_uart();
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
int target_debug_init(void)
|
||||
{
|
||||
#if WITH_HW_MCU
|
||||
mcu_start_recover();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
switch (target) {
|
||||
case BOOT_DARWIN:
|
||||
case BOOT_DIAGS:
|
||||
#if WITH_HW_MCU
|
||||
#if WITH_HW_DISPLAY_DISPLAYPORT && PRODUCT_IBOOT
|
||||
/* Potentially delay boot so we have a
|
||||
* logo. We might have to do this if a
|
||||
* connected TV is particularly slow at
|
||||
* responding to EDID. Sorry. */
|
||||
dp_device_wait_started(gPowerOnTime + kDPDeviceStartTimeout);
|
||||
#endif
|
||||
mcu_start_boot();
|
||||
#endif
|
||||
break;
|
||||
case BOOT_DARWIN_RESTORE:
|
||||
break;
|
||||
default:
|
||||
// do nothing
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
// trigger recovery mode whenever USB is attached, unless
|
||||
// environment variable says otherwise.
|
||||
|
||||
return power_has_usb() && !env_get_bool("auto-boot-usb", true);
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
// always powers on
|
||||
return true;
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
// never power off
|
||||
return false;
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
// u_int32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
// gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
|
||||
void * target_get_display_configuration(void)
|
||||
{
|
||||
#if (APPLICATION_IBOOT && PRODUCT_IBOOT)
|
||||
#if WITH_HW_DISPLAY_DISPLAYPORT
|
||||
return ((void *)(&dp_link_config));
|
||||
#endif
|
||||
#else
|
||||
return NULL;
|
||||
#endif //(APPLICATION_IBOOT && PRODUCT_IBOOT)
|
||||
}
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
env_set("boot-device", "nand0", 0);
|
||||
env_set("display-color-space","RGB888", 0);
|
||||
env_set("display-timing", "720p", 0);
|
||||
env_set("idle-off", "false", 0); // do not idle off; there is no battery and this will just reboot (8035422)
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
DTNode *node;
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
// Update the pmu node with the actual vcore values
|
||||
if (FindNode(0, "arm-io/i2c0/pmu", &node)) {
|
||||
propName = "swi-vcores";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
platform_get_soc_voltages(propSize / sizeof(u_int32_t), propData);
|
||||
}
|
||||
}
|
||||
|
||||
if (FindNode(0, "arm-io/mcu0", &node)) {
|
||||
propName = "board-rev";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
((u_int32_t *)propData)[0] = j33_get_board_rev();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
static u_int32_t j33_get_board_rev(void)
|
||||
{
|
||||
u_int32_t gpio_board_rev;
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV3, GPIO_PDN);
|
||||
|
||||
spin(100); // Wait 100us
|
||||
|
||||
gpio_board_rev =
|
||||
(gpio_read(GPIO_BOARD_REV3) << 3) |
|
||||
(gpio_read(GPIO_BOARD_REV2) << 2) |
|
||||
(gpio_read(GPIO_BOARD_REV1) << 1) |
|
||||
(gpio_read(GPIO_BOARD_REV0) << 0);
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_DFLT);
|
||||
|
||||
return (gpio_board_rev &0xF);
|
||||
}
|
||||
@@ -0,0 +1,284 @@
|
||||
/*
|
||||
* Copyright (C) 2009-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <target.h>
|
||||
|
||||
/* S5L8942X FPGA Pin Configuration */
|
||||
#define DFU_STATUS_DRIVE_STR DRIVE_X1
|
||||
#define FMI_DRIVE_STR DRIVE_X2
|
||||
|
||||
static const u_int32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
/* Port 0 */
|
||||
CFG_IN, // GPIO0 -> MENU_KEY (REQUEST_DFU2)
|
||||
CFG_IN, // GPIO1 -> HOLD_KEY (REQUEST_DFU1)
|
||||
CFG_DISABLED, // GPIO2 ->
|
||||
CFG_DISABLED, // GPIO3 ->
|
||||
CFG_DISABLED, // GPIO4 ->
|
||||
CFG_DISABLED, // GPIO5 ->
|
||||
CFG_DISABLED, // GPIO6 ->
|
||||
CFG_DISABLED, // GPIO7 ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_OUT_1, // GPIO8 -> BT_EN
|
||||
CFG_IN, // GPIO9 -> BT_WAKE
|
||||
CFG_DISABLED, // GPIO10 ->
|
||||
CFG_IN, // GPIO11 -> LAN_HSIC_DEVICE_RDY
|
||||
CFG_DISABLED, // GPIO12 ->
|
||||
CFG_IN | PULL_UP, // GPIO13 -> PMU_IRQ_L
|
||||
CFG_DISABLED, // GPIO14 ->
|
||||
CFG_DISABLED, // GPIO15 ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_IN | PULL_DOWN, // GPIO16 -> BOARD_ID[3]
|
||||
CFG_DISABLED, // GPIO17 ->
|
||||
CFG_IN | PULL_DOWN, // GPIO18 -> BOOT_CONFIG[0]
|
||||
CFG_OUT_0, // GPIO19 -> KEEPACT
|
||||
CFG_IN, // GPIO20 -> WLAN0_HSIC_DEVICE_READY
|
||||
CFG_IN, // GPIO21 -> USB_DEVMUX_SEL_C0
|
||||
CFG_IN, // GPIO22 -> USB_DEVMUX_SEL_C0
|
||||
CFG_DISABLED, // GPIO23 ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // GPIO24 ->
|
||||
CFG_IN | PULL_DOWN, // GPIO25 -> BOOT_CONFIG[1]
|
||||
CFG_IN | PULL_DOWN, // GPIO26 -> FORCE_DFU
|
||||
CFG_OUT_0 | DFU_STATUS_DRIVE_STR | PULL_DOWN, // GPIO27 -> DFU_STATUS
|
||||
CFG_IN | PULL_DOWN, // GPIO28 -> BOOT_CONFIG[2]
|
||||
CFG_IN | PULL_DOWN, // GPIO29 -> BOOT_CONFIG[3]
|
||||
CFG_DISABLED, // GPIO30 ->
|
||||
CFG_OUT, // GPIO31 -> WLAN0_HSIC_HOST_READY
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED, // GPIO32 ->
|
||||
CFG_DISABLED, // GPIO33 ->
|
||||
CFG_DISABLED, // GPIO34 ->
|
||||
CFG_IN, // GPIO35 -> LAN_PHY_INT
|
||||
CFG_DISABLED, // GPIO36 ->
|
||||
CFG_IN | PULL_DOWN, // EHCI_PORT_PWR[0] -> BOARD_REV[0]
|
||||
CFG_IN | PULL_DOWN, // EHCI_PORT_PWR[1] -> BOARD_REV[1]
|
||||
CFG_IN | PULL_DOWN, // EHCI_PORT_PWR[2] -> BOARD_REV[2]
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0, // UART1_TXD -> BT_UART_TXD
|
||||
CFG_FUNC0, // UART1_RXD -> BT_UART_RXD
|
||||
CFG_OUT_1, // UART1_RTSN -> BT_UART_RTSN
|
||||
CFG_FUNC0, // UART1_CTSN -> BT_UART_CTSN
|
||||
CFG_FUNC0, // UART2_TXD -> AP_UART2_TXD
|
||||
CFG_FUNC0, // UART2_RXD -> AP_UART2_RXD
|
||||
CFG_DISABLED, // UART2_RTSN ->
|
||||
CFG_DISABLED, // UART2_CTSN ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_FUNC1, // UART3_TXD -> AP_SPDIF_OUT_1V8
|
||||
CFG_DISABLED, // UART3_RXD ->
|
||||
CFG_DISABLED, // UART3_RTSN ->
|
||||
CFG_DISABLED, // UART3_CTSN ->
|
||||
CFG_FUNC0, // I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0, // I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_DISABLED, // I2C1_SDA ->
|
||||
CFG_DISABLED, // I2C1_SCL ->
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED, // ISP0_SDA ->
|
||||
CFG_DISABLED, // ISP0_SCL ->
|
||||
CFG_DISABLED, // ISP1_SDA ->
|
||||
CFG_DISABLED, // ISP1_SCL ->
|
||||
CFG_DISABLED, // UART5_TXD/MIPI_VSYNC ->
|
||||
CFG_IN | PULL_DOWN, // TMR32_PWM0 -> BOARD_REV[3]
|
||||
CFG_DISABLED, // TMR32_PWM1 -> IRRCVR_OUT_TO_AP_AMR_R
|
||||
CFG_DISABLED, // TMR32_PWM2
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0, // SWI_DATA -> SWI_AP
|
||||
CFG_DISABLED, // DWI_DI ->
|
||||
CFG_DISABLED, // DWI_DO ->
|
||||
CFG_DISABLED, // DWI_CLK ->
|
||||
CFG_DISABLED, // SENSOR0_RST ->
|
||||
CFG_DISABLED, // SENSOR0_CLK ->
|
||||
CFG_DISABLED, // SENSOR1_RST ->
|
||||
CFG_DISABLED, // SENSOR1_CLK ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // ISP0_PRE_FLASH ->
|
||||
CFG_DISABLED, // ISP0_FLASH ->
|
||||
CFG_DISABLED, // ISP1_PRE_FLASH ->
|
||||
CFG_DISABLED, // ISP1_FLASH ->
|
||||
CFG_DISABLED, // I2S0_MCK ->
|
||||
CFG_FUNC0, // I2S0_LRCK -> AP_I2S0_LRCK
|
||||
CFG_FUNC0, // I2S0_SCLK -> AP_I2S0_SCLK
|
||||
CFG_FUNC0, // I2S0_DOUT -> AP_I2S0_DOUT
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // I2S0_DIN ->
|
||||
CFG_DISABLED, // I2S1_MCK ->
|
||||
CFG_DISABLED, // I2S1_LRCK ->
|
||||
CFG_DISABLED, // I2S1_SCLK ->
|
||||
CFG_DISABLED, // I2S1_DOUT ->
|
||||
CFG_DISABLED, // I2S1_DIN ->
|
||||
CFG_DISABLED, // I2S2_MCK ->
|
||||
CFG_DISABLED, // I2S2_LRCK ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // I2S2_BCLK ->
|
||||
CFG_DISABLED, // I2S2_DOUT ->
|
||||
CFG_DISABLED, // I2S2_DIN ->
|
||||
CFG_DISABLED, // I2S2_MCK ->
|
||||
CFG_DISABLED, // I2S3_LRCK ->
|
||||
CFG_DISABLED, // I2S3_BCLK ->
|
||||
CFG_DISABLED, // I2S3_DOUT ->
|
||||
CFG_DISABLED, // I2S3_DIN ->
|
||||
|
||||
/* Port 12 */
|
||||
CFG_IN | PULL_DOWN, // SPI0_SCLK -> BOARD_ID[0]
|
||||
CFG_IN | PULL_DOWN, // SPI0_MOSI -> BOARD_ID[1]
|
||||
CFG_IN | PULL_DOWN, // SPI0_MISO -> BOARD_ID[2]
|
||||
CFG_DISABLED | PULL_UP, // SPI0_SSIN ->
|
||||
CFG_DISABLED, // SPI1_SCLK ->
|
||||
CFG_DISABLED, // SPI1_MOSI ->
|
||||
CFG_DISABLED, // SPI1_MISO ->
|
||||
CFG_DISABLED, // SPI1_SSIN ->
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // SPI2_SCLK ->
|
||||
CFG_DISABLED, // SPI2_MOSI ->
|
||||
CFG_DISABLED, // SPI2_MISO ->
|
||||
CFG_DISABLED, // SPI2_SSIN ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0, // UART4_TXD -> UART4_TXD
|
||||
CFG_FUNC0, // UART4_RXD -> UART4_RXD
|
||||
CFG_DISABLED, // UART4_RTSN ->
|
||||
CFG_DISABLED, // UART4_CTSN ->
|
||||
CFG_IN, // SDIO0_DATA3 -> AP_MCU_RESET
|
||||
CFG_IN, // SDIO0_DATA2 -> AP_MCU_INT
|
||||
CFG_OUT, // SDIO0_DATA1 -> PME_MODE_SEL
|
||||
CFG_IN, // SDIO0_DATA0 -> AP_MCU_TCK_3V0
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // SDIO0_CMD ->
|
||||
CFG_DISABLED, // SDIO0_CLK ->
|
||||
CFG_DISABLED, // FMI0_CEN3 ->
|
||||
CFG_DISABLED, // FMI0_CEN2 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN1 -> FMI0_CEN1
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN0 -> FMI0_CEN0
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CLE -> FMI0_CLE
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_ALE -> FMI0_ALE
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_REN -> FMI0_REN
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_WEN -> FMI0_WEN
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO7 -> FMI0_IO7
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO6 -> FMI0_IO6
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO5 -> FMI0_IO5
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO4 -> FMI0_IO4
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED | PULL_DOWN, // FMI0_DQS -> FMI0_DQS
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO3 -> FMI0_IO3
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO2 -> FMI0_IO2
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO1 -> FMI0_IO1
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO0 -> FMI0_IO0
|
||||
CFG_DISABLED, // FMI1_CEN3 ->
|
||||
CFG_DISABLED, // FMI1_CEN2 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN1 -> FMI1_CEN1
|
||||
|
||||
/* Port 21 */
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN0 -> FMI1_CEN0
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CLE -> FMI1_CLE
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_ALE -> FMI1_ALE
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_REN -> FMI1_REN
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_WEN -> FMI1_WEN
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO7 -> FMI1_IO7
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO6 -> FMI1_IO6
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO5 -> FMI1_IO5
|
||||
|
||||
/* Port 22 */
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO4 -> FMI1_IO4
|
||||
CFG_DISABLED | PULL_DOWN, // FMI1_DQS -> FMI1_DQS
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO3 -> FMI1_IO3
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO2 -> FMI1_IO2
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO1 -> FMI1_IO1
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO0 -> FMI1_IO7
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
|
||||
/* Port 24 */
|
||||
CFG_FUNC0, // I2C2_SDA -> I2C2_SDA_3V0
|
||||
CFG_FUNC0, // I2C2_SCL -> I2C2_SCL_3V0
|
||||
CFG_FUNC0, // UART0_TXD -> AP_UART0_TXD
|
||||
CFG_FUNC0, // UART0_RXD -> AP_UART0_RXD
|
||||
CFG_FUNC0, // UART5_RTXD ->
|
||||
CFG_FUNC0, // DP_HPD ->
|
||||
CFG_DISABLED, // TST_CLKOUT ->
|
||||
CFG_DISABLED, // TST_STPCLK ->
|
||||
|
||||
/* Port 25 */
|
||||
CFG_FUNC0, // WDOG -> AP_WDOG
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
return gpio_default_cfg;
|
||||
}
|
||||
@@ -0,0 +1,58 @@
|
||||
# Copyright (C) 2009-2010 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D1815=1 \
|
||||
WITH_SWI_BACKLIGHT=1 \
|
||||
TARGET_HIGH_SOC_VOLTAGE=CHIPID_SOC_VOLTAGE_MED \
|
||||
TARGET_HIGH_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_MED \
|
||||
TARGET_EMA_CTL_CPU_SEL=2 \
|
||||
TARGET_CPU_SOURCE=2 \
|
||||
TARGET_CPU_850M=1 \
|
||||
TARGET_DDR_256M=1 \
|
||||
TARGET_MIPI_DSI_SOURCE=1 \
|
||||
WITH_HW_BS=1 \
|
||||
TARGET_MANAGED2H_SOURCE=1 \
|
||||
TARGET_MANAGED2L_SOURCE=1 \
|
||||
TARGET_MANAGED2H_DIV=2 \
|
||||
TARGET_MANAGED2L_DIV=2 \
|
||||
TARGET_PCLK1_SOURCE=2 \
|
||||
TARGET_PCLK1_DIV=6 \
|
||||
TARGET_GFX_SOURCE=2 \
|
||||
TARGET_GFX_SLC_SOURCE=2 \
|
||||
TARGET_IOP_SOURCE=3 \
|
||||
TARGET_LPERFS_SOURCE=3 \
|
||||
TARGET_HPERFNRT_SOURCE=0 \
|
||||
TARGET_DSIM_DPHYCTL=0x30 \
|
||||
TARGET_USE_HSIC=1 \
|
||||
TARGET_USB_DEVICE_SELF_POWERED=1 \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
AMC_CHANNEL_WIDTH=4 \
|
||||
BT_DTPATH=\"arm-io/uart1/bluetooth\" \
|
||||
ETHERNET_DTPATH=\"arm-io/usb-complex/usb-ehci/lan0\" \
|
||||
WIFI_DTPATH=\"arm-io/usb-complex/usb-ehci/wlan\" \
|
||||
WITH_TARGET_AMC_PARAMS=1 \
|
||||
WITH_TARGET_AMG_PARAMS=1
|
||||
|
||||
ifeq ($(PRODUCT),iBoot)
|
||||
OPTIONS += \
|
||||
DP_DTPATH=\"arm-io/displayport\" \
|
||||
WITH_HW_DISPLAY_DISPLAYPORT=1
|
||||
endif
|
||||
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
Reference in new issue
Block a user