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@@ -0,0 +1,27 @@
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/*
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* Copyright (C) 2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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||||
*
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||||
* This document may not be reproduced or transmitted in any form,
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||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* J33i specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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#define GPIO_BOARD_REV0 GPIO(12, 3)
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#define GPIO_BOARD_REV1 GPIO(12, 4)
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#define GPIO_BOARD_REV2 GPIO(12, 5)
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#define GPIO_BOARD_REV3 GPIO(12, 6)
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#define HDMI_DDC_IIC_BUS 2
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,92 @@
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// Copyright (C) 2008-2010 Apple, Inc. All rights reserved.
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//
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// This document is the property of Apple, Inc.
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// It is considered confidential and proprietary.
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//
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// This document may not be reproduced or transmitted in any form,
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// in whole or in part, without the express written permission of
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// Apple, Inc.
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//
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// NOTE: This is a generated file and should not be hand-edited!
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//
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// =============================================================================
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// Nand Geometry Table
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static NandGeometry _nandGeometryTable[] =
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{
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};
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// =============================================================================
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// Nand Timing Table
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static NandTiming _nandTimingTable[] =
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{
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};
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#if (defined (AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
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// =============================================================================
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// NandChipId Description
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const NandChipIdDescription _nandChipIdDescriptionTable[] =
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{
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};
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// =============================================================================
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// Nand Description Table
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static const NandDescription _nandDescriptionTable[] =
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{
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};
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const UInt32 _nandDescriptionTableSize = sizeof(_nandDescriptionTable) / sizeof(NandDescription);
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#endif // (defined(AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
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// =============================================================================
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// Nand Board Support Table
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static NandBoardSupport _nandBoardSupportTable[] =
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{
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};
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// =============================================================================
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// Nand Board Timing Table
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static NandBoardInfo _nandBoardInfo =
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{
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/* controlDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* dataDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* chipEnableDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* socToNandRiseNanosecs */ 3,
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/* socToNandFallNanosecs */ 3,
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/* nandToSocRiseNanosecs */ 3,
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/* nandToSocFallNanosecs */ 4,
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/* landing map */
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{
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0x00000001
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},
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/* useToggleMode */ TRUE32,
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/* useDiffDQSMode */ FALSE32,
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/* useDiffREMode */ FALSE32,
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/* useVref */ TRUE32,
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/* useSingleHostChannel */ FALSE32,
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/* allowSingleChipEnable */ TRUE32
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};
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static NandFormat _nandFormatPpn =
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{
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/* metaPerLogicalPage */ 16,
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/* validMetaPerLogicalPage */ 16,
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/* logicalPageSize */ 4096
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};
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static NandFormat _nandFormatRaw =
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{
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/* metaPerLogicalPage */ 12,
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/* validMetaPerLogicalPage */ 10,
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/* logicalPageSize */ 0
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};
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@@ -0,0 +1,98 @@
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/*
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* Copyright (C) 2009-2010 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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// XXX derived from values read from regs on K66 Dev 0 board; need to
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// reconcile these with OTP doc (which appears to differ) and intended
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// settings
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// XXX also, need to reconcile OTP settings between K66 Dev 0 and K66 Proto 0
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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{ PMU_IIC_BUS, kD1815_LDO1, 0x00 }, // PP2V5_BS 2.50V
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{ PMU_IIC_BUS, kD1815_LDO2, 0x1E }, // PP1V8_AP_PVDDP 1.80V
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{ PMU_IIC_BUS, kD1815_LDO3, 0x0A }, // PP3V0_USBMUX 3.00V
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{ PMU_IIC_BUS, kD1815_LDO4, 0x00 }, // PP1V8_AP_DAC 3.00V
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{ PMU_IIC_BUS, kD1815_LDO5, 0x0A }, // PPNNAD 3.00V
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{ PMU_IIC_BUS, kD1815_LDO6, 0x0A }, // PP3V0_MCU 3.00V
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{ PMU_IIC_BUS, kD1815_LDO7, 0x03 }, // PP1V8_AP_VDD 1.80V
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{ PMU_IIC_BUS, kD1815_LDO8, 0x00 }, // PP3V0_CPU 2.00V
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{ PMU_IIC_BUS, kD1815_LDO9, 0x00 }, // PP1V2_HSIC 1.20V
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{ PMU_IIC_BUS, kD1815_LDO10, 0x0A }, // PP3V0_IO 3.00V
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{ PMU_IIC_BUS, kD1815_LDO11, 0x02 }, // PP1V8_AP_VIDEO 1.80V
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{ PMU_IIC_BUS, kD1815_LDO12, 0x10 }, // PP1V0_AP 1.00V
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{ PMU_IIC_BUS, kD1815_LCM_CONTROL1, 0x05 }, // unused
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{ PMU_IIC_BUS, kD1815_LCM_CONTROL2, 0x0E }, // unused
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{ PMU_IIC_BUS, kD1815_LCM_CONTROL3, 0x00 }, // VBOOST_LCM 5.10V
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{ PMU_IIC_BUS, kDIALOG_LDO_CONTROL, 0x00 }, // Leave bypass off
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD1815_ACTIVE1, 0xFF }, //
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{ PMU_IIC_BUS, kD1815_ACTIVE2, 0x3F }, //
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{ PMU_IIC_BUS, kD1815_ACTIVE3, 0x0C }, // VBOOST_LCM, CPU_SW, WDig
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL, 0 }, // Disable SWI by default
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{ PMU_IIC_BUS, kDIALOG_ADC_CONTROL, kDIALOG_ADC_CONTROL_DEFAULTS },
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// <rdar://problem/12297780> J33i: Configure PMU Register 0x2a to 0xa8 for iBoot, iOS
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{ PMU_IIC_BUS, kDIALOG_BUCK_CONTROL2, 0xA8 },
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{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_A, 0xC0 },
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{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_B, 0xFF },
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{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_C, 0xBF },
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{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_D, 0xFF },
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{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_E, 0xAE },
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{ PMU_IIC_BUS, kDIALOG_IRQ_MASK_F, 0xFF },
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};
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// XXX: review setup for each GPIO and add back decoded description of each config
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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{ PMU_IIC_BUS, kD1815_SYS_GPIO_1, 0xB9 }, // ENBL_USB_BUFF_L
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{ PMU_IIC_BUS, kD1815_SYS_GPIO_2, 0xBA }, // LAN_PME_PMU
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{ PMU_IIC_BUS, kD1815_SYS_GPIO_3, 0xBA }, // WLAN_WAKE_HOST
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{ PMU_IIC_BUS, kD1815_SYS_GPIO_4, 0x03 }, // ENET_PWR_EN_L
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{ PMU_IIC_BUS, kD1815_SYS_GPIO_5, 0x01 }, // WLAN_PWR_EN_L
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{ PMU_IIC_BUS, kD1815_SYS_GPIO_6, 0xFA }, // VBAT_DETECT
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{ PMU_IIC_BUS, kD1815_SYS_GPIO_7, 0xBA }, // BT_HOST_WAKE
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{ PMU_IIC_BUS, kD1815_SYS_GPIO_8, 0x18 }, // WLAN_RESET_L
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{ PMU_IIC_BUS, kD1815_SYS_GPIO_TEMP, 0x18 }, // LAN_RESET_L
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{ PMU_IIC_BUS, kD1815_SYS_GPIO_SPARE, 0x4B }, // WLAN_CLK32K_R
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{ PMU_IIC_BUS, kD1815_SYS_GPIO_DEB6, 0x80 }, // enable 32kHz clocks in hibernate
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};
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static const struct core_rails_struct soc_rails[] =
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{
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};
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#endif /* POWERCONFIG_PMU_SETUP */
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#define TARGET_POWER_NO_BATTERY 1
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#define TARGET_POWER_USB_MASK STATUS_FLAG_MAKE(0, kD1815_STATUS_A_VBUS_EXT)
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#define ALWAYS_BOOT_BATTERY_VOLTAGE (3000)
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#define PRECHARGE_BACKLIGHT_LEVEL 103
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#endif
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@@ -0,0 +1,21 @@
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/*
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* Copyright (C) 2009 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_UARTCONFIG_H
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#define __TARGET_UARTCONFIG_H
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/* define two debug serial ports */
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#define DEBUG_SERIAL_PORT (3)
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#define MCU_SERIAL_PORT (1)
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#define UART_FLOWCONTROL_MASK (0x08)
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#endif
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@@ -0,0 +1,218 @@
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/*
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* Copyright (C) 2009-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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||||
* It is considered confidential and proprietary.
|
||||
*
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||||
* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <drivers/display.h>
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#include <drivers/hdmi.h>
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#include <drivers/flash_nor.h>
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#include <drivers/iic.h>
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#include <drivers/power.h>
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#include <drivers/mcu.h>
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#include <lib/devicetree.h>
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#include <lib/env.h>
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#include <lib/mib.h>
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#include <lib/syscfg.h>
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#include <platform.h>
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#include <platform/gpio.h>
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#include <platform/gpiodef.h>
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#include <platform/memmap.h>
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#include <sys.h>
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#include <sys/boot.h>
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#include <sys/menu.h>
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#include <sys/task.h>
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#include <target.h>
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#include <target/powerconfig.h>
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static u_int32_t j33i_get_board_rev(void);
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MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 1);
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MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
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static uint32_t display_config;
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void target_early_init(void)
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{
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// <rdar://problem/12315444> J33i: HDMI DDC - change tSU;STA interval (iOS & iBoot).
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iic_set_filter(2, 0x4A334009);
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//<rdar://problem/12711386> J33i: iBoot DDC speed should be ~50 kHz
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iic_set_frequency(2, 50000);
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}
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void target_late_init(void)
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{
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#if WITH_HW_MCU
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// Late display initialization. Needed to wait for MCU.
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mcu_init();
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#endif
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#if WITH_HW_DISPLAY_HDMI
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// Backgrounded. See hdmi_device_wait_started() call below.
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hdmi_init();
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#endif
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}
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void target_init(void)
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{
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#if WITH_HW_FLASH_NOR
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flash_nor_init(SPI_NOR0);
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#endif
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}
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void target_quiesce_hardware(void)
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{
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#if WITH_HW_MCU
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// radar 9746416 -- UART4 left in interrupt mode will cause kernel panic
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mcu_quiesce_uart();
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#endif
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}
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void target_poweroff(void)
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{
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}
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int target_debug_init(void)
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{
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||||
#if WITH_HW_MCU
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mcu_start_recover();
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#endif
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return 0;
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||||
}
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int target_bootprep(enum boot_target target)
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{
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||||
switch (target) {
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case BOOT_DARWIN:
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case BOOT_DIAGS:
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#if WITH_HW_MCU
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||||
#if WITH_HW_DISPLAY_HDMI && PRODUCT_IBOOT
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/* Potentially delay boot so we have a
|
||||
* logo. We might have to do this if a
|
||||
* connected TV is particularly slow at
|
||||
* responding to EDID. Sorry. */
|
||||
hdmi_device_wait_started();
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||||
#endif
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||||
mcu_start_boot();
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#endif
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break;
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||||
case BOOT_DARWIN_RESTORE:
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break;
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||||
default:
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||||
// do nothing
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break;
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||||
}
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||||
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||||
return 0;
|
||||
}
|
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|
||||
bool target_should_recover(void)
|
||||
{
|
||||
// trigger recovery mode whenever USB is attached, unless
|
||||
// environment variable says otherwise.
|
||||
|
||||
return power_has_usb() && !env_get_bool("auto-boot-usb", true);
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
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||||
// always powers on
|
||||
return true;
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
// never power off
|
||||
return false;
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
// u_int32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
// gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
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||||
}
|
||||
#endif // APPLICATION_IBOOT
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||||
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||||
void * target_get_display_configuration(void)
|
||||
{
|
||||
display_config = 0x00000000;
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||||
return ((void *)&display_config);
|
||||
}
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
env_set("boot-device", "nand0", 0);
|
||||
env_set("display-color-space","RGB888", 0);
|
||||
env_set("display-timing", "720p-hdmi", 0);
|
||||
env_set("idle-off", "false", 0); // do not idle off; there is no battery and this will just reboot (8035422)
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
DTNode *node;
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
// Update the pmu node with the actual vcore values
|
||||
if (FindNode(0, "arm-io/i2c0/pmu", &node)) {
|
||||
propName = "swi-vcores";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
platform_get_soc_voltages(propSize / sizeof(u_int32_t), propData);
|
||||
}
|
||||
}
|
||||
|
||||
if (FindNode(0, "arm-io/mcu0", &node)) {
|
||||
propName = "board-rev";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
((u_int32_t *)propData)[0] = j33i_get_board_rev();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
static u_int32_t j33i_get_board_rev(void)
|
||||
{
|
||||
u_int32_t gpio_board_rev;
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV3, GPIO_PDN);
|
||||
|
||||
spin(100); // Wait 100us
|
||||
|
||||
gpio_board_rev =
|
||||
(gpio_read(GPIO_BOARD_REV3) << 3) |
|
||||
(gpio_read(GPIO_BOARD_REV2) << 2) |
|
||||
(gpio_read(GPIO_BOARD_REV1) << 1) |
|
||||
(gpio_read(GPIO_BOARD_REV0) << 0);
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_DFLT);
|
||||
|
||||
return (gpio_board_rev &0xF);
|
||||
}
|
||||
@@ -0,0 +1,187 @@
|
||||
/*
|
||||
* Copyright (C) 2009-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <target.h>
|
||||
|
||||
/* S5L8947X FPGA Pin Configuration */
|
||||
#define DFU_STATUS_DRIVE_STR DRIVE_X1
|
||||
#define FMI_DRIVE_STR DRIVE_X2
|
||||
|
||||
static const u_int32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
/* Port 0 */
|
||||
CFG_IN, // 00/I2S0_MCK -> AP_TO_MCU_RESET_3V0_L
|
||||
CFG_IN, // 01/I2S0_LRCK -> AP_TO_MCU_TCK_3V0
|
||||
CFG_IN, // 02/I2S0_BCLK -> AP_MCU_INT
|
||||
CFG_DISABLED, // 03/I2S0_DOUT ->
|
||||
CFG_OUT, // 04/I2S0_DIN -> VCORE_ADJ_R
|
||||
CFG_FUNC0, // 05/UART0_TXD -> UART0_TXD
|
||||
CFG_FUNC0, // 06/UART0_RXD -> UART0_RXD
|
||||
CFG_FUNC0, // 07/UART1_TXD -> UART1_TXD
|
||||
/* Port 1 */
|
||||
CFG_FUNC0, // 08/UART1_RXD -> UART1_RXD
|
||||
CFG_FUNC0, // 09/I2C1_SDA -> I2C1_SDA_3V0
|
||||
CFG_FUNC0, // 10/I2C1_SCL -> I2C1_SCL_3V0
|
||||
CFG_FUNC0, // 11/HDMI_HPD -> HDMI_HDP
|
||||
CFG_FUNC0, // 12/HDMI_CEC -> HDMI_CEC
|
||||
CFG_FUNC0, // 13/I2C2_SDA -> AP_DDC_DATA_3V0
|
||||
CFG_FUNC0, // 14/I2C2_SCL -> AP_DDC_CLK_3V0
|
||||
CFG_FUNC0, // 15/SPDIF -> AP_SPDIF_OUT_R_3V0
|
||||
/* Port 2 */
|
||||
CFG_IN, // 16/GPIO22 -> USB_DEVMUX_SEL_C0,
|
||||
CFG_DISABLED, // 17/GPIO23 ->
|
||||
CFG_FUNC0, // 18/UART2_TXD -> AP_UART2_TXD
|
||||
CFG_FUNC0, // 19/UART2_RXD -> AP_UART2_RXD
|
||||
CFG_OUT_1, // 20/UART2_RTSN -> AP_UART2_RTS_L
|
||||
CFG_FUNC0, // 21/UART2_CTSN -> AP_UART2_CTS_L
|
||||
CFG_FUNC0, // 22/UART3_TXD -> UART3_TXD
|
||||
CFG_FUNC0, // 23/UART3_RXD -> UART3_RXD
|
||||
/* Port 3 */
|
||||
CFG_FUNC0, // 24/UART4_TXD -> UART4_TXD
|
||||
CFG_FUNC0, // 25/UART4_RXD -> UART4_RXD
|
||||
CFG_DISABLED, // 26/TST_CLKOUT ->
|
||||
CFG_DISABLED, // 27/TST_STPCLK ->
|
||||
CFG_FUNC0, // 28/WDOG -> AP_WDOG
|
||||
CFG_DISABLED, // 29
|
||||
CFG_DISABLED, // 30
|
||||
CFG_DISABLED, // 31
|
||||
/* Port 4 */
|
||||
CFG_FUNC0, // 32/ENET_MDC -> ENET_MDC
|
||||
CFG_FUNC0, // 33/ENET_MDIO -> ENET_MDIO
|
||||
CFG_FUNC0, // 34/RMII_CLK -> RMII_CLK
|
||||
CFG_FUNC0, // 35/RMII_RXER -> RMII_RXER
|
||||
CFG_FUNC0, // 36/RMII_TXD0 -> RMII_TXD0
|
||||
CFG_FUNC0, // 37/RMII_CRSDV -> RMII_CRSDV
|
||||
CFG_FUNC0, // 38/RMII_RXD0 -> RMII_RXD0
|
||||
CFG_FUNC0, // 39/RMII_RXD1 -> RMII_RXD1
|
||||
/* Port 5 */
|
||||
CFG_FUNC0, // 40/RMII_TXD1 -> RMII_TXD1
|
||||
CFG_FUNC0, // 41/RMII_TXEN -> RMII_TXEN
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // 42/FMI0_CEN1 -> FMI0_CEN1
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // 43/FMI0_CEN0 -> FMI0_CEN0
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // 44/FMI0_CLE -> FMI0_CLE
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // 45/FMI0_ALE -> FMI0_ALE
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // 46/FMI0_REN -> FMI0_REN
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // 47/FMI0_WEN -> FMI0_WEN
|
||||
/* Port 6 */
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 48/FMI0_IO7 -> FMI0_IO7
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 49/FMI0_IO6 -> FMI0_IO6
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 50/FMI0_IO5 -> FMI0_IO5
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 51/FMI0_IO4 -> FMI0_IO4
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 52/FMI0_DQS -> FMI0_DQS
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 53/FMI0_IO3 -> FMI0_IO3
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 54/FMI0_IO2 -> FMI0_IO2
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 55/FMI0_IO1 -> FMI0_IO1
|
||||
/* Port 7 */
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 56/FMI0_IO0 -> FMI0_IO0
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // 57/FMI1_CEN1 -> FMI1_CEN1
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // 58/FMI1_CEN0 -> FMI1_CEN0
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // 59/FMI1_CLE -> FMI1_CLE
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // 60/FMI1_ALE -> FMI1_ALE
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // 61/FMI1_REN -> FMI1_REN
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // 62/FMI1_WEN -> FMI1_WEN
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 63/FMI1_IO7 -> FMI1_IO7
|
||||
/* Port 8 */
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 64/FMI1_IO6 -> FMI1_IO6
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 65/FMI1_IO5 -> FMI1_IO5
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 66/FMI1_IO4 -> FMI1_IO4
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 67/FMI1_DQS -> FMI1_DQS
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 68/FMI1_IO3 -> FMI1_IO3
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 69/FMI1_IO2 -> FMI1_IO2
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 70/FMI1_IO1 -> FMI1_IO1
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // 71/FMI1_IO0 -> FMI1_IO0
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // 72
|
||||
CFG_DISABLED, // 73
|
||||
CFG_DISABLED, // 74
|
||||
CFG_DISABLED, // 75
|
||||
CFG_DISABLED, // 76
|
||||
CFG_DISABLED, // 77
|
||||
CFG_DISABLED, // 78
|
||||
CFG_DISABLED, // 79
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // 80
|
||||
CFG_DISABLED, // 81
|
||||
CFG_DISABLED, // 82
|
||||
CFG_DISABLED, // 83
|
||||
CFG_DISABLED, // 84
|
||||
CFG_DISABLED, // 85
|
||||
CFG_DISABLED, // 86
|
||||
CFG_DISABLED, // 87
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // 88
|
||||
CFG_DISABLED, // 89
|
||||
CFG_DISABLED, // 90
|
||||
CFG_DISABLED, // 91
|
||||
CFG_DISABLED, // 92
|
||||
CFG_DISABLED, // 93
|
||||
CFG_DISABLED, // 94
|
||||
CFG_DISABLED, // 95
|
||||
/* Port 12 */
|
||||
CFG_IN, // 96/GPIO0 -> MENU_KEY (REQUEST_DFU2)
|
||||
CFG_IN, // 97/GPIO1 -> HOLD_KEY (REQUEST_DFU1)
|
||||
CFG_DISABLED, // 98/GPIO2 ->
|
||||
CFG_IN | PULL_DOWN, // 99/GPIO3 -> BOARD_REV[0]
|
||||
CFG_IN | PULL_DOWN, // 00/GPIO4 -> BOARD_REV[1]
|
||||
CFG_IN | PULL_DOWN, // 01/GPIO5 -> BOARD_REV[2]
|
||||
CFG_IN | PULL_DOWN, // 02/GPIO6 -> BOARD_REV[3]
|
||||
CFG_DISABLED, // 03/GPIO7 ->
|
||||
/* Port 13 */
|
||||
CFG_OUT_1, // 04/GPIO8 -> BT_EN
|
||||
CFG_IN, // 05/GPIO9 -> BT_WAKE
|
||||
CFG_DISABLED, // 06/GPIO10 ->
|
||||
CFG_IN, // 07/GPIO11 -> LAN_HSIC_DEVICE_RDY
|
||||
CFG_DISABLED, // 08/GPIO12 ->
|
||||
CFG_IN | PULL_UP, // 09/GPIO13 -> PMU_IRQ_L
|
||||
CFG_DISABLED, // 10/GPIO14 ->
|
||||
CFG_DISABLED, // 11/GPIO15 ->
|
||||
/* Port 14 */
|
||||
CFG_IN | PULL_DOWN, // 12/GPIO16 -> BOARD_ID[3]
|
||||
CFG_OUT, // 13/GPIO17 -> WLAN0_HSIC_HOST_READY
|
||||
CFG_IN | PULL_DOWN, // 14/GPIO18 -> BOOT_CONFIG[0]
|
||||
CFG_OUT_0, // 15/GPIO19 -> KEEPACT
|
||||
CFG_DISABLED, // 16
|
||||
CFG_DISABLED, // 17
|
||||
CFG_DISABLED, // 18
|
||||
CFG_DISABLED, // 19
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // 20
|
||||
CFG_DISABLED, // 21
|
||||
CFG_DISABLED, // 22
|
||||
CFG_DISABLED, // 23
|
||||
CFG_DISABLED, // 24
|
||||
CFG_DISABLED, // 25
|
||||
CFG_DISABLED, // 26
|
||||
CFG_DISABLED, // 27
|
||||
/* Port 16 */
|
||||
CFG_IN, // 28/GPIO20 -> WLAN0_HSIC_DEVICE_READY
|
||||
CFG_IN, // 29/GPIO21 -> USB_DEVMUX_SEL_C0
|
||||
CFG_DISABLED, // 30/GPIO24 ->
|
||||
CFG_IN | PULL_DOWN, // 31/GPIO25 -> BOOT_CONFIG[1]
|
||||
CFG_IN | PULL_DOWN, // 32/GPIO26 -> FORCE_DFU
|
||||
CFG_OUT_0 | DFU_STATUS_DRIVE_STR | PULL_DOWN, // 33/GPIO27 -> DFU_STATUS
|
||||
CFG_IN | PULL_DOWN, // 34/GPIO28 -> BOOT_CONFIG[2]
|
||||
CFG_IN | PULL_DOWN, // 35/GPIO29 -> BOOT_CONFIG[3]
|
||||
/* Port 17 */
|
||||
CFG_FUNC0, // 36/I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0, // 37/I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_DISABLED, // 38/TMR32_PWM0 ->
|
||||
CFG_IN | PULL_DOWN, // 39/SPI0_SCLK -> BOARD_ID[0]
|
||||
CFG_IN | PULL_DOWN, // 40/SPI0_MOSI -> BOARD_ID[1]
|
||||
CFG_IN | PULL_DOWN, // 41/SPI0_MISO -> BOARD_ID[2]
|
||||
CFG_DISABLED | PULL_UP, // 42/SPI0_SSIN ->
|
||||
CFG_FUNC0, // 43/SWI_DATA -> SWI_AP
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
return gpio_default_cfg;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
# Copyright (C) 2009-2010 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D1815=1 \
|
||||
WITH_SWI_BACKLIGHT=1 \
|
||||
TARGET_CPU_SOURCE=2 \
|
||||
TARGET_CPU_850M=1 \
|
||||
TARGET_DDR_533M=1 \
|
||||
TARGET_MIPI_DSI_SOURCE=0 \
|
||||
WITH_HW_BS=1 \
|
||||
TARGET_MANAGED2H_SOURCE=1 \
|
||||
TARGET_MANAGED2L_SOURCE=1 \
|
||||
TARGET_MANAGED2H_DIV=2 \
|
||||
TARGET_MANAGED2L_DIV=2 \
|
||||
TARGET_PCLK1_SOURCE=2 \
|
||||
TARGET_PCLK1_DIV=10 \
|
||||
TARGET_GFX_SOURCE=3 \
|
||||
TARGET_GFX_SLC_SOURCE=3 \
|
||||
TARGET_IOP_SOURCE=0 \
|
||||
TARGET_LPERFS_SOURCE=0 \
|
||||
TARGET_HPERFNRT_SOURCE=2 \
|
||||
TARGET_USE_PREDIV4=1 \
|
||||
TARGET_PREDIV4_DIV=2 \
|
||||
TARGET_PREDIV4_SOURCE=3 \
|
||||
TARGET_USE_HSIC=1 \
|
||||
TARGET_USB_DEVICE_SELF_POWERED=1 \
|
||||
AMC_NUM_CHANNELS=1 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
AMC_CHANNEL_WIDTH=4 \
|
||||
BT_DTPATH=\"arm-io/uart2/bluetooth\" \
|
||||
ETHERNET_DTPATH=\"arm-io/ethernet\" \
|
||||
WIFI_DTPATH=\"arm-io/usb0-complex/usb0-ehci/wlan\"
|
||||
|
||||
ifeq ($(PRODUCT),iBoot)
|
||||
OPTIONS += \
|
||||
WITH_HW_DISPLAY_HDMI=1
|
||||
endif
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
Reference in new issue
Block a user