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@@ -0,0 +1,32 @@
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/*
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* Copyright (C) 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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||||
*
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||||
* This document may not be reproduced or transmitted in any form,
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||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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||||
*/
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#ifndef __TARGET_ADBE_SETTINGS_H
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#define __TARGET_ADBE_SETTINGS_H
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static struct adbe_v1_tuneable adbe_tuneables[] = {
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{
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.name = "default",
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.adbe0_vblank_pos_vbi_pulse = 0x0000,
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.adbe0_vblank_clk_gate_wakeup = 0x0000,
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.adbe0_vblank_clk_gate_idle = 0x0001,
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.adbe0_vblank_blk_idle_dpb = 0x0000,
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.adbe0_vblank_blk_idle_aap = 0x0000,
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/*
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* disable all clock gating until SEG resolves:
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* <rdar://problem/13305313> J34: adbe dynamic clock gating causes no video on dp_tx
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*/
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.adbe0_tunable_mode_ctrl = 0,
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.adbe0_aap_support = 1,
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},
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};
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#endif
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@@ -0,0 +1,106 @@
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/*
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* Copyright (C) 2011-2014 Apple Inc. All rights reserved.
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||||
*
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||||
* This document is the property of Apple Inc.
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||||
* It is considered confidential and proprietary.
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*
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||||
* This document may not be reproduced or transmitted in any form,
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||||
* in whole or in part, without the express written permission of
|
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* Apple Inc.
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*/
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static const struct amc_param amc_params = {
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.flags = (FLAG_AMC_PARAM_BUSTAT23 | FLAG_AMC_PARAM_SLOW_BOOT | FLAG_AMC_PARAM_ZQCL),
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.tREFi = 0x5d,
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.longsrcnt = 0x2008,
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.srextrarefcnt = 0x00020000,
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.rdlat = 6,
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.wrlat = 3,
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.phyrdlat = 10,
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.phywrlat = 2,
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.pdn = 0x22000403,
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.read = 0x00000203,
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.bustat = 0x00222209,
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.bustat2 = 0x00222209,
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.derate = 0x2483135b,
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.mcphyupdate = 0x05030000,
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.autoref_params = 0x00000021,
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.pwrmngtparam_small = 0x00011000,
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.pwrmngtparam_guided = 0x01801000,
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.chnldec = 0x00050000,
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.aref_freq0 = 0x00000110,
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.schen_default = 0x00000110,
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.mr1 = 0x44,
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.mr2 = 0x1a,
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.mr3 = 0x01,
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.pwrmngten_default = 0x00100100,
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.mcphyupdate1 = 0x00000001,
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.odts = 0x190,
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.readleveling = 0x00000300,
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.offset_shift_hynix = 0,
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.offset_shift_elpida = 1,
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.freq = {
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{ // 800MHz
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.cas = 0x00000308,
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.pch = 0x00030612,
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.act = 0x12040908,
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.autoref = 0x19350000,
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.selfref = 0x00039060,
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.modereg = 0x20250782,
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.mifcassch = 0x00000110,
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.arefparam = 0x0c022131,
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},
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{ // 400MHz
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.cas = 0x00000005,
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.pch = 0x00000009,
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.act = 0x09020505,
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.autoref = 0x0d1b0000,
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.selfref = 0x0001d000,
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.modereg = 0x00130000,
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.mifcassch = 0x00000000,
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.arefparam = 0x00000101,
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},
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{ // 200MHz
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.cas = 0x00000003,
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.pch = 0x00000005,
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.act = 0x08020303,
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.autoref = 0x070e0000,
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.selfref = 0x0000f000,
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.modereg = 0x000a0000,
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.mifcassch = 0x00000000,
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.arefparam = 0x00000101,
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},
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{ // 50MHz
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.cas = 0x00000003,
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.pch = 0x00000003,
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.act = 0x08020303,
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.autoref = 0x02040000,
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.selfref = 0x00004000,
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.modereg = 0x00030000,
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.mifcassch = 0x00000000,
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.arefparam = 0x00000101,
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}
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}
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};
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static const struct amc_tunable amc_tunables[] = {
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{ &rAMC_MCSARBCFG, 0x00000001 },
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{ &rAMC_OPIDLETMR, 0x00200000 },
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{ &rAMC_OPTMRADJPARAM, 0x20400064 },
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{ &rAMC_MIFACTSCH, 0x00000001 },
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{ &rAMC_MIFCASSCH_FREQ(0), 0x10000010 },
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{ &rAMC_PSQRQCTL0, 0xff010110 },
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{ &rAMC_PSQRQCTL1, 0x00001728 },
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{ &rAMC_PSQRQTIMER0, 0x00000040 },
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{ &rAMC_PSQRQTIMER1, 0x00000014 },
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{ &rAMC_PSQRQTIMER2, 0x00000040 },
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{ &rAMC_PSQRQBRST, 0x04100410 },
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{ &rAMC_PSQRQSCHCRD, 0x00101400 },
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{ &rAMC_PSQWQCTL0, 0x00010100 },
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{ &rAMC_PSQWQBRST, 0x04100410 },
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{ &rAMC_PSQWQSCHCRD, 0x00101400 },
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{ &rAMC_MCUQOS, 0x00001919 },
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{ &rAMC_MCUQOSLLT, 0x0000011f },
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};
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ASPNANDCONFIG_H
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#define __TARGET_ASPNANDCONFIG_H
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//MLC devices
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#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
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#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_DIES_IN_PARALLEL 4
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#define ASPNAND_READ_DIES_IN_PARALLEL 4
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#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
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//TLC devices
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#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
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// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
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#define ASPNAND_INDIRECTION_MEMORY (2*1024*1024)
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#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
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#endif
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@@ -0,0 +1,36 @@
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/*
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* Copyright (C) 2014 Apple Inc. All rights reserved.
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||||
*
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||||
* This document is the property of Apple Inc.
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||||
* It is considered confidential and proprietary.
|
||||
*
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||||
* This document may not be reproduced or transmitted in any form,
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||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* j34m specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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/* Board Revision */
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#define GPIO_BOARD_REV0 GPIO(14, 6)
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#define GPIO_BOARD_REV1 GPIO(14, 5)
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#define GPIO_BOARD_REV2 GPIO(14, 4)
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#define GPIO_BOARD_REV3 GPIO(14, 3)
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/* which IICs to initialize */
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#define IICS_MASK (0xD)
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#define TRISTAR_IIC_BUS (2)
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/* D2089 watchdog tickle, 'KEEPACT' */
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#define GPIO_WDOG_TICKLE GPIO(12, 6)
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#define POWER_GPIO_HVR_RESET_L (5)
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,83 @@
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD2089_ACTIVE2, 0x03 }, // WLEDA/B BST
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{ PMU_IIC_BUS, kD2089_BUCK4_VSEL, 0xD0 }, // rdar:// 15918274 PP1V2_S2R
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{ PMU_IIC_BUS, kD2089_BUCK4_VSEL_ALT, 0xD0 }, //
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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};
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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/* GPIO configuration from I/O spreadsheet.
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<rdar://problem/15995289> J34m: IO spreadsheet
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Request spreadsheet update before modifying
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update GPIO1,15 and remove dup of OTP per <rdar://16415219> J34m: set iBoot PMU GPIOs to IOSpreadsheet
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update GPIO1 per <rdar://problem/16502988> J34m: PMU register for GPIO1 not set properly
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*/
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{ PMU_IIC_BUS, kD2089_GPIO1, 0x01 }, // PHY_SEL Out 0, Push-Pull, no PU
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{ PMU_IIC_BUS, kD2089_GPIO3, 0x09 }, // PMU_GPIO_BT_REG_ON Out 0, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD2089_GPIO4, 0x09 }, // PMU_GPIO_WLAN_REG_ON Out 0, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD2089_GPIO7, 0xBA }, // PMU_GPIO_BT2PMU_HOST_WAKE In, R Edge, Wake, PD
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{ PMU_IIC_BUS, kD2089_GPIO8, 0xBA }, // PMU_GPIO_WLAN2PMU_HOST_WAKE In, R Edge, Wake, PD
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{ PMU_IIC_BUS, kD2089_GPIO12, 0x7B }, // GPIO_TS2SOC2PMU_INT In, Hi level, Wake, PD
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{ PMU_IIC_BUS, kD2089_GPIO15, 0x88 }, // MOCA_LINK_L In, Lo level, PU, VBUCK3
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{ PMU_IIC_BUS, kD2089_GPIO16, 0x18 }, // PMU_LAN2_RESET_L Out 0, Open-Drain, No PU
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{ PMU_IIC_BUS, kD2089_GPIO17, 0xA1 }, // VBAT_DETECT In, R Edge, PD, VCC_MAIN
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{ PMU_IIC_BUS, kD2089_GPIO_DEB3, 0x20 }, // GPIO5_DEBOUNCE=0, rdar://16735592 Debounce of ENET_DET needs to be disabled
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{ PMU_IIC_BUS, kD2089_BUCK_DWI_CTRL0, 0x03 }, // enable DWI for BUCK0, BUCK1
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{ PMU_IIC_BUS, kD2089_ACT_TO_HIB_DLY, 0x03 }, // set ACT_TO_HIB_DLY to 3 (6ms)
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{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2, 0x11 }, // enable HIB_32kHz (for WIFI/BT) and DWI
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};
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static const struct pmu_setup_struct pmu_backlight_enable[] =
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{
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};
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static const struct pmu_setup_struct pmu_backlight_disable[] =
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{
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};
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static const struct core_rails_struct soc_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2089_BUCK2_VSEL }
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};
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static const struct core_rails_struct cpu_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2089_BUCK0_VSEL }
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};
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static const struct core_rails_struct ram_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2089_BUCK5_VSEL }
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};
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#endif /* POWERCONFIG_PMU_SETUP */
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#define TARGET_POWER_NO_BATTERY 1
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#define ALWAYS_BOOT_BATTERY_VOLTAGE (3000)
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#define PRECHARGE_BACKLIGHT_LEVEL 103
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#define TARGET_MAX_USB_INPUT_CURRENT 2400
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#define ACC_PWR_LDO (6)
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#endif
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@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define one debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (3)
|
||||
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#define MCU_SERIAL_PORT (1)
|
||||
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#define UART_FLOWCONTROL_MASK (0x08)
|
||||
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#endif
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@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_USBCONFIG_H
|
||||
#define __TARGET_USBCONFIG_H
|
||||
|
||||
#ifdef USBPHY_OTGTUNE0
|
||||
|
||||
#undef USBPHY_OTGTUNE0
|
||||
#define USBPHY_OTGTUNE0 (0x37449373)
|
||||
|
||||
#endif /* USBPHY_OTGTUNE0 */
|
||||
|
||||
#endif /* __TARGET_USBCONFIG_H */
|
||||
@@ -0,0 +1,320 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/displayport.h>
|
||||
#include <drivers/flash_nor.h>
|
||||
#include <drivers/iic.h>
|
||||
#include <drivers/power.h>
|
||||
#include <drivers/mcu.h>
|
||||
#include <lib/devicetree.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <lib/syscfg.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <sys.h>
|
||||
#include <sys/boot.h>
|
||||
#include <sys/menu.h>
|
||||
#include <sys/task.h>
|
||||
#include <target.h>
|
||||
#include <target/powerconfig.h>
|
||||
|
||||
// DEV Boards
|
||||
#define J34M_DEV0_BOARD (0x0) //Hoover Only
|
||||
#define J34M_DEV1_BOARD (0x1) //Hoover Only
|
||||
#define J34M_DEV2_BOARD (0x2) //Hoover Only
|
||||
// ...define other DEV Boards here...
|
||||
#define J34M_DEV_BOARD_LAST (0x7) //Hoover Only
|
||||
|
||||
// AP Boards
|
||||
#define J34M_AP_BOARD_FIRST (0x8) //Hoover Only
|
||||
// ...define AP Boards here...
|
||||
#define J34M_DVT_BOARD (0xC) //Hoover Only
|
||||
#define J34M_PVT_BOARD (0xF) //Hoover Only
|
||||
|
||||
// Do not delay iBoot by more than this amount from power on (microseconds).
|
||||
// Give up waiting for a boot logo and carry on at this point.
|
||||
#define kDPDeviceStartTimeout (8 * 1000 * 1000)
|
||||
extern utime_t gPowerOnTime;
|
||||
static bool gpio_board_rev_valid;
|
||||
static u_int32_t gpio_board_rev;
|
||||
#if WITH_HW_DISPLAY_DISPLAYPORT
|
||||
static dp_t dp_link_config = {
|
||||
.mode = 1,
|
||||
.type = 0,
|
||||
.min_link_rate = 0xa,
|
||||
.max_link_rate = 0xa,
|
||||
.lanes = 4,
|
||||
.ssc = 0,
|
||||
.alpm = 0,
|
||||
.vrr_enable = 0,
|
||||
.vrr_on = 0,
|
||||
};
|
||||
#endif
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 1);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
|
||||
static u_int32_t j34m_get_board_rev(void)
|
||||
{
|
||||
|
||||
if (!gpio_board_rev_valid) {
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PUP);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV3, GPIO_PUP);
|
||||
|
||||
spin(100); // Wait 100us
|
||||
|
||||
gpio_board_rev =
|
||||
(gpio_read(GPIO_BOARD_REV3) << 3) |
|
||||
(gpio_read(GPIO_BOARD_REV2) << 2) |
|
||||
(gpio_read(GPIO_BOARD_REV1) << 1) |
|
||||
(gpio_read(GPIO_BOARD_REV0) << 0);
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_DFLT);
|
||||
|
||||
gpio_board_rev_valid = true;
|
||||
}
|
||||
|
||||
printf("board_rev 0x%x\n", gpio_board_rev);
|
||||
|
||||
return gpio_board_rev;
|
||||
}
|
||||
|
||||
static void j34m_reset_hoover(bool reset)
|
||||
{
|
||||
power_set_gpio(POWER_GPIO_HVR_RESET_L, 1, !reset);
|
||||
}
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
if (target_config_dev() && j34m_get_board_rev() > J34M_DEV_BOARD_LAST) {
|
||||
platform_not_supported();
|
||||
}
|
||||
if (target_config_ap() && j34m_get_board_rev() < J34M_AP_BOARD_FIRST) {
|
||||
platform_not_supported();
|
||||
}
|
||||
|
||||
#if WITH_HW_MCU
|
||||
// Late display initialization. Needed to wait for MCU.
|
||||
mcu_init();
|
||||
#if WITH_HW_DISPLAY_DISPLAYPORT
|
||||
// Backgrounded. See dp_device_wait_started() call below.
|
||||
displayport_init(&dp_link_config);
|
||||
j34m_reset_hoover(false);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
#if WITH_HW_MCU
|
||||
// radar 9746416 -- UART4 left in interrupt mode will cause kernel panic
|
||||
mcu_quiesce_uart();
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
int target_debug_init(void)
|
||||
{
|
||||
#if WITH_HW_MCU
|
||||
mcu_start_recover();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
switch (target) {
|
||||
case BOOT_DARWIN:
|
||||
case BOOT_DIAGS:
|
||||
#if WITH_HW_MCU
|
||||
#if WITH_HW_DISPLAY_DISPLAYPORT && PRODUCT_IBOOT
|
||||
/* Potentially delay boot so we have a
|
||||
* logo. We might have to do this if a
|
||||
* connected TV is particularly slow at
|
||||
* responding to EDID. Sorry. */
|
||||
dp_device_wait_started(gPowerOnTime + kDPDeviceStartTimeout);
|
||||
#endif
|
||||
mcu_start_boot();
|
||||
#endif
|
||||
break;
|
||||
case BOOT_DARWIN_RESTORE:
|
||||
break;
|
||||
default:
|
||||
// do nothing
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
// trigger recovery mode whenever USB is attached, unless
|
||||
// environment variable says otherwise.
|
||||
|
||||
return power_has_usb() && !env_get_bool("auto-boot-usb", true);
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
// always powers on
|
||||
return true;
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
// never power off
|
||||
return false;
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
u_int32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
void * target_get_display_configuration(void)
|
||||
{
|
||||
#if WITH_HW_DISPLAY_DISPLAYPORT
|
||||
return ((void *)(&dp_link_config));
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
env_set("boot-device", "asp_nand", 0);
|
||||
env_set("display-color-space","RGB888", 0);
|
||||
env_set("display-timing", "720p-j34", 0);
|
||||
env_set("idle-off", "false", 0); // do not idle off; there is no battery and this will just reboot (8035422)
|
||||
}
|
||||
|
||||
#endif // WITH_ENV
|
||||
|
||||
bool target_has_tristar2(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
DTNode *node;
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
// Update the pmu node with the actual vcore values
|
||||
if (FindNode(0, "arm-io/i2c0/pmu", &node)) {
|
||||
propName = "swi-vcores";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
platform_get_soc_voltages(propSize / sizeof(u_int32_t), propData);
|
||||
}
|
||||
}
|
||||
//
|
||||
// TriStar 1 on older systems
|
||||
if (!target_has_tristar2()) {
|
||||
if (FindNode(0, "arm-io/i2c2/tristar", &node)) {
|
||||
propName = "compatible";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
strlcpy(propData, "tristar,cbtl1608", kPropNameLength);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (FindNode(0, "arm-io/mcu0", &node)) {
|
||||
propName = "board-rev";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
((u_int32_t *)propData)[0] = j34m_get_board_rev();
|
||||
}
|
||||
|
||||
// Store pinto mac address into products node
|
||||
if (FindNode(0, "product", &node)) {
|
||||
propName = "mac-address-pinto0";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (env_get("pintoaddr")) {
|
||||
env_get_ethaddr("pintoaddr", propData);
|
||||
} else {
|
||||
int retlen = 0;
|
||||
if (!target_get_property(TARGET_PROPERTY_PINTO_MACADDR, propData, 6, &retlen)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Store pinto mac address into pinto node
|
||||
if (FindNode(0, "arm-io/spi1/pinto", &node)) {
|
||||
propName = "local-mac-address";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (env_get("pintoaddr")) {
|
||||
env_get_ethaddr("pintoaddr", propData);
|
||||
} else {
|
||||
int retlen = 0;
|
||||
if (!target_get_property(TARGET_PROPERTY_PINTO_MACADDR, propData, 6, &retlen)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Store RBDA (Remote Bluetooth Device Address) into products node
|
||||
if (FindNode(0, "product", &node)) {
|
||||
propName = "bluetooth-dev-addr0";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (env_get("rbdaddr0")) {
|
||||
env_get_ethaddr("rbdaddr0", propData);
|
||||
} else {
|
||||
int retlen = 0;
|
||||
if (!target_get_property(TARGET_PROPERTY_BLUETOOTH_DEV_MACADDR0, propData, 6, &retlen)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,276 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <target.h>
|
||||
|
||||
/* THIS STRUCT IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: rev 0.40
|
||||
I/O Spreadsheet tracker: 16419127
|
||||
*/
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED, // 0 : TST_CLKOUT ->
|
||||
CFG_FUNC0 | FAST_SLEW, // 1 : WDOG -> WDOG_SOC
|
||||
CFG_IN, // 2 : GPIO0 -> MCU_AP_RECOVERY_MODE_L
|
||||
CFG_IN, // 3 : GPIO1 -> MCU_PMU_WAKE_L
|
||||
CFG_DISABLED, // 4 : GPIO2 -> GPIO_BTN_VOL_DOWN_L
|
||||
CFG_DISABLED, // 5 : GPIO3 -> GPIO_BTN_VOL_UP_L
|
||||
CFG_DISABLED, // 6 : GPIO4 -> NC_GPIO_MOCA_PLUG_DETECT
|
||||
CFG_OUT_0 | FAST_SLEW, // 7 : GPIO5 -> GPIO_SOC2BT_WAKE
|
||||
|
||||
/* Port 1 */
|
||||
CFG_OUT_0 | FAST_SLEW, // 8 : GPIO6 -> AP_MCU_INT_1V8
|
||||
CFG_OUT_0 | PULL_UP, // 9 : GPIO7 -> AP_TO_MCU_TCK_1V8
|
||||
CFG_IN, // 10 : GPIO8 -> LAN_PHY_INT_1V8
|
||||
CFG_DISABLED, // 11 : GPIO9 ->
|
||||
CFG_OUT_0 | FAST_SLEW, // 12 : GPIO10 -> LAN_PME_MODE_SEL_AP_1V8
|
||||
CFG_DISABLED, // 13 : GPIO11 ->
|
||||
CFG_IN, // 14 : GPIO12 -> HVR_IRQ
|
||||
CFG_IN | PULL_DOWN, // 15 : GPIO13 -> LAN_HSIC_DEVICE_READY_1V8
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // 16 : GPIO14 ->
|
||||
CFG_IN, // 17 : GPIO15 -> MOCA_IRQ_1.8V
|
||||
CFG_IN | PULL_DOWN, // 18 : GPIO16 -> GPIO_BOARD_ID_3
|
||||
CFG_IN, // 19 : GPIO17 -> GPIO_TS2SOC2PMU_INT
|
||||
CFG_IN | PULL_DOWN, // 20 : GPIO18 -> GPIO_BOOT_CONFIG_0
|
||||
CFG_OUT_0 | FAST_SLEW, // 21 : GPIO19 -> PMON_SWCLK
|
||||
CFG_IN, // 22 : GPIO20 -> PMON_MCU_TO_SOC_2V05_1
|
||||
CFG_IN | FAST_SLEW, // 23 : GPIO21 -> PMON_SWDIO
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_FUNC0 | FAST_SLEW, // 32 : UART1_TXD -> AP_UART1_TXD_1V8
|
||||
CFG_FUNC0, // 33 : UART1_RXD -> AP_UART1_RXD_1V8
|
||||
CFG_DISABLED, // 34 : UART1_RTSN -> NC_UART1_RTS_L
|
||||
CFG_DISABLED, // 35 : UART1_CTSN -> NC_UART1_RTS_L
|
||||
CFG_FUNC0 | FAST_SLEW, // 36 : UART2_TXD -> UART2_SOC_TO_PMON_R
|
||||
CFG_FUNC0, // 37 : UART2_RXD -> UART2_PMON_TO_SOC
|
||||
CFG_DISABLED, // 38 : UART2_RTSN -> NC_GPIO_UART2_RTSN
|
||||
CFG_DISABLED, // 39 : UART2_CTSN -> NC_GPIO_UART2_CTSN
|
||||
|
||||
/* Port 5 */
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 40 : UART3_TXD -> AP_UART3_TXD_1V8
|
||||
CFG_FUNC0, // 41 : UART3_RXD -> AP_UART3_RXD_1V8
|
||||
CFG_DISABLED, // 42 : UART3_RTSN -> NC_UART3_BB_RTS_L
|
||||
CFG_DISABLED, // 43 : UART3_CTSN -> NC_UART3_BB_CTS_:
|
||||
CFG_FUNC0, // 44 : UART5_RTXD -> UART5_WLAN_RXD
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0 | FAST_SLEW, // 64 : UART4_TXD -> UART4_BT_TXD
|
||||
CFG_FUNC0, // 65 : UART4_RXD -> UART4_BT_RXD
|
||||
CFG_FUNC0 | FAST_SLEW, // 66 : UART4_RTSN -> UART4_BT_RTS_L
|
||||
CFG_FUNC0, // 67 : UART4_CTSN -> UART4_BT_CTS_L
|
||||
CFG_FUNC0 | FAST_SLEW, // 68 : SPI1_SCLK -> SPI1_SOC_SCLK_1V8
|
||||
CFG_FUNC0 | FAST_SLEW, // 69 : SPI1_MOSI -> SPI1_SOC_MOSI_1V8
|
||||
CFG_FUNC0, // 70 : SPI1_MISO -> SPI1_SOC_MISO_1V8
|
||||
CFG_FUNC0 | FAST_SLEW, // 71 : SPI1_SSIN -> SPI1_SOC_CS_L_1V8
|
||||
|
||||
/* Port 9 */
|
||||
CFG_IN | PULL_DOWN, // 72 : SPI0_SCLK -> GPIO_BOARD_ID_0
|
||||
CFG_IN | PULL_DOWN, // 73 : SPI0_MOSI -> GPIO_BOARD_ID_1
|
||||
CFG_IN | PULL_DOWN, // 74 : SPI0_MISO -> GPIO_BOARD_ID_2
|
||||
CFG_DISABLED, // 75 : SPI0_SSIN -> NC_SPI0_SSIN
|
||||
CFG_DISABLED, // 76 : SPI2_SCLK -> NC_SPI2_SCLK
|
||||
CFG_DISABLED, // 77 : SPI2_MOSI -> NC_SPI2_MOSI
|
||||
CFG_DISABLED, // 78 : SPI2_MISO -> NC_SPI2_MISO
|
||||
CFG_DISABLED, // 79 : SPI2_SSIN -> NC_SPI2_CS_L
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 80 : I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 81 : I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 82 : I2C1_SDA -> I2C1_HOOVR_SDA
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 83 : I2C1_SCL -> I2C1_HOOVR_SCL
|
||||
CFG_DISABLED, // 84 : ISP0_SDA -> TP_ISP0_CAM_REAR_SDA
|
||||
CFG_DISABLED, // 85 : ISP0_SCL -> TP_ISP0_CAM_REAR_SCL
|
||||
CFG_DISABLED, // 86 : ISP1_SDA -> TP_ISP1_CAM_FRONT_SDA
|
||||
CFG_DISABLED, // 87 : ISP1_SCL -> TP_ISP1_CAM_FRONT_SCL
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // 88 : SENSOR0_RST -> NC_ISP0_CAM_REAR_CLK
|
||||
CFG_DISABLED, // 89 : SENSOR0_CLK -> NC_ISP0_CAM_REAR_SHUTDOWN
|
||||
CFG_DISABLED, // 90 : SENSOR0_XSHUTDOWN -> NC_SENSOR0_XSHUTDOWN
|
||||
CFG_DISABLED, // 91 : SENSOR0_ISTRB -> NC_SENSOR0_ISTRB
|
||||
CFG_DISABLED, // 92 : SENSOR1_RST -> NC_ISP1_CAM_FRONT_SHUTDOWN_L
|
||||
CFG_DISABLED, // 93 : SENSOR1_CLK -> NC_ISP1_CAM_FRONT_CLK
|
||||
CFG_DISABLED, // 94 : SENSOR1_XSHUTDOWN -> NC_SENSOR1_XSHUTDOWN
|
||||
CFG_DISABLED, // 95 : SENSOR1_ISTRB -> NC_SENSOR1_ISTRB
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // 96 : SPI3_MOSI -> NC_SPI3_MOSI
|
||||
CFG_DISABLED, // 97 : SPI3_MISO -> NC_SPI3_MISO
|
||||
CFG_DISABLED, // 98 : SPI3_SCLK -> NC_SPI3_SCLK
|
||||
CFG_DISABLED, // 99 : SPI3_SSIN -> NC_SPI3_CS_L
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 100 : I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 101 : I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_OUT_0 | FAST_SLEW, // 102 : GPIO22 -> GPIO_SOC2PMU_KEEPACT
|
||||
CFG_IN | PULL_UP, // 103 : GPIO23 -> GPIO_PMU2SOC_IRQ_L
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // 104 : GPIO24 -> NC_GPIO24
|
||||
CFG_IN | PULL_DOWN, // 105 : GPIO25 -> GPIO_BOOT_CONFIG_1
|
||||
CFG_IN, // 106 : GPIO26 -> GPIO_FORCE_DFU
|
||||
CFG_OUT_0 | FAST_SLEW, // 107 : GPIO27 -> MCU_DFU_STATUS_1V8
|
||||
CFG_IN | PULL_DOWN, // 108 : GPIO28 -> GPIO_BOOT_CONFIG_2
|
||||
CFG_IN | PULL_DOWN, // 109 : GPIO29 -> GPIO_BOOT_CONFIG_3
|
||||
CFG_DISABLED, // 110 : GPIO30 -> GPIO_BTN_SRL_L
|
||||
CFG_OUT_0, // 111 : GPIO31 -> SOC_TO_PMON_RESET_1V8_L
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : GPIO32 -> NC
|
||||
CFG_OUT_0, // 113 : GPIO33 -> PMON_ISP_EN_L
|
||||
CFG_IN, // 114 : GPIO34 -> SOC_TO_MCU_RESET_1V8_L
|
||||
CFG_IN | PULL_DOWN, // 115 : GPIO35 -> GPIO_BRD_REV3
|
||||
CFG_IN | PULL_DOWN, // 116 : GPIO36 -> GPIO_BRD_REV2
|
||||
CFG_IN | PULL_DOWN, // 117 : GPIO37 -> GPIO_BRD_REV1
|
||||
CFG_IN | PULL_DOWN, // 118 : GPIO38 -> GPIO_BRD_REV0
|
||||
CFG_DISABLED, // 119 : DISP_VSYNC -> NC_DISPLAY_SYNC
|
||||
|
||||
/* Port 15 */
|
||||
CFG_FUNC0, // 120 : SOCHOT0 -> SOCHOT0_L
|
||||
CFG_FUNC0 | FAST_SLEW, // 121 : SOCHOT1 -> SOCHOT1_L
|
||||
CFG_FUNC0, // 122 : UART0_TXD -> AP_UART0_TXD_1V8
|
||||
CFG_FUNC0, // 123 : UART0_RXD -> AP_UART0_RXD_1V8
|
||||
CFG_OUT_0, // 124 : DWI_DI -> SOC_TST_CPUSWITCH_OUT
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 125 : DWI_DO -> DWI_AP_DO
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 126 : DWI_CLK -> DWI_AP_CLK
|
||||
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 128 : I2S0_LRCK -> I2S0_HOOVR_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 129 : I2S0_BCLK -> I2S0_HOOVR_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 130 : I2S0_DOUT -> I2S0_HOOVR_DOUT
|
||||
CFG_DISABLED, // 131 : I2S0_DIN -> TP_I2S0_DIN
|
||||
CFG_DISABLED, // 132 : I2S1_MCK -> NC_I2S1_MCK
|
||||
CFG_DISABLED, // 133 : I2S1_LRCK -> TP_I2S1_LRCK
|
||||
CFG_DISABLED, // 134 : I2S1_BCLK -> TP_I2S1_BCLK
|
||||
CFG_DISABLED, // 135 : I2S1_DOUT -> TP_I2S1_DOUT
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // 136 : I2S1_DIN -> TP_I2S1_DIN
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 137 : I2S2_LRCK -> TP_I2S2_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 138 : I2S2_BCLK -> TP_I2S2_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 139 : I2S2_DOUT -> TP_I2S2_DOUT
|
||||
CFG_DISABLED, // 140 : I2S2_DIN -> TP_I2S2_DIN
|
||||
CFG_DISABLED, // 141 : I2S3_MCK -> TP_I2S3_MCK
|
||||
CFG_DISABLED, // 142 : I2S3_LRCK -> TP_I2S3_LRCK
|
||||
CFG_DISABLED, // 143 : I2S3_BCLK -> TP_I2S3_BCLK
|
||||
|
||||
/* Port 18 */
|
||||
CFG_FUNC0 | FAST_SLEW, // 144 : I2S3_DOUT -> I2S3_WLAN_TXD
|
||||
CFG_DISABLED, // 145 : I2S3_DIN -> TP_I2S3_DIN
|
||||
CFG_DISABLED, // 146 : I2S4_MCK -> NC_I2S4_MCK
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 147 : I2S4_LRCK -> I2S4_BT_LRCK
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 148 : I2S4_BCLK -> I2S4_BT_BCLK
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 149 : I2S4_DOUT -> I2S4_BT_DOUT
|
||||
CFG_FUNC0 | DRIVE_X2 | FAST_SLEW, // 150 : I2S4_DIN -> I2S4_BT_DIN
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // 160 : TMR32_PWM0 -> NC_TMR32_PWM0
|
||||
CFG_DISABLED, // 161 : TMR32_PWM1 -> NC_TMR32_PWM1
|
||||
CFG_DISABLED, // 162 : TMR32_PWM2 -> NC_TMR32_PWM2
|
||||
CFG_OUT_0 | FAST_SLEW, // 163 : SIO_7816UART0_SDA -> HSIC1_SOC2WLAN_HOST_RDY
|
||||
CFG_IN, // 164 : SIO_7816UART0_SCL -> HSIC1_WLAN2SOC_DEVICE_RDY
|
||||
CFG_IN, // 165 : SIO_7816UART0_RST -> HSIC1_WLAN2SOC_REMOTE_WAKE
|
||||
CFG_DISABLED, // 166 : SIO_7816UART1_SDA -> NC_SIO_SDA
|
||||
CFG_DISABLED, // 167 : SIO_7816UART1_SCL -> NC_SIO_SCL
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : SIO_7816UART1_RST -> NC_SIO_RST
|
||||
CFG_FUNC0 | FAST_SLEW, // 169 : UART6_TXD -> UART6_TS_ACC_TXD
|
||||
CFG_FUNC0, // 170 : UART6_RXD -> UART6_TS_ACC_RXD
|
||||
CFG_DISABLED, // 171 : I2C3_SDA -> NC_I2C3_SDA_1V8
|
||||
CFG_DISABLED, // 172 : I2C3_SCL -> NC_I2C3_SCL_1V8
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 24 */
|
||||
CFG_FUNC0 | FAST_SLEW, // 192 : EDP_HPD -> EDP_HPD
|
||||
CFG_FUNC0 | FAST_SLEW, // 193 : I2S0_MCK -> I2S0_HOOVR_MCK
|
||||
CFG_DISABLED, // 194 : I2S2_MCK -> TP_I2S2_MCK
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
return gpio_default_cfg;
|
||||
}
|
||||
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <target.h>
|
||||
#include <target/powerconfig.h>
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
bool
|
||||
target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
|
||||
{
|
||||
int length = 0;
|
||||
bool result = false;
|
||||
|
||||
if ((result = target_get_property_base(prop, data, maxdata, retlen)) == false) {
|
||||
switch(prop) {
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (retlen != NULL) *retlen = length;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,56 @@
|
||||
# Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2089=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_MED \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=0 \
|
||||
TARGET_SPARE0_CLK_CFG=0x81000001 \
|
||||
TARGET_VID0_CLK_CFG=0x81000000 \
|
||||
WITH_HW_HOOVER=1 \
|
||||
DISPLAY_APPLE_TV_TUNABLES=1 \
|
||||
TARGET_DITHER_TYPE=DITHER_NONE \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
AMP_SWIZZLE=2 \
|
||||
WITH_TARGET_AMC_PARAMS=1 \
|
||||
TARGET_USE_HSIC=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
TARGET_USB_DEVICE_SELF_POWERED=1 \
|
||||
TARGET_ADBE0_VBLANK_POSITION=0xF0000 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_GPU=1 \
|
||||
WITH_CPU_APSC=1 \
|
||||
BT_DTPATH=\"arm-io/uart4/bluetooth\" \
|
||||
WIFI_DTPATH=\"arm-io/usb-complex/usb-ehci0/wlan\" \
|
||||
PINTO_DTPATH=\"arm-io/usb-complex/usb-ehci0/lan1\" \
|
||||
ETHERNET_DTPATH=\"arm-io/usb-complex/usb-ehci1/lan0\" \
|
||||
WITH_TARGET_USB_CONFIG=1 \
|
||||
TARGET_DDR_784M=1
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ifeq ($(PRODUCT),iBoot)
|
||||
OPTIONS += \
|
||||
DP_DTPATH=\"arm-io/displayport\" \
|
||||
WITH_HW_DISPLAY_DISPLAYPORT=1
|
||||
endif
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
|
||||
ifneq ($(PRODUCT),LLB)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/properties.o
|
||||
endif
|
||||
Reference in new issue
Block a user