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@@ -0,0 +1,29 @@
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/*
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* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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*/
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#ifndef __TARGET_ADBE_SETTINGS_H
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#define __TARGET_ADBE_SETTINGS_H
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static struct adbe_v2_tuneable adbe_tuneables[] = {
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{
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.name = "default",
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.adbe0_vblank_pos_vbi_pulse = 0x0001,
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.adbe0_vblank_clk_gate_wakeup = 0x000e,
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.adbe0_vblank_clk_gate_idle = 0x0000,
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.adbe0_vblank_busy_finish = 2,
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.adbe0_tunable_mode_ctrl = (DBEMODECNTL_DPB_BUSY_MASK | \
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DBEMODECNTL_DYN_CLK_GATE_ENABLE | \
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DBEMODECNTL_BLK_CLK_GATE_ENABLE),
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.adbe0_aap_support = 1,
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.adbe0_aap_format_control_reg1 = (AAP_FORMAT_CONTROL_REG1_AUTOPOS | AAP_FORMAT_CONTROL_REG1_RSVD(8) | AAP_FORMAT_CONTROL_REG1_VS_POL),
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},
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};
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#endif
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@@ -0,0 +1,103 @@
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/*
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* Copyright (C) 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
|
||||
*
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||||
* This document may not be reproduced or transmitted in any form,
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||||
* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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/* Memory settings for j42d only (2 GB) */
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static const struct amc_param amc_params = {
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.lat = 0x00060300,
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.phyrdwrtim = 0x00020a04,
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.tREFi = 0x5d,
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.pdn = 0x22000403,
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.derate = 0x24831359,
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.read = 0x00000203,
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.bustat = 0x00222209,
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.bustat2 = 0x00222209,
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.pwrmngten_default = 0x00100100,
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.schen_default = 0x00001110,
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.mcphyupdate = 0x15030000,
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.mcphyupdate1 = 0x00000003,
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.arefparam = 0x0ca2b532,
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.longsr = 0x05022008,
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.mr1 = 0x44,
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.mr2 = 0x1a,
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.mr3 = 0x03,
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.addrcfg = 0x00030201,
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.mccchnldec = 0x00060010,
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.mcuchnhash = 0x0ffffd54,
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.mcschnldec = 0x00010200,
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.qbrparam = 0x00050200,
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.odts = 0x00000320,
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.addrmapmode = 0x00000601,
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.readleveling = 0x00000300,
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.freq = {
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{ // 800MHz
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.cas = 0x00000308,
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.pch = 0x00030612,
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.act = 0x12040908,
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.autoref = 0x25550000,
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.selfref = 0x00059060,
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.modereg = 0x20250782,
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},
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{ // 400MHz
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.cas = 0x00000005,
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.pch = 0x00000009,
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.act = 0x09020505,
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.autoref = 0x132b0000,
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.selfref = 0x0002d000,
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.modereg = 0x00130000,
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},
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{ // 200MHz
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.cas = 0x00000003,
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.pch = 0x00000005,
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.act = 0x05010303,
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.autoref = 0x0a160000,
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.selfref = 0x00017000,
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.modereg = 0x000a0000,
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},
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{ // 50MHz
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.cas = 0x00000002,
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.pch = 0x00000002,
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.act = 0x04010202,
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.autoref = 0x03050000,
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.selfref = 0x00006000,
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.modereg = 0x00030000,
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}
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}
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};
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static const struct amc_tunable amc_tunables[] = {
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{ &rAMC_MCSARBCFG, 0x00000001 },
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{ &rAMC_OPIDLETMR, 0x00200000 },
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{ &rAMC_OPTMRADJPARAM, 0x20400064 },
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{ &rAMC_MIFACTSCH, 0x00000001 },
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{ &rAMC_MIFCASSCH_FREQ(0), 0x10000010 },
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{ &rAMC_PSQRQCTL0, 0xff010110 },
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{ &rAMC_PSQRQCTL1, 0x00001700 },
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{ &rAMC_PSQRQTIMER0, 0x00000040 },
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{ &rAMC_PSQRQTIMER1, 0x00000014 },
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{ &rAMC_PSQRQTIMER2, 0x00000040 },
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{ &rAMC_PSQRQBRST, 0x04100410 },
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{ &rAMC_PSQRQSCHCRD, 0x00101400 },
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{ &rAMC_PSQWQCTL0, 0x00010100 },
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#if DISPLAY_D600_TUNABLES
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{ &rAMC_PSQWQCTL1, 0x00000bd4 },
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#else
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{ &rAMC_PSQWQCTL1, 0x00000158 },
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#endif
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{ &rAMC_PSQWQBRST, 0x04080410 },
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{ &rAMC_PSQWQSCHCRD, 0x00101400 },
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{ &rAMC_MCUQOSLLT, 0x0000011f },
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#if DISPLAY_D600_TUNABLES
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{ &rAMC_PWRMNGTPARAM, 0x0c003000 },
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#else
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{ &rAMC_PWRMNGTPARAM, 0x01803000 },
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#endif
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};
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ASPNANDCONFIG_H
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#define __TARGET_ASPNANDCONFIG_H
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//MLC devices
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#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
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#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_DIES_IN_PARALLEL 4
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#define ASPNAND_READ_DIES_IN_PARALLEL 4
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#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
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//TLC devices
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#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
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// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
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#define ASPNAND_INDIRECTION_MEMORY (4*1024*1024)
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#define ASPNAND_LEGACY_INDIRECTION_MEMORY ASPNAND_INDIRECTION_MEMORY
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#endif
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
|
||||
*
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||||
* This document may not be reproduced or transmitted in any form,
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||||
* in whole or in part, without the express written permission of
|
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* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* j42 specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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/* Board Revision */
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#define GPIO_BOARD_REV0 GPIO( 9, 2) // 74 : GPIO[37] -> GPIO_BRD_REV0
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#define GPIO_BOARD_REV1 GPIO( 9, 1) // 73 : GPIO[36] -> GPIO_BRD_REV1
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#define GPIO_BOARD_REV2 GPIO( 9, 0) // 72 : GPIO[35] -> GPIO_BRD_REV2
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#define GPIO_BOARD_REV3 GPIO( 8, 7) // 71 : GPIO[34] -> GPIO_BRD_REV3
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/* D2186 watchdog tickle, 'KEEPACT' */
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#define GPIO_WDOG_TICKLE GPIO( 8, 2) // 66 : GPIO[22] -> GPIO_SOC2PMU_KEEPACT
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/* which IICs to initialize */
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#define IICS_MASK (0xD) // i2c0, i2c2, i2c3
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#define TRISTAR_IIC_BUS (2)
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#define POWER_GPIO_HVR_RESET_L (5)
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#define POWER_GPIO_VBUS_PROT_2V5 (19)
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,87 @@
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD2186_ACTIVE1, 0x3f }, // <rdar://problem/18255102> J42: Enable GPU in iBoot
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{ PMU_IIC_BUS, kD2186_ACTIVE6, 0x11 }, // <rdar://problem/17940873> J42: DEV1 PMU OTP Change - Disable BUCK4_SW2 in HIB and ACT
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{ PMU_IIC_BUS, kD2186_HIBERNATE6, 0x00 }, // <rdar://problem/17940873> J42: DEV1 PMU OTP Change - Disable BUCK4_SW2 in HIB and ACT
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};
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#define PMU_LDO_COLD_SETUP_AP_DEV 1
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static const struct pmu_setup_struct pmu_ldo_cold_setup_dev[] =
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{
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup_ap[] =
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{
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// <rdar://problem/18181374> J42: PMU PreProto OTP Override [URGENT!]
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{ PMU_IIC_BUS, kD2186_ACTIVE4, 0x0f }, // (LDO9 enabled in Active)
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{ PMU_IIC_BUS, kD2186_HIBERNATE3, 0x44 }, // (LDO5 disabled in Hibernate)
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{ PMU_IIC_BUS, kD2186_HIBERNATE4, 0x03 }, // (LDO9 enabled in Hibernate)
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{ PMU_IIC_BUS, kD2186_LDO9_VSEL, 0x54 }, // (LDO9 set to 3.3V)
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{ PMU_IIC_BUS, kD2186_BUCK5_SLOT, 0x33 }, // (BUCK5 slot 3)
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{ PMU_IIC_BUS, kD2186_LDO9_SLOT, 0x33 }, // (LDO9 slot 3)
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{ PMU_IIC_BUS, kD2186_LDO10_SLOT, 0x44 }, // (LDO10 slot 4)
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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};
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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{ PMU_IIC_BUS, kD2186_GPIO3_CONF1, 0x00 }, // <rdar://problem/18585578> J42 IOKit / wlan / Match Timeout [iBoot BT_REG_ON]
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{ PMU_IIC_BUS, kD2186_GPIO4_CONF1, 0x00 }, // <rdar://problem/17960476> J42: DEV1 OTP Change - WLAN_REG_ON should be low
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{ PMU_IIC_BUS, kD2186_GPIO6_CONF1, 0x00 }, // <rdar://problem/17922907> J42: DEV1 PMU OTP Change - Assert HVR_RESET_L
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{ PMU_IIC_BUS, kD2186_GPIO7_CONF1, 0x92 }, // <rdar://problem/18036378> GPIO_BT2PMU_HOST_WAKE In, R Edge, Wake, PU
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{ PMU_IIC_BUS, kD2186_GPIO7_CONF2, 0x72 }, // <rdar://problem/18036378> GPIO_BT2PMU_HOST_WAKE PU Disabled
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{ PMU_IIC_BUS, kD2186_GPIO12_CONF1, 0x81 }, // <rdar://problem/18414083> j42: disable wake on tristar pmu gpio 12
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{ PMU_IIC_BUS, kD2186_GPIO17_CONF1, 0x93 }, // <rdar://problem/17923135> J42: DEV1 PMU OTP Change - GPIO17 Wake on Rising Edge
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{ PMU_IIC_BUS, kD2186_GPIO20_CONF1, 0xa1 }, // <rdar://problem/18388179> J42: PMU kD2186_GPIO20_CONF1 needs to be updated to 0xa1
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{ PMU_IIC_BUS, kD2186_BUCK_DWI_CTRL0, 0x07 }, // enable DWI for BUCK0, BUCK1, BUCK2
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{ PMU_IIC_BUS, kD2186_SYS_CTRL2, 0x11 }, // enable HIB_32kHz (for WIFI/BT) and DWI
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// TODO: verify
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{ PMU_IIC_BUS, kD2186_ACT_TO_HIB_DLY, 0x03 }, // set ACT_TO_HIB_DLY to 3 (6ms)
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};
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static const struct core_rails_struct soc_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2186_BUCK2_VSEL }
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};
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static const struct core_rails_struct cpu_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2186_BUCK0_VSEL }
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};
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||||
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static const struct core_rails_struct ram_rails[] =
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{
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||||
{ PMU_IIC_BUS, 0, kD2186_BUCK5_VSEL }
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};
|
||||
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#endif /* POWERCONFIG_PMU_SETUP */
|
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#define TARGET_POWER_NO_BATTERY 1
|
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#define ALWAYS_BOOT_BATTERY_VOLTAGE (3000)
|
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#define PRECHARGE_BACKLIGHT_LEVEL 103
|
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#define TARGET_MAX_USB_INPUT_CURRENT 2400
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|
||||
#define ACC_PWR_LDO (0) // <rdar://problem/17977549> J42: PMU LDO config wrong in iBoot
|
||||
|
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#endif
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define one debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (6)
|
||||
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||||
#define MCU_SERIAL_PORT (3)
|
||||
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||||
#define UART_FLOWCONTROL_MASK (0x08)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,290 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#if (APPLICATION_IBOOT && PRODUCT_IBOOT)
|
||||
#include <drivers/displayport/displayport.h>
|
||||
#include <drivers/displayport.h>
|
||||
#endif
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <drivers/iic.h>
|
||||
#include <drivers/power.h>
|
||||
#include <drivers/mcu.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <lib/syscfg.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <target.h>
|
||||
|
||||
// Board ids
|
||||
#define J42_AP_BOARD_ID (0x14)
|
||||
#define J42_DEV_BOARD_ID (0x15)
|
||||
#define J42M_AP_BOARD_ID (0x16)
|
||||
#define J42M_DEV_BOARD_ID (0x17)
|
||||
#define J42D_AP_BOARD_ID (0x34)
|
||||
#define J42D_DEV_BOARD_ID (0x35)
|
||||
|
||||
// Board revs
|
||||
#define J42_DEV1_BOARD_REV (0x7)
|
||||
#define J42_PROTO1_BOARD_REV (0x6)
|
||||
#define J42_EVT1_BOARD_REV (0x4)
|
||||
|
||||
// Do not delay iBoot by more than this amount from power on (microseconds).
|
||||
// Give up waiting for a boot logo and carry on at this point.
|
||||
#define kDPDeviceStartTimeout (10 * 1000 * 1000)
|
||||
extern utime_t gPowerOnTime;
|
||||
static bool gpio_board_rev_valid;
|
||||
static uint32_t gpio_board_rev;
|
||||
#if WITH_HW_DISPLAY_DISPLAYPORT
|
||||
static dp_t dp_link_config = {
|
||||
.mode = 1,
|
||||
.type = 0,
|
||||
.min_link_rate = 0xa,
|
||||
.max_link_rate = 0xa,
|
||||
.lanes = 4,
|
||||
.ssc = 0,
|
||||
.alpm = 0,
|
||||
.vrr_enable = 0,
|
||||
.vrr_on = 0,
|
||||
.fast_link_training = true,
|
||||
};
|
||||
#endif
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 1);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
|
||||
static uint32_t j42_get_board_rev(void)
|
||||
{
|
||||
if (!gpio_board_rev_valid) {
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV3, GPIO_PDN);
|
||||
|
||||
spin(100); // Wait 100us
|
||||
|
||||
gpio_board_rev =
|
||||
(gpio_read(GPIO_BOARD_REV3) << 3) |
|
||||
(gpio_read(GPIO_BOARD_REV2) << 2) |
|
||||
(gpio_read(GPIO_BOARD_REV1) << 1) |
|
||||
(gpio_read(GPIO_BOARD_REV0) << 0);
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_DFLT);
|
||||
|
||||
gpio_board_rev_valid = true;
|
||||
|
||||
printf("board_rev 0x%x\n", gpio_board_rev);
|
||||
|
||||
}
|
||||
|
||||
return gpio_board_rev;
|
||||
}
|
||||
|
||||
static void j42_reset_hoover(bool reset)
|
||||
{
|
||||
power_set_gpio(POWER_GPIO_HVR_RESET_L, 1, !reset);
|
||||
}
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
#if PRODUCT_LLB || PRODUCT_IBSS
|
||||
dprintf(DEBUG_INFO, "%s: chip rev: %d, fuse: %d\n", __func__,
|
||||
chipid_get_chip_revision(), chipid_get_fuse_revision());
|
||||
|
||||
// target_fixup_pmu();
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
#if 0
|
||||
if (target_config_dev() && j42_get_board_rev() > J42_DEV_BOARD_LAST) {
|
||||
platform_not_supported();
|
||||
}
|
||||
if (target_config_ap() && j42_get_board_rev() < J42_AP_BOARD_FIRST) {
|
||||
platform_not_supported();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if WITH_HW_MCU
|
||||
// Late display initialization. Needed to wait for MCU.
|
||||
mcu_init();
|
||||
#if WITH_HW_DISPLAY_DISPLAYPORT
|
||||
// Backgrounded. See dp_device_wait_started() call below.
|
||||
displayport_init(&dp_link_config);
|
||||
j42_reset_hoover(false);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
#if WITH_HW_MCU
|
||||
// radar 9746416 -- UART4 left in interrupt mode will cause kernel panic
|
||||
mcu_quiesce_uart();
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
int target_debug_init(void)
|
||||
{
|
||||
#if WITH_HW_MCU
|
||||
mcu_start_recover();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
switch (target) {
|
||||
case BOOT_DARWIN:
|
||||
case BOOT_DIAGS:
|
||||
#if WITH_HW_MCU
|
||||
#if WITH_HW_DISPLAY_DISPLAYPORT && PRODUCT_IBOOT
|
||||
/* Potentially delay boot so we have a
|
||||
* logo. We might have to do this if a
|
||||
* connected TV is particularly slow at
|
||||
* responding to EDID. Sorry. */
|
||||
dp_device_wait_started(gPowerOnTime + kDPDeviceStartTimeout);
|
||||
#endif
|
||||
mcu_start_boot();
|
||||
#endif
|
||||
break;
|
||||
case BOOT_DARWIN_RESTORE:
|
||||
break;
|
||||
default:
|
||||
// do nothing
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
// trigger recovery mode whenever USB is attached, unless
|
||||
// environment variable says otherwise.
|
||||
|
||||
// <rdar://problem/18089191> J42: USB VBUS detection should be changed from PMU to PMU GPIO
|
||||
return power_get_gpio(POWER_GPIO_VBUS_PROT_2V5) && !env_get_bool("auto-boot-usb", true);
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
// always powers on
|
||||
return true;
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
// never power off
|
||||
return false;
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
uint32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
void * target_get_display_configuration(void)
|
||||
{
|
||||
#if WITH_HW_DISPLAY_DISPLAYPORT
|
||||
return ((void *)(&dp_link_config));
|
||||
#else
|
||||
return (NULL);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
env_set("boot-device", "asp_nand", 0);
|
||||
env_set("display-color-space","RGB888", 0);
|
||||
env_set("display-timing", "720p", 0); // XXX DBJ do we need updated timing table in platform/t7000/include/platform/soc/display_timings.h for j42?
|
||||
env_set("idle-off", "false", 0); // do not idle off; there is no battery and this will just reboot (8035422)
|
||||
env_set("adbe-tunables", "default", 0);
|
||||
env_set("adfe-tunables", "default", 0);
|
||||
}
|
||||
|
||||
#endif // WITH_ENV
|
||||
|
||||
bool target_has_tristar2(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
DTNode *node;
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
// Update the pmu node with the actual vcore values
|
||||
if (FindNode(0, "arm-io/i2c0/pmu", &node)) {
|
||||
propName = "swi-vcores";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
platform_get_soc_voltages(propSize / sizeof(u_int32_t), propData);
|
||||
}
|
||||
}
|
||||
|
||||
if (FindNode(0, "arm-io/mcu0", &node)) {
|
||||
propName = "board-rev";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
((u_int32_t *)propData)[0] = j42_get_board_rev();
|
||||
}
|
||||
|
||||
// Store RBDA (Remote Bluetooth Device Address) into products node
|
||||
if (FindNode(0, "product", &node)) {
|
||||
propName = "bluetooth-dev-addr0";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (env_get("rbdaddr0")) {
|
||||
env_get_ethaddr("rbdaddr0", propData);
|
||||
} else {
|
||||
int retlen = 0;
|
||||
if (!target_get_property(TARGET_PROPERTY_BLUETOOTH_DEV_MACADDR0, propData, 6, &retlen)) {
|
||||
propName[0] = '~';
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif // WITH_DEVICETREE
|
||||
|
||||
@@ -0,0 +1,692 @@
|
||||
/*
|
||||
* Copyright (C) 2014-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: rev 2v7
|
||||
I/O Spreadsheet tracker: <rdar://problem/22973757> J42d: GPIO 178 Configuration Change
|
||||
Conversion command: ./tools/csvtopinconfig.py --soc fiji --radar '<rdar://problem/22973757> J42d: GPIO 178 Configuration Change' --copyright 2014-2015 <filename>
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
|
||||
enum {
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED_DRIVE_X4_FAST_SLEW,
|
||||
GPIOCFG_CFG_DISABLED_FAST_SLEW,
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW,
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0,
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_FAST_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_FAST_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4,
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_FUNC0_FAST_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_FAST_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_FAST_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_FAST_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_FAST_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_FAST_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_IN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW,
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_IN_PULL_UP_DRIVE_X4_SLOW_SLEW,
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW,
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW,
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW,
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW,
|
||||
GPIOCFG_CFG_OUT_1_DRIVE_X4_SLOW_SLEW,
|
||||
GPIOCFG_CFG_OUT_1_SLOW_SLEW,
|
||||
};
|
||||
|
||||
|
||||
static const uint32_t enum_map[] = {
|
||||
[GPIOCFG_CFG_DISABLED] = CFG_DISABLED,
|
||||
[GPIOCFG_CFG_DISABLED_DRIVE_X4_FAST_SLEW] = CFG_DISABLED | DRIVE_X4 | FAST_SLEW,
|
||||
[GPIOCFG_CFG_DISABLED_FAST_SLEW] = CFG_DISABLED | FAST_SLEW,
|
||||
[GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT] = CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW] = CFG_DISABLED | PULL_DOWN | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT] = CFG_DISABLED | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_DISABLED_PULL_UP_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT] = CFG_DISABLED | PULL_UP | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW] = CFG_DISABLED | PULL_UP | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW_INPUT_SCHMITT] = CFG_DISABLED | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_DISABLED_SLOW_SLEW] = CFG_DISABLED | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0] = CFG_FUNC0,
|
||||
[GPIOCFG_CFG_FUNC0_DRIVE_X2_FAST_SLEW] = CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_DRIVE_X2_FAST_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | DRIVE_X2 | FAST_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_FUNC0_DRIVE_X4] = CFG_FUNC0 | DRIVE_X4,
|
||||
[GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW] = CFG_FUNC0 | DRIVE_X4 | FAST_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | DRIVE_X4 | FAST_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW] = CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_FUNC0_FAST_SLEW] = CFG_FUNC0 | FAST_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_FAST_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | FAST_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_FAST_SLEW] = CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | FAST_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_FAST_SLEW] = CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | FAST_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW] = CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW] = CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_FAST_SLEW] = CFG_FUNC0 | PULL_UP | DRIVE_X4 | FAST_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_SLOW_SLEW] = CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_UP_FAST_SLEW] = CFG_FUNC0 | PULL_UP | FAST_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW] = CFG_FUNC0 | PULL_UP | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_FUNC0_SLOW_SLEW] = CFG_FUNC0 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_IN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT] = CFG_IN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW] = CFG_IN | PULL_DOWN | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT] = CFG_IN | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_IN_PULL_UP_DRIVE_X4_SLOW_SLEW] = CFG_IN | PULL_UP | DRIVE_X4 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW] = CFG_IN | PULL_UP | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_IN_SLOW_SLEW] = CFG_IN | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT] = CFG_IN | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW] = CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_OUT_0_SLOW_SLEW] = CFG_OUT_0 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_OUT_1_DRIVE_X4_SLOW_SLEW] = CFG_OUT_1 | DRIVE_X4 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_OUT_1_SLOW_SLEW] = CFG_OUT_1 | SLOW_SLEW,
|
||||
};
|
||||
|
||||
|
||||
static const uint8_t pinconfig_ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 0 : ULPI_DIR -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 1 : ULPI_STP -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 2 : ULPI_NXT -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 3 : ULPI_DATA[7] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 4 : ULPI_DATA[6] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 5 : ULPI_DATA[5] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 6 : ULPI_DATA[4] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 7 : ULPI_CLK -> NC
|
||||
|
||||
/* Port 1 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 8 : ULPI_DATA[3] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 9 : ULPI_DATA[2] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 10 : ULPI_DATA[1] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 11 : ULPI_DATA[0] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 12 : SPI1_SCLK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 13 : SPI1_MOSI -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 14 : SPI1_MISO -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 15 : SPI1_SSIN -> NC
|
||||
|
||||
/* Port 2 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 32 : GPIO[11] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 33 : GPIO[12] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 34 : I2S3_MCK -> NC
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 35 : I2S3_LRCK -> I2S3_SOC2BT_LRCK
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 36 : I2S3_BCLK -> I2S3_SOC2BT_BCLK
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 37 : I2S3_DOUT -> I2S3_SOC2BT_DOUT
|
||||
GPIOCFG_CFG_FUNC0, // 38 : I2S3_DIN -> I2S3_BT2SOC_DIN
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 39 : CLK32K_OUT -> NC
|
||||
|
||||
/* Port 5 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 40 : PCIE_CLKREQ0_N -> NC_PCIE0_DEBUG2SOC_CLKREQ_L
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 41 : PCIE_CLKREQ1_N -> PCIE1_WLAN2SOC_CLKREQ_L
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 42 : NAND_SYS_CLK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 43 : GPIO[0] -> NC
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT, // 44 : GPIO[1] -> MCU_PMU_WAKE_L
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 45 : GPIO[2] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 46 : GPIO[3] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 47 : GPIO[4] -> NC
|
||||
|
||||
/* Port 6 */
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 48 : GPIO[5] -> GPIO_SOC2BT_WAKE
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 49 : GPIO[6] -> AP_MCU_INT_1V8
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW, // 50 : GPIO[7] -> AP_TO_MCU_TCK_1V8
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 51 : GPIO[14] -> NC
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 52 : GPIO[16] -> GPIO_BOARD_ID_3
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW, // 53 : GPIO[17] -> NC
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 54 : GPIO[18] -> GPIO_BOOT_CONFIG_0
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT, // 55 : GPIO[20] -> PMON_TO_SOC_INT_1V8_L
|
||||
|
||||
/* Port 7 */
|
||||
GPIOCFG_CFG_DISABLED_FAST_SLEW, // 56 : GPIO[21] -> NC
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 57 : UART5_RTXD -> AP_UART5_SIL_TUNING_1V8
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 58 : UART8_TXD -> NC_AP_UART8_TXD_1V8
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 59 : UART8_RXD -> NC_AP_UART8_RXD_1V8
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 60 : SPI0_SCLK -> GPIO_BOARD_ID_0
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 61 : SPI0_MOSI -> GPIO_BOARD_ID_1
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 62 : SPI0_MISO -> GPIO_BOARD_ID_2
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 63 : SPI0_SSIN -> GPIO_SOC2WLAN_WAKE
|
||||
|
||||
/* Port 8 */
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_FAST_SLEW_INPUT_SCHMITT, // 64 : I2C2_SDA -> I2C2_DEBUG_SDA
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_FAST_SLEW_INPUT_SCHMITT, // 65 : I2C2_SCL -> I2C2_DEBUG_SCL
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 66 : GPIO[22] -> GPIO_SOC2PMU_KEEPACT
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT, // 67 : GPIO[23] -> GPIO_PMU2SOC_IRQ_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 68 : GPIO[25] -> GPIO_BOOT_CONFIG_1
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 69 : GPIO[28] -> GPIO_BOOT_CONFIG_2
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 70 : GPIO[29] -> GPIO_BOARD_ID_4
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 71 : GPIO[34] -> GPIO_BRD_REV3
|
||||
|
||||
/* Port 9 */
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 72 : GPIO[35] -> GPIO_BRD_REV2
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 73 : GPIO[36] -> GPIO_BRD_REV1
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 74 : GPIO[37] -> GPIO_BRD_REV0
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 75 : GPIO[39] -> NC_AP_TO_PCIE0_RST_1V8_L
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 76 : GPIO[42] -> NC
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT, // 77 : GPIO[43] -> PCIE1_SOC2WLAN_RESET_L
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 78 : DISP_VSYNC -> NC
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW, // 79 : UART0_TXD -> AP_UART0_MCU_BSL_TXD_1V8
|
||||
|
||||
/* Port 10 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 80 : UART0_RXD -> AP_UART0_MCU_BSL_RXD_1V8_R
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 81 : TMR32_PWM0 -> WLAN_TO_AP_TMR32_PWM0
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 82 : TMR32_PWM1 -> NC
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 83 : TMR32_PWM2 -> NC
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW, // 84 : UART6_TXD -> AP_UART6_DEBUG_TXD_1V8
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 85 : UART6_RXD -> AP_UART6_DEBUG_RXD_1V8
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 86 : I2C3_SDA -> I2C3_HOOVR_SDA
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 87 : I2C3_SCL -> I2C3_HOOVR_SCL
|
||||
|
||||
/* Port 11 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 12 */
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 96 : I2C0_SDA -> I2C0_PMU_SDA
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 97 : I2C0_SCL -> I2C0_PMU_SCL
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 98 : GPIO[38] -> AP_MCU_REQUEST_DFU_1V8
|
||||
GPIOCFG_CFG_FUNC0_FAST_SLEW, // 99 : UART2_TXD -> AP_UART2_WLAN_TXD_1V8
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 100 : UART2_RXD -> AP_UART2_WLAN_RXD_1V8
|
||||
GPIOCFG_CFG_OUT_1_SLOW_SLEW, // 101 : UART2_RTSN -> AP_UART2_WLAN_RTS_1V8_L
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 102 : UART2_CTSN -> AP_UART2_WLAN_CTS_1V8_L
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_FAST_SLEW, // 103 : DWI_DO -> DWI_AP_DO
|
||||
|
||||
/* Port 13 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_FAST_SLEW, // 104 : DWI_CLK -> DWI_AP_CLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 105 : WDOG -> WDOG_SOC2PMU_RESET_IN
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 106 : GPIO[13] -> HVR_IRQ
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 107 : GPIO[19] -> PMON_SWCLK
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT, // 108 : GPIO[26] -> MCU2SOC_FORCE_DFU_1V8
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 109 : GPIO[27] -> MCU_DFU_STATUS_1V8
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW, // 110 : SOCHOT0 -> SOCHOT0_L
|
||||
GPIOCFG_CFG_FUNC0_FAST_SLEW_INPUT_SCHMITT, // 111 : SOCHOT1 -> SOCHOT1_L
|
||||
|
||||
/* Port 14 */
|
||||
GPIOCFG_CFG_DISABLED, // 112 : UNSPECIFIED -> UNSPECIFIED
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 113 : TST_CLKOUT -> AP_TO_PMU_TEST_CLKOUT
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT, // 114 : GPIO[8] -> LAN_PHY_INT_1V8
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 115 : GPIO[9] -> GPIO9_TEST_POINT
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 116 : GPIO[10] -> SOC2LAN_PME_MODE_1V8
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 117 : GPIO[15] -> PMON_SWDIO
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_FAST_SLEW, // 118 : UART4_TXD -> AP_UART4_PMON_TXD_1V8
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 119 : UART4_RXD -> AP_UART4_PMON_RXD_1V8
|
||||
|
||||
/* Port 15 */
|
||||
GPIOCFG_CFG_DISABLED_FAST_SLEW, // 120 : UART4_RTSN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 121 : UART4_CTSN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 122 : SPI3_MOSI -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 123 : SPI3_MISO -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 124 : SPI3_SCLK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 125 : SPI3_SSIN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 126 : GPIO[24] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 127 : GPIO[30] -> NC
|
||||
|
||||
/* Port 16 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 128 : GPIO[31] -> PMON_RST_L
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 129 : GPIO[32] -> PMON_ISP_EN_L
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 130 : GPIO[33] -> SOC_TO_MCU_RESET_1V8_L
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 131 : GPIO[40] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 132 : GPIO[41] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 133 : I2S4_MCK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 134 : I2S4_LRCK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 135 : I2S4_BCLK -> NC
|
||||
|
||||
/* Port 17 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 136 : I2S4_DOUT -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 137 : I2S4_DIN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 138 : I2C1_SDA -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 139 : I2C1_SCL -> NC
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 18 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 19 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 160 : I2S0_LRCK -> I2S0_HOOVR_LRCK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 161 : I2S0_BCLK -> I2S0_HOOVR_BCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 162 : I2S0_DOUT -> I2S0_HOOVR_DOUT
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 163 : I2S0_DIN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 164 : I2S1_MCK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 165 : I2S1_LRCK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 166 : I2S1_BCLK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 167 : I2S1_DOUT -> NC
|
||||
|
||||
/* Port 21 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 168 : I2S1_DIN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 169 : I2S2_LRCK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 170 : I2S2_BCLK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 171 : I2S2_DOUT -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 172 : I2S2_DIN -> NC
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 173 : UART1_TXD -> AP_UART1_BT_TXD_1V8
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 174 : UART1_RXD -> AP_UART1_BT_RXD_1V8
|
||||
GPIOCFG_CFG_OUT_1_SLOW_SLEW, // 175 : UART1_RTSN -> AP_UART1_BT_RTS_1V8_L
|
||||
|
||||
/* Port 22 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW, // 176 : UART1_CTSN -> AP_UART1_BT_CTS_1V8_L
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 177 : EDP_HPD -> EPD_HPD_1V8
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_FAST_SLEW, // 178 : UART3_TXD -> AP_UART3_MCU_COMMS_TXD_1V8
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 179 : UART3_RXD -> AP_UART3_MCU_COMMS_RXD_1V8_R
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 180 : UART3_RTSN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 181 : UART3_CTSN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 182 : SPI2_SCLK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 183 : SPI2_MOSI -> NC
|
||||
|
||||
/* Port 23 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 184 : SPI2_MISO -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 185 : SPI2_SSIN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 186 : ISP0_SDA -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 187 : ISP0_SCL -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 188 : ISP1_SDA -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 189 : ISP1_SCL -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 190 : SENSOR0_RST -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 191 : SENSOR0_CLK -> NC
|
||||
|
||||
/* Port 24 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 192 : SENSOR0_XSHUTDOWN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 193 : SENSOR0_ISTRB -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 194 : ISP_UART0_TXD -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 195 : ISP_UART0_RXD -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 196 : SENSOR1_RST -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 197 : SENSOR1_CLK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 198 : SENSOR1_XSHUTDOWN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 199 : SENSOR1_ISTRB -> NC
|
||||
|
||||
/* Port 25 */
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW, // 200 : UART7_TXD -> NC_AP_UART7_ASTRIS_TXD_1V8
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 201 : UART7_RXD -> NC_AP_UART7_ASTRIS_RXD_1V8
|
||||
GPIOCFG_CFG_FUNC0_FAST_SLEW, // 202 : I2S0_MCK -> I2S0_HOOVR_MCK
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 203 : I2S2_MCK -> NC
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
};
|
||||
|
||||
static const uint8_t pinconfig_dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 0 : ULPI_DIR -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 1 : ULPI_STP -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 2 : ULPI_NXT -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 3 : ULPI_DATA[7] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 4 : ULPI_DATA[6] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 5 : ULPI_DATA[5] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 6 : ULPI_DATA[4] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 7 : ULPI_CLK -> NC
|
||||
|
||||
/* Port 1 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 8 : ULPI_DATA[3] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 9 : ULPI_DATA[2] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 10 : ULPI_DATA[1] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 11 : ULPI_DATA[0] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 12 : SPI1_SCLK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 13 : SPI1_MOSI -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 14 : SPI1_MISO -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 15 : SPI1_SSIN -> NC
|
||||
|
||||
/* Port 2 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 3 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 32 : GPIO[11] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 33 : GPIO[12] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 34 : I2S3_MCK -> NC
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW, // 35 : I2S3_LRCK -> I2S3_SOC2BT_LRCK
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW, // 36 : I2S3_BCLK -> I2S3_SOC2BT_BCLK
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW, // 37 : I2S3_DOUT -> I2S3_SOC2BT_DOUT
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4, // 38 : I2S3_DIN -> I2S3_BT2SOC_DIN
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 39 : CLK32K_OUT -> NC
|
||||
|
||||
/* Port 5 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 40 : PCIE_CLKREQ0_N -> NC_PCIE0_DEBUG2SOC_CLKREQ_L
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 41 : PCIE_CLKREQ1_N -> PCIE1_WLAN2SOC_CLKREQ_L
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 42 : NAND_SYS_CLK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 43 : GPIO[0] -> NC
|
||||
GPIOCFG_CFG_IN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 44 : GPIO[1] -> MCU_PMU_WAKE_L
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 45 : GPIO[2] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 46 : GPIO[3] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 47 : GPIO[4] -> NC
|
||||
|
||||
/* Port 6 */
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW, // 48 : GPIO[5] -> GPIO_SOC2BT_WAKE
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW, // 49 : GPIO[6] -> AP_MCU_INT_1V8
|
||||
GPIOCFG_CFG_IN_PULL_UP_DRIVE_X4_SLOW_SLEW, // 50 : GPIO[7] -> AP_TO_MCU_TCK_1V8
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 51 : GPIO[14] -> NC
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 52 : GPIO[16] -> GPIO_BOARD_ID_3
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW, // 53 : GPIO[17] -> NC
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 54 : GPIO[18] -> GPIO_BOOT_CONFIG_0
|
||||
GPIOCFG_CFG_IN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 55 : GPIO[20] -> PMON_TO_SOC_INT_1V8_L
|
||||
|
||||
/* Port 7 */
|
||||
GPIOCFG_CFG_DISABLED_DRIVE_X4_FAST_SLEW, // 56 : GPIO[21] -> NC
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 57 : UART5_RTXD -> AP_UART5_SIL_TUNING_1V8
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 58 : UART8_TXD -> NC_AP_UART8_TXD_1V8
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 59 : UART8_RXD -> NC_AP_UART8_RXD_1V8
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 60 : SPI0_SCLK -> GPIO_BOARD_ID_0
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 61 : SPI0_MOSI -> GPIO_BOARD_ID_1
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 62 : SPI0_MISO -> GPIO_BOARD_ID_2
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 63 : SPI0_SSIN -> GPIO_SOC2WLAN_WAKE
|
||||
|
||||
/* Port 8 */
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW_INPUT_SCHMITT, // 64 : I2C2_SDA -> I2C2_DEBUG_SDA
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW_INPUT_SCHMITT, // 65 : I2C2_SCL -> I2C2_DEBUG_SCL
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 66 : GPIO[22] -> GPIO_SOC2PMU_KEEPACT
|
||||
GPIOCFG_CFG_IN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 67 : GPIO[23] -> GPIO_PMU2SOC_IRQ_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 68 : GPIO[25] -> GPIO_BOOT_CONFIG_1
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 69 : GPIO[28] -> GPIO_BOOT_CONFIG_2
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 70 : GPIO[29] -> GPIO_BOARD_ID_4
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 71 : GPIO[34] -> GPIO_BRD_REV3
|
||||
|
||||
/* Port 9 */
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 72 : GPIO[35] -> GPIO_BRD_REV2
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 73 : GPIO[36] -> GPIO_BRD_REV1
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 74 : GPIO[37] -> GPIO_BRD_REV0
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 75 : GPIO[39] -> NC_AP_TO_PCIE0_RST_1V8_L
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 76 : GPIO[42] -> NC
|
||||
GPIOCFG_CFG_IN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 77 : GPIO[43] -> PCIE1_SOC2WLAN_RESET_L
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 78 : DISP_VSYNC -> NC
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_SLOW_SLEW, // 79 : UART0_TXD -> AP_UART0_MCU_BSL_TXD_1V8
|
||||
|
||||
/* Port 10 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 80 : UART0_RXD -> AP_UART0_MCU_BSL_RXD_1V8_R
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 81 : TMR32_PWM0 -> WLAN_TO_AP_TMR32_PWM0
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 82 : TMR32_PWM1 -> NC
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 83 : TMR32_PWM2 -> NC
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_SLOW_SLEW, // 84 : UART6_TXD -> AP_UART6_DEBUG_TXD_1V8
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 85 : UART6_RXD -> AP_UART6_DEBUG_RXD_1V8
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 86 : I2C3_SDA -> I2C3_HOOVR_SDA
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 87 : I2C3_SCL -> I2C3_HOOVR_SCL
|
||||
|
||||
/* Port 11 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 12 */
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 96 : I2C0_SDA -> I2C0_PMU_SDA
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 97 : I2C0_SCL -> I2C0_PMU_SCL
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 98 : GPIO[38] -> AP_MCU_REQUEST_DFU_1V8
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW, // 99 : UART2_TXD -> AP_UART2_WLAN_TXD_1V8
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW, // 100 : UART2_RXD -> AP_UART2_WLAN_RXD_1V8
|
||||
GPIOCFG_CFG_OUT_1_DRIVE_X4_SLOW_SLEW, // 101 : UART2_RTSN -> AP_UART2_WLAN_RTS_1V8_L
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW, // 102 : UART2_CTSN -> AP_UART2_WLAN_CTS_1V8_L
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_FAST_SLEW, // 103 : DWI_DO -> DWI_AP_DO
|
||||
|
||||
/* Port 13 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_FAST_SLEW, // 104 : DWI_CLK -> DWI_AP_CLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 105 : WDOG -> WDOG_SOC2PMU_RESET_IN
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 106 : GPIO[13] -> HVR_IRQ
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW, // 107 : GPIO[19] -> PMON_SWCLK
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT, // 108 : GPIO[26] -> MCU2SOC_FORCE_DFU_1V8
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 109 : GPIO[27] -> MCU_DFU_STATUS_1V8
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW, // 110 : SOCHOT0 -> SOCHOT0_L
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW_INPUT_SCHMITT, // 111 : SOCHOT1 -> SOCHOT1_L
|
||||
|
||||
/* Port 14 */
|
||||
GPIOCFG_CFG_DISABLED, // 112 : UNSPECIFIED -> UNSPECIFIED
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 113 : TST_CLKOUT -> AP_TO_PMU_TEST_CLKOUT
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT, // 114 : GPIO[8] -> LAN_PHY_INT_1V8
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 115 : GPIO[9] -> GPIO9_TEST_POINT
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 116 : GPIO[10] -> SOC2LAN_PME_MODE_1V8
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 117 : GPIO[15] -> PMON_SWDIO
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_FAST_SLEW, // 118 : UART4_TXD -> AP_UART4_PMON_TXD_1V8
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 119 : UART4_RXD -> AP_UART4_PMON_RXD_1V8
|
||||
|
||||
/* Port 15 */
|
||||
GPIOCFG_CFG_DISABLED_FAST_SLEW, // 120 : UART4_RTSN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 121 : UART4_CTSN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 122 : SPI3_MOSI -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 123 : SPI3_MISO -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 124 : SPI3_SCLK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 125 : SPI3_SSIN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 126 : GPIO[24] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 127 : GPIO[30] -> NC
|
||||
|
||||
/* Port 16 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 128 : GPIO[31] -> PMON_RST_L
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 129 : GPIO[32] -> PMON_ISP_EN_L
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 130 : GPIO[33] -> SOC_TO_MCU_RESET_1V8_L
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 131 : GPIO[40] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 132 : GPIO[41] -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 133 : I2S4_MCK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 134 : I2S4_LRCK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 135 : I2S4_BCLK -> NC
|
||||
|
||||
/* Port 17 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 136 : I2S4_DOUT -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 137 : I2S4_DIN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 138 : I2C1_SDA -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 139 : I2C1_SCL -> NC
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 18 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 19 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 160 : I2S0_LRCK -> I2S0_HOOVR_LRCK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 161 : I2S0_BCLK -> I2S0_HOOVR_BCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 162 : I2S0_DOUT -> I2S0_HOOVR_DOUT
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 163 : I2S0_DIN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 164 : I2S1_MCK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 165 : I2S1_LRCK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 166 : I2S1_BCLK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 167 : I2S1_DOUT -> NC
|
||||
|
||||
/* Port 21 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 168 : I2S1_DIN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 169 : I2S2_LRCK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 170 : I2S2_BCLK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 171 : I2S2_DOUT -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 172 : I2S2_DIN -> NC
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW, // 173 : UART1_TXD -> AP_UART1_BT_TXD_1V8
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 174 : UART1_RXD -> AP_UART1_BT_RXD_1V8
|
||||
GPIOCFG_CFG_OUT_1_DRIVE_X4_SLOW_SLEW, // 175 : UART1_RTSN -> AP_UART1_BT_RTS_1V8_L
|
||||
|
||||
/* Port 22 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW, // 176 : UART1_CTSN -> AP_UART1_BT_CTS_1V8_L
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW, // 177 : EDP_HPD -> EPD_HPD_1V8
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW, // 178 : UART3_TXD -> AP_UART3_MCU_COMMS_TXD_1V8
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 179 : UART3_RXD -> AP_UART3_MCU_COMMS_RXD_1V8_R
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 180 : UART3_RTSN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 181 : UART3_CTSN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 182 : SPI2_SCLK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 183 : SPI2_MOSI -> NC
|
||||
|
||||
/* Port 23 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 184 : SPI2_MISO -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 185 : SPI2_SSIN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 186 : ISP0_SDA -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 187 : ISP0_SCL -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 188 : ISP1_SDA -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 189 : ISP1_SCL -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 190 : SENSOR0_RST -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 191 : SENSOR0_CLK -> NC
|
||||
|
||||
/* Port 24 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 192 : SENSOR0_XSHUTDOWN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 193 : SENSOR0_ISTRB -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 194 : ISP_UART0_TXD -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 195 : ISP_UART0_RXD -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 196 : SENSOR1_RST -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 197 : SENSOR1_CLK -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 198 : SENSOR1_XSHUTDOWN -> NC
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 199 : SENSOR1_ISTRB -> NC
|
||||
|
||||
/* Port 25 */
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW, // 200 : UART7_TXD -> NC_AP_UART7_ASTRIS_TXD_1V8
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 201 : UART7_RXD -> NC_AP_UART7_ASTRIS_RXD_1V8
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW, // 202 : I2S0_MCK -> I2S0_HOOVR_MCK
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 203 : I2S2_MCK -> NC
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
};
|
||||
|
||||
struct pinconfig_map {
|
||||
uint32_t board_id;
|
||||
uint32_t board_id_mask;
|
||||
const uint8_t *pinconfigs[GPIOC_COUNT];
|
||||
};
|
||||
|
||||
static const struct pinconfig_map cfg_map[] = {
|
||||
{ 0, 1, { pinconfig_ap_0 } },
|
||||
{ 1, 1, { pinconfig_dev_0 } },
|
||||
};
|
||||
|
||||
static uint32_t *expanded_pinconfigs[GPIOC_COUNT];
|
||||
|
||||
static const uint32_t controller_pins[GPIOC_COUNT] = {
|
||||
GPIO_GROUP_COUNT * GPIOPADPINS,
|
||||
};
|
||||
|
||||
const uint32_t * target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
static const struct pinconfig_map *selected_map = NULL;
|
||||
|
||||
/* Cannot use malloc as chunk manager is yet to be intialized */
|
||||
static uint32_t pinconfig_buf[GPIO_GROUP_COUNT * GPIOPADPINS];
|
||||
expanded_pinconfigs[0] = pinconfig_buf;
|
||||
|
||||
ASSERT(gpioc < GPIOC_COUNT);
|
||||
|
||||
if (selected_map == NULL) {
|
||||
uint32_t board_id = platform_get_board_id();
|
||||
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
|
||||
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
|
||||
selected_map = &cfg_map[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (selected_map == NULL)
|
||||
panic("no default pinconfig for board id %u", board_id);
|
||||
|
||||
for (unsigned i = 0; i < GPIOC_COUNT; i++) {
|
||||
uint32_t num_pins = controller_pins[i];
|
||||
|
||||
for (uint32_t j = 0; j < num_pins; j++) {
|
||||
uint8_t enum_key = selected_map->pinconfigs[i][j];
|
||||
expanded_pinconfigs[i][j] = enum_map[enum_key];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return expanded_pinconfigs[gpioc];
|
||||
}
|
||||
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <target.h>
|
||||
#include <target/powerconfig.h>
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
bool
|
||||
target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
|
||||
{
|
||||
int length = 0;
|
||||
bool result = false;
|
||||
|
||||
if ((result = target_get_property_base(prop, data, maxdata, retlen)) == false) {
|
||||
switch(prop) {
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (retlen != NULL) *retlen = length;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,65 @@
|
||||
# Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2186=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_V2 \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=CHIPID_SOC_VOLTAGE_VMIN \
|
||||
TARGET_HAS_BASEBAND=$(TARGET_HAS_BASEBAND) \
|
||||
\
|
||||
TARGET_SPARE0_CLK_CFG=0x81000001 \
|
||||
TARGET_VID0_CLK_CFG=0x81100000 \
|
||||
PLL2_T=1 \
|
||||
PLL2_P=2 \
|
||||
PLL2_M=99 \
|
||||
PLL2_S=15 \
|
||||
\
|
||||
WITH_HW_HOOVER=1 \
|
||||
DISPLAY_APPLE_TV_TUNABLES=1 \
|
||||
TARGET_DITHER_TYPE=DITHER_BLUE_NOISE \
|
||||
\
|
||||
TARGET_CORE_PHY_TMR_LPCLK_CFG=0x00330087 \
|
||||
TARGET_CORE_PHY_TMR_CFG=0x256f0000 \
|
||||
TARGET_PHY_STOP_WAIT_TIME=0x28 \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_SOC=2 \
|
||||
BUCK_GPU=1 \
|
||||
BT_DTPATH=\"arm-io/uart1/bluetooth\" \
|
||||
DP_DTPATH=\"arm-io/displayport\" \
|
||||
DPPHY_DTPATH=\"arm-io/lpdp-phy\" \
|
||||
WIFI_DTPATH=\"arm-io/uart2/wlan\" \
|
||||
ETHERNET_DTPATH=\"arm-io/usb-complex/usb-ehci2/lan0\"
|
||||
|
||||
ifeq ($(SUB_TARGET),j42d)
|
||||
OPTIONS += \
|
||||
WITH_TARGET_AMC_PARAMS=1
|
||||
endif
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ifeq ($(PRODUCT),iBoot)
|
||||
OPTIONS += \
|
||||
WITH_HW_DISPLAY_DISPLAYPORT=1
|
||||
endif
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
|
||||
ifneq ($(PRODUCT),LLB)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/properties.o
|
||||
endif
|
||||
Reference in new issue
Block a user