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/*
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* Copyright (C) 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ADBE_SETTINGS_H
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#define __TARGET_ADBE_SETTINGS_H
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static struct adbe_v2_tuneable adbe_tuneables[] =
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{
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{
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.name = "D410",
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.adbe0_vblank_clk_gate_wakeup = 364,
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.adbe0_vblank_clk_gate_idle = 0x0000,
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.adbe0_vblank_busy_finish = 0x2,
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.adbe0_tunable_mode_ctrl = (DBEMODECNTL_DPB_BUSY_MASK | \
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DBEMODECNTL_PMGR_CLK_GATE_ENABLE | \
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DBEMODECNTL_DYN_CLK_GATE_ENABLE | \
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DBEMODECNTL_BLK_CLK_GATE_ENABLE),
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.adbe0_aap_support = 1,
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.adbe0_aap_format_control_reg1 = (AAP_FORMAT_CONTROL_REG1_AUTOPOS | AAP_FORMAT_CONTROL_REG1_RSVD(8) | AAP_FORMAT_CONTROL_REG1_VS_POL),
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},
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};
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#endif
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ASPNANDCONFIG_H
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#define __TARGET_ASPNANDCONFIG_H
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//MLC devices
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#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
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#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_DIES_IN_PARALLEL 4
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#define ASPNAND_READ_DIES_IN_PARALLEL 4
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#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
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//TLC devices
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#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 4
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#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 4
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#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
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// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
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#define ASPNAND_INDIRECTION_MEMORY (4*1024*1024)
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#define ASPNAND_LEGACY_INDIRECTION_MEMORY ASPNAND_INDIRECTION_MEMORY
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#endif
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@@ -0,0 +1,46 @@
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/*
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* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* iphone7,x specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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/* Board Revision */
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#define GPIO_BOARD_REV0 GPIO( 9, 2) // 74 : GPIO[34]
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#define GPIO_BOARD_REV1 GPIO( 9, 1) // 73 : GPIO[35]
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#define GPIO_BOARD_REV2 GPIO( 9, 0) // 72 : GPIO[36]
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#define GPIO_BOARD_REV3 GPIO( 8, 7) // 71 : GPIO[37]
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/* Miscellaneous Pins */
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/* Display reset */
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#define GPIO_LCD_RST GPIO( 0, 1) // 1 : ULPI_STP -> AP_TO_LCM_RESET_L
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#define GPIO_LCD_RST_POLARITY (0) // active low
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/* Ringer Switch */
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#define GPIO_RINGER_AB GPIO(16, 3) // 131 : GPIO[40] -> BUTTON_TO_AP_RINGER_A
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/* D2186 watchdog tickle, 'KEEPACT' */
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#define GPIO_WDOG_TICKLE GPIO(13, 3) // 107 : GPIO[19] -> AP_TO_PMU_KEEPACT
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/* which IICs to initialize */
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#define IICS_MASK (7)
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#define TRISTAR_IIC_BUS (0)
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#define DISPLAY_PMU_IIC_BUS (0)
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#endif /* ! __TARGET_GPIODEF_H */
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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#define CHARGER_IIC_BUS 1
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD2186_ACTIVE6, 0x17 }, // enable BUCK3_SW1, BUCK3_SW2, BUCK3_SW3, BUCK4_SW1
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{ PMU_IIC_BUS, kD2186_ACTIVE3, 0xBE }, // enable LDO4 along with LDO{1,2,3,5,7}
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{ PMU_IIC_BUS, kD2186_ACTIVE6, 0x37 }, // enable BUCK4_SW2
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{ PMU_IIC_BUS, kD2186_HIBERNATE3, 0x18 }, // enable LDO3+LDO4 in hibernate
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{ PMU_IIC_BUS, kD2186_OUT_32K, 0x49 }, // enable OUT32 clock
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{ PMU_IIC_BUS, kD2186_LDO9_VSEL, 0x39 }, // <rdar://problem/18857506> Request for N59 iBoot LDO9 voltage change
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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};
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// Settings as of <rdar://problem/14388548> N59 | IOSpreadsheet, version 0v5
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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{ PMU_IIC_BUS, kD2186_GPIO1_CONF1, 0x8a }, // CHG_TO_PMU_INT_L In, L Low, Wake, PU
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{ PMU_IIC_BUS, kD2186_GPIO1_CONF2, 0x72 }, // CHG_TO_PMU_INT_L POR
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{ PMU_IIC_BUS, kD2186_GPIO2_CONF1, 0x8a }, // BB_TO_PMU_HOST_WAKE_L In, L Low, Wake, PU
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{ PMU_IIC_BUS, kD2186_GPIO2_CONF2, 0x72 }, // BB_TO_PMU_HOST_WAKE_L POR
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{ PMU_IIC_BUS, kD2186_GPIO3_CONF1, 0x01 }, // PMU_TO_BB_RST_R_L Out 0, Low , Push-Pull
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{ PMU_IIC_BUS, kD2186_GPIO3_CONF2, 0x12 }, // PMU_TO_BB_RST_R_L VBUCK3
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{ PMU_IIC_BUS, kD2186_GPIO4_CONF1, 0x83 }, // TRISTAR_TO_AP_INT In, L High, Wake, PD
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{ PMU_IIC_BUS, kD2186_GPIO4_CONF2, 0x72 }, // TRISTAR_TO_AP_INT POR
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{ PMU_IIC_BUS, kD2186_GPIO5_CONF1, 0x83 }, // STOCKHOLM_TO_PMU_HOST_WAKE_L In, L High, Wake, PD
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{ PMU_IIC_BUS, kD2186_GPIO5_CONF2, 0x72 }, // STOCKHOLM_TO_PMU_HOST_WAKE_L POR
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{ PMU_IIC_BUS, kD2186_GPIO6_CONF1, 0x01 }, // PMU_TO_OSCAR_RESET_CLK_32K_L Out 0, Push-Pull
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{ PMU_IIC_BUS, kD2186_GPIO6_CONF2, 0x12 }, // PMU_TO_OSCAR_RESET_CLK_32K_L VBUCK3
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{ PMU_IIC_BUS, kD2186_GPIO7_CONF1, 0x83 }, // WLAN_TO_PMU_HOST_WAKE In, L High, Wake, PD
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{ PMU_IIC_BUS, kD2186_GPIO7_CONF2, 0x72 }, // WLAN_TO_PMU_HOST_WAKE POR
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{ PMU_IIC_BUS, kD2186_GPIO8_CONF1, 0xA2 }, // CODEC_TO_PMU_MIKEY_INT_L In, Any Edge, Wake, PU
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{ PMU_IIC_BUS, kD2186_GPIO8_CONF2, 0x12 }, // CODEC_TO_PMU_MIKEY_INT_L VBUCK3
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{ PMU_IIC_BUS, kD2186_GPIO9_CONF1, 0x01 }, // PMU_TO_BT_REG_ON_R Out 0, Push-Pull
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{ PMU_IIC_BUS, kD2186_GPIO9_CONF2, 0x12 }, // PMU_TO_BT_REG_ON_R VBUCK3
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{ PMU_IIC_BUS, kD2186_GPIO10_CONF1, 0x92 }, // BT_TO_PMU_HOST_WAKE In, R Edge, Wake, Push-Pull
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{ PMU_IIC_BUS, kD2186_GPIO10_CONF2, 0x72 }, // BT_TO_PMU_HOST_WAKE Disabled
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{ PMU_IIC_BUS, kD2186_GPIO11_CONF1, 0x01 }, // PMU_TO_WLAN_REG_ON_R Out 0, Push-Pull
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{ PMU_IIC_BUS, kD2186_GPIO11_CONF2, 0x12 }, // PMU_TO_WLAN_REG_ON_R VBUCK3
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{ PMU_IIC_BUS, kD2186_GPIO12_CONF1, 0x08 }, // AP_TO_I2C0_SCL Out, nReset, PU
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{ PMU_IIC_BUS, kD2186_GPIO12_CONF2, 0x72 }, // AP_TO_I2C0_SCL POR
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{ PMU_IIC_BUS, kD2186_GPIO13_CONF1, 0x83 }, // OSCAR_TO_PMU_HOST_WAKE In, In, L High, Wake, PD
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{ PMU_IIC_BUS, kD2186_GPIO13_CONF2, 0x72 }, // OSCAR_TO_PMU_HOST_WAKE POR
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{ PMU_IIC_BUS, kD2186_GPIO14_CONF1, 0x01 }, // PMU_TO_STOCKHOLM_EN Out 0, Push-Pull
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{ PMU_IIC_BUS, kD2186_GPIO14_CONF2, 0x12 }, // PMU_TO_STOCKHOLM_EN VBUCK3
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{ PMU_IIC_BUS, kD2186_GPIO15_CONF1, 0x01 }, // PMU_TO_BB_VBUS_DET Out 0, Low, Push-Pull
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{ PMU_IIC_BUS, kD2186_GPIO15_CONF2, 0x02 }, // PMU_TO_BB_VBUS_DET VCC_MAIN
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{ PMU_IIC_BUS, kD2186_GPIO16_CONF1, 0x91 }, // NC
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{ PMU_IIC_BUS, kD2186_GPIO16_CONF2, 0x72 }, // POR
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{ PMU_IIC_BUS, kD2186_GPIO17_CONF1, 0x91 }, // NC
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{ PMU_IIC_BUS, kD2186_GPIO17_CONF2, 0x72 }, // POR
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{ PMU_IIC_BUS, kD2186_GPIO18_CONF1, 0x91 }, // NC
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{ PMU_IIC_BUS, kD2186_GPIO18_CONF2, 0x72 }, // POR
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{ PMU_IIC_BUS, kD2186_GPIO19_CONF1, 0x91 }, // NC
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{ PMU_IIC_BUS, kD2186_GPIO19_CONF2, 0x72 }, // POR
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{ PMU_IIC_BUS, kD2186_GPIO20_CONF1, 0x91 }, // NC
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{ PMU_IIC_BUS, kD2186_GPIO20_CONF2, 0x72 }, // POR
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{ PMU_IIC_BUS, kD2186_GPIO21_CONF1, 0x91 }, // NC
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{ PMU_IIC_BUS, kD2186_GPIO21_CONF2, 0x72 }, // POR
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// TODO: configure debounce for WAS kD2045_GPIO_DEB2,kD2045_GPIO_DEB5,kD2045_GPIO_DEB6?
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{ PMU_IIC_BUS, kD2186_BUCK_DWI_CTRL0, 0x07 }, // enable DWI for BUCK0, BUCK1, BUCK2
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{ PMU_IIC_BUS, kD2186_SYS_CTRL2, 0x11 }, // enable HIB_32kHz (for WIFI/BT) and DWI
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{ PMU_IIC_BUS, kD2186_SYS_CTRL1, 0x24 }, // disable PROT_FET_DIS, BAT_PWR_SUSP rdar://15680815
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// TODO: verify
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{ PMU_IIC_BUS, kD2186_ACT_TO_HIB_DLY, 0x03 }, // set ACT_TO_HIB_DLY to 3 (6ms)
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};
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static const struct core_rails_struct soc_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2186_BUCK2_VSEL }
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};
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static const struct core_rails_struct cpu_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2186_BUCK0_VSEL }
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};
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static const struct core_rails_struct ram_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2186_BUCK5_VSEL }
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};
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#endif /* POWERCONFIG_PMU_SETUP */
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#define NO_BATTERY_VOLTAGE 2700
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#define MIN_BOOT_BATTERY_VOLTAGE 3600
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#define TARGET_BOOT_BATTERY_VOLTAGE 3700
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#define PRECHARGE_BACKLIGHT_LEVEL 824
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#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
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#define TARGET_POWER_NEEDS_BATTERY_PROTECTION_RESET 1
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#define ACC_PWR_LDO (6)
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#endif
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@@ -0,0 +1,23 @@
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/*
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* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_UARTCONFIG_H
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#define __TARGET_UARTCONFIG_H
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/* define one debug serial ports */
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#define DEBUG_SERIAL_PORT (0)
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#define HDQGAUGE_SERIAL_PORT (5)
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#if SUPPORT_FPGA
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#define UART_OVERSAMPLE_OVERRIDE (11)
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#endif
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#endif
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