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@@ -0,0 +1,31 @@
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/*
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* Copyright (C) 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ADBE_SETTINGS_H
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#define __TARGET_ADBE_SETTINGS_H
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static struct adbe_v2_tuneable adbe_tuneables[] =
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{
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{
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.name = "D403",
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.adbe0_vblank_pos_vbi_pulse = 0x0169,
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.adbe0_vblank_clk_gate_wakeup = 0x0007,
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.adbe0_vblank_clk_gate_idle = 0x0000,
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.adbe0_vblank_busy_finish = 0x2,
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.adbe0_tunable_mode_ctrl = (DBEMODECNTL_DPB_BUSY_MASK | \
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DBEMODECNTL_PMGR_CLK_GATE_ENABLE | \
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DBEMODECNTL_DYN_CLK_GATE_ENABLE | \
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DBEMODECNTL_BLK_CLK_GATE_ENABLE),
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.adbe0_aap_support = 1,
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.adbe0_aap_format_control_reg1 = (AAP_FORMAT_CONTROL_REG1_AUTOPOS | AAP_FORMAT_CONTROL_REG1_RSVD(9) | AAP_FORMAT_CONTROL_REG1_VS_POL),
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},
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};
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#endif
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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||||
* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ASPNANDCONFIG_H
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#define __TARGET_ASPNANDCONFIG_H
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//MLC devices
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#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
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#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_DIES_IN_PARALLEL 4
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#define ASPNAND_READ_DIES_IN_PARALLEL 4
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#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
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//TLC devices
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#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 4
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#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 4
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#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
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// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
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#define ASPNAND_INDIRECTION_MEMORY (4*1024*1024)
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#define ASPNAND_LEGACY_INDIRECTION_MEMORY ASPNAND_INDIRECTION_MEMORY
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#endif
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@@ -0,0 +1,49 @@
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/*
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* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* iphone8,x specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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/* Board Revision */
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#define GPIO_BOARD_REV0 GPIO_ID(146) // 74 : GPIO[34]
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#define GPIO_BOARD_REV1 GPIO_ID(145) // 73 : GPIO[35]
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#define GPIO_BOARD_REV2 GPIO_ID(144) // 72 : GPIO[36]
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#define GPIO_BOARD_REV3 GPIO_ID(143) // 71 : GPIO[37]
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/* Miscellaneous Pins */
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#define GPIO_DISPLAY_ID1 GPIO( 4, 0) // 32 : UART7_TXD -> DISPLAY_TO_AP_ID0 (DEV BOARD only)
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#define GPIO_DISPLAY_ID0 GPIO( 4, 1) // 33 : UART7_RXD -> DISPLAY_TO_AP_ID1 (DEV BOARD only)
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#define GPIO_PROX_SELECT GPIO( 4, 1) // 32 : UART7_RXD -> PROX_SELECT (AP BOARD only)
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/* Display reset */
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#define GPIO_LCD_RST GPIO( 9, 4) // GPIO[12] -> AP_TO_LCM_RESET_L
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#define GPIO_LCD_RST_POLARITY (0) // active low
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/* Ringer Switch */
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#define GPIO_RINGER_AB GPIO(16, 3) // 131 : GPIO[40] -> BUTTON_TO_AP_RINGER_A
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#define GPIO_S3E_BOOT_FROM_HOST GPIO_ID(141) // 141 : GPIO[32] -> AP_TO_NAND_FW_STRAP
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/* which IICs to initialize */
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#define IICS_MASK (7)
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#define TRISTAR_IIC_BUS (1)
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#define DISPLAY_PMU_IIC_BUS (0)
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#define GPIO_PMU_NAND_LOW_POWER_MODE (5) // PMU_TO_NAND_LOW_BATT_BOOT
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,144 @@
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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#define CHARGER_IIC_BUS 1
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD2255_EN_CMD0, (1<<7)|(1<<2)|(1<<1)|(1<<0) },
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{ PMU_IIC_BUS, kD2255_EN_CMD1, (1<<0) }, // buck8
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{ PMU_IIC_BUS, kD2255_SPI_CTRL, 1 }, // enable SPI access
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{ PMU_IIC_BUS, kD2255_LDO9_VSEL, 0x1E}, // LDO9 at 2.55V rdar://20437860
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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};
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// IO_CONFIG[7:6] 0=I 1=O_OD 2=O_PP 3=SS
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// IO_TYPE[5:3] O 0=L 1=32K 2=nR 3=TI 4=L
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// PUPD[2:1] O 0=NP 1=PU 2=NP 3=<0>
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// WAKE_LVL[0] O 0=low 1=high
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// IO_TYPE[5:3] I 0=L_AH 1=L_AL 2=RE 3=FE 4=AE
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// PUPD[2:1] I 0=NP 1=PU 2=PD_GND 3=<0>
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// WAKE_LVL[0] I 0=NW 1=W
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//
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// <rdar://19269873 N69 IO Spreadsheet
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// <rdar://21492643 N69 PMU GPIO: Implement IOspreadsheet 0v15
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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{ PMU_IIC_BUS, kD2255_GPIO1_CONF1, (0<<6)|(1<<3)|(0<<1)|(1<<0) }, // I.AL.NP.WS TIGRIS_TO_PMU_INT_L
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{ PMU_IIC_BUS, kD2255_GPIO1_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO2_CONF1, (0<<6)|(1<<3)|(2<<1)|(0<<0) }, // I.AL.PD.NW*, BB_TO_PMU_HOST_WAKE_L
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{ PMU_IIC_BUS, kD2255_GPIO2_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO3_CONF1, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // O_PP.L.NP.0 PMU_TO_BB_PMIC_RESET_R_L
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{ PMU_IIC_BUS, kD2255_GPIO3_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO4_CONF1, (0<<6)|(0<<3)|(2<<1)|(1<<0) }, // I.AH.PD.WS TRISTAR_TO_AP_INT
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{ PMU_IIC_BUS, kD2255_GPIO4_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO5_CONF1, (0<<6)|(0<<3)|(2<<1)|(1<<0) }, // I.AH.PD.WS STOCKHOLM_TO_PMU_HOST_WAKE
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{ PMU_IIC_BUS, kD2255_GPIO5_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO6_CONF1, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // O_PP.L.NP.0 PMU_TO_NAND_LOW_BATT_BOOT_L
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{ PMU_IIC_BUS, kD2255_GPIO6_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO7_CONF1, (0<<6)|(0<<3)|(2<<1)|(1<<0) }, // I.AH.PD.WS WLAN_TO_PMU_HOST_WAKE
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{ PMU_IIC_BUS, kD2255_GPIO7_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO8_CONF1, (0<<6)|(4<<3)|(1<<1)|(1<<0) }, // I.AE.PU.WS CODEC_TO_PMU_MIKEY_INT_L
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{ PMU_IIC_BUS, kD2255_GPIO8_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO9_CONF1, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // O_PP.L.NP.0 PMU_TO_BT_REG_ON
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{ PMU_IIC_BUS, kD2255_GPIO9_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO10_CONF1, (0<<6)|(2<<3)|(0<<1)|(1<<0) }, // I.RE.NP.WS BT_TO_PMU_HOST_WAKE
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{ PMU_IIC_BUS, kD2255_GPIO10_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO11_CONF1, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // O_PP.L.NP.0 PMU_TO_WLAN_REG_ON
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{ PMU_IIC_BUS, kD2255_GPIO11_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO12_CONF1, (1<<6)|(2<<3)|(0<<1)|(0<<0) }, // O_OD.nR.NP.0 NC
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{ PMU_IIC_BUS, kD2255_GPIO12_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO13_CONF1, (1<<6)|(0<<3)|(1<<1)|(0<<0) }, // O_OD.L.PU.0 PMU_TO_CODEC_DIGLDO_PULLDN
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{ PMU_IIC_BUS, kD2255_GPIO13_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO14_CONF1, (0<<6)|(3<<3)|(1<<1)|(0<<0) }, // I.FE.PU.NW CODEC_TO_AP_PMU_INT_L
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{ PMU_IIC_BUS, kD2255_GPIO14_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO15_CONF1, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // O_PP.L.NP.0 PMU_TO_BB_USB_VBUS_DETECT
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{ PMU_IIC_BUS, kD2255_GPIO15_CONF2, (0<<3)|(2<<0) }, // VCC_MAIN, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO16_CONF1, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // O_PP.L.NP.0 PMU_TO_STOCKHOLM_EN
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{ PMU_IIC_BUS, kD2255_GPIO16_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO17_CONF1, (0<<6)|(1<<3)|(1<<1)|(0<<0) }, // I.AL.PU.NW, WLAN_TO_PMU_PCIE_WAKE_L
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{ PMU_IIC_BUS, kD2255_GPIO17_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO18_CONF1, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // O_PP.L.NP.0 NC
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{ PMU_IIC_BUS, kD2255_GPIO18_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO19_CONF1, (2<<6)|(0<<3)|(0<<1)|(1<<0) }, // O_PP.L.NP.1 PMU_TO_LCM_PANICB use OTP-AJ..AG setting rdar://19987012
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{ PMU_IIC_BUS, kD2255_GPIO19_CONF2, (2<<3)|(2<<0) }, // VBUCK3_SW1, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO20_CONF1, (3<<6)|(2<<3)|(2<<1)|(0<<0) }, // SS.RE.PD.NW NC
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{ PMU_IIC_BUS, kD2255_GPIO20_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO21_CONF1, (1<<6)|(0<<3)|(0<<1)|(1<<0) }, // O_OD.L.NP.1 I2C0_AP_SCL
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{ PMU_IIC_BUS, kD2255_GPIO21_CONF2, (2<<3)|(2<<0) }, // VBUCK3_SW1, 10ms
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// Overrides for OTP-AI per <rdar://problem/19869417> N69m iBoot driver update
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{ PMU_IIC_BUS, kDIALOG_TEST_ACCESS, kDIALOG_TEST_ACCESS_ENA }, // enable test register access
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{ PMU_IIC_BUS, kD2255_BUCK1_ANA_TRIM10, 0x69 },
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{ PMU_IIC_BUS, kD2255_BUCK1_CLK_TRIM1, 0x01 },
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{ PMU_IIC_BUS, kD2255_BUCK1_CLK_TRIM2, 0x05 },
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{ PMU_IIC_BUS, kD2255_BUCK1_CLK_TRIM3, 0x0F },
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{ PMU_IIC_BUS, kD2255_BUCK2_MINV, 0x8 }, // <rdar://problem/21472020> Lower BUCK2_MINV
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// Set Buck5 Current
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{ PMU_IIC_BUS, kD2255_BUCK5_ANA_TRIM14, 0x36 }, // Malta ILIM at 1.80A Max Load at 1.43 rdar://19846032
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{ PMU_IIC_BUS, kD2255_PWRONOFF_OUT_32K_EN, 0x7 }, // OUT_32K active in ACTIVE, SLEEP1,2
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{ PMU_IIC_BUS, kDIALOG_TEST_ACCESS, kDIALOG_TEST_ACCESS_DIS }, // disabled test register access
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{ PMU_IIC_BUS, kD2255_PWRONOFF_LDO8_EN, 0x1}, // enable Vibrator rdar://20643930
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{ PMU_IIC_BUS, kD2255_OUT_32K, 0x49 }, // OUT_32K active, VBUCK3, PP
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};
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static const struct core_rails_struct soc_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2255_BUCK2_VSEL }
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};
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static const struct core_rails_struct cpu_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2255_BUCK0_VSEL }
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};
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// it's VDD FIXED! used for RAM inside the SOC
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static const struct core_rails_struct ram_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2255_BUCK5_VSEL }
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};
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// this is indexed with POWER_RAIL_*, I really just need to use the index in LDO[]
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target_rails_t target_rails = {
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{ 0x0F, 500, 1296, 3125 }, // POWER_RAIL_CPU, BUCK0
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{ 0x14, 600, 1396, 3125 }, // POWER_RAIL_VDD_FIXED BUCK5
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{ 0x11, 600, 1396, 3125 }, // POWER_RAIL_SOC, BUCK2
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{ 0x16, 600, 1396, 3125 }, // POWER_RAIL_CPU_RAM, BUCK7
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{ 0x17, 500, 1296, 3125 }, // POWER_RAIL_GPU, BUCK1
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{ 0x17, 600, 1396, 3125 }, // POWER_RAIL_GPU_RAM, BUCK8
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};
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#endif /* POWERCONFIG_PMU_SETUP */
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#define NO_BATTERY_VOLTAGE 2700
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#define MIN_BOOT_BATTERY_VOLTAGE 3600
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#define TARGET_BOOT_BATTERY_VOLTAGE 3700
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#define TARGET_POWER_NEEDS_BATTERY_PROTECTION_RESET 1
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#define PRECHARGE_BACKLIGHT_LEVEL 824
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#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
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#define ACC_PWR_LDO (6)
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#endif
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||||
@@ -0,0 +1,23 @@
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||||
/*
|
||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
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||||
#define __TARGET_UARTCONFIG_H
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||||
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||||
/* define one debug serial ports */
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||||
#define DEBUG_SERIAL_PORT (0)
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#define HDQGAUGE_SERIAL_PORT (5)
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||||
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||||
#if SUPPORT_FPGA
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||||
#define UART_OVERSAMPLE_OVERRIDE (11)
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||||
#endif
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||||
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||||
#endif
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||||
@@ -0,0 +1,542 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
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||||
#include <drivers/apple/gpio.h>
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||||
#include <drivers/power.h>
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||||
#include <drivers/gasgauge.h>
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||||
#include <lib/env.h>
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||||
#include <lib/mib.h>
|
||||
#include <lib/paint.h>
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||||
#include <lib/syscfg.h>
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||||
#include <platform.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/soc/chipid.h>
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||||
#include <target.h>
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||||
#include <platform/soc/hwclocks.h>
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||||
#if WITH_HW_DISPLAY_PMU
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||||
#include <drivers/display_pmu.h>
|
||||
#endif
|
||||
|
||||
#define BOARD_REV_AP_PROTO2 0x2
|
||||
|
||||
static uint32_t n69_get_board_rev(void);
|
||||
|
||||
#if WITH_HW_LM3534
|
||||
MIB_CONSTANT(kMIBTargetBacklight0I2CBus, kOIDTypeUInt32, 0);
|
||||
MIB_CONSTANT(kMIBTargetBacklight0I2CAddress, kOIDTypeUInt32, 0xC4);
|
||||
#endif
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
|
||||
static bool gpio_board_rev_valid;
|
||||
static uint32_t gpio_board_rev;
|
||||
|
||||
#if (APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC))
|
||||
#include <drivers/mipi/mipi.h>
|
||||
static mipi_t display_panel_configurations[] = {
|
||||
{
|
||||
.lanes = 2,
|
||||
.esc_div = 6,
|
||||
.pll_n = 0x3,
|
||||
.pll_m = 0x115,
|
||||
.pll_p = 0x1,
|
||||
.hsfreq = 0x29,
|
||||
.target_phy_settings = {4, {{0x44, 1, {0x52}}, {0x30, 1, {0x3F}}, {0x20, 1, {0x45}}, {0x32, 1, {0x28}}}}, //843 Mhz
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
// Read the board rev GPIOs. Note that the encoding is done
|
||||
// with active-low GPIOs, so we need to invert the values
|
||||
// we read from the GPIOs
|
||||
static uint32_t n69_get_board_rev(void)
|
||||
{
|
||||
if (!gpio_board_rev_valid) {
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV3, GPIO_PDN);
|
||||
|
||||
spin(100); // Wait 100us
|
||||
|
||||
gpio_board_rev =
|
||||
(gpio_read(GPIO_BOARD_REV3) << 3) |
|
||||
(gpio_read(GPIO_BOARD_REV2) << 2) |
|
||||
(gpio_read(GPIO_BOARD_REV1) << 1) |
|
||||
(gpio_read(GPIO_BOARD_REV0) << 0);
|
||||
|
||||
// Invert
|
||||
gpio_board_rev ^= 0xf;
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_DFLT);
|
||||
|
||||
gpio_board_rev_valid = true;
|
||||
}
|
||||
|
||||
return gpio_board_rev;
|
||||
}
|
||||
|
||||
int target_get_boot_battery_capacity(void)
|
||||
{
|
||||
int temp=0;
|
||||
#if WITH_HW_GASGAUGE
|
||||
if ( gasgauge_read_temperature(&temp) != 0 ) temp=0; // defensive
|
||||
#endif
|
||||
|
||||
const uint32_t charge_current=power_get_available_charge_current();
|
||||
if ( temp>500 && charge_current>500 ) return 0; // rely on SOC1 clear only
|
||||
|
||||
return 50; // @see rdar://16587240
|
||||
}
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
if (target_config_ap() && n69_get_board_rev() < BOARD_REV_AP_PROTO2) {
|
||||
dprintf(DEBUG_INFO, "Proto1 is deprecated\n");
|
||||
platform_not_supported();
|
||||
}
|
||||
|
||||
power_set_gpio(GPIO_PMU_NAND_LOW_POWER_MODE, 1, 1);
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
uint32_t board_rev = n69_get_board_rev();
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
|
||||
dprintf(DEBUG_INFO, "board rev 0x%x (raw 0x%x)\n", board_rev, board_rev ^ 0xf);
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return platform_get_request_dfu2() && power_has_usb();
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
#if WITH_HW_POWER
|
||||
if (power_get_boot_flag() == kPowerBootFlagColdButton) *cold_button_boot = true;
|
||||
#else
|
||||
*cold_button_boot = false;
|
||||
#endif // WITH_HW_POWER
|
||||
|
||||
return !*cold_button_boot || platform_get_request_dfu1();
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
|
||||
}
|
||||
|
||||
void * target_get_display_configuration(void)
|
||||
{
|
||||
#if (APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC))
|
||||
return ((void *)(&display_panel_configurations[0]));
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
// boot-device is set in platform's init.c
|
||||
env_set("display-color-space","RGB888", 0);
|
||||
env_set("display-timing", "D403", 0);
|
||||
env_set("adbe-tunables", "D403", 0);
|
||||
env_set("adfe-tunables", "D403", 0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if WITH_HW_CHESTNUT
|
||||
uint8_t target_get_lcm_ldos(void)
|
||||
{
|
||||
return (DISPLAY_PMU_LDO(0) | DISPLAY_PMU_LDO(1));
|
||||
}
|
||||
#endif
|
||||
|
||||
#if WITH_HW_LM3534
|
||||
uint8_t target_lm3534_gpr(uint32_t ctlr)
|
||||
{
|
||||
return ((1 << 1) | (1 << 0) | (1 << 4)); // (ramp disable) | (chip enable) | (auto mode);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
#if WITH_HW_DISPLAY_PINOT
|
||||
DTNode *disp0_node, *backlight_node;
|
||||
#endif
|
||||
DTNode *node;
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
#if WITH_HW_DISPLAY_PINOT
|
||||
// Find the DISP0 (display-subsystem 0) node
|
||||
FindNode(0, "arm-io/disp0", &disp0_node);
|
||||
|
||||
if (FindNode(0, "arm-io/mipi-dsim/lcd", &node)) {
|
||||
extern int pinot_update_device_tree(DTNode *pinot_node, DTNode *clcd_node, DTNode *backlight_node);
|
||||
|
||||
FindNode(0, "backlight", &backlight_node);
|
||||
pinot_update_device_tree(node, disp0_node, backlight_node);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if WITH_HW_MIPI_DSIM
|
||||
// Find the mipi node
|
||||
if (FindNode(0, "arm-io/mipi-dsim", &node)) {
|
||||
extern int mipi_update_device_tree(DTNode *mipi_node);
|
||||
mipi_update_device_tree(node);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Update the speaker calibration data
|
||||
if (FindNode(0, "arm-io/i2c1/audio-speaker", &node)) {
|
||||
propName = "speaker-rdc";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('SRdc', propData, propSize);
|
||||
}
|
||||
propName = "speaker-calib";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('SpCl', propData, propSize);
|
||||
}
|
||||
propName = "speaker-config";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
uint8_t vpbr;
|
||||
if (syscfgCopyDataForTag('VPBR', &vpbr, sizeof(vpbr)) == 1) {
|
||||
((uint8_t *)propData)[12] = (((uint8_t *)propData)[12] & ~0x1f) | (vpbr & 0x1f);
|
||||
}
|
||||
uint8_t vbst;
|
||||
if (syscfgCopyDataForTag('VBST', &vbst, sizeof(vbst)) == 1) {
|
||||
((uint8_t *)propData)[16] = vbst;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (FindNode(0, "arm-io/i2c1/audio-actuator", &node)) {
|
||||
propName = "actuator-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('TCal', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the codec with acoustic transducer scale data
|
||||
if (FindNode(0, "arm-io/spi1/audio-codec", &node)) {
|
||||
propName = "acoustic-trim-gains";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ATGa', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the als calibration data
|
||||
if (FindNode(0, "arm-io/i2c2/als", &node)) {
|
||||
propName = "alsCalibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LSCI', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the backlight calibration data
|
||||
if (FindNode(0, "backlight", &node)) {
|
||||
propName = "backlight-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('BLCl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the compass calibration data
|
||||
if (FindNode(0, "arm-io/aop/iop-aop-nub/compass", &node)) {
|
||||
propName = "compass-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('CPAS', propData, propSize);
|
||||
}
|
||||
propName = "compass-orientation";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('CRot', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the gyro calibration data
|
||||
if (FindNode(0, "arm-io/aop/iop-aop-nub/gyro", &node)) {
|
||||
propName = "gyro-orientation";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GRot', propData, propSize);
|
||||
}
|
||||
propName = "gyro-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GSCl', propData, propSize);
|
||||
}
|
||||
propName = "gyro-temp-table";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GYTT', propData, propSize);
|
||||
}
|
||||
propName = "gyro-interrupt-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GICl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update accelerometer calibration data
|
||||
if (FindNode(0, "arm-io/aop/iop-aop-nub/accel", &node)) {
|
||||
propName = "accel-orientation";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ARot', propData, propSize);
|
||||
}
|
||||
propName = "low-temp-accel-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LTAO', propData, propSize);
|
||||
}
|
||||
propName = "accel-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ASCl', propData, propSize);
|
||||
}
|
||||
propName = "accel-interrupt-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('AICl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update pressure sensor calibration data
|
||||
if (FindNode(0, "arm-io/aop/iop-aop-nub/pressure", &node)) {
|
||||
propName = "pressure-offset-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('SPPO', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update prox calibration data
|
||||
if (FindNode(0, "arm-io/spi2/multi-touch", &node)) {
|
||||
propName = "prox-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
syscfgCopyDataForTag('PxCl', propData, propSize);
|
||||
propName = "orb-gap-cal";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
syscfgCopyDataForTag('OrbG', propData, propSize);
|
||||
propName = "orb-accel-cal";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
syscfgCopyDataForTag('OICo', propData, propSize);
|
||||
propName = "orb-force-cal";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
syscfgCopyDataForTag('OFCl', propData, propSize);
|
||||
propName = "orb-dynamic-accel-cal";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
syscfgCopyDataForTag('FDAC', propData, propSize);
|
||||
}
|
||||
|
||||
// Stockholm calibration
|
||||
if (FindNode(0, "arm-io/uart2/stockholm", &node)) {
|
||||
propName = "calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
syscfgCopyDataForTag('NFCl', propData, propSize);
|
||||
}
|
||||
|
||||
// Update the X162 calibration data
|
||||
if (FindNode(0, "arm-io/spi3/mesa", &node)) {
|
||||
propName = "calibration-blob";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('FSCl', propData, propSize);
|
||||
}
|
||||
propName = "modulation-ratio";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('NvMR', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update cover glass type
|
||||
if (FindNode(0, "product", &node)) {
|
||||
propName = "cover-glass";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('CGSp', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update charger calibration data
|
||||
if (FindNode(0, "charger", &node)) {
|
||||
propName = "usb-input-limit-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
syscfgCopyDataForTag('CBAT', propData, propSize);
|
||||
}
|
||||
|
||||
// vibrator calibration
|
||||
if (FindNode(0, "arm-io/pwm/vibrator", &node)) {
|
||||
propName = "duty-cycle";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
uint32_t pct;
|
||||
if (syscfgCopyDataForTag('VLSg', (void *)&pct, sizeof(pct)) > 0) {
|
||||
((uint32_t *)propData)[0] = ((uint64_t)pct << 32) / 100;
|
||||
}
|
||||
}
|
||||
propName = "intensity-config";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
uint32_t pct;
|
||||
if (syscfgCopyDataForTag('VLWk', (void *)&pct, sizeof(pct)) > 0) {
|
||||
((uint32_t *)propData)[1] = ((uint64_t)pct << 32) / 100;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#if WITH_HW_DISPLAY_PMU
|
||||
display_pmu_update_device_tree("arm-io/i2c0/display-pmu");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif // WITH_DEVICETREE
|
||||
|
||||
#if WITH_PAINT
|
||||
|
||||
// The default background is expected to to be black and the artwork is expected
|
||||
// to be white. This arrangement will be inverted depending upon the cover glass
|
||||
// color of the device.
|
||||
|
||||
// Sample DClr_override values for testing devices without DClr syscfg entries (enclosure/cover glass):
|
||||
// gray/black: setenv DClr_override 00020000B9B5B4003C3B3B0000000000
|
||||
// gold/white: setenv DClr_override 00020000B5CCE100E3E4E10000000000
|
||||
// silver/white: setenv DClr_override 00020000D8D9D700E3E4E10000000000
|
||||
|
||||
static color_policy_invert_t target_cover_glass_color_table[] = {
|
||||
{ RGB( 59, 59, 60), false }, // Black - black background, white logo
|
||||
{ RGB(225, 228, 227), true }, // White - white background, black logo
|
||||
{ RGB( 18, 18, 17), false }, // Black - black background, white logo
|
||||
{ RGB(200, 202, 202), true }, // White - white background, black logo
|
||||
};
|
||||
|
||||
color_policy_t *target_color_map_init(enum colorspace cs, color_policy_t *color_policy)
|
||||
{
|
||||
// Must have a color policy structure passed in.
|
||||
if (color_policy == NULL)
|
||||
goto fail;
|
||||
|
||||
// We only support the RGB888 colorspace.
|
||||
if (cs != CS_RGB888)
|
||||
goto fail;
|
||||
|
||||
color_policy->policy_type = COLOR_MAP_POLICY_INVERT;
|
||||
color_policy->color_table = (void *)target_cover_glass_color_table;
|
||||
color_policy->color_count = ARRAY_SIZE(target_cover_glass_color_table);
|
||||
color_policy->map_color = NULL; // Use standard remapper
|
||||
|
||||
return color_policy;
|
||||
|
||||
fail:
|
||||
return NULL;
|
||||
}
|
||||
#endif // WITH_PAINT
|
||||
|
||||
#if !WITH_HW_POWER
|
||||
|
||||
bool power_needs_precharge(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
void power_cancel_buttonwait(void)
|
||||
{
|
||||
}
|
||||
|
||||
bool power_do_chargetrap(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
bool power_is_suspended(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
void power_will_resume(void)
|
||||
{
|
||||
}
|
||||
|
||||
bool power_has_usb(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
int power_read_dock_id(unsigned *id)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
bool power_get_diags_dock(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
uint32_t power_get_boot_battery_level(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int power_get_nvram(uint8_t key, uint8_t *data)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int power_set_nvram(uint8_t key, uint8_t data)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int power_set_soc_voltage(unsigned mv, int override)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
bool force_usb_power = false;
|
||||
|
||||
void power_set_usb_state(bool configured, bool suspended)
|
||||
{
|
||||
}
|
||||
|
||||
int power_backlight_enable(uint32_t backlight_level)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* ! WITH_HW_POWER */
|
||||
@@ -0,0 +1,769 @@
|
||||
/*
|
||||
* Copyright (C) YEAR Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: rev 0v21
|
||||
I/O Spreadsheet tracker: None
|
||||
Conversion command: ./tools/csvtopinconfig.py --soc maui --sheet Malta <filename>
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
|
||||
enum {
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED_DRIVE_X4_SLOW_SLEW,
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN,
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X2,
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X2_SLOW_SLEW,
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X4_SLOW_SLEW,
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_DRIVE_X4_SLOW_SLEW,
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW,
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X6_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X2_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW,
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_IN_DRIVE_X2_SLOW_SLEW,
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X2_SLOW_SLEW,
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X4_SLOW_SLEW,
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW,
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_IN_PULL_UP_DRIVE_X4_SLOW_SLEW,
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW,
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW,
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT,
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X2_SLOW_SLEW,
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW,
|
||||
GPIOCFG_CFG_OUT_0_PULL_DOWN_DRIVE_X4_SLOW_SLEW,
|
||||
GPIOCFG_CFG_OUT_0_PULL_DOWN_SLOW_SLEW,
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW,
|
||||
GPIOCFG_CFG_OUT_1_DRIVE_X4_SLOW_SLEW,
|
||||
GPIOCFG_CFG_OUT_1_SLOW_SLEW,
|
||||
};
|
||||
|
||||
|
||||
static const uint32_t enum_map[] = {
|
||||
[GPIOCFG_CFG_DISABLED] = CFG_DISABLED,
|
||||
[GPIOCFG_CFG_DISABLED_DRIVE_X4_SLOW_SLEW] = CFG_DISABLED | DRIVE_X4 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_DISABLED_PULL_DOWN] = CFG_DISABLED | PULL_DOWN,
|
||||
[GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X2] = CFG_DISABLED | PULL_DOWN | DRIVE_X2,
|
||||
[GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X2_SLOW_SLEW] = CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X4_SLOW_SLEW] = CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW] = CFG_DISABLED | PULL_DOWN | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT] = CFG_DISABLED | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_DISABLED_PULL_UP_DRIVE_X4_SLOW_SLEW] = CFG_DISABLED | PULL_UP | DRIVE_X4 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW] = CFG_DISABLED | PULL_UP | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_DISABLED_SLOW_SLEW] = CFG_DISABLED | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_DRIVE_X2_SLOW_SLEW] = CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW] = CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_FUNC0_DRIVE_X6_SLOW_SLEW] = CFG_FUNC0 | DRIVE_X6 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_SLOW_SLEW] = CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW] = CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW] = CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X2_SLOW_SLEW] = CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_SLOW_SLEW] = CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW] = CFG_FUNC0 | PULL_UP | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_FUNC0_SLOW_SLEW] = CFG_FUNC0 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_IN_DRIVE_X2_SLOW_SLEW] = CFG_IN | DRIVE_X2 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X2_SLOW_SLEW] = CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT] = CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X4_SLOW_SLEW] = CFG_IN | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW] = CFG_IN | PULL_DOWN | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT] = CFG_IN | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_IN_PULL_UP_DRIVE_X4_SLOW_SLEW] = CFG_IN | PULL_UP | DRIVE_X4 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW] = CFG_IN | PULL_UP | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW_INPUT_SCHMITT] = CFG_IN | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_IN_SLOW_SLEW] = CFG_IN | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT] = CFG_IN | SLOW_SLEW | INPUT_SCHMITT,
|
||||
[GPIOCFG_CFG_OUT_0_DRIVE_X2_SLOW_SLEW] = CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW] = CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_OUT_0_PULL_DOWN_DRIVE_X4_SLOW_SLEW] = CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_OUT_0_PULL_DOWN_SLOW_SLEW] = CFG_OUT_0 | PULL_DOWN | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_OUT_0_SLOW_SLEW] = CFG_OUT_0 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_OUT_1_DRIVE_X4_SLOW_SLEW] = CFG_OUT_1 | DRIVE_X4 | SLOW_SLEW,
|
||||
[GPIOCFG_CFG_OUT_1_SLOW_SLEW] = CFG_OUT_1 | SLOW_SLEW,
|
||||
};
|
||||
|
||||
|
||||
static const uint8_t pinconfig_ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 0 : SWD_TMS2 -> SWD_AP_BI_NAND_SWDIO
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 1 : SWD_TMS3 -> NC
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 2 : UART5_RTXD -> SWI_AP_BI_TIGRIS
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT, // 3 : I2S4_MCK -> TRISTAR_TO_AP_INT
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 4 : I2S4_BCLK -> I2S_AP_TO_CODEC_MSP_BCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 5 : I2S4_LRCK -> I2S_AP_TO_CODEC_MSP_LRCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 6 : I2S4_DIN -> I2S_CODEC_TO_AP_MSP_DIN
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 7 : I2S4_DOUT -> I2S_AP_TO_CODEC_MSP_DOUT
|
||||
|
||||
/* Port 1 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 8 : I2S2_MCK -> I2S_AP_TO_SPEAKERAMP_MCLK_R
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 9 : I2S2_BCLK -> I2S_AP_TO_CODEC_ASP_BCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 10 : I2S2_LRCK -> I2S_AP_TO_CODEC_ASP_LRCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 11 : I2S2_DIN -> I2S_CODEC_TO_AP_ASP_DIN
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 12 : I2S2_DOUT -> I2S_AP_TO_CODEC_ASP_DOUT
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 13 : SPI1_SCLK -> SPI_AP_TO_CODEC_SCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 14 : SPI1_MOSI -> SPI_CODEC_TO_AP_MOSI
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 15 : SPI1_MISO -> SPI_CODEC_TO_AP_MISO
|
||||
|
||||
/* Port 2 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW, // 16 : SPI1_SSIN -> SPI_AP_TO_CODEC_CS_L
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 17 : I2S0_MCK -> I2S_AP_TO_CODEC_MCLK_R
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 18 : I2S0_BCLK -> I2S_AP_OWL_TO_CODEC_XSP_BCLK
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 19 : I2S0_LRCK -> I2S_AP_OWL_TO_CODEC_XSP_LRCLK
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 20 : I2S0_DIN -> I2S_CODEC_TO_AP_OWL_XSP_DIN
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 21 : I2S0_DOUT -> I2S_AP_TO_CODEC_XSP_DOUT
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 22 : I2C2_SDA -> I2C2_AP_SDA
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 23 : I2C2_SCL -> I2C2_AP_SCL
|
||||
|
||||
/* Port 3 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW, // 24 : UART1_TXD -> UART_AP_TO_BT_TXD
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 25 : UART1_RXD -> UART_BT_TO_AP_RXD
|
||||
GPIOCFG_CFG_OUT_1_SLOW_SLEW, // 26 : UART1_RTS_L -> UART_AP_TO_BT_RTS_L
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 27 : UART1_CTS_L -> UART_BT_TO_AP_CTS_L
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW, // 28 : UART4_TXD -> UART_AP_TO_WLAN_TXD
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 29 : UART4_RXD -> UART_WLAN_TO_AP_RXD
|
||||
GPIOCFG_CFG_OUT_1_SLOW_SLEW, // 30 : UART4_RTS_L -> UART_AP_TO_WLAN_RTS_L
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 31 : UART4_CTS_L -> UART_WLAN_TO_AP_CTS_L
|
||||
|
||||
/* Port 4 */
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW, // 32 : UART7_TXD -> NC
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW, // 33 : UART7_RXD -> PROX_SELECT
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 34 : CLK32K_OUT -> AP_TO_TOUCH_CLK32K_RESET_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 35 : DP_WAKEUP -> NC
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 36 : MIPICSI_MUXSEL -> NC
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 37 : ISP_I2C1_SDA -> I2C_ISP_BI_FCAM_SDA
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 38 : ISP_I2C1_SCL -> I2C_ISP_TO_FCAM_SCL
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 39 : ISP_I2C0_SDA -> I2C_ISP_BI_RCAM_SDA
|
||||
|
||||
/* Port 5 */
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 40 : ISP_I2C0_SCL -> I2C_ISP_TO_RCAM_SCL
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 41 : SPI2_SCLK -> SPI_AP_TO_TOUCH_SCLK_R
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 42 : SPI2_MOSI -> SPI_AP_TO_TOUCH_MOSI
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 43 : SPI2_MISO -> SPI_TOUCH_TO_AP_MISO
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW, // 44 : SPI2_SSIN -> SPI_AP_TO_TOUCH_CS_L
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 45 : I2C0_SDA -> I2C0_AP_SDA
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 46 : I2C0_SCL -> I2C0_AP_SCL
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW, // 47 : SENSOR0_ISTRB -> NC
|
||||
|
||||
/* Port 6 */
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 48 : SENSOR0_RST -> AP_TO_RCAM_SHUTDOWN_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X2_SLOW_SLEW, // 49 : SENSOR0_CLK -> AP_TO_RCAM_CLK_R
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW, // 50 : SENSOR0_XSHUTDOWN -> AP_TO_STOCKHOLM_DWLD_REQUEST
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 51 : SENSOR1_ISTRB -> NC
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 52 : SENSOR1_RST -> AP_TO_FCAM_SHUTDOWN_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X2_SLOW_SLEW, // 53 : SENSOR1_CLK -> AP_TO_FCAM_CLK_R
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 54 : SENSOR1_XSHUTDOWN -> NC_AP_TO_MUON_BL_STROBE_EN
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 7 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 8 */
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 64 : GPIO[0] -> AP_TO_HP_HS3_CTRL
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 65 : GPIO[1] -> AP_TO_HP_HS4_CTRL
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 66 : GPIO[2] -> BUTTON_VOL_UP_L
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 67 : GPIO[3] -> BUTTON_VOL_DOWN_L
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 68 : GPIO[4] -> SPEAKERAMP_TO_AP_INT_L
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 69 : GPIO[5] -> AP_TO_SPEAKERAMP_STAYIN_ALIVE
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 70 : GPIO[6] -> AP_TO_SPEAKERAMP_RESET_L
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 71 : GPIO[7] -> AP_TO_BT_WAKE
|
||||
|
||||
/* Port 9 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 72 : GPIO[8] -> AP_TO_BB_RESET_L
|
||||
GPIOCFG_CFG_OUT_0_PULL_DOWN_SLOW_SLEW, // 73 : GPIO[9] -> PCIE_AP_TO_WLAN_DEV_WAKE
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 74 : GPIO[10] -> AP_TO_LED_DRIVER_EN
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 75 : GPIO[11] -> AP_TO_TOUCH_RESET_L
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 76 : GPIO[12] -> AP_TO_LCM_RESET_L
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 77 : GPIO[13] -> PMU_TO_AP_IRQ_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 78 : GPIO[14] -> AP_TO_BB_PCIE_DEV_WAKE
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 79 : GPIO[15] -> AP_TO_STOCKHOLM_DEV_WAKE
|
||||
|
||||
/* Port 10 */
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 80 : GPIO[16] -> BOARD_ID3
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 81 : GPIO[17] -> AP_TO_STOCKHOLM_SIM_SEL
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 82 : GPIO[18] -> BOOT_CONFIG0
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 83 : I2S1_MCK -> I2S_AP_TO_ARC_MCLK_R
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 84 : I2S1_BCLK -> I2S_AP_TO_BT_BCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 85 : I2S1_LRCK -> I2S_AP_TO_BT_LRCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 86 : I2S1_DIN -> I2S_BT_TO_AP_DIN
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 87 : I2S1_DOUT -> I2S_AP_TO_BT_DOUT
|
||||
|
||||
/* Port 11 */
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 88 : UART3_TXD -> UART_AP_TO_STOCKHOLM_TXD
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 89 : UART3_RXD -> UART_STOCKHOLM_TO_AP_RXD
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 90 : UART3_RTS_L -> UART_AP_TO_STOCKHOLM_RTS_L
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 91 : UART3_CTS_L -> UART_STOCKHOLM_TO_AP_CTS_L
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 12 */
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 96 : MENU_KEY_L -> BUTTON_MENU_KEY_L
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 97 : HOLD_KEY_L -> BUTTON_HOLD_KEY_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN, // 98 : SKEY_L -> NC
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 99 : SPI3_SCLK -> SPI_AP_TO_MESA_SCLK_R
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 100 : SPI3_MOSI -> SPI_AP_TO_MESA_MOSI
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 101 : SPI3_MISO -> SPI_MESA_TO_AP_MISO
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 102 : SPI3_SSIN -> MESA_TO_AP_INT
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 103 : SPI0_SCLK -> BOARD_ID0
|
||||
|
||||
/* Port 13 */
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 104 : SPI0_MOSI -> BOARD_ID1
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 105 : SPI0_MISO -> BOARD_ID2
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 106 : SPI0_SSIN -> USB_RLC_SWITCH_OE_L
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW, // 107 : UART0_TXD -> UART_AP_DEBUG_TXD
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 108 : UART0_RXD -> UART_AP_DEBUG_RXD
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW, // 109 : UART6_TXD -> UART_AP_TO_ACCESSORY_TXD
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 110 : UART6_RXD -> UART_ACCESSORY_TO_AP_RXD
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 111 : TMR32_PWM0 -> NC
|
||||
|
||||
/* Port 14 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 112 : TMR32_PWM1 -> NC
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 113 : TMR32_PWM2 -> NC
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 114 : I2C1_SDA -> I2C1_AP_SDA
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 115 : I2C1_SCL -> I2C1_AP_SCL
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 116 : GPIO[19] -> AP_TO_ARC_RESET_L
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW, // 117 : GPIO[20] -> LCM_TO_OWL_BSYNC
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 118 : GPIO[21] -> ARC_TO_AP_INT_L
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 119 : GPIO[22] -> BB_TO_AP_GPS_TIME_MARK
|
||||
|
||||
/* Port 15 */
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 120 : GPIO[23] -> AP_TO_ARC_STAYIN_ALIVE
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 121 : GPIO[24] -> BB_TO_AP_RESET_DETECT_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 122 : GPIO[25] -> BOOT_CONFIG1
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 123 : GPIO[26] -> FORCE_DFU
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 124 : PMGR_MOSI -> DWI_PMGR_TO_PMU_BACKLIGHT_MOSI
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 125 : PMGR_MISO -> DWI_PMU_TO_PMGR_MISO
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 126 : PMGR_SCLK0 -> DWI_PMGR_TO_PMU_SCLK
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 127 : PMGR_SSCLK1 -> DWI_PMGR_TO_BACKLIGHT_SCLK
|
||||
|
||||
/* Port 16 */
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 128 : SOCHOT0 -> PMU_TO_AP_SOCHOT0_R_L
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 129 : SOCHOT1 -> AP_TO_PMU_SOCHOT1_R_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 130 : EDP_HPD -> NC
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 131 : I2S3_MCK -> ALS_TO_AP_INT_L
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 132 : I2S3_BCLK -> I2S_AP_TO_BB_BCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 133 : I2S3_LRCK -> I2S_AP_TO_BB_LRCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 134 : I2S3_DOUT -> I2S_AP_TO_BB_DOUT
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 135 : I2S3_DIN -> I2S_BB_TO_AP_DIN
|
||||
|
||||
/* Port 17 */
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 136 : GPIO[27] -> DFU_STATUS
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 137 : GPIO[28] -> BOOT_CONFIG2
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 138 : GPIO[29] -> BOARD_ID4
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT, // 139 : GPIO[30] -> CODEC_TO_AP_PMU_INT_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 140 : GPIO[31] -> AP_TO_BB_RADIO_ON_L
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 141 : GPIO[32] -> AP_TO_NAND_FW_STRAP
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 142 : GPIO[33] -> TOUCH_TO_AP_INT_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 143 : GPIO[34] -> BOARD_REV3
|
||||
|
||||
/* Port 18 */
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 144 : GPIO[35] -> BOARD_REV2
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 145 : GPIO[36] -> BOARD_REV1
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 146 : GPIO[37] -> BOARD_REV0
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 147 : GPIO[38] -> AP_TO_BB_COREDUMP
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 148 : GPIO[39] -> BB_IPC_GPIO
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW, // 149 : GPIO[40] -> BUTTON_RINGER_A
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 150 : GPIO[41] -> AP_TO_BB_MESA_ON
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 151 : GPIO[42] -> CAM_EXT_LDO_EN
|
||||
|
||||
/* Port 19 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW, // 160 : PCIE_PERST0_L -> PCIE_AP_TO_NAND_RESET_L
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW, // 161 : PCIE_PERST1_L -> PCIE_AP_TO_WLAN_RESET_L
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW, // 162 : PCIE_PERST2_L -> PCIE_AP_TO_BB_RESET_L
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW, // 163 : PCIE_PERST3_L -> NC
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 164 : PCIE_CLKREQ0_L -> PCIE_NAND_TO_AP_CLKREQ_L
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 165 : PCIE_CLKREQ1_L -> PCIE_WLAN_TO_AP_CLKREQ_L
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 166 : PCIE_CLKREQ2_L -> PCIE_BB_BI_AP_CLKREQ_L
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 167 : PCIE_CLKREQ3_L -> NC
|
||||
|
||||
/* Port 21 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 22 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 23 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 24 */
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW, // 192 : UART2_TXD -> NC
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 193 : UART2_RXD -> NC
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW, // 194 : UART2_RTS_L -> NC
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 195 : UART2_CTS_L -> NC
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 196 : NAND_SYS_CLK -> AP_TO_NAND_SYS_CLK_R
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 197 : S3E_RESET_L -> AP_TO_NAND_RESET_L
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 198 : TST_CLKOUT -> AP_TO_PMU_TEST_CLKOUT
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
};
|
||||
|
||||
static const uint8_t pinconfig_ap_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 0 : OWL_SPI_SCLK -> SPI_OWL_TO_IMU_SCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 1 : OWL_SPI_MOSI -> SPI_OWL_TO_IMU_MOSI
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 2 : OWL_SPI_MISO -> SPI_IMU_TO_OWL_MISO
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 3 : OWL_UART1_TXD -> OWL_TO_WLAN_CONTEXT_A
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 4 : OWL_UART1_RXD -> OWL_TO_WLAN_CONTEXT_B
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 5 : OWL_UART0_TXD -> UART_OWL_TO_BB_TXD
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 6 : OWL_UART0_RXD -> UART_BB_TO_OWL_RXD
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 7 : OWL_UART2_TXD -> UART_OWL_TO_TOUCH_TXD
|
||||
|
||||
/* Port 1 */
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 8 : OWL_UART2_RXD -> TOUCH_TO_OWL_ACCEL_DATA_REQUEST
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 9 : OWL_I2CM_SDA -> TP_I2C_OWL_SDA
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 10 : OWL_I2CM_SCL -> TP_I2C_OWL_SCL
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW, // 11 : OWL_FUNC[0] -> SPI_OWL_TO_COMPASS_CS_L
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 12 : OWL_FUNC[1] -> COMPASS_TO_OWL_INT
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 13 : OWL_FUNC[2] -> OWL_FUNC2
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 14 : OWL_FUNC[3] -> ACCEL_GYRO_TO_OWL_INT1
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW, // 15 : OWL_FUNC[4] -> SPI_OWL_TO_ACCEL_GYRO_CS_L
|
||||
|
||||
/* Port 2 */
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 16 : OWL_FUNC[5] -> ACCEL_GYRO_TO_OWL_INT2
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW, // 17 : OWL_FUNC[6] -> SPI_OWL_TO_PHOSPHOROUS_CS_L
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW, // 18 : OWL_FUNC[7] -> LCM_TO_OWL_BSYNC
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 19 : OWL_FUNC[8] -> OWL_TO_PMU_SHDN_BI_TIGRIS_SWI
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 20 : OWL_FUNC[9] -> PHOSPHORUS_TO_OWL_IRQ
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 21 : OWL_SWD_TCK_OUT -> SWD_AP_PERIPHERAL_SWCLK
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 22 : OWL_SWD_TMS0 -> NC
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 23 : OWL_SWD_TMS1 -> SWD_AP_BI_BB_SWDIO
|
||||
|
||||
/* Port 3 */
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW, // 24 : OWL_I2S_MCK -> NC
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 25 : OWL_I2S_BCLK -> I2S_AP_OWL_TO_CODEC_XSP_BCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 26 : OWL_I2S_LRCK -> I2S_AP_OWL_TO_CODEC_XSP_LRCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 27 : OWL_I2S_DIN -> I2S_CODEC_TO_AP_OWL_XSP_DIN
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
};
|
||||
|
||||
static const uint8_t pinconfig_dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_SLOW_SLEW, // 0 : SWD_TMS2 -> SWD_AP_BI_NAND_SWDIO
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X2_SLOW_SLEW, // 1 : SWD_TMS3 -> NC
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_SLOW_SLEW, // 2 : UART5_RTXD -> SWI_AP_BI_TIGRIS
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT, // 3 : I2S4_MCK -> TRISTAR_TO_AP_INT
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 4 : I2S4_BCLK -> I2S_AP_TO_CODEC_MSP_BCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 5 : I2S4_LRCK -> I2S_AP_TO_CODEC_MSP_LRCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 6 : I2S4_DIN -> I2S_CODEC_TO_AP_MSP_DIN
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 7 : I2S4_DOUT -> I2S_AP_TO_CODEC_MSP_DOUT
|
||||
|
||||
/* Port 1 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 8 : I2S2_MCK -> I2S_AP_TO_SPEAKERAMP_MCLK_R
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 9 : I2S2_BCLK -> I2S_AP_TO_CODEC_ASP_BCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 10 : I2S2_LRCK -> I2S_AP_TO_CODEC_ASP_LRCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 11 : I2S2_DIN -> I2S_CODEC_TO_AP_ASP_DIN
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 12 : I2S2_DOUT -> I2S_AP_TO_CODEC_ASP_DOUT
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 13 : SPI1_SCLK -> SPI_AP_TO_CODEC_SCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW, // 14 : SPI1_MOSI -> SPI_CODEC_TO_AP_MOSI
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 15 : SPI1_MISO -> SPI_CODEC_TO_AP_MISO
|
||||
|
||||
/* Port 2 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW, // 16 : SPI1_SSIN -> SPI_AP_TO_CODEC_CS_L
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 17 : I2S0_MCK -> I2S_AP_TO_CODEC_MCLK_R
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 18 : I2S0_BCLK -> I2S_AP_OWL_TO_CODEC_XSP_BCLK
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 19 : I2S0_LRCK -> I2S_AP_OWL_TO_CODEC_XSP_LRCLK
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 20 : I2S0_DIN -> I2S_CODEC_TO_AP_OWL_XSP_DIN
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 21 : I2S0_DOUT -> I2S_AP_TO_CODEC_XSP_DOUT
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 22 : I2C2_SDA -> I2C2_AP_SDA
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 23 : I2C2_SCL -> I2C2_AP_SCL
|
||||
|
||||
/* Port 3 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_SLOW_SLEW, // 24 : UART1_TXD -> UART_AP_TO_BT_TXD
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 25 : UART1_RXD -> UART_BT_TO_AP_RXD
|
||||
GPIOCFG_CFG_OUT_1_DRIVE_X4_SLOW_SLEW, // 26 : UART1_RTS_L -> UART_AP_TO_BT_RTS_L
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 27 : UART1_CTS_L -> UART_BT_TO_AP_CTS_L
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_SLOW_SLEW, // 28 : UART4_TXD -> UART_AP_TO_WLAN_TXD
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 29 : UART4_RXD -> UART_WLAN_TO_AP_RXD
|
||||
GPIOCFG_CFG_OUT_1_DRIVE_X4_SLOW_SLEW, // 30 : UART4_RTS_L -> UART_AP_TO_WLAN_RTS_L
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 31 : UART4_CTS_L -> UART_WLAN_TO_AP_CTS_L
|
||||
|
||||
/* Port 4 */
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW, // 32 : UART7_TXD -> NC
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW, // 33 : UART7_RXD -> PROX_SELECT
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 34 : CLK32K_OUT -> AP_TO_TOUCH_CLK32K_RESET_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X2_SLOW_SLEW, // 35 : DP_WAKEUP -> NC
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X2_SLOW_SLEW, // 36 : MIPICSI_MUXSEL -> NC
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 37 : ISP_I2C1_SDA -> I2C_ISP_BI_FCAM_SDA
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_SLOW_SLEW, // 38 : ISP_I2C1_SCL -> I2C_ISP_TO_FCAM_SCL
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 39 : ISP_I2C0_SDA -> I2C_ISP_BI_RCAM_SDA
|
||||
|
||||
/* Port 5 */
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_SLOW_SLEW, // 40 : ISP_I2C0_SCL -> I2C_ISP_TO_RCAM_SCL
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 41 : SPI2_SCLK -> SPI_AP_TO_TOUCH_SCLK_R
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 42 : SPI2_MOSI -> SPI_AP_TO_TOUCH_MOSI
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 43 : SPI2_MISO -> SPI_TOUCH_TO_AP_MISO
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_SLOW_SLEW, // 44 : SPI2_SSIN -> SPI_AP_TO_TOUCH_CS_L
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 45 : I2C0_SDA -> I2C0_AP_SDA
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 46 : I2C0_SCL -> I2C0_AP_SCL
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW, // 47 : SENSOR0_ISTRB -> NC
|
||||
|
||||
/* Port 6 */
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X2_SLOW_SLEW, // 48 : SENSOR0_RST -> AP_TO_RCAM_SHUTDOWN_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 49 : SENSOR0_CLK -> AP_TO_RCAM_CLK_R
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW, // 50 : SENSOR0_XSHUTDOWN -> AP_TO_STOCKHOLM_DWLD_REQUEST
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 51 : SENSOR1_ISTRB -> NC
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X2_SLOW_SLEW, // 52 : SENSOR1_RST -> AP_TO_FCAM_SHUTDOWN_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 53 : SENSOR1_CLK -> AP_TO_FCAM_CLK_R
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 54 : SENSOR1_XSHUTDOWN -> NC_AP_TO_MUON_BL_STROBE_EN
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 7 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 8 */
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 64 : GPIO[0] -> AP_TO_HP_HS3_CTRL
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 65 : GPIO[1] -> AP_TO_HP_HS4_CTRL
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 66 : GPIO[2] -> BUTTON_VOL_UP_L
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 67 : GPIO[3] -> BUTTON_VOL_DOWN_L
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 68 : GPIO[4] -> SPEAKERAMP_TO_AP_INT_L
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW, // 69 : GPIO[5] -> AP_TO_SPEAKERAMP_STAYIN_ALIVE
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW, // 70 : GPIO[6] -> AP_TO_SPEAKERAMP_RESET_L
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW, // 71 : GPIO[7] -> AP_TO_BT_WAKE
|
||||
|
||||
/* Port 9 */
|
||||
GPIOCFG_CFG_DISABLED_SLOW_SLEW, // 72 : GPIO[8] -> AP_TO_BB_RESET_L
|
||||
GPIOCFG_CFG_OUT_0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 73 : GPIO[9] -> PCIE_AP_TO_WLAN_DEV_WAKE
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW, // 74 : GPIO[10] -> AP_TO_LED_DRIVER_EN
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW, // 75 : GPIO[11] -> AP_TO_TOUCH_RESET_L
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW, // 76 : GPIO[12] -> AP_TO_LCM_RESET_L
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 77 : GPIO[13] -> PMU_TO_AP_IRQ_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 78 : GPIO[14] -> AP_TO_BB_PCIE_DEV_WAKE
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 79 : GPIO[15] -> AP_TO_STOCKHOLM_DEV_WAKE
|
||||
|
||||
/* Port 10 */
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 80 : GPIO[16] -> BOARD_ID3
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 81 : GPIO[17] -> AP_TO_STOCKHOLM_SIM_SEL
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 82 : GPIO[18] -> BOOT_CONFIG0
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X2_SLOW_SLEW, // 83 : I2S1_MCK -> I2S_AP_TO_ARC_MCLK_R
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 84 : I2S1_BCLK -> I2S_AP_TO_BT_BCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 85 : I2S1_LRCK -> I2S_AP_TO_BT_LRCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 86 : I2S1_DIN -> I2S_BT_TO_AP_DIN
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 87 : I2S1_DOUT -> I2S_AP_TO_BT_DOUT
|
||||
|
||||
/* Port 11 */
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 88 : UART3_TXD -> UART_AP_TO_STOCKHOLM_TXD
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 89 : UART3_RXD -> UART_STOCKHOLM_TO_AP_RXD
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 90 : UART3_RTS_L -> UART_AP_TO_STOCKHOLM_RTS_L
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 91 : UART3_CTS_L -> UART_STOCKHOLM_TO_AP_CTS_L
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 12 */
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 96 : MENU_KEY_L -> BUTTON_MENU_KEY_L
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW, // 97 : HOLD_KEY_L -> BUTTON_HOLD_KEY_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X2, // 98 : SKEY_L -> NC
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 99 : SPI3_SCLK -> SPI_AP_TO_MESA_SCLK_R
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 100 : SPI3_MOSI -> SPI_AP_TO_MESA_MOSI
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 101 : SPI3_MISO -> SPI_MESA_TO_AP_MISO
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 102 : SPI3_SSIN -> MESA_TO_AP_INT
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 103 : SPI0_SCLK -> BOARD_ID0
|
||||
|
||||
/* Port 13 */
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 104 : SPI0_MOSI -> BOARD_ID1
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 105 : SPI0_MISO -> BOARD_ID2
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 106 : SPI0_SSIN -> USB_RLC_SWITCH_OE_L
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_SLOW_SLEW, // 107 : UART0_TXD -> UART_AP_DEBUG_TXD
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 108 : UART0_RXD -> UART_AP_DEBUG_RXD
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_SLOW_SLEW, // 109 : UART6_TXD -> UART_AP_TO_ACCESSORY_TXD
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 110 : UART6_RXD -> UART_ACCESSORY_TO_AP_RXD
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW, // 111 : TMR32_PWM0 -> NC
|
||||
|
||||
/* Port 14 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 112 : TMR32_PWM1 -> NC
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 113 : TMR32_PWM2 -> NC
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 114 : I2C1_SDA -> I2C1_AP_SDA
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 115 : I2C1_SCL -> I2C1_AP_SCL
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 116 : GPIO[19] -> AP_TO_ARC_RESET_L
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW, // 117 : GPIO[20] -> LCM_TO_OWL_BSYNC
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 118 : GPIO[21] -> ARC_TO_AP_INT_L
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 119 : GPIO[22] -> BB_TO_AP_GPS_TIME_MARK
|
||||
|
||||
/* Port 15 */
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 120 : GPIO[23] -> AP_TO_ARC_STAYIN_ALIVE
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 121 : GPIO[24] -> BB_TO_AP_RESET_DETECT_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 122 : GPIO[25] -> BOOT_CONFIG1
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW, // 123 : GPIO[26] -> FORCE_DFU
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW, // 124 : PMGR_MOSI -> DWI_PMGR_TO_PMU_BACKLIGHT_MOSI
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 125 : PMGR_MISO -> DWI_PMU_TO_PMGR_MISO
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW, // 126 : PMGR_SCLK0 -> DWI_PMGR_TO_PMU_SCLK
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW, // 127 : PMGR_SSCLK1 -> DWI_PMGR_TO_BACKLIGHT_SCLK
|
||||
|
||||
/* Port 16 */
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 128 : SOCHOT0 -> PMU_TO_AP_SOCHOT0_R_L
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW, // 129 : SOCHOT1 -> AP_TO_PMU_SOCHOT1_R_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 130 : EDP_HPD -> NC
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 131 : I2S3_MCK -> ALS_TO_AP_INT_L
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 132 : I2S3_BCLK -> I2S_AP_TO_BB_BCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 133 : I2S3_LRCK -> I2S_AP_TO_BB_LRCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 134 : I2S3_DOUT -> I2S_AP_TO_BB_DOUT
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT, // 135 : I2S3_DIN -> I2S_BB_TO_AP_DIN
|
||||
|
||||
/* Port 17 */
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 136 : GPIO[27] -> DFU_STATUS
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 137 : GPIO[28] -> BOOT_CONFIG2
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 138 : GPIO[29] -> BOARD_ID4
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT, // 139 : GPIO[30] -> CODEC_TO_AP_PMU_INT_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_DRIVE_X4_SLOW_SLEW, // 140 : GPIO[31] -> AP_TO_BB_RADIO_ON_L
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW, // 141 : GPIO[32] -> AP_TO_NAND_FW_STRAP
|
||||
GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW_INPUT_SCHMITT, // 142 : GPIO[33] -> TOUCH_TO_AP_INT_L
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 143 : GPIO[34] -> BOARD_REV3
|
||||
|
||||
/* Port 18 */
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 144 : GPIO[35] -> BOARD_REV2
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 145 : GPIO[36] -> BOARD_REV1
|
||||
GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW, // 146 : GPIO[37] -> BOARD_REV0
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 147 : GPIO[38] -> AP_TO_BB_COREDUMP
|
||||
GPIOCFG_CFG_DISABLED_DRIVE_X4_SLOW_SLEW, // 148 : GPIO[39] -> BB_IPC_GPIO
|
||||
GPIOCFG_CFG_IN_SLOW_SLEW, // 149 : GPIO[40] -> BUTTON_RINGER_A
|
||||
GPIOCFG_CFG_DISABLED_DRIVE_X4_SLOW_SLEW, // 150 : GPIO[41] -> AP_TO_BB_MESA_ON
|
||||
GPIOCFG_CFG_OUT_0_SLOW_SLEW, // 151 : GPIO[42] -> CAM_EXT_LDO_EN
|
||||
|
||||
/* Port 19 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
GPIOCFG_CFG_IN_DRIVE_X2_SLOW_SLEW, // 160 : PCIE_PERST0_L -> PCIE_AP_TO_NAND_RESET_L
|
||||
GPIOCFG_CFG_IN_DRIVE_X2_SLOW_SLEW, // 161 : PCIE_PERST1_L -> PCIE_AP_TO_WLAN_RESET_L
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X2_SLOW_SLEW, // 162 : PCIE_PERST2_L -> PCIE_AP_TO_BB_RESET_L
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X2_SLOW_SLEW, // 163 : PCIE_PERST3_L -> NC
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 164 : PCIE_CLKREQ0_L -> PCIE_NAND_TO_AP_CLKREQ_L
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 165 : PCIE_CLKREQ1_L -> PCIE_WLAN_TO_AP_CLKREQ_L
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 166 : PCIE_CLKREQ2_L -> PCIE_BB_BI_AP_CLKREQ_L
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 167 : PCIE_CLKREQ3_L -> NC
|
||||
|
||||
/* Port 21 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 22 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 23 */
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
|
||||
/* Port 24 */
|
||||
GPIOCFG_CFG_IN_PULL_UP_DRIVE_X4_SLOW_SLEW, // 192 : UART2_TXD -> NC
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 193 : UART2_RXD -> NC
|
||||
GPIOCFG_CFG_IN_PULL_UP_DRIVE_X4_SLOW_SLEW, // 194 : UART2_RTS_L -> NC
|
||||
GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT, // 195 : UART2_CTS_L -> NC
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X6_SLOW_SLEW, // 196 : NAND_SYS_CLK -> AP_TO_NAND_SYS_CLK_R
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_SLOW_SLEW, // 197 : S3E_RESET_L -> AP_TO_NAND_RESET_L
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_SLOW_SLEW, // 198 : TST_CLKOUT -> AP_TO_PMU_TEST_CLKOUT
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
};
|
||||
|
||||
static const uint8_t pinconfig_dev_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_SLOW_SLEW, // 0 : OWL_SPI_SCLK -> SPI_OWL_TO_IMU_SCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_SLOW_SLEW, // 1 : OWL_SPI_MOSI -> SPI_OWL_TO_IMU_MOSI
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 2 : OWL_SPI_MISO -> SPI_IMU_TO_OWL_MISO
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X2_SLOW_SLEW, // 3 : OWL_UART1_TXD -> OWL_TO_WLAN_CONTEXT_A
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X2_SLOW_SLEW, // 4 : OWL_UART1_RXD -> OWL_TO_WLAN_CONTEXT_B
|
||||
GPIOCFG_CFG_OUT_0_DRIVE_X2_SLOW_SLEW, // 5 : OWL_UART0_TXD -> UART_OWL_TO_BB_TXD
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 6 : OWL_UART0_RXD -> UART_BB_TO_OWL_RXD
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_SLOW_SLEW, // 7 : OWL_UART2_TXD -> UART_OWL_TO_TOUCH_TXD
|
||||
|
||||
/* Port 1 */
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 8 : OWL_UART2_RXD -> TOUCH_TO_OWL_ACCEL_DATA_REQUEST
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 9 : OWL_I2CM_SDA -> TP_I2C_OWL_SDA
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_SLOW_SLEW, // 10 : OWL_I2CM_SCL -> TP_I2C_OWL_SCL
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X2_SLOW_SLEW, // 11 : OWL_FUNC[0] -> SPI_OWL_TO_COMPASS_CS_L
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 12 : OWL_FUNC[1] -> COMPASS_TO_OWL_INT
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 13 : OWL_FUNC[2] -> OWL_FUNC2
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 14 : OWL_FUNC[3] -> ACCEL_GYRO_TO_OWL_INT1
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X2_SLOW_SLEW, // 15 : OWL_FUNC[4] -> SPI_OWL_TO_ACCEL_GYRO_CS_L
|
||||
|
||||
/* Port 2 */
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 16 : OWL_FUNC[5] -> ACCEL_GYRO_TO_OWL_INT2
|
||||
GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X2_SLOW_SLEW, // 17 : OWL_FUNC[6] -> SPI_OWL_TO_PHOSPHOROUS_CS_L
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X2_SLOW_SLEW, // 18 : OWL_FUNC[7] -> LCM_TO_OWL_BSYNC
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X2_SLOW_SLEW, // 19 : OWL_FUNC[8] -> OWL_TO_PMU_SHDN_BI_TIGRIS_SWI
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 20 : OWL_FUNC[9] -> PHOSPHORUS_TO_OWL_IRQ
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_SLOW_SLEW, // 21 : OWL_SWD_TCK_OUT -> SWD_AP_PERIPHERAL_SWCLK
|
||||
GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X2_SLOW_SLEW, // 22 : OWL_SWD_TMS0 -> NC
|
||||
GPIOCFG_CFG_FUNC0_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 23 : OWL_SWD_TMS1 -> SWD_AP_BI_BB_SWDIO
|
||||
|
||||
/* Port 3 */
|
||||
GPIOCFG_CFG_IN_PULL_DOWN_DRIVE_X4_SLOW_SLEW, // 24 : OWL_I2S_MCK -> NC
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 25 : OWL_I2S_BCLK -> I2S_AP_OWL_TO_CODEC_XSP_BCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT, // 26 : OWL_I2S_LRCK -> I2S_AP_OWL_TO_CODEC_XSP_LRCLK
|
||||
GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_SLOW_SLEW_INPUT_SCHMITT, // 27 : OWL_I2S_DIN -> I2S_CODEC_TO_AP_OWL_XSP_DIN
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
GPIOCFG_CFG_DISABLED,
|
||||
};
|
||||
|
||||
struct pinconfig_map {
|
||||
uint32_t board_id;
|
||||
uint32_t board_id_mask;
|
||||
const uint8_t *pinconfigs[GPIOC_COUNT];
|
||||
};
|
||||
|
||||
static const struct pinconfig_map cfg_map[] = {
|
||||
{ 0, 1, { pinconfig_ap_0, pinconfig_ap_1 } },
|
||||
{ 1, 1, { pinconfig_dev_0, pinconfig_dev_1 } },
|
||||
};
|
||||
|
||||
static uint32_t *expanded_pinconfigs[GPIOC_COUNT];
|
||||
|
||||
static const uint32_t controller_pins[GPIOC_COUNT] = {
|
||||
GPIO_GROUP_COUNT * GPIOPADPINS,
|
||||
GPIO_1_GROUP_COUNT * GPIOPADPINS,
|
||||
};
|
||||
|
||||
const uint32_t * target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
static const struct pinconfig_map *selected_map = NULL;
|
||||
|
||||
/* Cannot use malloc as chunk manager is yet to be intialized */
|
||||
static uint32_t pinconfig_buf[GPIO_GROUP_COUNT * GPIOPADPINS];
|
||||
expanded_pinconfigs[0] = pinconfig_buf;
|
||||
static uint32_t pinconfig_buf_1[GPIO_1_GROUP_COUNT * GPIOPADPINS];
|
||||
expanded_pinconfigs[1] = pinconfig_buf_1;
|
||||
|
||||
ASSERT(gpioc < GPIOC_COUNT);
|
||||
|
||||
if (selected_map == NULL) {
|
||||
uint32_t board_id = platform_get_board_id();
|
||||
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
|
||||
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
|
||||
selected_map = &cfg_map[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (selected_map == NULL)
|
||||
panic("no default pinconfig for board id %u", board_id);
|
||||
|
||||
for (unsigned i = 0; i < GPIOC_COUNT; i++) {
|
||||
uint32_t num_pins = controller_pins[i];
|
||||
|
||||
for (uint32_t j = 0; j < num_pins; j++) {
|
||||
uint8_t enum_key = selected_map->pinconfigs[i][j];
|
||||
expanded_pinconfigs[i][j] = enum_map[enum_key];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return expanded_pinconfigs[gpioc];
|
||||
}
|
||||
@@ -0,0 +1,55 @@
|
||||
# Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D2255=1 \
|
||||
TARGET_CHESTNUT_USE_LOW_RIPPLE_MODE=1 \
|
||||
TARGET_BOOT_CPU_VOLTAGE=0 \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=3 \
|
||||
TARGET_PLL_VCO_CAP=0 \
|
||||
TARGET_VCO_RANGE=3 \
|
||||
TARGET_LPF_CTRL=8 \
|
||||
TARGET_ICP_CTR=6 \
|
||||
TARGET_HS_2_LP_DATA_TIME=35 \
|
||||
TARGET_LP_2_HS_DATA_TIME=54 \
|
||||
TARGET_HS_2_LP_CLOCK_TIME=57 \
|
||||
TARGET_LP_2_HS_CLOCK_TIME=119 \
|
||||
TARGET_PHY_STOP_WAIT_TIME=0x28 \
|
||||
DISPLAY_IPHONE_TUNABLES=1 \
|
||||
DPB_DETECT_VIB_CONTROL_TUNABLE=0xa4830001 \
|
||||
DCS_NUM_RANKS=1 \
|
||||
DCS_NUM_CHANNELS=4 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_CPU_RAM=7 \
|
||||
BUCK_SOC=2 \
|
||||
BUCK_GPU=1 \
|
||||
BUCK_GPU_RAM=8 \
|
||||
WITH_CPU_APSC=1 \
|
||||
MULTITOUCH_DTPATH=\"arm-io/spi2/multi-touch\" \
|
||||
WIFI_DTPATH=\"arm-io/uart4/wlan\" \
|
||||
BT_DTPATH=\"arm-io/uart1/bluetooth\"
|
||||
|
||||
# XXX - Needs added for Agile clocking
|
||||
# WITH_HW_AGC_MIPI_V2=1 \
|
||||
# TARGET_AGILE_LINECOUNT=0x9 \
|
||||
# TARGET_AGILE_SEQ1=0x2010002 \
|
||||
# TARGET_AGILE_SEQ2=0x6010231 \
|
||||
# TARGET_AGILE_CTRL=0xC1804 \
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/pinconfig.o
|
||||
Reference in new issue
Block a user