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@@ -0,0 +1,31 @@
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/*
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* Copyright (C) 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ADBE_SETTINGS_H
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#define __TARGET_ADBE_SETTINGS_H
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static struct adbe_v2_tuneable adbe_tuneables[] =
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{
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{
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.name = "D403",
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.adbe0_vblank_pos_vbi_pulse = 0x0169,
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.adbe0_vblank_clk_gate_wakeup = 0x0007,
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.adbe0_vblank_clk_gate_idle = 0x0000,
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.adbe0_vblank_busy_finish = 0x2,
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.adbe0_tunable_mode_ctrl = (DBEMODECNTL_DPB_BUSY_MASK | \
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DBEMODECNTL_PMGR_CLK_GATE_ENABLE | \
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DBEMODECNTL_DYN_CLK_GATE_ENABLE | \
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DBEMODECNTL_BLK_CLK_GATE_ENABLE),
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.adbe0_aap_support = 1,
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.adbe0_aap_format_control_reg1 = (AAP_FORMAT_CONTROL_REG1_AUTOPOS | AAP_FORMAT_CONTROL_REG1_RSVD(9) | AAP_FORMAT_CONTROL_REG1_VS_POL),
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},
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};
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#endif
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ASPNANDCONFIG_H
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#define __TARGET_ASPNANDCONFIG_H
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//MLC devices
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#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
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#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_DIES_IN_PARALLEL 4
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#define ASPNAND_READ_DIES_IN_PARALLEL 4
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#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
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//TLC devices
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#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 4
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#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 4
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#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
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// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
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#define ASPNAND_INDIRECTION_MEMORY (4*1024*1024)
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#define ASPNAND_LEGACY_INDIRECTION_MEMORY ASPNAND_INDIRECTION_MEMORY
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#endif
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@@ -0,0 +1,49 @@
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/*
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* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* iphone8,x specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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/* Board Revision */
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#define GPIO_BOARD_REV0 GPIO_ID(146) // 74 : GPIO[34]
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#define GPIO_BOARD_REV1 GPIO_ID(145) // 73 : GPIO[35]
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#define GPIO_BOARD_REV2 GPIO_ID(144) // 72 : GPIO[36]
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#define GPIO_BOARD_REV3 GPIO_ID(143) // 71 : GPIO[37]
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/* Miscellaneous Pins */
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#define GPIO_DISPLAY_ID1 GPIO( 4, 0) // 32 : UART7_TXD -> DISPLAY_TO_AP_ID0 (DEV BOARD only)
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#define GPIO_DISPLAY_ID0 GPIO( 4, 1) // 33 : UART7_RXD -> DISPLAY_TO_AP_ID1 (DEV BOARD only)
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#define GPIO_PROX_SELECT GPIO( 4, 1) // 32 : UART7_RXD -> PROX_SELECT (AP BOARD only)
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/* Display reset */
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#define GPIO_LCD_RST GPIO( 9, 4) // GPIO[12] -> AP_TO_LCM_RESET_L
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#define GPIO_LCD_RST_POLARITY (0) // active low
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/* Ringer Switch */
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#define GPIO_RINGER_AB GPIO(16, 3) // 131 : GPIO[40] -> BUTTON_TO_AP_RINGER_A
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#define GPIO_S3E_BOOT_FROM_HOST GPIO_ID(141) // 141 : GPIO[32] -> AP_TO_NAND_FW_STRAP
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/* which IICs to initialize */
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#define IICS_MASK (7)
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#define TRISTAR_IIC_BUS (1)
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#define DISPLAY_PMU_IIC_BUS (0)
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#define GPIO_PMU_NAND_LOW_POWER_MODE (5) // PMU_TO_NAND_LOW_BATT_BOOT
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,144 @@
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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#define CHARGER_IIC_BUS 1
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD2255_EN_CMD0, (1<<7)|(1<<2)|(1<<1)|(1<<0) },
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{ PMU_IIC_BUS, kD2255_EN_CMD1, (1<<0) }, // buck8
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{ PMU_IIC_BUS, kD2255_SPI_CTRL, 1 }, // enable SPI access
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{ PMU_IIC_BUS, kD2255_LDO9_VSEL, 0x1E}, // LDO9 at 2.55V rdar://20437860
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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};
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// IO_CONFIG[7:6] 0=I 1=O_OD 2=O_PP 3=SS
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// IO_TYPE[5:3] O 0=L 1=32K 2=nR 3=TI 4=L
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// PUPD[2:1] O 0=NP 1=PU 2=NP 3=<0>
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// WAKE_LVL[0] O 0=low 1=high
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// IO_TYPE[5:3] I 0=L_AH 1=L_AL 2=RE 3=FE 4=AE
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// PUPD[2:1] I 0=NP 1=PU 2=PD_GND 3=<0>
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// WAKE_LVL[0] I 0=NW 1=W
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//
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// <rdar://19269873 N69 IO Spreadsheet
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// <rdar://21492643 N69 PMU GPIO: Implement IOspreadsheet 0v15
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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{ PMU_IIC_BUS, kD2255_GPIO1_CONF1, (0<<6)|(1<<3)|(0<<1)|(1<<0) }, // I.AL.NP.WS TIGRIS_TO_PMU_INT_L
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{ PMU_IIC_BUS, kD2255_GPIO1_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO2_CONF1, (0<<6)|(1<<3)|(2<<1)|(0<<0) }, // I.AL.PD.NW*, BB_TO_PMU_HOST_WAKE_L
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{ PMU_IIC_BUS, kD2255_GPIO2_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO3_CONF1, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // O_PP.L.NP.0 PMU_TO_BB_PMIC_RESET_R_L
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{ PMU_IIC_BUS, kD2255_GPIO3_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO4_CONF1, (0<<6)|(0<<3)|(2<<1)|(1<<0) }, // I.AH.PD.WS TRISTAR_TO_AP_INT
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{ PMU_IIC_BUS, kD2255_GPIO4_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO5_CONF1, (0<<6)|(0<<3)|(2<<1)|(1<<0) }, // I.AH.PD.WS STOCKHOLM_TO_PMU_HOST_WAKE
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{ PMU_IIC_BUS, kD2255_GPIO5_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO6_CONF1, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // O_PP.L.NP.0 PMU_TO_NAND_LOW_BATT_BOOT_L
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{ PMU_IIC_BUS, kD2255_GPIO6_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO7_CONF1, (0<<6)|(0<<3)|(2<<1)|(1<<0) }, // I.AH.PD.WS WLAN_TO_PMU_HOST_WAKE
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{ PMU_IIC_BUS, kD2255_GPIO7_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO8_CONF1, (0<<6)|(4<<3)|(1<<1)|(1<<0) }, // I.AE.PU.WS CODEC_TO_PMU_MIKEY_INT_L
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{ PMU_IIC_BUS, kD2255_GPIO8_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO9_CONF1, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // O_PP.L.NP.0 PMU_TO_BT_REG_ON
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{ PMU_IIC_BUS, kD2255_GPIO9_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO10_CONF1, (0<<6)|(2<<3)|(0<<1)|(1<<0) }, // I.RE.NP.WS BT_TO_PMU_HOST_WAKE
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{ PMU_IIC_BUS, kD2255_GPIO10_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO11_CONF1, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // O_PP.L.NP.0 PMU_TO_WLAN_REG_ON
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{ PMU_IIC_BUS, kD2255_GPIO11_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO12_CONF1, (1<<6)|(2<<3)|(0<<1)|(0<<0) }, // O_OD.nR.NP.0 NC
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{ PMU_IIC_BUS, kD2255_GPIO12_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO13_CONF1, (1<<6)|(0<<3)|(1<<1)|(0<<0) }, // O_OD.L.PU.0 PMU_TO_CODEC_DIGLDO_PULLDN
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{ PMU_IIC_BUS, kD2255_GPIO13_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO14_CONF1, (0<<6)|(3<<3)|(1<<1)|(0<<0) }, // I.FE.PU.NW CODEC_TO_AP_PMU_INT_L
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{ PMU_IIC_BUS, kD2255_GPIO14_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO15_CONF1, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // O_PP.L.NP.0 PMU_TO_BB_USB_VBUS_DETECT
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{ PMU_IIC_BUS, kD2255_GPIO15_CONF2, (0<<3)|(2<<0) }, // VCC_MAIN, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO16_CONF1, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // O_PP.L.NP.0 PMU_TO_STOCKHOLM_EN
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{ PMU_IIC_BUS, kD2255_GPIO16_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO17_CONF1, (0<<6)|(1<<3)|(1<<1)|(0<<0) }, // I.AL.PU.NW, WLAN_TO_PMU_PCIE_WAKE_L
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{ PMU_IIC_BUS, kD2255_GPIO17_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO18_CONF1, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // O_PP.L.NP.0 NC
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{ PMU_IIC_BUS, kD2255_GPIO18_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO19_CONF1, (2<<6)|(0<<3)|(0<<1)|(1<<0) }, // O_PP.L.NP.1 PMU_TO_LCM_PANICB use OTP-AJ..AG setting rdar://19987012
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{ PMU_IIC_BUS, kD2255_GPIO19_CONF2, (2<<3)|(2<<0) }, // VBUCK3_SW1, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO20_CONF1, (3<<6)|(2<<3)|(2<<1)|(0<<0) }, // SS.RE.PD.NW NC
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{ PMU_IIC_BUS, kD2255_GPIO20_CONF2, (1<<3)|(2<<0) }, // VBUCK3, 10ms
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{ PMU_IIC_BUS, kD2255_GPIO21_CONF1, (1<<6)|(0<<3)|(0<<1)|(1<<0) }, // O_OD.L.NP.1 I2C0_AP_SCL
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{ PMU_IIC_BUS, kD2255_GPIO21_CONF2, (2<<3)|(2<<0) }, // VBUCK3_SW1, 10ms
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// Overrides for OTP-AI per <rdar://problem/19869417> N69m iBoot driver update
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{ PMU_IIC_BUS, kDIALOG_TEST_ACCESS, kDIALOG_TEST_ACCESS_ENA }, // enable test register access
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{ PMU_IIC_BUS, kD2255_BUCK1_ANA_TRIM10, 0x69 },
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{ PMU_IIC_BUS, kD2255_BUCK1_CLK_TRIM1, 0x01 },
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{ PMU_IIC_BUS, kD2255_BUCK1_CLK_TRIM2, 0x05 },
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{ PMU_IIC_BUS, kD2255_BUCK1_CLK_TRIM3, 0x0F },
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{ PMU_IIC_BUS, kD2255_BUCK2_MINV, 0x8 }, // <rdar://problem/21472020> Lower BUCK2_MINV
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// Set Buck5 Current
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{ PMU_IIC_BUS, kD2255_BUCK5_ANA_TRIM14, 0x36 }, // Malta ILIM at 1.80A Max Load at 1.43 rdar://19846032
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{ PMU_IIC_BUS, kD2255_PWRONOFF_OUT_32K_EN, 0x7 }, // OUT_32K active in ACTIVE, SLEEP1,2
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{ PMU_IIC_BUS, kDIALOG_TEST_ACCESS, kDIALOG_TEST_ACCESS_DIS }, // disabled test register access
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{ PMU_IIC_BUS, kD2255_PWRONOFF_LDO8_EN, 0x1}, // enable Vibrator rdar://20643930
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{ PMU_IIC_BUS, kD2255_OUT_32K, 0x49 }, // OUT_32K active, VBUCK3, PP
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};
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static const struct core_rails_struct soc_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2255_BUCK2_VSEL }
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};
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static const struct core_rails_struct cpu_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2255_BUCK0_VSEL }
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};
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// it's VDD FIXED! used for RAM inside the SOC
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static const struct core_rails_struct ram_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2255_BUCK5_VSEL }
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};
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// this is indexed with POWER_RAIL_*, I really just need to use the index in LDO[]
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target_rails_t target_rails = {
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{ 0x0F, 500, 1296, 3125 }, // POWER_RAIL_CPU, BUCK0
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{ 0x14, 600, 1396, 3125 }, // POWER_RAIL_VDD_FIXED BUCK5
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{ 0x11, 600, 1396, 3125 }, // POWER_RAIL_SOC, BUCK2
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{ 0x16, 600, 1396, 3125 }, // POWER_RAIL_CPU_RAM, BUCK7
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{ 0x17, 500, 1296, 3125 }, // POWER_RAIL_GPU, BUCK1
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{ 0x17, 600, 1396, 3125 }, // POWER_RAIL_GPU_RAM, BUCK8
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};
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#endif /* POWERCONFIG_PMU_SETUP */
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#define NO_BATTERY_VOLTAGE 2700
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#define MIN_BOOT_BATTERY_VOLTAGE 3600
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#define TARGET_BOOT_BATTERY_VOLTAGE 3700
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#define TARGET_POWER_NEEDS_BATTERY_PROTECTION_RESET 1
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#define PRECHARGE_BACKLIGHT_LEVEL 824
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#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
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#define ACC_PWR_LDO (6)
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#endif
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@@ -0,0 +1,23 @@
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/*
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||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
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#define __TARGET_UARTCONFIG_H
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/* define one debug serial ports */
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#define DEBUG_SERIAL_PORT (0)
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#define HDQGAUGE_SERIAL_PORT (5)
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#if SUPPORT_FPGA
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#define UART_OVERSAMPLE_OVERRIDE (11)
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#endif
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#endif
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