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Chris Nutter committed 2023-07-08 13:03:17 -07:00
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target/n78/include/target/gpiodef.h
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/*
* Copyright (C) 2011 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_GPIODEF_H
#define __TARGET_GPIODEF_H
/* N78 specific gpio -> pin mappings */
#include <platform/gpio.h>
/* define target-specific gpios in a generic fashion here. */
#define GPIO_LCD_RST GPIO( 2, 6)
#define GPIO_LCD_RST_POLARITY (0)
#define GPIO_RINGER_AB GPIO( 0, 4)
/* Board Revision */
#define GPIO_BOARD_REV0 GPIO( 4, 5)
#define GPIO_BOARD_REV1 GPIO( 4, 6)
#define GPIO_BOARD_REV2 GPIO( 4, 7)
#define GPIO_BOARD_REV3 GPIO( 2, 1)
/* Grape ID */
#define GPIO_GRAPE_ID0 GPIO( 3, 7)
#define GPIO_GRAPE_ID1 GPIO( 4, 0)
#define GPIO_GRAPE_ID2 GPIO( 4, 3)
/* which IICs to initialize */
#define IICS_MASK (5)
#define TRISTAR_IIC_BUS (0)
/* D1881 watchdog tickle, 'KEEPACT' */
#define GPIO_WDOG_TICKLE GPIO(2, 3)
#endif /* ! __TARGET_GPIODEF_H */
target/n78/include/target/nand_spec_tables.h
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// Copyright (C) 2008-2010 Apple, Inc. All rights reserved.
//
// This document is the property of Apple, Inc.
// It is considered confidential and proprietary.
//
// This document may not be reproduced or transmitted in any form,
// in whole or in part, without the express written permission of
// Apple, Inc.
//
// NOTE: This is a generated file and should not be hand-edited!
//
// =============================================================================
// Nand Geometry Table
static NandGeometry _nandGeometryTable[] =
{
};
// =============================================================================
// Nand Timing Table
static NandTiming _nandTimingTable[] =
{
};
#if (defined (AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
// =============================================================================
// NandChipId Description
const NandChipIdDescription _nandChipIdDescriptionTable[] =
{
};
// =============================================================================
// Nand Description Table
static const NandDescription _nandDescriptionTable[] =
{
};
const UInt32 _nandDescriptionTableSize = sizeof(_nandDescriptionTable) / sizeof(NandDescription);
#endif // (defined(AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
// =============================================================================
// Nand Board Support Table
static NandBoardSupport _nandBoardSupportTable[] =
{
};
// =============================================================================
// Nand Board Timing Table
static NandBoardInfo _nandBoardInfo =
{
/* controlDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
/* dataDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
/* chipEnableDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
/* socToNandRiseNanosecs */ 10,
/* socToNandFallNanosecs */ 10,
/* nandToSocRiseNanosecs */ 10,
/* nandToSocFallNanosecs */ 10,
/* landing map */
{
0x00000101
},
/* useToggleMode */ TRUE32,
/* useDiffDQSMode */ FALSE32,
/* useDiffREMode */ FALSE32,
/* useVref */ TRUE32,
/* useSingleHostChannel */ FALSE32,
/* allowSingleChipEnable */ TRUE32
};
static NandFormat _nandFormatPpn =
{
/* metaPerLogicalPage */ 16,
/* validMetaPerLogicalPage */ 16,
/* logicalPageSize */ 4096
};
static NandFormat _nandFormatRaw =
{
/* metaPerLogicalPage */ 12,
/* validMetaPerLogicalPage */ 10,
/* logicalPageSize */ 0
};
target/n78/include/target/pinconfig.h
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/*
* Copyright (C) 2009-2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
/* Default n78 SoC Pin Configuration */
/* Same drive strength for AP and DEV */
#define AUD_SPKRAMP_MUTE_L_DRIVE_STR DRIVE_X1
#define DFU_STATUS_DRIVE_STR DRIVE_X1
#define DWI_DRIVE_STR DRIVE_X1
#define FMI_DRIVE_STR DRIVE_X2 // SecureROM is X2
#define GRAPE_DRIVE_STR DRIVE_X1
#define MLC_DRIVE_STR DRIVE_X1
#define PM_BT_WAKE_DRIVE_STR DRIVE_X1
#define PM_CAM_SHUTDOWN_DRIVE_STR DRIVE_X1
#define CLK_CAM_DRIVE_STR DRIVE_X1
#define PM_KEEPACT_DRIVE_STR DRIVE_X1
#define RST_PMU_IN_DRIVE_STR DRIVE_X1
#define SDIO_WL_DRIVE_STR DRIVE_X1
#define VIDEO_AMP_EN_DRIVE_STR DRIVE_X1
#define I2C_DRIVE_STR DRIVE_X1
#define UART_5_DRIVE_STR DRIVE_X2
#define I2S_DRIVE_STR DRIVE_X1
#define I2S_MCK_DRIVE_STR DRIVE_X1
#define SPI_CS_DRIVE_STR DRIVE_X1
#define SPI_DATA_DRIVE_STR DRIVE_X1
/* Different drive strength for AP and DEV. // AP DEV */
#if PIN_CFG_AP
#define BT_UART_DRIVE_STR DRIVE_X1 // X2 X3
#define UART_0_DRIVE_STR DRIVE_X1 // X2 X3
#else
#define BT_UART_DRIVE_STR DRIVE_X1 // X2 X3
#define UART_0_DRIVE_STR DRIVE_X1 // X2 X2
#endif
#define FMI_SLEW_RATE SLEW_RATE_SLOW
#if PIN_CFG_AP
static const u_int32_t gpio_default_cfg_ap[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#elif PIN_CFG_DEV
static const u_int32_t gpio_default_cfg_dev[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#endif
/* Port 0 */
CFG_IN, // GPIO0 -> MENU_KEY (REQUEST_DFU2)
CFG_IN, // GPIO1 -> HOLD_KEY (REQUEST_DFU1)
CFG_IN | PULL_UP, // GPIO2 -> VOL_UP_L
CFG_IN | PULL_UP, // GPIO3 -> VOL_DOWN_L
CFG_OUT_0, // GPIO4 -> ACC_UHPM_EN
CFG_IN | PULL_UP, // GPIO5 -> SPKR_AMP_INT_L
CFG_IN | PULL_DOWN, // GPIO6 -> WLAN_HSIC_OOB
CFG_OUT_0, // GPIO7 -> BT_WAKE
/* Port 1 */
CFG_OUT_0, // GPIO8 -> WLAN_HSIC_AP_RDY
CFG_IN | PULL_DOWN, // GPIO9 -> WLAN_HSIC_DEV_RDY
CFG_OUT_0, // GPIO10 -> STAYIN_ALIVE
CFG_OUT_1, // GPIO11 -> CAM_REAR_EXT_LDO_EN
CFG_OUT_1, // GPIO12 -> CAM_FRONT_EXT_LDO_EN
CFG_IN | PULL_UP, // GPIO13 -> IRQ_PMU_L
CFG_OUT_0, // GPIO14 -> GRAPE_RESET_L
CFG_OUT_0, // GPIO15 -> SPKR_AMP_RESET_L
/* Port 2 */
CFG_IN, // GPIO16 -> BOARD_ID_3
CFG_IN, // GPIO17 -> BRD_REV3
CFG_IN | PULL_DOWN, // GPIO18 -> BOOT_CONFIG_0
CFG_OUT_0 | PM_KEEPACT_DRIVE_STR, // GPIO19 -> PM_KEEPACT
CFG_IN, // GPIO20 -> TRISTAR_INT
CFG_IN | PULL_UP, // GPIO21 -> GRAPE_INT_L
CFG_OUT_0 | GRAPE_DRIVE_STR, // GPIO22 -> LCD_RESET_L
CFG_IN, // GPIO23 -> LCD_HIFA_BSYNC
/* Port 3 */
CFG_DISABLED | PULL_DOWN, // GPIO24 ->
CFG_IN | PULL_DOWN, // GPIO25 -> BOOT_CONFIG_1
CFG_IN | PULL_DOWN, // GPIO26 -> FORCE_DFU
CFG_OUT_0 | DFU_STATUS_DRIVE_STR, // GPIO27 -> DFU_STATUS
CFG_IN, // GPIO28 -> BOOT_CONFIG_2
CFG_IN, // GPIO29 -> BOOT_CONFIG_3
CFG_IN | PULL_UP, // GPIO30 -> CODEC_INT_L
CFG_DISABLED | PULL_DOWN, // GPIO31 ->
/* Port 4 */
CFG_DISABLED | PULL_DOWN, // GPIO32 ->
CFG_IN, // GPIO33 -> IRQ_GYRO_INT1
CFG_IN, // GPIO34 -> ACC_UHPM_POK
CFG_DISABLED | PULL_DOWN, // GPIO35 ->
CFG_IN, // GPIO36 -> ACCEL_INT2_L
CFG_IN, // EHCI_PORT_PWR[0] -> AP_GPIO37_BRD_REV0
CFG_IN, // EHCI_PORT_PWR[1] -> AP_GPIO38_BRD_REV1
CFG_IN, // EHCI_PORT_PWR[2] -> AP_GPIO39_BRD_REV2
/* Port 5 */
CFG_FUNC0, // UART1_TXD -> UART1_TXD_AP_DBG
CFG_FUNC0, // UART1_RXD -> UART1_RXD_AP_DBG
CFG_DISABLED | PULL_DOWN, // UART1_RTSN ->
CFG_DISABLED | PULL_DOWN, // UART1_CTSN ->
CFG_FUNC0, // UART2_TXD -> UART2_TXD_ACC
CFG_FUNC0, // UART2_RXD -> UART2_RXD_ACC
CFG_IN, // UART2_RTSN -> CAM_STROBE_EN
CFG_DISABLED | PULL_DOWN, // UART2_CTSN ->
/* Port 6 */
CFG_FUNC0 | BT_UART_DRIVE_STR, // UART3_TXD -> UART_3_TXD_BT
CFG_FUNC0, // UART3_RXD -> UART_3_RXD_BT
CFG_OUT_1 | BT_UART_DRIVE_STR, // UART3_RTSN -> UART_3_CTS_L_BT
CFG_FUNC0, // UART3_CTSN -> UART_3_RTS_L_BT
CFG_FUNC0 | I2C_DRIVE_STR, // I2C0_SDA -> I2C0_SDA_1V8
CFG_FUNC0 | I2C_DRIVE_STR, // I2C0_SCL -> I2C0_SCL_1V8
CFG_DISABLED | PULL_DOWN, // I2C1_SDA ->
CFG_DISABLED | PULL_DOWN, // I2C1_SCL ->
/* Port 7 */
CFG_FUNC0 | I2C_DRIVE_STR, // ISP0_SDA -> I2C_CAM_REAR_SDA_1V8
CFG_FUNC0 | I2C_DRIVE_STR, // ISP0_SCL -> I2C_CAM_REAR_SCL_1V8
CFG_FUNC0 | I2C_DRIVE_STR, // ISP1_SDA -> I2C_FRONT_SDA_1V8
CFG_FUNC0 | I2C_DRIVE_STR, // ISP1_SCL -> I2C_FRONT_SCL_1V8
CFG_DISABLED | PULL_DOWN, // UART5_TXD/MIPI_VSYNC ->
CFG_FUNC0 | PULL_DOWN, // TMR32_PWM0 -> GYRO_INT2
CFG_FUNC0 | PULL_DOWN, // TMR32_PWM1 -> ACCEL_INT1_L
CFG_FUNC0 | GRAPE_DRIVE_STR, // TMR32_PWM2 -> CLK32K_GRAPE_CLK
/* Port 8 */
CFG_DISABLED | PULL_DOWN, // SWI_DATA ->
CFG_FUNC0 | DWI_DRIVE_STR, // DWI_DI -> DWI_AP_DI
CFG_FUNC0 | DWI_DRIVE_STR, // DWI_DO -> DWI_AP_DO
CFG_FUNC0 | DWI_DRIVE_STR, // DWI_CLK -> DWI_AP_CLK
CFG_OUT_1 | PM_CAM_SHUTDOWN_DRIVE_STR, // SENSOR0_RST -> PM_REAR_CAM_SHUTDOWN_L
CFG_OUT_0 | CLK_CAM_DRIVE_STR, // SENSOR0_CLK -> CLK_CAM_RF
CFG_OUT_1 | PM_CAM_SHUTDOWN_DRIVE_STR, // SENSOR1_RST -> PM_FRONT_CAM_SHUTDOWN
CFG_OUT_0 | CLK_CAM_DRIVE_STR, // SENSOR1_CLK -> CLK_CAM_FF
/* Port 9 */
CFG_OUT_0, // ISP0_PRE_FLASH -> CAM_REAR_TORCH
CFG_DISABLED | PULL_DOWN, // ISP0_FLASH -> CAM_REAR_RESET_L
CFG_DISABLED | PULL_DOWN, // ISP1_PRE_FLASH ->
CFG_DISABLED | PULL_DOWN, // ISP1_FLASH -> CAM_FRONT_RESET_L
CFG_FUNC0 | I2S_MCK_DRIVE_STR, // I2S0_MCK -> I2S_AP_0_MCK
CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_LRCK -> I2S_AP_0_LRCK
CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_SCLK -> I2S_AP_0_BCLK
CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_DOUT -> I2S_AP_0_DOUT
/* Port 10 */
CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_DIN -> I2S_AP_0_DIN
CFG_DISABLED | PULL_DOWN, // I2S1_MCK ->
CFG_FUNC0 | I2S_DRIVE_STR, // I2S1_LRCK -> BT_PCM_SYNC
CFG_FUNC0 | I2S_DRIVE_STR, // I2S1_SCLK -> BT_PCM_CLK
CFG_FUNC0 | I2S_DRIVE_STR, // I2S1_DOUT -> BT_PCM_IN
CFG_FUNC0 | I2S_DRIVE_STR, // I2S1_DIN -> BT_PCM_OUT
CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_MCK -> SPKR_AMP_PCM_MCLK_R
CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_LRCK -> SPKR_AMP_PCM_FSYNC_R
/* Port 11 */
CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_BCLK -> SPKR_AMP_PCM_BITCLK_R
CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_DOUT -> SPKR_AMP_PCM_DOUT_R
CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_DIN -> SPKR_AMP_PCM_DIN_R
CFG_DISABLED | PULL_DOWN, // I2S3_MCK ->
CFG_FUNC0 | I2S_DRIVE_STR, // I2S3_LRCK -> CODEC_XSP_MCLK_R
CFG_FUNC0 | I2S_DRIVE_STR, // I2S3_BCLK -> CODEC_XSP_FSYNC_R
CFG_FUNC0 | I2S_DRIVE_STR, // I2S3_DOUT -> CODEC_XSP_DOUT_R
CFG_FUNC0 | I2S_DRIVE_STR, // I2S3_DIN -> CODEC_XSP_DIN_R
/* Port 12 */
CFG_IN, // SPI0_SCLK -> BOARD_ID_0
CFG_IN, // SPI0_MOSI -> BOARD_ID_1
CFG_IN, // SPI0_MISO -> BOARD_ID_2
CFG_OUT_1, // SPI0_SSIN -> LCD_PIFA_R
CFG_FUNC0 | SPI_DATA_DRIVE_STR, // SPI1_SCLK -> SPI_GRAPE_SCLK
CFG_FUNC0 | SPI_DATA_DRIVE_STR, // SPI1_MOSI -> SPI_GRAPE_MOSI
CFG_FUNC0, // SPI1_MISO -> SPI_GRAPE_MISO
CFG_FUNC0 | SPI_CS_DRIVE_STR, // SPI1_SSIN -> SPI_GRAPE_CS_L
/* Port 13 */
CFG_FUNC0, // SPI2_SCLK -> SPI_CODEC_CLK
CFG_FUNC0, // SPI2_MOSI -> SPI_CODEC_MOSI
CFG_FUNC0, // SPI2_MISO -> SPI_CODEC_MISO
CFG_FUNC0, // SPI2_SSIN -> SPI_CODEC_SSN
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
/* Port 14 */
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
/* Port 15 */
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
/* Port 16 */
CFG_FUNC0 | MLC_DRIVE_STR, // UART4_TXD -> WLAN_DBG_UART_RXD
CFG_FUNC0 | MLC_DRIVE_STR, // UART4_RXD -> WLAN_DBG_UART_TXD
CFG_DISABLED | PULL_DOWN, // UART4_RTSN ->
CFG_OUT_0, // UART4_CTSN -> PMU_AMUX_AY_CTRL
CFG_DISABLED | PULL_DOWN, // SDIO0_DATA3 ->
CFG_DISABLED | PULL_DOWN, // SDIO0_DATA2 ->
CFG_DISABLED | PULL_DOWN, // SDIO0_DATA1 ->
CFG_DISABLED | PULL_DOWN, // SDIO0_DATA0 ->
/* Port 17 */
CFG_DISABLED | PULL_DOWN, // SDIO0_CMD ->
CFG_DISABLED | PULL_DOWN, // SDIO0_CLK ->
CFG_DISABLED | PULL_DOWN, // FMI0_CEN3 -> F0CE3_L
CFG_DISABLED | PULL_DOWN, // FMI0_CEN2 -> F0CE2_L
CFG_DISABLED | PULL_DOWN, // FMI0_CEN1 -> F0CE1_L
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN0 -> F0CE0_L
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CLE -> F0CLE
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_ALE -> F0ALE
/* Port 18 */
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_REN -> F0RE_L
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_WEN -> F0WE_L
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI0_IO7 -> F0AD<7>
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI0_IO6 -> F0AD<6>
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI0_IO5 -> F0AD<5>
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI0_IO4 -> F0AD<4>
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
/* Port 19 */
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
/* Port 20 */
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI0_DQS -> F0DQS
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI0_IO3 -> F0AD<3>
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI0_IO2 -> F0AD<2>
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI0_IO1 -> F0AD<1>
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI0_IO0 -> F0AD<0>
CFG_DISABLED | PULL_DOWN, // FMI1_CEN3 ->
CFG_DISABLED | PULL_DOWN, // FMI1_CEN2 ->
CFG_DISABLED | PULL_DOWN, // FMI1_CEN1 ->
/* Port 21 */
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN0 -> F1CE0_L
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CLE -> F1CLE
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_ALE -> F1ALE
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_REN -> F1RE_L
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_WEN -> F1WE_L
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI1_IO7 -> F1AD<7>
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI1_IO6 -> F1AD<6>
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI1_IO5 -> F1AD<5>
/* Port 22 */
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI1_IO4 -> F1AD<4>
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI1_DQS -> FMI1DQS
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI1_IO3 -> F1AD<3>
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI1_IO2 -> F1AD<2>
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI1_IO1 -> F1AD<1>
CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD, // FMI1_IO0 -> F1AD<0>
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
/* Port 23 */
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
/* Port 24 */
CFG_FUNC0 | I2C_DRIVE_STR, // I2C2_SDA -> I2C2_SDA_1V8
CFG_FUNC0 | I2C_DRIVE_STR, // I2C2_SCL -> I2C2_SCL_1V8
CFG_OUT_0, // UART0_TXD -> CAM_FLASH_EN
CFG_DISABLED | PULL_DOWN, // UART0_RXD ->
CFG_DISABLED | PULL_DOWN, // UART5_RTXD ->
CFG_DISABLED | PULL_DOWN, // DP_HPD ->
CFG_DISABLED | PULL_DOWN, // TST_CLKOUT ->
CFG_DISABLED | PULL_DOWN, // TST_STPCLK -> GND
/* Port 25 */
CFG_FUNC0 | RST_PMU_IN_DRIVE_STR, // WDOG -> RST_PMU_IN
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
CFG_DISABLED | PULL_DOWN, // ->
};
#undef AUD_SPKRAMP_MUTE_L_DRIVE_STR
#undef DFU_STATUS_DRIVE_STR
#undef DWI_DRIVE_STR
#undef FMI_DRIVE_STR
#undef GRAPE_DRIVE_STR
#undef MLC_DRIVE_STR
#undef PM_BT_WAKE_DRIVE_STR
#undef PM_CAM_SHUTDOWN_DRIVE_STR
#undef CLK_CAM_DRIVE_STR
#undef PM_KEEPACT_DRIVE_STR
#undef RST_PMU_IN_DRIVE_STR
#undef SDIO_WL_DRIVE_STR
#undef VIDEO_AMP_EN_DRIVE_STR
#undef I2C_DRIVE_STR
#undef UART_5_DRIVE_STR
#undef I2S_DRIVE_STR
#undef I2S_MCK_DRIVE_STR
#undef SPI_CS_DRIVE_STR
#undef SPI_DATA_DRIVE_STR
#undef BT_UART_DRIVE_STR
#undef UART_0_DRIVE_STR
#undef FMI_SLEW_RATE
target/n78/include/target/powerconfig.h
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/*
* Copyright (C) 2010-2011 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_POWERCONFIG_H
#define __TARGET_POWERCONFIG_H
#include <stdbool.h>
/* configuration per target */
#define PMU_IIC_BUS 0
/* this configuration is very PMU specific and must be included exactly once in power.c */
#ifdef POWERCONFIG_PMU_SETUP
/* Matched to D1881B1-OTP-CD-v5 */
static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
{
{ PMU_IIC_BUS, kD1881_LDO1, 0x0D }, // PP3V0_USB 3.15V <rdar://problem/9200307>
{ PMU_IIC_BUS, kD1881_LDO2, 0x0A }, // PP1V7_VA_VCP 1.70V
{ PMU_IIC_BUS, kD1881_LDO3, 0x0A }, // PP3V0_IMU 3.00V
{ PMU_IIC_BUS, kD1881_LDO4, 0x16 }, // PP3V0_OPTICAL 2.90V
{ PMU_IIC_BUS, kD1881_LDO5, 0x0A }, // PP3V0_NAND 3.00V
{ PMU_IIC_BUS, kD1881_LDO6, 0x10 }, // PP3V3_ACC 3.30V
{ PMU_IIC_BUS, kD1881_LDO7, 0x0F }, // PP3V3_VIDEO 3.00V
{ PMU_IIC_BUS, kD1881_LDO8, 0x14 }, // PP3V0_USBMUX 3.00V
{ PMU_IIC_BUS, kD1881_LDO9, 0x01 }, // PP1V5_CAM_AVDD 1.30V
{ PMU_IIC_BUS, kD1881_LDO10, 0x01 }, // PP2V8_CAM_AVDD 2.55V
{ PMU_IIC_BUS, kD1881_LDO11, 0x02 }, // 1.80V
{ PMU_IIC_BUS, kD1881_LDO12, 0x10 }, // PP1V1 1.00V
{ PMU_IIC_BUS, kDIALOG_LDO_CONTROL, 0x00 }, // no bypass
};
static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
{
{ PMU_IIC_BUS, kD1881_ACTIVE1, 0xBD }, // Everything except VBUCK1, LDO2
{ PMU_IIC_BUS, kD1881_ACTIVE2, 0xBB }, // LDO4, LDO5, LDO7, LDO8, LDO9, LDO11 enabled
{ PMU_IIC_BUS, kD1881_ACTIVE3, 0x2F }, // LDO12
{ PMU_IIC_BUS, kD1881_ACTIVE4, 0xE0 }, // CPU1V8 & CPU1V2 on, WDIG off
{ PMU_IIC_BUS, kD1881_LCM_CONTROL1, 0x02 }, // PP5V1_GRAPE_VDDH 5.10V
{ PMU_IIC_BUS, kD1881_LCM_CONTROL2, 0x0E }, // PP5V7_LCD_AVDDH 5.70V
{ PMU_IIC_BUS, kD1881_LCM_CONTROL3, 0x00 }, // BB_VBUS_DET 5.00V
{ PMU_IIC_BUS, kD1881_LCM_BST_CONTROL, 0x1A }, // PP6V3_LCM_VBOOST 6.30V
};
static const struct pmu_setup_struct pmu_warm_init[] =
{
{ PMU_IIC_BUS, kDIALOG_ADC_CONTROL, kDIALOG_ADC_CONTROL_DEFAULTS },
};
static const struct pmu_setup_struct pmu_cold_init[] =
{
/* Note: the following differences from OTP are intentional:
- GPIO 5: Enable CLK32k
- GPIO 8: Enable Codec (Mikey) Wake
- GPIO 7: Enable WiFi Wake
- GPIO 10: Enable Wake amd Pull-Up
*/
{ PMU_IIC_BUS, kD1881_SYS_GPIO_1, 0xB9 }, // CLK32K_GRAPE In, R Edge, No Wake, No PU
// Clock is enabled by AppleARMFunction default
{ PMU_IIC_BUS, kD1881_SYS_GPIO_2, 0x09 }, // BB_WAKE_AP -- NC
{ PMU_IIC_BUS, kD1881_SYS_GPIO_3, 0x09 }, // BB_PMU_FET_ON -- NC
{ PMU_IIC_BUS, kD1881_SYS_GPIO_4, 0xBA }, // TRISTAR_INT In, R Edge, Wake, No PU
{ PMU_IIC_BUS, kD1881_SYS_GPIO_5, 0x49 }, // CLK32K_WIFI Out 0, Push-Pull, VBUCK3
{ PMU_IIC_BUS, kD1881_SYS_GPIO_6, 0x09 }, // BATTERY_SWI -- NC
{ PMU_IIC_BUS, kD1881_SYS_GPIO_7, 0xBB }, // WLAN_HOST_WAKE In, R Edge, Wake, PD, No PU
{ PMU_IIC_BUS, kD1881_SYS_GPIO_8, 0xEA }, // CODEC_HOST_WAKE_L In, Any Edge, Wake, PU, VBUCK3
{ PMU_IIC_BUS, kD1881_SYS_GPIO_9, 0x09 }, // BT_REG_ON Out 1, Push-Pull, VBUCK3
{ PMU_IIC_BUS, kD1881_SYS_GPIO_10, 0xBA }, // BT_HOST_WAKE In, R Edge, Wake, PU
{ PMU_IIC_BUS, kD1881_SYS_GPIO_11, 0x09 }, // WIFI_REG_ON Out 0, Push-Pull, VBUCK3
{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB1, 0x12 },
{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB2, 0x02 },
{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB3, 0x12 },
{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB4, 0x00 },
{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB5, 0x12 },
{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB6, 0x02 },
{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2, 0x10 }, // enable HIB_32kHz (for WIFI/BT); DWI disabled
// <rdar://problem/12192156> turn off buck4 negative current limit
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x01 }, // set bank1
{ PMU_IIC_BUS, kD1881_TEST_MODE, 0x01 }, // enter test mode
{ PMU_IIC_BUS, 0xCB, 0x23 }, // turn off negative current limit
{ PMU_IIC_BUS, kD1881_TEST_MODE, 0x00 }, // exit test mode
{ PMU_IIC_BUS, kDIALOG_BANKSEL, 0x00 }, // set bank0
};
static const struct pmu_setup_struct pmu_backlight_enable[] =
{
{ PMU_IIC_BUS, kDIALOG_WLED_ISET, 0xC8 }, // 50% value from OS
{ PMU_IIC_BUS, kDIALOG_WLED_ISET2, 0x01 },
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, // enable LED Power
(kDIALOG_WLED_CONTROL_WLED_ENABLE2 | kDIALOG_WLED_CONTROL_WLED_ENABLE1 | kDIALOG_WLED_CONTROL_WLED_RAMP_EN) }
};
static const struct pmu_setup_struct pmu_backlight_disable[] =
{
{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, 0x0 } // disable LED power
};
static const struct core_rails_struct soc_rails[] =
{
{ PMU_IIC_BUS, 0, kDIALOG_BUCK0 }
};
static const struct core_rails_struct cpu_rails[] =
{
{ PMU_IIC_BUS, 0, kDIALOG_BUCK2 }
};
#endif /* POWERCONFIG_PMU_SETUP */
#define NO_BATTERY_VOLTAGE 2700
#define MIN_BOOT_BATTERY_VOLTAGE 3600
#define TARGET_BOOT_BATTERY_VOLTAGE 3700
#define TARGET_BOOT_BATTERY_CAPACITY 50
#define PRECHARGE_BACKLIGHT_LEVEL 824
#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
#if WITH_HW_TRISTAR
extern bool n78_get_e75(void);
#define TARGET_IGNORE_TRISTAR (!n78_get_e75())
#define TARGET_BRICKID_FULL_SCALE (5000 * (n78_get_e75() ? 1 : 3))
#else
#define TARGET_BRICKID_FULL_SCALE (5000 * 3) // H5P has resistor divider for USB monitor
#endif
#define ACC_PWR_LDO (6)
#endif
target/n78/include/target/uartconfig.h
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/*
* Copyright (C) 2010 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_UARTCONFIG_H
#define __TARGET_UARTCONFIG_H
/* define two debug serial ports */
#define DEBUG_SERIAL_PORT (1)
#endif
target/n78/include/target/usbconfig.h
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/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_USBCONFIG_H
#define __TARGET_USBCONFIG_H
#ifdef USBPHY_UOTGTUNE1
#undef USBPHY_UOTGTUNE1
#define USBPHY_UOTGTUNE1 (0x749)
#endif /* USBPHY_UOTGTUNE1 */
#ifdef USBPHY_UOTGTUNE2
#undef USBPHY_UOTGTUNE2
#define USBPHY_UOTGTUNE2 (0x2FF3)
#endif /* USBPHY_UOTGTUNE2 */
#endif /* __TARGET_USBCONFIG_H */
target/n78/init.c
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/*
* Copyright (C) 2011-2015 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <debug.h>
#include <drivers/display.h>
#include <drivers/flash_nor.h>
#include <drivers/iic.h>
#include <drivers/power.h>
#include <lib/devicetree.h>
#include <lib/env.h>
#include <lib/mib.h>
#include <lib/syscfg.h>
#include <platform.h>
#include <platform/gpio.h>
#include <platform/gpiodef.h>
#include <platform/memmap.h>
#include <sys.h>
#include <sys/boot.h>
#include <sys/menu.h>
#include <sys/task.h>
#include <target.h>
#include <target/powerconfig.h>
// BRD_REV3 is pulled down to 0 until EVT3, but we are inverting its value
#define N78_PROTO0A_BOARD (15)
#define N78_PROTO0B_BOARD (13)
#define N78_PROTO1_BOARD (12)
#define N78_EVT1_BOARD (9)
#define N78_EVT2_BOARD (8)
// Starting with EVT3, BRD_REV3 is pulled up to 1, but we are inverting its value
#define N78_EVT3_BOARD (7)
static u_int32_t n78_get_board_rev(void);
static uint32_t display_config;
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
void target_early_init(void)
{
}
void target_late_init(void)
{
}
void target_init(void)
{
#if WITH_HW_FLASH_NOR
flash_nor_init(SPI_NOR0);
#endif
// <rdar://problem/11625584> N78 LDO7 needs to be off for units older than EVT3
// NOTE: A board is EARLIER than an EVT3, because its board ID is larger (according to #defines above)
if (n78_get_board_rev() > N78_EVT3_BOARD) {
unsigned int i;
const uint8_t pmu_data[] = {
0x21, 0xB3, // kD1881_ACTIVE2: LDO4, LDO5, LDO8, LDO9, LDO11 enabled
};
for (i = 0; i < sizeof(pmu_data); i += 2)
iic_write(0, 0xe8, &pmu_data[i], 2);
}
}
void target_quiesce_hardware(void)
{
}
void target_poweroff(void)
{
}
int target_bootprep(enum boot_target target)
{
switch (target) {
case BOOT_DARWIN:
case BOOT_DARWIN_RESTORE:
case BOOT_DIAGS:
break;
default:
; // do nothing
}
return 0;
}
bool target_should_recover(void)
{
return platform_get_request_dfu2() && power_has_usb();
}
bool target_should_poweron(bool *cold_button_boot)
{
#if WITH_HW_POWER
if (power_get_boot_flag() == kPowerBootFlagColdButton) *cold_button_boot = true;
#else
*cold_button_boot = false;
#endif
return !*cold_button_boot || platform_get_request_dfu1();
}
bool target_should_poweroff(bool at_boot)
{
return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
}
#if APPLICATION_IBOOT
void target_watchdog_tickle(void)
{
u_int32_t value = gpio_read(GPIO_WDOG_TICKLE);
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
}
#endif // APPLICATION_IBOOT
void * target_get_display_configuration(void)
{
display_config = 0x00000964;
return ((void *)(&display_config));
}
#if WITH_ENV
void target_setup_default_environment(void)
{
env_set("boot-device", "nand0", 0);
env_set("display-color-space","RGB888", 0);
env_set("display-timing", "n41", 0);
}
bool n78_get_e75(void)
{
return env_get_uint("e75", n78_get_board_rev() != N78_PROTO0A_BOARD) != 0;
}
#endif
static bool gpio_board_rev_valid;
static u_int32_t gpio_board_rev;
static u_int32_t n78_get_board_rev(void)
{
if (!gpio_board_rev_valid) {
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_IN);
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PDN);
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PDN);
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PDN);
gpio_configure_pupdn(GPIO_BOARD_REV3, GPIO_PDN);
spin(100); // Wait 100us
uint32_t brd_rev3_inverted = (gpio_read(GPIO_BOARD_REV3) ? 0UL : 1UL);
gpio_board_rev =
(brd_rev3_inverted << 3) |
(gpio_read(GPIO_BOARD_REV2) << 2) |
(gpio_read(GPIO_BOARD_REV1) << 1) |
(gpio_read(GPIO_BOARD_REV0) << 0);
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_DFLT);
gpio_board_rev_valid = true;
}
return gpio_board_rev;
}
#if WITH_DEVICETREE
int target_update_device_tree(void)
{
#if WITH_HW_DISPLAY_PINOT
DTNode *clcd_node, *backlight_node;
#endif
DTNode *node;
uint32_t propSize, propCnt;
char *propName;
void *propData;
// Update the DWI node with the actual voltages
if (FindNode(0, "arm-io/dwi", &node)) {
propName = "voltages-buck2";
if (FindProperty(node, &propName, &propData, &propSize)) {
propCnt = propSize / sizeof(u_int32_t);
platform_get_cpu_voltages(propCnt, propData);
platform_convert_voltages(2, propCnt, propData);
}
propName = "voltages-buck0";
if (FindProperty(node, &propName, &propData, &propSize)) {
propCnt = propSize / sizeof(u_int32_t);
platform_get_soc_voltages(propCnt, propData);
platform_convert_voltages(0, propCnt, propData);
}
}
#if WITH_HW_DISPLAY_PINOT
// Find the CLCD node
FindNode(0, "arm-io/clcd", &clcd_node);
if (FindNode(0, "arm-io/mipi-dsim/lcd", &node)) {
extern int pinot_update_device_tree(DTNode *pinot_node, DTNode *clcd_node, DTNode *backlight_node);
FindNode(0, "backlight", &backlight_node);
pinot_update_device_tree(node, clcd_node, backlight_node);
}
#endif
// Update the backlight calibration data
if (FindNode(0, "backlight", &node)) {
propName = "backlight-calibration";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('BLCl', propData, propSize);
}
}
// Update als node with calibration data
if (FindNode(0, "arm-io/i2c2/als", &node)) {
propName = "backlight-leakage-channel0";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('ALC0', propData, propSize);
}
propName = "backlight-leakage-channel1";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('ALC1', propData, propSize);
}
propName = "alsCalibration";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('AlsC', propData, propSize);
}
}
// Update the gyro calibration data
if (FindNode(0, "arm-io/i2c2/gyro", &node)) {
propName = "low-temp-offset";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('LTGO', propData, propSize);
}
propName = "high-temp-offset";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('HTGO', propData, propSize);
}
propName = "gyro-sensitivity-calibration";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('GSCl', propData, propSize);
}
propName = "gyro-temp-table";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('GYTT', propData, propSize);
}
propName = "gyro-interrupt-calibration";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('GICl', propData, propSize);
}
}
// Update accelerometer calibration data
if (FindNode(0, "arm-io/i2c2/accelerometer", &node)) {
propName = "low-temp-accel-offset";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('LTAO', propData, propSize);
}
propName = "accel-sensitivity-calibration";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('ASCl', propData, propSize);
}
propName = "accel-interrupt-calibration";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('AICl', propData, propSize);
}
}
// Updte the speaker calibration data
if (FindNode(0, "arm-io/i2c0/audio-speaker", &node)) {
propName = "speaker-rdc";
if (FindProperty(node, &propName, &propData, &propSize)) {
syscfgCopyDataForTag('SRdc', propData, propSize);
}
propName = "speaker-config";
if (FindProperty(node, &propName, &propData, &propSize)) {
uint8_t vpbr;
if (syscfgCopyDataForTag('VPBR', &vpbr, sizeof(vpbr)) == 1) {
((uint8_t *)propData)[12] = (((uint8_t *)propData)[12] & ~0x1f) | (vpbr & 0x1f);
}
uint8_t vbst;
if (syscfgCopyDataForTag('VBST', &vbst, sizeof(vbst)) == 1) {
((uint8_t *)propData)[16] = vbst;
}
}
}
if (FindNode(0, "product", &node)) {
// N78a: If the NoBC syscfg key present, and it have bit 0 set
uint32_t sysCfgData;
int result = syscfgCopyDataForTag('NoBC', (uint8_t *)(&sysCfgData), sizeof(sysCfgData));
int isn78a = 0;
if (result == sizeof(sysCfgData) && (sysCfgData & 0x1) ) isn78a = 1;
// this isn't an N78a, so get rid of the n78a-mode property
propName = "n78a-mode";
if (isn78a==0 && FindProperty(node, &propName, &propData, &propSize) ) propName[0] = '~';
if (isn78a && FindNode(0, "product/camera", &node)) {
// isp/camera-rear and other product/camera rear camera related properties
// will be deleted by common code in lib/macho/dt.c.
// Here, remove the product/camera/auto-focus entry
propName = "auto-focus";
if (FindProperty(node, &propName, &propData, &propSize) ) {
propName[0] = '~';
}
propName = "rear-hdr-on";
if (FindProperty(node, &propName, &propData, &propSize) ) {
//n78a: set rear-hdr-on to 0
memset(propData, 0, propSize );
}
propName = "rear-burst-image-duration";
if (FindProperty(node, &propName, &propData, &propSize) ) {
//n78a: set rear-burst-image-duration to 0
memset(propData, 0, propSize );
}
}
}
// if E75 config, reconfigure everything
if (n78_get_e75()) {
// enable uart2
if (FindNode(0, "arm-io/uart2", &node)) {
propName = "AAPL,ignore";
if (FindProperty(node, &propName, &propData, &propSize)) {
propName[0] = '~';
}
}
// reconfigure uart1
if (FindNode(0, "arm-io/uart1/iap", &node)) {
propName = "name";
if (FindProperty(node, &propName, &propData, &propSize)) {
strlcpy(propData, "debug-console", kPropNameLength);
}
propName = "function-dock_parent";
if (FindProperty(node, &propName, &propData, &propSize)) {
propName[0] = '~';
}
}
// enable tristar
uint32_t tristarPHandle = -1;
if (FindNode(0, "arm-io/i2c0/tristar", &node)) {
propName = "AAPL,ignore";
if (FindProperty(node, &propName, &propData, &propSize)) {
propName[0] = '~';
}
propName = "AAPL,phandle";
if (FindProperty(node, &propName, &propData, &propSize)) {
tristarPHandle = *(uint32_t *)propData;
}
}
// disconnect BRICK_ID from USB
if (FindNode(0, "arm-io/otgphyctrl", &node)) {
propName = "function-dmon_voltage";
if (FindProperty(node, &propName, &propData, &propSize)) {
propName[0] = '~';
}
}
// change dock from 30-pin to 9-pin
uint32_t dockPHandle = -1;
if (FindNode(0, "dock", &node)) {
propName = "compatible";
if (FindProperty(node, &propName, &propData, &propSize)) {
strlcpy(propData, "dock,9pin", kPropNameLength);
}
propName = "function-read_acc";
if (FindProperty(node, &propName, &propData, &propSize)) {
propName[0] = '~';
}
propName = "function-acc_detect";
if (FindProperty(node, &propName, &propData, &propSize)) {
propName[0] = '~';
}
propName = "interrupt-parent";
if (FindProperty(node, &propName, &propData, &propSize)) {
propName[0] = '~';
}
propName = "interrupts";
if (FindProperty(node, &propName, &propData, &propSize)) {
propName[0] = '~';
}
propName = "AAPL,phandle";
if (FindProperty(node, &propName, &propData, &propSize)) {
dockPHandle = *(uint32_t *)propData;
}
}
// use TriStar for brick detect
if (FindNode(0, "charger", &node)) {
propName = "function-usb_dmonitor";
if (FindProperty(node, &propName, &propData, &propSize)) {
((uint32_t *)propData)[0] = tristarPHandle;
}
}
}
// pre-EVT1 Grape clock config
if (n78_get_board_rev() > N78_EVT1_BOARD) {
if (FindNode(0, "arm-io/spi1/multi-touch", &node)) {
propName = "function-clock_enable";
if (FindProperty(node, &propName, &propData, &propSize)) {
propName[0] = '~';
}
propName = "function-clock_enable-pmu";
if (FindProperty(node, &propName, &propData, &propSize)) {
propName[21] = '\0';
}
}
// configure PMU GPIO1 to be Grape clock (off until enabled)
// configure SoC PWM2 to be disabled
power_gpio_configure(0, 0x09);
gpio_configure(GPIO(7, 7), GPIO_CFG_IN);
}
// pre-EVT2 codec config
if (n78_get_board_rev() > N78_EVT2_BOARD) {
if (FindNode(0, "arm-io/spi2/audio-codec", &node)) {
propName = "class-h-control";
if (FindProperty(node, &propName, &propData, &propSize)) {
((uint32_t *)propData)[0] = 0;
}
}
}
return 0;
}
#endif
target/n78/pinconfig.c
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/*
* Copyright (C) 2009-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <drivers/apple/gpio.h>
#include <platform/soc/hwregbase.h>
#include <target.h>
#define PIN_CFG_AP 1
#include <target/pinconfig.h>
#undef PIN_CFG_AP
#define PIN_CFG_DEV 1
#include <target/pinconfig.h>
#undef PIN_CFG_DEV
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
{
if (target_config_ap())
return gpio_default_cfg_ap;
else
return gpio_default_cfg_dev;
}
target/n78/rules.mk
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# Copyright (C) 2010-2012 Apple Inc. All rights reserved.
#
# This document is the property of Apple Inc.
# It is considered confidential and proprietary.
#
# This document may not be reproduced or transmitted in any form,
# in whole or in part, without the express written permission of
# Apple Inc.
#
LOCAL_DIR := $(GET_LOCAL_DIR)
TARGET_DIR := $(LOCAL_DIR)
OPTIONS += \
DIALOG_D1881=1 \
TARGET_HIGH_SOC_VOLTAGE=CHIPID_SOC_VOLTAGE_MED \
TARGET_HIGH_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_MED \
TARGET_CPU_SOURCE=2 \
TARGET_MIPI_DSI_SOURCE=1 \
TARGET_MANAGED2H_SOURCE=0 \
TARGET_MANAGED2L_SOURCE=0 \
TARGET_MANAGED2H_DIV=1 \
TARGET_MANAGED2L_DIV=2 \
TARGET_PCLK1_SOURCE=1 \
TARGET_PCLK1_DIV=4 \
TARGET_GFX_SOURCE=2 \
TARGET_GFX_SLC_SOURCE=3 \
TARGET_IOP_SOURCE=3 \
TARGET_LPERFS_SOURCE=3 \
TARGET_HPERFNRT_SOURCE=0 \
TARGET_USE_HSIC=1 \
TARGET_DSIM_CONFIG=0x00400000 \
TARGET_DSIM_DPHYCTL=0x30 \
TARGET_DSIM_SUPPRESS=0x1 \
AMC_NUM_CHANNELS=2 \
AMC_NUM_RANKS=1 \
AMC_CHANNEL_WIDTH=4 \
MULTITOUCH_DTPATH=\"arm-io/spi1/multi-touch\" \
WIFI_DTPATH=\"arm-io/usb-complex/usb-ehci/wlan\" \
WITH_TARGET_USB_CONFIG=1
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
ALL_OBJS += $(LOCAL_DIR)/init.o \
$(LOCAL_DIR)/pinconfig.o