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@@ -0,0 +1,46 @@
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/*
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* Copyright (C) 2010-2011 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* N94 specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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#define GPIO_LCD_RST GPIO( 2, 6)
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#define GPIO_LCD_RST_POLARITY (0)
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#define GPIO_LCD_CHKSUM GPIO( 2, 7)
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#define GPIO_RINGER_AB GPIO( 0, 4)
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/* Board Revision */
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#define GPIO_BOARD_REV0 GPIO( 5, 0)
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#define GPIO_BOARD_REV1 GPIO( 5, 1)
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#define GPIO_BOARD_REV2 GPIO( 5, 2)
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#define GPIO_BOARD_REV3 GPIO(27, 0)
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/* radio gpios */
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#define GPIO_WLAN_RESET GPIO( 0, 6)
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#define GPIO_BT_RESET GPIO( 1, 0)
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#define POWER_GPIO_BATTERY_SWI (5)
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#define POWER_GPIO_BATTERY_SWI_CONFIG_OUTPUT 0x03
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#define POWER_GPIO_BATTERY_SWI_CONFIG_INPUT 0xD8
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/* which IICs to initialize */
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#define IICS_MASK (7)
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/* D1881 watchdog tickle, 'KEEPACT' */
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#define GPIO_WDOG_TICKLE GPIO(2, 3)
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,92 @@
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// Copyright (C) 2008-2010 Apple, Inc. All rights reserved.
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//
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// This document is the property of Apple, Inc.
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// It is considered confidential and proprietary.
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//
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// This document may not be reproduced or transmitted in any form,
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// in whole or in part, without the express written permission of
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// Apple, Inc.
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//
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// NOTE: This is a generated file and should not be hand-edited!
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//
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// =============================================================================
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// Nand Geometry Table
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static NandGeometry _nandGeometryTable[] =
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{
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};
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// =============================================================================
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// Nand Timing Table
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static NandTiming _nandTimingTable[] =
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{
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};
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#if (defined (AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
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// =============================================================================
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// NandChipId Description
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const NandChipIdDescription _nandChipIdDescriptionTable[] =
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{
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};
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// =============================================================================
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// Nand Description Table
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static const NandDescription _nandDescriptionTable[] =
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{
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};
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const UInt32 _nandDescriptionTableSize = sizeof(_nandDescriptionTable) / sizeof(NandDescription);
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#endif // (defined(AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
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// =============================================================================
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// Nand Board Support Table
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static NandBoardSupport _nandBoardSupportTable[] =
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{
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};
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// =============================================================================
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// Nand Board Timing Table
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static NandBoardInfo _nandBoardInfo =
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{
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/* controlDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* dataDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* chipEnableDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* socToNandRiseNanosecs */ 10,
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/* socToNandFallNanosecs */ 10,
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/* nandToSocRiseNanosecs */ 10,
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/* nandToSocFallNanosecs */ 10,
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/* landing map */
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{
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0x00000F0F
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},
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/* useToggleMode */ FALSE32,
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/* useDiffDQSMode */ FALSE32,
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/* useDiffREMode */ FALSE32,
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/* useVref */ FALSE32,
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/* useSingleHostChannel */ FALSE32,
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/* allowSingleChipEnable */ TRUE32
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};
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static NandFormat _nandFormatPpn =
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{
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/* metaPerLogicalPage */ 16,
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/* validMetaPerLogicalPage */ 16,
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/* logicalPageSize */ 4096
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};
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static NandFormat _nandFormatRaw =
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{
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/* metaPerLogicalPage */ 12,
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/* validMetaPerLogicalPage */ 10,
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/* logicalPageSize */ 0
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};
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@@ -0,0 +1,129 @@
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/*
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* Copyright (C) 2010-2011 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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/* configuration per target */
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#define PMU_IIC_BUS 0
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/* this configuration is very PMU specific and must be included exactly once in power.c */
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#ifdef POWERCONFIG_PMU_SETUP
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/* Matched to D1881A3-OTP-AO-v4 */
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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{ PMU_IIC_BUS, kD1881_LDO1, 0x0D }, // PP3V0_USB 3.15V <rdar://problem/9200307>
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{ PMU_IIC_BUS, kD1881_LDO2, 0x0A }, // PP1V7_VA_VCP 1.70V
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{ PMU_IIC_BUS, kD1881_LDO3, 0x0A }, // PP3V0_IMU 3.00V
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{ PMU_IIC_BUS, kD1881_LDO4, 0x18 }, // PP3V0_OPTICAL 3.00V
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{ PMU_IIC_BUS, kD1881_LDO5, 0x0A }, // PP3V0_NAND 3.00V
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{ PMU_IIC_BUS, kD1881_LDO6, 0x10 }, // PP3V3_ACC 3.30V
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{ PMU_IIC_BUS, kD1881_LDO7, 0x0F }, // PP3V3_VIDEO 3.00V
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{ PMU_IIC_BUS, kD1881_LDO8, 0x14 }, // PP3V0_USBMUX 3.00V
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{ PMU_IIC_BUS, kD1881_LDO9, 0x12 }, // PP3V0_IO 3.00V
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{ PMU_IIC_BUS, kD1881_LDO10, 0x06 }, // PP2V8_CAM_AVDD 2.80V
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{ PMU_IIC_BUS, kD1881_LDO11, 0x16 }, // PP2V8_CAM_AF 2.80V
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{ PMU_IIC_BUS, kD1881_LDO12, 0x14 }, // PP1V1 1.10V
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{ PMU_IIC_BUS, kDIALOG_LDO_CONTROL, 0x00 }, // no bypass
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD1881_ACTIVE1, 0xFD }, // Everything except VBUCK1
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{ PMU_IIC_BUS, kD1881_ACTIVE2, 0xFB }, // Everything except LDO6
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{ PMU_IIC_BUS, kD1881_ACTIVE3, 0x2B }, // WLED_BST, LCM_BST, LDO_LCM2, LDO12
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{ PMU_IIC_BUS, kD1881_ACTIVE4, 0xA0 }, // CPU1V8 & CPU1V2 on, WDIG off
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{ PMU_IIC_BUS, kD1881_LCM_CONTROL1, 0x02 }, // PP5V1_GRAPE_VDDH 5.10V
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{ PMU_IIC_BUS, kD1881_LCM_CONTROL2, 0x0E }, // PP5V7_LCD_AVDDH 5.70V
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{ PMU_IIC_BUS, kD1881_LCM_CONTROL3, 0x00 }, // BB_VBUS_DET 5.00V
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{ PMU_IIC_BUS, kD1881_LCM_BST_CONTROL, 0x14 }, // PP6V0_LCM_VBOOST 6.00V
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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{ PMU_IIC_BUS, kDIALOG_ADC_CONTROL, kDIALOG_ADC_CONTROL_DEFAULTS },
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};
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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{ PMU_IIC_BUS, kDIALOG_BUCK_CONTROL1, 0x0a }, // buck0 sync mode, 1.25A limit per phase
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{ PMU_IIC_BUS, kDIALOG_BUCK_CONTROL3, 0x0e }, // buck2 sync mode, 1.55A limit per phase
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/* Note: the following differences from OTP are intentional:
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- GPIO2,6,7,8,10 enable wake
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- GPIO5 enables CLK32
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- GPIO8 interrupt type
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- GPIO9 asserted
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- GPIO6,8 no debounce
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*/
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_1, 0x11 }, // CLK32K_GRAPE Out 0, Push-Pull, CPU_1V8
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// Clock is enabled by AppleARMFunction default
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_2, 0xBA }, // BB_WAKE_AP In, R Edge, Wake, No PU or PD
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_3, 0x09 }, // BB_PMU_FET_ON Out 0, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_4, 0x09 }, // DOCK_BB_USB_SEL Out 0, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_5, 0x49 }, // CLK32K_WIFI Out 0, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_6, 0xDA }, // BATTERY_SWI In, F Edge, Out Hib, Wake, PD, No PU
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_7, 0xBB }, // WLAN_WAKE_AP In, R Edge, Wake, PD, No PU
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_8, 0xEA }, // MIKEY_INT_L In, Any Edge, Wake, PU, VBUCK3
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_9, 0x0B }, // BT_REG_ON Out 1, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_10, 0xBB }, // BT_WAKE_AP In, R Edge, Wake, PD, No PU
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_11, 0x09 }, // WIFI_REG_ON Out 0, Push-Pull, VBUCK3
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB1, 0x12 },
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB2, 0x12 },
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB3, 0x02 },
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB4, 0x02 },
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB5, 0x12 },
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{ PMU_IIC_BUS, kD1881_SYS_GPIO_DEB6, 0x02 },
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{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2, 0x10 }, // enable HIB_32kHz (for WIFI/BT); DWI disabled
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};
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static const struct pmu_setup_struct pmu_backlight_enable[] =
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{
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{ PMU_IIC_BUS, kDIALOG_WLED_ISET, 0xC8 }, // 50% value from OS
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{ PMU_IIC_BUS, kDIALOG_WLED_ISET2, 0x01 },
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{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, // enable LED Power
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(kDIALOG_WLED_CONTROL_WLED_ENABLE1 | kDIALOG_WLED_CONTROL_WLED_RAMP_EN |
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kDIALOG_WLED_CONTROL_WLED_DITH_EN) }
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};
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static const struct pmu_setup_struct pmu_backlight_disable[] =
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{
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{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, 0x0 } // disable LED power
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};
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static const struct core_rails_struct soc_rails[] =
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{
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{ PMU_IIC_BUS, 0, kDIALOG_BUCK2 }
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};
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static const struct core_rails_struct cpu_rails[] =
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{
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{ PMU_IIC_BUS, 0, kDIALOG_BUCK0 }
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};
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#endif /* POWERCONFIG_PMU_SETUP */
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#define NO_BATTERY_VOLTAGE 2700
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#define MIN_BOOT_BATTERY_VOLTAGE 3600
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#define TARGET_BOOT_BATTERY_VOLTAGE 3700
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#define TARGET_BOOT_BATTERY_CAPACITY 50
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#define PRECHARGE_BACKLIGHT_LEVEL 824
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#define TARGET_DISPLAY_VOLTAGE_BASE 6000
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#define TARGET_DISPLAY_VOLTAGE_SCALE 50
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#define TARGET_DISPLAY_BOOST_LDO kD1881_LCM_CONTROL2
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#define TARGET_DISPLAY_BOOST_OFFSET 300
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#endif
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@@ -0,0 +1,25 @@
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/*
|
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* Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
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#ifndef __TARGET_RADIOCONFIG_H
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#define __TARGET_RADIOCONFIG_H
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/* configuration per target */
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#define RADIO_VERIFY_BASEBAND_EXISTS 1
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static const gpio_t target_radio_quiesce_pins[] =
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{
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GPIO_UART1_TXD
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};
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#define RADIO_ENABLE_IMEI_OVERRIDE 0
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#endif /* ! __TARGET_RADIOCONFIG_H */
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@@ -0,0 +1,26 @@
|
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/*
|
||||
* Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
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#define __TARGET_UARTCONFIG_H
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/* define two debug serial ports */
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#define DEBUG_SERIAL_PORT (0)
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/* define radio serial port */
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#define RADIO_SERIAL_PORT (1)
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#define RADIO_MAX_READ_ERRORS (10)
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/* define HDQ serial port */
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#define HDQGAUGE_SERIAL_PORT (5)
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||||
#define UART_FLOWCONTROL_MASK (0x08)
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#endif
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@@ -0,0 +1,443 @@
|
||||
/*
|
||||
* Copyright (C) 2010-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
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#include <drivers/display.h>
|
||||
#include <drivers/flash_nor.h>
|
||||
#include <drivers/iic.h>
|
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#include <drivers/power.h>
|
||||
#include <lib/devicetree.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <lib/syscfg.h>
|
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#include <platform.h>
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#include <platform/gpio.h>
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||||
#include <platform/gpiodef.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <sys.h>
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#include <sys/boot.h>
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||||
#include <sys/menu.h>
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#include <sys/task.h>
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||||
#include <target.h>
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// These are sequential revision numbers, reordered from the hardware straps
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||||
#define N94_ILLEGAL_BOARD (255)
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#define N94_PROTO1_BOARD (10)
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#define N94_PROTO1a_BOARD (9)
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#define N94_PROTO2_BOARD (8)
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||||
#define N94_PROTO3_BOARD (7)
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||||
#define N94_PROTO3a_BOARD (6)
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||||
#define N94_EVT1_BOARD (5)
|
||||
#define N94_EVT1a_BOARD (4)
|
||||
#define N94_EVT2_BOARD (3)
|
||||
#define N94_DVT_BOARD (2)
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||||
#define N94_PVT_BOARD (1)
|
||||
#define N94_PRQ_BOARD (0)
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||||
|
||||
// Convert the 4-bit hardware board rev to a monotonic software rev
|
||||
static u_int8_t hw_rev_to_sw[] = {
|
||||
N94_PRQ_BOARD,
|
||||
N94_DVT_BOARD,
|
||||
N94_EVT1_BOARD,
|
||||
N94_PROTO3a_BOARD, // also DEV3a, N78 D300 DEV
|
||||
N94_PROTO3_BOARD, // also PreProto3, DEV3
|
||||
N94_PROTO2_BOARD,
|
||||
N94_PROTO1_BOARD, // and DEV2
|
||||
N94_PROTO1a_BOARD, // and DEV1
|
||||
N94_PVT_BOARD,
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||||
N94_ILLEGAL_BOARD,
|
||||
N94_ILLEGAL_BOARD,
|
||||
N94_ILLEGAL_BOARD,
|
||||
N94_ILLEGAL_BOARD,
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||||
N94_ILLEGAL_BOARD,
|
||||
N94_EVT2_BOARD, // and DEV4 (probably)
|
||||
N94_EVT1a_BOARD,
|
||||
};
|
||||
|
||||
static u_int32_t n94_get_board_rev(void);
|
||||
|
||||
static u_int32_t display_config;
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
// OTP-AO matching code for TellurideNanshan DVT: <rdar://problem/9876366>
|
||||
if (N94_DVT_BOARD == n94_get_board_rev()) {
|
||||
uint8_t pmu_setup[][2] = {
|
||||
// buck0 and buck2 controls are set in powerconfig.h for all revs
|
||||
{ 0x18, 0x01 }, // BANKSEL=1
|
||||
{ 0xe0, 0x01 }, // Enable test mode
|
||||
{ 0xa9, 0x48 }, // 0us blanking time
|
||||
{ 0xd2, 0x33 }, // 0-180 phasing
|
||||
{ 0xa3, 0xa2 }, // reduce charger headroom by 50mV
|
||||
{ 0xe0, 0x00 }, // Disable test mode
|
||||
{ 0x18, 0x00 }, // BANKSEL=0
|
||||
};
|
||||
int entries = sizeof(pmu_setup) / (2*sizeof(uint8_t)), index;
|
||||
for (index = 0; index < entries; index++)
|
||||
iic_write(0, 0xe8, pmu_setup[index], 2);
|
||||
}
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
if (target_config_dev()) {
|
||||
if (n94_get_board_rev() >= N94_PROTO2_BOARD)
|
||||
platform_not_supported();
|
||||
} else {
|
||||
if (n94_get_board_rev() >= N94_EVT1_BOARD)
|
||||
platform_not_supported();
|
||||
}
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
|
||||
// All AP and PMU GPIOS for the radios are set by pinconfig.h
|
||||
// and powerconfig.h. While the AP settings are compatible with wake,
|
||||
// the BB PMU will be in reset thanks to powerconfig.h providing
|
||||
// dedicated cold boot settings. The AppleARMFunctions in the device
|
||||
// tree will take care of the rest for a cold boot.
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
switch (target) {
|
||||
case BOOT_DARWIN:
|
||||
case BOOT_DARWIN_RESTORE:
|
||||
case BOOT_DIAGS:
|
||||
break;
|
||||
|
||||
default:
|
||||
; // do nothing
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return platform_get_request_dfu2() && power_has_usb();
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
#if WITH_HW_POWER
|
||||
if (power_get_boot_flag() == kPowerBootFlagColdButton) *cold_button_boot = true;
|
||||
#else
|
||||
*cold_button_boot = false;
|
||||
#endif
|
||||
|
||||
return !*cold_button_boot || platform_get_request_dfu1();
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
void target_watchdog_tickle(void)
|
||||
{
|
||||
u_int32_t value = gpio_read(GPIO_WDOG_TICKLE);
|
||||
gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
|
||||
}
|
||||
#endif // APPLICATION_IBOOT
|
||||
|
||||
void * target_get_display_configuration(void)
|
||||
{
|
||||
display_config = 0x00000963;
|
||||
return ((void *)(&display_config));
|
||||
}
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
env_set("boot-device", "nand0", 0);
|
||||
env_set("display-color-space","RGB888", 0);
|
||||
env_set("display-timing", "n94", 0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
u_int32_t target_lookup_backlight_cal(int index)
|
||||
{
|
||||
return (index == 2) ? 0x09 : 0;
|
||||
}
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
u_int32_t board_rev = n94_get_board_rev();
|
||||
|
||||
#if WITH_HW_DISPLAY_PINOT
|
||||
DTNode *clcd_node, *backlight_node;
|
||||
#endif
|
||||
DTNode *node;
|
||||
uint32_t propSize, propCnt;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
// Update the DWI node with the actual voltages
|
||||
if (FindNode(0, "arm-io/dwi", &node)) {
|
||||
propName = "voltages-buck0";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propCnt = propSize / sizeof(u_int32_t);
|
||||
platform_get_cpu_voltages(propCnt, propData);
|
||||
platform_convert_voltages(0, propCnt, propData);
|
||||
}
|
||||
propName = "voltages-buck2";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
propCnt = propSize / sizeof(u_int32_t);
|
||||
platform_get_soc_voltages(propCnt, propData);
|
||||
platform_convert_voltages(2, propCnt, propData);
|
||||
}
|
||||
}
|
||||
|
||||
#if WITH_HW_DISPLAY_PINOT
|
||||
// Find the CLCD node
|
||||
FindNode(0, "arm-io/clcd", &clcd_node);
|
||||
|
||||
if (FindNode(0, "arm-io/mipi-dsim/lcd", &node)) {
|
||||
extern int pinot_update_device_tree(DTNode *pinot_node, DTNode *clcd_node, DTNode *backlight_node);
|
||||
|
||||
FindNode(0, "backlight", &backlight_node);
|
||||
pinot_update_device_tree(node, clcd_node, backlight_node);
|
||||
}
|
||||
#endif
|
||||
|
||||
if (board_rev > N94_EVT1a_BOARD)
|
||||
{
|
||||
// old headset circutry
|
||||
if (FindNode(0, "arm-io/i2c0/headset-switch", &node)) {
|
||||
propName = "function-ext_switch";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
strlcpy(propName, "unused-ext_switch", kPropNameLength);
|
||||
}
|
||||
}
|
||||
if (FindNode(0, "arm-io/i2c0/audio0", &node)) {
|
||||
propName = "unused-hpout_ref_control";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
strlcpy(propName, "function-hpout_ref_control", kPropNameLength);
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (board_rev > N94_EVT1_BOARD)
|
||||
{
|
||||
// old headset circutry
|
||||
if (FindNode(0, "arm-io/i2c0/headset-switch", &node)) {
|
||||
propName = "switch-config";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
*(uint32_t *)propData = 0;
|
||||
}
|
||||
}
|
||||
if (FindNode(0, "arm-io/i2c0/audio0", &node)) {
|
||||
propName = "headphone-pop-workaround";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
*(uint32_t *)propData = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (board_rev > N94_DVT_BOARD)
|
||||
{
|
||||
if (FindNode(0, "arm-io/i2c0/headset-switch", &node)) {
|
||||
propName = "switch-config";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
*(uint32_t *)propData = 0x1a;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (board_rev > N94_PRQ_BOARD)
|
||||
{
|
||||
if (FindNode(0, "arm-io/i2c0/audio0", &node)) {
|
||||
propName = "headphone-pop-workaround";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
*(uint32_t *)propData |= 0x8;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (board_rev > N94_PROTO3a_BOARD) {
|
||||
// <rdar://problem/8777592>
|
||||
if (FindNode(0, "arm-io/dwi", &node)) {
|
||||
propName = "dwi-version";
|
||||
if (FindProperty(node, &propName, &propData, &propSize))
|
||||
((u_int32_t *)propData)[0] = 0;
|
||||
}
|
||||
// Pulldown on BB_WAKE_AP, removed for <rdar://problem/8929181>
|
||||
power_gpio_configure(1, 0xBB);
|
||||
}
|
||||
|
||||
// Update the highland-park node with acoustic transducer scale data
|
||||
if (FindNode(0, "arm-io/highland-park", &node)) {
|
||||
propName = "at-scale";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ATSc', propData, propSize);
|
||||
}
|
||||
}
|
||||
if (FindNode(0, "arm-io/i2c0/audio0", &node)) {
|
||||
propName = "at-scale";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ATSc', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the als calibration data
|
||||
if (FindNode(0, "arm-io/i2c1/als", &node)) {
|
||||
propName = "alsCalibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('AlsC', propData, propSize);
|
||||
}
|
||||
propName = "als-colorCfg";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ClrC', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the compass calibration data
|
||||
if (FindNode(0, "arm-io/i2c1/compass", &node)) {
|
||||
propName = "compass-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('CPAS', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the gyro calibration data
|
||||
if (FindNode(0, "arm-io/i2c2/gyro", &node)) {
|
||||
propName = "low-temp-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LTGO', propData, propSize);
|
||||
}
|
||||
propName = "high-temp-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('HTGO', propData, propSize);
|
||||
}
|
||||
propName = "gyro-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GSCl', propData, propSize);
|
||||
}
|
||||
propName = "gyro-temp-table";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GYTT', propData, propSize);
|
||||
}
|
||||
propName = "gyro-interrupt-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GICl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the gyro calibration data
|
||||
if (FindNode(0, "arm-io/i2c2/gyro1", &node)) {
|
||||
propName = "low-temp-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LTGO', propData, propSize);
|
||||
}
|
||||
propName = "high-temp-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('HTGO', propData, propSize);
|
||||
}
|
||||
propName = "gyro-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GSCl', propData, propSize);
|
||||
}
|
||||
propName = "gyro-temp-table";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GYTT', propData, propSize);
|
||||
}
|
||||
propName = "gyro-interrupt-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('GICl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update accelerometer calibration data
|
||||
if (FindNode(0, "arm-io/i2c2/accelerometer", &node)) {
|
||||
propName = "low-temp-accel-offset";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('LTAO', propData, propSize);
|
||||
}
|
||||
propName = "accel-sensitivity-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('ASCl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update prox calibration data
|
||||
if (FindNode(0, "arm-io/spi1/multi-touch", &node)) {
|
||||
propName = "prox-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('PxCl', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Update charger calibration data
|
||||
if (FindNode(0, "charger", &node)) {
|
||||
propName = "usb-input-limit-calibration";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
syscfgCopyDataForTag('CBAT', propData, propSize);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static u_int32_t n94_get_board_rev(void)
|
||||
{
|
||||
u_int32_t gpio_board_rev;
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_IN);
|
||||
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PDN);
|
||||
gpio_configure_pupdn(GPIO_BOARD_REV3, GPIO_PDN);
|
||||
|
||||
spin(100); // Wait 100us
|
||||
|
||||
gpio_board_rev =
|
||||
(gpio_read(GPIO_BOARD_REV3) << 3) |
|
||||
(gpio_read(GPIO_BOARD_REV2) << 2) |
|
||||
(gpio_read(GPIO_BOARD_REV1) << 1) |
|
||||
(gpio_read(GPIO_BOARD_REV0) << 0);
|
||||
|
||||
gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
|
||||
gpio_configure(GPIO_BOARD_REV3, GPIO_CFG_DFLT);
|
||||
|
||||
// Convert and sanity-check
|
||||
gpio_board_rev = hw_rev_to_sw[gpio_board_rev & 0xf];
|
||||
if (N94_ILLEGAL_BOARD == gpio_board_rev)
|
||||
panic("Illegal board revision");
|
||||
|
||||
return (gpio_board_rev);
|
||||
}
|
||||
@@ -0,0 +1,654 @@
|
||||
/*
|
||||
* Copyright (C) 2009-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <target.h>
|
||||
|
||||
/* Default N94 Hardware Pin Configuration - Proto3A */
|
||||
|
||||
#define BB_UART_DRIVE_STR DRIVE_X3
|
||||
#define UMTS_DRIVE_STR DRIVE_X3
|
||||
#define BT_UART_DRIVE_STR DRIVE_X3
|
||||
#define SWI_UART_DRIVE_STR DRIVE_X3
|
||||
#define GPS_UART_DRIVE_STR DRIVE_X3
|
||||
#define FMI_DRIVE_STR DRIVE_X3
|
||||
#define GRAPE_DRIVE_STR DRIVE_X3
|
||||
#define BB_SPI_DRIVE_STR DRIVE_X3
|
||||
#define I2C_DRIVE_STR DRIVE_X3
|
||||
#define CAM_CLK_DRIVE_STR DRIVE_X3
|
||||
#define I2S_DRIVE_STR DRIVE_X3
|
||||
#define DOCK_UART_DRIVE_STR DRIVE_X3
|
||||
#define IPC_DRIVE_STR DRIVE_X3
|
||||
|
||||
#define CAM_I2C_DRIVE_STR DRIVE_X2
|
||||
#define CAM_STROBE_DRIVE_STR DRIVE_X2
|
||||
#define DWI_DRIVE_STR DRIVE_X2
|
||||
#define NOR_DRIVE_STR DRIVE_X2
|
||||
|
||||
static const u_int32_t gpio_default_cfg_ap[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
/* Port 0 */
|
||||
CFG_IN, // GPIO0 -> MENU_KEY_BUFF_L (REQUEST_DFU2)
|
||||
CFG_IN, // GPIO1 -> HOLD_KEY_L (REQUEST_DFU1)
|
||||
CFG_IN | PULL_UP, // GPIO2 -> VOL_DWN_L
|
||||
CFG_IN | PULL_UP, // GPIO3 -> VOL_UP_L
|
||||
CFG_IN, // GPIO4 -> RINGER_A
|
||||
CFG_OUT_0, // GPIO5 -> SPKAMP_RESET_L
|
||||
CFG_DISABLED, // GPIO6 ->
|
||||
CFG_OUT_0, // GPIO7 -> BT_WAKE
|
||||
|
||||
/* Port 1 */
|
||||
CFG_OUT_1, // GPIO8 -> BT_RESET_L
|
||||
CFG_DISABLED, // GPIO9 ->
|
||||
CFG_IN, // GPIO10 -> BB_RESET_L
|
||||
CFG_IN | PULL_DOWN, // GPIO11 -> BB_RESET_DET_L
|
||||
CFG_IN | PULL_DOWN, // GPIO12 -> IPC_SRDY
|
||||
CFG_IN | PULL_UP, // GPIO13 -> PMU_IRQ_L
|
||||
CFG_IN, // GPIO14 -> RADIO_ON_L
|
||||
CFG_IN, // GPIO15 -> RESET_BB_PMU_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // GPIO16 -> BOARD_ID[3]
|
||||
CFG_IN | PULL_DOWN, // GPIO17 -> BB_HSIC_RDY
|
||||
CFG_DISABLED, // GPIO18 -> BOOT_CONFIG[0]
|
||||
CFG_OUT_0, // GPIO19 -> KEEPACT
|
||||
CFG_IN, // GPIO20 -> BB_EMERGENCY_DWLD_L
|
||||
CFG_IN | PULL_UP, // GPIO21 -> GRAPE_INT_L
|
||||
CFG_OUT_0, // GPIO22 -> LCD_RESET_L
|
||||
CFG_IN | PULL_UP, // GPIO23 -> LCD_HIFA
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // GPIO24 ->
|
||||
CFG_DISABLED, // GPIO25 -> BOOT_CONFIG[1]
|
||||
CFG_IN | PULL_DOWN, // GPIO26 -> FORCE_DFU
|
||||
CFG_DISABLED | PULL_DOWN, // GPIO27 -> DFU_STATUS
|
||||
CFG_DISABLED, // GPIO28 -> BOOT_CONFIG[2]
|
||||
CFG_DISABLED, // GPIO29 -> BOOT_CONFIG[3]
|
||||
CFG_IN | PULL_UP, // GPIO30 -> CODEC_INT_L
|
||||
CFG_IN, // GPIO31 -> WLAN_HSIC_RDY
|
||||
|
||||
/* Port 4 */
|
||||
CFG_IN | PULL_DOWN, // GPIO32 -> GYRO_INT2
|
||||
CFG_IN | PULL_DOWN, // GPIO33 -> GYRO_INT
|
||||
CFG_IN | PULL_DOWN, // GPIO34 -> COMPASS_BRD_INT
|
||||
CFG_DISABLED, // GPIO35 ->
|
||||
CFG_IN | PULL_UP, // GPIO36 -> ACCEL_INT1_L
|
||||
CFG_IN | PULL_UP, // GPIO37 -> ACCEL_INT2_L
|
||||
CFG_IN | PULL_UP, // GPIO38 -> ALS_INT_L
|
||||
CFG_OUT_0, // GPIO39 -> GRAPE_RESET_L
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED, // EHCI_PORT_PWR[0] -> BOARD_REV[0]
|
||||
CFG_DISABLED, // EHCI_PORT_PWR[1] -> BOARD_REV[1]
|
||||
CFG_DISABLED, // EHCI_PORT_PWR[2] -> BOARD_REV[2]
|
||||
CFG_IN | BB_UART_DRIVE_STR, // UART1_TXD -> (BB USART)
|
||||
CFG_FUNC0, // UART1_RXD ->
|
||||
CFG_FUNC0 | BB_UART_DRIVE_STR, // UART1_RTSN ->
|
||||
CFG_FUNC0, // UART1_CTSN ->
|
||||
CFG_OUT_0, // UART2_TXD -> HOST_WLAN_HSIC_RDY
|
||||
|
||||
/* Port 6 */
|
||||
CFG_IN, // UART2_RXD -> IPC_GPIO4
|
||||
CFG_DISABLED, // UART2_RTSN -> PMU_AMUX_AY_CTRL
|
||||
CFG_DISABLED, // UART2_CTSN -> PMU_AMUX_BY_CTRL
|
||||
CFG_FUNC0 | BT_UART_DRIVE_STR, // UART3_TXD -> (BT)
|
||||
CFG_FUNC0, // UART3_RXD ->
|
||||
CFG_OUT_1 | BT_UART_DRIVE_STR, // UART3_RTSN ->
|
||||
CFG_FUNC0, // UART3_CTSN ->
|
||||
CFG_FUNC0 | SWI_UART_DRIVE_STR, // UART5_RTXD -> BATTERY_SWI
|
||||
|
||||
/* Port 7 */
|
||||
CFG_OUT_0, // UART6_TXD -> HOST_BB_HSIC_RDY
|
||||
CFG_DISABLED, // UART6_RXD ->
|
||||
CFG_DISABLED, // UART6_RTSN ->
|
||||
CFG_DISABLED, // UART6_CTSN ->
|
||||
CFG_DISABLED, // UART4_TXD/SPI4_MOSI ->
|
||||
CFG_DISABLED, // UART4_RXD/SPI4_MISO ->
|
||||
CFG_DISABLED, // UART4_RTSN/SPI4_SCLK ->
|
||||
CFG_DISABLED, // UART4_CTSN/SPI4_SSIN ->
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN3 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN2 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN1 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN0 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CLE ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_ALE ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_REN ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_WEN ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO7 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO6 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO5 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO4 ->
|
||||
CFG_DISABLED | PULL_DOWN, // FMI0_DQS ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO3 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO2 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO1 ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO0 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN3 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN2 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN1 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN0 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CLE ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_ALE ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_REN ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_WEN ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO7 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO6 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO5 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO4 ->
|
||||
CFG_DISABLED | PULL_DOWN, // FMI1_DQS ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO3 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO2 ->
|
||||
|
||||
/* Port 12 */
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO1 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO0 ->
|
||||
CFG_DISABLED, // FMI2_CEN3 ->
|
||||
CFG_DISABLED, // FMI2_CEN2 ->
|
||||
CFG_DISABLED, // FMI2_CEN1 ->
|
||||
CFG_DISABLED, // FMI2_CEN0 ->
|
||||
CFG_DISABLED, // FMI2_CLE ->
|
||||
CFG_DISABLED, // FMI2_ALE ->
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // FMI2_REN ->
|
||||
CFG_DISABLED, // FMI2_WEN ->
|
||||
CFG_DISABLED, // FMI2_IO7 ->
|
||||
CFG_DISABLED, // FMI2_IO6 ->
|
||||
CFG_DISABLED, // FMI2_IO5 ->
|
||||
CFG_DISABLED, // FMI2_IO4 ->
|
||||
CFG_DISABLED, // FMI2_DQS ->
|
||||
CFG_DISABLED, // FMI2_IO3 ->
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // FMI2_IO2 ->
|
||||
CFG_DISABLED, // FMI2_IO1 ->
|
||||
CFG_DISABLED, // FMI2_IO0 ->
|
||||
CFG_DISABLED, // FMI0_CEN7 ->
|
||||
CFG_DISABLED, // FMI0_CEN6 ->
|
||||
CFG_DISABLED, // FMI0_CEN5 ->
|
||||
CFG_DISABLED, // FMI0_CEN4 ->
|
||||
CFG_DISABLED, // FMI1_CEN7 ->
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // FMI1_CEN6 ->
|
||||
CFG_DISABLED, // FMI1_CEN5 ->
|
||||
CFG_DISABLED, // FMI1_CEN4 ->
|
||||
CFG_DISABLED, // FMI3_CEN3 ->
|
||||
CFG_DISABLED, // FMI3_CEN2 ->
|
||||
CFG_DISABLED, // FMI3_CEN1 ->
|
||||
CFG_DISABLED, // FMI3_CEN0 ->
|
||||
CFG_DISABLED, // FMI3_CLE ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED, // FMI3_ALE ->
|
||||
CFG_DISABLED, // FMI3_REN ->
|
||||
CFG_DISABLED, // FMI3_WEN ->
|
||||
CFG_DISABLED, // FMI3_IO7 ->
|
||||
CFG_DISABLED, // FMI3_IO6 ->
|
||||
CFG_DISABLED, // FMI3_IO5 ->
|
||||
CFG_DISABLED, // FMI3_IO4 ->
|
||||
CFG_DISABLED, // FMI3_DQS ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // FMI3_IO3 ->
|
||||
CFG_DISABLED, // FMI3_IO2 ->
|
||||
CFG_DISABLED, // FMI3_IO1 ->
|
||||
CFG_DISABLED, // FMI3_IO0 ->
|
||||
CFG_DISABLED, // FMI2_CEN7 ->
|
||||
CFG_DISABLED, // FMI2_CEN6 ->
|
||||
CFG_DISABLED, // FMI2_CEN5 ->
|
||||
CFG_DISABLED, // FMI2_CEN4 ->
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED, // FMI3_CEN7 ->
|
||||
CFG_DISABLED, // FMI3_CEN6 ->
|
||||
CFG_DISABLED, // FMI3_CEN5 ->
|
||||
CFG_DISABLED, // FMI3_CEN4 ->
|
||||
CFG_DISABLED, // SPI3_MOSI ->
|
||||
CFG_DISABLED, // SPI3_MISO ->
|
||||
CFG_DISABLED, // SPI3_SCLK ->
|
||||
CFG_DISABLED, // SPI3_SSIN ->
|
||||
|
||||
/* Port 19 */
|
||||
CFG_OUT_0, // ISP0_PRE_FLASH -> CAM0_VDDCORE_EN
|
||||
CFG_OUT_0, // ISP0_FLASH -> CAM0_RESET_L
|
||||
CFG_DISABLED, // ISP1_PRE_FLASH ->
|
||||
CFG_OUT_0, // ISP1_FLASH -> CAM1_RESET_L
|
||||
CFG_FUNC0 | GRAPE_DRIVE_STR, // SPI1_SCLK -> SPI1_SCLK (GRAPE)
|
||||
CFG_FUNC0 | GRAPE_DRIVE_STR, // SPI1_MOSI -> SPI1_MOSI
|
||||
CFG_FUNC0, // SPI1_MISO -> SPI1_MISO
|
||||
CFG_OUT_1 | GRAPE_DRIVE_STR, // SPI1_SSIN -> SPI1_CS_L
|
||||
|
||||
/* Port 20 */
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_DISABLED, // SPI0_SCLK -> SPI0_SCLK/BOARD_ID[0]
|
||||
CFG_DISABLED, // SPI0_MOSI -> SPI0_MOSI/BOARD_ID[1]
|
||||
CFG_DISABLED, // SPI0_MISO -> SPI0_MISO/BOARD_ID[2]
|
||||
CFG_DISABLED, // SPI0_SSIN -> SPI0_SSIN
|
||||
CFG_DISABLED, // SPI2_SCLK ->
|
||||
CFG_DISABLED, // SPI2_MOSI ->
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // SPI2_MISO ->
|
||||
CFG_OUT_0 | BB_SPI_DRIVE_STR, // SPI2_SSIN -> SPI2_MRDY / IPC_MRDY
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_FUNC0 | CAM_I2C_DRIVE_STR, // ISP0_SDA ->
|
||||
CFG_FUNC0 | CAM_I2C_DRIVE_STR, // ISP0_SCL ->
|
||||
|
||||
/* Port 22 */
|
||||
CFG_FUNC0 | CAM_I2C_DRIVE_STR, // ISP1_SDA ->
|
||||
CFG_FUNC0 | CAM_I2C_DRIVE_STR, // ISP1_SCL ->
|
||||
CFG_DISABLED, // SDIO_CLK ->
|
||||
CFG_DISABLED, // SDIO_CMD ->
|
||||
CFG_DISABLED, // SDIO_DATA0 ->
|
||||
CFG_DISABLED, // SDIO_DATA1 ->
|
||||
CFG_DISABLED, // SDIO_DATA2 ->
|
||||
CFG_DISABLED, // SDIO_DATA3 ->
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED, // MIPI_VSYNC ->
|
||||
CFG_IN, // TMR32_PWM0 -> GYRO_INT2 (also GPIO32)
|
||||
CFG_IN, // TMR32_PWM1 -> ACCEL_INT2_L (also GPIO37)
|
||||
CFG_OUT_0 | CAM_STROBE_DRIVE_STR, // TMR32_PWM2 -> CAM_STROBE_EN
|
||||
CFG_DISABLED, // SWI_DATA ->
|
||||
CFG_FUNC0 | PULL_DOWN, // DWI_DI ->
|
||||
CFG_FUNC0 | DWI_DRIVE_STR, // DWI_DO ->
|
||||
CFG_FUNC0 | DWI_DRIVE_STR, // DWI_CLK ->
|
||||
|
||||
/* Port 24 */
|
||||
CFG_OUT_0, // SENSOR0_RST -> CAM0_SHUTDOWN
|
||||
CFG_OUT_0 | CAM_CLK_DRIVE_STR, // SENSOR0_CLK -> CAM0_CLK
|
||||
CFG_OUT_1, // SENSOR1_RST -> CAM1_SHUTDOWN
|
||||
CFG_OUT_0 | CAM_CLK_DRIVE_STR, // SENSOR1_CLK -> CAM1_CLK
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_MCK -> (codec ASP)
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_LRCK ->
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_BCLK ->
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_DOUT ->
|
||||
|
||||
/* Port 25 */
|
||||
CFG_FUNC0, // I2S0_DIN ->
|
||||
CFG_DISABLED, // I2S1_MCK -> (BB)
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S1_LRCK ->
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S1_BCLK ->
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S1_DOUT ->
|
||||
CFG_FUNC0, // I2S1_DIN ->
|
||||
CFG_DISABLED, // I2S2_MCK -> (codec VSP, bluetooth)
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_LRCK ->
|
||||
|
||||
/* Port 26 */
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_BCLK ->
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_DOUT ->
|
||||
CFG_FUNC0, // I2S2_DIN ->
|
||||
CFG_DISABLED, // I2S3_MCK -> (codec XSP, Amp)
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S3_LRCK ->
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S3_BCLK ->
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S3_DOUT ->
|
||||
CFG_FUNC0, // I2S3_DIN ->
|
||||
|
||||
/* Port 27 */
|
||||
CFG_DISABLED, // SPDIF -> BOARD_REV[3]
|
||||
CFG_OUT_0, // GPIO217 -> VIDEO_AMP_EN_3V0
|
||||
CFG_OUT_1, // GPIO218 -> HPHONE_REF_CTRL
|
||||
CFG_FUNC0, // DP_HPD ->
|
||||
CFG_FUNC0 | DOCK_UART_DRIVE_STR, // UART0_TXD ->
|
||||
CFG_FUNC0, // UART0_RXD ->
|
||||
CFG_DISABLED, // TST_CLKOUT ->
|
||||
CFG_DISABLED, // TST_STPCLK ->
|
||||
|
||||
/* Port 28 */
|
||||
CFG_FUNC0, // WDOG ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
};
|
||||
|
||||
#undef BB_UART_DRIVE_STR
|
||||
#undef UMTS_DRIVE_STR
|
||||
#undef BT_UART_DRIVE_STR
|
||||
#undef SWI_UART_DRIVE_STR
|
||||
#undef GPS_UART_DRIVE_STR
|
||||
#undef FMI_DRIVE_STR
|
||||
#undef GRAPE_DRIVE_STR
|
||||
#undef BB_SPI_DRIVE_STR
|
||||
#undef I2C_DRIVE_STR
|
||||
#undef CAM_CLK_DRIVE_STR
|
||||
#undef I2S_DRIVE_STR
|
||||
#undef DOCK_UART_DRIVE_STR
|
||||
#undef IPC_DRIVE_STR
|
||||
|
||||
#define BB_UART_DRIVE_STR DRIVE_X4
|
||||
#define UMTS_DRIVE_STR DRIVE_X4
|
||||
#define BT_UART_DRIVE_STR DRIVE_X4
|
||||
#define SWI_UART_DRIVE_STR DRIVE_X4
|
||||
#define GPS_UART_DRIVE_STR DRIVE_X4
|
||||
#define FMI_DRIVE_STR DRIVE_X4
|
||||
#define GRAPE_DRIVE_STR DRIVE_X4
|
||||
#define BB_SPI_DRIVE_STR DRIVE_X4
|
||||
#define I2C_DRIVE_STR DRIVE_X4
|
||||
#define CAM_CLK_DRIVE_STR DRIVE_X4
|
||||
#define I2S_DRIVE_STR DRIVE_X4
|
||||
#define DOCK_UART_DRIVE_STR DRIVE_X4
|
||||
#define IPC_DRIVE_STR DRIVE_X4
|
||||
|
||||
static const u_int32_t gpio_default_cfg_dev[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
/* Port 0 */
|
||||
CFG_IN, // GPIO0 -> MENU_KEY_BUFF_L (REQUEST_DFU2)
|
||||
CFG_IN, // GPIO1 -> HOLD_KEY_L (REQUEST_DFU1)
|
||||
CFG_IN | PULL_UP, // GPIO2 -> VOL_DWN_L
|
||||
CFG_IN | PULL_UP, // GPIO3 -> VOL_UP_L
|
||||
CFG_IN, // GPIO4 -> RINGER_A
|
||||
CFG_OUT_0, // GPIO5 -> SPKAMP_RESET_L
|
||||
CFG_DISABLED, // GPIO6 ->
|
||||
CFG_OUT_0, // GPIO7 -> BT_WAKE
|
||||
|
||||
/* Port 1 */
|
||||
CFG_OUT_1, // GPIO8 -> BT_RESET_L
|
||||
CFG_DISABLED, // GPIO9 ->
|
||||
CFG_IN, // GPIO10 -> BB_RESET_L
|
||||
CFG_IN | PULL_DOWN, // GPIO11 -> BB_RESET_DET_L
|
||||
CFG_IN | PULL_DOWN, // GPIO12 -> IPC_SRDY
|
||||
CFG_IN | PULL_UP, // GPIO13 -> PMU_IRQ_L
|
||||
CFG_IN, // GPIO14 -> RADIO_ON_L
|
||||
CFG_IN, // GPIO15 -> RESET_BB_PMU_L
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // GPIO16 -> BOARD_ID[3]
|
||||
CFG_IN | PULL_DOWN, // GPIO17 -> BB_HSIC_RDY
|
||||
CFG_DISABLED, // GPIO18 -> BOOT_CONFIG[0]
|
||||
CFG_OUT_0, // GPIO19 -> KEEPACT
|
||||
CFG_IN, // GPIO20 -> BB_EMERGENCY_DWLD_L
|
||||
CFG_IN | PULL_UP, // GPIO21 -> GRAPE_INT_L
|
||||
CFG_OUT_0, // GPIO22 -> LCD_RESET_L
|
||||
CFG_IN | PULL_UP, // GPIO23 -> LCD_HIFA
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // GPIO24 ->
|
||||
CFG_DISABLED, // GPIO25 -> BOOT_CONFIG[1]
|
||||
CFG_IN | PULL_DOWN, // GPIO26 -> FORCE_DFU
|
||||
CFG_DISABLED | PULL_DOWN, // GPIO27 -> DFU_STATUS
|
||||
CFG_DISABLED, // GPIO28 -> BOOT_CONFIG[2]
|
||||
CFG_DISABLED, // GPIO29 -> BOOT_CONFIG[3]
|
||||
CFG_IN | PULL_UP, // GPIO30 -> CODEC_INT_L
|
||||
CFG_IN, // GPIO31 -> WLAN_HSIC_RDY
|
||||
|
||||
/* Port 4 */
|
||||
CFG_IN | PULL_DOWN, // GPIO32 -> GYRO_INT2
|
||||
CFG_IN | PULL_DOWN, // GPIO33 -> GYRO_INT
|
||||
CFG_IN | PULL_DOWN, // GPIO34 -> COMPASS_BRD_INT
|
||||
CFG_DISABLED, // GPIO35 ->
|
||||
CFG_IN | PULL_UP, // GPIO36 -> ACCEL_INT1_L
|
||||
CFG_IN | PULL_UP, // GPIO37 -> ACCEL_INT2_L
|
||||
CFG_IN | PULL_UP, // GPIO38 -> ALS_INT_L
|
||||
CFG_OUT_0, // GPIO39 -> GRAPE_RESET_L
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED, // EHCI_PORT_PWR[0] -> BOARD_REV[0]
|
||||
CFG_DISABLED, // EHCI_PORT_PWR[1] -> BOARD_REV[1]
|
||||
CFG_DISABLED, // EHCI_PORT_PWR[2] -> BOARD_REV[2]
|
||||
CFG_IN | BB_UART_DRIVE_STR, // UART1_TXD -> (BB USART)
|
||||
CFG_FUNC0, // UART1_RXD ->
|
||||
CFG_FUNC0 | BB_UART_DRIVE_STR, // UART1_RTSN ->
|
||||
CFG_FUNC0, // UART1_CTSN ->
|
||||
CFG_OUT_0, // UART2_TXD -> HOST_WLAN_HSIC_RDY
|
||||
|
||||
/* Port 6 */
|
||||
CFG_IN, // UART2_RXD -> IPC_GPIO4
|
||||
CFG_DISABLED, // UART2_RTSN -> PMU_AMUX_AY_CTRL
|
||||
CFG_DISABLED, // UART2_CTSN -> PMU_AMUX_BY_CTRL
|
||||
CFG_FUNC0 | BT_UART_DRIVE_STR, // UART3_TXD -> (BT)
|
||||
CFG_FUNC0, // UART3_RXD ->
|
||||
CFG_OUT_1 | BT_UART_DRIVE_STR, // UART3_RTSN ->
|
||||
CFG_FUNC0, // UART3_CTSN ->
|
||||
CFG_FUNC0 | SWI_UART_DRIVE_STR, // UART5_RTXD -> BATTERY_SWI
|
||||
|
||||
/* Port 7 */
|
||||
CFG_OUT_0, // UART6_TXD -> HOST_BB_HSIC_RDY
|
||||
CFG_DISABLED, // UART6_RXD ->
|
||||
CFG_DISABLED, // UART6_RTSN ->
|
||||
CFG_DISABLED, // UART6_CTSN ->
|
||||
CFG_DISABLED, // UART4_TXD/SPI4_MOSI ->
|
||||
CFG_DISABLED, // UART4_RXD/SPI4_MISO ->
|
||||
CFG_DISABLED, // UART4_RTSN/SPI4_SCLK ->
|
||||
CFG_DISABLED, // UART4_CTSN/SPI4_SSIN ->
|
||||
|
||||
/* Port 8 */
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN3 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN2 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN1 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN0 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CLE ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_ALE ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_REN ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_WEN ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO7 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO6 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO5 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO4 ->
|
||||
CFG_DISABLED | PULL_DOWN, // FMI0_DQS ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO3 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO2 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO1 ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO0 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN3 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN2 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN1 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN0 ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CLE ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_ALE ->
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_REN ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_WEN ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO7 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO6 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO5 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO4 ->
|
||||
CFG_DISABLED | PULL_DOWN, // FMI1_DQS ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO3 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO2 ->
|
||||
|
||||
/* Port 12 */
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO1 ->
|
||||
CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO0 ->
|
||||
CFG_DISABLED, // FMI2_CEN3 ->
|
||||
CFG_DISABLED, // FMI2_CEN2 ->
|
||||
CFG_DISABLED, // FMI2_CEN1 ->
|
||||
CFG_DISABLED, // FMI2_CEN0 ->
|
||||
CFG_DISABLED, // FMI2_CLE ->
|
||||
CFG_DISABLED, // FMI2_ALE ->
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // FMI2_REN ->
|
||||
CFG_DISABLED, // FMI2_WEN ->
|
||||
CFG_DISABLED, // FMI2_IO7 ->
|
||||
CFG_DISABLED, // FMI2_IO6 ->
|
||||
CFG_DISABLED, // FMI2_IO5 ->
|
||||
CFG_DISABLED, // FMI2_IO4 ->
|
||||
CFG_DISABLED, // FMI2_DQS ->
|
||||
CFG_DISABLED, // FMI2_IO3 ->
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // FMI2_IO2 ->
|
||||
CFG_DISABLED, // FMI2_IO1 ->
|
||||
CFG_DISABLED, // FMI2_IO0 ->
|
||||
CFG_DISABLED, // FMI0_CEN7 ->
|
||||
CFG_DISABLED, // FMI0_CEN6 ->
|
||||
CFG_DISABLED, // FMI0_CEN5 ->
|
||||
CFG_DISABLED, // FMI0_CEN4 ->
|
||||
CFG_DISABLED, // FMI1_CEN7 ->
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // FMI1_CEN6 ->
|
||||
CFG_DISABLED, // FMI1_CEN5 ->
|
||||
CFG_DISABLED, // FMI1_CEN4 ->
|
||||
CFG_DISABLED, // FMI3_CEN3 ->
|
||||
CFG_DISABLED, // FMI3_CEN2 ->
|
||||
CFG_DISABLED, // FMI3_CEN1 ->
|
||||
CFG_DISABLED, // FMI3_CEN0 ->
|
||||
CFG_DISABLED, // FMI3_CLE ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED, // FMI3_ALE ->
|
||||
CFG_DISABLED, // FMI3_REN ->
|
||||
CFG_DISABLED, // FMI3_WEN ->
|
||||
CFG_DISABLED, // FMI3_IO7 ->
|
||||
CFG_DISABLED, // FMI3_IO6 ->
|
||||
CFG_DISABLED, // FMI3_IO5 ->
|
||||
CFG_DISABLED, // FMI3_IO4 ->
|
||||
CFG_DISABLED, // FMI3_DQS ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // FMI3_IO3 ->
|
||||
CFG_DISABLED, // FMI3_IO2 ->
|
||||
CFG_DISABLED, // FMI3_IO1 ->
|
||||
CFG_DISABLED, // FMI3_IO0 ->
|
||||
CFG_DISABLED, // FMI2_CEN7 ->
|
||||
CFG_DISABLED, // FMI2_CEN6 ->
|
||||
CFG_DISABLED, // FMI2_CEN5 ->
|
||||
CFG_DISABLED, // FMI2_CEN4 ->
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED, // FMI3_CEN7 ->
|
||||
CFG_DISABLED, // FMI3_CEN6 ->
|
||||
CFG_DISABLED, // FMI3_CEN5 ->
|
||||
CFG_DISABLED, // FMI3_CEN4 ->
|
||||
CFG_DISABLED, // SPI3_MOSI ->
|
||||
CFG_DISABLED, // SPI3_MISO ->
|
||||
CFG_DISABLED, // SPI3_SCLK ->
|
||||
CFG_DISABLED, // SPI3_SSIN ->
|
||||
|
||||
/* Port 19 */
|
||||
CFG_OUT_0, // ISP0_PRE_FLASH -> CAM0_VDDCORE_EN
|
||||
CFG_OUT_0, // ISP0_FLASH -> CAM0_RESET_L
|
||||
CFG_DISABLED, // ISP1_PRE_FLASH ->
|
||||
CFG_OUT_0, // ISP1_FLASH -> CAM1_RESET_L
|
||||
CFG_FUNC0 | GRAPE_DRIVE_STR, // SPI1_SCLK -> SPI1_SCLK (GRAPE)
|
||||
CFG_FUNC0 | GRAPE_DRIVE_STR, // SPI1_MOSI -> SPI1_MOSI
|
||||
CFG_FUNC0, // SPI1_MISO -> SPI1_MISO
|
||||
CFG_OUT_1 | GRAPE_DRIVE_STR, // SPI1_SSIN -> SPI1_CS_L
|
||||
|
||||
/* Port 20 */
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C2_SDA -> I2C2_SDA_1V8
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C2_SCL -> I2C2_SCL_1V8
|
||||
CFG_DISABLED, // SPI0_SCLK -> SPI0_SCLK/BOARD_ID[0]
|
||||
CFG_DISABLED, // SPI0_MOSI -> SPI0_MOSI/BOARD_ID[1]
|
||||
CFG_DISABLED, // SPI0_MISO -> SPI0_MISO/BOARD_ID[2]
|
||||
CFG_DISABLED, // SPI0_SSIN -> SPI0_SSIN
|
||||
CFG_DISABLED, // SPI2_SCLK ->
|
||||
CFG_DISABLED, // SPI2_MOSI ->
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // SPI2_MISO ->
|
||||
CFG_OUT_0 | BB_SPI_DRIVE_STR, // SPI2_SSIN -> SPI2_MRDY / IPC_MRDY
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C0_SDA -> I2C0_SDA_1V8
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C0_SCL -> I2C0_SCL_1V8
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C1_SDA -> I2C1_SDA_1V8
|
||||
CFG_FUNC0 | I2C_DRIVE_STR, // I2C1_SCL -> I2C1_SCL_1V8
|
||||
CFG_FUNC0 | CAM_I2C_DRIVE_STR, // ISP0_SDA ->
|
||||
CFG_FUNC0 | CAM_I2C_DRIVE_STR, // ISP0_SCL ->
|
||||
|
||||
/* Port 22 */
|
||||
CFG_FUNC0 | CAM_I2C_DRIVE_STR, // ISP1_SDA ->
|
||||
CFG_FUNC0 | CAM_I2C_DRIVE_STR, // ISP1_SCL ->
|
||||
CFG_DISABLED, // SDIO_CLK ->
|
||||
CFG_DISABLED, // SDIO_CMD ->
|
||||
CFG_DISABLED, // SDIO_DATA0 ->
|
||||
CFG_DISABLED, // SDIO_DATA1 ->
|
||||
CFG_DISABLED, // SDIO_DATA2 ->
|
||||
CFG_DISABLED, // SDIO_DATA3 ->
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED, // MIPI_VSYNC ->
|
||||
CFG_IN, // TMR32_PWM0 -> GYRO_INT2 (also GPIO32)
|
||||
CFG_IN, // TMR32_PWM1 -> ACCEL_INT2_L (also GPIO37)
|
||||
CFG_OUT_0 | CAM_STROBE_DRIVE_STR, // TMR32_PWM2 -> CAM_STROBE_EN
|
||||
CFG_DISABLED, // SWI_DATA ->
|
||||
CFG_FUNC0 | PULL_DOWN, // DWI_DI ->
|
||||
CFG_FUNC0 | DWI_DRIVE_STR, // DWI_DO ->
|
||||
CFG_FUNC0 | DWI_DRIVE_STR, // DWI_CLK ->
|
||||
|
||||
/* Port 24 */
|
||||
CFG_OUT_0, // SENSOR0_RST -> CAM0_SHUTDOWN
|
||||
CFG_OUT_0 | CAM_CLK_DRIVE_STR, // SENSOR0_CLK -> CAM0_CLK
|
||||
CFG_OUT_1, // SENSOR1_RST -> CAM1_SHUTDOWN
|
||||
CFG_OUT_0 | CAM_CLK_DRIVE_STR, // SENSOR1_CLK -> CAM1_CLK
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_MCK -> (codec ASP)
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_LRCK ->
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_BCLK ->
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S0_DOUT ->
|
||||
|
||||
/* Port 25 */
|
||||
CFG_FUNC0, // I2S0_DIN ->
|
||||
CFG_DISABLED, // I2S1_MCK -> (BB)
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S1_LRCK ->
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S1_BCLK ->
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S1_DOUT ->
|
||||
CFG_FUNC0, // I2S1_DIN ->
|
||||
CFG_DISABLED, // I2S2_MCK -> (codec VSP, bluetooth)
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_LRCK ->
|
||||
|
||||
/* Port 26 */
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_BCLK ->
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S2_DOUT ->
|
||||
CFG_FUNC0, // I2S2_DIN ->
|
||||
CFG_DISABLED, // I2S3_MCK -> (codec XSP, Amp)
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S3_LRCK ->
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S3_BCLK ->
|
||||
CFG_FUNC0 | I2S_DRIVE_STR, // I2S3_DOUT ->
|
||||
CFG_FUNC0, // I2S3_DIN ->
|
||||
|
||||
/* Port 27 */
|
||||
CFG_FUNC0, // SPDIF -> BOARD_REV[3] / SPDIF
|
||||
CFG_OUT_0, // GPIO217 -> VIDEO_AMP_EN_3V0
|
||||
CFG_OUT_1, // GPIO218 -> HPHONE_REF_CTRL
|
||||
CFG_FUNC0, // DP_HPD ->
|
||||
CFG_FUNC0 | DOCK_UART_DRIVE_STR, // UART0_TXD ->
|
||||
CFG_FUNC0, // UART0_RXD ->
|
||||
CFG_DISABLED, // TST_CLKOUT ->
|
||||
CFG_DISABLED, // TST_STPCLK ->
|
||||
|
||||
/* Port 28 */
|
||||
CFG_FUNC0, // WDOG ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
if (target_config_ap())
|
||||
return gpio_default_cfg_ap;
|
||||
else
|
||||
return gpio_default_cfg_dev;
|
||||
}
|
||||
@@ -0,0 +1,42 @@
|
||||
# Copyright (C) 2010-2011 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DIALOG_D1881=1 \
|
||||
TARGET_HIGH_SOC_VOLTAGE=CHIPID_SOC_VOLTAGE_MED \
|
||||
TARGET_HIGH_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_MED \
|
||||
TARGET_CPU_SOURCE=2 \
|
||||
TARGET_MIPI_DSI_SOURCE=1 \
|
||||
TARGET_MANAGED2H_SOURCE=0 \
|
||||
TARGET_MANAGED2L_SOURCE=0 \
|
||||
TARGET_MANAGED2H_DIV=1 \
|
||||
TARGET_MANAGED2L_DIV=2 \
|
||||
TARGET_PCLK1_SOURCE=2 \
|
||||
TARGET_PCLK1_DIV=6 \
|
||||
TARGET_GFX_SOURCE=2 \
|
||||
TARGET_GFX_SLC_SOURCE=3 \
|
||||
TARGET_IOP_SOURCE=3 \
|
||||
TARGET_LPERFS_SOURCE=3 \
|
||||
TARGET_HPERFNRT_SOURCE=0 \
|
||||
TARGET_USE_HSIC=1 \
|
||||
TARGET_DSIM_DPHYCTL=0x30 \
|
||||
AMC_NUM_CHANNELS=2 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
AMC_CHANNEL_WIDTH=4 \
|
||||
MULTITOUCH_DTPATH=\"arm-io/spi1/multi-touch\" \
|
||||
BASEBAND_DTPATH=\"baseband\" \
|
||||
WIFI_DTPATH=\"arm-io/usb-complex/usb-ehci/wlan\"
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig.o
|
||||
Reference in new issue
Block a user