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@@ -0,0 +1,27 @@
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/*
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* Copyright (C) 2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ADBE_SETTINGS_H
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#define __TARGET_ADBE_SETTINGS_H
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static struct adbe_v2_tuneable adbe_tuneables[] = {
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{
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.name = "default",
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.adbe0_vblank_pos_vbi_pulse = 0x0000,
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.adbe0_vblank_clk_gate_wakeup = 0x0000,
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.adbe0_vblank_clk_gate_idle = 0x0001,
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.adbe0_vblank_busy_finish = 0,
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.adbe0_tunable_mode_ctrl = 0,
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.adbe0_aap_support = 1,
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.adbe0_aap_format_control_reg1 = (AAP_FORMAT_CONTROL_REG1_AUTOPOS | AAP_FORMAT_CONTROL_REG1_RSVD(8) | AAP_FORMAT_CONTROL_REG1_VS_POL),
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},
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};
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#endif
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __TARGET_ASPNANDCONFIG_H
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#define __TARGET_ASPNANDCONFIG_H
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//MLC devices
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#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
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#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_DIES_IN_PARALLEL 4
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#define ASPNAND_READ_DIES_IN_PARALLEL 4
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#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
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//TLC devices
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#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
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#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
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#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
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// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
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#define ASPNAND_INDIRECTION_MEMORY (2*1024*1024)
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#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
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#endif
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@@ -0,0 +1,18 @@
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/*
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* Copyright (C) 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#if SUB_PLATFORM_S8001
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#include <target/dcsfixup_s8001.h>
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#elif SUB_PLATFORM_S8003
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#include <target/dcsfixup_s8003.h>
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#else
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#include <target/dcsfixup_s8000.h>
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#endif
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@@ -0,0 +1,74 @@
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/*
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* Copyright (C) 2014-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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static inline
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void dcs_init_config_fixup_params(dcs_config_params_t *dcs_params, dcs_target_t targtype)
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{
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uint32_t chip_rev = platform_get_chip_revision();
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if(chip_rev < CHIP_REVISION_B0) {
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dcs_params->freq[0].freqchngctl[1] = 0x000b110c;
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dcs_params->freq[1].freqchngctl[1] = 0x000b110c;
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dcs_params->freq[0].selfref = 0x02001012;
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dcs_params->freq[1].selfref = 0x02001012;
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dcs_params->freq[2].selfref = 0x02001012;
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dcs_params->freq[3].selfref = 0x02001012;
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} else {
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dcs_params->freq[0].freqchngctl[2] = 0xb303000b;
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dcs_params->freq[1].freqchngctl[2] = 0xf303000b;
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dcs_params->freq[0].selfref = 0x28002012;
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dcs_params->freq[1].selfref = 0x28002012;
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dcs_params->freq[2].selfref = 0x28002012;
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dcs_params->freq[3].selfref = 0x28002012;
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}
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dcs_params->freq[0].lat = 0x001030c2;
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dcs_params->freq[1].lat = 0x001020c2;
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dcs_params->freq[0].phyrdwrtim = 0x00010c01;
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dcs_params->freq[1].phyrdwrtim = 0x00010b01;
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dcs_params->freq[0].caspch = 0x40c20402;
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dcs_params->freq[0].act = 0x01020202;
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dcs_params->freq[0].autoref = 0x01010078;
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dcs_params->modereg = 0x04009024;
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dcs_params->freq[1].caspch = 0x40c20402;
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dcs_params->freq[1].act = 0x01020202;
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dcs_params->freq[1].autoref = 0x01010050;
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dcs_params->freq[2].caspch = 0x40c20402;
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dcs_params->freq[2].act = 0x01020202;
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dcs_params->freq[2].autoref = 0x01010014;
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dcs_params->freq[3].act = 0x01020404;
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dcs_params->freq[3].autoref = 0x01010005;
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dcs_params->autoref_params = 0x00150013;
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dcs_params->pdn = 0x21262222;
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dcs_params->freq[0].derate = 0x08212082;
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dcs_params->freq[1].derate = 0x08212082;
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dcs_params->freq[2].derate = 0x08212082;
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dcs_params->freq[0].lat2 = 0x001110c2;
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dcs_params->freq[1].lat2 = 0x001110c2;
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dcs_params->freq[0].tat = 0x01212222;
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dcs_params->freq[1].tat = 0x01212222;
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dcs_params->freq[3].mifqmaxctrl = 0x00000003;
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dcs_params->freq[0].odt_enable = 0x00000000;
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dcs_params->freq[1].odt_enable = 0x00000000;
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dcs_params->freq[0].rdcapcfg = 0x01000606;
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dcs_params->freq[1].rdcapcfg = 0x21000606;
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dcs_params->freq[2].rdcapcfg = 0x41000606;
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dcs_params->freq[3].rdcapcfg = 0x61000606;
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dcs_params->freq[0].autoref2 = 0x01010001;
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dcs_params->freq[1].autoref2 = 0x01010001;
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dcs_params->freq[2].autoref2 = 0x01010001;
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dcs_params->freq[3].autoref2 = 0x01010001;
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dcs_params->autoref_params2 = 0x00170013;
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dcs_params->odtszqc = 0x00000000;
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dcs_params->odtszqc2 = 0xc0000000;
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dcs_params->qbrparam = 0x00006100;
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dcs_params->odtszqc3 = 0xc0002320;
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};
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@@ -0,0 +1,69 @@
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/*
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* Copyright (C) 2014-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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static inline
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void dcs_init_config_fixup_params(dcs_config_params_t *dcs_params, dcs_target_t targtype)
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{
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dcs_params->freq[0].freqchngctl[2] = 0xb303000b;
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dcs_params->freq[1].freqchngctl[2] = 0xd303000b;
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dcs_params->freq[0].lat = 0x001030c2;
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dcs_params->freq[1].lat = 0x001020c2;
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dcs_params->freq[0].phyrdwrtim = 0x00010d01;
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dcs_params->freq[1].phyrdwrtim = 0x00010b01;
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dcs_params->freq[0].caspch = 0x40c20402;
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dcs_params->freq[0].act = 0x01020202;
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dcs_params->freq[0].autoref = 0x01010078;
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dcs_params->freq[0].selfref = 0x28002012;
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dcs_params->modereg = 0x060c5024;
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dcs_params->freq[1].caspch = 0x40c20402;
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dcs_params->freq[1].act = 0x01020202;
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dcs_params->freq[1].autoref = 0x01010050;
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dcs_params->freq[1].selfref = 0x28002012;
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dcs_params->freq[2].caspch = 0x40c20402;
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dcs_params->freq[2].act = 0x01020202;
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dcs_params->freq[2].autoref = 0x01010014;
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dcs_params->freq[2].selfref = 0x28002012;
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dcs_params->freq[3].act = 0x01020404;
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dcs_params->freq[3].autoref = 0x01010005;
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dcs_params->freq[3].selfref = 0x28002012;
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dcs_params->autoref_params = 0x00150013;
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dcs_params->pdn = 0x21272222;
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dcs_params->freq[0].derate = 0x08212082;
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dcs_params->freq[1].derate = 0x08212082;
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dcs_params->freq[2].derate = 0x08212082;
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dcs_params->freq[0].lat2 = 0x001110c2;
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dcs_params->freq[1].lat2 = 0x001110c2;
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dcs_params->freq[0].tat = 0x01212222;
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dcs_params->freq[1].tat = 0x01212222;
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dcs_params->freq[3].mifqmaxctrl = 0x00000003;
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dcs_params->freq[0].odt_enable = 0x00000000;
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dcs_params->freq[1].odt_enable = 0x00000000;
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dcs_params->freq[0].rdcapcfg = 0x01000606;
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dcs_params->freq[1].rdcapcfg = 0x21000606;
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dcs_params->freq[2].rdcapcfg = 0x41000606;
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dcs_params->freq[3].rdcapcfg = 0x61000606;
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dcs_params->b0odtctrl = 0x00000000;
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dcs_params->b1odtctrl = 0x00000000;
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dcs_params->dqs0odtctrl = 0x00000000;
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dcs_params->dqs1odtctrl = 0x00000000;
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dcs_params->freq[0].autoref2 = 0x01010001;
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dcs_params->freq[1].autoref2 = 0x01010001;
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dcs_params->freq[2].autoref2 = 0x01010001;
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dcs_params->freq[3].autoref2 = 0x01010001;
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dcs_params->autoref_params2 = 0x002f0013;
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dcs_params->mr13cmd_step15 = 0x50,
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dcs_params->odtszqc = 0x00000000;
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dcs_params->odtszqc2 = 0xc0000000;
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dcs_params->qbrparam = 0x00000000;
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// Commenting the pwrmngten fixup b/c DV thinks this is a mistake in the spec
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// dcs_params->pwrmngten = 0x00000132;
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dcs_params->odtszqc3 = 0xc0002320;
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};
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@@ -0,0 +1,66 @@
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/*
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* Copyright (C) 2014-2015 Apple Inc. All rights reserved.
|
||||
*
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||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
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static inline
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void dcs_init_config_fixup_params(dcs_config_params_t *dcs_params, dcs_target_t targtype)
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{
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dcs_params->freq[0].freqchngctl[2] = 0xb303000b;
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dcs_params->freq[1].freqchngctl[2] = 0xf303000b;
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dcs_params->freq[0].lat = 0x001030c2;
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dcs_params->freq[1].lat = 0x001020c2;
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dcs_params->freq[0].phyrdwrtim = 0x00010d01;
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dcs_params->freq[1].phyrdwrtim = 0x00010c01;
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dcs_params->freq[0].caspch = 0x40c20402;
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dcs_params->freq[0].act = 0x01020202;
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dcs_params->freq[0].autoref = 0x01010078;
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dcs_params->freq[0].selfref = 0x28002012;
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dcs_params->modereg = 0x060a9024;
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dcs_params->freq[1].caspch = 0x40c20402;
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dcs_params->freq[1].act = 0x01020202;
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dcs_params->freq[1].autoref = 0x01010050;
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dcs_params->freq[1].selfref = 0x28002012;
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dcs_params->freq[2].caspch = 0x40c20402;
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dcs_params->freq[2].act = 0x01020202;
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dcs_params->freq[2].autoref = 0x01010014;
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dcs_params->freq[2].selfref = 0x28002012;
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dcs_params->freq[3].act = 0x01020404;
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dcs_params->freq[3].autoref = 0x01010005;
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dcs_params->freq[3].selfref = 0x28002012;
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dcs_params->autoref_params = 0x00150013;
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dcs_params->pdn = 0x21262222;
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dcs_params->freq[0].derate = 0x08212082;
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dcs_params->freq[1].derate = 0x08212082;
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dcs_params->freq[2].derate = 0x08212082;
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dcs_params->freq[0].lat2 = 0x001110c2;
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dcs_params->freq[1].lat2 = 0x001110c2;
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dcs_params->freq[0].tat = 0x01212222;
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dcs_params->freq[1].tat = 0x01212222;
|
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dcs_params->freq[3].mifqmaxctrl = 0x00000003;
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dcs_params->freq[0].odt_enable = 0x00000000;
|
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dcs_params->freq[1].odt_enable = 0x00000000;
|
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dcs_params->freq[0].rdcapcfg = 0x01000606;
|
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dcs_params->freq[1].rdcapcfg = 0x21000606;
|
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dcs_params->freq[2].rdcapcfg = 0x41000606;
|
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dcs_params->freq[3].rdcapcfg = 0x61000606;
|
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dcs_params->b0odtctrl = 0x00000000;
|
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dcs_params->b1odtctrl = 0x00000000;
|
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dcs_params->dqs0odtctrl = 0x00000000;
|
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dcs_params->dqs1odtctrl = 0x00000000;
|
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dcs_params->freq[0].autoref2 = 0x01010001;
|
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dcs_params->freq[1].autoref2 = 0x01010001;
|
||||
dcs_params->freq[2].autoref2 = 0x01010001;
|
||||
dcs_params->freq[3].autoref2 = 0x01010001;
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dcs_params->autoref_params2 = 0x00170013;
|
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dcs_params->odtszqc = 0x00000000;
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dcs_params->odtszqc2 = 0xc0000000;
|
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dcs_params->qbrparam = 0x00006100;
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||||
dcs_params->odtszqc3 = 0xc0002320;
|
||||
};
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_GPIODEF_H
|
||||
#define __TARGET_GPIODEF_H
|
||||
|
||||
/* S8000FPGA specific gpio -> pin mappings */
|
||||
|
||||
#include <platform/gpio.h>
|
||||
|
||||
/* define target-specific gpios in a generic fashion here. */
|
||||
|
||||
#endif /* ! __TARGET_GPIODEF_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define one debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (0)
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define UART_OVERSAMPLE_OVERRIDE (11)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,242 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/flash_nor.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <sys.h>
|
||||
#include <sys/menu.h>
|
||||
#include <sys/task.h>
|
||||
#include <target.h>
|
||||
|
||||
#if !SUPPORT_FPGA
|
||||
#error "FPGA target without SUPPORT_FPGA set"
|
||||
#endif
|
||||
|
||||
static uint32_t display_config;
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 1);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
*cold_button_boot = true;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if !PRODUCT_LLB
|
||||
bool target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
void * target_get_display_configuration(void)
|
||||
{
|
||||
display_config = 0x00000000;
|
||||
return ((void *)(&display_config));
|
||||
}
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
env_set("boot-args", " debug=0x14e serial=3 amfi=3 amfi_get_out_of_my_way=1 cs_enforcement_disable=1 fips_mode=0", 0);
|
||||
// boot-device is set in platform's init.c
|
||||
env_set("display-color-space","RGB888", 0);
|
||||
env_set("display-timing", "fpga-wsvga", 0);
|
||||
env_set("ramdisk-delay", "30000000", 0); /* This tells PurpleRestore to slow down; rdar://6345846 */
|
||||
env_set("idle-off", "false", 0);
|
||||
env_set("bootdelay", "3", 0);
|
||||
env_set("debug-uarts", "3", 0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
#define MAX_NODES_PER_DEVICE 3
|
||||
struct fpgaNode_t
|
||||
{
|
||||
uint32_t mask; // Block enable mask
|
||||
const char *nodeName[MAX_NODES_PER_DEVICE]; // Device tree nodes to disable if block is absent
|
||||
};
|
||||
|
||||
// Devices tree nodes to disable based upon FPGA block instantiation
|
||||
struct fpgaNode_t fpgaNodes[] = {
|
||||
{ FPGA_HAS_VXD, { "arm-io/vxd", NULL, NULL }},
|
||||
{ FPGA_HAS_AVE, { "arm-io/ave", "arm-io/dart-ave", "arm-io/dart-ave/mapper-ave" }},
|
||||
{ FPGA_HAS_ISP, { "arm-io/isp", "arm-io/dart-isp", "arm-io/dart-isp/mapper-isp" }},
|
||||
{ FPGA_HAS_DISP, { "arm-io/disp0", "arm-io/dart-disp0", "arm-io/dart-disp0/mapper-disp0" }},
|
||||
{ FPGA_HAS_MSR, { "arm-io/scaler0", "arm-io/dart-scaler", "arm-io/dart-scaler/mapper-scaler" }},
|
||||
{ FPGA_HAS_JPEG, { "arm-io/jpeg", "arm-io/dart-jpeg", "arm-io/dart-jpeg/mapper-jpeg" }},
|
||||
{ FPGA_HAS_GFX, { "arm-io/sgx", NULL, NULL }},
|
||||
};
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
DTNode *node;
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
uint32_t i, j;
|
||||
|
||||
// Get the hardware blocks that are instantiated on this FPGA.
|
||||
uint32_t fpgaBlocks = chipid_get_fpga_block_instantiation();
|
||||
dprintf(DEBUG_SPEW, "FPGA block instantiation mask = 0x%X\n", fpgaBlocks);
|
||||
|
||||
for (i = 0; i < sizeof(fpgaNodes)/sizeof(fpgaNodes[0]); i++) {
|
||||
if ((fpgaBlocks & fpgaNodes[i].mask) == 0) {
|
||||
for (j = 0; j < MAX_NODES_PER_DEVICE; j++) {
|
||||
if (fpgaNodes[i].nodeName[j] == NULL) {
|
||||
break;
|
||||
}
|
||||
if (FindNode(0, fpgaNodes[i].nodeName[j], &node)) {
|
||||
propName = "compatible";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (j == 0) {
|
||||
dprintf(DEBUG_INFO,
|
||||
"FPGA block not instantiated: disabling %s\n",
|
||||
fpgaNodes[i].nodeName[j]);
|
||||
}
|
||||
propName[0] = '~';
|
||||
} else {
|
||||
dprintf(DEBUG_SPEW,
|
||||
"FPGA: Could not find 'compatible' property for %s DT node\n",
|
||||
fpgaNodes[i].nodeName[j]);
|
||||
}
|
||||
} else {
|
||||
dprintf(DEBUG_SPEW,
|
||||
"FPGA: Could not find %s DT node\n",
|
||||
fpgaNodes[i].nodeName[j]);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if !WITH_HW_POWER
|
||||
|
||||
bool power_needs_precharge(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
void power_cancel_buttonwait(void)
|
||||
{
|
||||
}
|
||||
|
||||
bool power_do_chargetrap(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
bool power_is_suspended(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
void power_will_resume(void)
|
||||
{
|
||||
}
|
||||
|
||||
bool power_has_usb(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
int power_read_dock_id(unsigned *id)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
bool power_get_diags_dock(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
u_int32_t power_get_boot_battery_level(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int power_get_nvram(u_int8_t key, u_int8_t *data)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int power_set_nvram(u_int8_t key, u_int8_t data)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int power_set_soc_voltage(unsigned mv, int override)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
bool force_usb_power = false;
|
||||
|
||||
void power_set_usb_state(bool configured, bool suspended)
|
||||
{
|
||||
}
|
||||
|
||||
int power_backlight_enable(u_int32_t backlight_level)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* ! WITH_HW_POWER */
|
||||
@@ -0,0 +1,325 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <stdint.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
/* THIS STRUCT IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
*/
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED, // 0 : SWD_TMS2 ->
|
||||
CFG_DISABLED, // 1 : SWD_TMS3 ->
|
||||
CFG_DISABLED, // 2 : UART5_RTXD ->
|
||||
CFG_DISABLED, // 3 : I2S4_MCK ->
|
||||
CFG_DISABLED, // 4 : I2S4_BCLK ->
|
||||
CFG_DISABLED, // 5 : I2S4_LRCK ->
|
||||
CFG_DISABLED, // 6 : I2S4_DIN ->
|
||||
CFG_DISABLED, // 7 : I2S4_DOUT ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED, // 8 : I2S2_MCK ->
|
||||
CFG_DISABLED, // 9 : I2S2_BCLK ->
|
||||
CFG_DISABLED, // 10 : I2S2_LRCK ->
|
||||
CFG_DISABLED, // 11 : I2S2_DIN ->
|
||||
CFG_DISABLED, // 12 : I2S2_DOUT ->
|
||||
CFG_DISABLED, // 13 : SPI1_SCLK ->
|
||||
CFG_DISABLED, // 14 : SPI1_MOSI ->
|
||||
CFG_DISABLED, // 15 : SPI1_MISO ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // 16 : SPI1_SSIN ->
|
||||
CFG_DISABLED, // 17 : I2S0_MCK ->
|
||||
CFG_DISABLED, // 18 : I2S0_BCLK ->
|
||||
CFG_DISABLED, // 19 : I2S0_LRCK ->
|
||||
CFG_DISABLED, // 20 : I2S0_DIN ->
|
||||
CFG_DISABLED, // 21 : I2S0_DOUT ->
|
||||
CFG_DISABLED, // 22 : I2C2_SDA ->
|
||||
CFG_DISABLED, // 23 : I2C2_SCL ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // 24 : UART1_TXD ->
|
||||
CFG_DISABLED, // 25 : UART1_RXD ->
|
||||
CFG_DISABLED, // 26 : UART1_RTSN ->
|
||||
CFG_DISABLED, // 27 : UART1_CTSN ->
|
||||
CFG_DISABLED, // 28 : UART4_TXD ->
|
||||
CFG_DISABLED, // 29 : UART4_RXD ->
|
||||
CFG_DISABLED, // 30 : UART4_RTSN ->
|
||||
CFG_DISABLED, // 31 : UART4_CTSN ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED, // 32 : UART7_TXD ->
|
||||
CFG_DISABLED, // 33 : UART7_RXD ->
|
||||
CFG_DISABLED, // 34 : CLK32K_OUT ->
|
||||
CFG_DISABLED, // 35 : DP_WAKEUP ->
|
||||
CFG_DISABLED, // 36 : MIPICSI_MUXSEL ->
|
||||
CFG_DISABLED, // 37 : ISP_I2C1_SDA ->
|
||||
CFG_DISABLED, // 38 : ISP_I2C1_SCL ->
|
||||
CFG_DISABLED, // 39 : ISP_I2C0_SDA ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED, // 40 : ISP_I2C0_SCL ->
|
||||
CFG_DISABLED, // 41 : SPI2_SCLK ->
|
||||
CFG_DISABLED, // 42 : SPI2_MOSI ->
|
||||
CFG_DISABLED, // 43 : SPI2_MISO ->
|
||||
CFG_DISABLED, // 44 : SPI2_SSIN ->
|
||||
CFG_DISABLED, // 45 : I2C0_SDA ->
|
||||
CFG_DISABLED, // 46 : I2C0_SCL ->
|
||||
CFG_DISABLED, // 47 : SENSOR0_ISTRB ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED, // 48 : SENSOR0_RST ->
|
||||
CFG_DISABLED, // 49 : SENSOR0_CLK ->
|
||||
CFG_DISABLED, // 50 : SENSOR0_XSHUTDOWN ->
|
||||
CFG_DISABLED, // 51 : SENSOR1_ISTRB ->
|
||||
CFG_DISABLED, // 52 : SENSOR1_RST ->
|
||||
CFG_DISABLED, // 53 : SENSOR1_CLK ->
|
||||
CFG_DISABLED, // 54 : SENSOR1_XSHUTDOWN ->
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // 64 : GPIO[0] ->
|
||||
CFG_DISABLED, // 65 : GPIO[1] ->
|
||||
CFG_DISABLED, // 66 : GPIO[2] ->
|
||||
CFG_DISABLED, // 67 : GPIO[3] ->
|
||||
CFG_DISABLED, // 68 : GPIO[4] ->
|
||||
CFG_DISABLED, // 69 : GPIO[5] ->
|
||||
CFG_DISABLED, // 70 : GPIO[6] ->
|
||||
CFG_DISABLED, // 71 : GPIO[7] ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // 72 : GPIO[8] ->
|
||||
CFG_DISABLED, // 73 : GPIO[9] ->
|
||||
CFG_DISABLED, // 74 : GPIO[10] ->
|
||||
CFG_DISABLED, // 75 : GPIO[11] ->
|
||||
CFG_DISABLED, // 76 : GPIO[12] ->
|
||||
CFG_DISABLED, // 77 : GPIO[13] ->
|
||||
CFG_DISABLED, // 78 : GPIO[14] ->
|
||||
CFG_DISABLED, // 79 : GPIO[15] ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // 80 : GPIO[16] -> BOARD_ID[3]
|
||||
CFG_DISABLED, // 81 : GPIO[17] ->
|
||||
CFG_DISABLED, // 82 : GPIO[18] -> BOOT_CONFIG[0]
|
||||
CFG_DISABLED, // 83 : I2S1_MCK ->
|
||||
CFG_DISABLED, // 84 : I2S1_BCLK ->
|
||||
CFG_DISABLED, // 85 : I2S1_LRCK ->
|
||||
CFG_DISABLED, // 86 : I2S1_DIN ->
|
||||
CFG_DISABLED, // 87 : I2S1_DOUT ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // 88 : UART3_TXD ->
|
||||
CFG_DISABLED, // 89 : UART3_RXD ->
|
||||
CFG_DISABLED, // 90 : UART3_RTSN ->
|
||||
CFG_DISABLED, // 91 : UART3_CTSN ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 12 */
|
||||
CFG_IN, // 96 : MENU_KEY_L -> REQUEST_DFU2
|
||||
CFG_IN, // 97 : HOLD_KEY_L -> REQUEST_DFU1
|
||||
CFG_DISABLED, // 98 : SKEY_L ->
|
||||
CFG_DISABLED, // 99 : SPI3_SCLK ->
|
||||
CFG_DISABLED, // 100 : SPI3_MOSI ->
|
||||
CFG_DISABLED, // 101 : SPI3_MISO ->
|
||||
CFG_DISABLED, // 102 : SPI3_SSIN ->
|
||||
CFG_FUNC0, // 103 : SPI0_SCLK -> SPI0_SCLK/BOARD_ID[0]
|
||||
|
||||
/* Port 13 */
|
||||
CFG_FUNC0, // 104 : SPI0_MOSI -> SPI0_MOSI/BOARD_ID[1]
|
||||
CFG_FUNC0, // 105 : SPI0_MISO -> SPI0_MISO/BOARD_ID[2]
|
||||
CFG_OUT_1, // 106 : SPI0_SSIN -> SPI0_CS
|
||||
CFG_DISABLED, // 107 : UART0_TXD ->
|
||||
CFG_DISABLED, // 108 : UART0_RXD ->
|
||||
CFG_DISABLED, // 109 : UART6_TXD ->
|
||||
CFG_DISABLED, // 110 : UART6_RXD ->
|
||||
CFG_DISABLED, // 111 : TMR32_PWM0 ->
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : TMR32_PWM1 ->
|
||||
CFG_DISABLED, // 113 : TMR32_PWM2 ->
|
||||
CFG_DISABLED, // 114 : I2C1_SDA ->
|
||||
CFG_DISABLED, // 115 : I2C1_SCL ->
|
||||
CFG_DISABLED, // 116 : GPIO[19] ->
|
||||
CFG_DISABLED, // 117 : GPIO[20] ->
|
||||
CFG_DISABLED, // 118 : GPIO[21] ->
|
||||
CFG_DISABLED, // 119 : GPIO[22] ->
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // 120 : GPIO[23] ->
|
||||
CFG_DISABLED, // 121 : GPIO[24] ->
|
||||
CFG_DISABLED, // 122 : GPIO[25] -> BOOT_CONFIG[1]
|
||||
CFG_IN | PULL_DOWN, // 123 : GPIO[26] -> FORCE_DFU
|
||||
CFG_DISABLED | PULL_DOWN, // 124 : PMGR_MOSI -> DFU_STATUS
|
||||
CFG_DISABLED, // 125 : PMGR_MISO ->
|
||||
CFG_DISABLED, // 126 : PMGR_SCLK0 ->
|
||||
CFG_DISABLED, // 127 : PMGR_SSCLK1 ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED, // 128 : SOCHOT0 ->
|
||||
CFG_DISABLED, // 129 : SOCHOT1 ->
|
||||
CFG_DISABLED, // 130 : EDP_HPD ->
|
||||
CFG_DISABLED, // 131 : I2S3_MCK ->
|
||||
CFG_DISABLED, // 132 : I2S3_BCLK ->
|
||||
CFG_DISABLED, // 133 : I2S3_LRCK ->
|
||||
CFG_DISABLED, // 134 : I2S3_DOUT ->
|
||||
CFG_DISABLED, // 135 : I2S3_DIN ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // 136 : GPIO[27] ->
|
||||
CFG_DISABLED, // 137 : GPIO[28] -> BOOT_CONFIG[2]
|
||||
CFG_DISABLED, // 138 : GPIO[29] -> BOARD_ID[4]
|
||||
CFG_DISABLED, // 139 : GPIO[30] ->
|
||||
CFG_DISABLED, // 140 : GPIO[31] ->
|
||||
CFG_DISABLED, // 141 : GPIO[32] ->
|
||||
CFG_DISABLED, // 142 : GPIO[33] ->
|
||||
CFG_DISABLED, // 143 : GPIO[34] ->
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED, // 144 : GPIO[35] ->
|
||||
CFG_DISABLED, // 145 : GPIO[36] ->
|
||||
CFG_DISABLED, // 146 : GPIO[37] ->
|
||||
CFG_DISABLED, // 147 : GPIO[38] ->
|
||||
CFG_DISABLED, // 148 : GPIO[39] ->
|
||||
CFG_DISABLED, // 149 : GPIO[40] ->
|
||||
CFG_DISABLED, // 150 : GPIO[41] ->
|
||||
CFG_DISABLED, // 151 : GPIO[42] ->
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // 160 : PCIE_PERST0_N -> NAND_PERST
|
||||
CFG_DISABLED, // 161 : PCIE_PERST1_N ->
|
||||
CFG_DISABLED, // 162 : PCIE_PERST2_N ->
|
||||
CFG_DISABLED, // 163 : PCIE_PERST3_N ->
|
||||
CFG_DISABLED, // 164 : PCIE_CLKREQ0_N -> NAND_CLKREQ
|
||||
CFG_DISABLED, // 165 : PCIE_CLKREQ1_N ->
|
||||
CFG_DISABLED, // 166 : PCIE_CLKREQ2_N ->
|
||||
CFG_DISABLED, // 167 : PCIE_CLKREQ3_N ->
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED, // 192 : UART2_TXD ->
|
||||
CFG_DISABLED, // 193 : UART2_RXD ->
|
||||
CFG_DISABLED, // 194 : UART2_RTSN ->
|
||||
CFG_DISABLED, // 195 : UART2_CTSN ->
|
||||
CFG_DISABLED, // 196 : NAND_SYS_CLK -> NAND_SYS_CLK
|
||||
CFG_DISABLED, // 197 : S3E_RESETN -> NAND_RESET
|
||||
CFG_DISABLED, // 198 : TST_CLKOUT ->
|
||||
CFG_DISABLED,
|
||||
};
|
||||
|
||||
static const uint32_t gpio_1_default_cfg[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED, // 0 : AOP_SPI_SCLK ->
|
||||
CFG_DISABLED, // 1 : AOP_SPI_MOSI ->
|
||||
CFG_DISABLED, // 2 : AOP_SPI_MISO ->
|
||||
CFG_DISABLED, // 3 : AOP_UART1_TXD ->
|
||||
CFG_DISABLED, // 4 : AOP_UART1_RXD ->
|
||||
CFG_DISABLED, // 5 : AOP_UART0_TXD ->
|
||||
CFG_DISABLED, // 6 : AOP_UART0_RXD ->
|
||||
CFG_DISABLED, // 7 : AOP_UART2_TXD ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED, // 8 : AOP_UART2_RXD ->
|
||||
CFG_DISABLED, // 9 : AOP_I2CM_SDA ->
|
||||
CFG_DISABLED, // 10 : AOP_I2CM_SCL ->
|
||||
CFG_DISABLED, // 11 : AOP_FUNC[0] ->
|
||||
CFG_DISABLED, // 12 : AOP_FUNC[1] ->
|
||||
CFG_DISABLED, // 13 : AOP_FUNC[2] ->
|
||||
CFG_DISABLED, // 14 : AOP_FUNC[3] ->
|
||||
CFG_DISABLED, // 15 : AOP_FUNC[4] ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // 16 : AOP_FUNC[5] ->
|
||||
CFG_DISABLED, // 17 : AOP_FUNC[6] ->
|
||||
CFG_DISABLED, // 18 : AOP_FUNC[7] ->
|
||||
CFG_DISABLED, // 19 : AOP_FUNC[8] ->
|
||||
CFG_DISABLED, // 20 : AOP_FUNC[9] ->
|
||||
CFG_DISABLED, // 21 : AOP_SWD_TCK_OUT ->
|
||||
CFG_DISABLED, // 22 : AOP_SWD_TMS0 ->
|
||||
CFG_DISABLED, // 23 : AOP_SWD_TMS1 ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // 24 : AOP_I2S_MCK ->
|
||||
CFG_DISABLED, // 25 : AOP_I2S_BCLK ->
|
||||
CFG_DISABLED, // 26 : AOP_I2S_LRCK ->
|
||||
CFG_DISABLED, // 27 : AOP_I2S_DIN ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
switch (gpioc) {
|
||||
case 0:
|
||||
return gpio_default_cfg;
|
||||
case 1:
|
||||
return gpio_1_default_cfg;
|
||||
default:
|
||||
panic("unknown gpio controller %u", gpioc);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,353 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <stdint.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED, // 0 : SPI1_SCLK ->
|
||||
CFG_DISABLED, // 1 : SPI1_MOSI ->
|
||||
CFG_DISABLED, // 2 : SPI1_MISO ->
|
||||
CFG_DISABLED, // 3 : SPI1_SSIN ->
|
||||
CFG_DISABLED, // 4 : ISP_I2C0_SDA ->
|
||||
CFG_DISABLED, // 5 : ISP_I2C0_SCL ->
|
||||
CFG_DISABLED, // 6 : ISP_I2C0_SDA ->
|
||||
CFG_DISABLED, // 7 : ISP_I2C0_SCL ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED, // 8 : SENSOR0_ISTRB ->
|
||||
CFG_DISABLED, // 9 : SENSOR0_RST ->
|
||||
CFG_DISABLED, // 10 : SENSOR0_CLK ->
|
||||
CFG_DISABLED, // 11 : SENSOR0_XSHUTDOWN ->
|
||||
CFG_DISABLED, // 12 : SENSOR1_ISTRB ->
|
||||
CFG_DISABLED, // 13 : SENSOR1_RST ->
|
||||
CFG_DISABLED, // 14 : SENSOR1_CLK ->
|
||||
CFG_DISABLED, // 15 : SENSOR1_XSHUTDOWN ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // 16 : GPIO[16] -> BOARD_ID[3]
|
||||
CFG_DISABLED, // 17 : GPIO[17] ->
|
||||
CFG_DISABLED, // 18 : GPIO[18] -> BOOT_CONFIG[0]
|
||||
CFG_DISABLED, // 19 : I2S1_MCK ->
|
||||
CFG_DISABLED, // 20 : I2S1_BLCK ->
|
||||
CFG_DISABLED, // 21 : I2S1_LRCK ->
|
||||
CFG_DISABLED, // 22 : I2S1_DIN ->
|
||||
CFG_DISABLED, // 23 : I2S1_DOUT ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // 24 : NAND_SYS_CLK ->
|
||||
CFG_DISABLED, // 25 : S3E0_RESETN ->
|
||||
CFG_DISABLED, // 26 : S3E1_RESETN ->
|
||||
CFG_DISABLED, // 27 : UART1_TXD ->
|
||||
CFG_DISABLED, // 28 : UART1_RXD ->
|
||||
CFG_DISABLED, // 29 : UART1_RTSN ->
|
||||
CFG_DISABLED, // 30 : UART1_CTSN ->
|
||||
CFG_DISABLED, // 31 : GPIO43 ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED, // 32 : I2S0_BCLK ->
|
||||
CFG_DISABLED, // 33 : I2S0_LRCK ->
|
||||
CFG_DISABLED, // 34 : I2S0_DIN ->
|
||||
CFG_DISABLED, // 35 : I2S0_DOUT ->
|
||||
CFG_DISABLED, // 36 : I2S0_MCK ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // 64 : I2S4_MCK ->
|
||||
CFG_DISABLED, // 65 : I2S4_BCLK ->
|
||||
CFG_DISABLED, // 66 : I2S4_LRCK ->
|
||||
CFG_DISABLED, // 67 : I2S4_DIN ->
|
||||
CFG_DISABLED, // 68 : I2S4_DOUT ->
|
||||
CFG_DISABLED, // 69 : I2S2_MCK ->
|
||||
CFG_DISABLED, // 70 : I2S2_BCLK ->
|
||||
CFG_DISABLED, // 71 : I2S2_LRCK ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // 72 : I2S2_DIN ->
|
||||
CFG_DISABLED, // 73 : I2S2_DOUT ->
|
||||
CFG_DISABLED, // 74 : GPIO[0] ->
|
||||
CFG_DISABLED, // 75 : GPIO[1] ->
|
||||
CFG_DISABLED, // 76 : GPIO[2] ->
|
||||
CFG_DISABLED, // 77 : GPIO[3] ->
|
||||
CFG_DISABLED, // 78 : GPIO[4] ->
|
||||
CFG_DISABLED, // 79 : GPIO[5] ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // 80 : GPIO[6] ->
|
||||
CFG_DISABLED, // 81 : GPIO[7] ->
|
||||
CFG_DISABLED, // 82 : GPIO[8] ->
|
||||
CFG_DISABLED, // 83 : GPIO[9] ->
|
||||
CFG_DISABLED, // 84 : GPIO[10] ->
|
||||
CFG_DISABLED, // 85 : GPIO[11] ->
|
||||
CFG_DISABLED, // 86 : GPIO[12] ->
|
||||
CFG_DISABLED, // 87 : GPIO[13] ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // 88 : GPIO[14] ->
|
||||
CFG_DISABLED, // 89 : GPIO[15] ->
|
||||
CFG_DISABLED, // 90 : UART3_TXD ->
|
||||
CFG_DISABLED, // 91 : UART3_RXD ->
|
||||
CFG_DISABLED, // 92 : UART3_RTSN ->
|
||||
CFG_DISABLED, // 93 : UART3_CTSN ->
|
||||
CFG_FUNC0, // 94 : SPI0_SCLK -> SPI0_SCLK/BOARD_ID[0]
|
||||
CFG_FUNC0, // 95 : SPI0_MOSI -> SPI0_MOSI/BOARD_ID[1]
|
||||
|
||||
/* Port 12 */
|
||||
CFG_FUNC0, // 96 : SPI0_MISO -> SPI0_MISO/BOARD_ID[2]
|
||||
CFG_OUT_1, // 97 : SPI0_SSIN -> SPI0_CS
|
||||
CFG_DISABLED, // 98 : PCIE_PERST0_N -> NAND_PERST
|
||||
CFG_DISABLED, // 99 : PCIE_PERST1_N ->
|
||||
CFG_DISABLED, // 100 : PCIE_PERST2_N ->
|
||||
CFG_DISABLED, // 101 : PCIE_PERST3_N ->
|
||||
CFG_DISABLED, // 102 : PCIE_PERST4_N ->
|
||||
CFG_DISABLED, // 103 : PCIE_PERST5_N ->
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // 104 : PCIE_CLKREQ0_N -> NAND_CLKREQ
|
||||
CFG_DISABLED, // 105 : PCIE_CLKREQ1_N ->
|
||||
CFG_DISABLED, // 106 : PCIE_CLKREQ2_N ->
|
||||
CFG_DISABLED, // 107 : PCIE_CLKREQ3_N ->
|
||||
CFG_DISABLED, // 108 : PCIE_CLKREQ4_N ->
|
||||
CFG_DISABLED, // 109 : PCIE_CLKREQ5_N ->
|
||||
CFG_DISABLED, // 110 : UART2_TXD ->
|
||||
CFG_DISABLED, // 111 : UART2_RXD ->
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // 112 : UART2_RTSN ->
|
||||
CFG_DISABLED, // 113 : UART2_CTSN ->
|
||||
CFG_DISABLED, // 114 : I2C3_SDA ->
|
||||
CFG_DISABLED, // 115 : I2C3_SCL ->
|
||||
CFG_DISABLED, // 116 : GPIO[44] ->
|
||||
CFG_DISABLED, // 117 : GPIO[45] ->
|
||||
CFG_DISABLED, // 118 : GPIO[46] ->
|
||||
CFG_DISABLED, // 119 : GPIO[47] ->
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // 120 : GPIO[48] ->
|
||||
CFG_DISABLED, // 121 : GPIO[49] ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 16 */
|
||||
CFG_IN, // 128 : MENU_KEY_L -> REQUEST_DFU2
|
||||
CFG_IN, // 129 : HOLD_KEY_L -> REQUEST_DFU1
|
||||
CFG_DISABLED, // 130 : SKEY_L ->
|
||||
CFG_DISABLED, // 131 : SWD_TMS2 ->
|
||||
CFG_DISABLED, // 132 : SWD_TMS3 ->
|
||||
CFG_DISABLED, // 133 : UART5_RTXD ->
|
||||
CFG_DISABLED, // 134 : I2C2_SDA ->
|
||||
CFG_DISABLED, // 135 : I2C2_SCL ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // 136 : UART4_TXD ->
|
||||
CFG_DISABLED, // 137 : UART4_RXD ->
|
||||
CFG_DISABLED, // 138 : UART4_RTSN ->
|
||||
CFG_DISABLED, // 139 : UART4_CTSN ->
|
||||
CFG_DISABLED, // 140 : UART7_TXD ->
|
||||
CFG_DISABLED, // 141 : UART7_RXD ->
|
||||
CFG_DISABLED, // 142 : CLK32K_OUT ->
|
||||
CFG_DISABLED, // 143 : DP_WAKEUP0 ->
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED, // 144 : DP_WAKEUP0 ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // 160 : SPI2_SCLK ->
|
||||
CFG_DISABLED, // 161 : SPI2_MOSI ->
|
||||
CFG_DISABLED, // 162 : SPI2_MISO ->
|
||||
CFG_DISABLED, // 163 : SPI2_SSIN ->
|
||||
CFG_DISABLED, // 164 : I2C0_SDA ->
|
||||
CFG_DISABLED, // 165 : I2C0_SCL ->
|
||||
CFG_DISABLED, // 166 : SPI3_SCLK ->
|
||||
CFG_DISABLED, // 167 : SPI3_MOSI ->
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // 168 : SPI3_MISO ->
|
||||
CFG_DISABLED, // 169 : SPI3_SSIN ->
|
||||
CFG_DISABLED, // 170 : UART0_TXD ->
|
||||
CFG_DISABLED, // 171 : UART0_RXD ->
|
||||
CFG_DISABLED, // 172 : UART6_TXD ->
|
||||
CFG_DISABLED, // 173 : UART6_RXD ->
|
||||
CFG_DISABLED, // 174 : TMR32_PWM0 ->
|
||||
CFG_DISABLED, // 175 : TMR32_PWM1 ->
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED, // 176 : TMR32_PWM2 ->
|
||||
CFG_DISABLED, // 177 : I2C1_SDA ->
|
||||
CFG_DISABLED, // 178 : I2C1_SCL ->
|
||||
CFG_DISABLED, // 179 : GPIO[19] ->
|
||||
CFG_DISABLED, // 180 : GPIO[20] ->
|
||||
CFG_DISABLED, // 181 : GPIO[21] ->
|
||||
CFG_DISABLED, // 182 : GPIO[22] ->
|
||||
CFG_DISABLED, // 183 : GPIO[23] ->
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED, // 184 : GPIO[24] ->
|
||||
CFG_DISABLED, // 185 : GPIO[25] -> BOOT_CONFIG[1]
|
||||
CFG_IN | PULL_DOWN, // 186 : GPIO[26] -> FORCE_DFU
|
||||
CFG_DISABLED, // 187 : PSPI_MOSI ->
|
||||
CFG_DISABLED, // 188 : DWI_DO ->
|
||||
CFG_DISABLED, // 189 : PMGR_MISO ->
|
||||
CFG_DISABLED, // 190 : PMGR_SCLK0 ->
|
||||
CFG_DISABLED, // 191 : PMGR_SSCLK1 ->
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED, // 192 : DROOP ->
|
||||
CFG_DISABLED, // 193 : SOCHOT1 ->
|
||||
CFG_DISABLED, // 194 : EDP_HPD0 ->
|
||||
CFG_DISABLED, // 195 : EDP_HPD1 ->
|
||||
CFG_DISABLED, // 196 : I2S3_MCK ->
|
||||
CFG_DISABLED, // 197 : I2S3_BCLK ->
|
||||
CFG_DISABLED, // 198 : I2S3_LRCK ->
|
||||
CFG_DISABLED, // 199 : I2S3_DOUT ->
|
||||
|
||||
/* Port 25 */
|
||||
CFG_DISABLED, // 200 : I2S3_DIN ->
|
||||
CFG_DISABLED | PULL_DOWN, // 201 : GPIO[27] -> DFU_STATUS
|
||||
CFG_DISABLED, // 202 : GPIO[28] -> BOOT_CONFIG[2]
|
||||
CFG_DISABLED, // 203 : GPIO[29] -> BOARD_ID[4]
|
||||
CFG_DISABLED, // 204 : GPIO[30] ->
|
||||
CFG_DISABLED, // 205 : GPIO[31] ->
|
||||
CFG_DISABLED, // 206 : GPIO[32] ->
|
||||
CFG_DISABLED, // 207 : GPIO[33] ->
|
||||
|
||||
/* Port 26 */
|
||||
CFG_DISABLED, // 208 : GPIO[34] ->
|
||||
CFG_DISABLED, // 209 : GPIO[35] ->
|
||||
CFG_DISABLED, // 210 : GPIO[36] ->
|
||||
CFG_DISABLED, // 211 : GPIO[37] ->
|
||||
CFG_DISABLED, // 212 : GPIO[38] ->
|
||||
CFG_DISABLED, // 213 : GPIO[39] ->
|
||||
CFG_DISABLED, // 214 : GPIO[40] ->
|
||||
CFG_DISABLED, // 215 : GPIO[41] ->
|
||||
|
||||
/* Port 27 */
|
||||
CFG_DISABLED, // 216 : GPIO[42] ->
|
||||
CFG_DISABLED, // 217 : TST_CLKOUT ->
|
||||
CFG_DISABLED, // 218 : GPU_TRIGGER1 ->
|
||||
CFG_DISABLED, // 219 : GPU_TRIGGER2 ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
};
|
||||
|
||||
static const uint32_t gpio_1_default_cfg[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED, // 0 : AOP_SPI_SCLK ->
|
||||
CFG_DISABLED, // 1 : AOP_SPI_MOSI ->
|
||||
CFG_DISABLED, // 2 : AOP_SPI_MISO ->
|
||||
CFG_DISABLED, // 3 : AOP_UART1_TXD ->
|
||||
CFG_DISABLED, // 4 : AOP_UART1_RXD ->
|
||||
CFG_DISABLED, // 5 : AOP_UART0_TXD ->
|
||||
CFG_DISABLED, // 6 : AOP_UART0_RXD ->
|
||||
CFG_DISABLED, // 7 : AOP_UART2_TXD ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED, // 8 : AOP_UART2_RXD ->
|
||||
CFG_DISABLED, // 9 : AOP_I2CM_SDA ->
|
||||
CFG_DISABLED, // 10 : AOP_I2CM_SCL ->
|
||||
CFG_DISABLED, // 11 : AOP_FUNC[0] ->
|
||||
CFG_DISABLED, // 12 : AOP_FUNC[1] ->
|
||||
CFG_DISABLED, // 13 : AOP_FUNC[2] ->
|
||||
CFG_DISABLED, // 14 : AOP_FUNC[3] ->
|
||||
CFG_DISABLED, // 15 : AOP_FUNC[4] ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // 16 : AOP_FUNC[5] ->
|
||||
CFG_DISABLED, // 17 : AOP_FUNC[6] ->
|
||||
CFG_DISABLED, // 18 : AOP_FUNC[7] ->
|
||||
CFG_DISABLED, // 19 : AOP_FUNC[8] ->
|
||||
CFG_DISABLED, // 20 : AOP_FUNC[9] ->
|
||||
CFG_DISABLED, // 21 : AOP_SWD_TCK_OUT ->
|
||||
CFG_DISABLED, // 22 : AOP_SWD_TMS0 ->
|
||||
CFG_DISABLED, // 23 : AOP_SWD_TMS1 ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // 24 : AOP_I2S_MCK ->
|
||||
CFG_DISABLED, // 25 : AOP_I2S_BCLK ->
|
||||
CFG_DISABLED, // 26 : AOP_I2S_LRCK ->
|
||||
CFG_DISABLED, // 27 : AOP_I2S_DIN ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
switch (gpioc) {
|
||||
case 0:
|
||||
return gpio_default_cfg;
|
||||
case 1:
|
||||
return gpio_1_default_cfg;
|
||||
default:
|
||||
panic("unknown gpio controller %u", gpioc);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,50 @@
|
||||
# Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
TARGET_BOOT_CPU_VOLTAGE=0 \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=0 \
|
||||
DISPLAY_FPGA_TUNABLES=1 \
|
||||
DCS_RUN_AT_50MHZ=1 \
|
||||
DCS_NUM_RANKS=1 \
|
||||
AMP_CALIBRATION_SKIP=1 \
|
||||
DCS_FIXUP_PARAMS=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_CPU_RAM=7 \
|
||||
BUCK_SOC=2 \
|
||||
BUCK_GPU=1 \
|
||||
BUCK_GPU_RAM=8 \
|
||||
WITH_CPU_APSC=1
|
||||
|
||||
OPTIONS += \
|
||||
SUPPORT_FPGA=1
|
||||
|
||||
ifeq ($(SUB_PLATFORM),s8001)
|
||||
OPTIONS += \
|
||||
DCS_NUM_CHANNELS=8
|
||||
else
|
||||
OPTIONS += \
|
||||
DCS_NUM_CHANNELS=4
|
||||
endif
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o
|
||||
|
||||
ifeq ($(SUB_PLATFORM),s8003)
|
||||
ALL_OBJS += $(LOCAL_DIR)/pinconfig_s8000fpga.o
|
||||
else
|
||||
ALL_OBJS += $(LOCAL_DIR)/pinconfig_$(SUB_TARGET).o
|
||||
endif
|
||||
Reference in new issue
Block a user