first and last commit
This commit is contained in:
Chris Nutter committed
commit
1bf4efd552
2612 files changed
+636500
No files matched your search
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_ADBE_SETTINGS_H
|
||||
#define __TARGET_ADBE_SETTINGS_H
|
||||
|
||||
static struct adbe_v2_tuneable adbe_tuneables[] = {
|
||||
{
|
||||
.name = "default",
|
||||
.adbe0_vblank_pos_vbi_pulse = 0x0000,
|
||||
.adbe0_vblank_clk_gate_wakeup = 0x0000,
|
||||
.adbe0_vblank_clk_gate_idle = 0x0001,
|
||||
.adbe0_vblank_busy_finish = 0,
|
||||
.adbe0_tunable_mode_ctrl = 0,
|
||||
.adbe0_aap_support = 1,
|
||||
.adbe0_aap_format_control_reg1 = (AAP_FORMAT_CONTROL_REG1_AUTOPOS | AAP_FORMAT_CONTROL_REG1_RSVD(8) | AAP_FORMAT_CONTROL_REG1_VS_POL),
|
||||
},
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#if SUB_PLATFORM_T7000
|
||||
#include <target/amcconfig_t7000.h>
|
||||
#elif SUB_PLATFORM_T7001
|
||||
#include <target/amcconfig_t7001.h>
|
||||
#endif
|
||||
@@ -0,0 +1,162 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The amc_param struct is defined in drivers/apple/amc/amc.h, and this
|
||||
* file should only by included from amc.c.
|
||||
*/
|
||||
|
||||
#define AMC_PARAMS_AP_DEV (1)
|
||||
|
||||
static const struct amc_param amc_params_dev = {
|
||||
.lat = 0x00040200,
|
||||
.phyrdwrtim = 0x00010802,
|
||||
.tREFi = 0x11,
|
||||
.pdn = 0x22000203,
|
||||
.derate = 0x04110111,
|
||||
.read = 0x00000101,
|
||||
.bustat = 0x00222209,
|
||||
.bustat2 = 0x00222209,
|
||||
.pwrmngten_default = 0x00100100,
|
||||
.schen_default = 0x00001110,
|
||||
.mcphyupdate = 0x15030000,
|
||||
.mcphyupdate1 = 0x00000003,
|
||||
.arefparam = 0x0ca2b532,
|
||||
.longsr = 0x05022008,
|
||||
.mr1 = 0x84,
|
||||
.mr2 = 0x06,
|
||||
.mr3 = 0x03,
|
||||
.addrcfg = 0x00020201,
|
||||
.mccchnldec = 0x00050010,
|
||||
.mcuchnhash = 0x0ffffd54,
|
||||
.mcschnldec = 0x00010200,
|
||||
.qbrparam = 0x00050200,
|
||||
.odts = 0x00000320,
|
||||
.addrmapmode = 0x00000601,
|
||||
|
||||
.freq = {
|
||||
{ // 800MHz
|
||||
.cas = 0x00000202,
|
||||
.pch = 0x00020202,
|
||||
.act = 0x04010202,
|
||||
.autoref = 0x01020000,
|
||||
.selfref = 0x00002020,
|
||||
.modereg = 0x20010722,
|
||||
},
|
||||
{ // 400MHz
|
||||
.cas = 0x00000002,
|
||||
.pch = 0x00000002,
|
||||
.act = 0x04010202,
|
||||
.autoref = 0x01020000,
|
||||
.selfref = 0x00002000,
|
||||
.modereg = 0x00010000,
|
||||
},
|
||||
{ // 200MHz
|
||||
.cas = 0x00000002,
|
||||
.pch = 0x00000002,
|
||||
.act = 0x04010202,
|
||||
.autoref = 0x01020000,
|
||||
.selfref = 0x00002000,
|
||||
.modereg = 0x00010000,
|
||||
},
|
||||
{ // 50MHz
|
||||
.cas = 0x00000002,
|
||||
.pch = 0x00000002,
|
||||
.act = 0x04010202,
|
||||
.autoref = 0x01020000,
|
||||
.selfref = 0x00002000,
|
||||
.modereg = 0x00010000,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static const struct amc_param amc_params_ap = {
|
||||
.lat = 0x00060300,
|
||||
.phyrdwrtim = 0x00020a04,
|
||||
.tREFi = 0x5d,
|
||||
.pdn = 0x22000403,
|
||||
.derate = 0x24831359,
|
||||
.read = 0x00000203,
|
||||
.bustat = 0x00222209,
|
||||
.bustat2 = 0x00222209,
|
||||
.pwrmngten_default = 0x00100100,
|
||||
.schen_default = 0x00001110,
|
||||
.mcphyupdate = 0x15030000,
|
||||
.mcphyupdate1 = 0x00000003,
|
||||
.arefparam = 0x0ca2b532,
|
||||
.longsr = 0x05022008,
|
||||
.mr1 = 0x44,
|
||||
.mr2 = 0x1a,
|
||||
.mr3 = 0x03,
|
||||
.addrcfg = 0x00020201,
|
||||
.mccchnldec = 0x00050010,
|
||||
.mcuchnhash = 0x0ffffd54,
|
||||
.mcschnldec = 0x00010200,
|
||||
.qbrparam = 0x00050200,
|
||||
.odts = 0x00000320,
|
||||
.addrmapmode = 0x00000601,
|
||||
|
||||
.freq = {
|
||||
{ // 800MHz
|
||||
.cas = 0x00000308,
|
||||
.pch = 0x00030612,
|
||||
.act = 0x12040908,
|
||||
.autoref = 0x19350000,
|
||||
.selfref = 0x00039060,
|
||||
.modereg = 0x20250782,
|
||||
},
|
||||
{ // 400MHz
|
||||
.cas = 0x00000005,
|
||||
.pch = 0x00000009,
|
||||
.act = 0x09020505,
|
||||
.autoref = 0x0d1b0000,
|
||||
.selfref = 0x0001d000,
|
||||
.modereg = 0x00130000,
|
||||
},
|
||||
{ // 200MHz
|
||||
.cas = 0x00000003,
|
||||
.pch = 0x00000005,
|
||||
.act = 0x05010303,
|
||||
.autoref = 0x070e0000,
|
||||
.selfref = 0x0000f000,
|
||||
.modereg = 0x000a0000,
|
||||
},
|
||||
{ // 50MHz
|
||||
.cas = 0x00000002,
|
||||
.pch = 0x00000002,
|
||||
.act = 0x04010202,
|
||||
.autoref = 0x02040000,
|
||||
.selfref = 0x00004000,
|
||||
.modereg = 0x00030000,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static const struct amc_tunable amc_tunables[] = {
|
||||
{ &rAMC_MCSARBCFG, 0x00000001 },
|
||||
{ &rAMC_OPIDLETMR, 0x00200000 },
|
||||
{ &rAMC_OPTMRADJPARAM, 0x20400064 },
|
||||
{ &rAMC_MIFACTSCH, 0x00000001 },
|
||||
{ &rAMC_MIFCASSCH_FREQ(0), 0x10000010 },
|
||||
{ &rAMC_PSQRQCTL0, 0xff010110 },
|
||||
{ &rAMC_PSQRQCTL1, 0x00001700 },
|
||||
{ &rAMC_PSQRQTIMER0, 0x00000040 },
|
||||
{ &rAMC_PSQRQTIMER1, 0x00000014 },
|
||||
{ &rAMC_PSQRQTIMER2, 0x00000040 },
|
||||
{ &rAMC_PSQRQBRST, 0x04100410 },
|
||||
{ &rAMC_PSQRQSCHCRD, 0x00101400 },
|
||||
{ &rAMC_PSQWQCTL0, 0x00010100 },
|
||||
{ &rAMC_PSQWQCTL1, 0x00000158 },
|
||||
{ &rAMC_PSQWQBRST, 0x04080410 },
|
||||
{ &rAMC_PSQWQSCHCRD, 0x00101400 },
|
||||
{ &rAMC_MCUQOSLLT, 0x0000011f },
|
||||
{ &rAMC_PWRMNGTPARAM, 0x01803000 },
|
||||
};
|
||||
@@ -0,0 +1,164 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The amc_param struct is defined in drivers/apple/amc/amc.h, and this
|
||||
* file should only by included from amc.c.
|
||||
*/
|
||||
|
||||
#define AMC_PARAMS_AP_DEV (1)
|
||||
|
||||
static const struct amc_param amc_params_dev = {
|
||||
.lat = 0x00040200,
|
||||
.phyrdwrtim = 0x00010802,
|
||||
.tREFi = 0x11,
|
||||
.pdn = 0x22000203,
|
||||
.derate = 0x04110111,
|
||||
.read = 0x00000101,
|
||||
.bustat = 0x00222209,
|
||||
.bustat2 = 0x00222209,
|
||||
.pwrmngten_default = 0x00100100,
|
||||
.schen_default = 0x00001110,
|
||||
.mcphyupdate = 0x15030000,
|
||||
.mcphyupdate1 = 0x00000003,
|
||||
.arefparam = 0x0ca2b532,
|
||||
.longsr = 0x05022008,
|
||||
.mr1 = 0x84,
|
||||
.mr2 = 0x06,
|
||||
.mr3 = 0x03,
|
||||
.addrcfg = 0x00020201,
|
||||
.mccchnldec = 0x00050020,
|
||||
.mcuchnhash = 0x0ffffd54,
|
||||
.mcuchnhash2 = 0x0aaaaaa8,
|
||||
.mcschnldec = 0x00020200,
|
||||
.qbrparam = 0x00050200,
|
||||
.odts = 0x00000320,
|
||||
.addrmapmode = 0x00000501,
|
||||
|
||||
.freq = {
|
||||
{ // 800MHz
|
||||
.cas = 0x00000202,
|
||||
.pch = 0x00020202,
|
||||
.act = 0x04010202,
|
||||
.autoref = 0x01020000,
|
||||
.selfref = 0x00002020,
|
||||
.modereg = 0x20010722,
|
||||
},
|
||||
{ // 400MHz
|
||||
.cas = 0x00000002,
|
||||
.pch = 0x00000002,
|
||||
.act = 0x04010202,
|
||||
.autoref = 0x01020000,
|
||||
.selfref = 0x00002000,
|
||||
.modereg = 0x00010000,
|
||||
},
|
||||
{ // 200MHz
|
||||
.cas = 0x00000002,
|
||||
.pch = 0x00000002,
|
||||
.act = 0x04010202,
|
||||
.autoref = 0x01020000,
|
||||
.selfref = 0x00002000,
|
||||
.modereg = 0x00010000,
|
||||
},
|
||||
{ // 50MHz
|
||||
.cas = 0x00000002,
|
||||
.pch = 0x00000002,
|
||||
.act = 0x04010202,
|
||||
.autoref = 0x01020000,
|
||||
.selfref = 0x00002000,
|
||||
.modereg = 0x00010000,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static const struct amc_param amc_params_ap = {
|
||||
.lat = 0x00060300,
|
||||
.phyrdwrtim = 0x00020a04,
|
||||
.tREFi = 0x5d,
|
||||
.pdn = 0x22000403,
|
||||
.derate = 0x24831359,
|
||||
.read = 0x00000203,
|
||||
.bustat = 0x00222209,
|
||||
.bustat2 = 0x00222209,
|
||||
.pwrmngten_default = 0x00100100,
|
||||
.schen_default = 0x00001110,
|
||||
.mcphyupdate = 0x15030000,
|
||||
.mcphyupdate1 = 0x00000001,
|
||||
.arefparam = 0x0ca2b532,
|
||||
.longsr = 0x05022008,
|
||||
.mr1 = 0x44,
|
||||
.mr2 = 0x1a,
|
||||
.mr3 = 0x03,
|
||||
.addrcfg = 0x00020201,
|
||||
.mccchnldec = 0x00050020,
|
||||
.mcuchnhash = 0x0ffffd54,
|
||||
.mcuchnhash2 = 0x0aaaaaa8,
|
||||
.mcschnldec = 0x00020200,
|
||||
.qbrparam = 0x00050200,
|
||||
.odts = 0x00000320,
|
||||
.addrmapmode = 0x00000501,
|
||||
|
||||
.freq = {
|
||||
{ // 800MHz
|
||||
.cas = 0x00000308,
|
||||
.pch = 0x00030612,
|
||||
.act = 0x12040908,
|
||||
.autoref = 0x19350000,
|
||||
.selfref = 0x00039060,
|
||||
.modereg = 0x20250782,
|
||||
},
|
||||
{ // 400MHz
|
||||
.cas = 0x00000005,
|
||||
.pch = 0x00000009,
|
||||
.act = 0x09020505,
|
||||
.autoref = 0x0d1b0000,
|
||||
.selfref = 0x0001d000,
|
||||
.modereg = 0x00130000,
|
||||
},
|
||||
{ // 200MHz
|
||||
.cas = 0x00000003,
|
||||
.pch = 0x00000005,
|
||||
.act = 0x05010303,
|
||||
.autoref = 0x070e0000,
|
||||
.selfref = 0x0000f000,
|
||||
.modereg = 0x000a0000,
|
||||
},
|
||||
{ // 50MHz
|
||||
.cas = 0x00000002,
|
||||
.pch = 0x00000002,
|
||||
.act = 0x04010202,
|
||||
.autoref = 0x02040000,
|
||||
.selfref = 0x00004000,
|
||||
.modereg = 0x00030000,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static const struct amc_tunable amc_tunables[] = {
|
||||
{ &rAMC_MCSARBCFG, 0x00000001 },
|
||||
{ &rAMC_OPIDLETMR, 0x00200000 },
|
||||
{ &rAMC_OPTMRADJPARAM, 0x20400064 },
|
||||
{ &rAMC_MIFACTSCH, 0x00000001 },
|
||||
{ &rAMC_MIFCASSCH_FREQ(0), 0x10000010 },
|
||||
{ &rAMC_PSQRQCTL0, 0xff010110 },
|
||||
{ &rAMC_PSQRQCTL1, 0x00001700 },
|
||||
{ &rAMC_PSQRQTIMER0, 0x00000040 },
|
||||
{ &rAMC_PSQRQTIMER1, 0x00000014 },
|
||||
{ &rAMC_PSQRQTIMER2, 0x00000040 },
|
||||
{ &rAMC_PSQRQBRST, 0x04100410 },
|
||||
{ &rAMC_PSQRQSCHCRD, 0x00101400 },
|
||||
{ &rAMC_PSQWQCTL0, 0x00010100 },
|
||||
{ &rAMC_PSQWQCTL1, 0x00000336 },
|
||||
{ &rAMC_PSQWQBRST, 0x04080410 },
|
||||
{ &rAMC_PSQWQSCHCRD, 0x00101400 },
|
||||
{ &rAMC_MCUQOSLLT, 0x0000011f },
|
||||
{ &rAMC_PWRMNGTPARAM, 0x03523000 },
|
||||
};
|
||||
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The amc_phy_params struct is defined in drivers/apple/amp_v3/amp_v3.h, and this
|
||||
* file should only by included from amp_v3.c.
|
||||
*/
|
||||
|
||||
static const struct amp_params amc_phy_params = {
|
||||
.freq = {
|
||||
{
|
||||
.caoutdllscl = 0x00000008,
|
||||
.dqsindllscl = 0x00000008,
|
||||
.rdcapcfg = 0x01010304,
|
||||
},
|
||||
{
|
||||
.caoutdllscl = 0x00000010,
|
||||
.dqsindllscl = 0x00000010,
|
||||
.rdcapcfg = 0x21010309,
|
||||
},
|
||||
{
|
||||
.caoutdllscl = 0x00000020,
|
||||
.dqsindllscl = 0x00000020,
|
||||
.rdcapcfg = 0x41010306,
|
||||
},
|
||||
{
|
||||
.caoutdllscl = 0x0000003f,
|
||||
.dqsindllscl = 0x0000003f,
|
||||
.rdcapcfg = 0x61010304,
|
||||
},
|
||||
},
|
||||
.ampclk = 0x00010000,
|
||||
};
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_ASPNANDCONFIG_H
|
||||
#define __TARGET_ASPNANDCONFIG_H
|
||||
|
||||
//MLC devices
|
||||
#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_ERASE_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_READ_DIES_IN_PARALLEL 4
|
||||
#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
|
||||
//TLC devices
|
||||
#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 8
|
||||
#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
|
||||
|
||||
// rdar://problem/18371949 - these values should be the same for post-OkemoTaos targets
|
||||
#define ASPNAND_INDIRECTION_MEMORY (2*1024*1024)
|
||||
#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_GPIODEF_H
|
||||
#define __TARGET_GPIODEF_H
|
||||
|
||||
/* T7000FPGA specific gpio -> pin mappings */
|
||||
|
||||
#include <platform/gpio.h>
|
||||
|
||||
/* define target-specific gpios in a generic fashion here. */
|
||||
|
||||
#endif /* ! __TARGET_GPIODEF_H */
|
||||
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#if SUB_PLATFORM_T7000
|
||||
#include <target/pinconfig_t7000.h>
|
||||
#elif SUB_PLATFORM_T7001
|
||||
#include <target/pinconfig_t7001.h>
|
||||
#endif
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (C) 2012, 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __TARGET_UARTCONFIG_H
|
||||
#define __TARGET_UARTCONFIG_H
|
||||
|
||||
/* define one debug serial ports */
|
||||
#define DEBUG_SERIAL_PORT (0)
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define UART_OVERSAMPLE_OVERRIDE (11)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,242 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/flash_nor.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/mib.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <sys.h>
|
||||
#include <sys/menu.h>
|
||||
#include <sys/task.h>
|
||||
#include <target.h>
|
||||
|
||||
#if !SUPPORT_FPGA
|
||||
#error "FPGA target without SUPPORT_FPGA set"
|
||||
#endif
|
||||
|
||||
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 1);
|
||||
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
|
||||
|
||||
void target_early_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_late_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_init(void)
|
||||
{
|
||||
#if WITH_HW_FLASH_NOR
|
||||
flash_nor_init(SPI_NOR0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void target_quiesce_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
void target_poweroff(void)
|
||||
{
|
||||
}
|
||||
|
||||
int target_bootprep(enum boot_target target)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_recover(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool target_should_poweron(bool *cold_button_boot)
|
||||
{
|
||||
*cold_button_boot = true;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool target_should_poweroff(bool at_boot)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if !PRODUCT_LLB
|
||||
bool target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
void * target_get_display_configuration(void)
|
||||
{
|
||||
return ((void *)(NULL));
|
||||
}
|
||||
|
||||
#if WITH_ENV
|
||||
|
||||
void target_setup_default_environment(void)
|
||||
{
|
||||
env_set("boot-args", " debug=0x14e serial=3 amfi_unrestrict_task_for_pid=1 amfi_allow_any_signature=1 amfi_get_out_of_my_way=1 cs_enforcement_disable=1 fips_mode=0", 0);
|
||||
// boot-device is set in platform's init.c
|
||||
env_set("display-color-space","RGB888", 0);
|
||||
env_set("display-timing", "fpga-wsvga", 0);
|
||||
env_set("ramdisk-delay", "30000000", 0); /* This tells PurpleRestore to slow down; rdar://6345846 */
|
||||
env_set("idle-off", "false", 0);
|
||||
env_set("bootdelay", "3", 0);
|
||||
env_set("debug-uarts", "3", 0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
#define MAX_NODES_PER_DEVICE 3
|
||||
struct fpgaNode_t
|
||||
{
|
||||
uint32_t mask; // Block enable mask
|
||||
const char *nodeName[MAX_NODES_PER_DEVICE]; // Device tree nodes to disable if block is absent
|
||||
};
|
||||
|
||||
// Devices tree nodes to disable based upon FPGA block instantiation
|
||||
struct fpgaNode_t fpgaNodes[] = {
|
||||
{ FPGA_HAS_PCIE, { "arm-io/apcie", "arm-io/dart-apcie0", "arm-io/dart-apcie0/mapper-apcie0" }},
|
||||
{ FPGA_HAS_PCIE, { "arm-io/apcie", "arm-io/dart-apcie1", "arm-io/dart-apcie1/mapper-apcie1" }},
|
||||
{ FPGA_HAS_VXD, { "arm-io/vxd", NULL, NULL }},
|
||||
{ FPGA_HAS_AVE, { "arm-io/ave", "arm-io/dart-ave", "arm-io/dart-ave/mapper-ave" }},
|
||||
{ FPGA_HAS_ISP, { "arm-io/isp", "arm-io/dart-isp", "arm-io/dart-isp/mapper-isp" }},
|
||||
{ FPGA_HAS_DISP0, { "arm-io/disp0", "arm-io/dart-disp0", "arm-io/dart-disp0/mapper-disp0" }},
|
||||
{ FPGA_HAS_DISP1, { "arm-io/disp1", "arm-io/dart-disp1", "arm-io/dart-disp1/mapper-disp1" }},
|
||||
{ FPGA_HAS_MSR, { "arm-io/scaler0", "arm-io/dart-scaler", "arm-io/dart-scaler/mapper-scaler" }},
|
||||
{ FPGA_HAS_JPEG, { "arm-io/jpeg", "arm-io/dart-jpeg", "arm-io/dart-jpeg/mapper-jpeg" }},
|
||||
{ FPGA_HAS_GFX, { "arm-io/sgx", NULL, NULL }},
|
||||
};
|
||||
|
||||
int target_update_device_tree(void)
|
||||
{
|
||||
DTNode *node;
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
uint32_t i, j;
|
||||
|
||||
// Get the hardware blocks that are instantiated on this FPGA.
|
||||
uint32_t fpgaBlocks = chipid_get_fpga_block_instantiation();
|
||||
dprintf(DEBUG_SPEW, "FPGA block instantiation mask = 0x%X\n", fpgaBlocks);
|
||||
|
||||
for (i = 0; i < sizeof(fpgaNodes)/sizeof(fpgaNodes[0]); i++) {
|
||||
if ((fpgaBlocks & fpgaNodes[i].mask) == 0) {
|
||||
for (j = 0; j < MAX_NODES_PER_DEVICE; j++) {
|
||||
if (fpgaNodes[i].nodeName[j] == NULL) {
|
||||
break;
|
||||
}
|
||||
if (FindNode(0, fpgaNodes[i].nodeName[j], &node)) {
|
||||
propName = "compatible";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (j == 0) {
|
||||
dprintf(DEBUG_INFO,
|
||||
"FPGA block not instantiated: disabling %s\n",
|
||||
fpgaNodes[i].nodeName[j]);
|
||||
}
|
||||
propName[0] = '~';
|
||||
} else {
|
||||
dprintf(DEBUG_SPEW,
|
||||
"FPGA: Could not find 'compatible' property for %s DT node\n",
|
||||
fpgaNodes[i].nodeName[j]);
|
||||
}
|
||||
} else {
|
||||
dprintf(DEBUG_SPEW,
|
||||
"FPGA: Could not find %s DT node\n",
|
||||
fpgaNodes[i].nodeName[j]);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if !WITH_HW_POWER
|
||||
|
||||
bool power_needs_precharge(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
void power_cancel_buttonwait(void)
|
||||
{
|
||||
}
|
||||
|
||||
bool power_do_chargetrap(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
bool power_is_suspended(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
void power_will_resume(void)
|
||||
{
|
||||
}
|
||||
|
||||
bool power_has_usb(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
int power_read_dock_id(unsigned *id)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
bool power_get_diags_dock(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
u_int32_t power_get_boot_battery_level(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int power_get_nvram(u_int8_t key, u_int8_t *data)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int power_set_nvram(u_int8_t key, u_int8_t data)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int power_set_soc_voltage(unsigned mv, int override)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
bool force_usb_power = false;
|
||||
|
||||
void power_set_usb_state(bool configured, bool suspended)
|
||||
{
|
||||
}
|
||||
|
||||
int power_backlight_enable(u_int32_t backlight_level)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* ! WITH_HW_POWER */
|
||||
@@ -0,0 +1,283 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
/* Pin configuration for FPGA - Fiji I/O Spreadsheet v9.3 */
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED, // ULPI_DIR ->
|
||||
CFG_DISABLED, // ULPI_STP ->
|
||||
CFG_DISABLED, // ULPI_NXT ->
|
||||
CFG_DISABLED, // ULPI_DATA7 ->
|
||||
CFG_DISABLED, // ULPI_DATA6 ->
|
||||
CFG_DISABLED, // ULPI_DATA5 ->
|
||||
CFG_DISABLED, // ULPI_DATA4 ->
|
||||
CFG_DISABLED, // ULPI_CLK ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED, // ULPI_DATA3 ->
|
||||
CFG_DISABLED, // ULPI_DATA2 ->
|
||||
CFG_DISABLED, // ULPI_DATA1 ->
|
||||
CFG_DISABLED, // ULPI_DATA0 ->
|
||||
CFG_DISABLED, // SPI1_SCLK ->
|
||||
CFG_DISABLED, // SPI1_MOSI ->
|
||||
CFG_DISABLED, // SPI1_MISO ->
|
||||
CFG_DISABLED, // SPI1_SSIN ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED, // GPIO11 ->
|
||||
CFG_IN, // GPIO12 -> HOLD_KEY (REQUEST_DFU1)
|
||||
CFG_DISABLED, // I2S3_MCK ->
|
||||
CFG_DISABLED, // I2S3_LRCK ->
|
||||
CFG_DISABLED, // I2S3_BCLK ->
|
||||
CFG_DISABLED, // I2S3_DOUT ->
|
||||
CFG_DISABLED, // I2S3_DIN ->
|
||||
CFG_DISABLED, // CLK32K_OUT ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED, // PCIE_CLKREQ0_N ->
|
||||
CFG_DISABLED, // PCIE_CLKREQ1_N ->
|
||||
CFG_DISABLED, // NAND_SYS_CLK ->
|
||||
CFG_DISABLED, // GPIO0 ->
|
||||
CFG_DISABLED, // GPIO1 ->
|
||||
CFG_DISABLED, // GPIO2 ->
|
||||
CFG_IN, // GPIO3 -> MENU_KEY (REQUEST_DFU2)
|
||||
CFG_DISABLED, // GPIO4 ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED, // GPIO5 ->
|
||||
CFG_DISABLED, // GPIO6 ->
|
||||
CFG_DISABLED, // GPIO7 ->
|
||||
CFG_DISABLED, // GPIO14 ->
|
||||
CFG_DISABLED, // GPIO16 -> BOARD_ID[3]
|
||||
CFG_DISABLED, // GPIO17 ->
|
||||
CFG_DISABLED, // GPIO18 -> BOOT_CONFIG[0]
|
||||
CFG_DISABLED, // GPIO20 ->
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED, // GPIO21 ->
|
||||
CFG_DISABLED, // UART5_RTXD ->
|
||||
CFG_DISABLED, // UART8_TXD ->
|
||||
CFG_DISABLED, // UART8_RXD ->
|
||||
CFG_FUNC0, // SPI0_SCLK -> SPI0_SCLK/BOARD_ID[0]
|
||||
CFG_FUNC0, // SPI0_MOSI -> SPI0_MOSI/BOARD_ID[1]
|
||||
CFG_FUNC0, // SPI0_MISO -> SPI0_MISO/BOARD_ID[2]
|
||||
CFG_OUT_1, // SPI0_SSIN ->
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // I2C2_SDA ->
|
||||
CFG_DISABLED, // I2C2_SCL ->
|
||||
CFG_DISABLED, // GPIO22 ->
|
||||
CFG_DISABLED, // GPIO23 ->
|
||||
CFG_DISABLED, // GPIO25 -> BOOT_CONFIG[1]
|
||||
CFG_DISABLED, // GPIO28 -> BOOT_CONFIG[2]
|
||||
CFG_DISABLED, // GPIO29 -> BOARD_ID[4]
|
||||
CFG_DISABLED, // GPIO34 ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // GPIO35 ->
|
||||
CFG_DISABLED, // GPIO36 ->
|
||||
CFG_DISABLED, // GPIO37 ->
|
||||
CFG_DISABLED, // GPIO39 ->
|
||||
CFG_DISABLED, // GPIO42 ->
|
||||
CFG_DISABLED, // GPIO43 ->
|
||||
CFG_DISABLED, // DISP_VSYNC ->
|
||||
CFG_FUNC0, // UART0_TXD ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_FUNC0, // UART0_RXD ->
|
||||
CFG_DISABLED, // TMR32_PWM0 ->
|
||||
CFG_DISABLED, // TMR32_PWM1 ->
|
||||
CFG_DISABLED, // TMR32_PWM2 ->
|
||||
CFG_DISABLED, // UART6_TXD ->
|
||||
CFG_DISABLED, // UART6_RXD ->
|
||||
CFG_DISABLED, // I2C3_SDA ->
|
||||
CFG_DISABLED, // I2C3_SCL ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // I2C0_SDA ->
|
||||
CFG_DISABLED, // I2C0_SCL ->
|
||||
CFG_DISABLED, // GPIO38 ->
|
||||
CFG_DISABLED, // UART2_TXD ->
|
||||
CFG_DISABLED, // UART2_RXD ->
|
||||
CFG_DISABLED, // UART2_RTSN ->
|
||||
CFG_DISABLED, // UART2_CTSN ->
|
||||
CFG_DISABLED, // DWI_DO ->
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // DWI_CLK ->
|
||||
CFG_FUNC0, // WDOG ->
|
||||
CFG_DISABLED, // GPIO13 ->
|
||||
CFG_DISABLED, // GPIO19 ->
|
||||
CFG_IN, // GPIO26 -> FORCE_DFU
|
||||
CFG_DISABLED, // GPIO27 -> DFU_STATUS
|
||||
CFG_DISABLED, // SOCHOT0 ->
|
||||
CFG_DISABLED, // SOCHOT1 ->
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // CPU_SLEEP_STATUS ->
|
||||
CFG_DISABLED, // TST_CLKOUT ->
|
||||
CFG_DISABLED, // GPIO8 ->
|
||||
CFG_DISABLED, // GPIO9 ->
|
||||
CFG_DISABLED, // GPIO10 ->
|
||||
CFG_DISABLED, // GPIO15 ->
|
||||
CFG_DISABLED, // UART4_TXD ->
|
||||
CFG_DISABLED, // UART4_RXD ->
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // UART4_RTSN ->
|
||||
CFG_DISABLED, // UART4_CTSN ->
|
||||
CFG_DISABLED, // SPI3_MOSI ->
|
||||
CFG_DISABLED, // SPI3_MISO ->
|
||||
CFG_DISABLED, // SPI3_SCLK ->
|
||||
CFG_DISABLED, // SPI3_SSIN ->
|
||||
CFG_DISABLED, // GPIO24 ->
|
||||
CFG_DISABLED, // GPIO30 ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED, // GPIO31 ->
|
||||
CFG_DISABLED, // GPIO32 ->
|
||||
CFG_DISABLED, // GPIO33 ->
|
||||
CFG_DISABLED, // GPIO40 ->
|
||||
CFG_DISABLED, // GPIO41 ->
|
||||
CFG_DISABLED, // I2S4_MCK ->
|
||||
CFG_DISABLED, // I2S4_LRCK ->
|
||||
CFG_DISABLED, // I2S4_BCLK ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // I2S4_DOUT ->
|
||||
CFG_DISABLED, // I2S4_DIN ->
|
||||
CFG_DISABLED, // I2C1_SDA ->
|
||||
CFG_DISABLED, // I2C1_SCL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // I2S0_LRCK ->
|
||||
CFG_DISABLED, // I2S0_BCLK ->
|
||||
CFG_DISABLED, // I2S0_DOUT ->
|
||||
CFG_DISABLED, // I2S0_DIN ->
|
||||
CFG_DISABLED, // I2S1_MCK ->
|
||||
CFG_DISABLED, // I2S1_LRCK ->
|
||||
CFG_DISABLED, // I2S1_BCLK ->
|
||||
CFG_DISABLED, // I2S1_DOUT ->
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // I2S1_DIN ->
|
||||
CFG_DISABLED, // I2S2_LRCK ->
|
||||
CFG_DISABLED, // I2S2_BCLK ->
|
||||
CFG_DISABLED, // I2S2_DOUT ->
|
||||
CFG_DISABLED, // I2S2_DIN ->
|
||||
CFG_DISABLED, // UART1_TXD ->
|
||||
CFG_DISABLED, // UART1_RXD ->
|
||||
CFG_DISABLED, // UART1_RTSN ->
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED, // UART1_CTSN ->
|
||||
CFG_DISABLED, // EDP_HPD ->
|
||||
CFG_DISABLED, // UART3_TXD ->
|
||||
CFG_DISABLED, // UART3_RXD ->
|
||||
CFG_DISABLED, // UART3_RTSN ->
|
||||
CFG_DISABLED, // UART3_CTSN ->
|
||||
CFG_DISABLED, // SPI2_SCLK ->
|
||||
CFG_DISABLED, // SPI2_MOSI ->
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED, // SPI2_MISO ->
|
||||
CFG_DISABLED, // SPI2_SSIN ->
|
||||
CFG_DISABLED, // ISP0_SDA ->
|
||||
CFG_DISABLED, // ISP0_SCL ->
|
||||
CFG_DISABLED, // ISP1_SDA ->
|
||||
CFG_DISABLED, // ISP1_SCL ->
|
||||
CFG_DISABLED, // SENSOR0_RST ->
|
||||
CFG_DISABLED, // SENSOR0_CLK ->
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED, // SENSOR0_XSHUTDOWN ->
|
||||
CFG_DISABLED, // SENSOR0_ISTRB ->
|
||||
CFG_DISABLED, // ISP_UART0_TXD ->
|
||||
CFG_DISABLED, // ISP_UART0_RXD ->
|
||||
CFG_DISABLED, // SENSOR1_RST ->
|
||||
CFG_DISABLED, // SENSOR1_CLK ->
|
||||
CFG_DISABLED, // SENSOR1_XSHUTDOWN ->
|
||||
CFG_DISABLED, // SENSOR1_ISTRB ->
|
||||
|
||||
/* Port 25 */
|
||||
CFG_DISABLED, // UART7_TXD ->
|
||||
CFG_DISABLED, // UART7_RXD ->
|
||||
CFG_DISABLED, // I2S0_MCK ->
|
||||
CFG_DISABLED, // I2S2_MCK ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
return gpio_default_cfg;
|
||||
}
|
||||
@@ -0,0 +1,253 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
/* Default T7001 FPGA Pin Configuration - Capri I/O Spreadsheet v10.29 */
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // MENU_KEY_L -> REQUEST_DFU2
|
||||
CFG_IN, // HOLD_KEY_L -> REQUEST_DFU1
|
||||
CFG_DISABLED, // ISP0_SDA ->
|
||||
CFG_DISABLED, // ISP0_SCL ->
|
||||
CFG_DISABLED, // ISP1_SDA ->
|
||||
CFG_DISABLED, // ISP1_SCL ->
|
||||
CFG_DISABLED, // SENSOR0_RST ->
|
||||
CFG_DISABLED, // SENSOR0_CLK ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED, // SENSOR0_XSHUTDOWN ->
|
||||
CFG_DISABLED, // SENSOR0_ISTRB ->
|
||||
CFG_DISABLED, // SENSOR1_RST ->
|
||||
CFG_DISABLED, // SENSOR1_CLK ->
|
||||
CFG_DISABLED, // SENSOR1_XSHUTDOWN ->
|
||||
CFG_DISABLED, // SENSOR1_ISTRB ->
|
||||
CFG_DISABLED, // UART3_TXD ->
|
||||
CFG_DISABLED, // UART3_RXD ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED, // UART3_RTSN ->
|
||||
CFG_DISABLED, // UART3_CTSN ->
|
||||
CFG_DISABLED, // UART5_RTXD ->
|
||||
CFG_DISABLED, // DWI0_DO ->
|
||||
CFG_DISABLED, // DWI0_CLK ->
|
||||
CFG_DISABLED, // I2C0_SDA ->
|
||||
CFG_DISABLED, // I2C0_SCL ->
|
||||
CFG_DISABLED, // I2S0_LRCK ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED, // I2S0_BCLK ->
|
||||
CFG_DISABLED, // I2S0_DOUT ->
|
||||
CFG_DISABLED, // I2S0_DIN ->
|
||||
CFG_DISABLED, // I2S1_MCK ->
|
||||
CFG_DISABLED, // I2S1_LRCK ->
|
||||
CFG_DISABLED, // I2S1_BCLK ->
|
||||
CFG_DISABLED, // I2S1_DOUT ->
|
||||
CFG_DISABLED, // I2S1_DIN ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED, // SPI3_MOSI ->
|
||||
CFG_DISABLED, // SPI3_MISO ->
|
||||
CFG_DISABLED, // SPI3_SCLK ->
|
||||
CFG_DISABLED, // SPI3_SSIN ->
|
||||
CFG_DISABLED, // TMR32_PWM0 ->
|
||||
CFG_DISABLED, // TMR32_PWM1 ->
|
||||
CFG_DISABLED, // TMR32_PWM2 ->
|
||||
CFG_DISABLED, // DISP_VSYNC ->
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0, // WDOG ->
|
||||
CFG_DISABLED, // SOCHOT0 ->
|
||||
CFG_DISABLED, // SOCHOT1 ->
|
||||
CFG_DISABLED, // CPU_SLEEP_STATUS ->
|
||||
CFG_DISABLED, // TST_CLKOUT ->
|
||||
CFG_DISABLED, // ISP_UART0_TXD ->
|
||||
CFG_DISABLED, // ISP_UART0_RXD ->
|
||||
CFG_DISABLED, // UART7_TXD ->
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // UART7_RXD ->
|
||||
CFG_DISABLED, // I2C1_SDA ->
|
||||
CFG_DISABLED, // I2C1_SCL ->
|
||||
CFG_FUNC0, // SPI0_SCLK -> BOARD_ID0
|
||||
CFG_FUNC0, // SPI0_MOSI -> BOARD_ID1
|
||||
CFG_FUNC0, // SPI0_MISO -> BOARD_ID2
|
||||
CFG_OUT_1, // SPI0_SSIN ->
|
||||
CFG_DISABLED, // I2S3_MCK ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // I2S3_LRCK ->
|
||||
CFG_DISABLED, // I2S3_BCLK ->
|
||||
CFG_DISABLED, // I2S3_DOUT ->
|
||||
CFG_DISABLED, // I2S3_DIN ->
|
||||
CFG_DISABLED, // UART4_TXD ->
|
||||
CFG_DISABLED, // UART4_RXD ->
|
||||
CFG_DISABLED, // UART4_RTSN ->
|
||||
CFG_DISABLED, // UART4_CTSN ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // GPIO0 ->
|
||||
CFG_DISABLED, // GPIO1 ->
|
||||
CFG_DISABLED, // GPIO2 ->
|
||||
CFG_DISABLED, // GPIO3 ->
|
||||
CFG_DISABLED, // GPIO4 ->
|
||||
CFG_DISABLED, // GPIO5 ->
|
||||
CFG_DISABLED, // GPIO6 ->
|
||||
CFG_DISABLED, // GPIO7 ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // GPIO8 ->
|
||||
CFG_DISABLED, // GPIO9 ->
|
||||
CFG_DISABLED, // GPIO10 ->
|
||||
CFG_DISABLED, // GPIO11 ->
|
||||
CFG_DISABLED, // GPIO12 ->
|
||||
CFG_DISABLED, // GPIO13 ->
|
||||
CFG_DISABLED, // GPIO14 ->
|
||||
CFG_DISABLED, // GPIO15 ->
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // GPIO16 -> BOARD_ID3
|
||||
CFG_DISABLED, // GPIO17 ->
|
||||
CFG_DISABLED, // GPIO18 -> BOOT_CONFIG0
|
||||
CFG_DISABLED, // GPIO19 ->
|
||||
CFG_DISABLED, // GPIO20 ->
|
||||
CFG_DISABLED, // GPIO21 ->
|
||||
CFG_DISABLED, // GPIO22 ->
|
||||
CFG_DISABLED, // GPIO23 ->
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // GPIO24 ->
|
||||
CFG_DISABLED, // GPIO25 -> BOOT_CONFIG1
|
||||
CFG_IN, // GPIO26 -> FORCE_DFU
|
||||
CFG_DISABLED, // GPIO27 -> DFU_STATUS
|
||||
CFG_DISABLED, // GPIO28 -> BOOT_CONFIG2
|
||||
CFG_DISABLED, // GPIO29 -> BOARD_ID4
|
||||
CFG_DISABLED, // GPIO30 ->
|
||||
CFG_DISABLED, // GPIO31 -> BOOT_CONFIG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // GPIO32 ->
|
||||
CFG_DISABLED, // GPIO33 ->
|
||||
CFG_DISABLED, // GPIO34 ->
|
||||
CFG_DISABLED, // GPIO35 ->
|
||||
CFG_DISABLED, // GPIO36 ->
|
||||
CFG_DISABLED, // GPIO37 ->
|
||||
CFG_DISABLED, // SPI2_SCLK ->
|
||||
CFG_DISABLED, // SPI2_MOSI ->
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // SPI2_MISO ->
|
||||
CFG_DISABLED, // SPI2_SSIN ->
|
||||
CFG_DISABLED, // UART8_TXD ->
|
||||
CFG_DISABLED, // UART8_RXD ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_FUNC0, // UART0_TXD ->
|
||||
CFG_FUNC0, // UART0_RXD ->
|
||||
CFG_DISABLED, // UART6_TXD ->
|
||||
CFG_DISABLED, // UART6_RXD ->
|
||||
CFG_DISABLED, // I2C2_SDA ->
|
||||
CFG_DISABLED, // I2C2_SCL ->
|
||||
CFG_DISABLED, // I2C3_SDA ->
|
||||
CFG_DISABLED, // I2C3_SCL ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // UART2_TXD ->
|
||||
CFG_DISABLED, // UART2_RXD ->
|
||||
CFG_DISABLED, // UART2_RTSN ->
|
||||
CFG_DISABLED, // UART2_CTSN ->
|
||||
CFG_DISABLED, // UART1_TXD ->
|
||||
CFG_DISABLED, // UART1_RXD ->
|
||||
CFG_DISABLED, // UART1_RTSN ->
|
||||
CFG_DISABLED, // UART1_CTSN ->
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED, // EDP_HPD ->
|
||||
CFG_DISABLED, // I2S4_MCK ->
|
||||
CFG_DISABLED, // I2S4_LRCK ->
|
||||
CFG_DISABLED, // I2S4_BCLK ->
|
||||
CFG_DISABLED, // I2S4_DOUT ->
|
||||
CFG_DISABLED, // I2S4_DIN ->
|
||||
CFG_DISABLED, // I2S2_LRCK ->
|
||||
CFG_DISABLED, // I2S2_BCLK ->
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // I2S2_DOUT ->
|
||||
CFG_DISABLED, // I2S2_DIN ->
|
||||
CFG_DISABLED, // SPI1_SCLK ->
|
||||
CFG_DISABLED, // SPI1_MOSI ->
|
||||
CFG_DISABLED, // SPI1_MISO ->
|
||||
CFG_DISABLED, // SPI1_SSIN ->
|
||||
CFG_DISABLED, // CLK32K_OUT ->
|
||||
CFG_DISABLED, // ULPI_DIR ->
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // ULPI_STP ->
|
||||
CFG_DISABLED, // ULPI_NXT ->
|
||||
CFG_DISABLED, // ULPI_DATA7 ->
|
||||
CFG_DISABLED, // ULPI_DATA6 ->
|
||||
CFG_DISABLED, // ULPI_DATA5 ->
|
||||
CFG_DISABLED, // ULPI_DATA4 ->
|
||||
CFG_DISABLED, // ULPI_CLK ->
|
||||
CFG_DISABLED, // ULPI_DATA3 ->
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // ULPI_DATA2 ->
|
||||
CFG_DISABLED, // ULPI_DATA1 ->
|
||||
CFG_DISABLED, // ULPI_DATA0 ->
|
||||
CFG_DISABLED, // DWI1_DO ->
|
||||
CFG_DISABLED, // DWI1_CLK ->
|
||||
CFG_DISABLED, // PCIE_CLKREQ0_N ->
|
||||
CFG_DISABLED, // PCIE_CLKREQ1_N ->
|
||||
CFG_DISABLED, // PCIE_CLKREQ2_N ->
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED, // PCIE_CLKREQ3_N ->
|
||||
CFG_DISABLED, // NAND_SYS_CLK ->
|
||||
CFG_DISABLED, // PCIE_PERST0_N ->
|
||||
CFG_DISABLED, // PCIE_PERST1_N ->
|
||||
CFG_DISABLED, // PCIE_PERST2_N ->
|
||||
CFG_DISABLED, // PCIE_PERST3_N ->
|
||||
CFG_DISABLED, // I2S0_MCK ->
|
||||
CFG_DISABLED, // I2S2_MCK ->
|
||||
};
|
||||
|
||||
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
return gpio_default_cfg;
|
||||
}
|
||||
@@ -0,0 +1,41 @@
|
||||
# Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_V2 \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=CHIPID_SOC_VOLTAGE_VMIN \
|
||||
TARGET_VID0_CLK_CFG=0x85100000 \
|
||||
DISPLAY_FPGA_TUNABLES=1 \
|
||||
AMC_NUM_RANKS=1 \
|
||||
TARGET_DWI_FREQUENCY=24000000 \
|
||||
TARGET_DWI_TRANSFER_GAP_US=2.5 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_SOC=2 \
|
||||
BUCK_GPU=1 \
|
||||
WITH_TARGET_AMC_PARAMS=1 \
|
||||
WITH_TARGET_AMP_PARAMS=1
|
||||
|
||||
ifeq ($(SUB_PLATFORM),t7000)
|
||||
OPTIONS += AMC_NUM_CHANNELS=2
|
||||
else
|
||||
OPTIONS += AMC_NUM_CHANNELS=4
|
||||
OPTIONS += BUCK_RAM=2
|
||||
endif
|
||||
|
||||
OPTIONS += \
|
||||
SUPPORT_FPGA=1
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o \
|
||||
$(LOCAL_DIR)/pinconfig_$(SUB_TARGET).o
|
||||
Reference in new issue
Block a user