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@@ -0,0 +1,20 @@
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/*
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* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
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||||
*
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||||
* This document is the property of Apple Inc.
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||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
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||||
#ifndef __TARGET_GPIODEF_H
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#define __TARGET_GPIODEF_H
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/* Typhonic specific gpio -> pin mappings */
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#include <platform/gpio.h>
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/* define target-specific gpios in a generic fashion here. */
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#endif /* ! __TARGET_GPIODEF_H */
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@@ -0,0 +1,153 @@
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// Copyright (C) 2008-2010 Apple, Inc. All rights reserved.
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//
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||||
// This document is the property of Apple, Inc.
|
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// It is considered confidential and proprietary.
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||||
//
|
||||
// This document may not be reproduced or transmitted in any form,
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||||
// in whole or in part, without the express written permission of
|
||||
// Apple, Inc.
|
||||
//
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// NOTE: This is a generated file and should not be hand-edited!
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//
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// =============================================================================
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// Nand Geometry Table
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static NandGeometry _nandGeometryTable[] =
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{
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{
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/* chipId */ { 0x98, 0xE7, 0x94, 0x32 },
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/* blocksPerCS */ 4100,
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/* pagesPerBlock */ 128,
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/* dataBytesPerPage */ 8192,
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/* spareBytesPerPage */ 448,
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/* eccPer512Bytes */ 16,
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/* initialBBType */ INIT_BBT_TOSHIBA_MLC,
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/* diesPerCS */ 1
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}
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};
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// =============================================================================
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// Nand Timing Table
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static NandTiming _nandTimingTable[] =
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{
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{
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/* configId */
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{
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/* connectedBusCnt */ 2,
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/* packageCnt */ 1,
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/* packageIds[] */
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{
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{
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/* chipId */ { 0x98, 0xE7, 0x94, 0x32 },
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/* ceCnt */ 2
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}
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}
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},
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/* writeCycleNanosecs */ 25,
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/* writeSetupNanosecs */ 12,
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/* writeHoldNanosecs */ 10,
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/* readCycleNanosecs */ 25,
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/* readSetupNanosecs */ 12,
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/* readHoldNanosecs */ 10,
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/* readDelayNanosecs */ 20,
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/* readValidNanosecs */ 25
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}
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};
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#if (defined (AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
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// =============================================================================
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// NandChipId Description
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const NandChipIdDescription _nandChipIdDescriptionTable[] =
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{
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{
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/* chipId */ { 0x98, 0xE7, 0x94, 0x32 },
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/* die */ "32nm",
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/* vendor_name */ "Toshiba"
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}
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};
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// =============================================================================
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// Nand Description Table
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static const NandDescription _nandDescriptionTable[] =
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{
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{
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/* packageId */
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{
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/* chipId */ { 0x98, 0xE7, 0x94, 0x32 },
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/* ceCnt */ 2
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},
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/* appleName */ "335S0700",
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/* vendor_part_num */ "TH58NVG6D2FLA49",
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/* package_type */ "DDP",
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/* package_size */ "1.00mm LGA"
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}
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};
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const UInt32 _nandDescriptionTableSize = sizeof(_nandDescriptionTable) / sizeof(NandDescription);
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#endif // (defined(AND_ENABLE_NAND_DESCRIPTION_TEXT) || AND_ENABLE_NAND_DESCRIPTION_TEXT)
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// =============================================================================
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// Nand Board Support Table
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static NandBoardSupport _nandBoardSupportTable[] =
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{
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{
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/* configId */
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{
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/* connectedBusCnt */ 2,
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/* packageCnt */ 1,
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/* packageIds[] */
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{
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{
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/* deviceId */ { 0x98, 0xE7, 0x94, 0x32 },
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/* ceCnt */ 2
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}
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}
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},
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/* vsType */ FIL_VS_TOSHIBA_2P_EXT
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}
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};
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// =============================================================================
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// Nand Board Timing Table
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static NandBoardInfo _nandBoardInfo =
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{
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/* controlDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* dataDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* chipEnableDstr */ NAND_DRIVE_STRENGTH_DEFAULT,
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/* socToNandRiseNanosecs */ 10,
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/* socToNandFallNanosecs */ 10,
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/* nandToSocRiseNanosecs */ 10,
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/* nandToSocFallNanosecs */ 10,
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/* landing map */
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{
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0x00000303
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},
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/* useToggleMode */ 0,
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/* useDiffDQSMode */ 0,
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/* useDiffREMode */ 0,
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/* useVref */ 0
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};
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static NandFormat _nandFormatPpn =
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{
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/* metaPerLogicalPage */ 16,
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/* validMetaPerLogicalPage */ 16,
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/* logicalPageSize */ 0
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};
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static NandFormat _nandFormatRaw =
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{
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/* metaPerLogicalPage */ 12,
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/* validMetaPerLogicalPage */ 10,
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/* logicalPageSize */ 0
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};
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@@ -0,0 +1,23 @@
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/*
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* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
|
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* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
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*/
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#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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// Minimal definitions to make lib/power.c happy
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#define TARGET_POWER_NO_BATTERY (1)
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#define PRECHARGE_BACKLIGHT_LEVEL (824)
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#define ALWAYS_BOOT_BATTERY_VOLTAGE (5000)
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// This fake SoC block takes the place of the external PMU in Fastsim
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#define SWIFTER_PMU_BASE (0x20F050000)
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#endif
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@@ -0,0 +1,17 @@
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/*
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||||
* Copyright (C) 2011-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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||||
*/
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#ifndef __TARGET_UARTCONFIG_H
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#define __TARGET_UARTCONFIG_H
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/* define two debug serial ports */
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#define DEBUG_SERIAL_PORT (0)
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#endif
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@@ -0,0 +1,223 @@
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/*
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* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
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||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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*/
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#include <debug.h>
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#include <drivers/flash_nor.h>
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#include <lib/devicetree.h>
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#include <lib/env.h>
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#include <lib/mib.h>
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#include <platform.h>
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#include <platform/gpiodef.h>
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#include <platform/memmap.h>
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#include <sys.h>
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#include <sys/menu.h>
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#include <sys/task.h>
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#include <target.h>
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static uint32_t display_config;
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MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
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MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
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void target_early_init(void)
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{
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}
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void target_late_init(void)
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{
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}
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void target_init(void)
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{
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#if WITH_HW_FLASH_NOR
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flash_nor_init(SPI_NOR0);
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#endif
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}
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void target_quiesce_hardware(void)
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{
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}
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void target_poweroff(void)
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{
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}
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int target_bootprep(enum boot_target target)
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{
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return 0;
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}
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bool target_should_recover(void)
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{
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return 0;
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}
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bool target_should_poweron(bool *cold_button_boot)
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{
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*cold_button_boot = true;
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return true;
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}
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bool target_should_poweroff(bool at_boot)
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{
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return 0;
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}
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#if !PRODUCT_LLB
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bool target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
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{
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return false;
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}
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#endif
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void * target_get_display_configuration(void)
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{
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display_config = 0x00000000;
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return ((void *)(&display_config));
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}
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#if WITH_ENV
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void target_setup_default_environment(void)
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{
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env_set("boot-args", "debug=0x14e serial=3 amfi=0x83 cs_enforcement_disable=1 fips_mode=0 -disable_aslr", ENV_PERSISTENT);
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// boot-device is set in platform's init.c
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env_set("display-color-space","RGB888", 0);
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env_set("display-timing", "fpga-wsvga", 0);
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env_set("idle-off", "false", 0);
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env_set("kaslr-slide", "0x10000000", 0);
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env_set("wifiaddr", "12:22:33:44:55:66", 0);
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env_set("ethaddr", "12:22:33:44:55:77", 0);
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env_set("btaddr", "00:00:00:00:00:00", 0);
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}
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#endif
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#if WITH_DEVICETREE
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#define ROOT_DTPATH ""
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int target_update_device_tree(void)
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{
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DTNode *node;
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uint32_t propSize;
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char *propName;
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void *propData;
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// Overwrite the serial-number with data from the simplertc fastsim model
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if (FindNode(0, ROOT_DTPATH, &node)) {
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propName = "serial-number";
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if (FindProperty(node, &propName, &propData, &propSize)) {
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if (propSize != 0x20) {
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dprintf(DEBUG_CRITICAL, "serial-number property size 0x%x (expected 0x20)\n", propSize);
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return -1;
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}
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uint64_t *serial = (uint64_t *)propData;
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serial[0] = *(volatile uint64_t *)0x20f050040;
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serial[1] = *(volatile uint64_t *)0x20f050048;
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serial[2] = *(volatile uint64_t *)0x20f050050;
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serial[3] = *(volatile uint64_t *)0x20f050058;
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}
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}
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// Overwrite the region-info with data from the simplertc fastsim model
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if (FindNode(0, ROOT_DTPATH, &node)) {
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propName = "region-info";
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if (FindProperty(node, &propName, &propData, &propSize)) {
|
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if (propSize != 0x20) {
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dprintf(DEBUG_CRITICAL, "region-info property size 0x%x (expected 0x20)\n", propSize);
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return -1;
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||||
}
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uint64_t *region = (uint64_t *)propData;
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region[0] = *(volatile uint64_t *)0x20f050060;
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region[1] = *(volatile uint64_t *)0x20f050068;
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region[2] = *(volatile uint64_t *)0x20f050070;
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region[3] = *(volatile uint64_t *)0x20f050078;
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}
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}
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return 0;
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}
|
||||
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#endif
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||||
|
||||
|
||||
#if !WITH_HW_POWER
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||||
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||||
bool power_needs_precharge(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
void power_cancel_buttonwait(void)
|
||||
{
|
||||
}
|
||||
|
||||
bool power_do_chargetrap(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
bool power_is_suspended(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
void power_will_resume(void)
|
||||
{
|
||||
}
|
||||
|
||||
bool power_has_usb(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
int power_read_dock_id(unsigned *id)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
bool power_get_diags_dock(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
u_int32_t power_get_boot_battery_level(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int power_get_nvram(u_int8_t key, u_int8_t *data)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int power_set_nvram(u_int8_t key, u_int8_t data)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int power_set_soc_voltage(unsigned mv, int override)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
bool force_usb_power = false;
|
||||
|
||||
void power_set_usb_state(bool configured, bool suspended)
|
||||
{
|
||||
}
|
||||
|
||||
int power_backlight_enable(u_int32_t backlight_level)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* ! WITH_HW_POWER */
|
||||
@@ -0,0 +1,429 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
|
||||
I/O Spreadsheet version: cayman io list. ver 3.13
|
||||
I/O Spreadsheet tracker: <rdar://problem/20286828> H9: Update SecureROM pin configuration to I/O spreadsheet v3.13
|
||||
Conversion command: csvtopinconfig.py --rom --soc h9p --pupd-column 'Default pull-up/pull-down' --netname-column D1x_Net --copyright 2015 --radar '<rdar://problem/20286828> H9: Update SecureROM pin configuration to I/O spreadsheet v3.13' <filename>
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/apple/gpio.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <stdint.h>
|
||||
|
||||
static const uint32_t pinconfig_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 0 : I2S0_MCK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 1 : I2S0_BCLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 2 : I2S0_LRCK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 3 : I2S0_DIN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 4 : I2S0_DOUT ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 5 : I2S2_MCK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 6 : I2S2_BCLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 7 : I2S2_LRCK ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 8 : I2S2_DIN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 9 : I2S2_DOUT ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 10 : NAND_SYS_CLK -> AP_TO_NAND_SYS_CLK_R
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 11 : S3E_RESETN -> AP_TO_NAND_RESET_L
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 12 : PCIE_PERST0_N -> PCIE_AP_TO_NAND_RESET_L
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 13 : PCIE_PERST1_N ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 14 : PCIE_PERST2_N ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 15 : PCIE_PERST3_N ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 16 : PCIE_CLKREQ0_N -> PCIE_NAND_BI_AP_CLKREQ_L
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 17 : PCIE_CLKREQ1_N ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 18 : PCIE_CLKREQ2_N ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 19 : PCIE_CLKREQ3_N ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 20 : GPIO[0] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 21 : GPIO[1] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 22 : GPIO[2] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 23 : GPIO[3] ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 24 : GPIO[4] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 25 : GPIO[5] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 26 : GPIO[6] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 27 : GPIO[7] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 28 : GPIO[8] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 29 : GPIO[9] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 30 : GPIO[10] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 31 : GPIO[11] ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 32 : CLK32K_OUT ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 33 : DWI_DO ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 34 : DWI_CLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 35 : PMU_MOSI ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 36 : PMU_MISO ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 37 : PMU_SCLK ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 38 : GPIO[12] ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 39 : I2C1_SDA ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 40 : I2C1_SCL ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 41 : I2C3_SDA ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 42 : I2C3_SCL ->
|
||||
CFG_DISABLED, // 43 : SENSOR2_RST ->
|
||||
CFG_DISABLED, // 44 : SENSOR3_RST ->
|
||||
CFG_DISABLED, // 45 : SENSOR4_RST ->
|
||||
CFG_DISABLED, // 46 : SENSOR_INT ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 47 : ISP_I2C3_SDA ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 48 : ISP_I2C3_SCL ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 49 : ISP_I2C2_SDA ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 50 : ISP_I2C2_SCL ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 51 : ISP_I2C1_SDA ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 52 : ISP_I2C1_SCL ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 53 : ISP_I2C0_SDA ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 54 : ISP_I2C0_SCL ->
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 64 : SENSOR0_ISTRB ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 65 : SENSOR0_RST ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 66 : SENSOR0_CLK ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 67 : SENSOR0_XSHUTDOWN ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 68 : SENSOR1_ISTRB ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 69 : SENSOR1_RST ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 70 : SENSOR1_CLK ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 71 : SENSOR1_XSHUTDOWN ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 72 : SENSOR2_CLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 73 : I2S1_MCK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 74 : I2S1_BCLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 75 : I2S1_LRCK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 76 : I2S1_DIN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 77 : I2S1_DOUT ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 78 : SPI2_SCLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 79 : SPI2_MOSI ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 80 : SPI2_MISO ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 81 : SPI2_SSIN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 82 : SPI3_SCLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 83 : SPI3_MOSI ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 84 : SPI3_MISO ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 85 : SPI3_SSIN ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 86 : GPIO[31] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 87 : GPIO[32] ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 88 : GPIO[33] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 89 : GPIO[34] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 90 : GPIO[35] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 91 : GPIO[36] ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 96 : UART1_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 97 : UART1_RXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 98 : UART1_RTSN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 99 : UART1_CTSN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 100 : UART4_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 101 : UART4_RXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 102 : UART4_RTSN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 103 : UART4_CTSN ->
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 128 : SPI1_SCLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 129 : SPI1_MOSI ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 130 : SPI1_MISO ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 131 : SPI1_SSIN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 132 : I2C2_SDA ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 133 : I2C2_SCL ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 134 : UART3_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 135 : UART3_RXD ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 136 : UART3_RTSN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 137 : UART3_CTSN ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 138 : GPIO[29] -> BOARD_ID4
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 139 : GPIO[30] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 140 : GPIO[13] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 141 : GPIO[14] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 142 : GPIO[15] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 143 : DROOP ->
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 144 : SOCHOT ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 145 : TMR32_PWM0 ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 146 : TMR32_PWM1 ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 147 : TMR32_PWM2 ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 148 : UART2_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 149 : UART2_RXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 150 : UART2_RTSN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 151 : UART2_CTSN ->
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 152 : UART7_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 153 : UART7_RXD ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 154 : DP_WAKEUP ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 160 : GPIO[37] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 161 : GPIO[38] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 162 : GPIO[39] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 163 : GPIO[40] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 164 : GPIO[41] ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 165 : GPIO[16] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 166 : GPIO[17] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 167 : GPIO[18] -> BOOT_CONFIG0
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 168 : GPIO[19] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 169 : GPIO[20] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 170 : GPIO[21] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 171 : GPIO[22] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 172 : GPIO[23] ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 173 : UART5_RTXD ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 174 : TST_CLKOUT ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 175 : EDP_HPD ->
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED, // 176 : DISP_TOUCH_BSYNC0 ->
|
||||
CFG_DISABLED, // 177 : DISP_TOUCH_BSYNC1 ->
|
||||
CFG_DISABLED, // 178 : DISP_TOUCH_EB ->
|
||||
CFG_IN, // 179 : REQUEST_DFU1 -> PMU_TO_AP_BUF_BUTTON1
|
||||
CFG_IN, // 180 : REQUEST_DFU2 -> PMU_TO_AP_BUF_BUTTON2
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 181 : SWD_TMS2 ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 182 : SWD_TMS3 ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 183 : GPU_TRIGGER ->
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 184 : SPI0_SCLK -> BOARD_ID0
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 185 : SPI0_MOSI -> BOARD_ID1
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 186 : SPI0_MISO -> BOARD_ID2
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 187 : SPI0_SSIN -> BOARD_ID3
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 192 : UART0_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 193 : UART0_RXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 194 : UART6_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 195 : UART6_RXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 196 : I2C0_SDA ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 197 : I2C0_SCL ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 198 : I2S3_MCK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 199 : I2S3_BCLK ->
|
||||
|
||||
/* Port 25 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 200 : I2S3_LRCK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 201 : I2S3_DOUT ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 202 : I2S3_DIN ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 203 : GPIO[24] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 204 : GPIO[25] -> BOOT_CONFIG1
|
||||
CFG_IN | PULL_DOWN | DRIVE_S4 | SLOW_SLEW, // 205 : GPIO[26] -> FORCE_DFU
|
||||
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW, // 206 : GPIO[27] -> DFU_STATUS
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 207 : GPIO[28] -> BOOT_CONFIG2
|
||||
};
|
||||
|
||||
static const uint32_t pinconfig_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 0 : AOP_SPI_SCLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 1 : AOP_SPI_MOSI ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 2 : AOP_SPI_MISO ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 3 : AOP_UART0_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 4 : AOP_UART0_RXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 5 : AOP_UART1_TXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 6 : AOP_UART1_RXD ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 7 : AOP_UART2_TXD ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 8 : AOP_UART2_RXD ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 9 : AOP_I2C0_SDA ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 10 : AOP_I2C0_SCL ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 11 : AOP_FUNC[0] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 12 : AOP_FUNC[1] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 13 : AOP_FUNC[2] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 14 : AOP_FUNC[3] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 15 : AOP_FUNC[4] ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 16 : AOP_FUNC[5] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 17 : AOP_FUNC[6] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 18 : AOP_FUNC[7] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 19 : AOP_FUNC[8] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 20 : AOP_FUNC[9] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 21 : AOP_FUNC[10] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 22 : AOP_FUNC[11] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 23 : AOP_FUNC[12] ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 24 : AOP_FUNC[13] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 25 : AOP_FUNC[14] ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 26 : AOP_FUNC[15] ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 27 : AOP_SWD_TCK_OUT ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 28 : AOP_SWD_TMS0 ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 29 : AOP_SWD_TMS1 ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 32 : AOP_I2S_DOUT ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 33 : AOP_I2S_BCLK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 34 : AOP_I2S_LRCK ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 35 : AOP_I2S_DIN ->
|
||||
CFG_DISABLED | DRIVE_S8 | SLOW_SLEW, // 36 : AOP_I2S_MCK ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 37 : DOCK_CONNECT ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 38 : DOCK_ATTENTION ->
|
||||
CFG_DISABLED, // 39 : AOP_PDM_CLK0 ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED, // 40 : AOP_PDM_DATA0 ->
|
||||
CFG_DISABLED, // 41 : AOP_PDM_DATA1 ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // 64 : XI0 ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 65 : XO0 ->
|
||||
CFG_DISABLED, // 66 : ANALOGMUX_OUT ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 67 : CFSB ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 68 : HOLD_RESET ->
|
||||
CFG_DISABLED, // 69 : TESTMODE ->
|
||||
CFG_DISABLED, // 70 : PACKAGED_N ->
|
||||
CFG_DISABLED, // 71 : CFSB_AOP ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // 72 : COLD_RESETN ->
|
||||
CFG_DISABLED, // 73 : JTAG_TRSTN ->
|
||||
CFG_DISABLED, // 74 : JTAG_SEL ->
|
||||
CFG_DISABLED, // 75 : JTAG_TMS ->
|
||||
CFG_DISABLED, // 76 : JTAG_TDI ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 77 : JTAG_TDO ->
|
||||
CFG_DISABLED, // 78 : JTAG_TCK ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 79 : AOP_DDR_REQ ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 80 : AOP_DDR_RESETN ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 81 : AWAKE_REQ ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 82 : AWAKE_RESETN ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 83 : WDOG ->
|
||||
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 84 : RT_CLK32768 ->
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
CFG_DISABLED,
|
||||
};
|
||||
|
||||
struct pinconfig_map {
|
||||
uint32_t board_id;
|
||||
uint32_t board_id_mask;
|
||||
const uint32_t *pinconfigs[GPIOC_COUNT];
|
||||
};
|
||||
|
||||
static const struct pinconfig_map cfg_map[] = {
|
||||
{ 0, 0, { pinconfig_0, pinconfig_1 } },
|
||||
};
|
||||
|
||||
const uint32_t * target_get_default_gpio_cfg(uint32_t gpioc)
|
||||
{
|
||||
static const struct pinconfig_map *selected_map = NULL;
|
||||
|
||||
if (selected_map == NULL) {
|
||||
uint32_t board_id = platform_get_board_id();
|
||||
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
|
||||
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
|
||||
selected_map = &cfg_map[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (selected_map == NULL)
|
||||
panic("no default pinconfig for board id %u", board_id);
|
||||
}
|
||||
|
||||
ASSERT(gpioc < GPIOC_COUNT);
|
||||
return selected_map->pinconfigs[gpioc];
|
||||
}
|
||||
@@ -0,0 +1,33 @@
|
||||
# Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
TARGET_DIR := $(LOCAL_DIR)
|
||||
|
||||
# TBD - BUCK_*
|
||||
|
||||
OPTIONS += \
|
||||
TARGET_BOOT_CPU_VOLTAGE=0 \
|
||||
TARGET_BOOT_RAM_VOLTAGE=0 \
|
||||
TARGET_BOOT_SOC_VOLTAGE=0 \
|
||||
DCS_NUM_CHANNELS=4 \
|
||||
DCS_NUM_RANKS=1 \
|
||||
AMP_CALIBRATION_SKIP=1 \
|
||||
BUCK_CPU=0 \
|
||||
BUCK_CPU_RAM=7 \
|
||||
BUCK_SOC=2 \
|
||||
BUCK_GPU=1 \
|
||||
BUCK_GPU_RAM=8 \
|
||||
WITH_CPU_APSC=1 \
|
||||
WIFI_DTPATH=\"arm-io/wlan\"
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o
|
||||
ALL_OBJS += $(LOCAL_DIR)/pinconfig_$(SUB_TARGET).o
|
||||
Reference in new issue
Block a user