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Chris Nutter committed 2023-07-08 13:03:17 -07:00
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target/watch2/include/target/adbe_settings.h
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/*
* Copyright (C) 2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Computer, Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_ADBE_SETTINGS_H
#define __TARGET_ADBE_SETTINGS_H
static struct adbe_v3_tuneable adbe_tuneables[] = {
{
.name = "default",
.adbe0_vblank_clk_gate_wakeup = 0x0000,
.adbe0_vblank_clk_gate_idle = 0x0001,
.adbe0_tunable_nrt_ctl = (ADBE_NRT_CTL_ADISP_CLK_GATE_ENABLE | ADBE_NRT_CTL_ADBE_CLK_GATE_ENABLE | ADBE_NRT_CTL_BLK_CLK_GATE_ENABLE),
.adbe0_aap_support = 0,
},
};
#endif
target/watch2/include/target/aspnandconfig.h
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/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Computer, Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_ASPNANDCONFIG_H
#define __TARGET_ASPNANDCONFIG_H
//MLC devices
#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 1
#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 1
#define ASPNAND_ERASE_DIES_IN_PARALLEL 1
#define ASPNAND_READ_DIES_IN_PARALLEL 1
#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 1
#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 1
#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 1
#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 1
//TLC devices
#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 1
#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 1
#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 1
#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 1
#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 1
#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 1
#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 1
#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 1
#define ASPNAND_INDIRECTION_MEMORY (2*1024*1024)
#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
#endif
target/watch2/include/target/dcsfixup.h
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/*
* Copyright (C) 2014-2015 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
static inline
void dcs_init_config_fixup_params(dcs_config_params_t *dcs_params, dcs_target_t targtype)
{
dcs_params->freq[0].freqchngctl[2] = 0xb203000b;
dcs_params->freq[1].freqchngctl[2] = 0xd303000b;
dcs_params->freq[3].freqchngctl[2] = 0xf203000b;
dcs_params->freq[0].lat = 0x001030c2;
dcs_params->freq[1].lat = 0x001020c2;
dcs_params->freq[0].phyrdwrtim = 0x00010c01;
dcs_params->freq[1].phyrdwrtim = 0x00010b01;
dcs_params->freq[0].caspch = 0x40c20402;
dcs_params->freq[0].act = 0x01020202;
dcs_params->freq[0].autoref = 0x01010078;
dcs_params->freq[0].selfref = 0x28001012;
dcs_params->modereg = 0x060c5024;
dcs_params->freq[1].caspch = 0x40c20402;
dcs_params->freq[1].act = 0x01020202;
dcs_params->freq[1].autoref = 0x01010050;
dcs_params->freq[1].selfref = 0x28001012;
dcs_params->freq[2].caspch = 0x40c20402;
dcs_params->freq[2].act = 0x01020202;
dcs_params->freq[2].autoref = 0x01010014;
dcs_params->freq[2].selfref = 0x28001012;
dcs_params->freq[3].autoref = 0x01010005;
dcs_params->freq[3].selfref = 0x28001012;
dcs_params->autoref_params = 0x00150013;
dcs_params->pdn = 0x32272222;
dcs_params->freq[0].derate = 0x08212082;
dcs_params->freq[1].derate = 0x08212082;
dcs_params->freq[2].derate = 0x08212082;
dcs_params->freq[0].lat2 = 0x001110c2;
dcs_params->freq[1].lat2 = 0x00111206;
dcs_params->freq[0].tat = 0x01212222;
dcs_params->freq[1].tat = 0x01212222;
dcs_params->freq[3].mifqmaxctrl = 0x00000003;
dcs_params->freq[0].odt_enable = 0x00000000;
dcs_params->freq[1].odt_enable = 0x00000000;
dcs_params->freq[0].rdcapcfg = 0x01000606;
dcs_params->freq[1].rdcapcfg = 0x21000606;
dcs_params->freq[2].rdcapcfg = 0x41000606;
dcs_params->freq[3].rdcapcfg = 0x61000606;
dcs_params->b0odtctrl = 0x00000000;
dcs_params->b1odtctrl = 0x00000000;
dcs_params->dqs0odtctrl = 0x00000000;
dcs_params->dqs1odtctrl = 0x00000000;
dcs_params->freq[0].autoref2 = 0x01010001;
dcs_params->freq[1].autoref2 = 0x01010001;
dcs_params->freq[2].autoref2 = 0x01010001;
dcs_params->freq[3].autoref2 = 0x01010001;
dcs_params->autoref_params2 = 0x00200013;
dcs_params->mr13cmd_step15 = 0x50,
dcs_params->odtszqc = 0x00002000;
dcs_params->odtszqc2 = 0xc0002000;
dcs_params->odtszqc3 = 0xc0002320;
};
target/watch2/include/target/gpiodef.h
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/*
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_GPIODEF_H
#define __TARGET_GPIODEF_H
/* iPod6,x specific gpio -> pin mappings */
#include <platform/gpio.h>
/* BOARD_REV mapping */
#define BOARD_REV_PROTON 0x0f
#define BOARD_REV_DEV3 0x0f
#define BOARD_REV_DEV4 0x0e
#define BOARD_REV_PROTO2A 0x0e
#define BOARD_REV_PROTO2B 0x0d
#define BOARD_REV_PROTO2X_CARDINAL 0x0c
#define BOARD_REV_PROTO2B_ALT_CARBON 0x0b
#define BOARD_REV_PROTO2D 0x0a
#define BOARD_REV_PROTO2F 0x09
#define BOARD_REV_EVT 0x08
#define BOARD_REV_EVT_ALT_CARBON 0x07
extern uint32_t ipod6_get_board_rev();
/* define target-specific gpios in a generic fashion here. */
#define GPIO_ALT_BOOST_ID GPIOC(GPIO_AP, 5, 3) // GPIO11
/* which IICs to initialize */
#define IICS_MASK (3)
#define TRISTAR_IIC_BUS (0)
#define DISPLAY_PMU_IIC_BUS (1)
/* Miscellaneous Pins */
#define GPIO_PMU_LCD_RST (11)
#define PMU_LCD_PWR_VCI (5)
#define PMU_LCD_PWR_DVDD (0xe)
#define PMU_LDO_OPAL (0x8)
/*
* support of video or command mode
*/
extern bool product_target_is_display_in_video_mode();
extern uint32_t product_target_get_ulps_in_delay(void);
extern uint32_t product_target_get_ulps_end_delay(void);
extern uint32_t product_target_get_ulps_out_delay(void);
extern bool product_target_no_burst_mode();
#define TARGET_DISP_VIDEO_MODE product_target_is_display_in_video_mode()
#define TARGET_DSI_ULPS_IN_DELAY product_target_get_ulps_in_delay()
#define TARGET_DSI_ULPS_END_DELAY product_target_get_ulps_end_delay()
#define TARGET_DSI_ULPS_OUT_DELAY product_target_get_ulps_out_delay()
#define TARGET_NO_BURST_MODE product_target_no_burst_mode()
#endif /* ! __TARGET_GPIODEF_H */
target/watch2/include/target/pinconfig.h
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/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#if CONFIG_FPGA
#include <target/pinconfig_fpga.h>
#elif CONFIG_SIM
#include <target/pinconfig_sim.h>
#else
#include <target/pinconfig_product.h>
#endif
target/watch2/include/target/pinconfig_product.h
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/*
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
/* THIS STRUCT IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
I/O Spreadsheet version: rev 0.2.5
I/O Spreadsheet tracker: <rdar://problem/15171729> M7 GPIO Spreadsheet
*/
/* Different drive strength for AP and DEV. */
#if PIN_CFG_AP
#define AP_DEV_DRIVE_STR(ap, dev) DRIVE_##ap
#elif PIN_CFG_DEV
#define AP_DEV_DRIVE_STR(ap, dev) DRIVE_##dev
#endif
/* Different slew rate for AP and DEV. */
#if PIN_CFG_AP
#define AP_DEV_SLEW_RATE(ap, dev) ap##_SLEW
#elif PIN_CFG_DEV
#define AP_DEV_SLEW_RATE(ap, dev) dev##_SLEW
#endif
#if PIN_CFG_AP
static const uint32_t gpio_default_cfg_ap[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#elif PIN_CFG_DEV
static const uint32_t gpio_default_cfg_dev[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#endif
/* Port 0 */
CFG_DISABLED, // 0 : I2S0_MCK -> GPIO_AP_TO_BERMUDA_CLK_XTAL1
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 1 : I2S1_MCK -> I2S1_AP_TO_CODEC_MCLK_12M
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 2 : SD_CLKOUT -> SDIO_AP_TO_WLAN_CLK
CFG_FUNC0 | PULL_UP | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW | INPUT_SCHMITT, // 3 : SD_CMD_IO -> SDIO_AP_BI_WLAN_CMD
CFG_FUNC0 | PULL_UP | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW | INPUT_SCHMITT, // 4 : SD_DATA_IO[0] -> SDIO_AP_BI_WLAN_DATA0
CFG_FUNC0 | PULL_UP | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW | INPUT_SCHMITT, // 5 : SD_DATA_IO[1] -> SDIO_AP_BI_WLAN_DATA1
CFG_FUNC0 | PULL_UP | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW | INPUT_SCHMITT, // 6 : SD_DATA_IO[2] -> SDIO_AP_BI_WLAN_DATA2
CFG_FUNC0 | PULL_UP | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW | INPUT_SCHMITT, // 7 : SD_DATA_IO[3] -> SDIO_AP_BI_WLAN_DATA3
/* Port 1 */
CFG_FUNC0 | INPUT_SCHMITT, // 8 : SDIO_IRQ -> GPIO_WLAN_TO_SPU_HOST_WAKE_IRQ
CFG_DISABLED, // 9 : WL_HOST_WAKE -> NC_WL_HOST_WAKE
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 2 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 3 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 4 */
CFG_DISABLED, // 32 : GPIO[0] -> NC_AP_GPIO0
CFG_DISABLED, // 33 : GPIO[1] -> NC_AP_GPIO1
CFG_DISABLED, // 34 : GPIO[2] -> GPIO_BOOT_CONFIG_0
CFG_DISABLED, // 35 : GPIO[3] -> GPIO_BOOT_CONFIG_1
CFG_DISABLED, // 36 : GPIO[4] -> GPIO_BOOT_CONFIG_2
CFG_DISABLED, // 37 : GPIO[5] -> NC_GPIO_BOOT_CONFIG_3
CFG_DISABLED, // 38 : GPIO[6] -> GPIO_BOARD_ID_3
CFG_DISABLED, // 39 : GPIO[7] -> GPIO_BOARD_REV_0
/* Port 5 */
CFG_DISABLED, // 40 : GPIO[8] -> GPIO_BOARD_REV_1
CFG_DISABLED, // 41 : GPIO[9] -> GPIO_BOARD_REV_2
CFG_DISABLED, // 42 : GPIO[10] -> GPIO_BOARD_REV_3
CFG_DISABLED, // 43 : GPIO[11] -> NC_GPIO_DEV_BOOST_ALT_ID
CFG_OUT_0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 44 : GPIO[12] -> GPIO_AP_TO_BT_DEVICE_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 45 : GPIO[13] -> GPIO_CODEC_TO_AP_IRQ_L
CFG_OUT_0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 46 : GPIO[14] -> GPIO_AP_TO_SEAJAY_RESET
CFG_OUT_0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 47 : GPIO[15] -> GPIO_AP_TO_BERMUDA_FW_DWLD_REQ
/* Port 6 */
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW | INPUT_SCHMITT, // 48 : I2C1_SDA -> I2C1_AP_1V8_SDA
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW | INPUT_SCHMITT, // 49 : I2C1_SCL -> I2C1_AP_1V8_SCL
CFG_DISABLED, // 50 : I2S0_LRCK -> NC_I2S0_LRCLK
CFG_DISABLED, // 51 : I2S0_BCLK -> NC_I2S0_BCLK
CFG_DISABLED, // 52 : I2S0_DOUT -> NC_I2S0_DOUT
CFG_DISABLED, // 53 : I2S0_DIN -> NC_I2S0_DIN
CFG_FUNC0, // 54 : I2S1_LRCK -> I2S1_CODEC_TO_AP_WCLK
CFG_FUNC0, // 55 : I2S1_BCLK -> I2S1_CODEC_TO_AP_BCLK
/* Port 7 */
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 56 : I2S1_DOUT -> I2S1_AP_TO_CODEC_DATA
CFG_FUNC0, // 57 : I2S1_DIN -> I2S1_CODEC_TO_AP_DATA
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 58 : UART1_TXD -> UART1_AP_TO_BT_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 59 : UART1_RXD -> UART1_BT_TO_AP_RXD
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 60 : UART1_RTSN -> UART1_AP_TO_BT_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 61 : UART1_CTSN -> UART1_BT_TO_AP_CTS_L
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 62 : UART2_TXD -> UART2_AP_TO_BERMUDA_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 63 : UART2_RXD -> UART2_BERMUDA_TO_AP_RXD
/* Port 8 */
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 64 : UART2_RTSN -> UART2_AP_TO_BERMUDA_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 65 : UART2_CTSN -> UART2_BERMUDA_TO_AP_CTS_L
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 66 : UART4_TXD -> UART4_AP_TO_WLAN_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 67 : UART4_RXD -> UART4_WLAN_TO_AP_RXD
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 68 : UART3_RTXD -> UART3_AP_BI_GG_SWI
CFG_DISABLED, // 69 : CLK32K_OUT -> NC_CLK32K_OUT
CFG_DISABLED, // 70 : TST_CLKOUT -> AP_TST_CLKOUT
CFG_DISABLED, // 71 : GPIO[16] -> NC_AP_GPIO16
/* Port 9 */
CFG_DISABLED, // 72 : GPIO[17] -> NC_AP_GPIO17
CFG_DISABLED, // 73 : GPIO[18] -> GPIO_GRAPE_SWDCLK
CFG_DISABLED, // 74 : TMR32_PWM1 -> NC_TMR32_PWM1
CFG_DISABLED, // 75 : TMR32_PWM2 -> NC_TMR32_PWM2
CFG_FUNC0, // 76 : TMR32_PWM0 -> PMU_VDD_OK
CFG_FUNC0, // 77 : DISP_TE -> DISP_BSYNC
CFG_DISABLED, // 78 : GPIO[19] -> GPIO_GRAPE_SWDIO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 79 : NAND_CEN[0] -> ANC_AP_TO_NAND_CEN<0>
/* Port 10 */
CFG_DISABLED, // 80 : NAND_CEN[1] -> NC_NAND_CEN1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 81 : NAND_IO[7] -> ANC_AP_BI_NAND_IO<7>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 82 : NAND_IO[6] -> ANC_AP_BI_NAND_IO<6>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 83 : NAND_IO[5] -> ANC_AP_BI_NAND_IO<5>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 84 : NAND_IO[4] -> ANC_AP_BI_NAND_IO<4>
CFG_DISABLED, // 85 : NAND_DQS -> NC_NAND_DQS
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 86 : NAND_REN -> ANC_AP_TO_NAND_RE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 87 : NAND_IO[3] -> ANC_AP_BI_NAND_IO<3>
/* Port 11 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 88 : NAND_IO[2] -> ANC_AP_BI_NAND_IO<2>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 89 : NAND_IO[1] -> ANC_AP_BI_NAND_IO<1>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 90 : NAND_IO[0] -> ANC_AP_BI_NAND_IO<0>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 91 : NAND_WEN -> ANC_AP_TO_NAND_WE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 92 : NAND_CLE -> ANC_AP_TO_NAND_CLE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 93 : NAND_ALE -> ANC_AP_TO_NAND_ALE
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW | INPUT_SCHMITT, // 94 : I2C0_SDA -> I2C0_AP_1V8_SDA
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW | INPUT_SCHMITT, // 95 : I2C0_SCL -> I2C0_AP_1V8_SCL
/* Port 12 */
CFG_DISABLED, // 96 : DISP_VSYNC -> NC_DISP_VSYNC
CFG_DISABLED, // 97 : SPI0_SCLK -> GPIO_BOARD_ID_0
CFG_DISABLED, // 98 : SPI0_MOSI -> GPIO_BOARD_ID_1
CFG_DISABLED, // 99 : SPI0_MISO -> GPIO_BOARD_ID_2
CFG_DISABLED, // 100 : SPI0_SSIN -> NC_SPI0_MCK
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 101 : UART0_TXD -> UART0_TXD
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 102 : UART0_RXD -> UART0_RXD
CFG_DISABLED, // 103 : SPI1_SCLK -> NC_SPI1_SCLK
/* Port 13 */
CFG_DISABLED, // 104 : SPI1_MOSI -> NC_SPI1_MOSI
CFG_DISABLED, // 105 : SPI1_MISO -> NC_SPI1_MISO
CFG_DISABLED, // 106 : SPI1_SSIN -> NC_SPI1_SSIN
CFG_DISABLED, // 107 : GPIO[20] -> NC_AP_GPIO20
CFG_OUT_0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 108 : GPIO[21] -> GPIO_AP_TO_WLAN_DEVICE_WAKE
CFG_IN | INPUT_SCHMITT, // 109 : GPIO[22] -> GPIO_TRISTAR_INT
CFG_DISABLED, // 110 : GPIO[23] -> GPIO_AP_TO_OPAL_LVBOOST_BUSY_L
CFG_IN, // 111 : GPIO[24] -> GPIO_OPAL_SWDIO
/* Port 14 */
CFG_IN, // 112 : GPIO[25] -> GPIO_OPAL_SWDCLK
CFG_DISABLED, // 113 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 114 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 115 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 116 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 117 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 118 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 119 : UNSPECIFIED -> UNSPECIFIED
/* Port 15 */
CFG_DISABLED, // 120 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 121 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 122 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 123 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
/* Port 16 */
CFG_DISABLED, // 128 : ENET_MDC -> NC_ENET_MDC
CFG_DISABLED, // 129 : ENET_MDIO -> NC_ENET_MDIO
CFG_DISABLED, // 130 : RMII_RXER -> GPIO_AP_TO_ORB_DEBUG
CFG_DISABLED, // 131 : RMII_TXEN -> NC_RMII_TXEN
CFG_DISABLED, // 132 : RMII_CLK -> NC_GPIO_DEV_DISPLAY_TO_AP_ID3
CFG_DISABLED, // 133 : RMII_TXD[0] -> NC_RMII_TXD0
CFG_DISABLED, // 134 : RMII_TXD[1] -> NC_FPGA_WL_REG_ON
CFG_DISABLED, // 135 : RMII_RXD[0] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID1
/* Port 17 */
CFG_DISABLED, // 136 : RMII_RXD[1] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID2
CFG_DISABLED, // 137 : RMII_CRSDV -> NC_GPIO_DEV_DISPLAY_TO_AP_ID0
};
#if PIN_CFG_AP
static const uint32_t gpio_1_default_cfg_ap[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#elif PIN_CFG_DEV
static const uint32_t gpio_1_default_cfg_dev[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#endif
/* Port 0 */
CFG_IN | INPUT_SCHMITT, // 0 : REQUEST_DFU1 -> BUTTON1_BUFF_L
CFG_IN | INPUT_SCHMITT, // 1 : REQUEST_DFU2 -> LISA_BTN_BUFF_L
CFG_FUNC0 | INPUT_SCHMITT, // 2 : DOCK_CONNECT -> DOCK_CONNECT
CFG_DISABLED | INPUT_SCHMITT, // 3 : CLK32K_IN -> GPIO_PMU_TO_SPU_CLK32K_IN
CFG_OUT_0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 4 : SPU_UART0_TXD -> GPIO_SPU_TO_WLAN_CONTEXT_B
CFG_OUT_0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 5 : SPU_UART0_RXD -> GPIO_SPU_TO_WLAN_CONTEXT_A
CFG_DISABLED, // 6 : SPU_UART0_RTSN -> NC_SPU_UART0_RTSN
CFG_DISABLED, // 7 : SPU_UART0_CTSN -> NC_SPU_UART0_CTSN
/* Port 1 */
CFG_DISABLED, // 8 : SPU_UART1_TXD -> NC_SPU_UART1_TXD
CFG_DISABLED, // 9 : SPU_UART1_RXD -> NC_SPU_UART1_RXD
CFG_DISABLED, // 10 : SPU_UART1_RTSN -> NC_SPU_UART1_RTSN
CFG_DISABLED, // 11 : SPU_UART1_CTSN -> NC_SPU_UART1_CTSN
CFG_DISABLED, // 12 : SPU_GPIO[0] -> NC_SPU_GPIO0
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 13 : SPU_GPIO[1] -> GPIO_WLAN_TO_SPU_HOST_WAKE_IRQ
CFG_IN | INPUT_SCHMITT, // 14 : SPU_GPIO[2] -> GPIO_BT_TO_SPU_HOST_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 15 : SPU_GPIO[3] -> GPIO_SUNFISH_TO_SPU_INT_L
/* Port 2 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 16 : SPU_GPIO[4] -> GPIO_PMU_TO_SPU_IRQ_L
CFG_OUT_0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 17 : SPU_GPIO[5] -> GPIO_SPU_TO_COMPASS_TRG
CFG_OUT_0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 18 : SPU_GPIO[6] -> GPIO_SPU_TO_LVBOOST_EN
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 19 : SPU_GPIO[7] -> GPIO_BERMUDA_TO_SPU_HOST_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 20 : SPU_GPIO[8] -> GPIO_OPAL_TO_SPU_INT_L
CFG_OUT_0, // 21 : DFU_STATUS -> TP_DFU_STATUS
CFG_IN | PULL_DOWN, // 22 : FORCE_DFU -> TP_FORCE_DFU
CFG_FUNC0 | INPUT_SCHMITT, // 23 : PWR_GOOD -> PMU_TO_SPU_PWR_GOOD
/* Port 3 */
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 24 : SOC_VDD_HI_LO -> SPU_TO_PMU_VDD_HI_LO
CFG_DISABLED, // 25 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 26 : DOCK_ATTENTION -> NC_DOCK_ATTENTION
CFG_DISABLED, // 27 : PMU_HOST_WAKE -> NC_PMU_HOST_WAKE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 28 : SPU_SPI_SCLK -> SPI_SPU_SCLK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 29 : SPU_SPI_MOSI -> SPI_SPU_MOSI
CFG_FUNC0 | PULL_DOWN, // 30 : SPU_SPI_MISO -> SPI_SPU_MISO
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 31 : SPU_SPI_CS_TRIG[0] -> SCM_SPU_TO_GRAPE_CS_L
/* Port 4 */
CFG_IN | INPUT_SCHMITT, // 32 : SPU_SPI_CS_TRIG[1] -> SCM_GRAPE_TO_SPU_HINT_L
CFG_DISABLED, // 33 : SPU_SPI_CS_TRIG[2] -> NC_SPU_SPI_CS_TRIG2
CFG_IN | PULL_UP | INPUT_SCHMITT, // 34 : SPU_SPI_CS_TRIG[3] -> SCM_LISA_TO_SPU_INT_L
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 35 : SPU_SPI_CS_TRIG[4] -> SCM_SPU_TO_CARBON_CS_L
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 36 : SPU_SPI_CS_TRIG[5] -> SCM_CARBON_TO_SPU_INT1
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 37 : SPU_SPI_CS_TRIG[6] -> SCM_CARBON_TO_SPU_INT2
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 38 : SPU_SPI_CS_TRIG[7] -> SCM_SPU_TO_COMPASS_CS_L
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 39 : SPU_SPI_CS_TRIG[8] -> SCM_COMPASS_TO_SPU_INT
/* Port 5 */
CFG_DISABLED, // 40 : SPU_SPI_CS_TRIG[9] -> NC_SPU_SPI_CS_TRIG9
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW, // 41 : SPU_SPI_CS_TRIG[10] -> SCM_SPU_TO_OPAL_CS_L
CFG_DISABLED, // 42 : SPU_SPI_CS_TRIG[11] -> NC_SPU_SPI_CS_TRIG11
CFG_IN | PULL_UP | INPUT_SCHMITT, // 43 : SPU_SPI_CS_TRIG[12] -> SCM_PT_TO_SPU_INT_L
CFG_DISABLED, // 44 : SPU_SPI_CS_TRIG[13] -> NC_SPU_SPI_CS_TRIG13
CFG_DISABLED, // 45 : SPU_SPI_CS_TRIG[14] -> NC_SPU_SPI_CS_TRIG14
CFG_DISABLED, // 46 : SPU_SPI_CS_TRIG[15] -> NC_SPU_SPI_CS_TRIG15
CFG_DISABLED, // 47 : SPU_GPIO[9] -> NC_GPIO_SPU_TO_OPAL_RESET_L
/* Port 6 */
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW | INPUT_SCHMITT, // 48 : SPU_I2C_SDA -> I2C_SPU_1V8_SDA
CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | SLOW_SLEW | INPUT_SCHMITT, // 49 : SPU_I2C_SCL -> I2C_SPU_1V8_SCL
};
#undef AP_DEV_SLEW_RATE
#undef AP_DEV_DRIVE_STR
target/watch2/include/target/powerconfig.h
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/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Computer, Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_POWERCONFIG_H
#define __TARGET_POWERCONFIG_H
/* configuration per target */
#define PMU_IIC_BUS 0
#define CHARGER_IIC_BUS 0
/* this configuration is very PMU specific and must be included exactly once in power.c */
#ifdef POWERCONFIG_PMU_SETUP
static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
{
};
static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
{
{ PMU_IIC_BUS, kD2238_BUCK2_VSEL, 0xc0 }, // <rdar://problem/18072042> M7 - Memory VDDQ and VDD2 Nominal Voltage
};
static const struct pmu_setup_struct pmu_warm_init[] =
{
};
static const struct pmu_setup_struct pmu_cold_init[] =
{
{ PMU_IIC_BUS, kD2238_ALL_RAILS_CONF, 0x00 }, // enable SOC_VDD_ALL_RAILS_ON processing
{ PMU_IIC_BUS, kD2238_GPIO14_CONF1, 0x93 }, // <rdar://problem/15821471> PMU register 0x041A needs to be changed to 0x93 during boot-up
{ PMU_IIC_BUS, kD2238_GPIO12_CONF1, 0x00 }, // Display needs to be in reset
{ PMU_IIC_BUS, kDIALOG_CHARGE_CONTROL_VSET, 0x3f }, // <rdar://problem/16344890> n27: PMU CV voltage needs to be changed from POR
};
static const struct core_rails_struct soc_rails[] =
{
};
static const struct core_rails_struct cpu_rails[] =
{
};
static const struct core_rails_struct ram_rails[] =
{
};
#endif /* POWERCONFIG_PMU_SETUP */
#define NO_BATTERY_VOLTAGE 2700
#define MIN_BOOT_BATTERY_VOLTAGE 3600
#define TARGET_BOOT_BATTERY_VOLTAGE 3700
#define TARGET_BOOT_BATTERY_CAPACITY 0 // rely on SOCF flag only
#define TARGET_PRECHARGE_GG_FLAG_MASK kHDQRegFlagsMaskSOCF
#define PRECHARGE_BACKLIGHT_LEVEL 824
#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
#define TARGET_FORCE_DEBUG_PRECHARGE 1 // always precharge if "debug" precharge bit set
#define TARGET_CHARGER_HEADROOM 150
#define TARGET_CHARGER_MAX_VRECT 7500
#define TARGET_CHARGER_NEEDS_MAX_VRECT(rem_cap, max_cap) (((rem_cap) * 1000) <= ((max_cap) * 15)) /* 1.5% or lower */
#define ACC_PWR_LDO (0) // ACC_PWR not connected
#endif
target/watch2/include/target/uartconfig.h
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/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __TARGET_UARTCONFIG_H
#define __TARGET_UARTCONFIG_H
/* define one debug serial ports */
#define DEBUG_SERIAL_PORT (0)
#define HDQGAUGE_SERIAL_PORT (3)
#if SUPPORT_FPGA
#define UART_OVERSAMPLE_OVERRIDE (11)
#endif
#endif
target/watch2/init.c
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/*
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <debug.h>
#include <drivers/display.h>
#if WITH_HW_DISPLAY_PMU
#include <drivers/display_pmu.h>
#endif
#include <drivers/flash_nor.h>
#include <drivers/iic.h>
#include <drivers/power.h>
#include <lib/devicetree.h>
#include <lib/env.h>
#include <lib/mib.h>
#include <lib/paint.h>
#include <lib/syscfg.h>
#include <platform.h>
#include <platform/chipid.h>
#include <platform/gpio.h>
#include <platform/gpiodef.h>
#include <platform/memmap.h>
#include <platform/soc/hwregbase.h>
#include <platform/soc/pmgr.h>
#include <sys.h>
#include <sys/boot.h>
#include <sys/menu.h>
#include <sys/task.h>
#include <target.h>
#include "init_fpga.h"
#include "init_product.h"
#include "init_sim.h"
MIB_CONSTANT(kMIBTargetOsPictureScale, kOIDTypeUInt32, 2);
MIB_CONSTANT(kMIBTargetPictureRotate, kOIDTypeInt32, 0);
void target_early_init(void)
{
#if !CONFIG_FPGA && !CONFIG_SIM
product_target_early_init();
#endif
}
void target_late_init(void)
{
#if !CONFIG_FPGA && !CONFIG_SIM
product_target_late_init();
#endif
}
void target_init(void)
{
#if WITH_HW_FLASH_NOR
flash_nor_init(SPI_NOR0);
#endif
}
void target_quiesce_hardware(void)
{
}
void target_poweroff(void)
{
}
int target_bootprep(enum boot_target target)
{
return 0;
}
bool target_should_recover(void)
{
#if CONFIG_SIM
return sim_target_should_recover();
#elif CONFIG_FPGA
return fpga_target_should_recover();
#else
return product_target_should_recover();
#endif
}
bool target_should_poweron(bool *cold_button_boot)
{
#if CONFIG_SIM
return sim_target_should_poweron(cold_button_boot);
#elif CONFIG_FPGA
return fpga_target_should_poweron(cold_button_boot);
#else
return product_target_should_poweron(cold_button_boot);
#endif
}
bool target_should_poweroff(bool at_boot)
{
#if CONFIG_SIM
return sim_target_should_poweroff(at_boot);
#elif CONFIG_FPGA
return fpga_target_should_poweroff(at_boot);
#else
return product_target_should_poweroff(at_boot);
#endif
}
#if WITH_ENV
void target_setup_default_environment(void)
{
#if CONFIG_SIM
sim_target_setup_default_environment();
#elif CONFIG_FPGA
fpga_target_setup_default_environment();
#else
product_target_setup_default_environment();
#endif
}
#endif // WITH_ENV
#if WITH_DEVICETREE
int target_update_device_tree(void)
{
#if CONFIG_SIM
return sim_target_update_device_tree();
#elif CONFIG_FPGA
return fpga_target_update_device_tree();
#else
return product_target_update_device_tree();
#endif
}
#endif // WITH_DEVICETREE
target/watch2/init_fpga.c
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/*
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <debug.h>
#include <drivers/flash_nor.h>
#include <lib/devicetree.h>
#include <lib/env.h>
#include <lib/mib.h>
#include <platform.h>
#include <platform/gpiodef.h>
#include <platform/memmap.h>
#include <sys.h>
#include <sys/menu.h>
#include <sys/task.h>
#include <target.h>
bool fpga_target_should_recover(void)
{
return false;
}
bool fpga_target_should_poweron(bool *cold_button_boot)
{
*cold_button_boot = true;
return true;
}
bool fpga_target_should_poweroff(bool at_boot)
{
return false;
}
#if !PRODUCT_LLB
bool target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
{
return false;
}
#endif
#if WITH_ENV
void fpga_target_setup_default_environment(void)
{
env_set("boot-args", " debug=0x14e serial=3 amfi_unrestrict_task_for_pid=1 amfi_allow_any_signature=1 amfi_get_out_of_my_way=1 cs_enforcement_disable=1 no-dockfifo-uart=1", 0);
env_set("boot-device", "asp_nand", 0);
env_set("display-color-space","RGB888", 0);
env_set("display-timing", "fpga-wsvga", 0); /* defaults to no display support */
env_set("ramdisk-delay", "600000000", 0); /* This tells PurpleRestore to slow down; rdar://6345846; rdar://problem/20524682 */
env_set("idle-off", "false", 0);
env_set("bootdelay", "3", 0);
env_set("debug-uarts", "3", 0);
}
#endif
#if WITH_DEVICETREE
int fpga_target_update_device_tree(void)
{
return 0;
}
#endif
bool target_needs_chargetrap(void)
{
return false;
}
bool target_do_chargetrap(void)
{
return false;
}
#if !WITH_HW_POWER
bool power_needs_thermal_trap(void)
{
return false;
}
bool power_needs_precharge(void)
{
return false;
}
void power_cancel_buttonwait(void)
{
}
bool power_do_chargetrap(void)
{
return false;
}
bool power_is_suspended(void)
{
return false;
}
void power_will_resume(void)
{
}
bool power_has_usb(void)
{
return false;
}
int power_read_dock_id(unsigned *id)
{
return -1;
}
bool power_get_diags_dock(void)
{
return false;
}
uint32_t power_get_boot_battery_level(void)
{
return 0;
}
int power_get_nvram(uint8_t key, uint8_t *data)
{
return -1;
}
int power_set_nvram(uint8_t key, uint8_t data)
{
return -1;
}
int power_set_soc_voltage(unsigned mv, int override)
{
return -1;
}
bool force_usb_power = false;
void power_set_usb_state(bool configured, bool suspended)
{
}
int power_backlight_enable(uint32_t backlight_level)
{
return 0;
}
#endif /* ! WITH_HW_POWER */
target/watch2/init_fpga.h
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/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef _TARGET_INIT_FPGA_H
#define _TARGET_INIT_FPGA_H
bool fpga_target_should_recover(void);
bool fpga_target_should_poweron(bool *cold_button_boot);
bool fpga_target_should_poweroff(bool at_boot);
void fpga_target_setup_default_environment(void);
int fpga_target_update_device_tree(void);
#endif /* ! _TARGET_INIT_FPGA_H */
target/watch2/init_product.c
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target/watch2/init_product.h
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/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef _TARGET_INIT_PRODUCT_H
#define _TARGET_INIT_PRODUCT_H
bool product_target_should_recover(void);
bool product_target_should_poweron(bool *cold_button_boot);
bool product_target_should_poweroff(bool at_boot);
void product_target_early_init(void);
void product_target_late_init(void);
void product_target_setup_default_environment(void);
int product_target_update_device_tree(void);
#endif /* ! _TARGET_INIT_PRODUCT_H */
target/watch2/init_sim.c
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/*
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <debug.h>
#include <drivers/flash_nor.h>
#include <lib/devicetree.h>
#include <lib/env.h>
#include <lib/mib.h>
#include <platform.h>
#include <platform/gpiodef.h>
#include <platform/memmap.h>
#include <sys.h>
#include <sys/menu.h>
#include <sys/task.h>
#include <target.h>
bool sim_target_should_recover(void)
{
return false;
}
bool sim_target_should_poweron(bool *cold_button_boot)
{
*cold_button_boot = true;
return true;
}
bool sim_target_should_poweroff(bool at_boot)
{
return false;
}
#if !PRODUCT_LLB
bool target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
{
return false;
}
#endif
#if WITH_ENV
void sim_target_setup_default_environment(void)
{
env_set("boot-args", "debug=0x14e serial=3 amfi=0x83 cs_enforcement_disable=1 -disable_aslr no-dockfifo-uart=1", ENV_PERSISTENT);
env_set("boot-device", "asp_nand", 0);
env_set("display-color-space","RGB888", 0);
env_set("display-timing", "fpga-wsvga", 0);
env_set("idle-off", "false", 0);
// env_set("kaslr-slide", "0x10000000", 0);
env_set("kaslr-off", "true", 0);
env_set("wifiaddr", "12:22:33:44:55:66", 0);
env_set("ethaddr", "12:22:33:44:55:77", 0);
env_set("btaddr", "00:00:00:00:00:00", 0);
}
#endif
#if WITH_DEVICETREE
#define ROOT_DTPATH ""
int sim_target_update_device_tree(void)
{
DTNode *node;
uint32_t propSize;
char *propName;
void *propData;
// Overwrite the serial-number with data from the simplertc fastsim model
if (FindNode(0, ROOT_DTPATH, &node)) {
propName = "serial-number";
if (FindProperty(node, &propName, &propData, &propSize)) {
if (propSize != 0x20) {
dprintf(DEBUG_CRITICAL, "serial-number property size 0x%x (expected 0x20)\n", propSize);
return -1;
}
uint64_t *serial = (uint64_t *)propData;
serial[0] = *(volatile uint64_t *)0x4e000040;
serial[1] = *(volatile uint64_t *)0x4e000048;
serial[2] = *(volatile uint64_t *)0x4e000050;
serial[3] = *(volatile uint64_t *)0x4e000058;
}
}
// Overwrite the region-info with data from the simplertc fastsim model
if (FindNode(0, ROOT_DTPATH, &node)) {
propName = "region-info";
if (FindProperty(node, &propName, &propData, &propSize)) {
if (propSize != 0x20) {
dprintf(DEBUG_CRITICAL, "region-info property size 0x%x (expected 0x20)\n", propSize);
return -1;
}
uint64_t *region = (uint64_t *)propData;
region[0] = *(volatile uint64_t *)0x4e000060;
region[1] = *(volatile uint64_t *)0x4e000068;
region[2] = *(volatile uint64_t *)0x4e000070;
region[3] = *(volatile uint64_t *)0x4e000078;
}
}
return 0;
}
#endif
bool target_needs_chargetrap(void)
{
return false;
}
bool target_do_chargetrap(void)
{
return false;
}
#if !WITH_HW_POWER
bool power_needs_thermal_trap(void)
{
return false;
}
bool power_needs_precharge(void)
{
return false;
}
void power_cancel_buttonwait(void)
{
}
bool power_do_chargetrap(void)
{
return false;
}
bool power_is_suspended(void)
{
return false;
}
void power_will_resume(void)
{
}
bool power_has_usb(void)
{
return false;
}
int power_read_dock_id(unsigned *id)
{
return -1;
}
bool power_get_diags_dock(void)
{
return false;
}
uint32_t power_get_boot_battery_level(void)
{
return 0;
}
int power_get_nvram(uint8_t key, uint8_t *data)
{
return -1;
}
int power_set_nvram(uint8_t key, uint8_t data)
{
return -1;
}
int power_set_soc_voltage(unsigned mv, int override)
{
return -1;
}
bool force_usb_power = false;
void power_set_usb_state(bool configured, bool suspended)
{
}
int power_backlight_enable(uint32_t backlight_level)
{
return 0;
}
#endif /* ! WITH_HW_POWER */
target/watch2/init_sim.h
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/*
* Copyright (C) 2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef _TARGET_INIT_SIM_H
#define _TARGET_INIT_SIM_H
bool sim_target_should_recover(void);
bool sim_target_should_poweron(bool *cold_button_boot);
bool sim_target_should_poweroff(bool at_boot);
void sim_target_setup_default_environment(void);
int sim_target_update_device_tree(void);
#endif /* ! _TARGET_INIT_SIM_H */
target/watch2/pinconfig_evt.c
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/*
* Copyright (C) YEAR Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
I/O Spreadsheet version: rev 0.4.0
I/O Spreadsheet tracker: 15171729
Conversion command: csvtopinconfig.py --soc m7 --radar 15171729 --prefix evt <filename>
*/
#include <debug.h>
#include <drivers/apple/gpio.h>
#include <platform.h>
#include <platform/soc/hwregbase.h>
#include <stdint.h>
static const uint32_t pinconfig_evt_ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // 0 : I2S0_MCK -> GPIO_AP_TO_BERMUDA_CLK_XTAL1
CFG_FUNC0 | SLOW_SLEW, // 1 : I2S1_MCK -> I2S1_AP_TO_CODEC_MCLK_12M
CFG_FUNC0 | SLOW_SLEW, // 2 : SD_CLKOUT -> SDIO_AP_TO_WLAN_CLK
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 3 : SD_CMD_IO -> SDIO_AP_BI_WLAN_CMD
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 4 : SD_DATA_IO[0] -> SDIO_AP_BI_WLAN_DATA0
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 5 : SD_DATA_IO[1] -> SDIO_AP_BI_WLAN_DATA1
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 6 : SD_DATA_IO[2] -> SDIO_AP_BI_WLAN_DATA2
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 7 : SD_DATA_IO[3] -> SDIO_AP_BI_WLAN_DATA3
/* Port 1 */
CFG_FUNC0 | INPUT_SCHMITT, // 8 : SDIO_IRQ -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 9 : WL_HOST_WAKE -> GPIO_WLAN_TO_AP_IRQ
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 2 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 3 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 4 */
CFG_DISABLED, // 32 : GPIO[0] -> NC_AP_GPIO0
CFG_DISABLED, // 33 : GPIO[1] -> NC_AP_GPIO1
CFG_DISABLED, // 34 : GPIO[2] -> GPIO_BOOT_CONFIG_0
CFG_DISABLED, // 35 : GPIO[3] -> PP1V8_SW3C_SNS
CFG_DISABLED, // 36 : GPIO[4] -> NC_GPIO_BOOT_CONFIG_2
CFG_DISABLED, // 37 : GPIO[5] -> NC_GPIO_BOOT_CONFIG_3
CFG_DISABLED, // 38 : GPIO[6] -> GPIO_BOARD_ID_3
CFG_DISABLED, // 39 : GPIO[7] -> GPIO_BOARD_REV_0
/* Port 5 */
CFG_DISABLED, // 40 : GPIO[8] -> GPIO_BOARD_REV_1
CFG_DISABLED, // 41 : GPIO[9] -> GPIO_BOARD_REV_2
CFG_DISABLED, // 42 : GPIO[10] -> GPIO_BOARD_REV_3
CFG_DISABLED, // 43 : GPIO[11] -> NC_GPIO_DEV_BOOST_ALT_ID
CFG_OUT_0 | SLOW_SLEW, // 44 : GPIO[12] -> GPIO_AP_TO_BT_DEVICE_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 45 : GPIO[13] -> GPIO_CODEC_TO_AP_IRQ_L
CFG_DISABLED, // 46 : GPIO[14] -> NC_AP_GPIO14
CFG_OUT_0 | SLOW_SLEW, // 47 : GPIO[15] -> GPIO_AP_TO_BERMUDA_FW_DWLD_REQ
/* Port 6 */
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 48 : I2C1_SDA -> I2C1_AP_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 49 : I2C1_SCL -> I2C1_AP_1V8_SCL
CFG_DISABLED, // 50 : I2S0_LRCK -> NC_I2S0_LRCLK
CFG_DISABLED, // 51 : I2S0_BCLK -> NC_I2S0_BCLK
CFG_DISABLED, // 52 : I2S0_DOUT -> NC_I2S0_DOUT
CFG_DISABLED, // 53 : I2S0_DIN -> NC_I2S0_DIN
CFG_FUNC0, // 54 : I2S1_LRCK -> I2S1_CODEC_TO_AP_WCLK
CFG_FUNC0, // 55 : I2S1_BCLK -> I2S1_CODEC_TO_AP_BCLK
/* Port 7 */
CFG_FUNC0 | SLOW_SLEW, // 56 : I2S1_DOUT -> I2S1_AP_TO_CODEC_DATA
CFG_FUNC0, // 57 : I2S1_DIN -> I2S1_CODEC_TO_AP_DATA
CFG_FUNC0 | SLOW_SLEW, // 58 : UART1_TXD -> UART1_AP_TO_BT_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 59 : UART1_RXD -> UART1_BT_TO_AP_RXD
CFG_FUNC0 | SLOW_SLEW, // 60 : UART1_RTSN -> UART1_AP_TO_BT_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 61 : UART1_CTSN -> UART1_BT_TO_AP_CTS_L
CFG_FUNC0 | SLOW_SLEW, // 62 : UART2_TXD -> UART2_AP_TO_BERMUDA_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 63 : UART2_RXD -> UART2_BERMUDA_TO_AP_RXD
/* Port 8 */
CFG_FUNC0 | SLOW_SLEW, // 64 : UART2_RTSN -> UART2_AP_TO_BERMUDA_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 65 : UART2_CTSN -> UART2_BERMUDA_TO_AP_CTS_L
CFG_FUNC0 | SLOW_SLEW, // 66 : UART4_TXD -> UART4_AP_TO_WLAN_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 67 : UART4_RXD -> UART4_WLAN_TO_AP_RXD
CFG_FUNC0 | SLOW_SLEW, // 68 : UART3_RTXD -> UART3_AP_BI_GG_SWI
CFG_DISABLED, // 69 : CLK32K_OUT -> NC_CLK32K_OUT
CFG_DISABLED, // 70 : TST_CLKOUT -> AP_TST_CLKOUT
CFG_OUT_0 | SLOW_SLEW, // 71 : GPIO[16] -> AP_TO_SEAJAY_I2C_SDA_ENABLE
/* Port 9 */
CFG_DISABLED, // 72 : GPIO[17] -> GPIO_AP_TO_BSYNC_RESET_EN_L
CFG_DISABLED, // 73 : GPIO[18] -> GPIO_GRAPE_SWDCLK
CFG_DISABLED, // 74 : TMR32_PWM1 -> NC_TMR32_PWM1
CFG_IN | INPUT_SCHMITT, // 75 : TMR32_PWM2 -> DISP_BSYNC
CFG_FUNC0, // 76 : TMR32_PWM0 -> PMU_VDD_OK
CFG_FUNC0 | INPUT_SCHMITT, // 77 : DISP_TE -> DISP_BSYNC
CFG_DISABLED, // 78 : GPIO[19] -> GPIO_GRAPE_SWDIO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 79 : NAND_CEN[0] -> ANC_AP_TO_NAND_CEN<0>
/* Port 10 */
CFG_DISABLED, // 80 : NAND_CEN[1] -> NC_NAND_CEN1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 81 : NAND_IO[7] -> ANC_AP_BI_NAND_IO<7>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 82 : NAND_IO[6] -> ANC_AP_BI_NAND_IO<6>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 83 : NAND_IO[5] -> ANC_AP_BI_NAND_IO<5>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 84 : NAND_IO[4] -> ANC_AP_BI_NAND_IO<4>
CFG_DISABLED, // 85 : NAND_DQS -> NC_NAND_DQS
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 86 : NAND_REN -> ANC_AP_TO_NAND_RE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 87 : NAND_IO[3] -> ANC_AP_BI_NAND_IO<3>
/* Port 11 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 88 : NAND_IO[2] -> ANC_AP_BI_NAND_IO<2>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 89 : NAND_IO[1] -> ANC_AP_BI_NAND_IO<1>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 90 : NAND_IO[0] -> ANC_AP_BI_NAND_IO<0>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 91 : NAND_WEN -> ANC_AP_TO_NAND_WE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 92 : NAND_CLE -> ANC_AP_TO_NAND_CLE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 93 : NAND_ALE -> ANC_AP_TO_NAND_ALE
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 94 : I2C0_SDA -> I2C0_AP_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 95 : I2C0_SCL -> I2C0_AP_1V8_SCL
/* Port 12 */
CFG_DISABLED, // 96 : DISP_VSYNC -> NC_DISP_VSYNC
CFG_DISABLED, // 97 : SPI0_SCLK -> NC_GPIO_BOARD_ID_0
CFG_DISABLED, // 98 : SPI0_MOSI -> GPIO_BOARD_ID_1
CFG_DISABLED, // 99 : SPI0_MISO -> GPIO_BOARD_ID_2
CFG_DISABLED, // 100 : SPI0_SSIN -> NC_SPI0_MCK
CFG_FUNC0 | SLOW_SLEW, // 101 : UART0_TXD -> UART0_TXD
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 102 : UART0_RXD -> UART0_RXD
CFG_DISABLED, // 103 : SPI1_SCLK -> NC_SPI1_SCLK
/* Port 13 */
CFG_DISABLED, // 104 : SPI1_MOSI -> NC_SPI1_MOSI
CFG_DISABLED, // 105 : SPI1_MISO -> NC_SPI1_MISO
CFG_DISABLED, // 106 : SPI1_SSIN -> NC_SPI1_SSIN
CFG_DISABLED, // 107 : GPIO[20] -> NC_AP_GPIO20
CFG_OUT_0 | SLOW_SLEW, // 108 : GPIO[21] -> GPIO_AP_TO_WLAN_DEVICE_WAKE
CFG_IN | INPUT_SCHMITT, // 109 : GPIO[22] -> GPIO_TRISTAR_INT
CFG_DISABLED, // 110 : GPIO[23] -> GPIO_AP_TO_OPAL_LVBOOST_BUSY_L
CFG_IN, // 111 : GPIO[24] -> GPIO_OPAL_SWDIO
/* Port 14 */
CFG_IN, // 112 : GPIO[25] -> GPIO_OPAL_SWDCLK
CFG_DISABLED, // 113 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 114 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 115 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 116 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 117 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 118 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 119 : UNSPECIFIED -> UNSPECIFIED
/* Port 15 */
CFG_DISABLED, // 120 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 121 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 122 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 123 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
/* Port 16 */
CFG_DISABLED, // 128 : ENET_MDC -> NC_ENET_MDC
CFG_DISABLED, // 129 : ENET_MDIO -> NC_ENET_MDIO
CFG_DISABLED, // 130 : RMII_RXER -> GPIO_AP_TO_ORB_DEBUG
CFG_DISABLED, // 131 : RMII_TXEN -> NC_RMII_TXEN
CFG_DISABLED, // 132 : RMII_CLK -> NC_GPIO_DEV_DISPLAY_TO_AP_ID3
CFG_DISABLED, // 133 : RMII_TXD[0] -> NC_RMII_TXD0
CFG_DISABLED, // 134 : RMII_TXD[1] -> NC_FPGA_WL_REG_ON
CFG_DISABLED, // 135 : RMII_RXD[0] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID1
/* Port 17 */
CFG_DISABLED, // 136 : RMII_RXD[1] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID2
CFG_DISABLED, // 137 : RMII_CRSDV -> NC_GPIO_DEV_DISPLAY_TO_AP_ID0
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_evt_ap_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_IN | INPUT_SCHMITT, // 0 : REQUEST_DFU1 -> BUTTON1_BUFF_L
CFG_IN | INPUT_SCHMITT, // 1 : REQUEST_DFU2 -> LISA_BTN_BUFF_L
CFG_FUNC0 | INPUT_SCHMITT, // 2 : DOCK_CONNECT -> DOCK_CONNECT
CFG_DISABLED, // 3 : UNSPECIFIED -> UNSPECIFIED
CFG_OUT_0 | SLOW_SLEW, // 4 : SPU_UART0_TXD -> GPIO_SPU_TO_WLAN_CONTEXT_B
CFG_OUT_0 | SLOW_SLEW, // 5 : SPU_UART0_RXD -> GPIO_SPU_TO_WLAN_CONTEXT_A
CFG_DISABLED, // 6 : SPU_UART0_RTSN -> NC_SPU_UART0_RTSN
CFG_DISABLED, // 7 : SPU_UART0_CTSN -> NC_SPU_UART0_CTSN
/* Port 1 */
CFG_DISABLED, // 8 : SPU_UART1_TXD -> NC_SPU_UART1_TXD
CFG_DISABLED, // 9 : SPU_UART1_RXD -> NC_SPU_UART1_RXD
CFG_DISABLED, // 10 : SPU_UART1_RTSN -> NC_SPU_UART1_RTSN
CFG_DISABLED, // 11 : SPU_UART1_CTSN -> NC_SPU_UART1_CTSN
CFG_DISABLED, // 12 : SPU_GPIO[0] -> NC_SPU_GPIO0
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 13 : SPU_GPIO[1] -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_IN | INPUT_SCHMITT, // 14 : SPU_GPIO[2] -> GPIO_BT_TO_SPU_HOST_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 15 : SPU_GPIO[3] -> GPIO_SUNFISH_TO_SPU_INT_L
/* Port 2 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 16 : SPU_GPIO[4] -> GPIO_PMU_TO_SPU_IRQ_L
CFG_OUT_0 | SLOW_SLEW, // 17 : SPU_GPIO[5] -> GPIO_AP_TO_SEAJAY_RESET
CFG_OUT_0 | SLOW_SLEW, // 18 : SPU_GPIO[6] -> GPIO_SPU_TO_LVBOOST_EN
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 19 : SPU_GPIO[7] -> GPIO_BERMUDA_TO_SPU_HOST_WAKE
CFG_DISABLED, // 20 : SPU_GPIO[8] -> NC_SPU_GPIO8
CFG_OUT_0, // 21 : DFU_STATUS -> TP_DFU_STATUS
CFG_IN | PULL_DOWN, // 22 : FORCE_DFU -> TP_FORCE_DFU
CFG_FUNC0 | INPUT_SCHMITT, // 23 : PWR_GOOD -> PMU_TO_SPU_PWR_GOOD
/* Port 3 */
CFG_FUNC0 | SLOW_SLEW, // 24 : SOC_VDD_HI_LO -> SPU_TO_PMU_VDD_HI_LO
CFG_DISABLED, // 25 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 26 : DOCK_ATTENTION -> NC_DOCK_ATTENTION
CFG_DISABLED, // 27 : PMU_HOST_WAKE -> NC_PMU_HOST_WAKE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 28 : SPU_SPI_SCLK -> SPI_SPU_SCLK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 29 : SPU_SPI_MOSI -> SPI_SPU_MOSI
CFG_FUNC0 | PULL_DOWN, // 30 : SPU_SPI_MISO -> SPI_SPU_MISO
CFG_FUNC0 | SLOW_SLEW, // 31 : SPU_SPI_CS_TRIG[0] -> SCM_SPU_TO_GRAPE_CS_L
/* Port 4 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 32 : SPU_SPI_CS_TRIG[1] -> SCM_GRAPE_TO_SPU_HINT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 33 : SPU_SPI_CS_TRIG[2] -> SCM_OSMIUM_TO_SPU_INT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 34 : SPU_SPI_CS_TRIG[3] -> SCM_LISA_TO_SPU_INT_L
CFG_FUNC0 | SLOW_SLEW, // 35 : SPU_SPI_CS_TRIG[4] -> SCM_SPU_TO_CARBON_CS_L
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 36 : SPU_SPI_CS_TRIG[5] -> SCM_CARBON_TO_SPU_INT1
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 37 : SPU_SPI_CS_TRIG[6] -> SCM_CARBON_TO_SPU_INT2
CFG_DISABLED, // 38 : SPU_SPI_CS_TRIG[7] -> NC_SCM_SPU_TO_COMPASS_CS_L
CFG_DISABLED, // 39 : SPU_SPI_CS_TRIG[8] -> NC_SCM_COMPASS_TO_SPU_INT
/* Port 5 */
CFG_DISABLED, // 40 : SPU_SPI_CS_TRIG[9] -> NC_SPU_SPI_CS_TRIG9
CFG_FUNC0 | SLOW_SLEW, // 41 : SPU_SPI_CS_TRIG[10] -> SCM_SPU_TO_OPAL_CS_L
CFG_DISABLED, // 42 : SPU_SPI_CS_TRIG[11] -> NC_SPU_SPI_CS_TRIG11
CFG_IN | PULL_UP | INPUT_SCHMITT, // 43 : SPU_SPI_CS_TRIG[12] -> SCM_PT_TO_SPU_INT_L
CFG_DISABLED, // 44 : SPU_SPI_CS_TRIG[13] -> NC_SPU_SPI_CS_TRIG13
CFG_DISABLED, // 45 : SPU_SPI_CS_TRIG[14] -> NC_SPU_SPI_CS_TRIG14
CFG_DISABLED, // 46 : SPU_SPI_CS_TRIG[15] -> NC_SPU_SPI_CS_TRIG15
CFG_IN | PULL_UP, // 47 : SPU_GPIO[9] -> GPIO_SEAJAY_TO_SPU_PING_DET_L
/* Port 6 */
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 48 : SPU_I2C_SDA -> I2C_SPU_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 49 : SPU_I2C_SCL -> I2C_SPU_1V8_SCL
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_evt_dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // 0 : I2S0_MCK -> GPIO_AP_TO_BERMUDA_CLK_XTAL1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 1 : I2S1_MCK -> I2S1_AP_TO_CODEC_MCLK_12M
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : SD_CLKOUT -> SDIO_AP_TO_WLAN_CLK
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 3 : SD_CMD_IO -> SDIO_AP_BI_WLAN_CMD
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 4 : SD_DATA_IO[0] -> SDIO_AP_BI_WLAN_DATA0
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 5 : SD_DATA_IO[1] -> SDIO_AP_BI_WLAN_DATA1
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 6 : SD_DATA_IO[2] -> SDIO_AP_BI_WLAN_DATA2
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 7 : SD_DATA_IO[3] -> SDIO_AP_BI_WLAN_DATA3
/* Port 1 */
CFG_FUNC0 | INPUT_SCHMITT, // 8 : SDIO_IRQ -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 9 : WL_HOST_WAKE -> GPIO_WLAN_TO_AP_IRQ
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 2 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 3 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 4 */
CFG_DISABLED, // 32 : GPIO[0] -> NC_AP_GPIO0
CFG_DISABLED, // 33 : GPIO[1] -> NC_AP_GPIO1
CFG_DISABLED, // 34 : GPIO[2] -> GPIO_BOOT_CONFIG_0
CFG_DISABLED, // 35 : GPIO[3] -> PP1V8_SW3C_SNS
CFG_DISABLED, // 36 : GPIO[4] -> NC_GPIO_BOOT_CONFIG_2
CFG_DISABLED, // 37 : GPIO[5] -> NC_GPIO_BOOT_CONFIG_3
CFG_DISABLED, // 38 : GPIO[6] -> GPIO_BOARD_ID_3
CFG_DISABLED, // 39 : GPIO[7] -> GPIO_BOARD_REV_0
/* Port 5 */
CFG_DISABLED, // 40 : GPIO[8] -> GPIO_BOARD_REV_1
CFG_DISABLED, // 41 : GPIO[9] -> GPIO_BOARD_REV_2
CFG_DISABLED, // 42 : GPIO[10] -> GPIO_BOARD_REV_3
CFG_DISABLED, // 43 : GPIO[11] -> NC_GPIO_DEV_BOOST_ALT_ID
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 44 : GPIO[12] -> GPIO_AP_TO_BT_DEVICE_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 45 : GPIO[13] -> GPIO_CODEC_TO_AP_IRQ_L
CFG_DISABLED, // 46 : GPIO[14] -> NC_AP_GPIO14
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 47 : GPIO[15] -> GPIO_AP_TO_BERMUDA_FW_DWLD_REQ
/* Port 6 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 48 : I2C1_SDA -> I2C1_AP_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 49 : I2C1_SCL -> I2C1_AP_1V8_SCL
CFG_DISABLED, // 50 : I2S0_LRCK -> NC_I2S0_LRCLK
CFG_DISABLED, // 51 : I2S0_BCLK -> NC_I2S0_BCLK
CFG_DISABLED, // 52 : I2S0_DOUT -> NC_I2S0_DOUT
CFG_DISABLED, // 53 : I2S0_DIN -> NC_I2S0_DIN
CFG_FUNC0, // 54 : I2S1_LRCK -> I2S1_CODEC_TO_AP_WCLK
CFG_FUNC0, // 55 : I2S1_BCLK -> I2S1_CODEC_TO_AP_BCLK
/* Port 7 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 56 : I2S1_DOUT -> I2S1_AP_TO_CODEC_DATA
CFG_FUNC0, // 57 : I2S1_DIN -> I2S1_CODEC_TO_AP_DATA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 58 : UART1_TXD -> UART1_AP_TO_BT_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 59 : UART1_RXD -> UART1_BT_TO_AP_RXD
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 60 : UART1_RTSN -> UART1_AP_TO_BT_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 61 : UART1_CTSN -> UART1_BT_TO_AP_CTS_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 62 : UART2_TXD -> UART2_AP_TO_BERMUDA_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 63 : UART2_RXD -> UART2_BERMUDA_TO_AP_RXD
/* Port 8 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 64 : UART2_RTSN -> UART2_AP_TO_BERMUDA_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 65 : UART2_CTSN -> UART2_BERMUDA_TO_AP_CTS_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : UART4_TXD -> UART4_AP_TO_WLAN_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 67 : UART4_RXD -> UART4_WLAN_TO_AP_RXD
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 68 : UART3_RTXD -> UART3_AP_BI_GG_SWI
CFG_DISABLED, // 69 : CLK32K_OUT -> NC_CLK32K_OUT
CFG_DISABLED, // 70 : TST_CLKOUT -> AP_TST_CLKOUT
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 71 : GPIO[16] -> AP_TO_SEAJAY_I2C_SDA_ENABLE
/* Port 9 */
CFG_DISABLED, // 72 : GPIO[17] -> GPIO_AP_TO_BSYNC_RESET_EN_L
CFG_DISABLED, // 73 : GPIO[18] -> GPIO_GRAPE_SWDCLK
CFG_DISABLED, // 74 : TMR32_PWM1 -> NC_TMR32_PWM1
CFG_IN | INPUT_SCHMITT, // 75 : TMR32_PWM2 -> DISP_BSYNC
CFG_FUNC0, // 76 : TMR32_PWM0 -> PMU_VDD_OK
CFG_FUNC0 | INPUT_SCHMITT, // 77 : DISP_TE -> DISP_BSYNC
CFG_DISABLED, // 78 : GPIO[19] -> GPIO_GRAPE_SWDIO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 79 : NAND_CEN[0] -> ANC_AP_TO_NAND_CEN<0>
/* Port 10 */
CFG_DISABLED, // 80 : NAND_CEN[1] -> NC_NAND_CEN1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 81 : NAND_IO[7] -> ANC_AP_BI_NAND_IO<7>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 82 : NAND_IO[6] -> ANC_AP_BI_NAND_IO<6>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 83 : NAND_IO[5] -> ANC_AP_BI_NAND_IO<5>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 84 : NAND_IO[4] -> ANC_AP_BI_NAND_IO<4>
CFG_DISABLED, // 85 : NAND_DQS -> NC_NAND_DQS
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 86 : NAND_REN -> ANC_AP_TO_NAND_RE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 87 : NAND_IO[3] -> ANC_AP_BI_NAND_IO<3>
/* Port 11 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 88 : NAND_IO[2] -> ANC_AP_BI_NAND_IO<2>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 89 : NAND_IO[1] -> ANC_AP_BI_NAND_IO<1>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 90 : NAND_IO[0] -> ANC_AP_BI_NAND_IO<0>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 91 : NAND_WEN -> ANC_AP_TO_NAND_WE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 92 : NAND_CLE -> ANC_AP_TO_NAND_CLE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 93 : NAND_ALE -> ANC_AP_TO_NAND_ALE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 94 : I2C0_SDA -> I2C0_AP_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 95 : I2C0_SCL -> I2C0_AP_1V8_SCL
/* Port 12 */
CFG_DISABLED, // 96 : DISP_VSYNC -> NC_DISP_VSYNC
CFG_DISABLED, // 97 : SPI0_SCLK -> NC_GPIO_BOARD_ID_0
CFG_DISABLED, // 98 : SPI0_MOSI -> GPIO_BOARD_ID_1
CFG_DISABLED, // 99 : SPI0_MISO -> GPIO_BOARD_ID_2
CFG_DISABLED, // 100 : SPI0_SSIN -> NC_SPI0_MCK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 101 : UART0_TXD -> UART0_TXD
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 102 : UART0_RXD -> UART0_RXD
CFG_DISABLED, // 103 : SPI1_SCLK -> NC_SPI1_SCLK
/* Port 13 */
CFG_DISABLED, // 104 : SPI1_MOSI -> NC_SPI1_MOSI
CFG_DISABLED, // 105 : SPI1_MISO -> NC_SPI1_MISO
CFG_DISABLED, // 106 : SPI1_SSIN -> NC_SPI1_SSIN
CFG_DISABLED, // 107 : GPIO[20] -> NC_AP_GPIO20
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 108 : GPIO[21] -> GPIO_AP_TO_WLAN_DEVICE_WAKE
CFG_IN | INPUT_SCHMITT, // 109 : GPIO[22] -> GPIO_TRISTAR_INT
CFG_DISABLED, // 110 : GPIO[23] -> GPIO_AP_TO_OPAL_LVBOOST_BUSY_L
CFG_IN, // 111 : GPIO[24] -> GPIO_OPAL_SWDIO
/* Port 14 */
CFG_IN, // 112 : GPIO[25] -> GPIO_OPAL_SWDCLK
CFG_DISABLED, // 113 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 114 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 115 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 116 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 117 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 118 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 119 : UNSPECIFIED -> UNSPECIFIED
/* Port 15 */
CFG_DISABLED, // 120 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 121 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 122 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 123 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
/* Port 16 */
CFG_DISABLED, // 128 : ENET_MDC -> NC_ENET_MDC
CFG_DISABLED, // 129 : ENET_MDIO -> NC_ENET_MDIO
CFG_DISABLED, // 130 : RMII_RXER -> GPIO_AP_TO_ORB_DEBUG
CFG_DISABLED, // 131 : RMII_TXEN -> NC_RMII_TXEN
CFG_DISABLED, // 132 : RMII_CLK -> NC_GPIO_DEV_DISPLAY_TO_AP_ID3
CFG_DISABLED, // 133 : RMII_TXD[0] -> NC_RMII_TXD0
CFG_DISABLED, // 134 : RMII_TXD[1] -> NC_FPGA_WL_REG_ON
CFG_DISABLED, // 135 : RMII_RXD[0] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID1
/* Port 17 */
CFG_DISABLED, // 136 : RMII_RXD[1] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID2
CFG_DISABLED, // 137 : RMII_CRSDV -> NC_GPIO_DEV_DISPLAY_TO_AP_ID0
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_evt_dev_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_IN | INPUT_SCHMITT, // 0 : REQUEST_DFU1 -> BUTTON1_BUFF_L
CFG_IN | INPUT_SCHMITT, // 1 : REQUEST_DFU2 -> LISA_BTN_BUFF_L
CFG_FUNC0 | INPUT_SCHMITT, // 2 : DOCK_CONNECT -> DOCK_CONNECT
CFG_DISABLED, // 3 : UNSPECIFIED -> UNSPECIFIED
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 4 : SPU_UART0_TXD -> GPIO_SPU_TO_WLAN_CONTEXT_B
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 5 : SPU_UART0_RXD -> GPIO_SPU_TO_WLAN_CONTEXT_A
CFG_DISABLED, // 6 : SPU_UART0_RTSN -> NC_SPU_UART0_RTSN
CFG_DISABLED, // 7 : SPU_UART0_CTSN -> NC_SPU_UART0_CTSN
/* Port 1 */
CFG_DISABLED, // 8 : SPU_UART1_TXD -> NC_SPU_UART1_TXD
CFG_DISABLED, // 9 : SPU_UART1_RXD -> NC_SPU_UART1_RXD
CFG_DISABLED, // 10 : SPU_UART1_RTSN -> NC_SPU_UART1_RTSN
CFG_DISABLED, // 11 : SPU_UART1_CTSN -> NC_SPU_UART1_CTSN
CFG_DISABLED, // 12 : SPU_GPIO[0] -> NC_SPU_GPIO0
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 13 : SPU_GPIO[1] -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_IN | INPUT_SCHMITT, // 14 : SPU_GPIO[2] -> GPIO_BT_TO_SPU_HOST_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 15 : SPU_GPIO[3] -> GPIO_SUNFISH_TO_SPU_INT_L
/* Port 2 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 16 : SPU_GPIO[4] -> GPIO_PMU_TO_SPU_IRQ_L
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 17 : SPU_GPIO[5] -> GPIO_AP_TO_SEAJAY_RESET
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 18 : SPU_GPIO[6] -> GPIO_SPU_TO_LVBOOST_EN
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 19 : SPU_GPIO[7] -> GPIO_BERMUDA_TO_SPU_HOST_WAKE
CFG_DISABLED, // 20 : SPU_GPIO[8] -> NC_SPU_GPIO8
CFG_OUT_0, // 21 : DFU_STATUS -> TP_DFU_STATUS
CFG_IN | PULL_DOWN, // 22 : FORCE_DFU -> TP_FORCE_DFU
CFG_FUNC0 | INPUT_SCHMITT, // 23 : PWR_GOOD -> PMU_TO_SPU_PWR_GOOD
/* Port 3 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 24 : SOC_VDD_HI_LO -> SPU_TO_PMU_VDD_HI_LO
CFG_DISABLED, // 25 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 26 : DOCK_ATTENTION -> NC_DOCK_ATTENTION
CFG_DISABLED, // 27 : PMU_HOST_WAKE -> NC_PMU_HOST_WAKE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 28 : SPU_SPI_SCLK -> SPI_SPU_SCLK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 29 : SPU_SPI_MOSI -> SPI_SPU_MOSI
CFG_FUNC0 | PULL_DOWN, // 30 : SPU_SPI_MISO -> SPI_SPU_MISO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 31 : SPU_SPI_CS_TRIG[0] -> SCM_SPU_TO_GRAPE_CS_L
/* Port 4 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 32 : SPU_SPI_CS_TRIG[1] -> SCM_GRAPE_TO_SPU_HINT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 33 : SPU_SPI_CS_TRIG[2] -> SCM_OSMIUM_TO_SPU_INT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 34 : SPU_SPI_CS_TRIG[3] -> SCM_LISA_TO_SPU_INT_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 35 : SPU_SPI_CS_TRIG[4] -> SCM_SPU_TO_CARBON_CS_L
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 36 : SPU_SPI_CS_TRIG[5] -> SCM_CARBON_TO_SPU_INT1
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 37 : SPU_SPI_CS_TRIG[6] -> SCM_CARBON_TO_SPU_INT2
CFG_DISABLED, // 38 : SPU_SPI_CS_TRIG[7] -> NC_SCM_SPU_TO_COMPASS_CS_L
CFG_DISABLED, // 39 : SPU_SPI_CS_TRIG[8] -> NC_SCM_COMPASS_TO_SPU_INT
/* Port 5 */
CFG_DISABLED, // 40 : SPU_SPI_CS_TRIG[9] -> NC_SPU_SPI_CS_TRIG9
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 41 : SPU_SPI_CS_TRIG[10] -> SCM_SPU_TO_OPAL_CS_L
CFG_DISABLED, // 42 : SPU_SPI_CS_TRIG[11] -> NC_SPU_SPI_CS_TRIG11
CFG_IN | PULL_UP | INPUT_SCHMITT, // 43 : SPU_SPI_CS_TRIG[12] -> SCM_PT_TO_SPU_INT_L
CFG_DISABLED, // 44 : SPU_SPI_CS_TRIG[13] -> NC_SPU_SPI_CS_TRIG13
CFG_DISABLED, // 45 : SPU_SPI_CS_TRIG[14] -> NC_SPU_SPI_CS_TRIG14
CFG_DISABLED, // 46 : SPU_SPI_CS_TRIG[15] -> NC_SPU_SPI_CS_TRIG15
CFG_IN | PULL_UP, // 47 : SPU_GPIO[9] -> GPIO_SEAJAY_TO_SPU_PING_DET_L
/* Port 6 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 48 : SPU_I2C_SDA -> I2C_SPU_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 49 : SPU_I2C_SCL -> I2C_SPU_1V8_SCL
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
struct pinconfig_map {
uint32_t board_id;
uint32_t board_id_mask;
const uint32_t *pinconfigs[GPIOC_COUNT];
};
static const struct pinconfig_map cfg_map[] = {
{ 0, 1, { pinconfig_evt_ap_0, pinconfig_evt_ap_1 } },
{ 1, 1, { pinconfig_evt_dev_0, pinconfig_evt_dev_1 } },
};
const uint32_t * target_get_evt_gpio_cfg(int gpioc)
{
static const struct pinconfig_map *selected_map = NULL;
if (selected_map == NULL) {
uint32_t board_id = platform_get_board_id();
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
selected_map = &cfg_map[i];
break;
}
}
if (selected_map == NULL)
panic("no default pinconfig for board id %u", board_id);
}
ASSERT(gpioc < GPIOC_COUNT);
return selected_map->pinconfigs[gpioc];
}
target/watch2/pinconfig_fpga.c
+359
View File
@@ -0,0 +1,359 @@
/*
* Copyright (C) 2015 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
I/O Spreadsheet version: m8 io list. version 148
I/O Spreadsheet tracker: 20260553
Conversion command: csvtopinconfig.py --rom --soc m8 --config-column 'SecureROM config' --pupd-column PU/PD --copyright 2015 --radar 20260553 --netname-column 'ROM Config' <filename>
*/
#include <debug.h>
#include <drivers/apple/gpio.h>
#include <platform.h>
#include <platform/soc/hwregbase.h>
#include <stdint.h>
static const uint32_t pinconfig_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // 0 : GPIO[0] ->
CFG_DISABLED, // 1 : GPIO[1] ->
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 2 : GPIO[2] -> Boot_config[0]
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 3 : GPIO[3] -> Boot_config[1]
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 4 : GPIO[4] -> Boot_config[2]
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 5 : GPIO[5] -> Boot_config[3]
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 6 : GPIO[6] -> Board_ID[3]
CFG_DISABLED, // 7 : GPIO[7] ->
/* Port 1 */
CFG_DISABLED, // 8 : GPIO[8] ->
CFG_DISABLED, // 9 : GPIO[9] ->
CFG_DISABLED, // 10 : GPIO[10] ->
CFG_DISABLED, // 11 : GPIO[11] ->
CFG_DISABLED, // 12 : GPIO[12] ->
CFG_DISABLED, // 13 : GPIO[13] ->
CFG_DISABLED, // 14 : GPIO[14] ->
CFG_DISABLED, // 15 : GPIO[15] ->
/* Port 2 */
CFG_DISABLED, // 16 : GPIO[16] ->
CFG_DISABLED, // 17 : GPIO[17] ->
CFG_DISABLED, // 18 : TMR32_PWM1 ->
CFG_DISABLED, // 19 : TMR32_PWM2 ->
CFG_DISABLED, // 20 : TMR32_PWM0 ->
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 21 : NAND_CEN[0] ->
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 22 : NAND_CEN[1] ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 23 : NAND_IO[7] ->
/* Port 3 */
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 24 : NAND_IO[6] ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 25 : NAND_IO[5] ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 26 : NAND_IO[4] ->
CFG_DISABLED | PULL_UP | DRIVE_S4 | SLOW_SLEW, // 27 : NAND_REN ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 28 : NAND_IO[3] ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 29 : NAND_IO[2] ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 30 : NAND_IO[1] ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 31 : NAND_IO[0] ->
/* Port 4 */
CFG_DISABLED | PULL_UP | DRIVE_S4 | SLOW_SLEW, // 32 : NAND_WEN ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW, // 33 : NAND_CLE ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW, // 34 : NAND_ALE ->
CFG_DISABLED, // 35 : I2S0_LRCK ->
CFG_DISABLED, // 36 : I2S0_BCLK ->
CFG_DISABLED, // 37 : I2S0_DOUT ->
CFG_DISABLED, // 38 : I2S0_DIN ->
CFG_DISABLED, // 39 : I2S1_LRCK ->
/* Port 5 */
CFG_DISABLED, // 40 : I2S1_BCLK ->
CFG_DISABLED, // 41 : I2S1_DOUT ->
CFG_DISABLED, // 42 : I2S1_DIN ->
CFG_DISABLED, // 43 : I2S2_LRCK ->
CFG_DISABLED, // 44 : I2S2_BCLK ->
CFG_DISABLED, // 45 : I2S2_DOUT ->
CFG_DISABLED, // 46 : I2S2_DIN ->
CFG_DISABLED, // 47 : SD_CLKOUT ->
/* Port 6 */
CFG_DISABLED, // 48 : sDIO_IRQ ->
CFG_DISABLED, // 49 : SD_DATA_IO[0] ->
CFG_DISABLED, // 50 : SD_DATA_IO[1] ->
CFG_DISABLED, // 51 : SD_DATA_IO[2] ->
CFG_DISABLED, // 52 : SD_DATA_IO[3] ->
CFG_DISABLED, // 53 : SDIO_IRQ ->
CFG_DISABLED, // 54 : WL_HOST_WAKE ->
CFG_DISABLED, // 55 : ENET_MDC ->
/* Port 7 */
CFG_DISABLED, // 56 : ENET_MDIO ->
CFG_DISABLED, // 57 : RMII_RXER ->
CFG_DISABLED, // 58 : RMII_TXEN ->
CFG_DISABLED, // 59 : RMII_CLK ->
CFG_DISABLED, // 60 : RMII_TXD[0] ->
CFG_DISABLED, // 61 : RMII_TXD[1] ->
CFG_DISABLED, // 62 : RMII_RXD[0] ->
CFG_DISABLED, // 63 : RMII_RXD[1] ->
/* Port 8 */
CFG_DISABLED, // 64 : RMII_CRSDV ->
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 65 : SPI0_SCLK -> SPI0_SCLK/Board_ID[0]
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 66 : SPI0_MOSI -> SPI0_MOSI/Board_ID[1]
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 67 : SPI0_MISO -> SPI0_MISO/Board_ID[2]
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 68 : SPI0_SSIN -> SPI0_CS
CFG_DISABLED, // 69 : SPI1_SCLK ->
CFG_DISABLED, // 70 : SPI1_MOSI ->
CFG_DISABLED, // 71 : SPI1_MISO ->
/* Port 9 */
CFG_DISABLED, // 72 : SPI1_SSIN ->
CFG_DISABLED, // 73 : I2C0_SDA ->
CFG_DISABLED, // 74 : I2C0_SCL ->
CFG_DISABLED, // 75 : I2C1_SDA ->
CFG_DISABLED, // 76 : I2C1_SCL ->
CFG_DISABLED, // 77 : I2C2_0_SDA ->
CFG_DISABLED, // 78 : I2C2_0_SCL ->
CFG_DISABLED, // 79 : I2C2_1_SDA ->
/* Port 10 */
CFG_DISABLED, // 80 : I2C2_1_SCL ->
CFG_DISABLED, // 81 : UART0_TXD ->
CFG_DISABLED, // 82 : UART0_RXD ->
CFG_DISABLED, // 83 : UART3_RTXD ->
CFG_DISABLED, // 84 : UART4_TXD ->
CFG_DISABLED, // 85 : UART4_RXD ->
CFG_DISABLED, // 86 : UART5_TXD ->
CFG_DISABLED, // 87 : UART5_RXD ->
/* Port 11 */
CFG_DISABLED, // 88 : UART2_TXD ->
CFG_DISABLED, // 89 : UART2_RXD ->
CFG_DISABLED, // 90 : UART2_RTSN ->
CFG_DISABLED, // 91 : UART2_CTSN ->
CFG_DISABLED, // 92 : UART1_TXD ->
CFG_DISABLED, // 93 : UART1_RXD ->
CFG_DISABLED, // 94 : UART1_RTSN ->
CFG_DISABLED, // 95 : UART1_CTSN ->
/* Port 12 */
CFG_DISABLED, // 96 : ISP0_SDA ->
CFG_DISABLED, // 97 : ISP0_SCL ->
CFG_DISABLED, // 98 : DISP_TE ->
CFG_DISABLED, // 99 : DISP_VSYNC ->
CFG_IN | DRIVE_S4 | VERY_FAST_SLEW | INPUT_SCHMITT, // 100 : REQUEST_DFU1 -> REQUEST_DFU1
CFG_IN | DRIVE_S4 | VERY_FAST_SLEW | INPUT_SCHMITT, // 101 : REQUEST_DFU2 -> REQUEST_DFU2
CFG_IN | PULL_DOWN | DRIVE_S4 | VERY_FAST_SLEW | INPUT_SCHMITT, // 102 : FORCE_DFU -> FORCE_DFU
CFG_DISABLED, // 103 : SWD_TMS2 ->
/* Port 13 */
CFG_DISABLED, // 104 : SWD_TMS3 ->
CFG_DISABLED, // 105 : CLK32K_OUT ->
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 14 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 15 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 16 */
CFG_DISABLED, // 128 : MON[0] ->
CFG_DISABLED, // 129 : MON[1] ->
CFG_DISABLED, // 130 : MON[2] ->
CFG_DISABLED, // 131 : MON[3] ->
CFG_DISABLED, // 132 : MON[4] ->
CFG_DISABLED, // 133 : MON[5] ->
CFG_DISABLED, // 134 : MON[6] ->
CFG_DISABLED, // 135 : MON[7] ->
/* Port 17 */
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | VERY_FAST_SLEW, // 136 : DFU_STATUS -> DFU_STATUS
CFG_DISABLED, // 137 : DROOP_N ->
CFG_DISABLED, // 138 : TST_CLKOUT ->
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // 0 : AOP_I2S1_MCK ->
CFG_DISABLED, // 1 : AOP_I2S0_MCK ->
CFG_DISABLED, // 2 : AOP_PDM_CLK ->
CFG_DISABLED, // 3 : AOP_PDM_DAT ->
CFG_DISABLED, // 4 : AOP_PLED[0] ->
CFG_DISABLED, // 5 : AOP_PLED[1] ->
CFG_FUNC0 | PULL_DOWN | DRIVE_S4 | VERY_FAST_SLEW | INPUT_SCHMITT, // 6 : AOP_DOCK_CONNECT -> DOCK_CONNECT
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | VERY_FAST_SLEW, // 7 : AOP_DOCK_ATTENTION ->
/* Port 1 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 2 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 3 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 4 */
CFG_DISABLED, // 32 : AOP_PLED[2] ->
CFG_DISABLED, // 33 : AOP_PLED[3] ->
CFG_DISABLED, // 34 : AOP_PLED[4] ->
CFG_DISABLED, // 35 : AOP_PLED[5] ->
CFG_DISABLED, // 36 : AOP_PLED[6] ->
CFG_DISABLED, // 37 : AOP_PLED[7] ->
CFG_DISABLED, // 38 : AOP_MON[0] ->
CFG_DISABLED, // 39 : AOP_MON[1] ->
/* Port 5 */
CFG_DISABLED, // 40 : AOP_MON[2] ->
CFG_DISABLED, // 41 : AOP_MON[3] ->
CFG_DISABLED, // 42 : AOP_MON[4] ->
CFG_DISABLED, // 43 : AOP_MON[5] ->
CFG_DISABLED, // 44 : AOP_MON[6] ->
CFG_DISABLED, // 45 : AOP_MON[7] ->
CFG_DISABLED, // 46 : AOP_SWD_TCK_OUT ->
CFG_DISABLED, // 47 : AOP_SWD_TMS0 ->
/* Port 6 */
CFG_DISABLED, // 48 : AOP_SWD_TMS1 ->
CFG_DISABLED, // 49 : AOP_UART0_TXD ->
CFG_DISABLED, // 50 : AOP_UART0_RXD ->
CFG_DISABLED, // 51 : AOP_UART0_RTSN ->
CFG_DISABLED, // 52 : AOP_UART0_CTSN ->
CFG_DISABLED, // 53 : AOP_UART1_TXD ->
CFG_DISABLED, // 54 : AOP_UART1_RXD ->
CFG_DISABLED, // 55 : AOP_UART1_RTSN ->
/* Port 7 */
CFG_DISABLED, // 56 : AOP_UART1_CTSN ->
CFG_DISABLED, // 57 : AOP_UART2_TXD ->
CFG_DISABLED, // 58 : AOP_UART2_RXD ->
CFG_DISABLED, // 59 : AOP_SPI_CS_TRIG[0] ->
CFG_DISABLED, // 60 : AOP_SPI_CS_TRIG[1] ->
CFG_DISABLED, // 61 : AOP_SPI_CS_TRIG[2] ->
CFG_DISABLED, // 62 : AOP_SPI_CS_TRIG[3] ->
CFG_DISABLED, // 63 : AOP_SPI_CS_TRIG[4] ->
/* Port 8 */
CFG_DISABLED, // 64 : AOP_SPI_CS_TRIG[5] ->
CFG_DISABLED, // 65 : AOP_SPI_CS_TRIG[6] ->
CFG_DISABLED, // 66 : AOP_SPI_CS_TRIG[7] ->
CFG_DISABLED, // 67 : AOP_SPI_CS_TRIG[8] ->
CFG_DISABLED, // 68 : AOP_SPI_CS_TRIG[9] ->
CFG_DISABLED, // 69 : AOP_SPI_CS_TRIG[10] ->
CFG_DISABLED, // 70 : AOP_SPI_CS_TRIG[11] ->
CFG_DISABLED, // 71 : AOP_SPI_CS_TRIG[12] ->
/* Port 9 */
CFG_DISABLED, // 72 : AOP_SPI_CS_TRIG[13] ->
CFG_DISABLED, // 73 : AOP_SPI_CS_TRIG[14] ->
CFG_DISABLED, // 74 : AOP_SPI_CS_TRIG[15] ->
CFG_DISABLED, // 75 : AOP_I2C0_SDA ->
CFG_DISABLED, // 76 : AOP_I2C0_SCL ->
CFG_DISABLED, // 77 : AOP_I2C1_SDA ->
CFG_DISABLED, // 78 : AOP_I2C1_SCL ->
CFG_DISABLED, // 79 : AOP_SPI0_SCLK ->
/* Port 10 */
CFG_DISABLED, // 80 : AOP_SPI0_MOSI ->
CFG_DISABLED, // 81 : AOP_SPI0_MISO ->
CFG_DISABLED, // 82 : AOP_PSPI_CS_TRIG[3] ->
CFG_DISABLED, // 83 : AOP_PSPI_CS_TRIG[4] ->
CFG_DISABLED, // 84 : AOP_PSPI_SCLK ->
CFG_DISABLED, // 85 : AOP_PSPI_MOSI ->
CFG_DISABLED, // 86 : AOP_PSPI_MISO ->
CFG_DISABLED, // 87 : AOP_LSPI_SCLK ->
/* Port 11 */
CFG_DISABLED, // 88 : AOP_LSPI_MOSI ->
CFG_DISABLED, // 89 : AOP_LSPI_MISO ->
CFG_DISABLED, // 90 : AOP_DETECT[0] ->
CFG_DISABLED, // 91 : AOP_DETECT[1] ->
CFG_DISABLED, // 92 : AOP_PSENSE_CTRL[4] ->
CFG_DISABLED, // 93 : AOP_PSENSE_CTRL[5] ->
CFG_DISABLED, // 94 : AOP_PSENSE_CTRL[6] ->
CFG_DISABLED, // 95 : AOP_PSENSE_CTRL[7] ->
};
struct pinconfig_map {
uint32_t board_id;
uint32_t board_id_mask;
const uint32_t *pinconfigs[GPIOC_COUNT];
};
static const struct pinconfig_map cfg_map[] = {
{ 0, 0, { pinconfig_0, pinconfig_1 } },
};
const uint32_t * target_get_default_gpio_cfg(uint32_t gpioc)
{
static const struct pinconfig_map *selected_map = NULL;
if (selected_map == NULL) {
uint32_t board_id = platform_get_board_id();
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
selected_map = &cfg_map[i];
break;
}
}
if (selected_map == NULL)
panic("no default pinconfig for board id %u", board_id);
}
ASSERT(gpioc < GPIOC_COUNT);
return selected_map->pinconfigs[gpioc];
}
target/watch2/pinconfig_product.c
+108
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@@ -0,0 +1,108 @@
/*
* Copyright (C) 2009-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <debug.h>
#include <drivers/apple/gpio.h>
#include <platform/gpiodef.h>
#include <platform/soc/hwregbase.h>
#include <target.h>
#define PIN_CFG_AP 1
#include <target/pinconfig.h>
#undef PIN_CFG_AP
#define PIN_CFG_DEV 1
#include <target/pinconfig.h>
#undef PIN_CFG_DEV
extern const uint32_t* target_get_proto2a_gpio_cfg(uint32_t gpioc);
extern const uint32_t* target_get_proto2b_gpio_cfg(uint32_t gpioc);
extern const uint32_t* target_get_evt_gpio_cfg(uint32_t gpioc);
static bool board_rev_determined;
static bool use_dummy_pinconfig;
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
{
// HACK: -- the first call into target_get_default_gpio_cfg() reads
// and attempts to restore BOARD_REV[3:0] to GPIO_CFG_DEFAULT.
//
// This will result in a recursive call back into target_get_default_gpio_cfg.
// To break the recursion, while determining board rev we can reply with any pinconfig
// since it's only being used for BOARD_REV[3:0] and it's CFG_DISABLED in all pinconfigs
//
// Remove this after we no longer have BOARD_REV-dependent pinconfigs.
if (use_dummy_pinconfig)
{
return gpio_default_cfg_ap;
}
if (!board_rev_determined)
{
use_dummy_pinconfig = true;
(void)ipod6_get_board_rev();
use_dummy_pinconfig = false;
board_rev_determined = true;
}
if (ipod6_get_board_rev() == BOARD_REV_PROTON /* BOARD_REV_DEV4 == BOARD_REV_PROTON == 0xF */)
{
// ProtoN and Dev3 share a GPIO spreadsheet. Fortunately they both have the same BOARD_REV
switch (gpioc)
{
case 0:
if (target_config_ap())
return gpio_default_cfg_ap;
else
return gpio_default_cfg_dev;
break;
case 1:
if (target_config_ap())
return gpio_1_default_cfg_ap;
else
return gpio_1_default_cfg_dev;
break;
default:
panic("unknown gpio controller");
}
} else if (target_config_dev()) {
// Dev boards 0xE through 0xA are currently all based off the proto2b Dev config, per
// Board Rev tracker and email clarification from HW EE
//
if (ipod6_get_board_rev() >= 0xA)
return target_get_proto2b_gpio_cfg(gpioc);
else
panic("Unknown BOARD_REV 0x%x", ipod6_get_board_rev());
} else {
// All that remains are post-ProtoN AP products.
// The story gets more complicated here -- see Board Rev tracker spreadsheet
switch (ipod6_get_board_rev())
{
case BOARD_REV_PROTO2A:
return target_get_proto2a_gpio_cfg(gpioc);
break;
case BOARD_REV_PROTO2B:
case BOARD_REV_PROTO2X_CARDINAL:
case BOARD_REV_PROTO2B_ALT_CARBON:
case BOARD_REV_PROTO2D:
case BOARD_REV_PROTO2F:
return target_get_proto2b_gpio_cfg(gpioc);
break;
case BOARD_REV_EVT:
case BOARD_REV_EVT_ALT_CARBON:
return target_get_evt_gpio_cfg(gpioc);
break;
default:
panic("Unknown board revision 0x%x", ipod6_get_board_rev());
}
}
}
target/watch2/pinconfig_proto2a.c
+566
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@@ -0,0 +1,566 @@
/*
* Copyright (C) 2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
I/O Spreadsheet version: rev 0.3.0
I/O Spreadsheet tracker: None
Conversion command: csvtopinconfig.py --soc m7 <filename> --prefix proto2a
*/
#include <debug.h>
#include <drivers/apple/gpio.h>
#include <platform.h>
#include <platform/soc/hwregbase.h>
#include <stdint.h>
static const uint32_t pinconfig_proto2a_ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // 0 : I2S0_MCK -> GPIO_AP_TO_BERMUDA_CLK_XTAL1
CFG_FUNC0 | SLOW_SLEW, // 1 : I2S1_MCK -> I2S1_AP_TO_CODEC_MCLK_12M
CFG_FUNC0 | SLOW_SLEW, // 2 : SD_CLKOUT -> SDIO_AP_TO_WLAN_CLK
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 3 : SD_CMD_IO -> SDIO_AP_BI_WLAN_CMD
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 4 : SD_DATA_IO[0] -> SDIO_AP_BI_WLAN_DATA0
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 5 : SD_DATA_IO[1] -> SDIO_AP_BI_WLAN_DATA1
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 6 : SD_DATA_IO[2] -> SDIO_AP_BI_WLAN_DATA2
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 7 : SD_DATA_IO[3] -> SDIO_AP_BI_WLAN_DATA3
/* Port 1 */
CFG_FUNC0 | INPUT_SCHMITT, // 8 : SDIO_IRQ -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 9 : WL_HOST_WAKE -> GPIO_WLAN_TO_AP_IRQ
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 2 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 3 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 4 */
CFG_DISABLED, // 32 : GPIO[0] -> NC_AP_GPIO0
CFG_DISABLED, // 33 : GPIO[1] -> NC_AP_GPIO1
CFG_DISABLED, // 34 : GPIO[2] -> GPIO_BOOT_CONFIG_0
CFG_DISABLED, // 35 : GPIO[3] -> PP1V8_SW3C_SNS
CFG_DISABLED, // 36 : GPIO[4] -> NC_GPIO_BOOT_CONFIG_2
CFG_DISABLED, // 37 : GPIO[5] -> NC_GPIO_BOOT_CONFIG_3
CFG_DISABLED, // 38 : GPIO[6] -> GPIO_BOARD_ID_3
CFG_DISABLED, // 39 : GPIO[7] -> GPIO_BOARD_REV_0
/* Port 5 */
CFG_DISABLED, // 40 : GPIO[8] -> GPIO_BOARD_REV_1
CFG_DISABLED, // 41 : GPIO[9] -> GPIO_BOARD_REV_2
CFG_DISABLED, // 42 : GPIO[10] -> GPIO_BOARD_REV_3
CFG_DISABLED, // 43 : GPIO[11] -> NC_GPIO_DEV_BOOST_ALT_ID
CFG_OUT_0 | SLOW_SLEW, // 44 : GPIO[12] -> GPIO_AP_TO_BT_DEVICE_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 45 : GPIO[13] -> GPIO_CODEC_TO_AP_IRQ_L
CFG_OUT_0 | SLOW_SLEW, // 46 : GPIO[14] -> GPIO_AP_TO_SEAJAY_RESET
CFG_OUT_0 | SLOW_SLEW, // 47 : GPIO[15] -> GPIO_AP_TO_BERMUDA_FW_DWLD_REQ
/* Port 6 */
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 48 : I2C1_SDA -> I2C1_AP_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 49 : I2C1_SCL -> I2C1_AP_1V8_SCL
CFG_DISABLED, // 50 : I2S0_LRCK -> NC_I2S0_LRCLK
CFG_DISABLED, // 51 : I2S0_BCLK -> NC_I2S0_BCLK
CFG_DISABLED, // 52 : I2S0_DOUT -> NC_I2S0_DOUT
CFG_DISABLED, // 53 : I2S0_DIN -> NC_I2S0_DIN
CFG_FUNC0, // 54 : I2S1_LRCK -> I2S1_CODEC_TO_AP_WCLK
CFG_FUNC0, // 55 : I2S1_BCLK -> I2S1_CODEC_TO_AP_BCLK
/* Port 7 */
CFG_FUNC0 | SLOW_SLEW, // 56 : I2S1_DOUT -> I2S1_AP_TO_CODEC_DATA
CFG_FUNC0, // 57 : I2S1_DIN -> I2S1_CODEC_TO_AP_DATA
CFG_FUNC0 | SLOW_SLEW, // 58 : UART1_TXD -> UART1_AP_TO_BT_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 59 : UART1_RXD -> UART1_BT_TO_AP_RXD
CFG_FUNC0 | SLOW_SLEW, // 60 : UART1_RTSN -> UART1_AP_TO_BT_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 61 : UART1_CTSN -> UART1_BT_TO_AP_CTS_L
CFG_FUNC0 | SLOW_SLEW, // 62 : UART2_TXD -> UART2_AP_TO_BERMUDA_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 63 : UART2_RXD -> UART2_BERMUDA_TO_AP_RXD
/* Port 8 */
CFG_FUNC0 | SLOW_SLEW, // 64 : UART2_RTSN -> UART2_AP_TO_BERMUDA_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 65 : UART2_CTSN -> UART2_BERMUDA_TO_AP_CTS_L
CFG_FUNC0 | SLOW_SLEW, // 66 : UART4_TXD -> UART4_AP_TO_WLAN_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 67 : UART4_RXD -> UART4_WLAN_TO_AP_RXD
CFG_FUNC0 | SLOW_SLEW, // 68 : UART3_RTXD -> UART3_AP_BI_GG_SWI
CFG_DISABLED, // 69 : CLK32K_OUT -> NC_CLK32K_OUT
CFG_DISABLED, // 70 : TST_CLKOUT -> AP_TST_CLKOUT
CFG_DISABLED, // 71 : GPIO[16] -> NC_AP_GPIO16
/* Port 9 */
CFG_IN, // 72 : GPIO[17] -> GPIO_SEAJAY_CLOAK_EN
CFG_DISABLED, // 73 : GPIO[18] -> GPIO_GRAPE_SWDCLK
CFG_DISABLED, // 74 : TMR32_PWM1 -> NC_TMR32_PWM1
CFG_DISABLED, // 75 : TMR32_PWM2 -> NC_TMR32_PWM2
CFG_FUNC0, // 76 : TMR32_PWM0 -> PMU_VDD_OK
CFG_FUNC0, // 77 : DISP_TE -> DISP_BSYNC
CFG_DISABLED, // 78 : GPIO[19] -> GPIO_GRAPE_SWDIO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 79 : NAND_CEN[0] -> ANC_AP_TO_NAND_CEN<0>
/* Port 10 */
CFG_DISABLED, // 80 : NAND_CEN[1] -> NC_NAND_CEN1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 81 : NAND_IO[7] -> ANC_AP_BI_NAND_IO<7>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 82 : NAND_IO[6] -> ANC_AP_BI_NAND_IO<6>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 83 : NAND_IO[5] -> ANC_AP_BI_NAND_IO<5>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 84 : NAND_IO[4] -> ANC_AP_BI_NAND_IO<4>
CFG_DISABLED, // 85 : NAND_DQS -> NC_NAND_DQS
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 86 : NAND_REN -> ANC_AP_TO_NAND_RE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 87 : NAND_IO[3] -> ANC_AP_BI_NAND_IO<3>
/* Port 11 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 88 : NAND_IO[2] -> ANC_AP_BI_NAND_IO<2>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 89 : NAND_IO[1] -> ANC_AP_BI_NAND_IO<1>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 90 : NAND_IO[0] -> ANC_AP_BI_NAND_IO<0>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 91 : NAND_WEN -> ANC_AP_TO_NAND_WE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 92 : NAND_CLE -> ANC_AP_TO_NAND_CLE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 93 : NAND_ALE -> ANC_AP_TO_NAND_ALE
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 94 : I2C0_SDA -> I2C0_AP_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 95 : I2C0_SCL -> I2C0_AP_1V8_SCL
/* Port 12 */
CFG_DISABLED, // 96 : DISP_VSYNC -> NC_DISP_VSYNC
CFG_DISABLED, // 97 : SPI0_SCLK -> NC_GPIO_BOARD_ID_0
CFG_DISABLED, // 98 : SPI0_MOSI -> GPIO_BOARD_ID_1
CFG_DISABLED, // 99 : SPI0_MISO -> GPIO_BOARD_ID_2
CFG_DISABLED, // 100 : SPI0_SSIN -> NC_SPI0_MCK
CFG_FUNC0 | SLOW_SLEW, // 101 : UART0_TXD -> UART0_TXD
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 102 : UART0_RXD -> UART0_RXD
CFG_DISABLED, // 103 : SPI1_SCLK -> NC_SPI1_SCLK
/* Port 13 */
CFG_DISABLED, // 104 : SPI1_MOSI -> NC_SPI1_MOSI
CFG_DISABLED, // 105 : SPI1_MISO -> NC_SPI1_MISO
CFG_DISABLED, // 106 : SPI1_SSIN -> NC_SPI1_SSIN
CFG_DISABLED, // 107 : GPIO[20] -> NC_AP_GPIO20
CFG_OUT_0 | SLOW_SLEW, // 108 : GPIO[21] -> GPIO_AP_TO_WLAN_DEVICE_WAKE
CFG_IN | INPUT_SCHMITT, // 109 : GPIO[22] -> GPIO_TRISTAR_INT
CFG_DISABLED, // 110 : GPIO[23] -> GPIO_AP_TO_OPAL_LVBOOST_BUSY_L
CFG_IN, // 111 : GPIO[24] -> GPIO_OPAL_SWDIO
/* Port 14 */
CFG_IN, // 112 : GPIO[25] -> GPIO_OPAL_SWDCLK
CFG_DISABLED, // 113 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 114 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 115 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 116 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 117 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 118 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 119 : UNSPECIFIED -> UNSPECIFIED
/* Port 15 */
CFG_DISABLED, // 120 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 121 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 122 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 123 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
/* Port 16 */
CFG_DISABLED, // 128 : ENET_MDC -> NC_ENET_MDC
CFG_DISABLED, // 129 : ENET_MDIO -> NC_ENET_MDIO
CFG_DISABLED, // 130 : RMII_RXER -> GPIO_AP_TO_ORB_DEBUG
CFG_DISABLED, // 131 : RMII_TXEN -> NC_RMII_TXEN
CFG_DISABLED, // 132 : RMII_CLK -> NC_GPIO_DEV_DISPLAY_TO_AP_ID3
CFG_DISABLED, // 133 : RMII_TXD[0] -> NC_RMII_TXD0
CFG_DISABLED, // 134 : RMII_TXD[1] -> NC_FPGA_WL_REG_ON
CFG_DISABLED, // 135 : RMII_RXD[0] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID1
/* Port 17 */
CFG_DISABLED, // 136 : RMII_RXD[1] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID2
CFG_DISABLED, // 137 : RMII_CRSDV -> NC_GPIO_DEV_DISPLAY_TO_AP_ID0
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_proto2a_ap_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_IN | INPUT_SCHMITT, // 0 : REQUEST_DFU1 -> BUTTON1_BUFF_L
CFG_IN | INPUT_SCHMITT, // 1 : REQUEST_DFU2 -> LISA_BTN_BUFF_L
CFG_FUNC0 | INPUT_SCHMITT, // 2 : DOCK_CONNECT -> DOCK_CONNECT
CFG_DISABLED, // 3 : UNSPECIFIED -> UNSPECIFIED
CFG_OUT_0 | SLOW_SLEW, // 4 : SPU_UART0_TXD -> GPIO_SPU_TO_WLAN_CONTEXT_B
CFG_OUT_0 | SLOW_SLEW, // 5 : SPU_UART0_RXD -> GPIO_SPU_TO_WLAN_CONTEXT_A
CFG_DISABLED, // 6 : SPU_UART0_RTSN -> NC_SPU_UART0_RTSN
CFG_DISABLED, // 7 : SPU_UART0_CTSN -> NC_SPU_UART0_CTSN
/* Port 1 */
CFG_DISABLED, // 8 : SPU_UART1_TXD -> NC_SPU_UART1_TXD
CFG_DISABLED, // 9 : SPU_UART1_RXD -> NC_SPU_UART1_RXD
CFG_DISABLED, // 10 : SPU_UART1_RTSN -> NC_SPU_UART1_RTSN
CFG_DISABLED, // 11 : SPU_UART1_CTSN -> NC_SPU_UART1_CTSN
CFG_DISABLED, // 12 : SPU_GPIO[0] -> NC_SPU_GPIO0
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 13 : SPU_GPIO[1] -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_IN | INPUT_SCHMITT, // 14 : SPU_GPIO[2] -> GPIO_BT_TO_SPU_HOST_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 15 : SPU_GPIO[3] -> GPIO_SUNFISH_TO_SPU_INT_L
/* Port 2 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 16 : SPU_GPIO[4] -> GPIO_PMU_TO_SPU_IRQ_L
CFG_DISABLED, // 17 : SPU_GPIO[5] -> NC_SPU_GPIO5
CFG_OUT_0 | SLOW_SLEW, // 18 : SPU_GPIO[6] -> GPIO_SPU_TO_LVBOOST_EN
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 19 : SPU_GPIO[7] -> GPIO_BERMUDA_TO_SPU_HOST_WAKE
CFG_DISABLED, // 20 : SPU_GPIO[8] -> NC_SPU_GPIO8
CFG_OUT_0, // 21 : DFU_STATUS -> TP_DFU_STATUS
CFG_IN | PULL_DOWN, // 22 : FORCE_DFU -> TP_FORCE_DFU
CFG_FUNC0 | INPUT_SCHMITT, // 23 : PWR_GOOD -> PMU_TO_SPU_PWR_GOOD
/* Port 3 */
CFG_FUNC0 | SLOW_SLEW, // 24 : SOC_VDD_HI_LO -> SPU_TO_PMU_VDD_HI_LO
CFG_DISABLED, // 25 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 26 : DOCK_ATTENTION -> NC_DOCK_ATTENTION
CFG_DISABLED, // 27 : PMU_HOST_WAKE -> NC_PMU_HOST_WAKE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 28 : SPU_SPI_SCLK -> SPI_SPU_SCLK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 29 : SPU_SPI_MOSI -> SPI_SPU_MOSI
CFG_FUNC0 | PULL_DOWN, // 30 : SPU_SPI_MISO -> SPI_SPU_MISO
CFG_FUNC0 | SLOW_SLEW, // 31 : SPU_SPI_CS_TRIG[0] -> SCM_SPU_TO_GRAPE_CS_L
/* Port 4 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 32 : SPU_SPI_CS_TRIG[1] -> SCM_GRAPE_TO_SPU_HINT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 33 : SPU_SPI_CS_TRIG[2] -> SCM_OSMIUM_TO_SPU_INT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 34 : SPU_SPI_CS_TRIG[3] -> SCM_LISA_TO_SPU_INT_L
CFG_FUNC0 | SLOW_SLEW, // 35 : SPU_SPI_CS_TRIG[4] -> SCM_SPU_TO_CARBON_CS_L
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 36 : SPU_SPI_CS_TRIG[5] -> SCM_CARBON_TO_SPU_INT1
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 37 : SPU_SPI_CS_TRIG[6] -> SCM_CARBON_TO_SPU_INT2
CFG_DISABLED, // 38 : SPU_SPI_CS_TRIG[7] -> NC_SCM_SPU_TO_COMPASS_CS_L
CFG_DISABLED, // 39 : SPU_SPI_CS_TRIG[8] -> NC_SCM_COMPASS_TO_SPU_INT
/* Port 5 */
CFG_DISABLED, // 40 : SPU_SPI_CS_TRIG[9] -> NC_SPU_SPI_CS_TRIG9
CFG_FUNC0 | SLOW_SLEW, // 41 : SPU_SPI_CS_TRIG[10] -> SCM_SPU_TO_OPAL_CS_L
CFG_DISABLED, // 42 : SPU_SPI_CS_TRIG[11] -> NC_SPU_SPI_CS_TRIG11
CFG_IN | PULL_UP | INPUT_SCHMITT, // 43 : SPU_SPI_CS_TRIG[12] -> SCM_PT_TO_SPU_INT_L
CFG_DISABLED, // 44 : SPU_SPI_CS_TRIG[13] -> NC_SPU_SPI_CS_TRIG13
CFG_DISABLED, // 45 : SPU_SPI_CS_TRIG[14] -> NC_SPU_SPI_CS_TRIG14
CFG_DISABLED, // 46 : SPU_SPI_CS_TRIG[15] -> NC_SPU_SPI_CS_TRIG15
CFG_IN | PULL_UP, // 47 : SPU_GPIO[9] -> GPIO_SEAJAY_TO_SPU_PING_DET_L
/* Port 6 */
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 48 : SPU_I2C_SDA -> I2C_SPU_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 49 : SPU_I2C_SCL -> I2C_SPU_1V8_SCL
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_proto2a_dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // 0 : I2S0_MCK -> GPIO_AP_TO_BERMUDA_CLK_XTAL1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 1 : I2S1_MCK -> I2S1_AP_TO_CODEC_MCLK_12M
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : SD_CLKOUT -> SDIO_AP_TO_WLAN_CLK
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 3 : SD_CMD_IO -> SDIO_AP_BI_WLAN_CMD
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 4 : SD_DATA_IO[0] -> SDIO_AP_BI_WLAN_DATA0
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 5 : SD_DATA_IO[1] -> SDIO_AP_BI_WLAN_DATA1
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 6 : SD_DATA_IO[2] -> SDIO_AP_BI_WLAN_DATA2
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 7 : SD_DATA_IO[3] -> SDIO_AP_BI_WLAN_DATA3
/* Port 1 */
CFG_FUNC0 | INPUT_SCHMITT, // 8 : SDIO_IRQ -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 9 : WL_HOST_WAKE -> GPIO_WLAN_TO_AP_IRQ
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 2 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 3 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 4 */
CFG_DISABLED, // 32 : GPIO[0] -> NC_AP_GPIO0
CFG_DISABLED, // 33 : GPIO[1] -> NC_AP_GPIO1
CFG_DISABLED, // 34 : GPIO[2] -> GPIO_BOOT_CONFIG_0
CFG_DISABLED, // 35 : GPIO[3] -> PP1V8_SW3C_SNS
CFG_DISABLED, // 36 : GPIO[4] -> NC_GPIO_BOOT_CONFIG_2
CFG_DISABLED, // 37 : GPIO[5] -> NC_GPIO_BOOT_CONFIG_3
CFG_DISABLED, // 38 : GPIO[6] -> GPIO_BOARD_ID_3
CFG_DISABLED, // 39 : GPIO[7] -> GPIO_BOARD_REV_0
/* Port 5 */
CFG_DISABLED, // 40 : GPIO[8] -> GPIO_BOARD_REV_1
CFG_DISABLED, // 41 : GPIO[9] -> GPIO_BOARD_REV_2
CFG_DISABLED, // 42 : GPIO[10] -> GPIO_BOARD_REV_3
CFG_DISABLED, // 43 : GPIO[11] -> NC_GPIO_DEV_BOOST_ALT_ID
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 44 : GPIO[12] -> GPIO_AP_TO_BT_DEVICE_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 45 : GPIO[13] -> GPIO_CODEC_TO_AP_IRQ_L
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 46 : GPIO[14] -> GPIO_AP_TO_SEAJAY_RESET
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 47 : GPIO[15] -> GPIO_AP_TO_BERMUDA_FW_DWLD_REQ
/* Port 6 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 48 : I2C1_SDA -> I2C1_AP_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 49 : I2C1_SCL -> I2C1_AP_1V8_SCL
CFG_DISABLED, // 50 : I2S0_LRCK -> NC_I2S0_LRCLK
CFG_DISABLED, // 51 : I2S0_BCLK -> NC_I2S0_BCLK
CFG_DISABLED, // 52 : I2S0_DOUT -> NC_I2S0_DOUT
CFG_DISABLED, // 53 : I2S0_DIN -> NC_I2S0_DIN
CFG_FUNC0, // 54 : I2S1_LRCK -> I2S1_CODEC_TO_AP_WCLK
CFG_FUNC0, // 55 : I2S1_BCLK -> I2S1_CODEC_TO_AP_BCLK
/* Port 7 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 56 : I2S1_DOUT -> I2S1_AP_TO_CODEC_DATA
CFG_FUNC0, // 57 : I2S1_DIN -> I2S1_CODEC_TO_AP_DATA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 58 : UART1_TXD -> UART1_AP_TO_BT_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 59 : UART1_RXD -> UART1_BT_TO_AP_RXD
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 60 : UART1_RTSN -> UART1_AP_TO_BT_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 61 : UART1_CTSN -> UART1_BT_TO_AP_CTS_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 62 : UART2_TXD -> UART2_AP_TO_BERMUDA_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 63 : UART2_RXD -> UART2_BERMUDA_TO_AP_RXD
/* Port 8 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 64 : UART2_RTSN -> UART2_AP_TO_BERMUDA_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 65 : UART2_CTSN -> UART2_BERMUDA_TO_AP_CTS_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : UART4_TXD -> UART4_AP_TO_WLAN_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 67 : UART4_RXD -> UART4_WLAN_TO_AP_RXD
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 68 : UART3_RTXD -> UART3_AP_BI_GG_SWI
CFG_DISABLED, // 69 : CLK32K_OUT -> NC_CLK32K_OUT
CFG_DISABLED, // 70 : TST_CLKOUT -> AP_TST_CLKOUT
CFG_DISABLED, // 71 : GPIO[16] -> NC_AP_GPIO16
/* Port 9 */
CFG_IN, // 72 : GPIO[17] -> GPIO_SEAJAY_CLOAK_EN
CFG_DISABLED, // 73 : GPIO[18] -> GPIO_GRAPE_SWDCLK
CFG_DISABLED, // 74 : TMR32_PWM1 -> NC_TMR32_PWM1
CFG_DISABLED, // 75 : TMR32_PWM2 -> NC_TMR32_PWM2
CFG_FUNC0, // 76 : TMR32_PWM0 -> PMU_VDD_OK
CFG_FUNC0, // 77 : DISP_TE -> DISP_BSYNC
CFG_DISABLED, // 78 : GPIO[19] -> GPIO_GRAPE_SWDIO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 79 : NAND_CEN[0] -> ANC_AP_TO_NAND_CEN<0>
/* Port 10 */
CFG_DISABLED, // 80 : NAND_CEN[1] -> NC_NAND_CEN1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 81 : NAND_IO[7] -> ANC_AP_BI_NAND_IO<7>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 82 : NAND_IO[6] -> ANC_AP_BI_NAND_IO<6>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 83 : NAND_IO[5] -> ANC_AP_BI_NAND_IO<5>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 84 : NAND_IO[4] -> ANC_AP_BI_NAND_IO<4>
CFG_DISABLED, // 85 : NAND_DQS -> NC_NAND_DQS
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 86 : NAND_REN -> ANC_AP_TO_NAND_RE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 87 : NAND_IO[3] -> ANC_AP_BI_NAND_IO<3>
/* Port 11 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 88 : NAND_IO[2] -> ANC_AP_BI_NAND_IO<2>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 89 : NAND_IO[1] -> ANC_AP_BI_NAND_IO<1>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 90 : NAND_IO[0] -> ANC_AP_BI_NAND_IO<0>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 91 : NAND_WEN -> ANC_AP_TO_NAND_WE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 92 : NAND_CLE -> ANC_AP_TO_NAND_CLE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 93 : NAND_ALE -> ANC_AP_TO_NAND_ALE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 94 : I2C0_SDA -> I2C0_AP_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 95 : I2C0_SCL -> I2C0_AP_1V8_SCL
/* Port 12 */
CFG_DISABLED, // 96 : DISP_VSYNC -> NC_DISP_VSYNC
CFG_DISABLED, // 97 : SPI0_SCLK -> NC_GPIO_BOARD_ID_0
CFG_DISABLED, // 98 : SPI0_MOSI -> GPIO_BOARD_ID_1
CFG_DISABLED, // 99 : SPI0_MISO -> GPIO_BOARD_ID_2
CFG_DISABLED, // 100 : SPI0_SSIN -> NC_SPI0_MCK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 101 : UART0_TXD -> UART0_TXD
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 102 : UART0_RXD -> UART0_RXD
CFG_DISABLED, // 103 : SPI1_SCLK -> NC_SPI1_SCLK
/* Port 13 */
CFG_DISABLED, // 104 : SPI1_MOSI -> NC_SPI1_MOSI
CFG_DISABLED, // 105 : SPI1_MISO -> NC_SPI1_MISO
CFG_DISABLED, // 106 : SPI1_SSIN -> NC_SPI1_SSIN
CFG_DISABLED, // 107 : GPIO[20] -> NC_AP_GPIO20
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 108 : GPIO[21] -> GPIO_AP_TO_WLAN_DEVICE_WAKE
CFG_IN | INPUT_SCHMITT, // 109 : GPIO[22] -> GPIO_TRISTAR_INT
CFG_DISABLED, // 110 : GPIO[23] -> GPIO_AP_TO_OPAL_LVBOOST_BUSY_L
CFG_IN, // 111 : GPIO[24] -> GPIO_OPAL_SWDIO
/* Port 14 */
CFG_IN, // 112 : GPIO[25] -> GPIO_OPAL_SWDCLK
CFG_DISABLED, // 113 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 114 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 115 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 116 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 117 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 118 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 119 : UNSPECIFIED -> UNSPECIFIED
/* Port 15 */
CFG_DISABLED, // 120 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 121 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 122 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 123 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
/* Port 16 */
CFG_DISABLED, // 128 : ENET_MDC -> NC_ENET_MDC
CFG_DISABLED, // 129 : ENET_MDIO -> NC_ENET_MDIO
CFG_DISABLED, // 130 : RMII_RXER -> GPIO_AP_TO_ORB_DEBUG
CFG_DISABLED, // 131 : RMII_TXEN -> NC_RMII_TXEN
CFG_DISABLED, // 132 : RMII_CLK -> NC_GPIO_DEV_DISPLAY_TO_AP_ID3
CFG_DISABLED, // 133 : RMII_TXD[0] -> NC_RMII_TXD0
CFG_DISABLED, // 134 : RMII_TXD[1] -> NC_FPGA_WL_REG_ON
CFG_DISABLED, // 135 : RMII_RXD[0] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID1
/* Port 17 */
CFG_DISABLED, // 136 : RMII_RXD[1] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID2
CFG_DISABLED, // 137 : RMII_CRSDV -> NC_GPIO_DEV_DISPLAY_TO_AP_ID0
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_proto2a_dev_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_IN | INPUT_SCHMITT, // 0 : REQUEST_DFU1 -> BUTTON1_BUFF_L
CFG_IN | INPUT_SCHMITT, // 1 : REQUEST_DFU2 -> LISA_BTN_BUFF_L
CFG_FUNC0 | INPUT_SCHMITT, // 2 : DOCK_CONNECT -> DOCK_CONNECT
CFG_DISABLED, // 3 : UNSPECIFIED -> UNSPECIFIED
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 4 : SPU_UART0_TXD -> GPIO_SPU_TO_WLAN_CONTEXT_B
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 5 : SPU_UART0_RXD -> GPIO_SPU_TO_WLAN_CONTEXT_A
CFG_DISABLED, // 6 : SPU_UART0_RTSN -> NC_SPU_UART0_RTSN
CFG_DISABLED, // 7 : SPU_UART0_CTSN -> NC_SPU_UART0_CTSN
/* Port 1 */
CFG_DISABLED, // 8 : SPU_UART1_TXD -> NC_SPU_UART1_TXD
CFG_DISABLED, // 9 : SPU_UART1_RXD -> NC_SPU_UART1_RXD
CFG_DISABLED, // 10 : SPU_UART1_RTSN -> NC_SPU_UART1_RTSN
CFG_DISABLED, // 11 : SPU_UART1_CTSN -> NC_SPU_UART1_CTSN
CFG_DISABLED, // 12 : SPU_GPIO[0] -> NC_SPU_GPIO0
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 13 : SPU_GPIO[1] -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_IN | INPUT_SCHMITT, // 14 : SPU_GPIO[2] -> GPIO_BT_TO_SPU_HOST_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 15 : SPU_GPIO[3] -> GPIO_SUNFISH_TO_SPU_INT_L
/* Port 2 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 16 : SPU_GPIO[4] -> GPIO_PMU_TO_SPU_IRQ_L
CFG_DISABLED, // 17 : SPU_GPIO[5] -> NC_SPU_GPIO5
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 18 : SPU_GPIO[6] -> GPIO_SPU_TO_LVBOOST_EN
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 19 : SPU_GPIO[7] -> GPIO_BERMUDA_TO_SPU_HOST_WAKE
CFG_DISABLED, // 20 : SPU_GPIO[8] -> NC_SPU_GPIO8
CFG_OUT_0, // 21 : DFU_STATUS -> TP_DFU_STATUS
CFG_IN | PULL_DOWN, // 22 : FORCE_DFU -> TP_FORCE_DFU
CFG_FUNC0 | INPUT_SCHMITT, // 23 : PWR_GOOD -> PMU_TO_SPU_PWR_GOOD
/* Port 3 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 24 : SOC_VDD_HI_LO -> SPU_TO_PMU_VDD_HI_LO
CFG_DISABLED, // 25 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 26 : DOCK_ATTENTION -> NC_DOCK_ATTENTION
CFG_DISABLED, // 27 : PMU_HOST_WAKE -> NC_PMU_HOST_WAKE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 28 : SPU_SPI_SCLK -> SPI_SPU_SCLK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 29 : SPU_SPI_MOSI -> SPI_SPU_MOSI
CFG_FUNC0 | PULL_DOWN, // 30 : SPU_SPI_MISO -> SPI_SPU_MISO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 31 : SPU_SPI_CS_TRIG[0] -> SCM_SPU_TO_GRAPE_CS_L
/* Port 4 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 32 : SPU_SPI_CS_TRIG[1] -> SCM_GRAPE_TO_SPU_HINT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 33 : SPU_SPI_CS_TRIG[2] -> SCM_OSMIUM_TO_SPU_INT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 34 : SPU_SPI_CS_TRIG[3] -> SCM_LISA_TO_SPU_INT_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 35 : SPU_SPI_CS_TRIG[4] -> SCM_SPU_TO_CARBON_CS_L
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 36 : SPU_SPI_CS_TRIG[5] -> SCM_CARBON_TO_SPU_INT1
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 37 : SPU_SPI_CS_TRIG[6] -> SCM_CARBON_TO_SPU_INT2
CFG_DISABLED, // 38 : SPU_SPI_CS_TRIG[7] -> NC_SCM_SPU_TO_COMPASS_CS_L
CFG_DISABLED, // 39 : SPU_SPI_CS_TRIG[8] -> NC_SCM_COMPASS_TO_SPU_INT
/* Port 5 */
CFG_DISABLED, // 40 : SPU_SPI_CS_TRIG[9] -> NC_SPU_SPI_CS_TRIG9
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 41 : SPU_SPI_CS_TRIG[10] -> SCM_SPU_TO_OPAL_CS_L
CFG_DISABLED, // 42 : SPU_SPI_CS_TRIG[11] -> NC_SPU_SPI_CS_TRIG11
CFG_IN | PULL_UP | INPUT_SCHMITT, // 43 : SPU_SPI_CS_TRIG[12] -> SCM_PT_TO_SPU_INT_L
CFG_DISABLED, // 44 : SPU_SPI_CS_TRIG[13] -> NC_SPU_SPI_CS_TRIG13
CFG_DISABLED, // 45 : SPU_SPI_CS_TRIG[14] -> NC_SPU_SPI_CS_TRIG14
CFG_DISABLED, // 46 : SPU_SPI_CS_TRIG[15] -> NC_SPU_SPI_CS_TRIG15
CFG_IN | PULL_UP, // 47 : SPU_GPIO[9] -> GPIO_SEAJAY_TO_SPU_PING_DET_L
/* Port 6 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 48 : SPU_I2C_SDA -> I2C_SPU_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 49 : SPU_I2C_SCL -> I2C_SPU_1V8_SCL
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
struct pinconfig_map {
uint32_t board_id;
uint32_t board_id_mask;
const uint32_t *pinconfigs[GPIOC_COUNT];
};
static const struct pinconfig_map cfg_map[] = {
{ 0, 1, { pinconfig_proto2a_ap_0, pinconfig_proto2a_ap_1 } },
{ 1, 1, { pinconfig_proto2a_dev_0, pinconfig_proto2a_dev_1 } },
};
const uint32_t * target_get_proto2a_gpio_cfg(int gpioc)
{
static const struct pinconfig_map *selected_map = NULL;
if (selected_map == NULL) {
uint32_t board_id = platform_get_board_id();
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
selected_map = &cfg_map[i];
break;
}
}
if (selected_map == NULL)
panic("no default pinconfig for board id %u", board_id);
}
ASSERT(gpioc < GPIOC_COUNT);
return selected_map->pinconfigs[gpioc];
}
target/watch2/pinconfig_proto2b.c
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/*
* Copyright (C) 2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
I/O Spreadsheet version: rev 0.3.6
I/O Spreadsheet tracker: 15171729
Conversion command: csvtopinconfig.py --soc m7 --radar 15171729 --prefix proto2b <filename>
*/
#include <debug.h>
#include <drivers/apple/gpio.h>
#include <platform.h>
#include <platform/soc/hwregbase.h>
#include <stdint.h>
static const uint32_t pinconfig_proto2b_ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // 0 : I2S0_MCK -> GPIO_AP_TO_BERMUDA_CLK_XTAL1
CFG_FUNC0 | SLOW_SLEW, // 1 : I2S1_MCK -> I2S1_AP_TO_CODEC_MCLK_12M
CFG_FUNC0 | SLOW_SLEW, // 2 : SD_CLKOUT -> SDIO_AP_TO_WLAN_CLK
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 3 : SD_CMD_IO -> SDIO_AP_BI_WLAN_CMD
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 4 : SD_DATA_IO[0] -> SDIO_AP_BI_WLAN_DATA0
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 5 : SD_DATA_IO[1] -> SDIO_AP_BI_WLAN_DATA1
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 6 : SD_DATA_IO[2] -> SDIO_AP_BI_WLAN_DATA2
CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 7 : SD_DATA_IO[3] -> SDIO_AP_BI_WLAN_DATA3
/* Port 1 */
CFG_FUNC0 | INPUT_SCHMITT, // 8 : SDIO_IRQ -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 9 : WL_HOST_WAKE -> GPIO_WLAN_TO_AP_IRQ
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 2 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 3 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 4 */
CFG_DISABLED, // 32 : GPIO[0] -> NC_AP_GPIO0
CFG_DISABLED, // 33 : GPIO[1] -> NC_AP_GPIO1
CFG_DISABLED, // 34 : GPIO[2] -> GPIO_BOOT_CONFIG_0
CFG_DISABLED, // 35 : GPIO[3] -> PP1V8_SW3C_SNS
CFG_DISABLED, // 36 : GPIO[4] -> NC_GPIO_BOOT_CONFIG_2
CFG_DISABLED, // 37 : GPIO[5] -> NC_GPIO_BOOT_CONFIG_3
CFG_DISABLED, // 38 : GPIO[6] -> GPIO_BOARD_ID_3
CFG_DISABLED, // 39 : GPIO[7] -> GPIO_BOARD_REV_0
/* Port 5 */
CFG_DISABLED, // 40 : GPIO[8] -> GPIO_BOARD_REV_1
CFG_DISABLED, // 41 : GPIO[9] -> GPIO_BOARD_REV_2
CFG_DISABLED, // 42 : GPIO[10] -> GPIO_BOARD_REV_3
CFG_DISABLED, // 43 : GPIO[11] -> NC_GPIO_DEV_BOOST_ALT_ID
CFG_OUT_0 | SLOW_SLEW, // 44 : GPIO[12] -> GPIO_AP_TO_BT_DEVICE_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 45 : GPIO[13] -> GPIO_CODEC_TO_AP_IRQ_L
CFG_DISABLED, // 46 : GPIO[14] -> NC_AP_GPIO14
CFG_OUT_0 | SLOW_SLEW, // 47 : GPIO[15] -> GPIO_AP_TO_BERMUDA_FW_DWLD_REQ
/* Port 6 */
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 48 : I2C1_SDA -> I2C1_AP_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 49 : I2C1_SCL -> I2C1_AP_1V8_SCL
CFG_DISABLED, // 50 : I2S0_LRCK -> NC_I2S0_LRCLK
CFG_DISABLED, // 51 : I2S0_BCLK -> NC_I2S0_BCLK
CFG_DISABLED, // 52 : I2S0_DOUT -> NC_I2S0_DOUT
CFG_DISABLED, // 53 : I2S0_DIN -> NC_I2S0_DIN
CFG_FUNC0, // 54 : I2S1_LRCK -> I2S1_CODEC_TO_AP_WCLK
CFG_FUNC0, // 55 : I2S1_BCLK -> I2S1_CODEC_TO_AP_BCLK
/* Port 7 */
CFG_FUNC0 | SLOW_SLEW, // 56 : I2S1_DOUT -> I2S1_AP_TO_CODEC_DATA
CFG_FUNC0, // 57 : I2S1_DIN -> I2S1_CODEC_TO_AP_DATA
CFG_FUNC0 | SLOW_SLEW, // 58 : UART1_TXD -> UART1_AP_TO_BT_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 59 : UART1_RXD -> UART1_BT_TO_AP_RXD
CFG_FUNC0 | SLOW_SLEW, // 60 : UART1_RTSN -> UART1_AP_TO_BT_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 61 : UART1_CTSN -> UART1_BT_TO_AP_CTS_L
CFG_FUNC0 | SLOW_SLEW, // 62 : UART2_TXD -> UART2_AP_TO_BERMUDA_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 63 : UART2_RXD -> UART2_BERMUDA_TO_AP_RXD
/* Port 8 */
CFG_FUNC0 | SLOW_SLEW, // 64 : UART2_RTSN -> UART2_AP_TO_BERMUDA_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 65 : UART2_CTSN -> UART2_BERMUDA_TO_AP_CTS_L
CFG_FUNC0 | SLOW_SLEW, // 66 : UART4_TXD -> UART4_AP_TO_WLAN_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 67 : UART4_RXD -> UART4_WLAN_TO_AP_RXD
CFG_FUNC0 | SLOW_SLEW, // 68 : UART3_RTXD -> UART3_AP_BI_GG_SWI
CFG_DISABLED, // 69 : CLK32K_OUT -> NC_CLK32K_OUT
CFG_DISABLED, // 70 : TST_CLKOUT -> AP_TST_CLKOUT
CFG_DISABLED, // 71 : GPIO[16] -> NC_AP_GPIO16
/* Port 9 */
CFG_DISABLED, // 72 : GPIO[17] -> TP_AP_GPIO17
CFG_DISABLED, // 73 : GPIO[18] -> GPIO_GRAPE_SWDCLK
CFG_DISABLED, // 74 : TMR32_PWM1 -> NC_TMR32_PWM1
CFG_DISABLED, // 75 : TMR32_PWM2 -> NC_TMR32_PWM2
CFG_FUNC0, // 76 : TMR32_PWM0 -> PMU_VDD_OK
CFG_FUNC0, // 77 : DISP_TE -> DISP_BSYNC
CFG_DISABLED, // 78 : GPIO[19] -> GPIO_GRAPE_SWDIO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 79 : NAND_CEN[0] -> ANC_AP_TO_NAND_CEN<0>
/* Port 10 */
CFG_DISABLED, // 80 : NAND_CEN[1] -> NC_NAND_CEN1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 81 : NAND_IO[7] -> ANC_AP_BI_NAND_IO<7>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 82 : NAND_IO[6] -> ANC_AP_BI_NAND_IO<6>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 83 : NAND_IO[5] -> ANC_AP_BI_NAND_IO<5>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 84 : NAND_IO[4] -> ANC_AP_BI_NAND_IO<4>
CFG_DISABLED, // 85 : NAND_DQS -> NC_NAND_DQS
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 86 : NAND_REN -> ANC_AP_TO_NAND_RE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 87 : NAND_IO[3] -> ANC_AP_BI_NAND_IO<3>
/* Port 11 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 88 : NAND_IO[2] -> ANC_AP_BI_NAND_IO<2>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 89 : NAND_IO[1] -> ANC_AP_BI_NAND_IO<1>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 90 : NAND_IO[0] -> ANC_AP_BI_NAND_IO<0>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 91 : NAND_WEN -> ANC_AP_TO_NAND_WE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 92 : NAND_CLE -> ANC_AP_TO_NAND_CLE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 93 : NAND_ALE -> ANC_AP_TO_NAND_ALE
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 94 : I2C0_SDA -> I2C0_AP_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 95 : I2C0_SCL -> I2C0_AP_1V8_SCL
/* Port 12 */
CFG_DISABLED, // 96 : DISP_VSYNC -> NC_DISP_VSYNC
CFG_DISABLED, // 97 : SPI0_SCLK -> NC_GPIO_BOARD_ID_0
CFG_DISABLED, // 98 : SPI0_MOSI -> GPIO_BOARD_ID_1
CFG_DISABLED, // 99 : SPI0_MISO -> GPIO_BOARD_ID_2
CFG_DISABLED, // 100 : SPI0_SSIN -> NC_SPI0_MCK
CFG_FUNC0 | SLOW_SLEW, // 101 : UART0_TXD -> UART0_TXD
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 102 : UART0_RXD -> UART0_RXD
CFG_DISABLED, // 103 : SPI1_SCLK -> NC_SPI1_SCLK
/* Port 13 */
CFG_DISABLED, // 104 : SPI1_MOSI -> NC_SPI1_MOSI
CFG_DISABLED, // 105 : SPI1_MISO -> NC_SPI1_MISO
CFG_DISABLED, // 106 : SPI1_SSIN -> NC_SPI1_SSIN
CFG_DISABLED, // 107 : GPIO[20] -> NC_AP_GPIO20
CFG_OUT_0 | SLOW_SLEW, // 108 : GPIO[21] -> GPIO_AP_TO_WLAN_DEVICE_WAKE
CFG_IN | INPUT_SCHMITT, // 109 : GPIO[22] -> GPIO_TRISTAR_INT
CFG_DISABLED, // 110 : GPIO[23] -> GPIO_AP_TO_OPAL_LVBOOST_BUSY_L
CFG_IN, // 111 : GPIO[24] -> GPIO_OPAL_SWDIO
/* Port 14 */
CFG_IN, // 112 : GPIO[25] -> GPIO_OPAL_SWDCLK
CFG_DISABLED, // 113 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 114 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 115 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 116 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 117 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 118 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 119 : UNSPECIFIED -> UNSPECIFIED
/* Port 15 */
CFG_DISABLED, // 120 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 121 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 122 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 123 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
/* Port 16 */
CFG_DISABLED, // 128 : ENET_MDC -> NC_ENET_MDC
CFG_DISABLED, // 129 : ENET_MDIO -> NC_ENET_MDIO
CFG_DISABLED, // 130 : RMII_RXER -> GPIO_AP_TO_ORB_DEBUG
CFG_DISABLED, // 131 : RMII_TXEN -> NC_RMII_TXEN
CFG_DISABLED, // 132 : RMII_CLK -> NC_GPIO_DEV_DISPLAY_TO_AP_ID3
CFG_DISABLED, // 133 : RMII_TXD[0] -> NC_RMII_TXD0
CFG_DISABLED, // 134 : RMII_TXD[1] -> NC_FPGA_WL_REG_ON
CFG_DISABLED, // 135 : RMII_RXD[0] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID1
/* Port 17 */
CFG_DISABLED, // 136 : RMII_RXD[1] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID2
CFG_DISABLED, // 137 : RMII_CRSDV -> NC_GPIO_DEV_DISPLAY_TO_AP_ID0
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_proto2b_ap_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_IN | INPUT_SCHMITT, // 0 : REQUEST_DFU1 -> BUTTON1_BUFF_L
CFG_IN | INPUT_SCHMITT, // 1 : REQUEST_DFU2 -> LISA_BTN_BUFF_L
CFG_FUNC0 | INPUT_SCHMITT, // 2 : DOCK_CONNECT -> DOCK_CONNECT
CFG_DISABLED | INPUT_SCHMITT, // 3 : CLK32K_IN -> GPIO_PMU_TO_SPU_CLK32K_IN
CFG_OUT_0 | SLOW_SLEW, // 4 : SPU_UART0_TXD -> GPIO_SPU_TO_WLAN_CONTEXT_B
CFG_OUT_0 | SLOW_SLEW, // 5 : SPU_UART0_RXD -> GPIO_SPU_TO_WLAN_CONTEXT_A
CFG_DISABLED, // 6 : SPU_UART0_RTSN -> NC_SPU_UART0_RTSN
CFG_DISABLED, // 7 : SPU_UART0_CTSN -> NC_SPU_UART0_CTSN
/* Port 1 */
CFG_DISABLED, // 8 : SPU_UART1_TXD -> NC_SPU_UART1_TXD
CFG_DISABLED, // 9 : SPU_UART1_RXD -> NC_SPU_UART1_RXD
CFG_DISABLED, // 10 : SPU_UART1_RTSN -> NC_SPU_UART1_RTSN
CFG_DISABLED, // 11 : SPU_UART1_CTSN -> NC_SPU_UART1_CTSN
CFG_DISABLED, // 12 : SPU_GPIO[0] -> NC_SPU_GPIO0
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 13 : SPU_GPIO[1] -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_IN | INPUT_SCHMITT, // 14 : SPU_GPIO[2] -> GPIO_BT_TO_SPU_HOST_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 15 : SPU_GPIO[3] -> GPIO_SUNFISH_TO_SPU_INT_L
/* Port 2 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 16 : SPU_GPIO[4] -> GPIO_PMU_TO_SPU_IRQ_L
CFG_OUT_0 | SLOW_SLEW, // 17 : SPU_GPIO[5] -> GPIO_AP_TO_SEAJAY_RESET
CFG_OUT_0 | SLOW_SLEW, // 18 : SPU_GPIO[6] -> GPIO_SPU_TO_LVBOOST_EN
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 19 : SPU_GPIO[7] -> GPIO_BERMUDA_TO_SPU_HOST_WAKE
CFG_DISABLED, // 20 : SPU_GPIO[8] -> NC_SPU_GPIO8
CFG_OUT_0, // 21 : DFU_STATUS -> TP_DFU_STATUS
CFG_IN | PULL_DOWN, // 22 : FORCE_DFU -> TP_FORCE_DFU
CFG_FUNC0 | INPUT_SCHMITT, // 23 : PWR_GOOD -> PMU_TO_SPU_PWR_GOOD
/* Port 3 */
CFG_FUNC0 | SLOW_SLEW, // 24 : SOC_VDD_HI_LO -> SPU_TO_PMU_VDD_HI_LO
CFG_DISABLED, // 25 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 26 : DOCK_ATTENTION -> NC_DOCK_ATTENTION
CFG_DISABLED, // 27 : PMU_HOST_WAKE -> NC_PMU_HOST_WAKE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 28 : SPU_SPI_SCLK -> SPI_SPU_SCLK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 29 : SPU_SPI_MOSI -> SPI_SPU_MOSI
CFG_FUNC0 | PULL_DOWN, // 30 : SPU_SPI_MISO -> SPI_SPU_MISO
CFG_FUNC0 | SLOW_SLEW, // 31 : SPU_SPI_CS_TRIG[0] -> SCM_SPU_TO_GRAPE_CS_L
/* Port 4 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 32 : SPU_SPI_CS_TRIG[1] -> SCM_GRAPE_TO_SPU_HINT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 33 : SPU_SPI_CS_TRIG[2] -> SCM_OSMIUM_TO_SPU_INT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 34 : SPU_SPI_CS_TRIG[3] -> SCM_LISA_TO_SPU_INT_L
CFG_FUNC0 | SLOW_SLEW, // 35 : SPU_SPI_CS_TRIG[4] -> SCM_SPU_TO_CARBON_CS_L
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 36 : SPU_SPI_CS_TRIG[5] -> SCM_CARBON_TO_SPU_INT1
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 37 : SPU_SPI_CS_TRIG[6] -> SCM_CARBON_TO_SPU_INT2
CFG_DISABLED, // 38 : SPU_SPI_CS_TRIG[7] -> NC_SCM_SPU_TO_COMPASS_CS_L
CFG_DISABLED, // 39 : SPU_SPI_CS_TRIG[8] -> NC_SCM_COMPASS_TO_SPU_INT
/* Port 5 */
CFG_DISABLED, // 40 : SPU_SPI_CS_TRIG[9] -> NC_SPU_SPI_CS_TRIG9
CFG_FUNC0 | SLOW_SLEW, // 41 : SPU_SPI_CS_TRIG[10] -> SCM_SPU_TO_OPAL_CS_L
CFG_DISABLED, // 42 : SPU_SPI_CS_TRIG[11] -> NC_SPU_SPI_CS_TRIG11
CFG_IN | PULL_UP | INPUT_SCHMITT, // 43 : SPU_SPI_CS_TRIG[12] -> SCM_PT_TO_SPU_INT_L
CFG_DISABLED, // 44 : SPU_SPI_CS_TRIG[13] -> NC_SPU_SPI_CS_TRIG13
CFG_DISABLED, // 45 : SPU_SPI_CS_TRIG[14] -> NC_SPU_SPI_CS_TRIG14
CFG_DISABLED, // 46 : SPU_SPI_CS_TRIG[15] -> NC_SPU_SPI_CS_TRIG15
CFG_IN | PULL_UP, // 47 : SPU_GPIO[9] -> GPIO_SEAJAY_TO_SPU_PING_DET_L
/* Port 6 */
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 48 : SPU_I2C_SDA -> I2C_SPU_1V8_SDA
CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT, // 49 : SPU_I2C_SCL -> I2C_SPU_1V8_SCL
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_proto2b_dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // 0 : I2S0_MCK -> GPIO_AP_TO_BERMUDA_CLK_XTAL1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 1 : I2S1_MCK -> I2S1_AP_TO_CODEC_MCLK_12M
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 2 : SD_CLKOUT -> SDIO_AP_TO_WLAN_CLK
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 3 : SD_CMD_IO -> SDIO_AP_BI_WLAN_CMD
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 4 : SD_DATA_IO[0] -> SDIO_AP_BI_WLAN_DATA0
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 5 : SD_DATA_IO[1] -> SDIO_AP_BI_WLAN_DATA1
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 6 : SD_DATA_IO[2] -> SDIO_AP_BI_WLAN_DATA2
CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 7 : SD_DATA_IO[3] -> SDIO_AP_BI_WLAN_DATA3
/* Port 1 */
CFG_FUNC0 | INPUT_SCHMITT, // 8 : SDIO_IRQ -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 9 : WL_HOST_WAKE -> GPIO_WLAN_TO_AP_IRQ
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 2 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 3 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 4 */
CFG_DISABLED, // 32 : GPIO[0] -> NC_AP_GPIO0
CFG_DISABLED, // 33 : GPIO[1] -> NC_AP_GPIO1
CFG_DISABLED, // 34 : GPIO[2] -> GPIO_BOOT_CONFIG_0
CFG_DISABLED, // 35 : GPIO[3] -> PP1V8_SW3C_SNS
CFG_DISABLED, // 36 : GPIO[4] -> NC_GPIO_BOOT_CONFIG_2
CFG_DISABLED, // 37 : GPIO[5] -> NC_GPIO_BOOT_CONFIG_3
CFG_DISABLED, // 38 : GPIO[6] -> GPIO_BOARD_ID_3
CFG_DISABLED, // 39 : GPIO[7] -> GPIO_BOARD_REV_0
/* Port 5 */
CFG_DISABLED, // 40 : GPIO[8] -> GPIO_BOARD_REV_1
CFG_DISABLED, // 41 : GPIO[9] -> GPIO_BOARD_REV_2
CFG_DISABLED, // 42 : GPIO[10] -> GPIO_BOARD_REV_3
CFG_DISABLED, // 43 : GPIO[11] -> NC_GPIO_DEV_BOOST_ALT_ID
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 44 : GPIO[12] -> GPIO_AP_TO_BT_DEVICE_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 45 : GPIO[13] -> GPIO_CODEC_TO_AP_IRQ_L
CFG_DISABLED, // 46 : GPIO[14] -> NC_AP_GPIO14
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 47 : GPIO[15] -> GPIO_AP_TO_BERMUDA_FW_DWLD_REQ
/* Port 6 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 48 : I2C1_SDA -> I2C1_AP_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 49 : I2C1_SCL -> I2C1_AP_1V8_SCL
CFG_DISABLED, // 50 : I2S0_LRCK -> NC_I2S0_LRCLK
CFG_DISABLED, // 51 : I2S0_BCLK -> NC_I2S0_BCLK
CFG_DISABLED, // 52 : I2S0_DOUT -> NC_I2S0_DOUT
CFG_DISABLED, // 53 : I2S0_DIN -> NC_I2S0_DIN
CFG_FUNC0, // 54 : I2S1_LRCK -> I2S1_CODEC_TO_AP_WCLK
CFG_FUNC0, // 55 : I2S1_BCLK -> I2S1_CODEC_TO_AP_BCLK
/* Port 7 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 56 : I2S1_DOUT -> I2S1_AP_TO_CODEC_DATA
CFG_FUNC0, // 57 : I2S1_DIN -> I2S1_CODEC_TO_AP_DATA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 58 : UART1_TXD -> UART1_AP_TO_BT_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 59 : UART1_RXD -> UART1_BT_TO_AP_RXD
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 60 : UART1_RTSN -> UART1_AP_TO_BT_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 61 : UART1_CTSN -> UART1_BT_TO_AP_CTS_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 62 : UART2_TXD -> UART2_AP_TO_BERMUDA_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 63 : UART2_RXD -> UART2_BERMUDA_TO_AP_RXD
/* Port 8 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 64 : UART2_RTSN -> UART2_AP_TO_BERMUDA_RTS_L
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 65 : UART2_CTSN -> UART2_BERMUDA_TO_AP_CTS_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 66 : UART4_TXD -> UART4_AP_TO_WLAN_TXD
CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 67 : UART4_RXD -> UART4_WLAN_TO_AP_RXD
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 68 : UART3_RTXD -> UART3_AP_BI_GG_SWI
CFG_DISABLED, // 69 : CLK32K_OUT -> NC_CLK32K_OUT
CFG_DISABLED, // 70 : TST_CLKOUT -> AP_TST_CLKOUT
CFG_DISABLED, // 71 : GPIO[16] -> NC_AP_GPIO16
/* Port 9 */
CFG_DISABLED, // 72 : GPIO[17] -> TP_AP_GPIO17
CFG_DISABLED, // 73 : GPIO[18] -> GPIO_GRAPE_SWDCLK
CFG_DISABLED, // 74 : TMR32_PWM1 -> NC_TMR32_PWM1
CFG_DISABLED, // 75 : TMR32_PWM2 -> NC_TMR32_PWM2
CFG_FUNC0, // 76 : TMR32_PWM0 -> PMU_VDD_OK
CFG_FUNC0, // 77 : DISP_TE -> DISP_BSYNC
CFG_DISABLED, // 78 : GPIO[19] -> GPIO_GRAPE_SWDIO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 79 : NAND_CEN[0] -> ANC_AP_TO_NAND_CEN<0>
/* Port 10 */
CFG_DISABLED, // 80 : NAND_CEN[1] -> NC_NAND_CEN1
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 81 : NAND_IO[7] -> ANC_AP_BI_NAND_IO<7>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 82 : NAND_IO[6] -> ANC_AP_BI_NAND_IO<6>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 83 : NAND_IO[5] -> ANC_AP_BI_NAND_IO<5>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 84 : NAND_IO[4] -> ANC_AP_BI_NAND_IO<4>
CFG_DISABLED, // 85 : NAND_DQS -> NC_NAND_DQS
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 86 : NAND_REN -> ANC_AP_TO_NAND_RE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 87 : NAND_IO[3] -> ANC_AP_BI_NAND_IO<3>
/* Port 11 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 88 : NAND_IO[2] -> ANC_AP_BI_NAND_IO<2>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 89 : NAND_IO[1] -> ANC_AP_BI_NAND_IO<1>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 90 : NAND_IO[0] -> ANC_AP_BI_NAND_IO<0>
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 91 : NAND_WEN -> ANC_AP_TO_NAND_WE_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 92 : NAND_CLE -> ANC_AP_TO_NAND_CLE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 93 : NAND_ALE -> ANC_AP_TO_NAND_ALE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 94 : I2C0_SDA -> I2C0_AP_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 95 : I2C0_SCL -> I2C0_AP_1V8_SCL
/* Port 12 */
CFG_DISABLED, // 96 : DISP_VSYNC -> NC_DISP_VSYNC
CFG_DISABLED, // 97 : SPI0_SCLK -> NC_GPIO_BOARD_ID_0
CFG_DISABLED, // 98 : SPI0_MOSI -> GPIO_BOARD_ID_1
CFG_DISABLED, // 99 : SPI0_MISO -> GPIO_BOARD_ID_2
CFG_DISABLED, // 100 : SPI0_SSIN -> NC_SPI0_MCK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 101 : UART0_TXD -> UART0_TXD
CFG_FUNC0 | PULL_DOWN | INPUT_SCHMITT, // 102 : UART0_RXD -> UART0_RXD
CFG_DISABLED, // 103 : SPI1_SCLK -> NC_SPI1_SCLK
/* Port 13 */
CFG_DISABLED, // 104 : SPI1_MOSI -> NC_SPI1_MOSI
CFG_DISABLED, // 105 : SPI1_MISO -> NC_SPI1_MISO
CFG_DISABLED, // 106 : SPI1_SSIN -> NC_SPI1_SSIN
CFG_DISABLED, // 107 : GPIO[20] -> NC_AP_GPIO20
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 108 : GPIO[21] -> GPIO_AP_TO_WLAN_DEVICE_WAKE
CFG_IN | INPUT_SCHMITT, // 109 : GPIO[22] -> GPIO_TRISTAR_INT
CFG_DISABLED, // 110 : GPIO[23] -> GPIO_AP_TO_OPAL_LVBOOST_BUSY_L
CFG_IN, // 111 : GPIO[24] -> GPIO_OPAL_SWDIO
/* Port 14 */
CFG_IN, // 112 : GPIO[25] -> GPIO_OPAL_SWDCLK
CFG_DISABLED, // 113 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 114 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 115 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 116 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 117 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 118 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 119 : UNSPECIFIED -> UNSPECIFIED
/* Port 15 */
CFG_DISABLED, // 120 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 121 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 122 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 123 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 124 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 125 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 126 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 127 : UNSPECIFIED -> UNSPECIFIED
/* Port 16 */
CFG_DISABLED, // 128 : ENET_MDC -> NC_ENET_MDC
CFG_DISABLED, // 129 : ENET_MDIO -> NC_ENET_MDIO
CFG_DISABLED, // 130 : RMII_RXER -> GPIO_AP_TO_ORB_DEBUG
CFG_DISABLED, // 131 : RMII_TXEN -> NC_RMII_TXEN
CFG_DISABLED, // 132 : RMII_CLK -> NC_GPIO_DEV_DISPLAY_TO_AP_ID3
CFG_DISABLED, // 133 : RMII_TXD[0] -> NC_RMII_TXD0
CFG_DISABLED, // 134 : RMII_TXD[1] -> NC_FPGA_WL_REG_ON
CFG_DISABLED, // 135 : RMII_RXD[0] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID1
/* Port 17 */
CFG_DISABLED, // 136 : RMII_RXD[1] -> NC_GPIO_DEV_DISPLAY_TO_AP_ID2
CFG_DISABLED, // 137 : RMII_CRSDV -> NC_GPIO_DEV_DISPLAY_TO_AP_ID0
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_proto2b_dev_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_IN | INPUT_SCHMITT, // 0 : REQUEST_DFU1 -> BUTTON1_BUFF_L
CFG_IN | INPUT_SCHMITT, // 1 : REQUEST_DFU2 -> LISA_BTN_BUFF_L
CFG_FUNC0 | INPUT_SCHMITT, // 2 : DOCK_CONNECT -> DOCK_CONNECT
CFG_DISABLED | INPUT_SCHMITT, // 3 : CLK32K_IN -> GPIO_PMU_TO_SPU_CLK32K_IN
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 4 : SPU_UART0_TXD -> GPIO_SPU_TO_WLAN_CONTEXT_B
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 5 : SPU_UART0_RXD -> GPIO_SPU_TO_WLAN_CONTEXT_A
CFG_DISABLED, // 6 : SPU_UART0_RTSN -> NC_SPU_UART0_RTSN
CFG_DISABLED, // 7 : SPU_UART0_CTSN -> NC_SPU_UART0_CTSN
/* Port 1 */
CFG_DISABLED, // 8 : SPU_UART1_TXD -> NC_SPU_UART1_TXD
CFG_DISABLED, // 9 : SPU_UART1_RXD -> NC_SPU_UART1_RXD
CFG_DISABLED, // 10 : SPU_UART1_RTSN -> NC_SPU_UART1_RTSN
CFG_DISABLED, // 11 : SPU_UART1_CTSN -> NC_SPU_UART1_CTSN
CFG_DISABLED, // 12 : SPU_GPIO[0] -> NC_SPU_GPIO0
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 13 : SPU_GPIO[1] -> GPIO_WLAN_TO_SPU_HOST_WAKE_SDIO_IRQ
CFG_IN | INPUT_SCHMITT, // 14 : SPU_GPIO[2] -> GPIO_BT_TO_SPU_HOST_WAKE
CFG_IN | PULL_UP | INPUT_SCHMITT, // 15 : SPU_GPIO[3] -> GPIO_SUNFISH_TO_SPU_INT_L
/* Port 2 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 16 : SPU_GPIO[4] -> GPIO_PMU_TO_SPU_IRQ_L
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 17 : SPU_GPIO[5] -> GPIO_AP_TO_SEAJAY_RESET
CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW, // 18 : SPU_GPIO[6] -> GPIO_SPU_TO_LVBOOST_EN
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 19 : SPU_GPIO[7] -> GPIO_BERMUDA_TO_SPU_HOST_WAKE
CFG_DISABLED, // 20 : SPU_GPIO[8] -> NC_SPU_GPIO8
CFG_OUT_0, // 21 : DFU_STATUS -> TP_DFU_STATUS
CFG_IN | PULL_DOWN, // 22 : FORCE_DFU -> TP_FORCE_DFU
CFG_FUNC0 | INPUT_SCHMITT, // 23 : PWR_GOOD -> PMU_TO_SPU_PWR_GOOD
/* Port 3 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 24 : SOC_VDD_HI_LO -> SPU_TO_PMU_VDD_HI_LO
CFG_DISABLED, // 25 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED, // 26 : DOCK_ATTENTION -> NC_DOCK_ATTENTION
CFG_DISABLED, // 27 : PMU_HOST_WAKE -> NC_PMU_HOST_WAKE
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 28 : SPU_SPI_SCLK -> SPI_SPU_SCLK
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 29 : SPU_SPI_MOSI -> SPI_SPU_MOSI
CFG_FUNC0 | PULL_DOWN, // 30 : SPU_SPI_MISO -> SPI_SPU_MISO
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 31 : SPU_SPI_CS_TRIG[0] -> SCM_SPU_TO_GRAPE_CS_L
/* Port 4 */
CFG_IN | PULL_UP | INPUT_SCHMITT, // 32 : SPU_SPI_CS_TRIG[1] -> SCM_GRAPE_TO_SPU_HINT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 33 : SPU_SPI_CS_TRIG[2] -> SCM_OSMIUM_TO_SPU_INT_L
CFG_IN | PULL_UP | INPUT_SCHMITT, // 34 : SPU_SPI_CS_TRIG[3] -> SCM_LISA_TO_SPU_INT_L
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 35 : SPU_SPI_CS_TRIG[4] -> SCM_SPU_TO_CARBON_CS_L
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 36 : SPU_SPI_CS_TRIG[5] -> SCM_CARBON_TO_SPU_INT1
CFG_IN | PULL_DOWN | INPUT_SCHMITT, // 37 : SPU_SPI_CS_TRIG[6] -> SCM_CARBON_TO_SPU_INT2
CFG_DISABLED, // 38 : SPU_SPI_CS_TRIG[7] -> NC_SCM_SPU_TO_COMPASS_CS_L
CFG_DISABLED, // 39 : SPU_SPI_CS_TRIG[8] -> NC_SCM_COMPASS_TO_SPU_INT
/* Port 5 */
CFG_DISABLED, // 40 : SPU_SPI_CS_TRIG[9] -> NC_SPU_SPI_CS_TRIG9
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW, // 41 : SPU_SPI_CS_TRIG[10] -> SCM_SPU_TO_OPAL_CS_L
CFG_DISABLED, // 42 : SPU_SPI_CS_TRIG[11] -> NC_SPU_SPI_CS_TRIG11
CFG_IN | PULL_UP | INPUT_SCHMITT, // 43 : SPU_SPI_CS_TRIG[12] -> SCM_PT_TO_SPU_INT_L
CFG_DISABLED, // 44 : SPU_SPI_CS_TRIG[13] -> NC_SPU_SPI_CS_TRIG13
CFG_DISABLED, // 45 : SPU_SPI_CS_TRIG[14] -> NC_SPU_SPI_CS_TRIG14
CFG_DISABLED, // 46 : SPU_SPI_CS_TRIG[15] -> NC_SPU_SPI_CS_TRIG15
CFG_IN | PULL_UP, // 47 : SPU_GPIO[9] -> GPIO_SEAJAY_TO_SPU_PING_DET_L
/* Port 6 */
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 48 : SPU_I2C_SDA -> I2C_SPU_1V8_SDA
CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT, // 49 : SPU_I2C_SCL -> I2C_SPU_1V8_SCL
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
struct pinconfig_map {
uint32_t board_id;
uint32_t board_id_mask;
const uint32_t *pinconfigs[GPIOC_COUNT];
};
static const struct pinconfig_map cfg_map[] = {
{ 0, 1, { pinconfig_proto2b_ap_0, pinconfig_proto2b_ap_1 } },
{ 1, 1, { pinconfig_proto2b_dev_0, pinconfig_proto2b_dev_1 } },
};
const uint32_t * target_get_proto2b_gpio_cfg(int gpioc)
{
static const struct pinconfig_map *selected_map = NULL;
if (selected_map == NULL) {
uint32_t board_id = platform_get_board_id();
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
selected_map = &cfg_map[i];
break;
}
}
if (selected_map == NULL)
panic("no default pinconfig for board id %u", board_id);
}
ASSERT(gpioc < GPIOC_COUNT);
return selected_map->pinconfigs[gpioc];
}
target/watch2/pinconfig_sim.c
+359
View File
@@ -0,0 +1,359 @@
/*
* Copyright (C) 2015 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
I/O Spreadsheet version: m8 io list. version 148
I/O Spreadsheet tracker: 20260553
Conversion command: csvtopinconfig.py --rom --soc m8 --config-column 'SecureROM config' --pupd-column PU/PD --copyright 2015 --radar 20260553 --netname-column 'ROM Config' <filename>
*/
#include <debug.h>
#include <drivers/apple/gpio.h>
#include <platform.h>
#include <platform/soc/hwregbase.h>
#include <stdint.h>
static const uint32_t pinconfig_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // 0 : GPIO[0] ->
CFG_DISABLED, // 1 : GPIO[1] ->
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 2 : GPIO[2] -> Boot_config[0]
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 3 : GPIO[3] -> Boot_config[1]
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 4 : GPIO[4] -> Boot_config[2]
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 5 : GPIO[5] -> Boot_config[3]
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 6 : GPIO[6] -> Board_ID[3]
CFG_DISABLED, // 7 : GPIO[7] ->
/* Port 1 */
CFG_DISABLED, // 8 : GPIO[8] ->
CFG_DISABLED, // 9 : GPIO[9] ->
CFG_DISABLED, // 10 : GPIO[10] ->
CFG_DISABLED, // 11 : GPIO[11] ->
CFG_DISABLED, // 12 : GPIO[12] ->
CFG_DISABLED, // 13 : GPIO[13] ->
CFG_DISABLED, // 14 : GPIO[14] ->
CFG_DISABLED, // 15 : GPIO[15] ->
/* Port 2 */
CFG_DISABLED, // 16 : GPIO[16] ->
CFG_DISABLED, // 17 : GPIO[17] ->
CFG_DISABLED, // 18 : TMR32_PWM1 ->
CFG_DISABLED, // 19 : TMR32_PWM2 ->
CFG_DISABLED, // 20 : TMR32_PWM0 ->
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 21 : NAND_CEN[0] ->
CFG_DISABLED | DRIVE_S4 | SLOW_SLEW, // 22 : NAND_CEN[1] ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 23 : NAND_IO[7] ->
/* Port 3 */
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 24 : NAND_IO[6] ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 25 : NAND_IO[5] ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 26 : NAND_IO[4] ->
CFG_DISABLED | PULL_UP | DRIVE_S4 | SLOW_SLEW, // 27 : NAND_REN ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 28 : NAND_IO[3] ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 29 : NAND_IO[2] ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 30 : NAND_IO[1] ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW | INPUT_SCHMITT, // 31 : NAND_IO[0] ->
/* Port 4 */
CFG_DISABLED | PULL_UP | DRIVE_S4 | SLOW_SLEW, // 32 : NAND_WEN ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW, // 33 : NAND_CLE ->
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | SLOW_SLEW, // 34 : NAND_ALE ->
CFG_DISABLED, // 35 : I2S0_LRCK ->
CFG_DISABLED, // 36 : I2S0_BCLK ->
CFG_DISABLED, // 37 : I2S0_DOUT ->
CFG_DISABLED, // 38 : I2S0_DIN ->
CFG_DISABLED, // 39 : I2S1_LRCK ->
/* Port 5 */
CFG_DISABLED, // 40 : I2S1_BCLK ->
CFG_DISABLED, // 41 : I2S1_DOUT ->
CFG_DISABLED, // 42 : I2S1_DIN ->
CFG_DISABLED, // 43 : I2S2_LRCK ->
CFG_DISABLED, // 44 : I2S2_BCLK ->
CFG_DISABLED, // 45 : I2S2_DOUT ->
CFG_DISABLED, // 46 : I2S2_DIN ->
CFG_DISABLED, // 47 : SD_CLKOUT ->
/* Port 6 */
CFG_DISABLED, // 48 : sDIO_IRQ ->
CFG_DISABLED, // 49 : SD_DATA_IO[0] ->
CFG_DISABLED, // 50 : SD_DATA_IO[1] ->
CFG_DISABLED, // 51 : SD_DATA_IO[2] ->
CFG_DISABLED, // 52 : SD_DATA_IO[3] ->
CFG_DISABLED, // 53 : SDIO_IRQ ->
CFG_DISABLED, // 54 : WL_HOST_WAKE ->
CFG_DISABLED, // 55 : ENET_MDC ->
/* Port 7 */
CFG_DISABLED, // 56 : ENET_MDIO ->
CFG_DISABLED, // 57 : RMII_RXER ->
CFG_DISABLED, // 58 : RMII_TXEN ->
CFG_DISABLED, // 59 : RMII_CLK ->
CFG_DISABLED, // 60 : RMII_TXD[0] ->
CFG_DISABLED, // 61 : RMII_TXD[1] ->
CFG_DISABLED, // 62 : RMII_RXD[0] ->
CFG_DISABLED, // 63 : RMII_RXD[1] ->
/* Port 8 */
CFG_DISABLED, // 64 : RMII_CRSDV ->
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 65 : SPI0_SCLK -> SPI0_SCLK/Board_ID[0]
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 66 : SPI0_MOSI -> SPI0_MOSI/Board_ID[1]
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 67 : SPI0_MISO -> SPI0_MISO/Board_ID[2]
CFG_DISABLED | DRIVE_S4 | VERY_FAST_SLEW, // 68 : SPI0_SSIN -> SPI0_CS
CFG_DISABLED, // 69 : SPI1_SCLK ->
CFG_DISABLED, // 70 : SPI1_MOSI ->
CFG_DISABLED, // 71 : SPI1_MISO ->
/* Port 9 */
CFG_DISABLED, // 72 : SPI1_SSIN ->
CFG_DISABLED, // 73 : I2C0_SDA ->
CFG_DISABLED, // 74 : I2C0_SCL ->
CFG_DISABLED, // 75 : I2C1_SDA ->
CFG_DISABLED, // 76 : I2C1_SCL ->
CFG_DISABLED, // 77 : I2C2_0_SDA ->
CFG_DISABLED, // 78 : I2C2_0_SCL ->
CFG_DISABLED, // 79 : I2C2_1_SDA ->
/* Port 10 */
CFG_DISABLED, // 80 : I2C2_1_SCL ->
CFG_DISABLED, // 81 : UART0_TXD ->
CFG_DISABLED, // 82 : UART0_RXD ->
CFG_DISABLED, // 83 : UART3_RTXD ->
CFG_DISABLED, // 84 : UART4_TXD ->
CFG_DISABLED, // 85 : UART4_RXD ->
CFG_DISABLED, // 86 : UART5_TXD ->
CFG_DISABLED, // 87 : UART5_RXD ->
/* Port 11 */
CFG_DISABLED, // 88 : UART2_TXD ->
CFG_DISABLED, // 89 : UART2_RXD ->
CFG_DISABLED, // 90 : UART2_RTSN ->
CFG_DISABLED, // 91 : UART2_CTSN ->
CFG_DISABLED, // 92 : UART1_TXD ->
CFG_DISABLED, // 93 : UART1_RXD ->
CFG_DISABLED, // 94 : UART1_RTSN ->
CFG_DISABLED, // 95 : UART1_CTSN ->
/* Port 12 */
CFG_DISABLED, // 96 : ISP0_SDA ->
CFG_DISABLED, // 97 : ISP0_SCL ->
CFG_DISABLED, // 98 : DISP_TE ->
CFG_DISABLED, // 99 : DISP_VSYNC ->
CFG_IN | DRIVE_S4 | VERY_FAST_SLEW | INPUT_SCHMITT, // 100 : REQUEST_DFU1 -> REQUEST_DFU1
CFG_IN | DRIVE_S4 | VERY_FAST_SLEW | INPUT_SCHMITT, // 101 : REQUEST_DFU2 -> REQUEST_DFU2
CFG_IN | PULL_DOWN | DRIVE_S4 | VERY_FAST_SLEW | INPUT_SCHMITT, // 102 : FORCE_DFU -> FORCE_DFU
CFG_DISABLED, // 103 : SWD_TMS2 ->
/* Port 13 */
CFG_DISABLED, // 104 : SWD_TMS3 ->
CFG_DISABLED, // 105 : CLK32K_OUT ->
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 14 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 15 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 16 */
CFG_DISABLED, // 128 : MON[0] ->
CFG_DISABLED, // 129 : MON[1] ->
CFG_DISABLED, // 130 : MON[2] ->
CFG_DISABLED, // 131 : MON[3] ->
CFG_DISABLED, // 132 : MON[4] ->
CFG_DISABLED, // 133 : MON[5] ->
CFG_DISABLED, // 134 : MON[6] ->
CFG_DISABLED, // 135 : MON[7] ->
/* Port 17 */
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | VERY_FAST_SLEW, // 136 : DFU_STATUS -> DFU_STATUS
CFG_DISABLED, // 137 : DROOP_N ->
CFG_DISABLED, // 138 : TST_CLKOUT ->
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED, // 0 : AOP_I2S1_MCK ->
CFG_DISABLED, // 1 : AOP_I2S0_MCK ->
CFG_DISABLED, // 2 : AOP_PDM_CLK ->
CFG_DISABLED, // 3 : AOP_PDM_DAT ->
CFG_DISABLED, // 4 : AOP_PLED[0] ->
CFG_DISABLED, // 5 : AOP_PLED[1] ->
CFG_FUNC0 | PULL_DOWN | DRIVE_S4 | VERY_FAST_SLEW | INPUT_SCHMITT, // 6 : AOP_DOCK_CONNECT -> DOCK_CONNECT
CFG_DISABLED | PULL_DOWN | DRIVE_S4 | VERY_FAST_SLEW, // 7 : AOP_DOCK_ATTENTION ->
/* Port 1 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 2 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 3 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 4 */
CFG_DISABLED, // 32 : AOP_PLED[2] ->
CFG_DISABLED, // 33 : AOP_PLED[3] ->
CFG_DISABLED, // 34 : AOP_PLED[4] ->
CFG_DISABLED, // 35 : AOP_PLED[5] ->
CFG_DISABLED, // 36 : AOP_PLED[6] ->
CFG_DISABLED, // 37 : AOP_PLED[7] ->
CFG_DISABLED, // 38 : AOP_MON[0] ->
CFG_DISABLED, // 39 : AOP_MON[1] ->
/* Port 5 */
CFG_DISABLED, // 40 : AOP_MON[2] ->
CFG_DISABLED, // 41 : AOP_MON[3] ->
CFG_DISABLED, // 42 : AOP_MON[4] ->
CFG_DISABLED, // 43 : AOP_MON[5] ->
CFG_DISABLED, // 44 : AOP_MON[6] ->
CFG_DISABLED, // 45 : AOP_MON[7] ->
CFG_DISABLED, // 46 : AOP_SWD_TCK_OUT ->
CFG_DISABLED, // 47 : AOP_SWD_TMS0 ->
/* Port 6 */
CFG_DISABLED, // 48 : AOP_SWD_TMS1 ->
CFG_DISABLED, // 49 : AOP_UART0_TXD ->
CFG_DISABLED, // 50 : AOP_UART0_RXD ->
CFG_DISABLED, // 51 : AOP_UART0_RTSN ->
CFG_DISABLED, // 52 : AOP_UART0_CTSN ->
CFG_DISABLED, // 53 : AOP_UART1_TXD ->
CFG_DISABLED, // 54 : AOP_UART1_RXD ->
CFG_DISABLED, // 55 : AOP_UART1_RTSN ->
/* Port 7 */
CFG_DISABLED, // 56 : AOP_UART1_CTSN ->
CFG_DISABLED, // 57 : AOP_UART2_TXD ->
CFG_DISABLED, // 58 : AOP_UART2_RXD ->
CFG_DISABLED, // 59 : AOP_SPI_CS_TRIG[0] ->
CFG_DISABLED, // 60 : AOP_SPI_CS_TRIG[1] ->
CFG_DISABLED, // 61 : AOP_SPI_CS_TRIG[2] ->
CFG_DISABLED, // 62 : AOP_SPI_CS_TRIG[3] ->
CFG_DISABLED, // 63 : AOP_SPI_CS_TRIG[4] ->
/* Port 8 */
CFG_DISABLED, // 64 : AOP_SPI_CS_TRIG[5] ->
CFG_DISABLED, // 65 : AOP_SPI_CS_TRIG[6] ->
CFG_DISABLED, // 66 : AOP_SPI_CS_TRIG[7] ->
CFG_DISABLED, // 67 : AOP_SPI_CS_TRIG[8] ->
CFG_DISABLED, // 68 : AOP_SPI_CS_TRIG[9] ->
CFG_DISABLED, // 69 : AOP_SPI_CS_TRIG[10] ->
CFG_DISABLED, // 70 : AOP_SPI_CS_TRIG[11] ->
CFG_DISABLED, // 71 : AOP_SPI_CS_TRIG[12] ->
/* Port 9 */
CFG_DISABLED, // 72 : AOP_SPI_CS_TRIG[13] ->
CFG_DISABLED, // 73 : AOP_SPI_CS_TRIG[14] ->
CFG_DISABLED, // 74 : AOP_SPI_CS_TRIG[15] ->
CFG_DISABLED, // 75 : AOP_I2C0_SDA ->
CFG_DISABLED, // 76 : AOP_I2C0_SCL ->
CFG_DISABLED, // 77 : AOP_I2C1_SDA ->
CFG_DISABLED, // 78 : AOP_I2C1_SCL ->
CFG_DISABLED, // 79 : AOP_SPI0_SCLK ->
/* Port 10 */
CFG_DISABLED, // 80 : AOP_SPI0_MOSI ->
CFG_DISABLED, // 81 : AOP_SPI0_MISO ->
CFG_DISABLED, // 82 : AOP_PSPI_CS_TRIG[3] ->
CFG_DISABLED, // 83 : AOP_PSPI_CS_TRIG[4] ->
CFG_DISABLED, // 84 : AOP_PSPI_SCLK ->
CFG_DISABLED, // 85 : AOP_PSPI_MOSI ->
CFG_DISABLED, // 86 : AOP_PSPI_MISO ->
CFG_DISABLED, // 87 : AOP_LSPI_SCLK ->
/* Port 11 */
CFG_DISABLED, // 88 : AOP_LSPI_MOSI ->
CFG_DISABLED, // 89 : AOP_LSPI_MISO ->
CFG_DISABLED, // 90 : AOP_DETECT[0] ->
CFG_DISABLED, // 91 : AOP_DETECT[1] ->
CFG_DISABLED, // 92 : AOP_PSENSE_CTRL[4] ->
CFG_DISABLED, // 93 : AOP_PSENSE_CTRL[5] ->
CFG_DISABLED, // 94 : AOP_PSENSE_CTRL[6] ->
CFG_DISABLED, // 95 : AOP_PSENSE_CTRL[7] ->
};
struct pinconfig_map {
uint32_t board_id;
uint32_t board_id_mask;
const uint32_t *pinconfigs[GPIOC_COUNT];
};
static const struct pinconfig_map cfg_map[] = {
{ 0, 0, { pinconfig_0, pinconfig_1 } },
};
const uint32_t * target_get_default_gpio_cfg(uint32_t gpioc)
{
static const struct pinconfig_map *selected_map = NULL;
if (selected_map == NULL) {
uint32_t board_id = platform_get_board_id();
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
selected_map = &cfg_map[i];
break;
}
}
if (selected_map == NULL)
panic("no default pinconfig for board id %u", board_id);
}
ASSERT(gpioc < GPIOC_COUNT);
return selected_map->pinconfigs[gpioc];
}
target/watch2/rules.mk
+77
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# Copyright (C) 2013 Apple Inc. All rights reserved.
#
# This document is the property of Apple Inc.
# It is considered confidential and proprietary.
#
# This document may not be reproduced or transmitted in any form,
# in whole or in part, without the express written permission of
# Apple Inc.
#
LOCAL_DIR := $(GET_LOCAL_DIR)
TARGET_DIR := $(LOCAL_DIR)
OPTIONS += \
DIALOG_D2238=1 \
TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_MED \
TARGET_BOOT_RAM_VOLTAGE=0 \
TARGET_BOOT_SOC_VOLTAGE=0 \
TARGET_PMU_DEV_ID=0x78 \
DCS_NUM_CHANNELS=1 \
DCS_NUM_RANKS=1 \
TARGET_DSIM_DPHYCTL=0x00003000 \
TARGET_DSIM_CONFIG=0x00400000 \
TARGET_DSIM_UP_CODE=0x1 \
TARGET_DSIM_DOWN_CODE=0x1 \
TARGET_DSIM_SUPPRESS=0x1 \
WITH_TARGET_CHARGETRAP=1 \
WITH_DALI=1 \
WIFI_DTPATH=\"arm-io/sdio\" \
BT_DTPATH=\"arm-io/uart1/bluetooth\" \
MULTITOUCH_DTPATH=\"arm-io/multi-touch\"
ifeq ($(CONFIG_SIM),true)
OPTIONS += \
CONFIG_SIM=1 \
AMP_CALIBRATION_SKIP=1
endif
ifeq ($(CONFIG_FPGA),true)
OPTIONS += \
CONFIG_FPGA=1 \
DISPLAY_FPGA_TUNABLES=1 \
SUPPORT_FPGA=1 \
AMP_CALIBRATION_SKIP=1 \
DCS_FIXUP_PARAMS=1 \
DCS_RUN_AT_50MHZ=1
endif
ifeq ($(NO_WFI),true)
OPTIONS += \
NO_ARM_HALT=1
endif
ifeq ($(RECOVERY_MODE_IBSS),true)
OPTIONS += \
WITH_RECOVERY_MODE_IBSS=1
endif
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
ALL_OBJS += $(LOCAL_DIR)/init.o \
$(LOCAL_DIR)/target_prepare_dali.o
ifeq ($(CONFIG_SIM),true)
ALL_OBJS += $(LOCAL_DIR)/init_sim.o \
$(LOCAL_DIR)/pinconfig_sim.o
else
ifeq ($(CONFIG_FPGA),true)
ALL_OBJS += $(LOCAL_DIR)/init_fpga.o \
$(LOCAL_DIR)/pinconfig_fpga.o
else
ALL_OBJS += $(LOCAL_DIR)/init_product.o \
$(LOCAL_DIR)/pinconfig_product.o \
$(LOCAL_DIR)/pinconfig_proto2a.o \
$(LOCAL_DIR)/pinconfig_proto2b.o \
$(LOCAL_DIR)/pinconfig_evt.o
endif
endif
target/watch2/target_prepare_dali.c
+81
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/*
* Copyright (C) 2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <target.h>
#include <platform/memmap.h>
#include <platform/gpiodef.h>
#include <target/gpiodef.h>
#include <drivers/power.h>
#include <stdlib.h>
#include <lib/env.h>
#include <lib/syscfg.h>
#include <platform/dmin.h>
enum {
kRTKitArgBlockVersion1 = 'RTK1',
kDaliFWArgVersion1 = 'DAL1',
kDaliFWArgVersion2 = 'DAL2'
};
enum
{
kMode24hEnabledOffset = 0,
kRotateScreenOffset = 1,
kDaliDarkWakeOffset = 2, /* 0 = normal wake, 1 = scheduled thermal wake, don't paint screen */
kPmuDebugOffset = 3
};
typedef struct dali_payload_t {
uint32_t magic; /* = kDaliFWArgVersion2 */
uint32_t reserved;
uint8_t charFlags[8];
int64_t utcOffset;
DMin_t dmin;
} dali_payload_t;
typedef struct dali_args_t {
uint32_t magic; /* = kRTKitArgBlockVersion1 */
uint32_t size; /* size of pending payload */
dali_payload_t payload;
} dali_args_t;
void*
target_prepare_dali(void)
{
#if defined(PMU_LDO_OPAL) && WITH_HW_POWER
// <rdar://problem/17768885> Interim Solution: Turn off LDO8 in Dali mode/iBoot
// Opal uses a lot of power when held in reset. For sure we don't need it in Dali.
power_enable_ldo(PMU_LDO_OPAL, false);
#endif
#ifdef GPIO_SPU_TO_OPAL_CS_L
gpio_configure(GPIO_SPU_TO_OPAL_CS_L, GPIO_CFG_IN);
#endif
dali_args_t* args = (dali_args_t *)PANIC_BASE;
bzero(args, sizeof(dali_args_t));
args->magic = kRTKitArgBlockVersion1;
args->size = sizeof(dali_payload_t);
args->payload.magic = kDaliFWArgVersion2;
args->payload.charFlags[kMode24hEnabledOffset] = (env_get_uint("dali-24h-mode", 0) == 1);
args->payload.charFlags[kRotateScreenOffset] = (env_get_uint("display-rotation", 0) == 1);
args->payload.charFlags[kPmuDebugOffset] = (env_get_uint("dali-pmu-debug", 0) == 1);
syscfgCopyDataForTag('DMin', (uint8_t*)&(args->payload.dmin), sizeof(DMin_t));
const char* utcOffsetStr = env_get("utc-offset");
if (utcOffsetStr) {
args->payload.utcOffset = atoi(utcOffsetStr);
}
return args;
}