/* * Copyright (C) 2010-2014 Apple Inc. All rights reserved. * * This document is the property of Apple Inc. * It is considered confidential and proprietary. * * This document may not be reproduced or transmitted in any form, * in whole or in part, without the express written permission of * Apple Inc. */ #define DPCD_ADDR_DPCD_REV 0x00000 #define DPCD_ADDR_DPCD_REV_MAJOR_SHIFT 4 #define DPCD_ADDR_DPCD_REV_MAJOR_MASK (0xf << DPCD_ADDR_DPCD_REV_MAJOR_SHIFT) #define DPCD_ADDR_DPCD_REV_MINOR_SHIFT 0 #define DPCD_ADDR_DPCD_REV_MINOR_MASK (0xf << DPCD_ADDR_DPCD_REV_MINOR_SHIFT) #define DPCD_ADDR_MAX_LINK_RATE 0x00001 #define DPCD_ADDR_MAX_LANE_COUNT 0x00002 #define DPCD_ADDR_MAX_DOWNSPREAD 0x00003 #define DPCD_ADDR_NORP 0x00004 #define DPCD_ADDR_DOWNSTREAMPORT_PRESENT 0x00005 #define DPCD_ADDR_RECEIVE_PORT0_CAP_0 0x00008 #define DPCD_ADDR_RECEIVE_PORT0_CAP_0_EDID (1 << 1) #define DPCD_ADDR_DOWNSTREAMPORT_COUNT 0x00007 #define DPCD_ADDR_RECEIVE_PORT0_CAP_1 0x00009 #define DPCD_ADDR_RECEIVE_PORT0_CAP_2 0x0000a #define DPCD_ADDR_RECEIVE_PORT0_CAP_3 0x0000b #define DPCD_ADDR_ALTERNATE_SCRAMBLE 0x0000d #define DPCD_ADDR_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) #define DPCD_ADDR_FRAMING_CHANGE_CAP (1 << 1) #define DPCD_ADDR_INVERTED_TRAINING_BIT_CAP (1 << 2) #define DPCD_ADDR_DOWNSTREAMPORT_0_CAPS 0x00080 #define DPCD_ADDR_ALPM_CAP 0x0002e #define DPCD_ADDR_LINK_BW_SET 0x00100 #define DPCD_ADDR_LANE_COUNT_SET 0x00101 #define DPCD_ADDR_LANE_COUNT_SET_ENHANCED (1 << 7) #define DPCD_ADDR_LANE_COUNT_SET_COUNT_MASK (0x1f) #define DPCD_ADDR_LANE_COUNT_TPS3_SUPPORTED (1 << 6) #define DPCD_ADDR_TRAINING_PATTERN_SET 0x00102 #define DPCD_ADDR_PATTERN_SET_MASK 0x3 #define DPCD_ADDR_QUALITY_PATTERN_SHIFT 2 #define DPCD_ADDR_TRAINING_PATTERN_SET_SCRMB_DISABLE (1 << 5) #define DPCD_ADDR_TRAINNIG_LANE0_SET 0x00103 #define DPCD_ADDR_TRAINNIG_LANE1_SET 0x00104 #define DPCD_ADDR_TRAINNIG_LANE2_SET 0x00105 #define DPCD_ADDR_TRAINNIG_LANE3_SET 0x00106 #define DPCD_ADDR_TRAINNIG_SET_VOL_SWING_SHIFT 0 #define DPCD_ADDR_TRAINNIG_SET_VOL_SWING_MASK (0x3 << DPCD_ADDR_TRAINNIG_SET_VOL_SWING_SHIFT) #define DPCD_ADDR_TRAINNIG_SET_VOL_SWING_MAX (0x1 << 2) #define DPCD_ADDR_TRAINNIG_SET_PRE_EMPH_SHIFT 3 #define DPCD_ADDR_TRAINNIG_SET_PRE_EMPH_MASK (0x3 << DPCD_ADDR_TRAINNIG_SET_PRE_EMPH_SHIFT) #define DPCD_ADDR_TRAINNIG_SET_PRE_EMPH_MAX (0x1 << 5) #define DPCD_ADDR_DOWNSPREAD_CTRL 0x00107 #define DPCD_ADDR_DOWNSPREAD_ENABLE (1 << 4) // eDP (DPCD 1.2) #define DPCD_ADDR_RECEIVER_EDP_CONFIG 0x0010a #define DPCD_ADDR_RECEIVER_EDP_CONFIG_ASSR_ENABLE (1<<0) #define DPCD_ADDR_ALPM_CTRL 0x00116 #define DPCD_ADDR_ALPM_ENABLE (1 << 0) #define DPCD_ADDR_ALPM_ALPM_LOCK_ERROR_IRQ_HPD (1 << 1) #define DPCD_ADDR_SINK_COUNT 0x00200 #define DPCD_ADDR_DEVICE_SERVICE_IRQ_VECTOR 0x00201 #define DPCD_IRQ_VECTOR_REMOTE_COMMAND (1 << 0) #define DPCD_IRQ_VECTOR_AUTOMATED_TEST (1 << 1) #define DPCD_IRQ_VECTOR_CP_IRQ (1 << 2) #define DPCD_IRQ_VECTOR_SINK_SPECIFIC (1 << 6) #define DPCD_ADDR_LANE0_1_STATUS 0x00202 #define DPCD_ADDR_LANE2_3_STATUS 0x00203 #define DPCD_ADDR_LANEX_Y_STATUS_X_SHIFT (0) #define DPCD_ADDR_LANEX_Y_STATUS_Y_SHIFT (4) #define DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED 0x00204 #define DPCD_ADDR_SINK_STATUS 0x00205 #define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x00206 #define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x00207 #define DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_VOL_SWG_X_SHIFT 0 #define DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_VOL_SWG_X_MASK (0x3 << DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_VOL_SWG_X_SHIFT) #define DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_PRE_EMP_X_SHIFT 2 #define DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_PRE_EMP_X_MASK (0x3 << DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_PRE_EMP_X_SHIFT) #define DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_VOL_SWG_Y_SHIFT 4 #define DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_VOL_SWG_Y_MASK (0x3 << DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_VOL_SWG_Y_SHIFT) #define DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_PRE_EMP_Y_SHIFT 6 #define DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_PRE_EMP_Y_MASK (0x3 << DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_PRE_EMP_Y_SHIFT) #define DPCD_ADDR_TRAINING_SCORE_LANE0 0x00208 #define DPCD_ADDR_TRAINING_SCORE_LANE1 0x00209 #define DPCD_ADDR_TRAINING_SCORE_LANE2 0x0020a #define DPCD_ADDR_TRAINING_SCORE_LANE3 0x0020b #define DPCD_ADDR_SYMBOL_ERROR_COUNT_LANE0_BYTE0 0x00210 #define DPCD_ADDR_SYMBOL_ERROR_COUNT_LANE0_BYTE1 0x00211 #define DPCD_ADDR_SYMBOL_ERROR_COUNT_LANE1_BYTE0 0x00212 #define DPCD_ADDR_SYMBOL_ERROR_COUNT_LANE1_BYTE1 0x00213 #define DPCD_ADDR_SYMBOL_ERROR_COUNT_LANE2_BYTE0 0x00214 #define DPCD_ADDR_SYMBOL_ERROR_COUNT_LANE2_BYTE1 0x00215 #define DPCD_ADDR_SYMBOL_ERROR_COUNT_LANE3_BYTE0 0x00216 #define DPCD_ADDR_SYMBOL_ERROR_COUNT_LANE3_BYTE1 0x00217 #define DPCD_ADDR_TEST_REQUEST 0x00218 #define DPCD_ADDR_TEST_REQUEST_LINK (1 << 0) #define DPCD_ADDR_TEST_REQUEST_PATTERN (1 << 1) #define DPCD_ADDR_TEST_REQUEST_EDID (1 << 2) #define DPCD_ADDR_TEST_REQUEST_PHY (1 << 3) #define DPCD_ADDR_TEST_LINK_RATE 0x00219 #define DPCD_ADDR_TEST_LANE_COUNT 0x00220 #define DPCD_ADDR_TEST_PATTERN 0x00221 #define DPCD_ADDR_TEST_H_TOTAL_H 0x00222 #define DPCD_ADDR_TEST_H_TOTAL_L 0x00223 #define DPCD_ADDR_TEST_V_TOTAL_H 0x00224 #define DPCD_ADDR_TEST_V_TOTAL_L 0x00225 #define DPCD_ADDR_TEST_H_START_H 0x00226 #define DPCD_ADDR_TEST_H_START_L 0x00227 #define DPCD_ADDR_TEST_V_START_H 0x00228 #define DPCD_ADDR_TEST_V_START_L 0x00229 #define DPCD_ADDR_TEST_HSYNC_H 0x0022a #define DPCD_ADDR_TEST_HSYNC_L 0x0022b #define DPCD_ADDR_TEST_VSYNC_H 0x0022c #define DPCD_ADDR_TEST_VSYNC_L 0x0022d #define DPCD_ADDR_TEST_H_WIDTH_H 0x0022e #define DPCD_ADDR_TEST_H_WIDTH_L 0x0022f #define DPCD_ADDR_TEST_V_HEGHT_H 0x00230 #define DPCD_ADDR_TEST_V_HEGHT_L 0x00231 #define DPCD_ADDR_TEST_PHY 0x00248 #define DPCD_ADDR_TEST_PHY_SEL_MASK 3 #define DPCD_ADDR_TEST_RESPONSE 0x00260 #define DPCD_ADDR_TEST_RESPONSE_ACK (1 << 0) #define DPCD_ADDR_TEST_RESPONSE_NACK (1 << 1) #define DPCD_ADDR_TEST_RESPONSE_EDID (1 << 2) #define DPCD_ADDR_TEST_EDID_CHECKSUM 0x00261 #define DPCD_ADDR_SOURCE_IEEE_OUI_7_0 0x00300 #define DPCD_ADDR_SOURCE_IEEE_OUI_15_8 0x00301 #define DPCD_ADDR_SOURCE_IEEE_OUI_23_16 0x00302 #define DPCD_ADDR_SOURCE_DEVICE_ID_BYTE_0 0x00303 #define DPCD_ADDR_SINK_IEEE_OUI_7_0 0x00400 #define DPCD_ADDR_SINK_IEEE_OUI_15_8 0x00401 #define DPCD_ADDR_SINK_IEEE_OUI_23_16 0x00402 #define DPCD_ADDR_SINK_DEVICE_ID_BYTE_0 0x00403 #define DPCP_ADDR_VENDOR_BYTES 0x00430 #define DPCD_ADDR_BRANCH_IEEE_OUI_7_0 0x00500 #define DPCD_ADDR_BRANCH_IEEE_OUI_15_8 0x00501 #define DPCD_ADDR_BRANCH_IEEE_OUI_23_16 0x00502 #define DPCD_ADDR_BRANCH_DEVICE_ID_BYTE_0 0x00503 #define DPCD_ADDR_HDMI_DVI_MODE_SELECT 0x00519 #define DPCD_HDMI_DVI_SELECT_DEFAULT 0x00 #define DPCD_ADDR_HDMI_DVI_MODE_SELECT_DVI 0x01 #define DPCD_HDCP_ENABLE 0x00 #define DPCD_HDCP_DISABLE 0x02 #define DPCD_ADDR_SINK_POWER_STATE 0x00600 #define DPCD_ADDR_SINK_POWER_STATE_ON 0x1 #define DPCD_ADDR_SINK_POWER_STATE_OFF 0x2 #define DPCD_ADDR_HDCP_BKSV_0 0x68000 #define DPCD_ADDR_HDCP_BKSV_1 0x68001 #define DPCD_ADDR_HDCP_BKSV_2 0x68002 #define DPCD_ADDR_HDCP_BKSV_3 0x68003 #define DPCD_ADDR_HDCP_BKSV_4 0x68004 #define DPCD_ADDR_HDCP_R0_0 0x68005 #define DPCD_ADDR_HDCP_R0_1 0x68006 #define DPCD_ADDR_HDCP_AKSV_0 0x68007 #define DPCD_ADDR_HDCP_AKSV_1 0x68008 #define DPCD_ADDR_HDCP_AKSV_2 0x68009 #define DPCD_ADDR_HDCP_AKSV_3 0x6800a #define DPCD_ADDR_HDCP_AKSV_4 0x6800b #define DPCD_ADDR_HDCP_AN_0 0x6800c #define DPCD_ADDR_HDCP_AN_1 0x6800d #define DPCD_ADDR_HDCP_AN_2 0x6800e #define DPCD_ADDR_HDCP_AN_3 0x6800f #define DPCD_ADDR_HDCP_AN_4 0x68010 #define DPCD_ADDR_HDCP_AN_5 0x68011 #define DPCD_ADDR_HDCP_AN_6 0x68012 #define DPCD_ADDR_HDCP_AN_7 0x68013 #define DPCD_ADDR_HDCP_H0_0 0x68014 #define DPCD_ADDR_HDCP_H0_1 0x68015 #define DPCD_ADDR_HDCP_H0_2 0x68016 #define DPCD_ADDR_HDCP_H0_3 0x68017 #define DPCD_ADDR_HDCP_H1_0 0x68018 #define DPCD_ADDR_HDCP_H1_1 0x68019 #define DPCD_ADDR_HDCP_H1_2 0x6801a #define DPCD_ADDR_HDCP_H1_3 0x6801b #define DPCD_ADDR_HDCP_H2_0 0x6801c #define DPCD_ADDR_HDCP_H2_1 0x6801d #define DPCD_ADDR_HDCP_H2_2 0x6801e #define DPCD_ADDR_HDCP_H2_3 0x6801f #define DPCD_ADDR_HDCP_H3_0 0x68020 #define DPCD_ADDR_HDCP_H3_1 0x68021 #define DPCD_ADDR_HDCP_H3_2 0x68022 #define DPCD_ADDR_HDCP_H3_3 0x68023 #define DPCD_ADDR_HDCP_H4_0 0x68024 #define DPCD_ADDR_HDCP_H4_1 0x68025 #define DPCD_ADDR_HDCP_H4_2 0x68026 #define DPCD_ADDR_HDCP_H4_3 0x68027 #define DPCD_ADDR_HDCP_BCAPS 0x68028 #define DPCD_ADDR_HDCP_BCAPS_HDCP_CAPABLE (1 << 0) #define DPCD_ADDR_HDCP_BCAPS_IS_REPEATER (1 << 1) #define DPCD_ADDR_HDCP_STATUS 0x68029 #define DPCD_ADDR_HDCP_STATUS_LINK_INTEGRITY_FAILURE (1 << 2) #define DPCD_ADDR_HDCP_STATUS_R0PRIME_AVAILABLE (1 << 1) #define DPCD_ADDR_HDCP_STATUS_READY (1 << 0) #define DPCD_ADDR_HDCP_BINFO_0 0x6802a #define DPCD_ADDR_HDCP_BINFO_1 0x6802b #define DPCD_ADDR_HDCP_INFO_MAX_CASCADE_EXCEEDED (1 << 11) #define DPCD_ADDR_HDCP_INFO_MAX_DEVS_EXCEEDED (1 << 7) #define DPCD_ADDR_HDCP_KSV_FIFO_0 0x6802c #define DPCD_ADDR_HDCP_KSV_FIFO_1 0x6802d #define DPCD_ADDR_HDCP_KSV_FIFO_2 0x6802e #define DPCD_ADDR_HDCP_KSV_FIFO_3 0x6802f #define DPCD_ADDR_HDCP_KSV_FIFO_4 0x68030 #define DPCD_ADDR_HDCP_KSV_FIFO_5 0x68031 #define DPCD_ADDR_HDCP_KSV_FIFO_6 0x68032 #define DPCD_ADDR_HDCP_KSV_FIFO_7 0x68033 #define DPCD_ADDR_HDCP_KSV_FIFO_8 0x68034 #define DPCD_ADDR_HDCP_KSV_FIFO_9 0x68035 #define DPCD_ADDR_HDCP_KSV_FIFO_10 0x68036 #define DPCD_ADDR_HDCP_KSV_FIFO_11 0x68037 #define DPCD_ADDR_HDCP_KSV_FIFO_12 0x68038 #define DPCD_ADDR_HDCP_KSV_FIFO_13 0x68039 #define DPCD_ADDR_HDCP_KSV_FIFO_14 0x6803a #define DPCD_ADDR_HDCP_RSVD 0x6803b