628 lines
10 KiB
ArmAsm
628 lines
10 KiB
ArmAsm
/*
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* Copyright (C) 2007-2011 Apple Inc. All rights reserved.
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* Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <arch/arm/assembler.h>
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.text
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#define ALL_ROUTINES 1
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// Define isb as a nop for older architectures
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#if !ARCH_ARMv7
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#define isb nop
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#define dsb nop
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#endif /* ! ARCH_ARMv7 */
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ARM_FUNCTION _arm_read_cpsr
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mrs r0, cpsr
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bx lr
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#if ALL_ROUTINES
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ARM_FUNCTION _arm_read_main_id
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mrc p15, 0, r0, c0, c0, 0
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bx lr
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#endif
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#if ALL_ROUTINES
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ARM_FUNCTION _arm_read_cache_id
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mrc p15, 0, r0, c0, c0, 1
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bx lr
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ARM_FUNCTION _arm_read_cache_level_id
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mrc p15, 1, r0, c0, c0, 1
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bx lr
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ARM_FUNCTION _arm_read_cache_size_selection
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mrc p15, 2, r0, c0, c0, 0
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bx lr
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ARM_FUNCTION _arm_write_cache_size_selection
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mcr p15, 2, r0, c0, c0, 0
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isb
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bx lr
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ARM_FUNCTION _arm_read_cache_size_id
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mrc p15, 1, r0, c0, c0, 0
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bx lr
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#endif
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#if ALL_ROUTINES
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ARM_FUNCTION _arm_read_extended_feature_regs
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mov r12, r0
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mrc p15, 0, r0, c0, c1, 0
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mrc p15, 0, r1, c0, c1, 1
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mrc p15, 0, r2, c0, c1, 2
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mrc p15, 0, r3, c0, c1, 3
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stmia r12!, { r0-r3 }
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mrc p15, 0, r0, c0, c1, 4
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mrc p15, 0, r1, c0, c1, 5
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mrc p15, 0, r2, c0, c1, 6
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mrc p15, 0, r3, c0, c1, 7
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stmia r12!, { r0-r3 }
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mrc p15, 0, r0, c0, c2, 0
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mrc p15, 0, r1, c0, c2, 1
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mrc p15, 0, r2, c0, c2, 2
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mrc p15, 0, r3, c0, c2, 3
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stmia r12!, { r0-r3 }
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mrc p15, 0, r0, c0, c2, 4
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mrc p15, 0, r1, c0, c2, 5
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mrc p15, 0, r2, c0, c2, 6
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mrc p15, 0, r3, c0, c2, 7
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stmia r12, { r0-r3 }
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bx lr
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#endif
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#if ALL_ROUTINES
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ARM_FUNCTION _arm_read_memory_model_feature_regs
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mov r12, r0
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mrc p15, 0, r0, c0, c1, 4
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mrc p15, 0, r1, c0, c1, 5
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mrc p15, 0, r2, c0, c1, 6
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mrc p15, 0, r3, c0, c1, 7
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stmia r12, { r0-r3 }
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bx lr
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#endif
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#if ALL_ROUTINES
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ARM_FUNCTION _arm_read_instruction_set_attribute_regs
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mov r12, r0
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mrc p15, 0, r0, c0, c2, 0
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mrc p15, 0, r1, c0, c2, 1
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mrc p15, 0, r2, c0, c2, 2
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mrc p15, 0, r3, c0, c2, 3
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stmia r12!, { r0-r3 }
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mrc p15, 0, r0, c0, c2, 4
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mrc p15, 0, r1, c0, c2, 5
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stmia r12!, { r0-r1 }
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bx lr
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#endif
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ARM_FUNCTION _arm_read_cr
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mrc p15, 0, r0, c1, c0, 0
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bx lr
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ARM_FUNCTION _arm_write_cr
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mcr p15, 0, r0, c1, c0, 0
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isb
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bx lr
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ARM_FUNCTION _arm_read_aux_cr
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mrc p15, 0, r0, c1, c0, 1
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bx lr
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ARM_FUNCTION _arm_write_aux_cr
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mcr p15, 0, r0, c1, c0, 1
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isb
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bx lr
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ARM_FUNCTION _arm_write_dar
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mcr p15, 0, r0, c3, c0, 0
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isb
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bx lr
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ARM_FUNCTION _arm_write_ttb
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mcr p15, 0, r0, c2, c0, 0
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isb
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bx lr
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ARM_FUNCTION _arm_write_ttbcr
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mcr p15, 0, r0, c2, c0, 2
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isb
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bx lr
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ARM_FUNCTION _arm_read_ifsr
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mrc p15, 0, r0, c5, c0, 1
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bx lr
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ARM_FUNCTION _arm_read_dfsr
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mrc p15, 0, r0, c5, c0, 0
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bx lr
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ARM_FUNCTION _arm_read_ifar
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#if ARCH_ARMv7
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mrc p15, 0, r0, c6, c0, 2
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bx lr
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#endif
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ARM_FUNCTION _arm_read_dfar
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mrc p15, 0, r0, c6, c0, 0
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bx lr
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ARM_FUNCTION _arm_read_cp_access_cr
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mrc p15, 0, r0, c1, c0, 2
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bx lr
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ARM_FUNCTION _arm_write_cp_access_cr
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mcr p15, 0, r0, c1, c0, 2
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isb
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bx lr
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#if WITH_VFP
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ARM_FUNCTION _arm_read_fpexc
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vmrs r0, fpexc
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bx lr
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ARM_FUNCTION _arm_write_fpexc
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vmsr fpexc, r0
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bx lr
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ARM_FUNCTION _arm_read_fpscr
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vmrs r0, fpscr
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bx lr
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ARM_FUNCTION _arm_write_fpscr
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vmsr fpscr, r0
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bx lr
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// Reset core registers to a known value. Kingfisher doesnt
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// do this on reset, and simulation traces will show 'x'
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// uninitialized values otherwise. Prefer deterministic
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ARM_FUNCTION _arm_init_fp_regs
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vmov.i64 q0, #0
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vmov q1, q0
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vmov q2, q0
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vmov q3, q0
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vmov q4, q0
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vmov q5, q0
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vmov q6, q0
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vmov q7, q0
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#if FP_REGISTER_COUNT > 16
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vmov q8, q0
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vmov q9, q0
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vmov q10, q0
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vmov q11, q0
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vmov q12, q0
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vmov q13, q0
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vmov q14, q0
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vmov q15, q0
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#endif
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bx lr
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#endif
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#if ARCH_ARMv7
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ARM_FUNCTION _arm_read_l2_aux_cr
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mrc p15, 1, r0, c9, c0, 2
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bx lr
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ARM_FUNCTION _arm_write_l2_aux_cr
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mcr p15, 1, r0, c9, c0, 2
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isb
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bx lr
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ARM_FUNCTION _arm_read_pmreg
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cmp r0, #0
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bne 1f
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mrc p15, 0, r0, c9, c12, 0
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b 2f
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1: cmp r0, #1
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bne 1f
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mrc p15, 0, r0, c9, c12, 1
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b 2f
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1: cmp r0, #2
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bne 1f
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mrc p15, 0, r0, c9, c12, 2
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b 2f
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1: cmp r0, #3
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bne 1f
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mrc p15, 0, r0, c9, c12, 3
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b 2f
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1: cmp r0, #4
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bne 1f
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mrc p15, 0, r0, c9, c12, 4
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b 2f
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1: cmp r0, #5
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bne 1f
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mrc p15, 0, r0, c9, c12, 5
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b 2f
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1: cmp r0, #6
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bne 1f
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mrc p15, 0, r0, c9, c13, 0
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b 2f
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1: cmp r0, #7
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bne 1f
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mrc p15, 0, r0, c9, c13, 1
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b 2f
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1: cmp r0, #8
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bne 2f
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mrc p15, 0, r0, c9, c13, 2
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b 2f
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1: cmp r0, #9
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bne 2f
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mcr p15, 0, r0, c9, c14, 0
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b 2f
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1: cmp r0, #10
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bne 2f
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mcr p15, 0, r0, c9, c14, 1
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b 2f
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1: cmp r0, #11
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bne 2f
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mcr p15, 0, r0, c9, c14, 2
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2: isb
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bx lr
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ARM_FUNCTION _arm_write_pmreg
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cmp r0, #0
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bne 1f
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mcr p15, 0, r1, c9, c12, 0
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b 2f
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1: cmp r0, #1
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bne 1f
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mcr p15, 0, r1, c9, c12, 1
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b 2f
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1: cmp r0, #2
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bne 1f
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mcr p15, 0, r1, c9, c12, 2
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b 2f
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1: cmp r0, #3
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bne 1f
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mcr p15, 0, r1, c9, c12, 3
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b 2f
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1: cmp r0, #4
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bne 1f
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mcr p15, 0, r1, c9, c12, 4
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b 2f
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1: cmp r0, #5
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bne 1f
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mcr p15, 0, r1, c9, c12, 5
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b 2f
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1: cmp r0, #6
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bne 1f
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mcr p15, 0, r1, c9, c13, 0
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b 2f
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1: cmp r0, #7
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bne 1f
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mcr p15, 0, r1, c9, c13, 1
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b 2f
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1: cmp r0, #8
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bne 2f
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mcr p15, 0, r1, c9, c13, 2
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b 2f
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1: cmp r0, #9
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bne 2f
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mcr p15, 0, r1, c9, c14, 0
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b 2f
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1: cmp r0, #10
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bne 2f
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mcr p15, 0, r1, c9, c14, 1
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b 2f
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1: cmp r0, #11
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bne 2f
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mcr p15, 0, r1, c9, c14, 2
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2: isb
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bx lr
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#endif /* ARCH_ARMv7 */
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#if ALL_ROUTINES
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ARM_FUNCTION _arm_read_user_rw_tid
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mrc p15, 0, r0, c13, c0, 2
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bx lr
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ARM_FUNCTION _arm_write_user_rw_tid
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mcr p15, 0, r0, c13, c0, 2
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isb
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bx lr
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ARM_FUNCTION _arm_read_user_ro_tid
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mrc p15, 0, r0, c13, c0, 3
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bx lr
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ARM_FUNCTION _arm_write_user_ro_tid
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mcr p15, 0, r0, c13, c0, 3
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isb
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bx lr
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ARM_FUNCTION _arm_read_sup_tid
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mrc p15, 0, r0, c13, c0, 4
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bx lr
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ARM_FUNCTION _arm_write_sup_tid
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mcr p15, 0, r0, c13, c0, 4
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isb
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bx lr
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#endif
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ARM_FUNCTION _arm_read_perip_port_remap
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mrc p15, 0, r0, c15, c2, 4
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bx lr
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ARM_FUNCTION _arm_write_perip_port_remap
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mcr p15, 0, r0, c15, c2, 4
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isb
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bx lr
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ARM_FUNCTION _arm_flush_tlbs
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0
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dsb
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isb
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bx lr
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#define EXT(x) _ ## x
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#if ALL_ROUTINES
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/* mpu routines */
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#define WRITE_DATA_PROT_REGION(func, n) \
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.global EXT(func); \
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EXT(func): \
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mcr p15, 0, r0, c6, c##n, 0; \
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isb
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bx lr
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WRITE_DATA_PROT_REGION(arm_write_dprot_region_0, 0)
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WRITE_DATA_PROT_REGION(arm_write_dprot_region_1, 1)
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WRITE_DATA_PROT_REGION(arm_write_dprot_region_2, 2)
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WRITE_DATA_PROT_REGION(arm_write_dprot_region_3, 3)
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WRITE_DATA_PROT_REGION(arm_write_dprot_region_4, 4)
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WRITE_DATA_PROT_REGION(arm_write_dprot_region_5, 5)
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WRITE_DATA_PROT_REGION(arm_write_dprot_region_6, 6)
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WRITE_DATA_PROT_REGION(arm_write_dprot_region_7, 7)
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WRITE_DATA_PROT_REGION(arm_write_dprot_region_8, 8)
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#define WRITE_INSTRUCTION_PROT_REGION(func, n) \
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.global EXT(func); \
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EXT(func): \
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mcr p15, 0, r0, c6, c##n, 1; \
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isb
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bx lr
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WRITE_INSTRUCTION_PROT_REGION(arm_write_iprot_region_0, 0)
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WRITE_INSTRUCTION_PROT_REGION(arm_write_iprot_region_1, 1)
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WRITE_INSTRUCTION_PROT_REGION(arm_write_iprot_region_2, 2)
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WRITE_INSTRUCTION_PROT_REGION(arm_write_iprot_region_3, 3)
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WRITE_INSTRUCTION_PROT_REGION(arm_write_iprot_region_4, 4)
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WRITE_INSTRUCTION_PROT_REGION(arm_write_iprot_region_5, 5)
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WRITE_INSTRUCTION_PROT_REGION(arm_write_iprot_region_6, 6)
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WRITE_INSTRUCTION_PROT_REGION(arm_write_iprot_region_7, 7)
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WRITE_INSTRUCTION_PROT_REGION(arm_write_iprot_region_8, 8)
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.global _arm_write_data_prot_register
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_arm_write_data_prot_register:
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mcr p15, 0, r0, c5, c0, 0
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isb
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bx lr
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.global _arm_write_ins_prot_register
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_arm_write_ins_prot_register:
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mcr p15, 0, r0, c5, c0, 1
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isb
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bx lr
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.global _arm_write_cacheable_registers
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_arm_write_cacheable_registers:
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mcr p15, 0, r0, c2, c0, 0
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mcr p15, 0, r1, c2, c0, 1
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isb
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bx lr
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.global _arm_write_bufferable_register
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_arm_write_bufferable_register:
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mcr p15, 0, r0, c3, c0, 0
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isb
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bx lr
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#endif
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/* uint arch_enable_ints(void); */
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ARM_FUNCTION _arch_enable_ints
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mrs r0, cpsr
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bic r1, r0, #(1<<7)
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#if WITH_FIQ_TIMER
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bic r1, r1, #(1<<6)
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#endif
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msr cpsr_c, r1
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and r0, r0, #(1<<7)
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bx lr
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/* uint arch_disable_ints(void); */
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ARM_FUNCTION _arch_disable_ints
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mrs r0, cpsr
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orr r1, r0, #(1<<7)
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#if WITH_FIQ_TIMER
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orr r1, r1, #(1<<6)
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#endif
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msr cpsr_c, r1
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and r0, r0, #(1<<7)
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bx lr
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/* uint arch_restore_ints(uint state); */
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ARM_FUNCTION _arch_restore_ints
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mrs r1, cpsr
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and r0, r0, #(1<<7)
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bic r1, r1, #(1<<7)
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orr r2, r1, r0
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msr cpsr_c, r2
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and r0, r1, #(1<<7)
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bx lr
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/* void arm_enable_fiqs(void); */
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ARM_FUNCTION _arm_enable_fiqs
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mrs r0, cpsr
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bic r0, r0, #(1<<6)
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msr cpsr_c, r0
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bx lr
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/* void arm_disable_fiqs(void); */
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ARM_FUNCTION _arm_disable_fiqs
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mrs r0, cpsr
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orr r0, r0, #(1<<6)
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msr cpsr_c, r0
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bx lr
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#if ARCH_ARMv7
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ARM_FUNCTION _arm_read_vbar
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mrc p15, 0, r0, c12, c0, 0
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bx lr
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ARM_FUNCTION _arm_write_vbar
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mcr p15,0, r0, c12, c0, 0
|
|
bx lr
|
|
|
|
#endif
|
|
|
|
#if ARCH_ARMv7
|
|
ARM_FUNCTION _arm_flush_branch_predictor
|
|
|
|
mov r0, #0
|
|
mcr p15, 0, r0, c7, c5, 6 /* flush the branch predictor cache */
|
|
isb
|
|
mov pc, lr
|
|
#endif
|
|
|
|
/* void arm_memory_barrier(void); */
|
|
ARM_FUNCTION _arm_memory_barrier
|
|
|
|
#if ARCH_ARMv7
|
|
dmb
|
|
#endif
|
|
bx lr
|
|
|
|
#ifdef PRODUCT_EMBEDDEDIOP
|
|
/* <rdar://problem/16290859> WFI errata workaround for Cortex-A5 */
|
|
dummy_store:
|
|
.long 0xaaaabbbb
|
|
|
|
.balign 32
|
|
#endif //PRODUCT_EMBEDDEDIOP
|
|
|
|
ARM_FUNCTION _arch_halt
|
|
|
|
#if !NO_ARM_HALT
|
|
# if ARCH_ARMv7
|
|
dsb
|
|
#ifdef PRODUCT_EMBEDDEDIOP
|
|
str r0, dummy_store
|
|
#endif //PRODUCT_EMBEDDEDIOP
|
|
wfi
|
|
# else
|
|
mov r0, #0
|
|
mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
|
|
# endif
|
|
#endif
|
|
bx lr
|
|
|
|
ARM_FUNCTION _arch_spin
|
|
|
|
#if ARCH_ARMv7 || ARCH_ARMv8
|
|
wfe
|
|
#endif
|
|
b _arch_spin
|
|
|
|
#if WITH_ARM_DCC
|
|
ARM_FUNCTION _read_dtr
|
|
|
|
mrc p14, 0, r0, c0, c5, 0
|
|
bx lr
|
|
|
|
ARM_FUNCTION _write_dtr
|
|
|
|
mcr p14, 0, r0, c0, c5, 0
|
|
isb
|
|
bx lr
|
|
|
|
ARM_FUNCTION _read_dscr
|
|
|
|
mrc p14, 0, r0, c0, c1, 0
|
|
bx lr
|
|
#endif /* WITH_ARM_DCC */
|
|
|
|
|
|
#if CPU_APPLE_SWIFT
|
|
ARM_FUNCTION _swift_read_l2cerrsts
|
|
|
|
mrc p15, 1, r0, c15, c2, 5
|
|
bx lr
|
|
|
|
ARM_FUNCTION _swift_write_l2cerrsts
|
|
|
|
mcr p15, 1, r0, c15, c2, 5
|
|
isb
|
|
bx lr
|
|
|
|
ARM_FUNCTION _swift_read_l2cerradr
|
|
|
|
mrc p15, 1, r0, c15, c2, 7
|
|
bx lr
|
|
|
|
ARM_FUNCTION _swift_write_l2cerradr
|
|
|
|
mcr p15, 1, r0, c15, c2, 7
|
|
isb
|
|
bx lr
|
|
#endif /* CPU_APPLE_SWIFT */
|