277 lines
4.1 KiB
ArmAsm
277 lines
4.1 KiB
ArmAsm
/*
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* Copyright (c) 2011-2012, 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <arch/arm64/proc_reg.h>
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.text
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.align 2
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.globl _arm_read_sctlr
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_arm_read_sctlr:
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mrs x0, SCTLR_ELx
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ret
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.text
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.align 2
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.globl _arm_write_sctlr
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_arm_write_sctlr:
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msr SCTLR_ELx, x0
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dsb sy
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isb sy
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// The ifdef should match the ifdef in arch_cpu_quiesce()
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#if CPU_APPLE_CYCLONE
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// Don't allow MMU or WXN to be disabled. Placing the check after the msr
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// means that a ROP attack will fail unless an attacker can trigger an
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// interrupt between the msr and check
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mov x1, x0
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orr x0, x0, #SCTLR_M_ENABLED
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orr x0, x0, #SCTLR_WXN_ENABLED
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cmp x0, x1
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b.ne _arm_write_sctlr
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#endif
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ret
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#if WITH_EL3
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.text
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.align 2
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.globl _arm_write_scr
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_arm_write_scr:
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msr SCR_EL3, x0
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isb sy
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ret
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#endif
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#if WITH_L2_AS_RAM
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.text
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.align 2
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.globl _arm_read_l2_cramconfig
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_arm_read_l2_cramconfig:
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mrs x0, s3_3_c15_c7_0
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ret
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#endif
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.text
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.align 2
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.globl _arm_write_mair
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_arm_write_mair:
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msr MAIR_ELx, x0
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isb sy
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ret
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.text
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.align 2
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.globl _arm_write_tcr
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_arm_write_tcr:
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msr TCR_ELx, x0
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isb sy
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ret
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.text
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.align 2
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.globl _arm_write_ttbr0
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_arm_write_ttbr0:
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msr TTBR0_ELx, x0
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isb sy
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ret
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.text
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.align 2
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.globl _arm_read_cpacr
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_arm_read_cpacr:
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mrs x0, CPACR_EL1
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ret
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.text
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.align 2
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.globl _arm_write_cpacr
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_arm_write_cpacr:
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msr CPACR_EL1, x0
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isb sy
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ret
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.text
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.align 2
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.globl _arm_read_cntp_ctl
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_arm_read_cntp_ctl:
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isb sy
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mrs x0, CNTP_CTL_EL0
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ret
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.text
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.align 2
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.globl _arm_write_cntp_ctl
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_arm_write_cntp_ctl:
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msr CNTP_CTL_EL0, x0
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isb sy
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ret
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.text
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.align 2
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.globl _arm_read_cntpct
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_arm_read_cntpct:
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isb sy
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mrs x0, CNTPCT_EL0
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ret
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.text
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.align 2
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.globl _arm_write_cntp_tval
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_arm_write_cntp_tval:
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msr CNTP_TVAL_EL0, x0
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isb sy
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ret
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.text
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.align 2
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.globl _arm_flush_tlbs
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_arm_flush_tlbs:
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dsb sy
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#if WITH_EL3
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tlbi alle3
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#else
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tlbi vmalle1
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#endif
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dsb sy
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isb sy
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ret
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.text
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.align 2
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.globl _arm_invalidate_icache
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_arm_invalidate_icache:
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ic iallu
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dsb sy
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isb sy
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ret
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.text
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.align 2
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.globl _arm_invalidate_dcache_line
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_arm_invalidate_dcache_line:
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ret
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.text
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.align 2
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.globl _arm_clean_dcache_line
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_arm_clean_dcache_line:
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ret
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.text
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.align 2
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.globl _arm_clean_invalidate_dcache
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_arm_clean_invalidate_dcache:
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ret
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.text
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.align 2
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.globl _arm_clean_dcache
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_arm_clean_dcache:
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ret
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.text
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.align 2
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.globl _arm_invalidate_dcache
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_arm_invalidate_dcache:
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ret
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.text
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.align 2
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.globl _arm_clean_invalidate_dcache_line
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_arm_clean_invalidate_dcache_line:
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dc civac, x0
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ret
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.text
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.align 2
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.globl _arm_drain_write_buffer
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_arm_drain_write_buffer:
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ret
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.text
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.align 2
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.globl _arm_memory_barrier
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_arm_memory_barrier:
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dmb sy
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ret
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.text
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.align 2
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.globl _arm_vtop
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_arm_vtop:
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mrs x2, DAIF // Load current DAIF
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msr DAIFSet, #(DAIFSC_IRQF | DAIFSC_FIQF) // Disable IRQ
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isb sy
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mov x9, x0 // Saved address
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at s1e3r, x0 // Translation Stage 1 EL1
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isb sy
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mrs x1, PAR_EL1 // Read result
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tst x1, #1 // Test Translation not valid
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cset x0, eq
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b.ne L_arm_vtop_ret
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movk x3, #0xf000
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movk x3, #0xffff, lsl #16
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movk x3, #0xffff, lsl #32
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and x1, x1, x3 // Get physical address base
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and x0, x9, #0xfff
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orr x0, x1, x0 // Add page offset
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L_arm_vtop_ret:
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msr DAIF, x2 // Restore interrupt state, return
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isb sy
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ret
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.text
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.align 2
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.globl _arm_disable_async_aborts
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_arm_disable_async_aborts:
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msr DAIFSet, #(DAIFSC_ASYNCF)
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isb sy
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ret
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.text
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.align 2
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.globl _arm_enable_async_aborts
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_arm_enable_async_aborts:
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msr DAIFClr, #(DAIFSC_ASYNCF)
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isb sy
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ret
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.text
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.align 2
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.globl _arch_disable_ints
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_arch_disable_ints:
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msr DAIFSet, #(DAIFSC_IRQF | DAIFSC_FIQF)
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isb sy
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ret
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.text
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.align 2
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.globl _arch_enable_ints
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_arch_enable_ints:
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msr DAIFClr, #(DAIFSC_IRQF | DAIFSC_FIQF)
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isb sy
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ret
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.text
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.align 2
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.globl _arch_halt
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_arch_halt:
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dsb sy
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isb sy
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wfi
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ret
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.text
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.align 2
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.globl _arch_spin
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_arch_spin:
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hint 0x45 // make fastsim drop to debugger (nop on hardware)
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b .
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