101 lines
1.9 KiB
C
101 lines
1.9 KiB
C
/*
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* Copyright (C) 2011-2012, 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <arch.h>
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#include <arch/arm/arm.h>
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#include <arch/arm64/proc_reg.h>
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#include <debug.h>
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#include <platform.h>
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#include <platform/memmap.h>
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extern void arm_write_sctlr(uint64_t);
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extern uint64_t arm_read_sctlr();
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extern void arm_enable_async_aborts();
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#if WITH_EL3
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extern void arm_write_scr(uint64_t);
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#endif
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int arch_cpu_init(bool resume)
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{
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uint64_t sctlr;
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#if WITH_EL3
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uint64_t scr;
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/* enable interrupts forwarding to EL3 */
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scr = (SCR_EA | SCR_FIQ | SCR_IRQ);
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arm_write_scr(scr);
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#endif
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/* enable async aborts */
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arm_enable_async_aborts();
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/* invalidate caches */
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arm_invalidate_icache();
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arm_invalidate_dcache();
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sctlr = arm_read_sctlr();
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/* turn on Stack Alignment check */
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sctlr |= SCTLR_SA_ENABLED;
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/* turn on the mmu */
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arm_mmu_init(resume);
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sctlr |= SCTLR_M_ENABLED;
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/* disallow executing from writeable pages */
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sctlr |= SCTLR_WXN_ENABLED;
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/* turn on d-cache */
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sctlr |= SCTLR_D_ENABLED;
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/* turn on i-cache */
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sctlr |= SCTLR_I_ENABLED;
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/* enable the MMU, caches and etc. */
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arm_write_sctlr(sctlr);
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#if WITH_VFP
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/* initialize VFP */
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arm_fp_init();
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#endif
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return 0;
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}
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int arch_cpu_quiesce(void)
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{
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#if !CPU_APPLE_CYCLONE
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uint64_t sctlr;
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/* clean the d-cache */
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arm_clean_dcache();
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/* read the control regiser base value */
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sctlr = arm_read_sctlr();
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sctlr &= ~(SCTLR_D_ENABLED | SCTLR_SA_ENABLED | SCTLR_I_ENABLED | SCTLR_M_ENABLED | SCTLR_WXN_ENABLED);
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/* disable the MMU, caches and etc. */
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arm_write_sctlr(sctlr);
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/* invalidate i-cache */
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arm_invalidate_icache();
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#endif /* !CPU_APPLE_CYCLONE */
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return 0;
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}
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int arch_cpu_init_posttasks(void)
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{
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return 0;
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}
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