106 lines
3.3 KiB
C
106 lines
3.3 KiB
C
/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include "amp_v3_shim.h"
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// This array will hold the contents of memory that will be used for dq calibration
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// static uint8_t dqcal_saved_data[AMC_NUM_RANKS][sizeof(DQ_PRBS7_PATTERNS) * AMC_NUM_CHANNELS]__aligned(32);
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static void shim_save_restore_memory_region(uint32_t save_or_restore);
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///////////////////////////////////////////////////////////////////////////////
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////// Local functions
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///////////////////////////////////////////////////////////////////////////////
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// Before starting dq calibration, saves the contents of dram region that will be written to with calibration patterns.
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// After calibration is complete, restores the contents back to DRAM.
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static void shim_save_restore_memory_region(uint32_t save_or_restore)
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{
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}
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///////////////////////////////////////////////////////////////////////////////
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////// Global functions
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///////////////////////////////////////////////////////////////////////////////
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void shim_init_calibration_params(struct amp_calibration_params *cfg_params)
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{
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// Set the number of channels and ranks on this target
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cfg_params->num_channels = AMC_NUM_CHANNELS;
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cfg_params->num_ranks = AMC_NUM_RANKS;
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// Fiji A0 has a 1 to 1 deskew to sdll step ratio
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if((platform_get_chip_id() == 0x7000) && (platform_get_chip_revision() == CHIP_REVISION_A0)) {
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cfg_params->sdll_scale = 1;
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cfg_params->deskew_scale = 1;
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}
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}
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void shim_configure_pre_ca(void)
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{
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amc_calibration_start(true);
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}
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void shim_enable_rddqcal(bool enable)
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{
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amc_enable_rddqcal(enable);
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}
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void shim_configure_post_wrlvl(struct amp_calibration_params *cfg_params)
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{
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amc_calibration_start(false);
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}
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void shim_configure_pre_wrdq(bool resume)
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{
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amc_calibration_start(true);
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// ok to keep PSQWQCTL0 and PSQWQCTL1 at their value setup for wrdqcal even for the rddqcal that follows
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amc_wrdqcal_start(true);
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}
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void shim_configure_post_prbs_rddq(struct amp_calibration_params *cfg_params)
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{
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amc_wrdqcal_start(false);
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amc_calibration_start(false);
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// Save off the CA, WrLvl, Rddq, and Wrdq offsets to PMU
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if (!(cfg_params->resume))
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calibration_save_restore_regs(CALIB_SAVE, cfg_params->num_channels);
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}
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void shim_mrcmd_to_ch_rnk(uint8_t rw, uint8_t channel, uint8_t rank, int32_t reg, uintptr_t val)
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{
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amc_mrcmd_to_ch_rnk((amc_mrcmd_op_t) rw, channel, rank, reg, val);
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}
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uint64_t shim_compute_dram_addr(uint32_t ch, uint32_t rnk, uint32_t bank, uint32_t row, uint32_t col)
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{
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return amc_get_uncached_dram_virt_addr(ch, rnk, bank, row, col);
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}
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uint32_t shim_get_consecutive_bytes_perchnrnk(void)
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{
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// query AMC for how many consecutive bytes before channel interleaving
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return amc_get_consecutive_bytes_perchnrnk();
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}
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void shim_store_memory_calibration(void *cal_values, uint32_t cal_size)
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{
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if (power_store_memory_calibration(cal_values, cal_size) == 0)
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panic("Unable to save memory calibration values to PMU nvram\n");
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}
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void shim_load_memory_calibration(void *cal_values, uint32_t cal_size)
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{
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if (power_load_memory_calibration(cal_values, cal_size) == 0)
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panic("Unable to load memory calibration values from PMU nvram\n");
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}
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