543 lines
21 KiB
C
543 lines
21 KiB
C
/*
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* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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/*
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* Driver for the LPDDR4 compatible DRAM Control Subsystem (DCS) block
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*/
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#include <debug.h>
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#include <sys/menu.h>
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#include <drivers/dcs/dcs_init_lib.h>
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#include <drivers/dram.h>
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#include <drivers/power.h>
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#include <drivers/miu.h>
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#include <lib/env.h>
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#include <platform.h>
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#include <platform/soc/hwclocks.h>
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#include <platform/chipid.h>
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#include <platform/memmap.h>
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#include <platform/timer.h>
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#include <sys.h>
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#include <string.h>
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void mcu_late_init(void)
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{
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}
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uint32_t density_to_Gb(int density)
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{
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switch (density) {
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case JEDEC_LPDDR4_DENSITY_4Gb:
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return 4;
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case JEDEC_LPDDR4_DENSITY_6Gb:
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return 6;
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case JEDEC_LPDDR4_DENSITY_8Gb:
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return 8;
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case JEDEC_LPDDR4_DENSITY_12Gb:
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return 12;
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case JEDEC_LPDDR4_DENSITY_16Gb:
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return 16;
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case JEDEC_LPDDR4_DENSITY_24Gb:
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return 24;
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case JEDEC_LPDDR4_DENSITY_32Gb:
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return 32;
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default:
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panic("unknown LPDDR4 density %d", density);
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}
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}
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static struct dcs_memory_device_info _dcs_device_info;
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static bool _dcs_device_info_inited;
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const struct dcs_memory_device_info *dcs_get_memory_device_info(void)
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{
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// if memory is not inited, device info is unknown, spin here ...
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if (false == _dcs_device_info_inited)
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panic("DCS Memory Device Info grab has jumped the gun");
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return ((const struct dcs_memory_device_info *)&_dcs_device_info);
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}
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// Returns memory size per amcc block
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uint64_t dcs_get_memory_size(void)
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{
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// if memory is not inited, density is unknown, spin here ...
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if (false == _dcs_device_info_inited)
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panic("DCS Memory Size grab has jumped the gun");
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// device density (in MBytes) * ( / 2 due to x16 lpddr4 devices) * num of channels * num of ranks
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return (density_to_Gb(_dcs_device_info.density) * (1024 / 8 / 2) * DCS_NUM_CHANNELS * DCS_NUM_RANKS);
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}
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uint32_t dcs_get_memory_info(void)
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{
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uint8_t config_id = 0;
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// Read device info: vendor, revision, and configuration info
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// Configuration info: device width, device type, device density
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// We are assuming all of our devices are identical
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dcs_mrcmd(MR_READ, 1, 1, 0x5, (uintptr_t)&_dcs_device_info.vendor_id);
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dcs_mrcmd(MR_READ, 1, 1, 0x6, (uintptr_t)&_dcs_device_info.rev_id);
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dcs_mrcmd(MR_READ, 1, 1, 0x7, (uintptr_t)&_dcs_device_info.rev_id2);
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dcs_mrcmd(MR_READ, 1, 1, 0x8, (uintptr_t)&config_id);
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if ((_dcs_device_info.vendor_id == 0) || (config_id == 0))
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panic("failed to read vendor-id/config-id, vid:%08x, config:%08x, rev:%08x\n",
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_dcs_device_info.vendor_id, config_id, _dcs_device_info.rev_id);
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_dcs_device_info.width = (32 >> ((config_id >> JEDEC_MR8_WIDTH_SHIFT) & JEDEC_MR8_WIDTH_MASK)) >> 3;
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_dcs_device_info.density = ((config_id >> JEDEC_MR8_DENSITY_SHIFT) & JEDEC_MR8_DENSITY_MASK);
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_dcs_device_info.type = ((config_id >> JEDEC_MR8_TYPE_SHIFT) & JEDEC_MR8_TYPE_MASK);
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_dcs_device_info_inited = true;
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uint32_t device_size_Gbits = density_to_Gb(_dcs_device_info.density);
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uint32_t total_size_Mbytes = dcs_get_memory_size();
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dprintf(DEBUG_INFO, "sdram vendor id:0x%02x rev id:0x%02x rev id2:%02x\n",
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_dcs_device_info.vendor_id, _dcs_device_info.rev_id, _dcs_device_info.rev_id2);
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dprintf(DEBUG_INFO, "sdram config: width %d/%d Gbit/type %d\n", _dcs_device_info.width << 3,
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device_size_Gbits, _dcs_device_info.type);
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// Check against Hardware Register Min/Max
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if (total_size_Mbytes < 128 || total_size_Mbytes > (16 * 1024) )
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panic("unsupported DRAM density: %d Gbit (with Chan==%d x Rank==%d yields %d MB)",
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device_size_Gbits, DCS_NUM_CHANNELS, DCS_NUM_RANKS, total_size_Mbytes);
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return 0;
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}
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//================================================================================
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void dcs_change_freq(uint32_t freq_bin)
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{
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// Change the MCU Clk Frequency to the new Frequency
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dbgprintf(DCS_DBG_FREQ, "Changing Frequency to Bin %d\n", freq_bin);
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// Make the actual Change by sending the appropriate message to the PMGR
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uint32_t perf_level = (freq_bin == 0)? kPerformanceMemoryFull:
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(freq_bin == 1)? kPerformanceMemoryMid:
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(freq_bin == 3)? kPerformanceMemoryLow:
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DCS_NONVAL;
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if (perf_level == DCS_NONVAL) {
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shim_panic("Unsupported Frequency Bin Request: %d\n", freq_bin);
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}
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clocks_set_performance(perf_level);
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}
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//================================================================================
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void dcs_store_memory_calibration(void *cal_values, uint32_t cal_size)
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{
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// Save the calibration array to PMU nvram
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#if 0
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if (power_store_memory_calibration(cal_values, cal_size) == 0)
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shim_panic("Unable to save memory calibration values to PMU nvram\n");
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#endif
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}
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void dcs_load_memory_calibration(void *cal_values, uint32_t cal_size)
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{
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// Retrieve calibration array from PMU nvram
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#if 0
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if (power_load_memory_calibration(cal_values, cal_size) == 0)
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shim_panic("Unable to load memory calibration values from PMU nvram\n");
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#endif
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}
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// To dump calibration results from iBoot menu command
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static int dump_mem_calibration_info(int argc, struct cmd_arg *args)
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{
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dcs_init_debug_enable(DCS_DBG_CAL);
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debug_level_dcs = DEBUG_CRITICAL;
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calibration_cfg_params_init(false, DCS_NUM_CHANNELS, DCS_NUM_RANKS);
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calibration_dump_results(SELECT_CAL_ALL, false);
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return 0;
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}
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MENU_COMMAND_DEBUG(memcal_info, dump_mem_calibration_info, "Prints memory calibration results", NULL);
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//================================================================================
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////////////////////////////////////////////////////////////
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//
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// DCS Init Sequence
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// Incorporates these specs from SEG
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// Maui: Init_A1.html dated Mar 2, 2015, Init_B0.html dated May 20, 2015, Init_B0_1200.html dated June 2, 2015, Init_1200.html dated Oct 29, 2015
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// Elba: Init.html dated March 04, 2016, Init_A0.html dated July 14 15, 2015
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// s8003: Init_A0.html dated May 20, 2015, Init_A0_1200.html dated June 17, 2015, Init_1200.html dated Oct 29, 2015
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// M8: Init.html dated Apr 2, 2015
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// Cayman: Init.html dated Feb 18, 2015
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////////////////////////////////////////////////////////////
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int32_t dcs_init(dcs_boottype_t boot_type)
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{
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uint32_t num_dcs = DCS_NUM_CHANNELS;
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uint32_t num_rnk = DCS_NUM_RANKS;
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dcs_config_params_t *param_table;
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#ifndef DCS_RUN_AT_50MHZ
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volatile uint32_t *cal_results_save_addr = (volatile uint32_t *) MEMORY_CALIB_SAVE_BASE_ADDR;
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#if DCS_DO_CALIBRATION
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struct amp_calibration_params *cal_cfg = NULL;
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#endif // #if DCS_DO_CALIBRATION
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#endif // #ifndef DCS_RUN_AT_50MHZ
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dprintf(DEBUG_INFO, "dcs_init() ... !\n");
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// Config our boot type and note the ChipID/Rev
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if (!dcs_init_config(boot_type, platform_get_chip_id(), platform_get_chip_revision(),
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num_dcs, num_rnk)) {
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panic("DCS Init Config is NOT RIGHT");
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}
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dcs_init_debug_enable(DCS_DBG_OVERVIEW);
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dcs_init_debug_enable(DCS_DBG_MILESTONE);
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// dcs_init_debug_enable(DCS_DBG_REG_ACCESS);
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// dcs_init_debug_enable(DCS_DBG_CHAN_DETAIL);
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// dcs_init_debug_enable(DCS_DBG_SPIN);
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// dcs_init_debug_enable(DCS_DBG_MR_READ);
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// dcs_init_debug_enable(DCS_DBG_CAL);
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dcs_init_debug_enable(DCS_DBG_CAL_MILESTONE);
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dcs_init_debug_enable(DCS_DBG_FREQ);
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// Initialize the DCS Parameter Table (uses platform-specific callout)
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param_table = dcs_init_param_table();
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// <rdar://problem/22429659> Maui/Malta/Elba: Reset DRAM during panic reboot in LLB to avoid problems with init sequence
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#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003 || SUB_PLATFORM_S8001
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#if WITH_HW_POWER
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int result;
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uint8_t boot_stage;
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// If we rebooted to save panic log, try resetting the DRAM to reset the FSP on the DRAM
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result = power_get_nvram(kPowerNVRAMiBootErrorStageKey, &boot_stage);
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// if we properly read the PMU NVRAM and it says we are booting to save panic log ...
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if(result == 0 && boot_stage == kPowerNVRAMiBootStagePanicSave) {
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dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 0);
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// Leave reset asserted for 200 us
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delay_for_us(200);
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dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 1);
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// Wait 2 ms before starting mem init sequence
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delay_for_us(2000);
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}
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#endif
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#endif
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//================================================================================
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// Step 0: AMC Prolog
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//================================================================================
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dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 0, "Prolog");
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dcs_init_Prolog();
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//================================================================================
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// Step 1: AMC Initial Configuration
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//================================================================================
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dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 1, "Initial AMC Config");
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dcs_init_AMC_Initial_Config();
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//================================================================================
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// Step 2: AMP Initial Configuration
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//================================================================================
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dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 2, "AMP Initial Config");
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dcs_init_AMP_Initial_Config();
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//================================================================================
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// Step 3: Self-Refresh Exit
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//================================================================================
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dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 3, "Self-Refresh Exit");
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dcs_init_Self_Refresh_Exit_a();
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if (izColdBoot && !izFPGA) {
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// Change MCU Clk --> 50Mz
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dcs_change_freq(3);
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// Wait 5 us after Switch to 50MHz to avoid race condition
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dcs_spin(5, "after 50MHz\n");
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}
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dcs_init_Self_Refresh_Exit_b();
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//================================================================================
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// Step 4: DRAM Reset, ZQ Calibration & Configuration (cold boot only)
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//================================================================================
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dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 4, "ZQ Calibration & Configuration");
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dcs_init_ZQ_Cal_Cfg();
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//================================================================================
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// Step 5: Topology-specific configuration
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//================================================================================
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dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 5, "Memory Topology Config");
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dcs_init_AddrCfg_Cfg();
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dcs_get_memory_info();
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uint32_t total_size_Mbytes = dcs_get_memory_size();
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dcs_init_TotalSize_Cfg(total_size_Mbytes);
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// DRAM vendor-specific workarounds
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dcs_dram_workarounds(boot_type);
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//================================================================================
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// Step 6: Prepare for switch from boot-clock speed to normal operation speed
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//================================================================================
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dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 6, "Reenable_AMC_Scheduler");
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dcs_init_Reenable_AMC_Scheduler();
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#if DCS_RUN_AT_50MHZ
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dprintf(DEBUG_CRITICAL, "DCS Init: memory frequency fixed to 50 MHz\n");
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#else
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#if DCS_DO_CALIBRATION
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cal_cfg = calibration_cfg_params_init(izResume, num_dcs, num_rnk);
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// Override the chip_id and chip_rev default values with actual values
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cal_cfg->chip_id = platform_get_chip_id();
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cal_cfg->chip_rev = platform_get_chip_revision();
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// Coarse CS training disabled on Maui A0/A1
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if(cal_cfg->chip_id == 0x8000 && cal_cfg->chip_rev < CHIP_REVISION_B0)
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cal_cfg->disable_coarse_cs_training = true;
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cal_cfg->clk_period_bin0 = param_table->freq[0].clk_period;
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cal_cfg->clk_period_bin1 = param_table->freq[1].clk_period;
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// Note if we will use Widest-Eye for calculating Optimal Vref
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if (dcs_init_variant_enable(0) & DCS_VARIANT_VREF_USES_WIDEST) {
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cal_cfg->opt_vref_mode = DCS_CAL_OPT_VREF_MODE_WIDEST;
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}
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dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: Config Init'd\n");
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#endif
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// Only perform steps 7-10 if frequequency bucket 1 is supported
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if(param_table->supported_freqs & DCS_FREQ(1)) {
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//================================================================================
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// Step 7: Setup registers for CA calibration for bucket 1
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//================================================================================
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dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 7, "CA Calibration Setup--800MHz");
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dcs_init_CA_Cal_Setup_Freq1();
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//================================================================================
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// Step 8: AMP Dynamic CA Vref Timing Calibration at Vmin 800MHz
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//================================================================================
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dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 8, "CA Vref Calibration--800MHz, Vmin");
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#if DCS_DO_CALIBRATION
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// Use these values for 800MHz
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cal_cfg->RL = 16;
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cal_cfg->WL = 12;
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// We will be calibrating for @800MHz (FreqBin 1)
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cal_cfg->freq_bin = 1;
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if (izColdBoot) {
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dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d CA Cal\n", cal_cfg->freq_bin);
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calibrate_ca();
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} else {
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dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d Cal Regs Restore\n", cal_cfg->freq_bin);
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// Restore Calibration Parameters from PMU
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calibration_save_restore_ca_wrlvl_regs(CALIB_RESTORE, num_dcs, cal_cfg->freq_bin);
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}
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#else
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dbgprintf(DCS_DBG_MILESTONE, "DCS is Skipping Calibration, per Build Config\n");
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#endif
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dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 8, "Post CA Vref Calibration");
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dcs_init_CA_Cal_Freq1();
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//================================================================================
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// Step 9: Setup registers for DQ calibration for bucket 1
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//================================================================================
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dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 9, "DQ Calibration Setup--800MHz");
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dcs_init_DQ_Cal_Setup_Freq1_a();
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// Change MCU Clk --> bucket 1
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if(!izFPGA)
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dcs_change_freq(1);
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dcs_init_DQ_Cal_Setup_Freq1_b();
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//================================================================================
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// Step 10: PHY write DQ calibration
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//================================================================================
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dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 10, "Wr DQ Cal--800MHz");
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#if DCS_DO_CALIBRATION
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if (izColdBoot) {
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dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d WrLvl\n", cal_cfg->freq_bin);
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calibrate_wrlvl();
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dcs_init_post_wrlvl();
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dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d Cal Regs Save\n", cal_cfg->freq_bin);
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// Save Calibration Parameters (so far) to Memory Stash
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calibration_save_restore_ca_wrlvl_regs(CALIB_SAVE, num_dcs, cal_cfg->freq_bin);
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dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d RdDQ Cal\n", cal_cfg->freq_bin);
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calibrate_rddq();
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dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d WrDQ Cal\n", cal_cfg->freq_bin);
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calibrate_wrdq();
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}
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#else
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dbgprintf(DCS_DBG_MILESTONE, "DCS is Skipping Calibration, per Build Config\n");
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#endif
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dcs_init_wrdq_skew();
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cal_results_save_addr = dcs_save_calibration_results(cal_results_save_addr, DCS_FREQ(1));
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} // if(param_table->supported_freqs & DCS_FREQ1) {
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//================================================================================
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// Step 11: Setup registers for CA calibration for bucket 0
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//================================================================================
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dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 11, "CA Vref Calibration Setup--1200MHz");
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dcs_init_CA_Cal_Setup_Freq0();
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//================================================================================
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// Step 12: AMP Dynamic CA Timing Calibration
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//================================================================================
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dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 12, "CA Vref Calibration--1200MHz, Vnom");
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#if DCS_DO_CALIBRATION
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if(param_table->freq[0].clk_period == CLK_PERIOD_1600) {
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// Use these values for 1600MHz
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cal_cfg->RL = 28;
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cal_cfg->WL = 14;
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} else if(param_table->freq[0].clk_period == CLK_PERIOD_800) {
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// Use these values for 800MHz
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cal_cfg->RL = 14;
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cal_cfg->WL = 12;
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} else {
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// Use these values for 1200MHz
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cal_cfg->RL = 24;
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cal_cfg->WL = 12;
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}
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|
|
|
// We will be calibrating for FreqBin 0
|
|
cal_cfg->freq_bin = 0;
|
|
|
|
if (izColdBoot) {
|
|
dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d CA Cal\n", cal_cfg->freq_bin);
|
|
calibrate_ca();
|
|
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
|
|
dcs_dram_workarounds_step12();
|
|
#endif
|
|
}
|
|
#else
|
|
dbgprintf(DCS_DBG_MILESTONE, "DCS is Skipping Calibration, per Build Config\n");
|
|
#endif
|
|
|
|
//================================================================================
|
|
// Step 13: Setup registers for DQ calibration for bucket 0
|
|
//================================================================================
|
|
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 13, "DQ Calibration Setup--1200MHz");
|
|
dcs_init_DQ_Cal_Setup_Freq0_a();
|
|
|
|
// Change MCU Clk --> bucket 0
|
|
if(!izFPGA)
|
|
dcs_change_freq(0);
|
|
|
|
dcs_init_DQ_Cal_Setup_Freq0_b();
|
|
|
|
//================================================================================
|
|
// Step 14: AMP Dynamic DQ Calibration
|
|
//================================================================================
|
|
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 14, "Wr DQ Cal--1200MHz, Vmin");
|
|
|
|
#if DCS_DO_CALIBRATION
|
|
if (izColdBoot) {
|
|
dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d WrLvl\n", cal_cfg->freq_bin);
|
|
calibrate_wrlvl();
|
|
|
|
dcs_init_post_wrlvl();
|
|
|
|
dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d Cal Regs Save\n", cal_cfg->freq_bin);
|
|
// Save Calibration Parameters (all the rest) to Memory Stash & then copy Stash to PMU
|
|
calibration_save_restore_ca_wrlvl_regs(CALIB_SAVE, num_dcs, cal_cfg->freq_bin);
|
|
|
|
dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d RdDQ Cal\n", cal_cfg->freq_bin);
|
|
calibrate_rddq();
|
|
dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d WrDQ Cal\n", cal_cfg->freq_bin);
|
|
calibrate_wrdq();
|
|
|
|
// Save off any applicable freq 0 registers
|
|
cal_results_save_addr = dcs_save_calibration_results(cal_results_save_addr, DCS_FREQ(0));
|
|
}
|
|
#else
|
|
dbgprintf(DCS_DBG_MILESTONE, "DCS is Skipping Calibration, per Build Config\n");
|
|
#endif
|
|
|
|
#endif // #if DCS_RUN_AT_50MHZ ... #else
|
|
|
|
//================================================================================
|
|
// Step 15: Setup Registers for Boot
|
|
//================================================================================
|
|
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 15, "Setup Registers for Boot");
|
|
dcs_init_Reg_for_Boot();
|
|
|
|
//================================================================================
|
|
// Step 16: Enable Other Features
|
|
//================================================================================
|
|
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 16, "Enable Other Features");
|
|
dcs_init_MoreFeatures();
|
|
|
|
//================================================================================
|
|
// Step 17: Enable Fast Critical Word Forwarding Feature
|
|
//================================================================================
|
|
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 17, "Fast Critical Word Forwarding");
|
|
dcs_init_Fast_Critical_Word_Forwarding();
|
|
|
|
//================================================================================
|
|
// Step 18: Enable Power- and Clock-Gating Features; Config MCC and Global Timers
|
|
//================================================================================
|
|
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 18, "Gating and Global Timers");
|
|
dcs_init_Gating_Global_Timers();
|
|
|
|
//================================================================================
|
|
// Step 19: ODTS read & set interval for periodic MR4 on-die Temp sensor reading
|
|
//================================================================================
|
|
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 19, "ODTS & Die Temp");
|
|
dcs_init_ODTS();
|
|
|
|
// rdar://problem/23244578, <rdar://problem/23355941>: Allow zqctimer value to be saved at this point to reconfig sequence
|
|
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003 || SUB_PLATFORM_S8001
|
|
#ifndef DCS_RUN_AT_50MHZ
|
|
cal_results_save_addr = dcs_save_calibration_results(cal_results_save_addr, 0);
|
|
#endif
|
|
#endif
|
|
|
|
//================================================================================
|
|
// Program tunables at the end
|
|
//================================================================================
|
|
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Tunables\n");
|
|
dcs_init_apply_tunables();
|
|
|
|
//================================================================================
|
|
// Restore clock frequency to bucket 1 if it is supported
|
|
//================================================================================
|
|
if(!izFPGA)
|
|
if(param_table->supported_freqs & DCS_FREQ(1))
|
|
dcs_change_freq(1);
|
|
|
|
// cache memory info for later
|
|
platform_set_memory_info_with_revids(_dcs_device_info.vendor_id, dcs_get_memory_size(), _dcs_device_info.rev_id, _dcs_device_info.rev_id2);
|
|
|
|
dbgprintf(DCS_DBG_MILESTONE, "DCS Init DONE!!\n");
|
|
return 0;
|
|
}
|
|
|
|
//================================================================================
|