283 lines
8.0 KiB
C
283 lines
8.0 KiB
C
/*
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* Copyright (C) 2007-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <drivers/apple/gpio.h>
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#include <drivers/spi.h>
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#include <platform.h>
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#include <platform/gpio.h>
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#include <platform/gpiodef.h>
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#include <platform/memconfig.h>
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#include <platform/soc/hwregbase.h>
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#if GPIO_VERSION > 5
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#include <platform/soc/pmgr.h>
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#endif
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static const struct {
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uintptr_t base_addr;
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uint32_t pin_count;
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} gpio_cfgs[GPIOC_COUNT] = {
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#if GPIOC_COUNT > 0
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{ GPIO_BASE_ADDR, GPIO_GROUP_COUNT * GPIOPADPINS },
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#endif
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#if GPIOC_COUNT > 1
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{ GPIO_1_BASE_ADDR, GPIO_1_GROUP_COUNT * GPIOPADPINS },
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#endif
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};
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uint32_t gpio_read(gpio_t gpio)
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{
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uint8_t gpioc = GPIO2CONTROLLER(gpio);
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uint8_t pad = GPIO2PAD(gpio);
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uint8_t pin = GPIO2PIN(gpio);
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uint8_t gpion = pad * GPIOPADPINS + pin;
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#if WITH_HW_SPI && defined(GPIO_PAD_SPI)
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if (pad == GPIO_PAD_SPI) return spi_gpio_read(pin);
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#endif
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return (rGPIOCFG(gpio_cfgs[gpioc].base_addr, gpion) & 1) ? 1UL : 0UL;
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}
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void gpio_write(gpio_t gpio, uint32_t val)
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{
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uint32_t cfg_val, cfg_mask;
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uint8_t gpioc = GPIO2CONTROLLER(gpio);
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uint8_t pad = GPIO2PAD(gpio);
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uint8_t pin = GPIO2PIN(gpio);
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uint8_t gpion = pad * GPIOPADPINS + pin;
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#if WITH_HW_SPI && defined(GPIO_PAD_SPI)
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if (pad == GPIO_PAD_SPI) {
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spi_gpio_write(pin, val);
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return;
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}
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#endif
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cfg_val = (val) ? CFG_OUT_1 : CFG_OUT_0;
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cfg_mask = INPUT_ENABLE | FUNC_MASK | INT_MASKED | CFG_MASK | DATA_1;
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rGPIOCFG(gpio_cfgs[gpioc].base_addr, gpion) = (rGPIOCFG(gpio_cfgs[gpioc].base_addr, gpion) & ~cfg_mask) | (cfg_val & cfg_mask);
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}
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void gpio_safe_reconfigure(uint8_t gpioc, uint8_t gpion, uint32_t config)
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{
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uint32_t old_config;
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uint32_t new_input_enable;
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uint32_t old_input_enable;
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old_config = rGPIOCFG(gpio_cfgs[gpioc].base_addr, gpion);
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new_input_enable = config & INPUT_ENABLE;
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if (new_input_enable == 0) {
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rGPIOCFG(gpio_cfgs[gpioc].base_addr, gpion) = old_config & ~INPUT_ENABLE;
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old_input_enable = 0;
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} else {
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old_input_enable = old_config & INPUT_ENABLE;
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}
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rGPIOCFG(gpio_cfgs[gpioc].base_addr, gpion) = (config & ~INPUT_ENABLE) | old_input_enable;
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if (new_input_enable != 0 && old_input_enable == 0)
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rGPIOCFG(gpio_cfgs[gpioc].base_addr, gpion) = config;
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}
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void gpio_configure(gpio_t gpio, uint32_t config)
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{
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uint32_t cfg_val, cfg_mask;
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uint8_t gpioc = GPIO2CONTROLLER(gpio);
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uint8_t pad = GPIO2PAD(gpio);
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uint8_t pin = GPIO2PIN(gpio);
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uint8_t gpion = pad * GPIOPADPINS + pin;
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#if WITH_HW_SPI && defined(GPIO_PAD_SPI)
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if (pad == GPIO_PAD_SPI) {
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spi_gpio_configure(pin, config);
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return;
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}
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#endif
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cfg_mask = INPUT_ENABLE | FUNC_MASK | INT_MASKED | CFG_MASK;
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switch (config) {
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case GPIO_CFG_IN : cfg_val = CFG_IN; break;
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case GPIO_CFG_OUT_0 : cfg_val = CFG_OUT_0; cfg_mask |= DATA_1; break;
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case GPIO_CFG_OUT_1 : cfg_val = CFG_OUT_1; cfg_mask |= DATA_1; break;
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case GPIO_CFG_OUT : cfg_val = CFG_OUT; break;
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case GPIO_CFG_FUNC0 : cfg_val = CFG_FUNC0; break;
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case GPIO_CFG_FUNC1 : cfg_val = CFG_FUNC1; break;
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case GPIO_CFG_FUNC2 : cfg_val = CFG_FUNC2; break;
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case GPIO_CFG_DFLT :
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cfg_val = platform_get_default_gpio_cfg(gpioc)[gpion]; cfg_mask |= PULL_MASK | DATA_1; break;
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default : return;
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}
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gpio_safe_reconfigure(gpioc, gpion, (rGPIOCFG(gpio_cfgs[gpioc].base_addr, gpion) & ~cfg_mask) | (cfg_val & cfg_mask));
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}
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void gpio_configure_pupdn(gpio_t gpio, int32_t pupdn)
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{
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uint8_t gpioc = GPIO2CONTROLLER(gpio);
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uint8_t pad = GPIO2PAD(gpio);
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uint8_t pin = GPIO2PIN(gpio);
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uint8_t gpion = pad * GPIOPADPINS + pin;
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uint32_t cfg_val;
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if (pupdn < GPIO_NO_PUPDN) {
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cfg_val = PULL_DOWN;
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} else if (pupdn > GPIO_NO_PUPDN) {
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#if GPIO_VERSION < 5
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cfg_val = PULL_UP;
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#else
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cfg_val = (pupdn > GPIO_PUP) ? PULL_UP_STRONG : PULL_UP;
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#endif
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} else {
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/* GPIO_NO_PUPDN */
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cfg_val = PULL_NONE;
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}
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rGPIOCFG(gpio_cfgs[gpioc].base_addr, gpion) = (rGPIOCFG(gpio_cfgs[gpioc].base_addr, gpion) & ~PULL_MASK) | (cfg_val & PULL_MASK);
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}
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int gpio_init_pinconfig(void)
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{
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uint8_t cnt, gpioc;
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for (gpioc = 0; gpioc < GPIOC_COUNT; gpioc++) {
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const uint32_t *pin_config = platform_get_default_gpio_cfg(gpioc);
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for (cnt = 0; cnt < gpio_cfgs[gpioc].pin_count; cnt++) {
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gpio_safe_reconfigure(gpioc, cnt, pin_config[cnt]);
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}
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#ifdef FMI_SLEW_RATE
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// Adjust global FMI pads slew rate.
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rGPIO_SR_EN(gpio_cfgs[gpioc].base_addr) = (rGPIO_SR_EN(gpio_cfgs[gpioc].base_addr) & ~1) | (FMI_SLEW_RATE & 1);
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#endif
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#ifdef FMI_DIFF_SEL
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// Configure FMI differential pin selection
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rGPIO_FMI_DIFF_SEL(gpio_cfgs[gpioc].base_addr) = FMI_DIFF_SEL;
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#endif
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#if GPIO_VERSION > 0
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// Enable interrupt when pin not configured as GPIO
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rGPIO_NPL_IN_EN(gpio_cfgs[gpioc].base_addr) = 1;
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#endif
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}
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#if GPIO_VERSION > 6
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#if !APPLICATION_SECUREROM
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// The GPIO Micro-Architecture Specification v1.3, section 4.1 (5) says:
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//
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// "To control the XTAL_DRIVE strength software needs to program
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// the GPIO_MISC_CTRL[XTAL_DRIVE_STRENGTH] bit. This should be
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// programmed only after 140,000 24MHZ clocks to allow the xtal
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// to lock to 24MHz. Once this change is made we should allow
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// 20,000 clocks for a stable duty cycle.
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//
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// Since we're not doing this in the SecureROM we're definitely far
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// enough along here that we've met the 140K cycles requirement.
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rGPIO_MISC_CTRL(gpio_cfgs[0].base_addr) = 0;
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#endif
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#endif
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return 0;
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}
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void gpio_fixup_pinconfig(const uint32_t *fixup_list) {
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int32_t i;
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for (i = 0; fixup_list[i * 2] != UINT32_MAX; i ++) {
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gpio_t gpio = fixup_list[(i * 2) + 0];
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uint8_t gpioc = GPIO2CONTROLLER(gpio);
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uint8_t pad = GPIO2PAD(gpio);
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uint8_t pin = GPIO2PIN(gpio);
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uint8_t gpion = pad * GPIOPADPINS + pin;
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gpio_safe_reconfigure(gpioc, gpion, fixup_list[(i * 2) + 1]);
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}
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}
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int gpio_init_memory(uint32_t drive_strength)
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{
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gpio_t gpio;
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uint32_t pin, pad, gpion, config;
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int32_t cnt, pin_count = sizeof(memory_interface_gpios) / sizeof(memory_interface_gpios[0]);
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/*
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* XXXX only one gpio controller is supported
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*/
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config = CFG_IN;
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#if GPIO_VERSION < 5
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switch (drive_strength) {
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case GPIO_DRIVE_X1 : config |= DRIVE_X1; break;
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case GPIO_DRIVE_X2 : config |= DRIVE_X2; break;
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case GPIO_DRIVE_X3 : config |= DRIVE_X3; break;
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case GPIO_DRIVE_X4 : config |= DRIVE_X4; break;
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case GPIO_DRIVE_X6 : config |= DRIVE_X6; break;
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}
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#else
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switch (drive_strength) {
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case GPIO_DRIVE_S0 : config |= DRIVE_S0; break;
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case GPIO_DRIVE_S1 : config |= DRIVE_S1; break;
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case GPIO_DRIVE_S2 : config |= DRIVE_S2; break;
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case GPIO_DRIVE_S3 : config |= DRIVE_S3; break;
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case GPIO_DRIVE_S4 : config |= DRIVE_S4; break;
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case GPIO_DRIVE_S5 : config |= DRIVE_S5; break;
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case GPIO_DRIVE_S6 : config |= DRIVE_S6; break;
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case GPIO_DRIVE_S7 : config |= DRIVE_S7; break;
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case GPIO_DRIVE_S8 : config |= DRIVE_S8; break;
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case GPIO_DRIVE_S9 : config |= DRIVE_S9; break;
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case GPIO_DRIVE_S10 : config |= DRIVE_S10; break;
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case GPIO_DRIVE_S11 : config |= DRIVE_S11; break;
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case GPIO_DRIVE_S12 : config |= DRIVE_S12; break;
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case GPIO_DRIVE_S13 : config |= DRIVE_S13; break;
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case GPIO_DRIVE_S14 : config |= DRIVE_S14; break;
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case GPIO_DRIVE_S15 : config |= DRIVE_S15; break;
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}
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#endif
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for (cnt = 0; cnt < pin_count; cnt++) {
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gpio = memory_interface_gpios[cnt];
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pad = GPIO2PAD(gpio);
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pin = GPIO2PIN(gpio);
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gpion = pad * GPIOPADPINS + pin;
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gpio_safe_reconfigure(0, gpion, config);
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}
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return 0;
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}
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uint32_t gpio_get_board_id(void)
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{
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#if GPIO_VERSION > 5
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// The board ID pins must have been sampled by the time this request is made.
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RELEASE_ASSERT(rGPIO_PINSTRAPS_VALID(gpio_cfgs[0].base_addr) & 1);
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// Return the sampled board ID value.
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return MINIPMGR_SECURITY_GPIO_STRAPS_BOARD_ID_XTRCT(rMINIPMGR_SECURITY_GPIO_STRAPS);
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#else
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panic("gpio_get_board_id() not supported for this platform");
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#endif
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}
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#if APPLICATION_IBOOT
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int gpio_diag_pinconfig(void)
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{
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return 0;
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}
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#endif /* APPLICATION_IBOOT */
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