128 lines
4.7 KiB
C
128 lines
4.7 KiB
C
/*
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* Copyright (C) 2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <lib/env.h>
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#include <lib/paint.h>
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#include <lib/syscfg.h>
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#include <drivers/wpc.h>
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#include "wpc.h"
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static const uint32_t wpcConfig_DeGamma[WPC_CONFIG_DE_GAMMA_COUNT] = {
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0, 159, 317, 476, 634, 793, 960,
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1146, 1352, 1577, 1824, 2091, 2380, 2691,
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3025, 3382, 3762, 4166, 4594, 5046, 5524,
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6027, 6556, 7111, 7692, 8300, 8936, 9599,
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10289, 11008, 11755, 12532, 13337, 14172, 15036,
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15930, 16855, 17810, 18796, 19813, 20862, 21942,
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23054, 24199, 25376, 26585, 27828, 29104, 30413,
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31756, 33133, 34544, 35990, 37470, 38986, 40536,
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42122, 43743, 45401, 47094, 48824, 50590, 52393,
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54233, 56110, 58024, 59976, 61965, 63993, 66059,
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68163, 70306, 72487, 74708, 76968, 79267, 81606,
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83984, 86402, 88861, 91360, 93899, 96479, 99100,
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101762, 104466, 107211, 109997, 112825, 115695, 118607,
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121562, 124559, 127599, 130681, 133807, 136976, 140188,
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143444, 146743, 150086, 153473, 156905, 160380, 163901,
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167466, 171075, 174730, 178430, 182175, 185966, 189802,
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193684, 197612, 201586, 205606, 209672, 213786, 217945,
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222152, 226406, 230706, 235054, 239450, 243893, 248384,
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252922, 257509,
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};
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static const uint32_t wpcConfig_EnGamma[WPC_CONFIG_EN_GAMMA_COUNT] = {
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0, 103, 207, 310, 413, 517, 620, 721,
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814, 900, 981, 1057, 1129, 1198, 1264, 1327,
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1388, 1447, 1503, 1558, 1611, 1663, 1713, 1762,
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1809, 1856, 1901, 1946, 1989, 2032, 2073, 2114,
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2154, 2194, 2233, 2271, 2308, 2345, 2381, 2417,
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2452, 2487, 2521, 2555, 2588, 2621, 2653, 2685,
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2717, 2748, 2779, 2809, 2840, 2869, 2899, 2928,
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2957, 2985, 3014, 3042, 3069, 3097, 3124, 3151,
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3178, 3230, 3282, 3333, 3383, 3432, 3480, 3528,
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3575, 3621, 3667, 3712, 3756, 3800, 3843, 3886,
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3928, 3970, 4011, 4052, 4092, 4132, 4171, 4210,
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4249, 4287, 4325, 4362, 4399, 4436, 4472, 4508,
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4543, 4614, 4683, 4750, 4817, 4883, 4947, 5011,
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5074, 5136, 5197, 5257, 5316, 5374, 5432, 5489,
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5545, 5601, 5656, 5710, 5764, 5817, 5870, 5922,
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5973, 6024, 6074, 6124, 6174, 6222, 6271, 6319,
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6366, 6460, 6552, 6643, 6732, 6820, 6906, 6991,
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7074, 7157, 7238, 7318, 7398, 7476, 7553, 7629,
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7704, 7778, 7852, 7924, 7996, 8067, 8137, 8206,
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8275, 8343, 8410, 8477, 8542, 8608, 8672, 8736,
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8800, 8925, 9048, 9169, 9288, 9405, 9520, 9633,
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9745, 9855, 9964, 10071, 10176, 10281, 10383, 10485,
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10585, 10684, 10782, 10879, 10975, 11069, 11163, 11256,
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11347, 11438, 11528, 11617, 11705, 11792, 11878, 11963,
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12048, 12215, 12379, 12541, 12699, 12856, 13009, 13161,
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13310, 13457, 13602, 13745, 13886, 14025, 14162, 14298,
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14431, 14564, 14694, 14824, 14951, 15078, 15203, 15326,
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15449, 15570, 15689, 15808, 15925, 16042, 16157, 16271,
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};
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void wpc_write_reg(uint32_t reg, uint32_t value);
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uint32_t wpc_read_reg(uint32_t reg);
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void wpc_init(uint32_t display_width, uint32_t display_height)
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{
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// WPC Configuration defined in ADBE TRM v0.1.14. Section 4.4
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// Active Region Start
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wpc_write_reg(WPC_CONFIG_ACTIVE_REGION_START_OFFSET,
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WPC_CONFIG_ACTIVE_REGION_START_START_X_INSRT(0) |
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WPC_CONFIG_ACTIVE_REGION_START_START_Y_INSRT(0));
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// Active Region Size
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wpc_write_reg(WPC_CONFIG_ACTIVE_REGION_SIZE_OFFSET,
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WPC_CONFIG_ACTIVE_REGION_SIZE_WIDTH_INSRT(display_width) |
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WPC_CONFIG_ACTIVE_REGION_SIZE_HEIGHT_INSRT(display_height));
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// Pixel Gain
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for (int i = 0; i < WPC_CONFIG_PIXEL_GAIN_COUNT; i ++) {
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wpc_write_reg(WPC_CONFIG_PIXEL_GAIN_OFFSET(i), 1 << 19);
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}
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// GainStep (Round using 48.16 Fixed Point)
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wpc_write_reg(WPC_CONFIG_GAIN_STEP_X_OFFSET, (uint32_t)((((16777216ULL << 16) / display_width) + (1<<15)) >> 16));
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wpc_write_reg(WPC_CONFIG_GAIN_STEP_Y_OFFSET, (uint32_t)((((16777216ULL << 16) / display_height) + (1<<15)) >> 16));
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// Kick the values in to the registers.
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wpc_write_reg(WPC_CONFIG_UPDATE_CONTROL_OFFSET, 0x3);
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}
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void wpc_install_gamma_table(u_int32_t *red_lut, u_int32_t *green_lut, u_int32_t *blue_lut, struct syscfg_wpcl *wpcl)
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{
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// DeGamma
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for (int i = 0; i < WPC_CONFIG_DE_GAMMA_COUNT; i ++) {
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wpc_write_reg(WPC_CONFIG_DE_GAMMA_OFFSET(i), wpcConfig_DeGamma[i]);
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}
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// DeGamma Last
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wpc_write_reg(WPC_CONFIG_DE_GAMMA_LAST_OFFSET, 262144);
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// EnGamma
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for (int i = 0; i < WPC_CONFIG_EN_GAMMA_COUNT; i ++) {
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wpc_write_reg(WPC_CONFIG_EN_GAMMA_OFFSET(i), wpcConfig_EnGamma[i]);
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}
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// EnGamma Last
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wpc_write_reg(WPC_CONFIG_EN_GAMMA_LAST_OFFSET, 16384);
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}
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void wpc_write_reg(uint32_t reg, uint32_t value)
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{
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(*(volatile u_int32_t *)(WPC_BASE_ADDR + reg)) = value;
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}
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uint32_t wpc_read_reg(uint32_t reg)
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{
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return (*(volatile u_int32_t *)(WPC_BASE_ADDR + reg));
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} |