348 lines
9.5 KiB
C
348 lines
9.5 KiB
C
/*
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* Copyright (C) 2014-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <arch.h>
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#include <debug.h>
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#include <drivers/dram.h>
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#include <lib/libc.h>
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#include <platform.h>
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#include <platform/tunables.h>
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#include <stdint.h>
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// platfom_indep holds generic functions that are just defined once for all
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// platforms, and are not expected to be rebuilt for every target/product.
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//
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// These functions can vary per BUILD, and per architecture, but not per
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// PLATFORM, TARGET, PRODUCT, or CONFIG
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void platform_not_supported(void)
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{
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dprintf(DEBUG_CRITICAL, "\n");
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dprintf(DEBUG_CRITICAL, "\n");
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dprintf(DEBUG_CRITICAL, "\n");
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dprintf(DEBUG_CRITICAL, "**************************************\n");
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dprintf(DEBUG_CRITICAL, "* *\n");
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dprintf(DEBUG_CRITICAL, "* This unit is not supported *\n");
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dprintf(DEBUG_CRITICAL, "* *\n");
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dprintf(DEBUG_CRITICAL, "**************************************\n");
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while (1);
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}
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// Fuse Modes
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// Bit 0 - Chip is Secure
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// Bit 1 - Chip is Production
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uint32_t platform_get_fuse_modes(void)
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{
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u_int32_t fuse_summary = 0;
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if (platform_get_secure_mode()) fuse_summary |= (1 << 0);
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if (platform_get_raw_production_mode()) fuse_summary |= (1 << 1);
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return fuse_summary;
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}
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const char *platform_get_memory_manufacturer_string(void)
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{
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uint8_t index;
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// This list is based of JEDEC Vendor list in dram.h
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// index 0 and 15 are reserverd, we are using them to provide additional information related to the system.
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static const char *memory_manufacturer_strings[JEDEC_NUM_MANUF_IDS] = {
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"Unknown",
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"Samsung",
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"Qimonda",
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"Elpida",
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"Etron",
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"Nanya",
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"Hynix",
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"Mosel",
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"Winbond",
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"ESMT",
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"Reserved",
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"Spansion",
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"SST",
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"ZMOS",
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"Intel",
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"Numonyx",
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"Micron",
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"FPGA",
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};
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index = platform_get_memory_manufacturer_id();
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if(platform_is_pre_lpddr4()) {
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if (index >= JEDEC_NUM_MANUF_IDS)
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return NULL;
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return memory_manufacturer_strings[index];
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} else {
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switch(index) {
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case JEDEC_LPDDR4_MANUF_ID_SAMSUNG:
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return "Samsung";
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break;
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case JEDEC_LPDDR4_MANUF_ID_HYNIX:
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return "Hynix";
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break;
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case JEDEC_LPDDR4_MANUF_ID_MICRON:
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return "Micron";
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break;
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default:
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return NULL;
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break;
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}
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}
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}
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uintptr_t platform_get_memory_region_base(memory_region_type_t region)
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{
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uintptr_t base = platform_get_memory_region_base_optional(region);
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if (base == (uintptr_t)-1)
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panic("unsupported region %d base requested\n", (int)region);
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return base;
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}
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size_t platform_get_memory_region_size(memory_region_type_t region)
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{
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size_t size = platform_get_memory_region_size_optional(region);
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if (size == (size_t)-1)
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panic("unsupported region %d size requested\n", region);
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return size;
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}
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void platform_apply_tunables(const struct tunable_chip_struct *tunable_chips, uint32_t num_tunable_chips, const char* type)
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{
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const struct tunable_struct *tunable;
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uintptr_t base_address;
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uint32_t chip_rev = platform_get_chip_revision();
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uint32_t i;
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uint32_t t;
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bool match = false;
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if (num_tunable_chips == 0)
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return;
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ASSERT(tunable_chips != NULL);
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// For each bucket of tunable values...
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for (i = 0; i < num_tunable_chips; i++) {
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// Tunable for a newer chip revision?
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if (tunable_chips[i].chip_rev > chip_rev) {
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continue;
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}
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// Tunable for an older chip revision?
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if (tunable_chips[i].chip_rev < chip_rev) {
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if (match) {
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// We've already found all the tunables matching
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// this chip revision -- we're done.
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break;
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} else {
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// We haven't found a match yet. Because the tunable
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// chip table is supposed to be sorted from highest
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// to lowest, finding an older chip revision means
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// that there is no entry in the table for this
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// chip revision and we'll use the first older one
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// we find.
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dprintf(DEBUG_SPEW, "%s tunables for chip rev %d not found -- using tunables for chip rev %d\n",
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type, chip_rev, tunable_chips[i].chip_rev);
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chip_rev = tunable_chips[i].chip_rev;
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}
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}
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// We've found a matching tunable chip revision (either an exact
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// match or the next older chip revision).
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match = true;
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// Get the base address and pointer to the tunables data.
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tunable = tunable_chips[i].tunable;
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ASSERT(tunable != NULL);
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base_address = tunable_chips[i].base_address;
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// For each tunable in registers at this base address...
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for (t = 0; tunable[t].offset != -1; t++) {
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// Elided tunables have a size of zero, just skip them.
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if (tunable[t].size == 0) {
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continue;
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}
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switch (tunable[t].size) {
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case sizeof(uint32_t):
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{
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volatile uint32_t *addr;
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uint32_t new_reg, old_reg, mask, value;
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// Get the address of the register.
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addr = (volatile uint32_t *)(base_address + tunable[t].offset);
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// Get the current value of the register.
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old_reg = *addr;
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mask = (uint32_t)tunable[t].mask;
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value = (uint32_t)tunable[t].value;
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// If the tunable needs to be applied, do it.
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if ((old_reg & mask) != (value & mask)) {
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new_reg = old_reg;
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new_reg &= ~mask;
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new_reg |= value & mask;
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*addr = new_reg;
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dprintf(DEBUG_SPEW, "%s tunable addr/mask/value=%p/0x%08x/0x%08x: 0x%08x -> 0x%08x\n",
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type, addr, mask, value, old_reg, new_reg);
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} else {
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dprintf(DEBUG_SPEW, "%s tunable addr/mask/value=%p/0x%08x/0x%08x: already correct 0x%08x\n",
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type, addr, mask, value, old_reg);
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}
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break;
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}
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case sizeof(uint64_t):
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{
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volatile uint64_t *addr;
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uint64_t new_reg, old_reg, mask, value;
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// Get the address of the register.
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addr = (volatile uint64_t *)(base_address + tunable[t].offset);
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// Get the current value of the register.
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old_reg = *addr;
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mask = tunable[t].mask;
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value = tunable[t].value;
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// If the tunable needs to be applied, do it.
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if ((old_reg & mask) != (value & mask)) {
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new_reg = old_reg;
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new_reg &= ~mask;
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new_reg |= value & mask;
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*addr = new_reg;
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dprintf(DEBUG_SPEW, "%s tunable addr/mask/value=%p/0x%016llx/0x%016llx: 0x%016llx -> 0x%016llx\n",
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type, addr, mask, value, old_reg, new_reg);
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} else {
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dprintf(DEBUG_SPEW, "%s tunable addr/mask/value=%p/0x%016llx/0x%016llx: already correct 0x%016llx\n",
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type, addr, mask, value, old_reg);
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}
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break;
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}
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default:
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panic("Unsupported tunable register size");
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}
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}
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}
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}
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uint8_t *platform_apply_dt_tunables(const struct tunable_chip_struct *tunable_chips,
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uint32_t num_tunable_chips, uint8_t *buffer,
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uintptr_t dt_base, const char *type)
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{
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const struct tunable_struct *tunable;
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struct tunable_struct_unpacked tunable_data;
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uintptr_t addr;
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uintptr_t base_address;
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uint32_t chip_rev = platform_get_chip_revision();
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uint32_t i;
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uint32_t t;
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bool match = false;
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if (num_tunable_chips == 0)
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return buffer;
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ASSERT((tunable_chips != NULL) && (buffer != NULL));
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// For each bucket of tunable values...
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for (i = 0; i < num_tunable_chips; i++) {
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// Tunable for a newer chip revision?
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if (tunable_chips[i].chip_rev > chip_rev) {
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continue;
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}
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// Tunable for an older chip revision?
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if (tunable_chips[i].chip_rev < chip_rev) {
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if (match) {
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// We've already found all the tunables matching
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// this chip revision -- we're done.
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break;
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} else {
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// We haven't found a match yet. Because the tunable
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// chip table is supposed to be sorted from highest
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// to lowest, finding an older chip revision means
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// that there is no entry in the table for this
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// chip revision and we'll use the first older one
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// we find.
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dprintf(DEBUG_SPEW, "%s tunables for chip rev %d not found -- using tunables for chip rev %d\n",
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type, chip_rev, tunable_chips[i].chip_rev);
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chip_rev = tunable_chips[i].chip_rev;
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}
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}
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// We've found a matching tunable chip revision (either an exact
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// match or the next older chip revision).
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match = true;
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// Copy the tunable value and get the base address of the block it pertains to.
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tunable = tunable_chips[i].tunable;
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ASSERT(tunable != NULL);
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base_address = tunable_chips[i].base_address;
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// For each tunable register at this base address...
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for (t = 0; tunable[t].offset != -1; t++) {
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// Elided tunables have a size of zero, but pass them
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// through in case the driver wants to un-elide them.
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// Copy the tunable data so we can update it.
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tunable_data.offset = tunable[t].offset;
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tunable_data.size = tunable[t].size;
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tunable_data.mask = tunable[t].mask;
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tunable_data.value = tunable[t].value;
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addr = base_address + tunable_data.offset;
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// Get the address of the register.
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if (dt_base != 0) {
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// Adjust the offset to match the reg property in the
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// device tree.
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tunable_data.offset = (uint32_t)addr - dt_base;
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ASSERT(tunable_data.offset != -1);
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}
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if (tunable_data.size == -1) {
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dprintf(DEBUG_SPEW, "%s DT tunable @ 0x%lx: offset=0x%08x, size=%d, mask=0x%16llx, value=0x%16llx\n",
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type, addr,
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tunable_data.offset, tunable_data.size,
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tunable_data.mask, tunable_data.value);
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} else {
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dprintf(DEBUG_SPEW, "%s DT tunable @ 0x%lx: offset=0x%08x, size=%d, mask=0x%08llx, value=0x%08llx\n",
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type, addr,
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tunable_data.offset, tunable_data.size,
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tunable_data.mask, tunable_data.value);
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}
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memcpy(buffer, &tunable_data, sizeof(tunable_data));
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buffer += sizeof(tunable_data);
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}
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}
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return buffer;
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}
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