856 lines
18 KiB
C
856 lines
18 KiB
C
/*
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* Copyright (C) 2007-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <arch.h>
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#include <arch/arm/arm.h>
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#include <drivers/aes.h>
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#include <drivers/flash_nor.h>
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#include <drivers/iic.h>
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#include <drivers/power.h>
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#include <drivers/spi.h>
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#include <drivers/uart.h>
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#include <drivers/usb/usb_public.h>
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#include <drivers/usbphy.h>
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#include <lib/devicetree.h>
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#include <lib/env.h>
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#include <lib/random.h>
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#include <platform.h>
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#include <platform/clocks.h>
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#include <platform/gpio.h>
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#include <platform/gpiodef.h>
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#include <platform/int.h>
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#include <platform/miu.h>
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#include <platform/memmap.h>
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#include <platform/power.h>
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#include <platform/timer.h>
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#include <platform/trampoline.h>
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#include <platform/soc/chipid.h>
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#include <platform/soc/hwclocks.h>
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#include <platform/soc/miu.h>
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#include <platform/soc/power.h>
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#include <sys.h>
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#include <sys/boot.h>
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#include <target.h>
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static void platform_init_boot_strap(void);
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static uint8_t boot_debug;
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int platform_early_init(void)
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{
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#if PRODUCT_LLB || PRODUCT_IBSS
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/* Verify that SecureROM has been disabled */
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if (((*(volatile u_int32_t *)SECURITY_REG) & ROM_READ_DISABLE) == 0) {
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panic("SecureROM is enabled");
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}
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#endif
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#if WITH_HW_PLATFORM_POWER
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/* initialize the s5l8747x power control driver */
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platform_power_init();
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#endif
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#if WITH_HW_MIU
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miu_init();
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#endif
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#if WITH_HW_CLOCKS
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/* initialize the clock driver */
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clocks_init();
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#endif
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#if WITH_HW_VIC
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/* initialize the vic, mask all interrupts */
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interrupt_init();
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#endif
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#if WITH_HW_TIMER
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timer_init(0);
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#endif
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#if WITH_HW_USBPHY
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usbphy_power_down();
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#endif
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#if WITH_HW_UART
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/* do whatever uart initialization we need to get a simple console */
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uart_init();
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#endif
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#if WITH_IIC
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iic_init();
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#endif
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#if !PRODUCT_IBOOT && !PRODUCT_IBEC
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platform_init_power();
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#if WITH_BOOT_STAGE
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boot_check_stage();
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#endif
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#endif
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#if WITH_BOOT_STAGE
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boot_set_stage(kPowerNVRAMiBootStageProductStart);
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#endif
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#if WITH_HW_POWER
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power_get_nvram(kPowerNVRAMiBootDebugKey, &boot_debug);
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debug_enable_uarts(boot_debug);
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#endif
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#if WITH_HW_DMA
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/* initialize the dma engine */
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dma_init();
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#endif
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#if WITH_TARGET_CONFIG
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target_early_init();
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#endif
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return 0;
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}
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int platform_late_init(void)
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{
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// Chips older then B0 are not supported
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if (platform_get_chip_revision() < 0x10) platform_not_supported();
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#if WITH_ENV
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/* publish secure-boot flag for restore mode */
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env_set_uint("secure-boot", 1, 0);
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#endif
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#if WITH_HW_USB && WITH_USB_MODE_RECOVERY
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usb_early_init();
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#endif
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#if WITH_HW_POWER
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power_late_init();
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#endif
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#if WITH_TARGET_CONFIG
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target_late_init();
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#endif
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return 0;
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}
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int platform_init_setup_clocks(void)
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{
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#if WITH_HW_CLOCKS
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clocks_set_default();
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#endif
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return 0;
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}
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int platform_init_hwpins(void)
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{
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// need board id to select the right pinconfig
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platform_init_boot_strap();
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#if WITH_HW_GPIO
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/* finish initializing the gpio driver */
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gpio_init_pinconfig();
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#endif
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return 0;
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}
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int platform_init_internal_mem(void)
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{
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#if WITH_HW_MIU
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/* initialize sram bus */
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miu_initialize_internal_ram();
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#endif
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return 0;
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}
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int platform_init_mainmem(bool resume)
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{
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#if WITH_HW_MIU && APPLICATION_IBOOT
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/* initialize sdram */
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miu_initialize_dram(resume);
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#endif
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return 0;
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}
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int platform_init_power(void)
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{
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#if WITH_HW_POWER
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power_init();
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#endif
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return 0;
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}
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int platform_quiesce_hardware(enum boot_target target)
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{
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bool quiesce_clocks = false;
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#if APPLICATION_SECUREROM
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quiesce_clocks = true;
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#endif
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#if WITH_TARGET_CONFIG
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target_quiesce_hardware();
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#endif
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#if WITH_HW_USB
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usb_quiesce();
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#endif
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switch (target) {
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case BOOT_HALT:
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case BOOT_DARWIN_RESTORE:
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break;
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case BOOT_IBOOT:
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case BOOT_DARWIN:
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#if WITH_BOOT_STAGE
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boot_set_stage(kPowerNVRAMiBootStageProductEnd);
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#endif
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break;
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case BOOT_DIAGS:
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case BOOT_SECUREROM:
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quiesce_clocks = true;
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// fall through to default
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default:
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#if WITH_BOOT_STAGE
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boot_set_stage(kPowerNVRAMiBootStageOff);
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#endif
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break;
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}
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#if WITH_HW_DMA
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#error "Need to quiesce DMA here if a DMA API is ever added"
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#endif
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#if WITH_HW_TIMER
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timer_stop_all();
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#endif
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#if WITH_HW_VIC
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interrupt_mask_all();
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#endif
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if (quiesce_clocks) {
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#if WITH_HW_CLOCKS
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clocks_quiesce();
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#endif
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}
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return 0;
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}
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int platform_bootprep(enum boot_target target)
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{
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u_int32_t gids = ~0, uids = ~0; /* leave crypto keys alone by default */
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/* prepare hardware for booting into various targets */
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#if WITH_HW_CLOCKS
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if (target != BOOT_IBOOT) clocks_set_performance(kPerformanceHigh);
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#endif
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#if WITH_TARGET_CONFIG
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target_bootprep(target);
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#endif
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/* If we're not restoring, reset the watchdog-on-wake until enabled */
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if ((boot_debug & kPowerNVRAMiBootDebugWDTWake) && (target == BOOT_DARWIN))
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{
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boot_debug &= ~kPowerNVRAMiBootDebugWDTWake;
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#if WITH_HW_POWER
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power_set_nvram(kPowerNVRAMiBootDebugKey, boot_debug);
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#endif
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}
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switch (target) {
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#if APPLICATION_IBOOT
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case BOOT_DARWIN_RESTORE:
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platform_quiesce_display();
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case BOOT_DARWIN:
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if (boot_debug & kPowerNVRAMiBootDebugWDTWake)
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wdt_enable();
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/* even when trusted, Darwin only gets the UID / GID1 */
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uids = 1;
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gids = 2;
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#if WITH_HW_MIU
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miu_select_remap(REMAP_SDRAM);
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#endif
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break;
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case BOOT_DIAGS:
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platform_quiesce_display();
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#if WITH_BOOT_STAGE
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boot_clear_error_count();
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#endif
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break;
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case BOOT_IBOOT:
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#endif
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case BOOT_SECUREROM:
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platform_quiesce_display();
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#if WITH_HW_MIU
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miu_select_remap(REMAP_SDRAM);
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#endif
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break;
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case BOOT_UNKNOWN:
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platform_quiesce_display();
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break;
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default:
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; // do nothing
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}
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/* Let security override keys */
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if (!security_allow_modes(kSecurityModeGIDKeyAccess))
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gids = 0;
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if (!security_allow_modes(kSecurityModeUIDKeyAccess))
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uids = 0;
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/* disable all keys not requested */
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platform_disable_keys(~gids, ~uids);
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return 0;
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}
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void platform_mmu_setup(bool resume)
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{
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RELEASE_ASSERT(false == resume);
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/* mark usable ram as cached/buffered */
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arm_mmu_map_section_range(SRAM_BASE, SRAM_BASE, ROUNDUP(SRAM_BANK_LEN, MB)/MB, kARMMMUNormal, false, false);
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#if APPLICATION_IBOOT
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arm_mmu_map_section_range(SDRAM_BASE, SDRAM_BASE, ROUNDUP(SDRAM_BANK_LEN * SDRAM_BANK_COUNT, MB)/MB, kARMMMUNormal, false, false);
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#endif
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#if APPLICATION_SECUREROM
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arm_mmu_map_section_range(VROM_BASE, VROM_BASE, ROUNDUP(VROM_BANK_LEN, MB)/MB, kARMMMUNormal, false, false);
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#endif
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/* Remap text base is to zero (for exception vectors) */
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arm_mmu_map_section(0, TEXT_BASE, kARMMMUNormalRX, false);
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#ifdef MMU_NONCACHE0_SIZE
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/* create the noncached0 mapping */
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arm_mmu_map_section_range(MMU_NONCACHE0_VBASE, MMU_NONCACHE0_PBASE, ROUNDUP(MMU_NONCACHE0_SIZE, MB)/MB, kARMMMUStronglyOrdered, false, false);
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#endif
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#ifdef MMU_NONCACHE1_SIZE
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/* create the noncached1 mapping */
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arm_mmu_map_section_range(MMU_NONCACHE1_VBASE, MMU_NONCACHE1_PBASE, ROUNDUP(MMU_NONCACHE1_SIZE, MB)/MB, kARMMMUStronglyOrdered, false, false);
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#endif
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}
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int platform_init(void)
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{
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#if WITH_HW_SPI
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spi_init();
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#endif
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#if APPLICATION_IBOOT
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target_init();
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#endif
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return 0;
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}
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int platform_debug_init(void)
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{
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#if WITH_HW_USB
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u_int32_t usb_enabled = 1;
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#if WITH_ENV && SUPPORT_FPGA
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usb_enabled = env_get_uint("usb-enabled", 1);
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#endif
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if (usb_enabled) usb_init();
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#endif
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#if WITH_TARGET_CONFIG
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target_debug_init();
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#endif
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return 0;
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}
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void platform_poweroff(void)
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{
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platform_quiesce_display();
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#if WITH_TARGET_CONFIG
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target_poweroff();
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#endif
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#if WITH_HW_POWER
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boot_set_stage(kPowerNVRAMiBootStageOff);
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power_shutdown();
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#endif
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for(;;);
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}
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u_int32_t platform_set_performance(u_int32_t performance_level)
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{
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u_int32_t old_performance_level = kPerformanceHigh;
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#if WITH_HW_CLOCKS
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old_performance_level = clocks_set_performance(performance_level);
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#endif
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return old_performance_level;
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}
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#if WITH_DEVICETREE
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int platform_update_device_tree(void)
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{
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DTNode *node;
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u_int32_t propSize;
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char *propName;
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void *propData;
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// Find the cpu0 node.
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if (FindNode(0, "cpus/cpu0", &node)) {
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// Fill in the cpu frequency
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propName = "clock-frequency";
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if (FindProperty(node, &propName, &propData, &propSize)) {
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*(uint32_t *)propData = clock_get_frequency(CLK_CPU);
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}
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// Fill in the memory frequency
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propName = "memory-frequency";
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if (FindProperty(node, &propName, &propData, &propSize)) {
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*(uint32_t *)propData = clock_get_frequency(CLK_MEM);
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}
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// Fill in the bus frequency
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propName = "bus-frequency";
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if (FindProperty(node, &propName, &propData, &propSize)) {
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*(uint32_t *)propData = clock_get_frequency(CLK_BUS);
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}
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// Fill in the peripheral frequency
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propName = "peripheral-frequency";
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if (FindProperty(node, &propName, &propData, &propSize)) {
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*(uint32_t *)propData = clock_get_frequency(CLK_PERIPH);
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}
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// Fill in the fixed frequency
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propName = "fixed-frequency";
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if (FindProperty(node, &propName, &propData, &propSize)) {
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*(uint32_t *)propData = clock_get_frequency(CLK_FIXED);
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}
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// Fill in the time base frequency
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propName = "timebase-frequency";
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if (FindProperty(node, &propName, &propData, &propSize)) {
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*(uint32_t *)propData = clock_get_frequency(CLK_TIMEBASE);
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}
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}
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// Find the arm-io node
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if (FindNode(0, "arm-io", &node)) {
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// Fill in the usb-phy frequency
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propName = "usbphy-frequency";
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if (FindProperty(node, &propName, &propData, &propSize)) {
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*(uint32_t *)propData = clock_get_frequency(CLK_USBPHYCLK);
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}
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}
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#if WITH_HW_PLATFORM_CHIPID
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// Find the arm-io node
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if (FindNode(0, "arm-io", &node)) {
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// Fill in the chip-revision property
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propName = "chip-revision";
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if (FindProperty(node, &propName, &propData, &propSize)) {
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*(uint32_t *)propData = platform_get_chip_revision();
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}
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}
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#endif
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#if WITH_HW_USBPHY
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// Fill in the otgphyctrl0 node
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if (FindNode(0, "arm-io/otgphyctrl0", &node)) {
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usbphy_update_device_tree(node);
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}
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// Fill in the otgphyctrl1 node
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if (FindNode(0, "arm-io/otgphyctrl1", &node)) {
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usbphy_update_device_tree(node);
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}
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#endif
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// Carve mfcram out of base of vram. mfcram node should already have size populated
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if (FindNode(0, "mfcram", &node)) {
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uint32_t *mfcramPropData;
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propName = "reg";
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if (FindProperty(node, &propName, &propData, &propSize)) {
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mfcramPropData = propData;
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if (FindNode(0, "vram", &node)) {
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propName = "reg";
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if (FindProperty(node, &propName, &propData, &propSize)) {
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uint32_t *vramPropData = propData;
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mfcramPropData[0] = vramPropData[0];
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vramPropData[0] += mfcramPropData[1];
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vramPropData[1] -= mfcramPropData[1];
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}
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}
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}
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}
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return target_update_device_tree();
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}
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#endif
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static void platform_init_boot_strap(void)
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{
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u_int32_t boot_strap, chip_board_id, gpio_board_id, boot_config;
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// If rSTATESAVE0[0] set then boot strap already valid
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if ((rSTATESAVE0 & 1) != 0) return;
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gpio_configure_pupdn(GPIO_BOARD_ID0, GPIO_PDN);
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gpio_configure_pupdn(GPIO_BOARD_ID1, GPIO_PDN);
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gpio_configure_pupdn(GPIO_BOARD_ID2, GPIO_PDN);
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gpio_configure_pupdn(GPIO_BOARD_ID3, GPIO_PDN);
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gpio_configure_pupdn(GPIO_BOOT_CONFIG0, GPIO_PDN);
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gpio_configure_pupdn(GPIO_BOOT_CONFIG1, GPIO_PDN);
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gpio_configure(GPIO_BOARD_ID0, GPIO_CFG_IN);
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gpio_configure(GPIO_BOARD_ID1, GPIO_CFG_IN);
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gpio_configure(GPIO_BOARD_ID2, GPIO_CFG_IN);
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gpio_configure(GPIO_BOARD_ID3, GPIO_CFG_IN);
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gpio_configure(GPIO_BOOT_CONFIG0, GPIO_CFG_IN);
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gpio_configure(GPIO_BOOT_CONFIG1, GPIO_CFG_IN);
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#if !SUPPORT_FPGA
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platform_power_spin(100); // Wait 100us
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#endif
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chip_board_id = chipid_get_board_id();
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gpio_board_id =
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(gpio_read(GPIO_BOARD_ID3) << 3) |
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(gpio_read(GPIO_BOARD_ID2) << 2) |
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(gpio_read(GPIO_BOARD_ID1) << 1) |
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(gpio_read(GPIO_BOARD_ID0) << 0);
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boot_config =
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(gpio_read(GPIO_BOOT_CONFIG1) << 1) |
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(gpio_read(GPIO_BOOT_CONFIG0) << 0);
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gpio_configure(GPIO_BOARD_ID0, GPIO_CFG_DFLT);
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gpio_configure(GPIO_BOARD_ID1, GPIO_CFG_DFLT);
|
|
gpio_configure(GPIO_BOARD_ID2, GPIO_CFG_DFLT);
|
|
gpio_configure(GPIO_BOARD_ID3, GPIO_CFG_DFLT);
|
|
|
|
gpio_configure(GPIO_BOOT_CONFIG0, GPIO_CFG_DFLT);
|
|
gpio_configure(GPIO_BOOT_CONFIG1, GPIO_CFG_DFLT);
|
|
|
|
boot_strap = (((chip_board_id << 4) | gpio_board_id) << 16) |
|
|
(boot_config << 8) |
|
|
(0x01 << 0);
|
|
|
|
rSTATESAVE0 = (rSTATESAVE0 & 0xFF000000) | (boot_strap & 0x00FFFFFF);
|
|
}
|
|
|
|
u_int32_t platform_get_board_id(void)
|
|
{
|
|
u_int32_t board_id;
|
|
|
|
ASSERT((rSTATESAVE0 & kPlatformScratchFlagBootStrap) != 0);
|
|
|
|
board_id = (rSTATESAVE0 >> 16) & 0xFF;
|
|
|
|
#if SUPPORT_FPGA
|
|
board_id = 0x3F;
|
|
#endif
|
|
|
|
return board_id;
|
|
}
|
|
|
|
u_int32_t platform_get_boot_config(void)
|
|
{
|
|
u_int32_t boot_config;
|
|
|
|
boot_config = (rSTATESAVE0 >> 8) & 0xFF;
|
|
|
|
return boot_config;
|
|
}
|
|
|
|
bool platform_get_boot_device(int32_t index, enum boot_device *boot_device, u_int32_t *boot_flag, u_int32_t *boot_arg)
|
|
{
|
|
u_int32_t boot_config = platform_get_boot_config();
|
|
|
|
/* S5L8747X supports one boot device then USB-DFU per boot config.
|
|
Unlike other platforms, the USB-DFU device is selectable. */
|
|
|
|
#ifdef HACK_BOOT_CONFIG_OVERRIDE
|
|
boot_config = HACK_BOOT_CONFIG_OVERRIDE;
|
|
#endif
|
|
|
|
/* If the index is not zero force DFU mode */
|
|
if (index != 0) index = 1;
|
|
|
|
switch (boot_config) {
|
|
case 0: /* SPI 0, then USB0 FDU */
|
|
case 1: /* SPI 0, then USB1 DFU */
|
|
if (index == 0) {
|
|
*boot_device = BOOT_DEVICE_SPI;
|
|
*boot_flag = 0;
|
|
*boot_arg = 0;
|
|
} else {
|
|
*boot_device = BOOT_DEVICE_USBDFU;
|
|
*boot_flag = 0;
|
|
*boot_arg = 0;
|
|
}
|
|
return true;
|
|
|
|
case 2: /* SPI 0, then USB0 FDU with TEST_MODE */
|
|
case 3: /* SPI 0, then USB1 DFU with TEST_MODE */
|
|
if (index == 0) {
|
|
*boot_device = BOOT_DEVICE_SPI;
|
|
*boot_flag = BOOT_FLAG_TEST_MODE;
|
|
*boot_arg = 0;
|
|
} else {
|
|
*boot_device = BOOT_DEVICE_USBDFU;
|
|
*boot_flag = BOOT_FLAG_TEST_MODE;
|
|
*boot_arg = 0;
|
|
}
|
|
return true;
|
|
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* boot_interface_pin tables
|
|
* tables are executed in order for disable and reverse order for enable
|
|
*
|
|
*/
|
|
|
|
struct boot_interface_pin {
|
|
gpio_t pin;
|
|
u_int32_t enable;
|
|
u_int32_t disable;
|
|
};
|
|
|
|
#if WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI
|
|
#ifdef SPI_NOR0
|
|
static const struct boot_interface_pin spi0_boot_interface_pins[] =
|
|
{
|
|
#if SUPPORT_FPGA
|
|
{ GPIO( 1, 3), GPIO_CFG_FUNC1, GPIO_CFG_DFLT }, // SPI0_CEN
|
|
#else
|
|
{ GPIO( 1, 3), GPIO_CFG_OUT_1, GPIO_CFG_DFLT }, // SPI0_CEN
|
|
#endif
|
|
{ GPIO( 1, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT }, // SPI0_CLK
|
|
{ GPIO( 1, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT }, // SPI0_MOSI
|
|
{ GPIO( 1, 6), GPIO_CFG_FUNC0, GPIO_CFG_DFLT } // SPI0_MISO
|
|
};
|
|
#endif
|
|
#endif /* WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI */
|
|
|
|
void platform_enable_boot_interface(bool enable, enum boot_device boot_device, u_int32_t boot_arg)
|
|
{
|
|
const struct boot_interface_pin *pins = 0;
|
|
u_int32_t cnt, func, pin_count = 0;
|
|
gpio_t pin;
|
|
|
|
switch (boot_device) {
|
|
#if WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI
|
|
case BOOT_DEVICE_SPI :
|
|
#ifdef SPI_NOR0
|
|
if (boot_arg == 0) {
|
|
pins = spi0_boot_interface_pins;
|
|
pin_count = (sizeof(spi0_boot_interface_pins) / sizeof(spi0_boot_interface_pins[0]));
|
|
}
|
|
#endif
|
|
break;
|
|
#endif /* WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI */
|
|
|
|
#if WITH_USB_DFU
|
|
case BOOT_DEVICE_USBDFU :
|
|
/* USB is always configured */
|
|
break;
|
|
#endif /* WITH_USB_DFU */
|
|
|
|
default :
|
|
break;
|
|
}
|
|
|
|
for (cnt = 0; cnt < pin_count; cnt++) {
|
|
if (enable) {
|
|
pin = pins[pin_count - 1 - cnt].pin;
|
|
func = pins[pin_count - 1 - cnt].enable;
|
|
} else {
|
|
pin = pins[cnt].pin;
|
|
func = pins[cnt].disable;
|
|
}
|
|
|
|
dprintf(DEBUG_INFO, "platform_enable_boot_interface: %x, %x\n", pin, func);
|
|
gpio_configure(pin, func);
|
|
}
|
|
}
|
|
|
|
u_int64_t platform_get_nonce(void)
|
|
{
|
|
u_int64_t nonce;
|
|
u_int32_t *nonce_words = (u_int32_t *)&nonce;
|
|
u_int8_t *nonce_bytes = (u_int8_t *)&nonce;
|
|
|
|
// If rSTATESAVE0[1] set then the nonce has already been generated
|
|
if ((rSTATESAVE0 & kPlatformScratchFlagNonce) == 0) {
|
|
#if WITH_RANDOM
|
|
if (random_get_bytes(nonce_bytes, sizeof(nonce)) != 0)
|
|
#endif
|
|
{
|
|
memset(nonce_bytes, 0, sizeof(nonce));
|
|
}
|
|
|
|
rSTATESAVE2 = nonce_words[0];
|
|
rSTATESAVE3 = nonce_words[1];
|
|
|
|
rSTATESAVE0 |= kPlatformScratchFlagNonce;
|
|
} else {
|
|
nonce_words[0] = rSTATESAVE2;
|
|
nonce_words[1] = rSTATESAVE3;
|
|
}
|
|
|
|
return nonce;
|
|
}
|
|
|
|
bool platform_get_ecid_image_personalization_required(void)
|
|
{
|
|
return chipid_get_ecid_image_personalization_required();
|
|
}
|
|
|
|
u_int32_t platform_get_osc_frequency(void)
|
|
{
|
|
return chipid_get_osc_frequency();
|
|
}
|
|
|
|
u_int32_t platform_get_base_soc_voltage(void)
|
|
{
|
|
return 1200;
|
|
}
|
|
|
|
int platform_get_soc_voltages(u_int32_t count, u_int32_t *voltages)
|
|
{
|
|
u_int32_t cnt;
|
|
|
|
if (voltages == 0) return -1;
|
|
|
|
for (cnt = 0; cnt < count; cnt++) {
|
|
voltages[cnt] = platform_get_base_soc_voltage();
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
bool platform_get_usb_cable_connected(void)
|
|
{
|
|
#if WITH_HW_USBPHY
|
|
return usbphy_is_cable_connected();
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
void platform_set_dfu_status(bool dfu)
|
|
{
|
|
gpio_write(GPIO_DFU_STATUS, dfu);
|
|
}
|
|
|
|
bool platform_get_force_dfu(void)
|
|
{
|
|
return gpio_read(GPIO_FORCE_DFU);
|
|
}
|
|
|
|
int platform_translate_key_selector(u_int32_t key_selector, u_int32_t *key_opts)
|
|
{
|
|
switch (key_selector) {
|
|
case IMAGE_KEYBAG_SELECTOR_PROD :
|
|
break;
|
|
|
|
default :
|
|
return -1;
|
|
}
|
|
|
|
*key_opts = AES_KEY_TYPE_GID0 | AES_KEY_SIZE_128;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if APPLICATION_IBOOT
|
|
u_int64_t platform_get_memory_size(void)
|
|
{
|
|
return (2 * 128 * 1024 * 1024);
|
|
}
|
|
|
|
uintptr_t platform_get_memory_region_base_optional(memory_region_type_t region)
|
|
{
|
|
uintptr_t base;
|
|
|
|
switch (region) {
|
|
case kMemoryRegion_Panic:
|
|
base = SDRAM_BASE + platform_get_memory_size() - PANIC_SIZE;
|
|
break;
|
|
|
|
case kMemoryRegion_Display:
|
|
base = SDRAM_BASE + platform_get_memory_size() - PURPLE_GFX_MEMORY_LEN - PANIC_SIZE;
|
|
break;
|
|
|
|
case kMemoryRegion_Kernel:
|
|
base = SDRAM_BASE;
|
|
break;
|
|
|
|
default:
|
|
base = (uintptr_t)-1;
|
|
}
|
|
|
|
return base;
|
|
}
|
|
|
|
size_t platform_get_memory_region_size_optional(memory_region_type_t region)
|
|
{
|
|
size_t size;
|
|
|
|
switch (region) {
|
|
case kMemoryRegion_Panic:
|
|
size = PANIC_SIZE;
|
|
break;
|
|
|
|
case kMemoryRegion_Display:
|
|
size = PURPLE_GFX_MEMORY_LEN;
|
|
break;
|
|
|
|
#if defined(SLEEP_TOKEN_BUFFER_SIZE)
|
|
case kMemoryRegion_SleepToken:
|
|
size = SLEEP_TOKEN_BUFFER_SIZE;
|
|
break;
|
|
|
|
#endif
|
|
|
|
case kMemoryRegion_Kernel:
|
|
size = platform_get_memory_size() - PURPLE_GFX_MEMORY_LEN - PANIC_SIZE;
|
|
break;
|
|
|
|
default:
|
|
size = (size_t)-1;
|
|
}
|
|
|
|
return size;
|
|
}
|
|
|
|
#endif
|
|
|