57 lines
1.5 KiB
ArmAsm
57 lines
1.5 KiB
ArmAsm
/*
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* Copyright (c) 2012-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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.text
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.align 2
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.globl _platform_start
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_platform_start:
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////////////////////////////////////////////////
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// Must preserve X0 and X1
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////////////////////////////////////////////////
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// Disable RSS non-speculative streaming: <rdar://problem/14349246>
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// Do this as early as possible is it can cause incorrect SPR writes.
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mrs x2, s3_0_c15_c1_0 // HID1
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orr x2, x2, #(1<<2) // rssDisNsStreaming
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msr s3_0_c15_c1_0, x2 // HID1
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isb
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// Enable the L2 cache load/store prefetcher on B0 (and later): <rdar://problem/12096765>
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mrs x2, s3_0_c15_c5_0 // HID5
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and x2, x2, #~(3<<44) // B0+: Enable L2C load (bit 44)/store (bit 45) prefetch
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msr s3_0_c15_c5_0, x2 // HID5
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isb
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ret
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.align 2
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.globl _platform_halt
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_platform_halt:
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// For Cyclone, we must disable the MTLB prefetcher before doing WFI.
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// <rdar://problem/15837639> iBoot: implement Cyclone/Typhoon WFI workaround
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mrs x1, s3_0_c15_c2_0 // Read HID2
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orr x0, x1, #(1 << 13) // Set HID2.DisableMTLBPrefetch
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msr s3_0_c15_c2_0, x0 // Write HID2
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dsb sy
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isb sy
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wfi
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// Re-enable MTLB prefetcher after WFI falls through.
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msr s3_0_c15_c2_0, x1 // Restore HID2
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dsb sy
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isb sy
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ret
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