350 lines
8.6 KiB
C
350 lines
8.6 KiB
C
/*
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* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <platform.h>
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#include <platform/pmgr.h>
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#include <platform/soc/chipid.h>
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#include <platform/soc/hwclocks.h>
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#if SUB_PLATFORM_S8000
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#define MINIMUM_FUSE_REVISION 0x8
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#elif SUB_PLATFORM_S8001
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#define MINIMUM_FUSE_REVISION 0x6
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#elif SUB_PLATFORM_S8003
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#define MINIMUM_FUSE_REVISION 0x3
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#else
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#error "Unknown platform"
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#endif
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bool chipid_get_current_production_mode(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_XTRCT(rCFG_FUSE0) != 0;
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}
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bool chipid_get_raw_production_mode(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_XTRCT(rCFG_FUSE0_RAW) != 0;
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}
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void chipid_clear_production_mode(void)
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{
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rCFG_FUSE0 &= ~MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_UMASK;
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}
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bool chipid_get_secure_mode(void)
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{
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// demotion only applies to the SEP, so iBoot always reads
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// the raw value for secure mode (<rdar://problem/15182573>)
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return MINIPMGR_FUSE_CFG_FUSE0_SECURE_MODE_XTRCT(rCFG_FUSE0_RAW);
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}
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uint32_t chipid_get_security_domain(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_SECURITY_DOMAIN_XTRCT(rCFG_FUSE0);
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}
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uint32_t chipid_get_board_id(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_BID_XTRCT(rCFG_FUSE0);
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}
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uint32_t chipid_get_minimum_epoch(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_MINIMUM_EPOCH_XTRCT(rCFG_FUSE0);
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}
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uint32_t chipid_get_chip_id(void)
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{
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#if SUB_PLATFORM_S8000
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return 0x8000;
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#elif SUB_PLATFORM_S8001
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return 0x8001;
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#elif SUB_PLATFORM_S8003
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return 0x8003;
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#else
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#error "Unknown platform"
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#endif
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}
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uint32_t chipid_get_chip_revision(void)
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{
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// we use 4 bits for base layer and 4 bits for metal,
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// the fuses use 3 for each
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#if defined(MINIPMGR_FUSE_CFG_FUSE4_DEV_VERSION_XTRCT)
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uint32_t fuse_val = MINIPMGR_FUSE_CFG_FUSE4_DEV_VERSION_XTRCT(rCFG_FUSE4);
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return (fuse_val & 0x7) | (((fuse_val >> 3) & 0x7) << 4);
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#elif defined(MINIPMGR_FUSE_CFG_FUSE4_CHIP_REV_MAJOR_XTRCT)
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uint32_t fuse = rCFG_FUSE4;
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return ((MINIPMGR_FUSE_CFG_FUSE4_CHIP_REV_MAJOR_XTRCT(fuse) << 4) |
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(MINIPMGR_FUSE_CFG_FUSE4_CHIP_REV_MINOR_XTRCT(fuse)));
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#else
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#error "SPDS doesn't contain expected chip rev extraction defines"
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#endif
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}
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uint32_t chipid_get_osc_frequency(void)
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{
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return OSC_FREQ;
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}
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uint64_t chipid_get_ecid_id(void)
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{
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return ((uint64_t)rECIDHI << 32) | rECIDLO;
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}
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uint64_t chipid_get_die_id(void)
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{
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return ((uint64_t)rECIDHI << 32) | rECIDLO;
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}
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uint32_t chipid_get_cpu_voltage(uint32_t index)
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{
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uint32_t voltage = pmgr_binning_get_mv(index, false, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid CPU voltage index %d\n", index);
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return voltage;
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}
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uint32_t chipid_get_cpu_sram_voltage(uint32_t index)
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{
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uint32_t voltage = pmgr_binning_get_mv(index, true, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid CPU SRAM voltage index %d\n", index);
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return voltage;
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}
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uint32_t chipid_get_soc_voltage(uint32_t index)
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{
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uint32_t voltage;
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#if SUB_PLATFORM_S8001
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#if SUB_TARGET_J99A | SUB_TARGET_J98A
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index = CHIPID_SOC_VOLTAGE_VMIN;
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#else
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index = CHIPID_SOC_VOLTAGE_VNOM;
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#endif
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#endif
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voltage = pmgr_binning_get_mv(index, false, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid SOC voltage index %d\n", index);
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return voltage;
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}
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uint32_t chipid_get_gpu_voltage(uint32_t index)
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{
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uint32_t voltage = pmgr_binning_get_mv(index, false, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid GPU voltage index %d\n", index);
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return voltage;
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}
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uint32_t chipid_get_gpu_sram_voltage(uint32_t index)
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{
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uint32_t voltage = pmgr_binning_get_mv(index, true, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid GPU SRAM voltage index %d\n", index);
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return voltage;
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}
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uint32_t chipid_get_sram_voltage(uint32_t index)
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{
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uint32_t voltage = pmgr_binning_get_mv(CHIPID_VOLTAGE_FIXED, true, chipid_get_fuse_revision() >= MINIMUM_FUSE_REVISION);
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if (voltage == PMGR_BINNING_NOTFOUND)
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panic("Invalid SRAM voltage index %d\n", index);
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return voltage;
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}
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bool chipid_get_fuse_lock(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE1_AP_LOCK_XTRCT(rCFG_FUSE1) != 0;
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}
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void chipid_set_fuse_lock(bool locked)
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{
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if (locked) {
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rCFG_FUSE1 |= MINIPMGR_FUSE_CFG_FUSE1_AP_LOCK_INSRT(1);
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asm("dsb sy");
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if (!chipid_get_fuse_lock()) {
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panic("Failed to lock fuses\n");
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}
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}
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}
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bool chipid_get_fuse_seal(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE1_SEAL_FUSES_XTRCT(rCFG_FUSE1) != 0;
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}
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uint32_t chipid_get_lpo_trim(void)
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{
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#if SUB_PLATFORM_S8000
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// <rdar://problem/18530570> LPO clock doesn't lock with fused TRIM value but does with 0 trim
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if (chipid_get_fuse_revision() < 3)
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return 0x20;
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else
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#endif
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return MINIPMGR_FUSE_CFG_FUSE2_LPO_TRIM_XTRCT(rCFG_FUSE2);
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}
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#if SUB_PLATFORM_S8000
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uint32_t chipid_get_pcie_txpll_vco_v2i_i_set(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE3_PCIE_TXPLL_VCO_V2I_I_SET_XTRCT(rCFG_FUSE3);
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}
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uint32_t chipid_get_pcie_txpll_vco_v2i_pi_set(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE3_PCIE_TXPLL_VCO_V2I_PI_SET_XTRCT(rCFG_FUSE3);
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}
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uint32_t chipid_get_pcie_refpll_vco_v2i_i_set(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE4_PCIE_REFPLL_VCO_V2I_I_SET_XTRCT(rCFG_FUSE4);
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}
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uint32_t chipid_get_pcie_refpll_vco_v2i_pi_set(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE4_PCIE_REFPLL_VCO_V2I_PI_SET_XTRCT(rCFG_FUSE4);
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}
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uint32_t chipid_get_pcie_rx_ldo(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE3_PCIE_RX_LDO_XTRCT(rCFG_FUSE3);
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}
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#elif SUB_PLATFORM_S8001 || SUB_PLATFORM_S8003
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uint32_t chipid_get_pcie_refpll_fcal_vco_digctrl(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE4_PCIE_REFPLL_FCAL_VCO_DIGCTRL_XTRCT(rCFG_FUSE4);
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}
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#endif
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uint32_t chipid_get_soc_temp_sensor_trim(uint32_t sensor_index)
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{
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uint32_t sensor_trim;
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#if SUB_PLATFORM_S8000 && defined(MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_TRIMG_UMASK)
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// S8000 A1
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if (chipid_get_chip_revision() == CHIP_REVISION_A1) {
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switch (sensor_index) {
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case 0:
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return MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_XTRCT_V1(rCFG_FUSE2);
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case 1:
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return MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN1_XTRCT_V1(rCFG_FUSE2);
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case 2:
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return MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN2_XTRCT_V1(rCFG_FUSE3);
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default:
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panic("invalid thermal sensor %u", sensor_index);
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}
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}
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#endif
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// S8000 B0/C0, S8001 A0/B0, S8003 A0/A1
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switch (sensor_index) {
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case 0:
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sensor_trim = rCFG_FUSE2;
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sensor_trim &= MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_TRIMG_UMASK | MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_TRIMO_UMASK;
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sensor_trim >>= MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN0_TRIMG_SHIFT;
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return sensor_trim;
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case 1:
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sensor_trim = rCFG_FUSE2;
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sensor_trim &= MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN1_TRIMG_UMASK | MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN1_TRIMO_UMASK;
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sensor_trim >>= MINIPMGR_FUSE_CFG_FUSE2_THERMAL_SEN1_TRIMG_SHIFT;
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return sensor_trim;
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case 2:
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sensor_trim = rCFG_FUSE3;
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sensor_trim &= MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN2_TRIMG_UMASK | MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN2_TRIMO_UMASK;
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sensor_trim >>= MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN2_TRIMG_SHIFT;
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return sensor_trim;
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#if SUB_PLATFORM_S8001
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case 3:
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sensor_trim = rCFG_FUSE3;
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sensor_trim &= MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN3_TRIMG_UMASK | MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN3_TRIMO_UMASK;
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sensor_trim >>= MINIPMGR_FUSE_CFG_FUSE3_THERMAL_SEN3_TRIMG_SHIFT;
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return sensor_trim;
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#endif
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default:
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panic("invalid thermal sensor %u", sensor_index);
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}
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}
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uint32_t chipid_get_fuse_revision(void)
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{
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uint32_t version = pmgr_binning_get_revision();
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if (version == PMGR_BINNING_NOTFOUND) {
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return 0;
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}
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return version;
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}
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uint32_t chipid_get_total_rails_leakage()
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{
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// FIXME
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return 0;
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}
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#if SUPPORT_FPGA
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#define FPGA_HAS_INT3 (FPGA_HAS_DISP | FPGA_HAS_MEDIA | FPGA_HAS_JPEG | FPGA_HAS_MSR | FPGA_HAS_VXD)
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uint32_t chipid_get_fpga_block_instantiation(void)
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{
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// Hardware blocks instantiated.
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uint32_t blocks = (rECID_FUSE3 >> 18) & 0xF;
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uint32_t mask = FPGA_HAS_ALWAYS;
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switch (blocks) {
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// INT2 := ACC + AF + AMC + SouthBridge + PCIE
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case 0x1:
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break;
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// INT2GFX := INT2 + GFX
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case 0x2:
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mask |= FPGA_HAS_GFX;
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break;
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// INT3 := INT2 + DISP + MEDIA + JPEG + MSR + VXD
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case 0x8:
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mask |= FPGA_HAS_INT3;
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break;
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// INT3GFX := INT3 + GFX
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case 0xA:
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mask |= (FPGA_HAS_INT3 | FPGA_HAS_GFX);
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break;
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default:
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panic("Unknown hardware block instantiation: 0x%x", blocks);
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}
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return mask;
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}
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#endif
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